# Solid Phase Recrystallization in Arsenic Ion-Implanted Silicon-On-Insulator by Microsecond UV Laser Annealing

Toshiyuki Tabata, Fabien Roze, Pablo Acosta Alba, Sebastien Halty, Pierre-Edouard Raynal, Imen Karmous, Sebastien Kerdiles, Fulvio Mazzamuto

► To cite this version:

Toshiyuki Tabata, Fabien Roze, Pablo Acosta Alba, Sebastien Halty, Pierre-Edouard Raynal, et al. Solid Phase Recrystallization in Arsenic Ion-Implanted Silicon-On-Insulator by Microsecond UV Laser Annealing. IEEE Journal of the Electron Devices Society, 2022, 10, pp.712-719. 10.1109/JEDS.2021.3131911. cea-04952113

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Distributed under a Creative Commons Attribution 4.0 International License
Received 17 September 2021; revised 3 November 2021 and 19 November 2021; accepted 27 November 2021. Date of publication 1 December 2021; date of current version 9 September 2022. The review of this article was arranged by Editor T. Narita.

Digital Object Identifier 10.1109/JEDS.2021.3131911

# Solid Phase Recrystallization in Arsenic Ion-Implanted Silicon-On-Insulator by Microsecond UV Laser Annealing

TOSHIYUKI TABATA¹ (Member, IEEE), FABIEN ROZÉ¹, PABLO ACOSTA ALBA¹,², SEBASTIEN HALTY¹, PIERRE-EDOUARD RAYNAL¹, IMEN KARMOUS¹, SÉBASTIEN KERDILÈS¹,², AND FULVIO MAZZAMUTO¹

1 Product Management & Application, Laser Systems & Solutions of Europe (LASSE), 92230 Gennevilliers, France
2 Université Grenoble Alpes, CEA-LETI, 38000 Grenoble, France

CORRESPONDING AUTHOR: T. TABATA (e-mail: toshiyuki.tabata@screen-lasse.com)

**ABSTRACT** UV laser annealing (UV-LA) enables surface-localized high-temperature thermal processing to form abrupt junctions in emerging monolithically stacked devices, where the applicable thermal budget is restricted. In this work, UV-LA is performed to regrow a silicon-on-insulator wafer partially amorphized by arsenic ion implantation as well as to activate the dopants. In a microsecond scale (~10⁻⁶ s to ~10⁻⁵ s) UV-LA process, monocrystalline solid phase recrystallization and dopant activation without junction deepening are evidenced, thus opening various applications in low thermal budget integration flows. However, some concerns remain. First, the surface morphology is degraded after the regrowth, possibly because of the non-perfect uniformity of the used laser beam and/or the formation of defects near the surface involving the excess dopants. Second, many of the dopants are inactive and seem to form deep levels in the Si band gap, suggesting a further optimization of the ion implantation condition to manage the initial crystal damage and the heating profile to better accommodate the dopants into the substitutional sites.

**INDEX TERMS** Laser annealing, solid phase recrystallization, silicon-on-insulator.

## I. INTRODUCTION

Nowadays, to further explore alternative scaling paths, monolithically stacked devices are emerging [1]–[8]. However, vertical stacking of multiple functional layers brings severe limitation of the thermal budget applicable to top-tier devices (e.g., 500 °C for 2 h [3], [6]), because bottom-tier ones must preserve their functions and performances during subsequent thermal processing steps. One of the most critical challenges is the formation of junctions on the top layers (e.g., source and drain [9] and their extension [8] for metal–oxide–semiconductor field-effect transistors (MOSFET), back-surface passivation for backside-illuminated complementary MOS imager sensors (BSI-CIS) [10], [11]). If conventional annealing processes such as high temperature furnace and rapid thermal processing (RTP) are not compatible, is generally used a lower temperature process called solid phase recrystallization (SPR), which can be performed at 500 to

600 °C in ion-implanted silicon (Si) [12], [13]. However, such low-temperature SPR undergoes significant reduction of the recrystallization rate [14]. To compensate it, the annealing time must be extended, but it may result in deactivation of the dopants. Ion implantation introduces a high concentration of interstitials (i.e., point defects) underneath the amorphized layer, and a thermal processing transforms them into dislocation loops (i.e., extended defects) [15]. These so-called end-of-range (EOR) defects newly release Si interstitials towards the neighboring surface and interface to reduce the free energy of system [16], [17]. Those Si interstitials may interact with substitutional dopants and lead to their deactivation [17].

UV laser annealing (UV-LA) can be advantageous for SPR because it allows to reach a high temperature while conserving the functionality of surrounding devices thanks to its short timescale and shallow irradiation absorption. In our
previous work, a UV-LA SPR process using a nanosecond
pulsed laser (its effective dwell time was ~10⁻⁷ s) has been
demonstrated on a 22-nm-thick silicon-on-insulator (SOI)
substrate partially amorphized by ion implantation [18], [19].
Then, a maximum crystallization rate of 1.8 nm per sin-
gle pulse irradiation was obtained, and it was necessary to
deposit thermally independent multiple laser pulses so that
the entire amorphized layer was recrystallized. Considering a
typical amorphization thickness in fully depleted SOI devices
(e.g., 5 to 7 nm for the extension [8], 13 to 20 nm for
the source and drain [1], [17]), this crystallization rate is
acceptable. However, other devices such as power IC may
require recrystallization of a much thicker layer (e.g., 150 nm
for a SOI-based lateral double-diffused MOSFET [20]), and
a more effective control of recrystallization, particularly
extending the dwell time of laser processing, may be manda-
tory to guarantee a reasonable productivity for high volume
manufacturing.

In this work, we present a UV-LA SPR process per-
formed with a microsecond-scale dwell time (i.e., ~10⁻⁶ s
to ~10⁻⁵ s) on a relatively thick SOI structure amor-
phized by arsenic (As) ion implantation for roughly a
half of its thickness. Sheet resistance, surface morphol-
ogy, atomic diffusion, As activation, and SOI microstructure
after UV-LA are discussed, evidencing a SPR comple-
tion among applied process conditions. The work initially
presented in the 20th International Workshop on Junction
Technology (IWJT2021) [21] has been re-edited, newly
involving (i) dwell time as a parameter representing the
UV-LA process, (ii) time-temperature profile simulation, and
(iii) additional experimental data.

II. EXPERIMENTAL PROCEDURE

A 70-nm-thick SOI wafer having a 145-nm-thick buried
oxide (BOX) was used as starting material. The wafer had
a (100) surface. Arsenic ion implantation was performed
at room temperature (RT) at 19 keV with a total dose of
4 × 10¹⁵ cm⁻². A 37-nm-thick amorphization was confirmed
by cross-sectional transmission electron microscopy (TEM).
The wafer was then submitted to UV-LA at RT in air,
varying both laser fluence and dwell time to control the
heat generated in the SOI structure. The laser wavelength
was between 300 and 400 nm. Sheet resistance (R<sub>sq</sub>) was
measured by a standard four-point probe. Surface morphol-
ogy was observed by atomic force microscopy (AFM).
Arsenic and oxygen (O) diffusion within the SOI layer
were measured by secondary ion mass spectroscopy (SIMS).
Crystallinity after UV-LA was discussed by cross-sectional
TEM. Active shallow donor and inactive defect-related deep
donor/acceptor concentrations were estimated by an analyti-
cal model developed for electrochemical capacitance voltage
profiling (ECVP) [22].

To extract the time-temperature profile in the ion-
implanted SOI structure, the UV-LA process was simulated
by means of a self-consistent time-harmonic solution of
the Maxwell equations, whose self-consistency derives from

<figure><img src="image_2.png" /><figcaption>FIGURE 1. Sheet resistance (R<sub>sq</sub>) plots at a given laser fluence as a function of the dwell time.</figcaption></figure>

dependence of an optical constant on temperatures and
phases (i.e., amorphous, crystal, and liquid). More details
of our simulation are explained elsewhere [23]. The dwell
time is defined at the full-width half-maximum of the profile
extracted for the amorphized SOI layer. It should be noted
that our simulation model does not consider yet the progress
of the SPR front, which changes the total reflectivity of the
stack (i.e., the absorption efficiency of the irradiated laser
light). For instance, the theoretically calculated reflectance
is 0.501 for the as-implanted stack, whereas 0.576 for the
fully recrystallized one. However, a rough estimation of the
applied UV-LA heating dynamics may be still obtained.

III. RESULTS AND DISCUSSION

First, based on the R<sub>sq</sub> value measured in the annealed SOI
layer, we identified a SPR condition. As shown in Fig. 1,
at a given laser fluence, increasing the dwell time led to a
continuous decrease of the R<sub>sq</sub> value. Interestingly, the R<sub>sq</sub>
value then became constant at around 10<sup>2</sup> ohm/sq. Here, we
suppose that the ion-implanted SOI layer is fully crystallized
by SPR, and that the R<sub>sq</sub> value does not further decrease until
the dopants start to diffuse due to melting of the SOI layer.
In the following discussion, the sample annealed for 20 µs
will be focused.

At this UV-LA condition, the time-temperature profile
in the amorphized SOI part was simulated. As shown in
Fig. 2, the maximum temperature reached during the process
(~1030 °C) does not exceed the melting point of amorphous
Si (1420 K [24]). Simply dividing the amorphized SOI layer
thickness (37 nm) by the applied dwell time (20 µs), the
overall SPR rate can be approximately estimated to be in a
range of ~10⁻³ m/s. This value is higher for almost two
orders of magnitude than the one reported in the literature
for the temperature close to ~1030 °C (~10⁻⁵ m/s) [25]. It
<figure><img src="image_3.png" /><figcaption>**FIGURE 2.** Time-temperature profile obtained by our simulation for the 20 µs UV-LA process. The dwell time is defined at the full-width half-maximum of the profile extracted for the amorphized SOI layer. The amorphous Si melting point is also shown.</figcaption></figure>

is indeed known that the doping enhances the SPR rate [26]. A thermal isolation of more than 100 °C in terms of the maximum temperature is also seen between the amorphized Si part and the underlying crystalline Si substrate. Inserting the 145-nm-thick silicon dioxide (SiO₂) layer helps it, because its thermal conductivity (~10⁰ W/m.K at 300 K [27]) is much lower than that of crystalline Si (~10² W/m.K at 300 K [27]). The degree of this thermal isolation should be tunable by the UV-LA parameters such as the wavelength of laser light as well as the frequency and duration of irradiation if the laser is pulsed.

Fig. 3 shows the As and O SIMS profiles before and after the 20 µs UV-LA. An important evidence of SPR is that there is no O diffusion at this condition (Fig. 3(b)). When melting of an ion-implanted Si happens, O incorporation is observed even in a nitrogen ambient for a much shorter dwell time (~10⁻⁷ s) [28]. On the other hand, at this possible SPR condition, a clear As segregation towards the surface was observed in the initially amorphized SOI layer (Fig. 3(a)). This may be induced by a “snowplow effect” in front of the moving amorphous/crystal (a/c) interface during SPR [29]. This characteristic As redistribution can be beneficial for lowering contact resistivity of transistors [30], [31].

Fig. 4 shows the dark-field cross-sectional TEM images taken before and after the 20 µs UV-LA. A partial amorphization of the SOI layer by the As ion implantation is clear and the amorphized thickness can be estimated to be about 37 nm (Fig. 4(a)). After the UV-LA process, the amorphized part was fully recrystallized into the single-crystalline state, showing no grain boundary in the presented cross-sectional TEM images (Fig. 4(b)). This observation finally confirms a SPR completion at this UV-LA condition. Here, some contrast non-uniformity was also observed in the whole SOI layer after its recrystallization, and this may imply presence of crystalline defects. It is possible that they were not

<figure><img src="image_4.png" /><figcaption>**FIGURE 3.** SIMS profiles of (a) As and (b) O atoms before and after the 20 µs UV-LA. The initial amorphous/crystal (a/c) interface in the SOI layer is also indicated by an arrow and a dotted line.</figcaption></figure>

visible in the presented TEM images because of their geometric relation to the applied analysis view [32] as well as of not high enough resolution. Then, the Si interstitials, whose source should be the ion implantation damage prior to UV-LA, probably do not contribute to formation of new crystalline defects during the SPR induced by the 20 µs UV-LA process. Considering the applied dwell time, the Si self-diffusion length calculated at the melting temperature of amorphous Si (1420 K [24]) in crystalline Si becomes negligible (~10⁻³ nm [33]). Therefore, it is supposed that the Si interstitials cannot travel and introduce any self-coalescence. As shown in Fig. 5, the weak-beam dark-field images indicate that many point defects were left prior to the UV-LA treatment underneath the initial amorphous/crystal
<figure><img src="image_5.png" /><figcaption>**FIGURE 4.** Dark-field cross-sectional TEM images taken (a) before (i.e., as-implanted) and (b) after the 20 µs UV-LA process.</figcaption></figure>

<figure><img src="image_6.png" /><figcaption>**FIGURE 5.** Weak-beam dark-field cross-sectional TEM images taken (a) before (i.e., as-implanted) and (b) after the 20 µs UV-LA process. The observation was performed with g/3g, g = 004, aiming at visualizing point defects (ion implantation damage) and their coalesced defects [32].</figcaption></figure>

(a/c) interface (Fig. 5(a)), but no white contrast implying the presence of either of remaining point defects or coalesced defects was observed after the 20 µs UV-LA SPR in the whole SOI layer (Fig. 5(b)). In the bottom-half of the SOI layer (i.e., non-amorphized), the contrast non-uniformity might be an artifact coming from our cross-sectional TEM lamella preparation, because it is present even near the SOI/BOX interface both before and after UV-LA SPR. On the other hand, in the upper-half of the SOI layer (i.e., amorphized then recrystallized by UV-LA SPR), the non-uniform

contrast seems becoming darker compared to the bottom part in the magnified cross-sectional TEM image, implying another contribution in addition to the possible TEM artifact. Indeed, the fast placement of atoms at the moving a/c interface during UV-LA SPR might leave disorders in the regrown crystal. Furthermore, the solid solubility limit of As in Si (~3 × 10²⁰ cm⁻³ at 1100 °C [34]) and the As concentration depth profile obtained by SIMS (>3 × 10²⁰ at 0 to 34 nm in depth (Fig. 3(a))) suggest formation of atomic clusters involving excess As atoms, and it might be enhanced towards the SOI surface along the As surface segregation. In fact, after the 20 µs UV-LA, the root-mean-square (RMS) value of surface roughness measured by AFM with a 30 µm × 30 µm scan was increased (~1.5 nm), compared to the as-implanted sample (~0.10 nm). This might be related to such atomic clusters preferably emerging near the surface. However, it should be noted that the laser beam used in this study was not perfectly optimized and still underwent a non-uniform shape. One may therefore speculate that a heat gradient is introduced in the SOI layer plane, resulting in a local variation of recrystallization rate. Anyhow, the possible formation of defects in the SOI layer during UV-LA SPR must be carefully investigated especially by means of high-resolution TEM to clearly capture their appearance.

It would be worth comparing our results with the others obtained by the LA treatment (regardless of UV or not) having different dwell times. In the case of a shorter dwell time (~10⁻⁷ s) from our previous works [18], [19], no obvious defect was pointed out at the cross-sectional TEM level after a SPR completion in a phosphorus (P) (4 keV, 1 × 10¹⁵ cm⁻²) [19] or As (9 keV, 1 × 10¹⁵ cm⁻²) [18] doped 22-nm-thick SOI layer. As the calculated Si self-diffusion length is further reduced in this shorter dwell time (~10⁻⁴ nm [33]), any self-coalescence of the Si interstitials (i.e., ion implantation damage) is not expected. In addition, since the as-implanted peak concentration of the dopants (~5 × 10²⁰ cm⁻³ for the applied P condition [35] and ~1 × 10²¹ cm⁻³ for the As one [36]) was lower than that of this work (~2 × 10²¹ cm⁻³), the possible atomic clustering would be greatly suppressed. A flat surface (~0.12 nm in RMS) was then maintained even after SPR [19]. Either of the much less atomic clustering near the surface or a better laser beam uniformity might have helped it. In the case of a longer dwell time (~10⁻³ to ~10⁻² s) [37], [38], the calculated Si self-diffusion length reaches ~10⁻² to ~10⁻¹ nm [33]. Considering the typical Si-Si bonding length in crystalline Si (~0.23 nm [39]), the Si interstitials may coalesce in this timescale. Indeed, presence and evolution of EOR defects were evidenced by weak-beam dark-field TEM [37], [38].

At the end, to investigate the As activation after the 20 µs UV-LA SPR, ECVP was performed. In a typical ECVP measurement, a doped semiconductor surface is in contact with an electrolyte and forms a Schottky junction. Applying a reverse polarization field to the junction, the doped semiconductor is depleted, and a space charge zone is formed. The measured capacitance (C) is written as the
<figure><img src="image_7.png" /><figcaption>FIGURE 6. Experimental $1/C^2$ ($C$ is the capacitance) versus the polarization field ($V$) curves (see the red solid lines) taken at different depths. The blue dotted and green dashed curves correspond to the fitting models (Fit 1 and Fit 2) with two different concentrations of shallow donors ($N_{sd1}$ and $N_{sd2}$, respectively). The other fitting parameters are $N_{dd}$ and $N_{da}$ for the concentration of deep donors and acceptors, $V_{dd}$ and $V_{da}$ for the polarization field at which the deep levels get ionized, then $\alpha_{dd}$ and $\alpha_{da}$ for the inverse of the potential variation inside the space charge zone [22].</figcaption></figure>

following [22]:

$$ \frac{1}{C^2} = \frac{2(V_{bi} - V)}{\varepsilon_r \varepsilon_0 q N^* A^2} \quad (1) $$

where $V_{bi}$ stands for the flat-band polarization field (called the built-in potential), $V$ for the applied polarization field, $\varepsilon_r$ and $\varepsilon_0$ for the relative and vacuum dielectric constants, $q$ for the electron charge, $N^*$ for the concentration of ionized impurities, and $A$ for the junction area. When any deep levels

exist, the $1/C^2$ versus $V$ plot shows a curvature. A fitting approach is therefore taken for all $1/C^2$ versus $V$ curves measured at different depths after cyclic etching, involving the active shallow donor ($N_{sd}$) and inactive defect-related deep donor/acceptor ($N_{dd}$ and $N_{da}$) concentrations into $N^*$. The detailed procedure is explained elsewhere [22]. As shown in Fig. 6, the curvature observed on the $1/C^2$ versus $V$ curve evolved with the measurement depth. A set of fitting parameters [22], which gave a good agreement with the
<figure><img src="image_8.png" /><figcaption>**FIGURE 7.** Depth profiles of the shallow donor (N<sub>sd</sub>) and deep donor/acceptor (N<sub>dd</sub> and N<sub>da</sub>) concentrations extracted by the 1/C<sup>2</sup> versus V curve fitting in ECVP for the 20 µs UV-LA SPR sample. The initial amorphous/crystal (a/c) interface in the SOI layer is also indicated by a dotted line.</figcaption></figure>

experimental data, could be found at each depth. Fig. 7 shows the depth profile of the N<sub>sd</sub>, N<sub>dd</sub>, and N<sub>da</sub> values extracted from the fitting. The theoretical R<sub>sq</sub> value can be calculated from the N<sub>sd</sub> profile, and it is 367 ohm/sq. This value is in fact much greater than the experimentally measured one (101 ohm/sq). It implies the still high inaccuracy of our fitting parameter selection, and the real N<sub>sd</sub> level might become much higher (1 to 4 × 10<sup>20</sup> cm<sup>-3</sup> as a rough estimation). To confirm it, a complementary analysis (e.g., differential Hall effect measurement [40]) is necessary. Anyhow, it does not affect the current discussion about the formation of deep levels after the UV-LA SPR.

First, it is suggested that, considering a known range of the equilibrium solid solubility limit of As in Si (~1 × 10<sup>20</sup> to ~3 × 10<sup>20</sup> cm<sup>-3</sup> at 700 to 1100 °C [34]), many substitutional As atoms are deactivated and form deep-level defects in the regrown SOI part. As already discussed, the Si interstitials hardly travel during the UV-LA SPR. Therefore, another deactivation pathway needs to be considered. In fact, a high As dose may make it happen [41]. To begin, an As<sub>n</sub> cluster is formed among substitutional As atoms. Coupling of this cluster with a vacancy (V<sub>Si</sub>) happens (i.e., formation of As<sub>n</sub>V), emitting an interstitial Si (I<sub>Si</sub>), especially for n = 3, 4. This emitted I<sub>Si</sub> replaces a nearest substitutional As atom (i.e., release of an interstitial As (I<sub>As</sub>)). The released I<sub>As</sub> makes As<sub>n</sub>V grow (i.e., formation of As<sub>n+1</sub>V). This process self-continues with time and stops with As<sub>4</sub>V. Indeed, As<sub>n</sub>V is supposed to introduce deep donor/acceptor levels in the Si bandgap [42], [43]. The kinetic Monte Carlo simulation tells that considerable As<sub>n</sub>V formation may happen in the applied dwell time scale [44]. It should be noted that there

is a discrepancy between the As SIMS and N<sub>sd</sub> + N<sub>dd</sub> + N<sub>da</sub> profiles. This might represent either the mean number of charges trapped by the As<sub>n</sub>V defects or another As-rich defect (e.g., precipitation of As atoms although there is no direct evidence of a phase change for instance from As solid solution in the Si lattice to crystalline As).

Second, the full As activation is observed in the non-amorphized SOI part. Nevertheless, some deep donors/acceptors still exist. Most of them are probably the point defects, which originally come from the ion implantation damage and are not fully annihilated during the UV-LA SPR. Indeed, V<sub>Si</sub> is supposed to form deep-level defects as well [42].

#### IV. CONCLUSION

We have investigated the microsecond UV-LA induced SPR on a partially amorphized 70-nm-thick SOI substrate. The results have evidenced a single-crystal regrowth of the amorphized region by SPR at the presented cross-sectional TEM level. However, there remains some concerns to address in a future work.

First, the surface morphology was degraded during the applied UV-LA SPR. So far, two root causes are suspected: (i) a possible laser beam non-uniformity and (ii) the atomic clustering involving excess As atoms near the surface where the As segregation was observed by SIMS. Second, the excess As concentration is also supposed to trigger the deactivation of substitutional As atoms. Therefore, the initial As dose must be carefully optimized. In the case of a zero-second rapid thermal annealing followed by fast cooling (250 °C/s), the maximum carrier (i.e., substitutional As) concentration monotonically increases with increase of the annealing temperature [45]. This suggests maintaining the annealing temperature close to the upper limit (1420 K) during SPR. To further improve the As activation, introducing excess Si interstitials by pre-amorphization implantation (PAI) may work [44] because it annihilates the vacancies which are involved in the As deactivation pathway. However, as it may compete with substitutional As replacement [41], an optimal condition must be carefully examined. Fluorine co-doping may also work for gettering the vacancies [44]. Third, although the EOR defects seem hardly formed due to the negligible Si self-diffusion length, some deep levels were electrically still measured in the EOR region. This suggests suppressing the ion implantation damage to further improve the crystallinity of the EOR region after the UV-LA SPR. Cryogenic ion implantation may help it [15], [46], [47].

#### ACKNOWLEDGMENT

The work covered by LASSE in this paper was supported by the IT2 project. This project has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 875999. The JU receives support from the European Union's Horizon 2020 research and innovation programme and Netherlands, Belgium, Germany, France, Austria, Hungary, United Kingdom, Romania, Israel.
REFERENCES

[1] C. Fenouillet-Beranger et al., "New insights on bottom layer thermal stability and laser annealing promises for high performance 3D VLSI," in *IEDM Tech. Dig.*, Dec. 2014, pp. 642–645, doi: 10.1109/IEDM.2014.7047121.

[2] A. Mallik et al., "The impact of sequential-3D integration on semiconductor scaling roadmap," in *IEDM Tech. Dig.*, Dec. 2017, pp. 717–720, doi: 10.1109/IEDM.2017.8268483.

[3] L. Brunet et al., "Breakthroughs in 3D sequential technology," in *IEDM Tech. Dig.*, Dec. 2018, pp. 153–156, doi: 10.1109/IEDM.2018.8614653.

[4] A. Vandooren et al., "First demonstration of 3D stacked fins at a 45nm fin pitch and 110nm gate pitch technology on 300nm wafers," in *IEDM Tech. Dig.*, Dec. 2018, pp. 149–152, doi: 10.1109/IEDM.2018.8614654.

[5] P.-Y. Hsieh et al., "Monolithic 3D BEOL FinFET switch arrays using location-controlled-grain technique in voltage regulator with better FOM than 2D regulators," in *IEDM Tech. Dig.*, Dec. 2019, pp. 46–49, doi: 10.1109/IEDM19573.2019.8993441.

[6] C. Cavalcante et al., "28nm FDSOI CMOS technology (FEOL and BEOL) thermal stability for 3D sequential integration: Yield and reliability analysis," in *Proc. Symp. VLSI Technol.*, Jun. 2020, pp. 1–2, doi: 10.1109/VLSITechnology18217.2020.9265075.

[7] C. Fenouillet-Beranger et al., "First demonstration of low temperature (≤500°C) CMOS devices featuring functional RO and SRAM bitcells toward 3D VLSI integration," in *Proc. Symp. VLSI Technol.*, Jun. 2020, pp. 1–2, doi: 10.1109/VLSITechnology18217.2020.9265092.

[8] A. Vandooren et al., "3D sequential low temperature top tier devices using dopant activation with excimer laser anneal and strained silicon as performance boosters," in *Proc. Symp. VLSI Technol.*, Jun. 2020, pp. 1–2, doi: 10.1109/VLSITechnology18217.2020.9265026.

[9] C. Fenouillet-Beranger et al., "Annealing techniques for low temperature junctions design in a 3D VLSI integration," in *Proc. Int. Conf. Solid State Devices Mater. (SSDM)*, Sep. 2015, pp. 1098–1099.

[10] P. Coudrain et al., "Setting up 3D sequential integration for back-illuminated CMOS image sensors with highly miniaturized pixels with low temperature fully depleted SOI transistors," in *IEDM Tech. Dig.*, Dec. 2008, pp. 271–274, doi: 10.1109/IEDM.2008.4796670.

[11] Z. A. F. Ali-Guerry et al., "Non-melt laser thermal annealing of shallow boron implantation for back surface passivation of backside-illuminated CMOS image sensors," *MRS Online Proc. Library*, vol. 1321, p. 614, Dec. 2011, doi: 10.1557/opl.2011.808.

[12] S. G. Tavakoli, S. Baek, and H. Hwang, "Effect of germanium pre-amorphization on solid-phase epitaxial regrowth of antimony and arsenic ion-implanted silicon," *Mater. Sci. Eng. B*, vols. 114–115, pp. 376–380, Dec. 2004, doi: 10.1016/j.mseb.2004.07.067.

[13] K. L. Saenger et al., "A study of trench-edge defect formation in (001) and (011) silicon recrystallized by solid phase epitaxy," *J. Appl. Phys.*, vol. 101, Jan. 2007, Art. no. 024908, doi: 10.1063/1.2426924.

[14] B. C. Johnson and J. C. McCallum, "Dopant-enhanced solid-phase epitaxy in buried amorphous silicon layers," *Phys. Rev. B, Condens. Matter*, vol. 76, Jul. 2007, Art. no. 045216, doi: 10.1103/PhysRevB.76.045216.

[15] K. S. Jones, S. Prussin, and E. R. Weber, "A systematic analysis of defects in ion-implanted silicon," *Appl. Phys. A, Solids Surf.*, vol. 45, pp. 1–34, Jan. 1988, doi: 10.1007/BF00618760.

[16] E. M. Bazizi et al., "Modeling of the effect of the buried Si-SiO$_2$ interface on transient enhanced boron diffusion in silicon on insulator," *J. Appl. Phys.*, vol. 107, Apr. 2010, Art. no. 074503, doi: 10.1063/1.3369160.

[17] B. Sklenard et al., "Low temperature junction formation by solid phase epitaxy on thin film devices: Atomistic modeling and experimental achievements," *Proc. Int. Workshop Junct. Technol. (IWJT)*, May 2014, pp. 1–6, doi: 10.1109/IWJT.2014.6842024.

[18] P. A. Alba, J. Aubin, S. Perrot, F. Mazzamuto, and S. Kerdilès, "Solid phase recrystallization induced by nanosecond pulsed laser," *Proc. Int. Conf. Solid State Devices Mater. (SSDM)*, Sep. 2019, pp. 599–600.

[19] P. A. Alba, J. Aubin, S. Perrot, F. Mazzamuto, A. Grenier, and S. Kerdilès, "Solid phase recrystallization induced by multi-pulse nanosecond laser annealing," *Appl. Surface Sci. Adv.*, vol. 3, Mar. 2021, Art. no. 100053, doi: 10.1016/j.apsadv.2020.100053.

[20] W. Zhang et al., "Novel superjunction LDMOS (>950 V) with a thin layer SOI," *IEEE Electron Device Lett.*, vol. 38, no. 11, pp. 1555–1558, Nov. 2017, doi: 10.1109/LED.2017.2751571.

[21] T. Tabata et al., "Solid phase recrystallization and dopant activation in arsenic ion-implanted silicon-on-insulator by UV laser annealing," in *Proc. Int. Workshop Junct. Technol. (IWJT)*, Jun. 2021, pp. 1–5.

[22] B. Sermage, T. Tabata, J. Ren, G. Priante, and Y. Gao, "Interpretation of the $1/C^2$ curvature and discontinuity in electrochemical capacitance voltage profiling of heavily Ga implanted sige followed by melt laser annealing," *ECS J. Solid State Sci. Technol.*, vol. 9, Dec. 2020, Art. no. 123008, doi: 10.1149/2162-8777/abcd09.

[23] S. F. Lombardo et al., "Theoretical study of the laser annealing process 286 in FinFET structures," *Appl. Surface Sci.*, vols. 467–468, pp. 666–672, Feb. 2019, doi: 10.1016/j.apsusc.2018.10.155.

[24] E. P. Donovan, F. Spaepen, D. Turnbull, J. M. Poate, and D. C. Jacobson, "Heat of crystallization and melting point of amorphous silicon," *Appl. Phys. Lett.*, vol. 42, Apr. 1983, pp. 698–700, doi: 10.1063/1.94077.

[25] W. Yang, J. Mathews, and J. S. Williams, "Hyperdoping of Si by ion implantation and pulsed laser melting," *Mater. Sci. Semicond. Process.*, vol. 62, May 2017, pp. 103–114, doi: 10.1016/j.mssp.2016.11.005.

[26] B. C. Johnson, T. Ohshima, and J. C. McCallum, "Dopant effects on solid phase epitaxy in silicon and germanium," *J. Appl. Phys.*, vol. 111, Feb. 2012, Art. no. 034906, doi: 10.1063/1.3682532.

[27] A. La Magna, P. Alippi, V. Privitera, G. Fortunato, M. Camalleri, and B. Svensson, "A phase-field approach to the simulation of the excimer laser annealing process in Si," *J. Appl. Phys.*, vol. 95, pp. 4806–4814, May 2004, doi: 10.1063/1.1690861.

[28] T. Tabata, P.-E. Raynal, K. Huet, and J.-L. Everaert, "Segregation and activation of Sb implanted in Si by UV nanosecond-laser-annealed non-equilibrium solidification," *J. Appl. Phys.*, vol. 127, Apr. 2020, Art. no. 135701, doi: 10.1063/5.0005176.

[29] M. J. P. Hopstaken, Y. Tamming, M. A. Verheijen, R. Duffy, V. C. Venezia, and A. Heringa, "Effects of crystalline regrowth on dopant profiles in preamorphized silicon," *Appl. Surf. Sci.*, vols. 231–232, pp. 688–692, May 2004, doi: 10.1016/j.apsusc.2004.03.184.

[30] H. Niimi et al., "Sub-$10^{-9}$ Ω-cm$^2$ n-type contact resistivity for FinFET technology," *IEEE Electron Device Lett.*, vol. 37, no. 11, pp. 1371–1374, Nov. 2016, doi: 10.1109/LED.2016.2610480.

[31] J.-L. Everaert et al., "Sub-$10^{-9}$ Ω-cm$^2$ contact resistivity on p-SiGe achieved by Ga doping and nanosecond laser activation," in *Proc. Symp. VLSI Technol.*, Jun. 2017, pp. 214–215, doi: 10.23919/VLSIT.2017.7998176.

[32] Y. Qiu et al., "Extended defects formation in nanosecond laser-annealed ion implanted silicon," *Nano Lett.*, vol. 14, pp. 1769–1775, Mar. 2014, doi: 10.1021/nl4042438.

[33] J. M. Fairfield and B. J. Masters, "Self-diffusion in intrinsic and extrinsic silicon," *J. Appl. Phys.*, vol. 38, pp. 3148–3154, Jul. 1967, doi: 10.1063/1.1710079.

[34] A. Lietoila, J. F. Gibbons, and T. W. Sigmon, "The solid solubility and thermal behavior of metastable concentrations of As in Si," *Appl. Phys. Lett.*, vol. 36, pp. 765–768, Feb. 1980, doi: 10.1063/1.91650.

[35] P. A. Alba et al., "Nanosecond laser annealing for phosphorous activation in ultra-thin implanted silicon-on-insulator substrates," in *Proc. Int. Conf. Ion Implantation Technol. (IIT)*, Sep. 2016, pp. 1–4, doi: 10.1109/IIT.2016.7882896.

[36] S. Kerdilès et al., "Dopant activation and crystal recovery in arsenic-implanted ultra-thin silicon-on-insulator structures using 308nm nanosecond laser annealing," in *Proc. Int. Workshop Junct. Technol. (IWJT)*, May 2016, pp. 1–4, doi: 10.1109/IWJT.2016.7486677.

[37] J. A. Sharp et al., "Deactivation of ultrashallow boron implants in preamorphized silicon after nonmelt laser annealing with multiple scans," *Appl. Phys. Lett.*, vol. 89, Nov. 2006, Art. no. 192105, doi: 10.1063/1.2385215.

[38] J. A. Sharp et al., "Surface proximity and boron concentration effects on end-of-range defect formation during nonmelt laser annealing," *Appl. Phys. Lett.*, vol. 92, Feb. 2008, Art. no. 082109, doi: 10.1063/1.2885091.

[39] M. Kaftory, M. Kapon, and M. Botoshansky, "The structural chemistry of organosilicon compounds," in *The Chemistry of Organic Silicon Compounds*, vol. 2, Chichester, U.K.: Wiley, 1998, ch. 5, pp. 181–265, doi: 10.1002/0470857250.ch5.
[40] A. Joshi and B. M. Basol, "Study of dopant activation in Si employing differential hall effect metrology (DHEM)," in *Proc. Int. Workshop Junct. Technol. (IWJT)*, Jun. 2021, pp. 52–57.

[41] R. Pinacho, M. Jaraiz, P. Castrillo, I. Martin-Bragado, J. E. Rubio, and J. Barbolla, "Modeling arsenic deactivation through arsenic-vacancy clusters using an atomistic kinetic Monte Carlo approach," *Appl. Phys. Lett.*, vol. 86, Jun. 2005, Art. no. 252103, doi: 10.1063/1.1948533.

[42] D. C. Mueller, E. Alonso, and W. Fichtner, "Arsenic deactivation in Si: Electronic structure and charge states of vacancy-impurity clusters," *Phys. Rev. B, Condens. Matter*, vol. 68, Jul. 2003, Art. no. 045208, doi: 10.1103/PhysRevB.68.045208.

[43] C. Janke, R. Jones, S. Öberg, and P. R. Briddon, "Ab initio studies of arsenic and boron related defects in silicon mesa diodes," *Appl. Phys. Lett.*, vol. 90, Apr. 2007, Art. no. 152103, doi: 10.1063/1.2721362.

[44] T. Noda et al., "Analysis of As, P diffusion and defect evolution during sub-millisecond non-melt laser annealing based on an atomistic kinetic Monte Carlo approach," in *IEDM Tech. Dig.*, Dec. 2007, pp. 955–958, doi: 10.1109/IEDM.2007.4419111.

[45] A. N. Larsen, B. Christensen, and S. Y. Shiryaev, "Deactivation of electrically active arsenic in silicon during cooling-down from elevated temperatures," *J. Appl. Phys.*, vol. 71, pp. 4854–4858, Jun. 1992, doi: 10.1063/1.350629.

[46] F. A. Khaja, B. Colombeau, T. Thanigaivelan, D. Ramappa, and T. Henry, "Physical understanding of cryogenic implant benefits for electrical junction stability," *Appl. Phys. Lett.*, vol. 100, Mar. 2012, Art. no. 112102, doi: 10.1063/1.3694275.

[47] Y. Wu et al., "Sub-$10^{-9}$ Ω-cm² specific contact resistivity on P-type Ge and GeSn: in-situ Ga doping with Ga Ion implantation at 300 °C, 25 °C, and -100 °C," in *IEDM Tech. Dig.*, Dec. 2018, pp. 823–826, doi: 10.1109/IEDM.2018.8614619.