# Speculative High-Level Synthesis of RISC-V Processors

Dylan Leothaud, Jean-Michel Gorius, Steven Derrien, Simon Rokicki

► To cite this version:

Dylan Leothaud, Jean-Michel Gorius, Steven Derrien, Simon Rokicki. Speculative High-Level Synthesis of RISC-V Processors. RISC-V Summit Europe 2024, Jun 2024, Munich, Germany., 2024. hal-04615846

HAL Id: hal-04615846

https://hal.science/hal-04615846

Submitted on 18 Jun 2024

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<figure><img src="image_1.png" /></figure>

Distributed under a Creative Commons Attribution 4.0 International License
# Speculative High-Level Synthesis of RISC-V Processors

Dylan Leothaud, Jean-Michel Gorius, Steven Derrien, Simon Rokicki

► To cite this version:

Dylan Leothaud, Jean-Michel Gorius, Steven Derrien, Simon Rokicki. Speculative High-Level Synthesis of RISC-V Processors. RISC-V Summit Europe 2024, Jun 2024, Munich, Germany., 2024. hal-04615846

HAL Id: hal-04615846

https://hal.science/hal-04615846v1

Submitted on 18 Jun 2024

HAL is a multi-disciplinary open access
archive for the deposit and dissemination of sci-
entific research documents, whether they are pub-
lished or not. The documents may come from
teaching and research institutions in France or
abroad, or from public or private research centers.

L'archive ouverte pluridisciplinaire HAL, est
destinée au dépôt et à la diffusion de documents
scientifiques de niveau recherche, publiés ou non,
émanant des établissements d'enseignement et de
recherche français ou étrangers, des laboratoires
publics ou privés.

<figure><img src="image_1.png" /></figure>

Distributed under a Creative Commons Attribution 4.0 International License
# Speculative High-Level Synthesis of RISC-V Processors

Dylan Leothaud, Jean-Michel Gorius, Steven Derrien, Simon Rokicki

<figure><img src="image_2.png" /></figure>

UMR

IRISA

Univ Rennes, Inria, CNRS, IRISA

`{dylan.leothaud, jean-michel.gorius, steven.derrien, simon.rokicki}@irisa.fr`

<figure><img src="image_3.png" /></figure>

Université
de Rennes

<figure><img src="image_4.png" /></figure>

## Designing a RISC-V CPU should be as simple as writing an Instruction Set Simulator

### Introduction

**Context:** Increasing need for customizable architectures for embedded applications.

**Problem:** Micro-architectural design is tedious and error-prone, how do we make such customizations available to everyone?

**Our approach:** Leverage High-Level Synthesis to synthesize micro-architectures from a single instruction set simulator in C.

<figure><img src="image_5.png" /><figcaption>Static loop-pipelined schedule</figcaption></figure>

<figure><img src="image_6.png" /></figure>

<figure><img src="image_7.png" /></figure>

### Key takeaway

High-Level Synthesis (HLS) tools allow automatic generation of hardware from C programs

## From ISS to RISC-V Processors

<figure><img src="image_8.png" /></figure>

### SpecHLS [1]

* Speculative HLS toolchain
* Backend-agnostic automatic transformation

<figure><img src="image_9.png" /><figcaption>Speculative pipelining</figcaption></figure>

4

<figure><img src="image_10.png" /></figure>

GeCoS
Generic Compiler Suite

<figure><img src="image_11.png" /></figure>

### Key takeaway

Synthesizing RISC-V CPUs is possible [2], but time-consuming!

## Efficient Design Space Exploration

### Key takeaway

Speculation comes at the cost of design space explosion

4 × 10²⁸ configurations for a simple RISC-V CPU!

<figure><img src="image_12.png" /></figure>

<table><thead><tr><th>Scenario</th><th>γ<sub>1</sub></th><th>γ<sub>2</sub></th><th>γ<sub>3</sub></th><th>γ<sub>4</sub></th><th>CP (ns)</th><th>Prob.</th></tr></thead><tbody><tr><td>configuration 1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>2 ns</td><td>0.34</td></tr><tr><td>configuration 2</td><td>0</td><td>0</td><td>1</td><td>1</td><td>2 ns</td><td>0.21</td></tr><tr><td>configuration 3</td><td>0</td><td>0</td><td>0</td><td>1</td><td>8 ns</td><td>0.17</td></tr><tr><td>configuration 4</td><td>1</td><td>1</td><td>0</td><td>0</td><td>27 ns</td><td>0.10</td></tr><tr><td>configuration 5</td><td>0</td><td>1</td><td>0</td><td>0</td><td>13 ns</td><td>0.08</td></tr><tr><td>configuration 6</td><td>1</td><td>0</td><td>0</td><td>1</td><td>27 ns</td><td>0.04</td></tr><tr><td>static</td><td>-</td><td>-</td><td>-</td><td>-</td><td>27 ns</td><td>1</td></tr><tr><td>speculative 1</td><td>0</td><td>-</td><td>0</td><td>1</td><td>8 ns</td><td>0.17</td></tr><tr><td>speculative 2</td><td>-</td><td>0</td><td>1</td><td>-</td><td>2 ns</td><td>0.58</td></tr></tbody></table>

### Exploring speculation opportunities

* Proposed algorithm based on Branch-and-Bound approach [3]
* Design space exploration leveraging *intertwined speculations* to obtain the best designs

### Pruning configurations

* Pruning based on probability
* Heuristics based on achievable II
* Select the smallest configuration

<figure><img src="image_13.png" /></figure>

## Conclusion

* We need speculation to synthesize processor cores [2, 4].
* Processor design from an ISS using **speculative pipelining** enables fast iteration times and **intuitive** design exploration.

## References

[1] Gorius, J.-M., Rokicki, S., and Derrien, S. (2022). *SpecHLS: Speculative Accelerator Design using High-Level Synthesis*. IEEE MICRO.
[2] Gorius, J.-M., Rokicki, S., and Derrien, S. (2022). *Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis*. ICFPT’22.
[3] Leothaud, D., Gorius, J.-M., Rokicki, S., and Derrien, S. (2024). *Efficient Design Space Exploration for Dynamic and Speculative High-Level Synthesis*. FPL’24.
[4] Derrien, S., Marty, T., Rokicki, S., and Yuki, T. (2020). *Toward speculative loop pipelining for high-level synthesis*. TCAD.
# Speculative High-Level Synthesis of RISC-V Processors

Dylan Leothaud, Jean-Michel Gorius, Steven Derrien, Simon Rokicki

<figure><img src="image_2.png" /></figure>

UMR

IRISA

Univ Rennes, Inria, CNRS, IRISA

`{dylan.leothaud, jean-michel.gorius, steven.derrien, simon.rokicki}@irisa.fr`

<figure><img src="image_3.png" /></figure>

Université
de Rennes

<figure><img src="image_4.png" /></figure>

## Designing a RISC-V CPU should be as simple as writing an Instruction Set Simulator

### Introduction

**Context:** Increasing need for customizable architectures for embedded applications.

**Problem:** Micro-architectural design is tedious and error-prone, how do we make such customizations available to everyone?

**Our approach:** Leverage High-Level Synthesis to synthesize micro-architectures from a single instruction set simulator in C.

<figure><img src="image_5.png" /></figure>

### Key takeaway

High-Level Synthesis (HLS) tools allow automatic generation of hardware from C programs

## From ISS to RISC-V Processors

<figure><img src="image_6.png" /></figure>

## Efficient Design Space Exploration

<figure><img src="image_7.png" /></figure>

### Key takeaway

Speculation comes at the cost of design space explosion

4 × 10²⁸ configurations for a simple RISC-V CPU!

### Exploring speculation opportunities

* Proposed algorithm based on Branch-and-Bound approach [3]

* Design space exploration leveraging *intertwined speculations* to obtain the best designs

<figure><img src="image_8.png" /></figure>

GeCoS
Generic Compiler Suite

### Pruning configurations

* Pruning based on probability

* Heuristics based on achievable II

* Select the smallest configuration

<figure><img src="image_9.png" /><figcaption>Speculative pipelining</figcaption></figure>

4

### Key takeaway

Synthesizing RISC-V CPUs is possible [2], but time-consuming!

## Conclusion

* We need speculation to synthesize processor cores [2, 4].

* Processor design from an ISS using **speculative pipelining** enables fast iteration times and **intuitive** design exploration.

## References

[1] Gorius, J.-M., Rokicki, S., and Derrien, S. (2022). *SpecHLS: Speculative Accelerator Design using High-Level Synthesis*. IEEE MICRO.
[2] Gorius, J.-M., Rokicki, S., and Derrien, S. (2022). *Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis*. ICFPT'22.
[3] Leothaud, D., Gorius, J.-M., Rokicki, S., and Derrien, S. (2024). *Efficient Design Space Exploration for Dynamic and Speculative High-Level Synthesis*. FPL'24.
[4] Derrien, S., Marty, T., Rokicki, S., and Yuki, T. (2020). *Toward speculative loop pipelining for high-level synthesis*. TCAD.