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# Impact of Multi-Bias on the Performance of 150 nm GaN HEMT for High-Frequency Applications

Mohammad Abdul Alim, Christophe Gaquière

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Mohammad Abdul Alim, Christophe Gaquière. Impact of Multi-Bias on the Performance of 150 nm GaN HEMT for High-Frequency Applications. Micromachines, 2025, 16, 10.3390/mi16080932. hal-05234668

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Article

# Impact of Multi-Bias on the Performance of 150 nm GaN HEMT for High-Frequency Applications

Mohammad Abdul Alim<sup>1,*</sup> and Christophe Gaquiere<sup>2</sup>

## Abstract

This study examines the performance of a GaN HEMT with a 150 nm gate length, fabricated on silicon carbide, across various operational modes, including direct current (DC), radio frequency (RF), and small-signal parameters. The evaluation of DC, RF, and small-signal performance under diverse bias conditions remains a relatively unexplored area of study for this specific technology. The DC characteristics revealed relatively little $I_{ds}$ at zero gate and drain voltages, and the current grew as $V_{gs}$ increased. Essential measurements include $I_{dss}$ at 109 mA and $I_{dssm}$ at 26 mA, while the peak $g_m$ was 62 mS. Because transconductance is sensitive to variations in $V_{gs}$ and $V_{ds}$, it shows "Vth roll-off," where Vth decreases as $V_{ds}$ increases. The transfer characteristics corroborated this trend, illustrating the impact of drain-induced barrier lowering (DIBL) on threshold voltage (Vth) values, which spanned from -5.06 V to -5.71 V across varying drain-source voltages ($V_{ds}$). The equivalent-circuit technique revealed substantial non-linear behaviors in capacitances such as $C_{gs}$ and $C_{gd}$ concerning $V_{gs}$ and $V_{ds}$, while also identifying extrinsic factors including parasitic capacitances and resistances. Series resistances ($R_{gs}$ and $R_{gd}$) decreased as $V_{gs}$ increased, thereby enhancing device conductivity. As $V_{gs}$ approached neutrality, particularly at elevated $V_{ds}$ levels, the intrinsic transconductance ($g_{m0}$) and time constants ($\tau_{gm}$, $\tau_{gs}$, and $\tau_{gd}$) exhibited enhanced performance. $f_t$ and $f_{max}$, which are essential for high-frequency applications, rose with decreasing $V_{gs}$ and increasing $V_{ds}$. When $V_{gs}$ approached -3 V, the $S_{21}$ and $Y_{21}$ readings demonstrated improved signal transmission, with peak $S_{21}$ values of approximately 11.2 dB. The stability factor (K), which increased with $V_{ds}$, highlighted the device's operational limits. The robust correlation between simulation and experimental data validated the equivalent-circuit model, which is essential for enhancing design and creating RF circuits. Further examination of bias conditions would enhance understanding of the device's performance.

**Keywords:** GaN HEMT; 150 nm gate length; multi-bias characterization; small-signal analysis; on-wafer measurements

## 1. Introduction

The beneficial properties of GaN HEMTs have made them a focal point in the semiconductor industry. Due to their high breakdown voltage, high electron mobility, and high thermal conductivity, they are suitable for high-power and high-frequency applications [1–4]. Compared to conventional silicon and GaAs devices, GaN HEMTs that utilize silicon carbide (SiC) substrates offer even greater benefits. SiC's exceptional

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updates

Academic Editors: Joseph Bernstein
and Asaf Albo

Received: 4 July 2025

Revised: 12 August 2025

Accepted: 12 August 2025

Published: 13 August 2025

**Citation:** Alim, M.A.; Gaquiere, C. Impact of Multi-Bias on the Performance of 150 nm GaN HEMT for High-Frequency Applications.

Micromachines **2025**, *16*, 932. https://doi.org/10.3390/mi16080932

**Copyright:** © 2025 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).

<footnote n="1">¹ Electrical and Electronic Engineering, University of Chittagong, Chittagong 4331, Bangladesh</footnote>

<footnote n="2">² Institute of Electronic, Microelectronic and Nanotechnology (IEMN), The University of Lille, F-59000 Lille, France; christophe.gaquiere@iemn.univ-lille1.fr</footnote>

<footnote>* Correspondence: mohammadabdulalim@cu.ac.bd; Tel.: +880-1305575390</footnote>
thermal conductivity enhances the efficiency and power density of various systems, including radar systems and RF amplifiers, by effectively dissipating heat during high-power operation [5–10]. Despite numerous studies examining the DC and RF performance characteristics of GaN HEMTs [11–24], there is limited information available regarding their behavior under varying bias conditions, especially concerning small-signal and multi-bias performance [25–30]. To design and analyze GaN RF circuits, it is essential to investigate how multi-bias conditions influence crucial parameters, including transconductance ($g_m$), output resistance ($R_{ds}$), and intrinsic capacitances. Existing literature has primarily focused on basic DC characteristics under static bias conditions, with earlier work addressing only the influence of bias on switching ability and efficiency. Prior research has focused on the effects of passive and active parasitics, leaving the dynamic impact of bias on RF and small-signal parameters less studied. For example, some research has examined the effects of parasitic components on frequency response and stability [31–33], while other research has focused on bias-related noise performance [14,34,35]. However, there has not been a thorough examination of DC, RF, and small-signal characteristics under various bias conditions. The objective of this research is to investigate the behavior of a GaN HEMT 150 with a 150 nm gate length, built on a SiC substrate, and to highlight the impact of bias conditions on equivalent circuit components and high-frequency performance.

Key DC results that highlight the device's performance capabilities include $I_{dss}$, which was measured at 109 mA, and $I_{dssm}$, which was measured at 26 mA. The device's sensitivity to these biasing parameters is further illustrated by the transconductance ($g_m$), which attained 62 mS at $V_{gs} = -4.8$ and $V_{ds} = 10$ V. Due to short-channel effects, such as DIBL, the threshold voltage (Vth) decreased as $V_{ds}$ increased, with values ranging from -5.06 V to -5.71 V. At higher $V_{ds}$, the dark current ($I_{dso}$) increased exponentially, indicating an increase in carrier generation. An equivalent circuit analysis shows how extrinsic elements, such as parasitic resistances and capacitances, affect performance. Biasing ranged from $V_{gs} = -6.0$ V to -3.0 V and from $V_{ds} = 3$ V to 15 V, with a focus on frequencies between 45 MHz and 50 GHz. The extraction process for device parameters starts by identifying extrinsic components to determine intrinsic parameters. $C_{gs}$ increased with both $V_{ds}$ and $V_{gs}$, while $C_{gd}$ decreased. Simultaneously, $C_{ds}$ rose as $V_{gs}$ neared pinch-off. Owing to non-quasi-static phenomena, the series resistances $R_{gs}$ and $R_{gd}$ exhibited charging delays, whereas $R_{ds}$ increased with $V_{ds}$, necessitating a balance for optimal design. At $V_{ds} = 11$ V and $V_{gs} = -4.8$ V, the intrinsic transconductance $g_{mo}$ reached a maximum of 71 mS. It escalates with $V_{gs}$. Transistor inertia at elevated frequencies is indicated by intrinsic $g_{mo}$ and time constants ($\tau_{gm}$, $\tau_{gs}$, and $\tau_{gd}$), with $g_{mo}$ reaching its maximum at reduced $V_{gs}$ as $V_{ds}$ increased. Increased $V_{ds}$ and decreased negative $V_{gs}$ yielded enhanced frequency performance metrics, with $f_T$ ranging from $1.18 \times 10^8$ Hz to $5.16 \times 10^{10}$ Hz and $f_{max}$ from $5.23 \times 10^8$ Hz to $9.96 \times 10^{10}$ Hz. The $S_{21}$ parameter peaked at 11.2 dB with $V_{gs} = -4.8$ V and $V_{ds}$ between 11 and 15 V. Furthermore, the stability factor K increased with higher $V_{ds}$ and lower $V_g$, reaching a maximum of approximately 1.3, indicating unconditional stability. This work utilises small-signal parameters derived from measured S-parameters in ADS software 2022 to compare simulations with measurements through an equivalent circuit model.

This research aims to investigate how biasing influences GaN HEMTs, particularly their small-signal operation and RF performance. It proposes a systematic method for evaluating circuit components under varying bias conditions, which is crucial for optimizing GaN HEMTs for high-power and high-frequency applications, thereby advancing semiconductor technology.
## 2. Fabrication and Measurements

This study aims to investigate a HEMT based on an AlGaN/GaN heterostructure [36] grown by metalorganic vapor-phase epitaxy (MOVPE) on a 400-µm-thick silicon carbide substrate, as in Figure 1. A GaN buffer layer was incorporated into the design to achieve a 2-DEG at the AlGaN-GaN junction, which relies on the charge induced by polarization between the AlGaN and GaN layers, thereby providing a good number of electrons without the need for impurity doping. The device utilized a 20 nm Al0.253Ga0.747N barrier and a 1.5 µm GaN buffer epitaxial layer to achieve a good lattice match with the substrate (SiC). This was succeeded by a GaN channel layer and a very thin 5 nm AlGaN spacer layer, which also enables high-speed electron motion and facilitates the modulation of charge density through control of the gate bias voltage applied. To obtain low-resistance ohmic contact at the source and drain regions, a thin 5 nm cap layer of GaN was deposited. Important parameters recorded include the sheet resistance (RSH) of 324 Ω/□ from Hall measurements, and TLM showed the contact resistance (Rt) to be 0.36 Ω·mm. In Hall measurements, the charge density (N<sub>S</sub>) was greater than 1.3 × 10<sup>13</sup> cm<sup>-2</sup>, and the most significant electron mobility was higher than 1400 cm<sup>2</sup>/V·s. The gate configuration comprised four 50 µm fingers, resulting in an overall gate width of 200 µm and a gate length of 0.15 µm. Ohmic contacts of Ti/Al/Ni/Au were created by thermally annealing at 900 °C. The mushroom-shaped Schottky gate consisted of a Pt/Ti/Pt/Au stack, which helps reduce the gate capacitance and consequently enhances the control of transconductance, while decreasing leakage and noise. The device was encapsulated with a 240 nm thick Si<sub>3</sub>N<sub>4</sub> layer, deposited by PECVD at 340 °C, to further enhance efficiency and reliability. The transistors were manufactured using the UMS GH15 process. They were created through Molecular Beam Epitaxy (MBE) at IEMN in the University of Lille, France.

<figure><img src="image_5.png" /><figcaption>**Figure 1.** (a) Cross-section view of AlGaN/GaN/SiC HEMT structure (not to scale); (b) optical micrographs [36].</figcaption></figure>

Four main steps comprise the device characterization process as illustrated in Figure 2: (1) S-parameter acquisition, (2) cold pinch-off technique, (3) de-embedding, and (4) ADS simulation flow. First, an HP8510C Vector Network Analyzer (VNA), with the aid of an HP4142B DC source, supplied the required current, connected via Ground-Signal-Ground (GSG) radio frequency probes that spanned 45 MHz to 50 GHz, to measure S-parameters. Multiple biasing conditions ($V_{gs}$ from -6 V to -3 V and $V_{ds}$ from 3 V to 15 V) were used for the measurements, and IC-CAP software 2022 was employed to automate data acquisition and ensure accuracy. In the second step, extrinsic parasitic components like inductances ($L_g, L_d, L_s$), resistances ($R_g, R_s, R_d$), and pad capacitances ($C_{pg}, C_{pd}$) could be accurately extracted by suppressing intrinsic device activity using the cold pinch-off technique with $V_{gs} = -10$ V and $V_{ds} = 0$ V. Third, by gradually modifying and eliminating capacitance values ($C_{pg}$ and $C_{pd}$), a de-embedding procedure was carried out to eradicate
parasitic effects, especially the PDRZ effect, until the frequency-dependent anomalies in Re (Zij) were removed. Inductive and resistive parameters were also extracted using OFF-state bias data ($V_{gs} = 0$ V, $V_{ds} = 0$ V). A comprehensive small-signal equivalent circuit model was then constructed by importing the cleaned and bias-dependent S-parameter data into the Advanced Design System (ADS). Both extrinsic and intrinsic components ($g_m$, $C_{gs}$, $C_{gd}$, $C_{ds}$, $R_{gs}$, $R_{gd}$, and $R_{ds}$) were included in this model, which was validated through simulations under all tested frequencies and bias conditions.

<figure><img src="image_6.png" /><figcaption>**Figure 2.** Diagram depicting the methodology for quantifying and assessing 150 nm GaN HEMT.</figcaption></figure>

### 3. Results and Analysis

The operation of HEMTs can be described across different voltage regions. In the sub-threshold region, when $V_{gs}$ is less than $V_{th}$, the current increases exponentially with $V_{gs}$, but is small enough, making it suitable for ultra-low-power device applications. When the dependence of $V_{gs}$ surpasses $V_{th}$ and $V_{ds}$ is adequately elevated, the square law region fluctuates, yielding a current that is roughly equivalent to $V_{gs}$ squared. This region is optimal for amplifiers due to the advantageous correlation between $V_{gs}$ and current, making it a preferred choice in analog circuit designs. In this instance, the transconductance ($g_m$) increases with current. In contrast, elevated $V_{gs}$ values lead to the saturation of carrier velocity within the velocity saturation region, maintaining constant transconductance and diminishing the increase in current, thereby affecting performance. When selecting $V_{gs} = -3.0$ V to $-7.0$ V and $V_{ds} = 3$ V to $15$ V, it is recommended that $V_{gs}$ be maintained above the threshold level for maximum amplification, and $V_{gs}$ should not enter the velocity saturation region. Regarding the square-law region, its emphasis enables most of the HEMT's characteristics to be effectively exploited, which is why it is suitable for use in high-performance analog circuits.

#### 3.1. DC Behavior with Biasing

Figure 3a illustrates the DC attributes of a GaN HEMT. Even with $V_{ds}$ and $V_{gs}$ equal to zero, there is practically no drain current ($I_{ds}$), which is usually less than the reverse leakage current [16]. As the gate voltage increases, the current through the drain also increases. The data can be divided into two main regions: the triode region, characterized by a linear increase in $I_{ds}$ with rising $V_{ds}$, and the saturation region, where $I_{ds}$ becomes limited or
saturated once V<sub>ds</sub> reaches a specific threshold due to channel constriction at the drain side [37]. From the I-V graph, two key metrics emerge: I<sub>dss</sub>, the drain current when the transistor was saturated at V<sub>gs</sub> = -3.0 V, measured at 109 mA, and I<sub>dssm</sub>, the maximum drain-source current at peak transconductance, recorded at 26 mA. Figure 3b,c show the transconductance (g<sub>m</sub>) and transfer characteristics (g<sub>m</sub> versus V<sub>gs</sub> and I<sub>ds</sub> versus V<sub>gs</sub>). The maximum transconductance achieved was 62 mS at V<sub>gs</sub> = -4.8 V and V<sub>ds</sub> = 10 V, resulting in a ratio of 4.23 between I<sub>dss</sub> and I<sub>dssm</sub>, which indicates optimal small-signal gain [38]. The maximum transconductance values were determined at different combinations of V<sub>gs</sub> and V<sub>ds</sub>. The measurements revealed a transconductance of 46.23 mS with V<sub>gs</sub> at -4.6 V and V<sub>ds</sub> at 3 V. A transconductance of 54.48 mS was observed at a V<sub>gs</sub> of -4.6 V and a V<sub>ds</sub> of 6 V. The peak transconductance of 59.62 mS was attained at a V<sub>gs</sub> of -4.7 V and a V<sub>ds</sub> of 9 V. A value of 57 mS was recorded at V<sub>gs</sub> of -4.8 V and V<sub>ds</sub> of 12 V. A transconductance of 56.8 mS was observed at a V<sub>gs</sub> of -4.9 V and a V<sub>ds</sub> of 15 V. These values underscore the sensitivity of transconductance to variations in both V<sub>gs</sub> and V<sub>ds</sub> within the designated ranges. As V<sub>ds</sub> increased from 3 V to 15 V, the peak transconductance (g<sub>m</sub>) changed from -4.6 V to -4.9 V. This is because threshold voltage (Vth) varies with V<sub>ds</sub>, a phenomenon known as "Vth roll-off" [39]. The roll-off has a significant impact on how well the device performs. As V<sub>ds</sub> increases, Vth decreases, which means that V<sub>gs</sub> must be adjusted to maintain the desired conduction levels. This behavior improves transconductance and overall efficiency between -4.6 V and -4.9 V. These differences demonstrate the importance of carefully managing circuit design to ensure that biasing, gain, and overall reliability are stable. Figure 3c shows that the threshold voltage (Vth) values had a consistent trend in the transfer characteristics (I<sub>ds</sub> vs. V<sub>gs</sub>). The Vth values were -5.06 V at V<sub>ds</sub> = 3 V, -5.19 V at V<sub>ds</sub> = 5 V, -5.32 V at V<sub>ds</sub> = 7 V, -5.43 V at V<sub>ds</sub> = 9 V, -5.50 V at V<sub>ds</sub> = 11 V, -5.59 V at V<sub>ds</sub> = 13 V, and -5.71 V at V<sub>ds</sub> = 15 V. The decrease in Vth as V<sub>ds</sub> rises suggests that higher drain-source voltages lower the threshold voltage, possibly because of short-channel effects like drain-induced barrier lowering (DIBL) [40]. This observation is essential for understanding device performance in low-voltage applications. V<sub>ds</sub> and effective channel length influence Vth in short-channel HEMTs but remain unaffected by channel width [41]. The semi-log transfer curve in Figure 3d shows the drain-to-source dark current (I<sub>dso</sub>) measurements, indicating a notable variation in current levels as V<sub>ds</sub> increased. The dark currents observed were 1.66 pA, 0.27 pA, 8.85 nA, 4.42 nA, 0.78 nA, 2.38 µA, and 5.19 µA for V<sub>ds</sub> values of 3 V, 5 V, 7 V, 9 V, 11 V, 13 V, and 15 V, respectively. This pattern suggests an exponential growth in dark current with increasing V<sub>ds</sub>, possibly indicating enhanced carrier generation or reduced barrier potential at higher voltages [42,43].

3.2. *Equivalent Circuit Parameters with Biasing*

The equivalent-circuit approach [44], outlined in Figure 4, is employed to evaluate
the S-parameters of the device. The equivalent-circuit parameters (ECPs) were determined
using the “cold” pinch-off technique, a method that has been successfully used in GaN
technology for many years. Our analysis focused on the extrinsic parameters of the
semiconductor device, particularly the parasitic capacitances (C<sub>pg</sub> and C<sub>pd</sub>), parasitic
inductances (L<sub>g</sub>, L<sub>d</sub>, and L<sub>s</sub>), and terminal resistances (R<sub>s</sub>, R<sub>g</sub>, and R<sub>d</sub>), among other
factors. When the device was under pinch-off bias conditions (V<sub>ds</sub> = 0, V<sub>gs</sub> = -10 V),
it was observed that the parasitic capacitances primarily affected the imaginary part of
the Y parameters. We also examined the frequency dependence of these capacitances.
Figure 5 depicts the behavior of Re (Zij) for the GaN device as a function of frequency
under “unbiased” conditions. The device exhibited the PDRZ effect [45], with Re (Zij)
starting to rise significantly for the GaN around 36 GHz. The values of Re (Zij) continued
to rise with increasing frequency after this onset frequency. The PDRZ effect could be
removed from the de-embedded data by deducting the appropriate values of C<sub>pg</sub> and
C<sub>pd</sub> from the measured data and gradually increasing them from zero until the effect was
eliminated. To extract the extrinsic inductances, we used hypothetical Z parameters at
OFF bias conditions (V<sub>ds</sub> = 0, V<sub>gs</sub> = 0 V) across a specific frequency range. The results
showed that inductance L<sub>g</sub> was significantly more prominent in devices with longer gate
lengths. Additionally, it was found that the terminal resistances were heightened due to the
influence of the contact metal in the semiconductor. Amongst the three terminal resistances,
R<sub>g</sub> was the smallest, reflecting the effects of metallization in this device. Table 1 presents all
the extrinsic parameters of the device.

<figure><img src="image_7.png" /><figcaption>**Figure 3.** (a) DC characteristics, (b) transconductance characteristics, (c) transfer characteristics, and (d) semi-logarithmic transfer characteristics.</figcaption></figure>

<figure><img src="image_8.png" /><figcaption>**Figure 4.** The equivalent circuit model for the investigated GaN HEMT.</figcaption></figure>
<figure><img src="image_9.png" /><figcaption>**Figure 5.** Re ($Z_{ij}$) against frequency under zero bias condition: (a) before and (b) after de-embedding of the extrinsic capacitances.</figcaption></figure>

<table><caption>**Table 1.** Extrinsic parameter values of the GaN HEMT.</caption><thead><tr><th colspan="2">V<sub>gs</sub> = 0 V and V<sub>ds</sub> = 0 V (OFF Condition)</th></tr><tr><th>Parameters</th><th>GaN HMET</th></tr></thead><tbody><tr><td>L<sub>g</sub> (pH)</td><td>142.0</td></tr><tr><td>L<sub>s</sub> (pH)</td><td>1.80</td></tr><tr><td>L<sub>d</sub> (pH)</td><td>64.0</td></tr><tr><td>R<sub>g</sub> (Ω)</td><td>2.69</td></tr><tr><td>R<sub>s</sub> (Ω)</td><td>3.10</td></tr><tr><td>R<sub>d</sub> (Ω)</td><td>5.81</td></tr><tr><td colspan="2">V<sub>gs</sub> = -10.0 V and V<sub>ds</sub> = 0 V (PINCH-OFF Condition)</td></tr><tr><td>C<sub>pg</sub> (fF)</td><td>51.0</td></tr><tr><td>C<sub>pd</sub> (fF)</td><td>85.0</td></tr></tbody></table>

The initial phase of the extraction process is dedicated to identifying the extrinsic parameters. The intrinsic parameters can be established once these parameters are minimized. The applied bias ranged from $V_{gs} = -6.0$ V to $-3.0$ V and $V_{ds} = 3$ V to $15$ V, with intrinsic parameters being extracted between 45 MHz and 50 GHz. Figure 6a shows that the gate-source capacitance, $C_{gs}$, went up when both $V_{ds}$ and $V_{gs}$ went up. $C_{gs}$ stands for the capacitance between the gate electrode and the channel. It shows very non-linear behaviour. It includes both depletion and inversion charges, which are essential for determining the extrinsic cut-off frequency. $C_{gs}$ decreases as $V_{gs}$ decreases owing to the widening of the gate-source depletion region at higher negative voltages [46]. Furthermore, $C_{gd}$ represents the feedback capacitance between the gate and drain, as shown in Figure 6b. Remarkably, this capacitance decreased at higher $V_{ds}$, contrasting with the lower $C_{gd}$ values observed at high negative $V_{gs}$ across varying $V_{ds}$. As $V_{gs}$ increased at a constant $V_{ds}$, $C_{gd}$ gradually rose. The subsequent capacitance analyzed is the drain-source capacitance, $C_{ds}$, depicted in Figure 6c with $V_{gs}$ and $V_{ds}$. As $V_{gs}$ rose from $-6$ V to $-3$ V, the $C_{ds}$ values demonstrated a significant increase, especially at lower $V_{ds}$ values. The capacitance substantially rose as $V_{gs}$ transitioned from $-6$ V to $-5.2$ V, indicating a substantial effect of gate voltage on capacitance. The effect of changing $V_{ds}$ is clear, especially in the middle range of $V_{gs}$. On the other hand, changing $C_{ds}$ values has a bigger effect when $V_{gs}$ changes. The series resistances, $R_{gs}$ and $R_{gd}$, are derived from the real components of $Y_{11}$ and $Y_{12}$, respectively. The charging delay resulting from non-quasi-static effects is depicted by the distributed channel resistances $R_{gs}$ and $R_{gd}$ [47] in Figure 7a,b. As $V_{gs}$ went from $-6$ V to $-3$ V, the $R_{gs}$ resistance values showed a clear downward trend. The resistance was relatively high when $V_{gs}$ was low, such as around $-6$ V. However, it dropped significantly as $V_{gs}$ increased, especially between $-5.4$ V and $-4.8$ V. This behavior indicates that within this
range, elevated gate voltages result in lower resistance. The overall trend suggests a more pronounced decline with increasing Vgs, even though variations in Vds also affect the resistance values. As Vgs rose from -6 V to -3 V, the Rgd values typically exhibited a declining trend. At reduced Vgs values, especially at -6 V, the resistance was comparatively elevated, reaching its maximum at increased Vds levels. As Vgs rose, particularly between -5.4 V and -4.8 V, Rgd declined considerably, indicating that elevated gate voltages result in reduced resistance. Although changes in Vds affected Rgs, the main trend indicates that Vgs had the most significant impact on resistance characteristics. The “anomalous dip” in S-parameters is more pronounced in devices connected in series to gate-drain capacitance with higher effective gate-drain channel resistance (Rgd).

As the Vgs rose from -6 V to -3 V, the Rds values usually showed a decreasing trend, as shown in Figure 7c. Rds was relatively high at lower Vgs values (roughly -6 V), indicating that the device was less conductive. Rds dramatically decreased as Vgs increased, particularly between -5.4 V and -4.8 V, suggesting that the device has better conductivity at higher gate voltages. The overall pattern indicates that higher Vgs values result in lower Rds, underscoring the influence of gate control on the device's conductivity. In addition, the Rds values vary with Vds.

<figure><img src="image_10.png" /><figcaption>**Figure 6.** Variation in intrinsic capacitances plotted at different V<sub>ds</sub> and V<sub>gs</sub> for the AlGaN/GaN/SiC HEMT: (a) C<sub>gs</sub>, (b) C<sub>gd</sub>, and (c) C<sub>ds</sub>.</figcaption></figure>

Figure 8 illustrates the intrinsic transconductance (g<sub>mo</sub>) alongside three intrinsic time constants (τ<sub>gm</sub>, τ<sub>gs</sub>, and τ<sub>gd</sub>). The time constants arise from the transistor's inherent delay in reacting to rapid signal variations and represent the intrinsic non-quasi-static (NQS) effects that become increasingly pronounced at elevated frequencies. As V<sub>gs</sub> transitioned from -6 V to -3 V, g<sub>mo</sub> typically rose across all V<sub>ds</sub> levels, signifying improved conductivity and the creation of channels within the transistor. The g<sub>mo</sub> values were noticeably low
at $V_{gs} = -6$ V, suggesting that there was insufficient gate voltage for strong channel formation. On the other hand, $g_{mo}$ attained significantly greater values at $V_{gs} = -3$ V, peaking at roughly 0.071 mS at $V_{ds} = 11$ V, suggesting adequate amplification. The data indicate that as $V_{ds}$ increases, $g_{mo}$ tends to stabilize, signifying that the transistor entered the saturation region where further increases in $V_{ds}$ have a decreasing impact on $g_{mo}$. The time delay $\tau_{gm}$ in a transistor circuit indicates that as $V_{gs}$ becomes less negative, $\tau_{gm}$ typically decreases. This means that charge carriers can move around more easily and respond faster. The time delay increased when $V_{gs}$ was lower, such as when it was close to $-6$ V, because the conductivity was insufficient. On the other hand, values close to $-3$ V showed minimal delay, which is perfect for quick switching.

<figure><img src="image_11.png" /><figcaption>**Figure 7.** Variation in intrinsic resistances plotted at different $V_{ds}$ and $V_{gs}$: (a) $R_{gs}$, (b) $R_{gd}$, and (c) $R_{ds}$.</figcaption></figure>

Furthermore, increasing the $V_{ds}$ can improve performance, although delays may stabilize at elevated levels due to saturation effects. This relationship is crucial for designing high-speed circuits. The intrinsic time delay values, $\tau_{gs}$, ranged from approximately $3.18 \times 10^{-12}$ s at $V_{gs} = -6$ V and $V_{ds} = 3$ V to about $1.29 \times 10^{-12}$ s as $V_{gs}$ approached $-3$ V with increasing $V_{ds}$. This pattern implies that lower $\tau_{gs}$ is linked to higher $V_{gs}$, suggesting a quicker transistor response, particularly at higher $V_{ds}$ levels. The intrinsic time delay values $\tau_{gd}$ ranged from approximately $8.59 \times 10^{-12}$ s at $V_{gs} = -6$ V and $V_{ds} = 3$ V to about $3.47 \times 10^{-12}$ s at $V_{gs} = -3$ V and $V_{ds} = 3$ V. A quicker gate-drain response was indicated by decreasing $\tau_{gd}$ values as the $V_{gs}$ became less negative. According to this pattern, improved transistor switching speeds—which are essential for high-frequency applications—are a result of higher $V_{gs}$.
<figure><img src="image_12.png" /><figcaption>Figure 8. Variation in intrinsic parameters plotted at different V<sub>ds</sub> and V<sub>gs</sub> for the AlGaN/GaN/SiC HEMT: (a) g<sub>mo</sub>, (b) τ<sub>gmo</sub>, (c) τ<sub>gs</sub>, and (d) τ<sub>gd</sub>.</figcaption></figure>

Even in the presence of parasitic effects, Figure 9 demonstrates that the measured h<sub>21</sub> and MAG exhibited ideal behaviour, declining with frequency at a rate of -20 dB/decade. The f<sub>t</sub> and f<sub>max</sub> obtained from the data are displayed in the inset images in Figure 9c,d, which show an inversion at various V<sub>ds</sub> values. When V<sub>ds</sub> was higher and V<sub>gs</sub> was less negative, the cutoff frequency (Figure 9a) typically increased, indicating improved device performance. The range of values was approximately 1.18 × 10<sup>8</sup> Hz to 5.16 × 10<sup>10</sup> Hz. Better device performance under these bias conditions was indicated by the f<sub>max</sub> (Figure 9b), which normally increases with increasing V<sub>ds</sub> and decreasing negative V<sub>gs</sub>. The range of the f<sub>max</sub> values was approximately 5.23 × 10<sup>8</sup> Hz to 9.96 × 10<sup>10</sup> Hz. The transistor's suitability for high-frequency applications, such as RF amplifiers and high-speed switching, is demonstrated by both f<sub>t</sub> and f<sub>max</sub> [48].

In Figure 10, the impact of biasing on the real part of Y<sub>21</sub>, the magnitude of S<sub>21</sub>, and the stability factor K, is illustrated. It is essential to note that the low-frequency values of both Y<sub>21</sub> and S<sub>21</sub> are specifically correlated with the intrinsic transconductance g<sub>mo</sub>, as depicted below [49]:

$$Y_{21} = \frac{g_{mo}}{1 + g_{mo}R_s + g_{DS}(R_s + R_D)} \qquad (1)$$

$$S_{21} = -2Y_{21} \left( Z_0 / Y_{22}^{-1} \right) \qquad (2)$$

where Z<sub>0</sub> equals 50 ohms, which is generally much smaller than 1/Y<sub>22</sub>.
<figure><img src="image_13.png" /><figcaption>**Figure 9.** Variation in cut-off and maximum frequencies: (a) f<sub>t</sub>, (b) f<sub>max</sub>, (c) h<sub>21</sub>, (d) MAG.</figcaption></figure>

The S<sub>21</sub> parameter indicates that the values were highly negative at lower V<sub>gs</sub>, such as -6 V, but increased significantly as V<sub>gs</sub> approached -3.0 V, reflecting improved signal transmission. The highest S<sub>21</sub> values, approximately 11.2 dB, occurred when V<sub>gs</sub> = -3.2 V and V<sub>ds</sub> ranged from 11 to 15 V. Additionally, beyond a certain point, higher V<sub>ds</sub> values resulted in smaller gains, indicating the transistor's limitations. As the drain-source voltage rose, the Y<sub>21</sub> values typically increased with higher V<sub>ds</sub> across the various V<sub>gs</sub> values, indicating improved signal transmission. The Y<sub>21</sub> values tended to rise as V<sub>gs</sub> became less negative (going from -6 V to -3 V), suggesting improved conductivity and transmission properties of the transistor. The values, which fell between roughly 0.032 and 0.043, indicate that the transistor exhibits good signal amplification capabilities within the tested voltage range. As V<sub>ds</sub> rose, the stability factor K usually increased as well. This was especially noticeable at V<sub>gs</sub> = -3 V, where K peaked at about 1.30. Conversely, lower V<sub>gs</sub> values exhibited a decreasing trend in K for most V<sub>ds</sub> levels, particularly at V<sub>gs</sub> = -6 V, where K initially started at around 1.05 but increased slightly at higher V<sub>ds</sub> values.

The equivalent-circuit model's precision in depicting the device's performance under these conditions is corroborated by the robust correlation between simulations and experimental data (Figure 11). Table 2 shows the coefficient of determination (R<sup>2</sup>) and root mean square error (RMSE) values for each bias setting. This was to verify that the simulated and experimental results are in agreement. The model's accuracy was validated by the low RMSE and high R<sup>2</sup> values; the former indicates the magnitude of error between the simulated and observed S<sub>21</sub> values, while the latter demonstrates the robustness of the linear
correlation. This validation is essential for assessing practical performance, optimizing design, and advancing complex RF integrated circuit designs.

<figure><img src="image_14.png" /><figcaption>**Figure 10.** Variation in the intrinsic parameters: (a) $S_{21}$, (b) $Y_{21}$, and (c) K.</figcaption></figure>

<figure><img src="image_15.png" /><figcaption>**Figure 11.** Verification of experimental (black) and modeled (red) data: (a) at $V_{ds}$ = 15 V, $V_{gs}$ = -4.8 V, (b) at $V_{ds}$ = 13 V, $V_{gs}$ = -4.6 V, (c) at $V_{ds}$ = 11 V, $V_{gs}$ = -4.4 V, and (d) at $V_{ds}$ = 9 V, $V_{gs}$ = -4.2 V.</figcaption></figure>
<table><caption>**Table 2.** Quantitative comparison between simulated and experimental data (Figure 11).</caption><thead><tr><th>Bias Condition (V<sub>ds</sub>, V<sub>gs</sub>)</th><th>RMSE (dB)</th><th>R<sup>2</sup> Value</th></tr></thead><tbody><tr><td>V<sub>ds</sub> = 15 V, V<sub>gs</sub> = -4.8 V</td><td>0.52</td><td>0.993</td></tr><tr><td>V<sub>ds</sub> = 13 V, V<sub>gs</sub> = -4.6 V</td><td>0.47</td><td>0.991</td></tr><tr><td>V<sub>ds</sub> = 11 V, V<sub>gs</sub> = -4.4 V</td><td>0.43</td><td>0.994</td></tr><tr><td>V<sub>ds</sub> = 9 V, V<sub>gs</sub> = -4.2 V</td><td>0.39</td><td>0.995</td></tr></tbody></table>

The data in Table 3 illustrate the performance of the GaN HEMT at varying V<sub>ds</sub> with a constant V<sub>gs</sub> of -4.8 V. The I<sub>ds</sub> consistently rose from 21.81 mA to 54.71 mA as V<sub>ds</sub> increased from 3 V to 15 V, suggesting better conduction and increased amplification potential. The transconductance (g<sub>m</sub>) peaked at 61.25 mS at 7 V, and the intrinsic g<sub>mo</sub> also peaked at 73.77 mS under the same conditions. This indicates that the output current control is functioning properly. The C<sub>gd</sub> went down, which is good because it would reduce the Miller effect and make things more stable. However, the C<sub>gs</sub> went up, which could mean that switching speeds would be slower. The resistances of R<sub>gs</sub> and R<sub>gd</sub> also increased, which could alter the input impedance and the amount of power used. Higher distributed resistance and a delayed charge response are likely causes of the increasing trend of R<sub>gd</sub> with V<sub>ds</sub>, resulting from non-quasi-static effects and increased voltage stress across the gate-drain region at higher drain biases.

<table><caption>**Table 3.** DC, RF, and intrinsic parameters for various drain biases at V<sub>gs</sub> = -4.8 V.</caption><thead><tr><th>V<sub>ds</sub> (V)</th><th>I<sub>ds</sub> (mA)</th><th>g<sub>m</sub> (mS)</th><th>C<sub>gs</sub> (fF)</th><th>C<sub>gd</sub> (fF)</th><th>C<sub>ds</sub> (fF)</th><th>R<sub>gs</sub> (Ω)</th><th>R<sub>gd</sub> (Ω)</th><th>R<sub>ds</sub> (Ω)</th><th>g<sub>mo</sub> (mS)</th><th>τ<sub>gm</sub> (ps)</th><th>τ<sub>gs</sub> (ps)</th><th>τ<sub>gd</sub> (ps)</th><th>f<sub>t</sub> (GHz)</th><th>f<sub>max</sub> (GHz)</th><th>S<sub>21</sub> (dB)</th><th>Y<sub>21</sub> (S)</th><th>K</th></tr></thead><tbody><tr><td>3</td><td>21.81</td><td>45.45</td><td>192.51</td><td>55.62</td><td>163.79</td><td>1.08</td><td>13.04</td><td>166.01</td><td>67.96</td><td>2.27</td><td>1.31</td><td>4.55</td><td>45.81</td><td>84.72</td><td>12.70</td><td>0.0327</td><td>1.04</td></tr><tr><td>5</td><td>29.54</td><td>50.02</td><td>195.91</td><td>52.68</td><td>162.17</td><td>1.15</td><td>14.83</td><td>158.10</td><td>72.57</td><td>2.15</td><td>1.42</td><td>4.89</td><td>50.92</td><td>92.34</td><td>13.45</td><td>0.03093</td><td>0.97</td></tr><tr><td>7</td><td>37.73</td><td>61.25</td><td>197.27</td><td>49.16</td><td>160.65</td><td>1.23</td><td>16.63</td><td>177.12</td><td>73.77</td><td>2.17</td><td>1.52</td><td>5.13</td><td>51.62</td><td>96.01</td><td>13.63</td><td>0.03052</td><td>0.96</td></tr><tr><td>9</td><td>43.65</td><td>56.36</td><td>201.39</td><td>45.20</td><td>159.13</td><td>1.39</td><td>20.07</td><td>196.14</td><td>73.66</td><td>2.20</td><td>1.76</td><td>5.70</td><td>50.46</td><td>98.12</td><td>13.74</td><td>0.03049</td><td>0.96</td></tr><tr><td>11</td><td>47.75</td><td>56.88</td><td>205.21</td><td>42.21</td><td>157.56</td><td>1.46</td><td>21.87</td><td>201.70</td><td>72.90</td><td>2.24</td><td>1.89</td><td>5.79</td><td>48.80</td><td>98.90</td><td>13.75</td><td>0.03037</td><td>0.97</td></tr><tr><td>13</td><td>51.40</td><td>56.58</td><td>209.26</td><td>39.76</td><td>156.01</td><td>1.58</td><td>24.49</td><td>213.99</td><td>71.70</td><td>2.30</td><td>2.08</td><td>6.11</td><td>46.82</td><td>98.76</td><td>13.72</td><td>0.03041</td><td>0.99</td></tr><tr><td>15</td><td>54.71</td><td>55.83</td><td>212.77</td><td>37.65</td><td>154.46</td><td>1.70</td><td>27.11</td><td>226.28</td><td>70.26</td><td>2.35</td><td>2.27</td><td>6.41</td><td>44.83</td><td>98.16</td><td>13.66</td><td>0.03048</td><td>1.01</td></tr></tbody></table>

R<sub>ds</sub> showed some fluctuation, which could affect efficiency and heat generation. Time constants (τ<sub>gm</sub>, τ<sub>gs</sub>, τ<sub>gd</sub>) also increased with V<sub>ds</sub>, resulting in longer response times and potentially limiting high-speed performance. f<sub>t</sub> reached its highest point at 51.62 GHz at 7 V, and f<sub>max</sub> rose to 98.90 GHz at 11 V. This means that the device can work at high frequencies. Overall, the forward gearbox gain, S<sub>21</sub>, increased slightly, indicating that amplification remained stable. The forward transconductance parameter, Y<sub>21</sub>, remained constant, indicating that the device remained stable. The stability factor K remained close to 1, indicating that the entire device operated effectively.

## 4. Discussions and Future Directions

This study thoroughly investigates the performance of the 150 nm AlGaN/GaN HEMT on a SiC substrate in the DC, RF, and small-signal regimes. Essential conclusions are emphasised, including the necessity for precise V<sub>ds</sub> control in high-frequency applications and the threshold voltage's (Vth) susceptibility to the drain-source voltage (V<sub>ds</sub>), which signifies short-channel phenomena such as DIBL. The study found that transconductance (g<sub>m</sub> and g<sub>mo</sub>) also changed with bias points, which suggests that charge transport is not linear. The highest intrinsic transconductance occurred at V<sub>gs</sub> = -4.8 V and V<sub>ds</sub> = 11 V, which was when the small-signal gain was at its highest. This highlights the importance of parasitic elements, such as capacitances (C<sub>pg</sub>, C<sub>pd</sub>) and resistances (R<sub>g</sub>, R<sub>s</sub>, R<sub>d</sub>), and illustrates how they affect high-frequency performance and frequency-dependent behaviour. Capacitance trends also indicate that increasing V<sub>gs</sub> and V<sub>ds</sub> could enhance forward gain and mitigate
the Miller effect. This can improve high-frequency parameters, such as $f_t$ and $f_{max}$. The research illustrates the influence of intrinsic resistances on conductivity and switching times, indicating that enhancements in resistance at reduced negative gate biases facilitated expedited carrier movement and diminished RC time delays. The S-parameter and Y-parameter responses confirm that signal transmission was improved and the RF amplifier performed well in various situations. Ultimately, the study offers essential insights for future RF circuit designs by validating the equivalent circuit model through substantial concordance with both measured and simulated results.

Future research must focus on several critical domains. To determine how GaN HEMTs will perform over time, they must undergo accelerated ageing tests, particularly under various biasing conditions. This will help us understand how the devices break down, how they fail, and how stable their performance is in high-power, high-frequency applications. A comparative analysis of GaN HEMT performance on various substrates, including SiC, Sapphire, and Si, could also shed light on the trade-offs between power handling, efficiency, cost, and scalability. Additionally, because non-linearities and parasitic effects become more pronounced at higher frequencies, future research should focus on enhancing thermal management, developing innovative packaging technologies, and optimizing device design to ensure that devices operate effectively in the mmWave and terahertz ranges. We also need better methods to address issues with device uniformity that arise due to fabrication tolerances. These tolerances are necessary to ensure that devices function consistently across a wide range of commercial applications. Ultimately, future research should incorporate noise figure measurements and power handling tests to gain a deeper understanding of how GaN HEMTs function. To further enhance the dependability and power handling capabilities of GaN HEMTs for high-frequency applications, effective thermal management techniques should be employed.

## 5. Conclusions

The detailed analysis reveals that the GaN HEMT device has considerable potential for high-frequency applications. It also illustrates the complexity of the relationship between performance metrics and biasing conditions. When there was no bias, the device had a low drain current. As the gate voltage ($V_{gs}$) increased, the drain current ($I_{ds}$) also increased. There were two distinct operating regions: the triode and saturation regions. Key metrics, such as $I_{dss}$ and maximum transconductance ($g_m$), show that the device could significantly amplify signals, especially when the bias levels are just right. The observed decrease in threshold voltage ($V_{th}$) as the drain-source voltage ($V_{ds}$) increased indicates that drain-induced barrier lowering (DIBL) and other important short-channel effects were occurring. To ensure the device works properly, these effects must be kept in check. Additionally, the dark current's exponential growth with higher $V_{ds}$ suggests that more carriers were being generated, which could render high-voltage applications less reliable. Finding the equivalent circuit parameters reveals how parasitic components impact a device's operation. For example, capacitances and resistances are very sensitive to changes in $V_{gs}$ and $V_{ds}$. Analysis of the intrinsic parameters shows that response times were faster and transconductance was better at lower negative gate voltages. These parameters are crucial for applications that require rapid switching. In the end, the equivalent-circuit model and the experimental data agreed very well with each other, indicating that the model is accurate in predicting the performance of a device. This study not only enhances our understanding of how GaN HEMTs function, but also provides valuable insights for developing more effective designs in cutting-edge RF integrated circuits.

**Author Contributions:** Conceptualization, M.A.A.; methodology, M.A.A. and C.G.; validation, M.A.A.; investigation, M.A.A.; writing—original draft preparation, M.A.A.; writing, review, and
editing, C.G.; supervision, C.G. All authors have read and agreed to the published version of
the manuscript.

**Funding:** This research received no external funding.

**Data Availability Statement:** The data presented in this study are available on request from the authors.

**Conflicts of Interest:** The authors declare no conflict of interest.

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