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Numerical simulation and analytical modelling of
self-heating in FDSOI MOSFETs down to very deep
cryogenic temperatures

Gérard Ghibaudo, M. Cassé, Francis Balestra

► To cite this version:

Gérard Ghibaudo, M. Cassé, Francis Balestra. Numerical simulation and analytical modelling of self-heating in FDSOI MOSFETs down to very deep cryogenic temperatures. World journal of physics, 2023, 01 (02), pp.87-109. 10.56439/WJP/2023.1110. hal-04273066

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https://hal.science/hal-04273066v1

Submitted on 11 Oct 2024

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# Numerical simulation and analytical modelling of self-heating in FDSOI MOSFETs down to very deep cryogenic temperatures

G. Ghibaudo

IMEP-LAHC, Univ. Grenoble Alpes,
Minatec, 38016 Grenoble, France

gerard.ghibaudo@gmail.com

M. Cassé

LETI-CEA, Univ. Grenoble Alpes, Minatec,
38054 Grenoble, France

F. Balestra

IMEP-LAHC, Univ. Grenoble Alpes,
Minatec, 38016 Grenoble, France

**Corresponding Author:** G. Ghibaudo

**Copyright** © 2023 G. Ghibaudo et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

## Abstract

Self-heating (SHE) TCAD numerical simulations have been performed, for the first time, on 30nm FDSOI MOS transistors at extremely low temperatures. The self-heating temperature rise □□□□ and the thermal resistance □h are computed as functions of the ambient temperature □o and the dissipated electrical power (□□), considering calibrated silicon and oxide thermal conductivities. The characteristics of the SHE temperature rise □□□□□(□□)display sub-linear behavior at sufficiently high levels of dissipated power, in line with standard FDSOI SHE experimental data. It has been observed that the SHE temperature rise □□□□ can significantly exceed the ambient temperature more easily at very low temperatures. Furthermore, a detailed thermal analysis of the primary heat flows in the FDSOI device has been conducted, leading to the development of an analytical SHE model calibrated against TCAD simulation data. This SHE analytical model accurately describes the □□□□ (□□) and □h (□) characteristics of an FDSOI MOS device operating at extreme low ambient temperatures. These TCAD simulations and analytical models hold great promise for predicting the SHE and electro-thermal performance of FDSOI MOS transistors against ambient temperature and dissipated power.

**Keywords:** Self-heating, electro-thermal transport, TCAD simulation, self-heating analytical modelling, FDSOI-MOSFET, cryogenic temperature.

## 1. INTRODUCTION

Cryogenic electronics remains an important area of research due to its ability to enhance circuit performance in terms of operation speed, turn-on behavior, thermal noise reduction, and punch-through
decrease [1–5]. It finds applications in various fields such as high-speed computing, detection and sensing, spatial electronics, readout CMOS electronics, and q-bit MOS devices for quantum computing [6–8]. However, there are still several challenges in characterizing and modeling CMOS devices at very low temperatures. Recent efforts have focused on achieving TCAD device simulations at deep cryogenic temperatures [9–11], with a particular emphasis on conducting electro-thermal simulations to assess self-heating (SHE) in FDSOI MOS devices at low temperatures [12–16]. However, self-heating electro-thermal simulations in CMOS devices at deep cryogenic temperatures are still lacking due to the significant challenges involved. Such simulations could provide crucial insights into the electro-thermal properties and self-heating phenomena in FDSOI MOS devices operating within the sub-Kelvin temperature range, especially in the context of quantum computing.

Therefore, in this study, building upon our previous work dedicated to electro-thermal transport coefficients in FDSOI MOS devices operating under deep cryogenic conditions [17], we present, for the first time, self-heating 2D TCAD semi-classical simulations performed on 30nm FDSOI MOS transistors at very low temperatures (around 10mK). We investigate the temperature rise caused by self-heating and evaluate the thermal resistance as functions of ambient temperature and dissipated power, taking into account calibrated material thermal conductivity. Additionally, by conducting a detailed thermal analysis of the primary heat flows within the FDSOI structure, we develop an analytical model for self-heating that accurately describes the temperature rise and thermal resistance in FDSOI MOS devices across a range of dissipated powers, even when operating at ambient temperatures as low as 10mK. This comprehensive approach allows us to predict the electro-thermal performance of FDSOI MOS transistors in extremely deep cryogenic conditions.

## 2. THEORETICAL BACKGROUND AND SIMULATION METHODOLOGY

In this section, we will discuss the equations governing electro-thermal transport in the FDSOI structure illustrated in Fig. 1. The simulated FDSOI structure comprises a 4nm top oxide thickness, a 6nm undoped silicon film, and a 20nm bottom oxide (BOX), with a channel length of 30nm. To simplify the computations, we have omitted the silicon substrate beneath the BOX and the physical source and drain regions.

The transport parameters, such as carrier density ($n$), electron mobility (μ), electronic conductivity (σ), thermopower ($S$), and electronic thermal conductivity (κ), are formulated using analytical approximations suitable for 2D TCAD semi-classical simulations. Furthermore, empirical analytical functions, calibrated using literature experimental data, are employed to express the lattice thermal conductivity in the silicon channel, as well as in the top and bottom oxides.

Finally, we present the methodology for solving the Poisson and electro-thermal transport equations, along with the associated boundary conditions. It should be mentioned that herein specific boundary conditions are applied on a single 30nm channel length device in order to properly differentiate short and long channel situations.
<figure><img src="image_3.png" /><figcaption>Figure 1: Schematic of FDSOI structure used for simulation (t□1 = 4nm, t□2 = 20nm, t□ = 6nm, □ = 30nm).</figcaption></figure>

## 2.1 Electro-Thermal Transport Equations

In silicon, the equations governing electron charge and heat transport can be expressed using linear response theory as follows [18]:

$$ \square_0 = \square_0 \nabla \square_0 - \square_0 \square_0 \nabla \square_0 \quad (1a) $$

$$ \square_0 = \square_0 \square_0 \nabla \square_0 - \square_0 \square_0 h \nabla \square_0 \quad (1b) $$

where $\square_0$ is electronic current density (A/cm²), $\square_0$ is the heat thermal flux density (W/cm²), $\square_0$ is the electron quasi-Fermi level, T is the local lattice temperature, $\square_0$ is the electronic conductivity, S is the thermopower (or Seebeck coefficient) and $\square_0 h$ is the heat thermal conductivity.

The local electrical conductivity $\square_0$ in the silicon channel is evaluated by considering a standard mobility law both depending on temperature, local vertical electric field $\square_0$ and lateral electric field $\square_0$ as [11, 17, 19],

$$ \square (\square) = \square_0 \square_0 \square_0 \quad (2a) $$

$$ \text{with} \quad \square_0 (\square) = \frac{[\frac{1}{5000} + \frac{1}{600} \square_0]}{\frac{1}{300}} \quad (\text{cm}^2/\text{Vs}) \quad (2b) $$

$$ \text{and} \quad \square = \frac{\square_0 (\square)}{1 + \frac{\square_0 (\square)}{1 + \square_0}} \quad (2c) $$

where $\square_0$ is a critical field (≈1MV/cm) allowing to emulate the mobility degradation at high gate voltage caused by surface roughness scattering, whereas $\square_0 = \square_0 \square_0 \square_0$, with $\square_0 \square_0 = 1.3 \times 10^7 / (1+\square_0/1000)$ being the electron saturation velocity (cm/s), accounting for the mobility decrease due to saturation velocity effect in short channel devices. Note that the latter effect is disabled in long
It is worth noting that the electrical conductivity in the top and bottom oxides is considered to be zero, as they are treated as perfect insulating dielectrics.

The bulk silicon heat conductivity data from Callaway [22] were adjusted to consider the reduction of □□□ in thin silicon films (in this case, 6nm) caused by increased phonon boundary scattering. This adjustment was performed using the approach proposed by Ashegi et al. [23]. The data were then interpolated and extrapolated with respect to temperature using a combined power law analytical function of the form [17],

$$ \Box\Box\Box(\Box) = 1.06 \times 10^4 \Box^{-1.7} + 2.6 \times 10^{-2} \Box^{-1} \quad [\text{W}/(\text{cm}\cdot\text{K})]. \quad (6) $$

Since the silicon channel is surrounded by a dielectric material (silicon dioxide), it is important to consider the heat conduction in the silicon dioxide as well. For this purpose, the heat conductivity data for silicon dioxide (□□□) adapted from Lee and Cahill [24] were fitted using a combined power law analytical function of the form,

$$ \Box\Box\Box(\Box) = 1.5 \times 10^4 \Box^{-1} + 6.3 \times 10^{-2} \Box^{-1} \quad [\text{W}/(\text{cm}\cdot\text{K})]. \quad (7) $$

As can be seen from Fig. 2, these fitting functions provide good approximations for both □□□ and □□□ as a function of temperature, especially in the cryogenic range where they will be extrapolated.

<figure><img src="image_4.png" /><figcaption>Figure 2: Experimental (symbols) and fitted (solid lines) variations of heat thermal conductivity for silicon □□□ and silicon dioxide □□□ as a function of temperature T. Experimental data taken from Refs [22, 24].</figcaption></figure>

## 2.2 Numerical Simulation Methodology

To simulate the self-heating in the FDSOI n MOSFET shown in Fig. 1, it is necessary to solve the Poisson equation, the electronic current continuity equation, and the heat flow continuity equation
self-consistently. By solving these equations simultaneously, the electro-thermal behavior of the device can be accurately modeled, taking into account the interaction between electrical and thermal effects.

The Poisson equation governing the electrical potential V in the FDSOI structure with channel residual doping level □□ reads,

$$ \nabla (\Box \Box \nabla \Box) = \Box \quad \int_{\Box} \frac{\Box (\Box - \Box_0 - \Box_1)}{\Box_0} - \Box \frac{\Box (-\Box - \Box_0)}{\Box_0} - \frac{\Box \Box}{1 + 4 \Box \Box \Box} \frac{\Box \Box}{\Box_0 + \Box_1} \quad (\text{Silicon}) $$

(8a)

$$ \nabla (\Box \Box \nabla \Box) = 0 \quad (\text{Oxide}) \quad (8b) $$

where □□□ and □□□ being the oxide and silicon permittivities, respectively, □0 ( ζ 0.55V) the mid-gap potential and □□ the impurity ionization potential (□□=□0-50mV). The carrier concentrations in Eq. (8a) were computed using the analytical approximation of Eq. (3). In practice, the hole concentration was overlooked as being negligible in an n MOSFET structure biased from weak to strong inversion.

The electronic current continuity equation in the silicon channel is given by,

$$ \nabla (\Box \Box) = \nabla (\Box \cdot \nabla \Box \Box - \Box \cdot \nabla \Box) = 0 \quad (\text{Silicon}) \quad (9) $$

where □ and S are evaluated with Eqs (2) and (4).

Similarly, the heat thermal flow continuity equations in the FDSOI structure accounting for the Joule dissipation in the silicon channel are expressed as,

$$ \nabla (\Box \Box) = (\Box \cdot \Box \cdot \nabla \Box \Box - \Box \cdot \Box \cdot \nabla \Box) = |\Box \Box|^2 / \Box \quad (\text{Silicon}) \quad (10a) $$

$$ \nabla (\Box \Box) = \nabla (-\Box \Box \nabla \Box) = 0 \quad (\text{Oxide}) \quad (10b) $$

where □□h = □□□ ⊕ □ is given by Eqs (5) and (6) and □ is given by Eq. (7). Note the presence of the source term |□□|²/□ in Eq. (10a) responsible for the self-heating in the silicon channel.

The equations (8) to (10) mentioned above were solved self-consistently in two dimensions using the finite element software FlexPDE [25]. Proper boundary conditions (BC) were defined within the FDSOI structure for the numerical simulations. The boundary conditions utilized in the simulations are summarized in Fig. 3 for the two thermal BC configurations considered in this study. In both cases, the electrical BC's are identical. Note that here specific boundary conditions are applied on a 30nm channel length device in order to differentiate short and long channel situations. The electrical potential V is fixed to the front gate voltage □□1 at the top gate (G) and to zero at the bottom gate (B). The quasi-Fermi potential □□ is set to zero at the source (S) and to the drain voltage □□ at the drain (D). At the source and drain boundaries, □□/□□ = 0 is imposed to emulate a long channel condition. In the case of a short channel, V is fixed to □□ at the source and to (□□ + □□) at the drain, where □□ ≈ 0.6V for a degenerate source-drain region with an n-type doping level N□ = 5 × 10¹⁹/cm³. In the “BSDG” BC configuration, the temperature T is fixed to the ambient temperature □□ at all boundaries, including the front gate (G), source (S), drain (D), and bottom gate (B). This configuration represents the case where the FDSOI device is thermally grounded at all electrodes, providing the best thermalization scenario. In the “B” BC configuration, the temperature
$T$ is only fixed to □□ at the bottom gate (B), assuming no or negligible heat flow at the source, drain, and top gate electrodes. This configuration represents the worst thermalization case since the bottom oxide (BOX) has the highest thermal resistance. It should be noted that this “B” BC configuration does not account for the thermal resistance of the silicon substrate, which is omitted in the simulation. However, it has been found based on separate heat transport simulations that the thermal spreading resistance of a thick silicon layer (300 μm) underneath a narrow BOX (30nm) is much smaller than the BOX thermal resistance due to the lower thermal conductivity of the BOX material and by turn can be neglected in the SHE simulation (see Fig. 2).

<figure><img src="image_5.png" /><figcaption>Figure 3: Schematic showing the two typical boundary conditions used for the numerical simulations carried out this work.</figcaption></figure>

Figure 4 shows typical results obtained from numerical simulations for the temperature rise ($dT=T_{\text{on}}$) with “BSDG” BC configuration, in which the ambient temperature (□□) is set to 10K. It can be observed that $dT$ exhibits a bell-shaped behavior with a peak located in the middle of the silicon film near the front oxide interface, where the channel is formed. This behavior is obtained by applying a front gate voltage □□1 = 1V and a drain voltage □□=43mV. In the presented example, the maximum temperature rise (□□□□□) is approximately 12K, which exceeds the imposed ambient temperature □□ of 10K at all boundaries in the “BSDG” configuration. It should be mentioned that as □□ is increased, the device goes into triode regime and the maximum temperature rise □□□□ is slightly displaced towards the drain side. In any case, once the maximum temperature rise is determined,
<figure><img src="image_6.png" /><figcaption>Figure 6: Temperature dependence of the subthreshold swing SS in linear scale (left) and log scale (right) as obtained from the transfer curves of Fig. 5 (long channel case FDSOI MOSFET, $t_{on}1 = 4$nm, $t_{on}2 = 10$nm, $t_{off} = 6$nm, $V_{GS} = 30$nm, $V_{GS} = 1$mV, $V_{GS} = 25$K).</figcaption></figure>

## 3.1 Self-Heating Results for “BSDG” BC configuration

We conducted simulations of typical output drain current $I_D(V_D)$ characteristics for a long channel BC FDSOI MOSFET under various ambient temperatures, both with and without self-heating effects (see Fig. 7a). The corresponding relative changes in drain current due to self-heating, $\Delta I/|I|$, are presented in Fig. 7b. It is important to highlight the significant influence of self-heating on the amplitude of the drain current, particularly as the ambient temperature is decreased towards deep cryogenic conditions. These results underscore the importance of considering self-heating effects when analyzing the performance of FDSOI MOSFETs operating in extreme temperature environments.

Figure 8 presents a comparison of the drain current output characteristics, $I_D(V_D)$, obtained from numerical simulations without (a) and with (b) consideration of the thermopower ($S$) term in the electro-thermal transport equations (1). Upon initial observation, it appears that the inclusion of the thermopower term has a negligible impact on the drain current characteristics.

Similarly, in Fig. 9, the maximum temperature rise characteristics, $\Delta T_{max}(\Delta T)$, are presented as function of power $\Delta P$, as obtained from numerical simulations without (a) and with (b) the inclusion of the thermopower in the electro-thermal transport equations. It can be observed that the influence of the thermopower on the maximum temperature rise appears to be minor, particularly at deep cryogenic temperatures. This observation is further supported by the plot of the corresponding thermal resistance $R_h$ as function of power $\Delta P$, as shown in Fig. 10, where only slight differences are observed, mainly at 100K. This result can be attributed to the fact that the thermopower in the metallic regime exhibits a linear variation with temperature and, as a consequence, diminishes at cryogenic temperatures [17].
<figure><img src="image_7.png" /><figcaption>Figure 7: a) Temperature dependence of $I_D(V)$ output characteristics obtained by numerical simulations with (solid lines) and without (dashed lines) self-heating. b) Corresponding relative drain current change $I_D(V)/I_D(V)$ due to self-heating (long channel case FDSOI MOSFET, $t_{on} = 4$nm, $t_{off} = 10$nm, $t_{on} = 6$nm, $I = 30$nm, $I_{on} = 1$V, $I_{off} = 25$K).</figcaption></figure>

<figure><img src="image_8.png" /><figcaption>Figure 8: Temperature dependence of $I_D(V)$ output characteristics obtained by numerical simulations without (a) and with (b) consideration of thermopower in the electro-thermal transport equations (long channel case FDSOI MOSFET, $t_{on} = 4$nm, $t_{off} = 10$nm, $t_{on} = 6$nm, $I = 30$nm, $I_{on} = 1$V, $I_{off} = 25$K).</figcaption></figure>

Based on the observed characteristics and results, it can be concluded that, as a first approximation, the thermopower term can be neglected in the electro-thermal transport equations for self-heating since the numerical simulations. This simplification is valuable as it significantly reduces the computation time, typically by a factor of 4-5, by more decoupling the electro-thermal transport equations (1a).
<figure><img src="image_9.png" /><figcaption>Figure 9: Temperature dependence of □□□□(□) characteristics obtained by numerical simulations without (a) and with (b) consideration of thermopower in the electro-thermal transport equations (long channel case FDSOI MOSFET, $t_{□1} = 4$nm, $t_{□2} = 10$nm, $t_{□} = 6$nm, □ = 30nm, □□1 = 1V, □□ = 25K).</figcaption></figure>

<figure><img src="image_10.png" /><figcaption>Figure 10: Temperature dependence of □ره (□) characteristics obtained by numerical simulations without (a) and with (b) consideration of thermopower in the electro-thermal transport equations (long channel case FDSOI MOSFET, $t_{□1} = 4$nm, $t_{□2} = 10$nm, $t_{□} = 6$nm, □ = 30nm, □□1 = 1V, □□ = 25K).</figcaption></figure>

and (1b). Therefore, in most of our self-heating studies, we will primarily focus on numerical results obtained with $S = 0$, assuming no thermopower contribution.
In Figure 11a, the variations of the thermal resistance $R_h$ with the ambient temperature $T_a$ are shown for various drain voltage values. The solid lines represent the results obtained by numerical simulations without considering the thermopower term in the electro-thermal transport equations, while the symbols represent the results with the inclusion of the thermopower term. These results further confirm that the thermopower term can be mostly neglected in the self-heating electro-thermal simulations. It is noteworthy that as the drain voltage increases, the thermal resistance $R_h$ saturates at an earlier ambient temperature, while still following the same decreasing asymptotic trend with increasing ambient temperature.

<figure><img src="image_11.png" /><figcaption>Figure 11: a) Variations of thermal resistance $R_h$ with ambient temperature $T_a$ as obtained by numerical simulations without (solid lines) and with (symbols) consideration of thermopower in the electro-thermal transport equations for various drain voltages (long channel case FDSOI MOSFET, $t_{a1} = 4$nm, $t_{a2} = 10$nm, $t_{a3} = 6$nm, $V_{d} = 30$nm, $V_{a} = 1$V, $I_{D} = 25$K). b) Variations of thermal resistance $R_h$ with ambient temperature $T_a$ as obtained by numerical simulations (solid lines) and with model $R_h(t_a, I_a) = R_h(t_a, I_a)$ of Eq. (A6) (dashed lines) for various drain voltages (long channel case FDSOI MOSFET, $t_{a1} = 4$nm, $t_{a2} = 10$nm, $t_{a3} = 6$nm, $V_{d} = 30$nm, $V_{a} = 1$V, $I_{D} = 25$K).</figcaption></figure>

In Figure 11b, a comparison is shown between the variations of thermal resistance $R_h(t_a)$ obtained from self-heating numerical simulations and semi-analytical modeling. The analytical model is based on the equivalent circuit of thermal resistances depicted in Fig. 12. To construct the analytical model, it is first noted that the one-dimensional thermal resistance $R_1$ of a material with conductivity $\kappa_1(T)$, length $l_1$, and width $w_1$, subjected to a temperature difference $dT$, can be expressed as Equation (A1), indicating that $R_1$ is a function not only of temperature $T$ but also of $dT$. Considering the “BSDG BC” condition, where the thermal heat primarily flows from the hot point in the channel to the gate through the front oxide, to the body through the BOX, and to the source and drain along the silicon channel, the global equivalent resistance $R_h(t_a, I_a)$ (T,dT) can be derived from the heat flow partition as expressed in Eq. (A6). The vertical resistance $R_{\text{vertical}}$ is neglected due to the thinness of the silicon layer. The modeling results in Fig. 12b are obtained from $R_h(t_a, I_a)$ (□, △□□), where △□□ corresponds to the values obtained from the numerical simulations for $R_h(□)$. With Equation (A6), the saturation of $R_h$ at low □ for higher □ values
can now be interpreted as the result of the strong nonlinearity of □h□□□ (□, □□□□) due to larger □□□□ at higher power i.e. higher □ values.

<figure><img src="image_12.png" /><figcaption>Figure 12: a) Schematic of thermal resistance equivalent circuit used for the analytical modelling of effective thermal resistance in the FDSOI structure for “BSDG” BC configuration. b) Formula of elementary thermal resistances in BOX, front oxide and silicon layer in the FDSOI structure.</figcaption></figure>

The characteristics □□□(□) shown in Fig. 13 provide further insights into the behavior of self-heating. Both numerical simulations and analytical modeling using Eq. (A7) are compared, demonstrating excellent agreement between the two. From the figure, it can be observed that as the temperature is lowered, the self-heating temperature rise □□□□ more easily enters the sublinear regime with respect to power, leading to nonlinearity in the thermal resistance. Additionally, at high power in the sublinear regime and at low ambient temperature, the maximum temperature rise □□□□ typically varies as ≈ □$^{0.5}$. This behavior can be attributed to the temperature dependence of □□(T) and □□(T), which are involved in Eqs (A2) to (A6).

Figure 14 presents the variations of the thermal resistance □h with power as obtained from both numerical simulations and analytical modeling using Eqs (A6) and (A7). The very good agreement between the two results is noticeable, which confirms the physical validity of the analytical model. The asymptotic decrease of □h with power as □$^{-0.5}$ is directly derived from the □$^{0.5}$ dependence observed in the □□□□ (□) curves shown in Fig. 13. This behavior of □h with power can be attributed to the nonlinearity phenomenon resulting from the temperature dependence of □□(T) and □□(T).

The simulation results for the thermal resistance □h (□) in short-channel FDSOI MOSFETs with different boundary conditions (□ = □□□ at source and □ = □□□+□□ at drain, see Fig. 3) were compared to those obtained in long-channel devices. The results, shown in Fig. 15, reveal that the □h (□) curves for short-channel devices closely resemble those for long-channel devices. This suggests that, despite the significant degradation of drain current in short devices due to the reduction in mobility caused by the saturation velocity effect, the thermal resistance remains largely unchanged
<figure><img src="image_13.png" /><figcaption>Figure 13: Variations of maximum temperature rise □□□□□□ with power □□ as obtained by (a) numerical simulations and (b) analytical model of Eq. (A7) for various ambient temperatures (long channel case FDSOI MOSFET, $t_{□1} = 4$nm, $t_{□2} = 10$nm, $t_{□} = 6$nm, □ = 30nm, □1 = 1V, □□ = 0 to 0.125V, □□ = 25K).</figcaption></figure>

<figure><img src="image_14.png" /><figcaption>Figure 14: Variations of thermal resistance □:h with power □□ as obtained by (a) numerical simulations and (b) analytical model of Eqs (A6) & (A7) for various ambient temperatures (long channel case FDSOI MOSFET, $t_{□1} = 4$nm, $t_{□2} = 10$nm, $t_{□} = 6$nm, □ = 30nm, □1 = 1V, □□ = 0 to 0.125V, □□ = 25K).</figcaption></figure>

at constant power. The reason for this observation is likely because the heat flows in the device are primarily governed by the phonon-originated thermal conductivities □□□(□) and K□□(□), which are not significantly influenced by the electronic transport characteristics.
<figure><img src="image_15.png" /><figcaption>Figure 15: Variations of thermal resistance $R_h$ with ambient temperature $T_a$ as obtained by numerical simulations for long (solid lines) and short (symbols) channel case FDSOI MOSFETs without consideration of thermopower in the electro-thermal transport equations for various drain voltages in short channel case. ($t_{a1} = 4$nm, $t_{a2} = 10$nm, $t_b = 6$nm, $R = 30$nm, $R_h = 1$V, $T_a = 25$K).</figcaption></figure>

## 3.2 Self-Heating Results for “B” BC Configuration

Figure 16a shows the output drain current ($I_D$) versus (V) characteristics obtained by numerical simulation with and without self-heating for various ambient temperatures in a long channel case FDSOI MOSFET with “B” BC configuration. The corresponding relative drain current changes due to self-heating, $I_D/I_n$, are displayed in Fig. 16b. It is worth noting that the impact of self-heating on the drain current amplitude is much larger in this “B” BC configuration than in “BSDG” BC case (see Fig. 7). This is due to the fact that, as can be seen from Fig. 17 where are reported the $R_h$ (R) and $I_D$ (I) characteristics for various temperatures, the temperature rise $T_a$ and the thermal resistance $R_h$ are about 10 times larger than those found in the “BSDG” BC configuration (see Figs 9 and 10). It should be mentioned that when the simulated self-heating temperature rise ($T_a$) is renormalized to the same device width, the amplitudes depicted in Fig. 17 reasonably align with experimental data obtained from real FDSOI MOS transistors [31]. This alignment strongly suggests that the primary heat flow in FDSOI devices is limited by the thermal resistance of the BOX (Buried Oxide) layer.

In Fig. 18, the thermal resistance ($R_h$) variations with ambient temperature ($T_a$) are presented for different drain voltage ($V$) values in the “B” BC configuration of a long channel case FDSOI MOSFET. The thermal resistance values are obtained through numerical simulation and are represented by symbols on the graph. The behavior of the thermal resistance variations in the “B” BC configuration is similar to that observed in the “BSDG” BC configuration (see Fig. 11). However, the $R_h$ values in the “B” BC configuration are approximately ten times larger, as mentioned earlier.
<figure><img src="image_16.png" /><figcaption>Figure 16: a) Temperature dependence of (a) $V_D$ (V) output characteristics obtained by numerical simulations with (solid lines) and without (dashed lines) SHE. (b) Corresponding relative drain current change $I_D/I$ (V) due to SHE ("B" BC configuration, long channel case FDSOI MOSFET, $t_{ON1} = 4$ nm, $t_{ON2} = 10$ nm, $t_{OFF} = 6$ nm, $V_{GS} = 30$ nm, $V_{DS1} = 1$ V, $V_{DS2} = 25$ K).</figcaption></figure>

<figure><img src="image_17.png" /><figcaption>Figure 17: Temperature dependence of (a) $V_{DS1}$ (V) characteristics and (b) $V_{DS2}$ (V) characteristics as obtained by numerical simulations without consideration of thermopower in the electro-thermal transport equations ("B" BC configuration, long channel case FDSOI MOSFET, $t_{ON1} = 4$ nm, $t_{ON2} = 10$ nm, $t_{OFF} = 6$ nm, $V_{GS} = 30$ nm, $V_{DS1} = 1$ V, $V_{DS2} = 25$ K).</figcaption></figure>

This disparity can be attributed to the fact that in this configuration, the heat flow is primarily limited by the thermal resistance of the BOX (Buried Oxide) layer. The graph provides an understanding of how the thermal resistance changes with ambient temperature for different drain voltages, high-
lighting the impact of the “B” BC configuration and the influence of the BOX thermal resistance on
the heat dissipation in the FDSOI MOSFET.

<figure><img src="image_18.png" /><figcaption>Figure 18: Variations of thermal resistance $R_h$ with ambient temperature $T_a$ as obtained by numerical simulations (symbols) and with model $R_{hα}$ ($T_a$, $R_{hαα}$) of Eqs (B3) & (B4) (dashed lines) for various drain voltage values (“B” BC configuration, long channel case FDSOI MOSFET, $t_{α1} = 4$nm, $t_{α2} = 10$nm, $t_{αα} = 6$nm, $R_{hα} = 30$nm, $R_{hα1} = 1$V, $R_{hαα} = 25$K).</figcaption></figure>

In the “B” BC configuration, a similar approach is followed as in the “BSDG” BC case to develop
an analytical model. The simplified thermal resistance equivalent circuit depicted in Fig. 19a is
utilized in this configuration. In this case, the heat flow due to self-heating (SHE) is limited by
the combined effect of $R_{hααα}$ (silicon resistance) and $R_{hαααα}$ (BOX thermal resistance). The temper-
ature division between these resistances is expressed by Eq. (B3). The entire thermal resistance,
denoted as $R_{hα}$ ($T_a$, $R_{hαα}$), is computed by solving Eqs (B3) and (B4) in a self-consistent manner.
The variations of $R_{hα}$ ($T_a$, $R_{hαα}$) are then calculated using the $R_{hαααα}$ values obtained from the
numerical simulations. These calculated variations are presented in Fig. 18 as solid lines. It is
important to highlight that the analytical model and the simulation results exhibit good agreement,
indicating that the model accurately captures the behavior of the thermal resistance. Additionally,
the results suggest that $R_{hα}$ is primarily influenced by the BOX thermal resistance. Actually,
$R_{hα}$ ($T_a$, $R_{hαα}$) can well be approximated by $R_{hαααα}$ ($T_a$, $R_{hαααα}$) since their difference is not ex-
ceeding 10% for ambient temperatures below 0.03K.

Figures 20 and 21 illustrate the self-heating performances obtained using the analytical models
described in Eqs (A7) and (B5) for the FDSOI MOSFET device, considering very low ambient
temperatures and dissipated powers. In Fig. 20, the variations of the self-heating temperature rise
($R_{hαααα}$) with the dissipated power ($R_{hα}$) are compared between the “worst” and “best” thermaliza-
tion cases, represented by the “B” and “BSDG” BC configurations, respectively. As previously
mentioned, in the “worst” case where heat evacuation is primarily limited by the BOX thermal
resistance, the self-heating temperature rise is approximately ten times larger than in the “best”
<figure><img src="image_19.png" /><figcaption>Figure 19: a) Schematic of thermal resistance equivalent circuit used for the analytical modelling of effective thermal resistance in the FDSOI structure for “B” BC configuration. b) Formula of elementary thermal resistances in BOX and silicon layer in the FDSOI structure.</figcaption></figure>

<figure><img src="image_20.png" /><figcaption>Figure 20: Comparison of SHE temperature rise (□□□□) variations with dissipated power (□□ as obtained from analytical modelling for “B” (left) and “BSDG” (right) BC configurations (FDSOI MOSFET, t□□1 = 4nm, t□□2 = 10nm, t□□ = 6nm, □ = 30nm).</figcaption></figure>

case. Figure 21 displays the variations of the self-heating temperature rise (□□□□) and the device temperature (□□□□ = □□+□□□□) with ambient temperature for different dissipated powers in the “worst” thermalization case. The graph clearly indicates that as the ambient temperature decreases to very deep cryogenic levels, the device temperature (□□□□) becomes more influenced
by the dissipated power. This highlights the critical importance of controlling the dissipated power for proper operation of FDSOI MOSFETs at extremely low cryogenic temperatures. These figures provide valuable insights into the self-heating behavior of the FDSOI MOSFETs under different thermalization scenarios, emphasizing the impact of the BC configuration and the necessity of managing dissipated power at deep cryogenic temperatures for reliable device performance.

<figure><img src="image_21.png" /><figcaption>Figure 21: Variations with ambient temperatures (left) of SHE temperature rise (right) for various dissipated power (Pd) as obtained from analytical modelling for “B” BC configurations (FDSOI MOSFET, $t_{on} = 4$nm, $t_{off} = 10$nm, $t_{on} = 6$nm, $t_{off} = 30$nm).</figcaption></figure>

## 4. SUMMARY AND CONCLUSIONS

In this study, we have conducted TCAD numerical simulations to investigate the self-heating behavior of 30nm FDSOI MOS transistors at extremely low temperatures. This is the first time such simulations have been performed in this temperature regime. The aim was to evaluate the self-heating temperature rise (□□□□) and thermal resistance (□h) as functions of ambient temperature (□) and dissipated electrical power (□ = I.V), using calibrated values for the thermal conductivities of silicon and oxide. The numerical simulations revealed several important findings. Firstly, the characteristics of the SHE temperature rise, □□□□(□), displayed a sub-linear behavior at sufficiently high dissipated powers, which is consistent with previous experimental results reported in the literature. Additionally, the simulations demonstrated that at very deep cryogenic temperatures, the SHE temperature rise (□□□□) can significantly surpass the ambient temperature more easily. Furthermore, a detailed thermal analysis of the heat flows within the FDSOI structure, considering the non-linear thermal resistances in the silicon channel and front/BOX oxides, was conducted. Based on this analysis and the TCAD simulation data, an analytical model for self-heating effects was developed and calibrated. This analytical model successfully describes the temperature rise due to self-heating and the thermal resistance as function of dissipated power in FDSOI MOS devices operating at ambient temperatures as low as 10mK. Moreover, it is worth noting that this self-heating model physically justifies the simple analytical modelling approach
developed in [32]. Consequently, these TCAD simulations and the analytical modelling provide valuable insights into the self-heating and electro-thermal performance of FDSOI MOS transistors, considering the interplay of ambient temperature and dissipated power. These findings can be particularly useful for cryogenic circuit design, enabling the prediction and optimization of self-heating effects in FDSOI MOS devices.

## 5. ACKNOWLEDGMENT

The authors are grateful to EU H2020 RIA project SEQUENCE (Grant No. 871764) for financial support.

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