# Dependence between drain current saturation level and short-circuit robustness of p-GaN HEMTs

Mohamed Lemine Dedew, Stéphane Lefebvre, Tien Anh Nguyen, T.L. Le, V.

Rustichelli, J. Oliveira, M. Alam, F. Coccetti

► To cite this version:

Mohamed Lemine Dedew, Stéphane Lefebvre, Tien Anh Nguyen, T.L. Le, V. Rustichelli, et al. Dependence between drain current saturation level and short-circuit robustness of p-GaN HEMTs. Microelectronics Reliability, 2025, 171, pp.115794. 10.1016/j.microrel.2025.115794. hal-05235273

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https://hal.science/hal-05235273v1

Submitted on 16 Oct 2025

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<figure><img src="image_1.png" /></figure>

Distributed under a Creative Commons Attribution 4.0 International License
Dependence between drain current saturation level and short-circuit
robustness of p-GaN HEMTs

M.L. Dedew<sup>a,b,*</sup>, S. Lefebvre<sup>c</sup>, T.A. Nguyen<sup>c</sup>, T.L. Le<sup>d</sup>, V. Rustichelli<sup>a</sup>,
J. Oliveira<sup>a</sup>, M. Alam<sup>a</sup>, F. Coccetti<sup>a</sup>

<sup>a</sup> IRT Saint-Exupéry, 3 rue Tarfaya, B612, 31400, Toulouse, France

<sup>b</sup> SATIE, Université Paris-Saclay, ENS Paris-Saclay, 4, avenue des sciences 91190, Gif-Sur-Yvette, France

<sup>c</sup> SATIE, Cnam, 292, rue Saint Martin, 75141, Paris Cedex 03, France

<sup>d</sup> SAFRAN TECH, 1, rue des jeunes bois Châteaufort, 78772, Magny-les-Hameaux, France

**Abstract**

This work presents an experimental investigation of drain current saturation ($I_{D-SAT}$) effect on short-circuit (SC) robustness of 650 V normally-off gallium nitride (GaN) high electron mobility transistors (HEMTs). SC tests were performed at a drain-source voltage ($V_{DS}$) of 400 V, varying parameters such as gate resistance ($R_G$), on-state gate-source voltage ($V_{GS}$), and parasitic source inductance ($L_S$) on the device under test (DUT). As expected, variation on maximum of $I_{D-SAT}$ ($I_{D-SAT-max}$) was observed by varying these parameters. In single shot destructive SCs, components demonstrated a very high robustness, withstanding SC durations of hundreds of microseconds. However, in repetitive SCs of very short durations, components proved extremely fragile, failing after only a few SC cycles, sometimes as few as two cycles. Results suggest that in repetitive SCs, the failure appears to result from a critical dissipated energy ($E_{SC}$) being exceeded depending on several parameters. This critical $E_{SC}$ value also seems to depend on SC pulse width ($t_p$). In one-shot destructive SCs, the cause of failure remains unclear, as no critical $E_{SC}$ or $I_{D-SAT-max}$ threshold was observed. However, it is important to note that, in destructive SCs, a correlation between $I_{D-SAT-max}$ and SC withstanding time (SCWT) has been identified.

**1. Introduction**

Compared to silicon, wide-bandgap semiconductors such as GaN are more promising for power electronics applications due to their intrinsic properties such as wide bandgap energy, high-switching frequency, high charge carrier mobility, high breakdown critical field, and good thermal conductivity [1]. Despite GaN HEMTs are emerging as a potential choice for automotive and aerospace industries [2], questions remain regarding their SC robustness, a factor that may limit their diffusion in the market.

The root cause of GaN HEMTs failures during SC conditions is still not fully understood, leading to conflicting explanations. Some suggest that the cause is the increased temperature due to power dissipation, which is inversely proportional to the SCWT [3]. Differently, [4] attributes the failures to a high electric field due to hot electron trapping in the aluminum-gallium nitride layer. In [5], it is

suggested that at lower $V_{DS}$, failures with SCWT (>1µs) are due to device temperature increase, while the physical mechanism of the failure with shorter SCWT is still under investigations. Despite all these hypotheses, there are papers asserting that the failure of GaN HEMTs under SC conditions is primarily linked to the initial value of $I_{D-SAT}$, as proposed in [6] and in [7]. In these papers, authors attempted to limit $I_{D-SAT}$ to improve component robustness, either by optimizing the gate drive circuit as in [6] or by directly inserting a SC current limiter, as in [7].

Here, the subject is approached differently. The objective of this paper is to investigate whether $I_{D-SAT}$ and especially $I_{D-SAT-max}$ truly affects the robustness of GaN HEMT under SC operations. As a reminder, in this paper, $I_{D-SAT-max}$ is defined as the maximum level of the SC current, excluding the high current values at failure. Similarly, $I_{D-SAT}$ defines the saturation of drain current during SC phase. Thus, $I_{D-SAT-max}$ is the maximum level of $I_{D-SAT}$ before failure.
<figure><img src="image_2.png" /><figcaption>Fig. 1. Electric schematic of the short-circuit test bench. (a) For a DUT mounted on a common source daughterboard. (b) For a DUT mounted on a separate Kelvin source daughterboard.</figcaption></figure>

In this work, the DUTs used are commercial normally-off 650 V, 50 mΩ, 30 A, Schottky p-GaN HEMTs, all from the same batch.

In section 2, the experimental setup is presented. Section 3 presents the design of experiments followed to evaluate the SC robustness at varied $I_{D-SAT-max}$. Section 4 presents the experimental results and section 5 discusses those results and presents a failure mechanisms analysis.

## 2. Experimental setup

The electric schematic of the SC test bench used in this work is shown in Fig. 1. It consists of a high-voltage power supply, a capacitive ballast, and a protective insulated gate bipolar transistor (IGBT) connected in series with the DUT and a coaxial shunt (15 mΩ - 1200 MHz) for measuring the SC current

($I_D$). To measure $V_{DS}$, a Tektronix P5100A 500 MHz 100:1 voltage probe captures the potential difference between the drain and the DUT's power source. The gate voltage ($V_G$) and the driver output voltage ($V_{Driver}$) are measured relative to the reference voltage point of power source or Kelvin source according to the daughterboard configuration, using two LeCroy PP018 500 MHz 10:1 voltage probes. The gate leakage current ($I_G$) is estimated by determining the voltage drop across $R_G$. A photo of the test setup is provided in Fig. 2.

DUTs can be driven in two configurations: by applying a positive voltage either between the gate and the main power source (see Fig. 1(a)), or between the gate and the separate Kelvin source ($S_K$) (see Fig. 1(b)). To enable testing in both configurations, two specialized daughterboards were especially designed and fabricated: one with a
common source and the other one with a separate $S_K$, as illustrated in Fig. 3. On both daughterboards, the DUT is mounted alongside its driver and $R_G$. For DUTs mounted on a separate $S_K$ daughterboard, $V_G$ and $V_{Driver}$ measurements are taken with reference voltage to the Kelvin source. In this case, throughout this paper, we refer to $V_{GSK}$ as the voltage between the gate and the separate Kelvin source.

The bench allows to conduct type I SC tests (meaning that the DUT is subjected to a SC stress while it was in the OFF-state). Fig. 4 presents the driving signals during SC testing. First, the protective IGBT is activated by applying a positive voltage between the IGBT's gate and its emitter ($V_{GE}$). Once the IGBT is ON, the bus voltage ($V_{bus}$) appears across the DUT drain and source while the DUT remains OFF. After a delay time, the DUT is switched ON by applying a positive $V_{GS}$ (or $V_{GSK}$), initiating a SC for a well-defined $t_p$. The delay time between applying drain bias voltage to the DUT and initiating the SC is not actively controlled, leading to a fluctuation of several seconds.

<figure><img src="image_3.png" /><figcaption>Fig. 2. Photograph of the SC test bench.</figcaption></figure>

<figure><img src="image_4.png" /><figcaption>Fig. 3. Photographs of daughterboards, with common source (left), and separate Kelvin source (right).</figcaption></figure>

<figure><img src="image_5.png" /><figcaption>Fig. 4. SC driving signals.</figcaption></figure>

Although the stress of drain bias voltage ($V_{DS}=V_{bus}$ while $V_{GS}=0$ V) during this delay time could impact the maximum level of the SC saturation current, as observed in [1], this bias effect is not studied in this paper. However, unlike the SC driving signals used in this work, an alternative method is used in [1] where the protective IGBT is initially in the OFF-state, and the DUT is initially in the ON-state. Due to such configuration, the DUT remains a certain time under a positive gate bias of $V_{GS}$, before being triggered to a SC fault. The authors observed that the longer the delay during which the DUT was stressed by applying a positive gate bias before triggering the SC, the more the $I_{D-SAT-max}$ decreases. Beyond a certain limit of this delay, $I_{D-SAT-max}$ no longer decreases and tends towards a stable value.

### 3. Design of experiments

At a constant $V_{DS}$ voltage, the parameters influencing the level of $I_{D-SAT-max}$ are primarily the device parasitic source inductance ($L_S$) (whether $S_K$ is separated or not), the gate resistance $R_G$, and the on-state gate-source voltage $V_{GS}$.

In this paper, the protective IGBT is initially in ON-state, and the DUT is in OFF-state (SC type I), as shown in Fig. 4. The variation of the parameters $L_S$, $R_G$, and $V_{GS}$ is performed during this study.

It is important to note that the DUTs are designed to be driven exclusively through their separate $S_K$ with the lowest possible $R_G$. Thus, testing a component under a critical condition such as a SC to evaluate its robustness should ideally be done, in our case, using a separate $S_K$ daughterboard with $R_G$ around 1 Ω to minimize parasitic inductance and preserve the DUT's switching speed. However, since the goal of this study is to assess the effect of $I_{D-SAT-max}$ on the DUTs' robustness under SC conditions and to better understand their failure mechanisms, some DUTs were also tested by applying a positive voltage directly between their gates and main power sources. Other DUTs were tested with varied $R_G$, noting that the lowest $R_G$ achievable in our case, using this test bench, without causing destructive oscillations was 10 Ω. Below this minimum value of $R_G$, the bench used in this work exhibits destructive undesirable oscillations.

In this study, SC testing was conducted on 27 DUTs in two phases. In the first phase, 14 DUTs were subjected to repetitive SC tests, with variations in the above-mentioned parameters ($L_S$, $R_G$, $V_{GS}$) to evaluate the effect of $I_{D-SAT-max}$ variation on SC robustness. The second phase focused on destructive
SC testing to analyze the component behavior under extended SC durations during which 13 DUTs were tested in one shot destructive SC. The DUTs are numbered from 1 to 27, including those tested under repetitive SCs (DUT1 to DUT14) and those tested in a single destructive SC (DUT15 to DUT27).

Typically, end users specify a V<sub>DS</sub> equal to 2/3 of the nominal breakdown voltage for SC qualification testing (433 V). Furthermore, in the literature, most articles addressing the SC robustness of 650 V normally-off GaN HEMTs conduct SC tests at V<sub>DS</sub>=400 V. Therefore, all SC tests presented in this study were conducted at room temperature, with V<sub>DS</sub> maintained at 400 V. The dissipated energy (E<sub>SC</sub>) is calculated by integrating the product of I<sub>D</sub> and V<sub>DS</sub> over time. In the case of a non-destructive SC, the integration limits are set from the moment when I<sub>D</sub> exceeds 5 A (lower limit) to when I<sub>D</sub> falls back below 5 A (upper limit). For a destructive SC, the integration limits are set from the moment I<sub>D</sub> exceeds 5 A (lower limit) to the SCWT (upper limit). The SCWT is defined as the point 10 ns before the moment when I<sub>D</sub> begins to increase drastically, indicating failure.

<table><caption>Table 1
Test conditions and the number of DUTs for each varied parameter in repetitive SC testing</caption><thead><tr><th>Varied parameter</th><th>SC tests conditions</th><th>Number of DUTs</th></tr></thead><tbody><tr><td>L<sub>S</sub><br>[Common source/separate S<sub>K</sub> daughterboard]</td><td>V<sub>DS</sub>=400 V; V<sub>GS</sub>=5 V; R<sub>G</sub>=10 Ω; t<sub>p</sub>=500 ns</td><td>4<br>(DUT1; DUT2; DUT3; DUT4)</td></tr><tr><td>R<sub>G</sub><br>[10 Ω; 47 Ω]</td><td>V<sub>DS</sub>=400 V; V<sub>GS</sub>=5 V; Separate S<sub>K</sub> daughterboard; t<sub>p</sub>=500 ns</td><td>4<br>(DUT3; DUT4; DUT5; DUT6)</td></tr><tr><td rowspan="2">V<sub>GS</sub><br>[4 V- 7 V, with steps of 0.5 V]</td><td rowspan="2">V<sub>DS</sub>=400 V; Separate S<sub>K</sub> daughterboard; R<sub>G</sub>=10 Ω; t<sub>p</sub>=500 ns</td><td>4<br>(DUT7; DUT8; DUT9; DUT10)</td></tr><tr><td>4<br>(DUT11; DUT12; DUT13; DUT14)</td></tr></tbody></table>

### 3.1. Repetitive SC tests with variable L<sub>S</sub>, R<sub>G</sub>, and V<sub>GS</sub>

This section details the conditions for repetitive SC tests conducted with varying L<sub>S</sub>, R<sub>G</sub>, and V<sub>GS</sub>. Only one of these parameters is varied at a time,

while the other two remain unchanged (see Table 1). The interval between consecutive SC cycles is not strictly controlled and ranges from one to several minutes, which is assumed to be sufficient for the component to cool down after each SC stress. We refer to N<sub>f</sub> as the number of SC cycles that a DUT can withstand until failure occurs. To determine whether there is a critical I<sub>D-SAT-max</sub> or a critical E<sub>SC</sub> leading to failure under repetitive SC conditions, we focus exclusively on the maximum I<sub>D-SAT-max</sub> that a DUT can sustain and the maximum E<sub>SC</sub> it can dissipate, regardless of the number of the SC cycle.

#### 3.1.1. Varying L<sub>S</sub>

Varying I<sub>D-SAT</sub> (especially I<sub>D-SAT-max</sub>) by varying L<sub>S</sub>, involves driving the DUT using either a common source daughterboard or a separate S<sub>K</sub> daughterboard. When using the common source daughterboard, a voltage drop occurs in V<sub>GS</sub> at the turn-on of the DUT with the amplitude of the drop given by L<sub>S</sub>·dI<sub>D</sub>/dt (see Fig. 1(a)). Consequently, this decrease in V<sub>GS</sub> at the beginning of the SC pulse reduces I<sub>D-SAT</sub>. In contrast, when using a separate S<sub>K</sub> daughterboard, the DUT is driven directly by V<sub>GSK</sub> and results in a higher I<sub>D-SAT-max</sub>.

To study the impact of L<sub>S</sub>, SC tests were conducted using both common source and separate S<sub>K</sub> daughterboards. Two components were tested with the common source daughterboard and two others with the separate S<sub>K</sub> daughterboard. R<sub>G</sub> was set to 10 Ω, t<sub>p</sub> was set to 500 ns and V<sub>GS</sub> (or V<sub>GSK</sub> when a separate S<sub>K</sub> daughterboard is used) was fixed to 5 V.

#### 3.1.2. Varying R<sub>G</sub>

In this case, SC tests were conducted using two different values of R<sub>G</sub> (10 Ω and 47 Ω), V<sub>GSK</sub> was fixed at 5 V, t<sub>p</sub> was set to 500 ns and only a separate S<sub>K</sub> daughterboard was used. Two components were tested for each R<sub>G</sub> value.

#### 3.1.3. Varying V<sub>GS</sub>

In this case, SC tests were conducted with V<sub>GSK</sub> incremented from 4 V to 7 V (Maximum value allowed by the datasheet). For each DUT, after each SC cycle, V<sub>GSK</sub> is incremented by 0.5 V until failure occurs. In this case, V<sub>GSK</sub><sub>f</sub> refers to the V<sub>GSK</sub> value at which failure occurs. R<sub>G</sub> is set to 10 Ω and only a separate S<sub>K</sub> daughterboard is used. Initially, four DUTs were tested, with t<sub>p</sub> set to 500 ns. However, as will be detailed below, it was observed that I<sub>D</sub> saturation always occurred before 200 ns. Therefore, four additional components were tested with a lower t<sub>p</sub> of 200 ns. The goal was to reduce the dissipated
energy during the SC while ensuring that $I_D$ saturation still occurred.

## 3.2. Destructive SC tests

Due to the extreme fragility of the DUTs under repetitive SC conditions, as will be discussed later, 13 components (DUT15 to DUT27) were tested under single shot destructive SC conditions to assess whether they maintained this fragility during one-shot long-duration SC events, and to compare the behaviour of the DUTs between repetitive and destructive SC tests. These components were tested using separate $S_K$ daughterboards, with $V_{GSK}$ maintained at 5 V, $R_G = 10 \ \Omega$, and $t_p = 2$ ms.

# 4. SC results and discussion

## 4.1. Repetitive SC tests with variable $L_S$, $R_G$, and $V_{GS}$

### 4.1.1. Repetitive SC tests with variable $L_S$

Firstly, this study investigated the impact of $L_S$ on the robustness of Schottky p-GaN HEMT during SC stress. Two components (DUT1 and DUT2) were tested with common-source daughterboards (resulting in higher $L_S$). These DUTs demonstrated high robustness, withstanding multiple SC cycles, reaching an $I_{D-SAT-max}$ of approximately 106 A. DUT1 failed on the tenth SC cycle, while DUT2 endured 25 SC cycles without failure. Fig. 5 shows the SC waveforms for DUT1. Two other components (DUT3 and DUT4) were tested using separate $S_K$ daughterboards (so a lower $L_S$ resulting in a higher $I_{D-SAT-max}$). This time, these components were much more fragile, failing only on the second SC cycle; however, they reached significantly higher $I_{D-SAT-max}$ levels than the common-source tested components, with $I_{D-SAT-max}$ ranging from 120 A to 130 A. Fig. 6 shows the SC waveforms for DUT3. It can be observed that with a separate $S_K$, the component switches much faster than with a common source. This difference in switching speed matches with what is seen in [8], which compares the switching speed of silicon carbide devices with a common source and a separate $S_K$.

<table><caption>Table 2
Summary of repetitive SC tests results at variable $L_S$</caption><thead><tr><th rowspan="2"></th><th colspan="2">Common source</th><th colspan="2">Separate S<sub>K</sub></th></tr><tr><th>DUT1</th><th>DUT2</th><th>DUT3</th><th>DUT4</th></tr></thead><tbody><tr><th>I<sub>D-SAT-max</sub><br>(cycle1)</th><td>108.8</td><td>106.9</td><td>132.1</td><td>124.6</td></tr></tbody></table>

<table><thead><tr><th>(A)</th><th></th><th></th><th></th><th></th></tr></thead><tbody><tr><td>E<sub>SC</sub><br>(cycle1)</td><td>18.7</td><td>18</td><td>21</td><td>20.2</td></tr><tr><td>(mJ)</td><td></td><td></td><td></td><td></td></tr><tr><td>N<sub>f</sub></td><td>10</td><td>&gt;25</td><td>2</td><td>2</td></tr></tbody></table>

<figure><img src="image_6.png" /><figcaption>Fig. 5. DUT1 tested at SC with common-source daughterboard. Test conditions: $V_{DS}=400$ V; $V_{GS}=5$ V; $R_G=10 \ \Omega$; $t_p=500$ ns.</figcaption></figure>

<figure><img src="image_7.png" /><figcaption>Fig. 6. DUT3 tested at SC with separate $S_K$ daughterboard. Test conditions: $V_{DS}=400$ V; $V_{GSK}=5$ V; $R_G=10 \ \Omega$; $t_p=500$ ns.</figcaption></figure>

Table 2 summarizes the SC test results for varying $L_S$. It can be observed that $I_{D-SAT-max}$ is significantly lower at high $L_S$ compared to low $L_S$. Additionally, as $I_{D-SAT-max}$ decreases, $N_f$ (the number of SC cycles to failure) increases.

### 4.1.2. Repetitive SC tests with variable $R_G$

The second parameter varied to adjust $I_{D-SAT-max}$ is $R_G$. SC tests were conducted with two $R_G$ values: 10 Ω and 47 Ω. The previous section presented results from two DUTs tested at $R_G=10 \ \Omega$ using separate $S_K$ daughterboards. In this section, two additional components (DUT5 and DUT6) were tested with $R_G=47 \ \Omega$. Results showed that increasing $R_G$ reduces $I_{D-SAT}$ and allows the component to withstand more SC cycles. Table 3 summarizes the SC test results conducted at variable $R_G$.
Like $L_S$, $R_G$ has also been found to directly influence the switching speed of components. In other words, if $L_S$ or $R_G$ decreases, the switching speed increases, which in turn raises the maximum saturation current level of the component. This can be explained as follows:

* With a lower $L_S$, the transient voltage drop of $V_{GS}$ at the very beginning of the SC stress is smaller compared to that with a higher $L_S$, resulting in a higher $I_{D-SAT-max}$.

* With a lower $R_G$, the gate capacitance charges more quickly, meaning that $V_{GS}$ reaches its defined level faster, allowing the component to switch more quickly at a lower $R_G$. Besides, we believe that an electro-thermal effect may explain why components with higher $R_G$ tend to exhibit the lowest $I_{D-SAT}$ levels.

<table><caption>Table 3 Summary of repetitive SC tests results at variable $R_G$</caption><thead><tr><th rowspan="2"></th><th colspan="2">R<sub>G</sub>=10 Ω</th><th colspan="2">R<sub>G</sub>=47 Ω</th></tr><tr><th>DUT3</th><th>DUT4</th><th>DUT5</th><th>DUT6</th></tr></thead><tbody><tr><td>I<sub>D-SAT-max</sub><br>(cycle1)<br>(A)</td><td>132.1</td><td>124.6</td><td>112.7</td><td>112.4</td></tr><tr><td>E<sub>SC</sub><br>(cycle1)<br>(mJ)</td><td>21</td><td>20.2</td><td>18.7</td><td>18.5</td></tr><tr><td>N<sub>f</sub></td><td>2</td><td>2</td><td>6</td><td>7</td></tr></tbody></table>

As noted in the previous section, despite the substantial variations in $I_{D-SAT-max}$, the $E_{SC}$ value leading to failure remains close to the values obtained at variable $L_S$.

### 4.1.3. Varying $V_{GS}$

The third parameter varied to study its effect on $I_{D-SAT}$ is $V_{GS}$. In this section, $V_{GSK}$ is increased from 4 V to 7 V in steps of 0.5 V, $R_G$ is set to 10 Ω.

Firstly, four components (DUT7, DUT8, DUT9, DUT10) were tested at $t_p$ set to 500 ns. One component (DUT7) failed on the 3rd cycle at $V_{GSK-f}=5$ V, two components (DUT8 & DUT9) failed on the 4th cycle at $V_{GSK-f}=5.5$ V, and one component (DUT10) failed on the 5th cycle at $V_{GSK-f}=6$ V. As shown in Fig. 7, $I_{D-SAT-max}$ continues to increase progressively with rising $V_{GSK}$ until failure occurs. In the same figure, it can also be observed that current saturation consistently occurs within the first 200 ns.

To determine whether the failure is due to a critical current saturation level or a critical dissipated energy level, four additional components (DUT11, DUT12, DUT13, DUT14) were tested with a shorter pulse width, $t_p=200$ ns. This condition ensures that

the pulse duration is long enough to ensure current saturation and that the saturation level increases after each cycle while reducing the dissipated energy during the SC pulse (see Fig. 8). In this configuration ($t_p=200$ ns), two components (DUT11 & DUT12) failed on the 6th cycle at $V_{GSK-f}=6.5$ V and two (DUT13 & DUT14) failed on the 7th cycle at $V_{GSK-f}=7$ V. Table 4 summarizes the results obtained with varying $V_{GSK}$.

<figure><img src="image_8.png" /><figcaption>Fig. 7. DUT10 tested at SC with separate $S_K$ daughterboard. Test conditions: $V_{DS}=400$ V; $V_{GSK}=[4$ V; 7 V] with steps of 0.5 V; $R_G=10$ Ω; $t_p=500$ ns.</figcaption></figure>

<figure><img src="image_9.png" /><figcaption>Fig. 8. DUT13 tested at SC with separate $S_K$ daughterboard. Test conditions: $V_{DS}=400$ V; $V_{GSK}=[4$ V; 7 V] with steps of 0.5 V; $R_G=10$ Ω; $t_p=200$ ns.</figcaption></figure>

Since $I_{D-SAT-max}$ level continues to increase progressively as $V_{GSK}$ increases until failure occurs, if we assume there is a critical $I_{D-SAT-max}$, it would correspond to the last cycle ($N_f$). Besides, given that components do not always fail at the same time during the SC pulse, and if we assume there is a critical $E_{SC}$, it would correspond to the second-to-last cycle ($N_f-1$). In any case, the energy of the last cycle is always lower than that of the second-to-last cycle.

At cycle $N_f$, the four components tested at $t_p=500$ ns had an average $I_{D-SAT-max}$ ($I_{D-SAT-max-av}$) of 132.6 A, with an absolute maximum deviation from the mean value ($|\Delta I_{D-SAT-max}|$) of 6.9%. For these
same components, the average $E_{SC}$ value ($E_{SC-av}$) at cycle $N_f-1$ was 19.2 mJ, with a maximum absolute deviation ($|\Delta E_{SC}|$) of 3.7% from the mean.

Meanwhile, the four components tested at $t_p=200$ ns reached an $I_{D-SAT-max-av}$ at cycle $N_f$ of 161.5 A, with a $|\Delta I_{D-SAT-max}|$ of 2.1%. The $E_{SC-av}$ at cycle $N_f-1$ for these components was 9.6 mJ, with $|\Delta E_{SC}|$ of 2.4% from the mean.

In this case, given that $E_{SC}$ and $I_{D-SAT-max}$ are relatively very close to their average values at a given $t_p$, this could suggest that, in the case of repetitive short-duration SCs, failure is due to a critical $E_{SC}$ and a critical $I_{D-SAT-max}$, which depend on the SC pulse width $t_p$. This hypothesis will be discussed in §5.

<table><caption>Table 4
Summary of repetitive SC tests results at variable $V_{GSK}$ (at different $V_{GSK_f}$, gate to source voltage leading to failure)</caption><thead><tr><th>DUT<br>n°</th><th>I<sub>D-SAT-max</sub><br>@ N<sub>f</sub> (A)</th><th>Esc<br>@<br>N<sub>f</sub>-1<br>(mJ)</th><th>Esc_av<br>@ N<sub>f</sub>-1<br>(mJ)</th><th>t<sub>p</sub><br>(ns)</th><th>V<sub>GSK_f</sub><br>(V)</th></tr></thead><tbody><tr><td>7</td><td>123.4</td><td>18.4</td><td rowspan="3">19.2</td><td rowspan="3">500</td><td>5</td></tr><tr><td>8</td><td>137.7</td><td>19.7</td><td>5.5</td></tr><tr><td>9</td><td>135.2</td><td>19.5</td><td>5.5</td></tr><tr><td>10</td><td>134.1</td><td>19</td><td></td><td></td><td>6</td></tr><tr><td>11</td><td>162.9</td><td>9.8</td><td rowspan="3">9.6</td><td rowspan="3">200</td><td>6.5</td></tr><tr><td>12</td><td>164.4</td><td>9.9</td><td>6.5</td></tr><tr><td>13</td><td>160.5</td><td>9.5</td><td>7</td></tr><tr><td>14</td><td>158.1</td><td>9.4</td><td></td><td></td><td>7</td></tr></tbody></table>

## 4.2. Destructive SC tests

The results presented above indicate that the components are highly fragile under repetitive short-duration SCs, able to dissipate only millijoule-level energies with very low SC durations, as low as 200 ns with a failure which appears all the more quickly (even from the second cycle) as the saturation current is high. To assess the robustness of these components in single-event destructive SC testing, 13 components mounted on separate $S_K$ daughterboards were tested under single-shot SC conditions. The following conditions were used: $V_{GSK}=5$ V, $R_G=10$ Ω, and long SC duration programmed $t_p=2$ ms. Unlike those tested under repetitive SC conditions, the components subjected to single-event destructive SC testing demonstrated extreme robustness, withstanding several hundred

microseconds, as illustrated in Fig. 9. The results of the single-event destructive SC tests are summarized in Table 5. The SCWT varied from 492 µs to 825 µs, with an average duration of 640 µs. One might wonder why components are extremely fragile under repetitive short-duration SCs but exceptionally robust under single shot long-duration destructive SCs. This suggests that there may be multiple possible failure mechanisms at play.

<figure><img src="image_10.png" /><figcaption>Fig. 9. DUT15 tested at single-event destructive SC with a SCWT of 852.8 µs and an $I_{D-SAT-max}$ of 111.2 A.</figcaption></figure>

<table><caption>Table 5
Summary of single-event destructive SC tests results on 13 tested devices</caption><tr><td>I<sub>D-SAT-max-av</sub> (A)</td><td>119.2</td></tr><tr><td>|ΔI<sub>D-SAT-max</sub>| (%)</td><td>6.7</td></tr><tr><td>E<sub>SC-av</sub> (J)</td><td>1.5</td></tr><tr><td>|ΔE<sub>SC</sub>| (%)</td><td>16.6</td></tr><tr><td>SCWT<sub>av</sub> (μs)</td><td>640.1</td></tr><tr><td>|ΔSCWT| (%)</td><td>33.2</td></tr></table>

## 5. Failure mechanisms

In short-duration repetitive SC testing, all components tested in this study at constant $V_{GS}$ showed a slight decrease in $I_{D-SAT-max}$ as the number of SC cycles increased. This suggests that the SC stress itself induces a change in the component's internal structure or material characteristics due to the cumulative SC stress. This gradual decline of $I_{D-SAT-max}$ after each SC cycle can be seen in Table 6, which presents the SC data measured at each cycle for two DUTs seen above (DUT3 and DUT5), tested with separate $S_K$ daughterboard at $V_{GSK}=5$ V and $t_p=500$ ns, one with $R_G=10$ Ω and the other with $R_G=47$ Ω.

Similarly to the assumptions made above with variable $V_{GS}$ (§4.1.3), in the case of constant $V_{GS}$ where $I_{D-SAT-max}$ decreases as the number of SC cycles increases, if the failure is due to a critical $E_{SC}$ or $I_{D-SAT-max}$ level, it would correspond to the $E_{SC}$ and/or $I_{D-SAT-max}$ of the first cycle. For this reason, in
the tables summarizing the results of repetitive SC tests with variable L<sub>S</sub> and variable R<sub>G</sub>, we focus solely on the energy and saturation current of the first cycle (see Table 2 and Table 3). In both cases (variable L<sub>S</sub> and variable R<sub>G</sub>), V<sub>GS</sub> was constant, and t<sub>p</sub> was maintained at 500 ns.

Regarding I<sub>D-SAT-max</sub>, when examining all components tested in this study under repetitive SC conditions (see Table 2, Table 3, and Table 4), it is not clear whether a critical I<sub>D-SAT-max</sub> exists. If we assume the existence of a truly critical I<sub>D-SAT-max</sub> (the maximum I<sub>D-SAT-max</sub> reached by a given DUT), the range be of critical I<sub>D-SAT-max</sub> values would be between 106 A and 138 A for a pulse width of t<sub>p</sub>=500 ns. Since this range is relatively wide, this hypothesis is excluded.

However, when examining the maximum energy dissipated by a given DUT across all components tested under repetitive SC conditions at t<sub>p</sub>=500 ns, it can be observed that this energy consistently remains between 18 and 21 mJ. Thus, for all components tested in this study under repetitive SC conditions, there appears to be a critical E<sub>SC</sub> of approximately 19 mJ for t<sub>p</sub>=500 ns and 9 mJ for t<sub>p</sub>=200 ns.

<table><caption>Table 6
Variation in I<sub>D-SAT-max</sub> and E<sub>SC</sub> after each SC cycle</caption><thead><tr><th>DUT n°</th><th>SC number</th><th>I<sub>D-SAT-max</sub> (A)</th><th>E<sub>SC</sub> (mJ)</th><th>R<sub>G</sub> (Ω)</th></tr></thead><tbody><tr><td rowspan="2">3</td><td>1</td><td>132.1</td><td>21</td><td rowspan="2">10</td></tr><tr><td>2</td><td>129.3</td><td>13.1</td></tr><tr><td rowspan="6">5</td><td>1</td><td>112.7</td><td>18.7</td><td rowspan="6">47</td></tr><tr><td>2</td><td>109.2</td><td>18.1</td></tr><tr><td>3</td><td>108.8</td><td>18</td></tr><tr><td>4</td><td>107</td><td>17.8</td></tr><tr><td>5</td><td>107.5</td><td>17.8</td></tr><tr><td>6</td><td>106.9</td><td>14</td></tr></tbody></table>

To clarify this critical energy hypothesis which aligns with [9], Fig. 10 plots E<sub>SC</sub> of the second-to-last cycle (assumed to be the critical energy) as a function of I<sub>D-SAT-max</sub> of the last cycle for the components tested with varying V<sub>GS</sub>. The figure clearly shows that in very short-duration repetitive SCs, failure is primarily due to a critical energy threshold being exceeded depending on the short-circuit duration or SC pulse width t<sub>p</sub>. This is evident and can be seen for the components tested at t<sub>p</sub>=200 ns (plotted in red), which have a critical energy level around 9.6 mJ, while those tested at t<sub>p</sub>=500 ns (plotted in blue) have a critical energy level of approximately 19 mJ.

<figure><img src="image_11.png" /><figcaption>Fig. 10. E<sub>SC</sub> as a function of I<sub>D-SAT-max</sub> for the DUTs tested with variable V<sub>GSK</sub> (see Table 4).</figcaption></figure>

However, this does not contradict the possibility that this critical energy could be combined with the aging effect of the components. Nevertheless, components tested under repetitive SC conditions with varying V<sub>GS</sub> (DUT11, DUT13 & DUT14) were characterized using the B1505A curve tracer before and after each SC cycle, and no significant parametric drift indicating aging was observed. The characterized parameters were the threshold voltage (V<sub>th</sub>), the drain-source ON resistance (R<sub>DS(on)</sub>), the gate-source leakage current (I<sub>GSS</sub>), and the drain-source leakage current (I<sub>DSS</sub>). It is important to keep in mind that the effect of charge trapping on SC robustness is not studied in this purely experimental observational study. Yet, studies have suggested that this phenomenon could be the origin of premature failures [10].

However, in the case of single-shot SC, Fig. 11 shows that in very long-duration SC, it appears that not only a critical E<sub>SC</sub> nor a critical I<sub>D-SAT-max</sub> seems to be responsible for the failure. It can be hypothesized that failure in this case may result from a combined effect of both parameters. Notably, components with a long SCWT tend to have the lowest I<sub>D-SAT-max</sub>, creating a correlation between these two parameters, as illustrated in Fig. 12. Additionally, the energy dissipated in this case is nearly 100 times higher than that dissipated in very short-duration repetitive SC. This is due to the fact that DUTs in destructive SCs can withstand SC pulses of hundreds of microseconds.
<figure><img src="image_12.png" /><figcaption>Fig. 11. $E_{SC}$ as a function of $I_{D-SAT-max}$ for the DUTs (DUT15 to DUT27) tested in destructive single shot SCs.</figcaption></figure>

<figure><img src="image_13.png" /><figcaption>Fig. 12. $I_{D-SAT-max}$ as a function of SCWT for the DUTs (DUT15 to DUT27) tested in destructive SCs.</figcaption></figure>

## 6. Conclusions

This study investigated the impact of various parameters on the maximum $I_{D-SAT}$ value, to analyze its influence on SC robustness of available 650 V-30 A p-GaN HEMT devices. In conclusion, SC tests conducted at a drain-source voltage of 400 V across varying gate resistance, on-state gate-source voltage, and parasitic source inductance revealed distinct failure characteristics depending on SC conditions. Variations in $I_{D-SAT-max}$ were evident with changes in these parameters. Under repetitive SCs with very short durations, the components showed extreme fragility, often failing after only a few cycles, sometimes in as few as two cycles. Findings indicate that failure in repetitive SCs is likely due to a critical dissipated energy $E_{SC}$ threshold being surpassed, with this $E_{SC}$ threshold appearing sensitive to SC pulse width ($t_p$). It is also clear that the robustness in repetitive SC is strongly dependent on the maximum saturation current ($I_{D-SAT-max}$).

However, in single-shot long duration destructive SC scenarios, components exhibited significant robustness, enduring SC events for hundreds of microseconds. In such scenario, no clear threshold for $E_{SC}$ or $I_{D-SAT-max}$ emerged in destructive SCs, suggesting a combined effect of these factors on failure. Additionally, a correlation was observed between $I_{D-SAT}$ and SCWT.

Finally, future failure physics analyses linked to charge trapping or tunneling effects studies will have to be implemented to analyze and explain the experimental results discussed above.

## Acknowledgements

This work was carried out in the framework of the IRT Saint Exupery's project GANRET (GaN Reliability Evaluation for Transport). We acknowledge the financial support from the GANRET's industrial and academic members and the French government under the France 2030 program under the reference ANR-10-AIRT-01. GANRET industrial members: ALTER Technology, STMICROELECTRONICS, AIRBUS DEFENCE AND SPACE, AIRBUS SAS, SAFRAN ELECTRONICS & DEFENSE, THALES ALENIA SPACE FRANCE, SCHAEFFLER (VITESCO), TRAD, NUCLETUDES, WISE INTEGRATION. GANRET academic members: AMPERE, LAAS, IES, SATIE, CEA, ICAM, DGA, CNES, ESRF.

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