# Special Sessions -Emerging Scope and Design Challenges for Approximate Computing: Optimizing Accuracy-PPA trade-offs and Beyond

Siva Satyendra Sahoo, Bastien Deveautour, Marcello Traiola, Chongyan Gu, Yun Wu, Aditya Japa, Salim Ullah, Akash Kumar

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Siva Satyendra Sahoo, Bastien Deveautour, Marcello Traiola, Chongyan Gu, Yun Wu, et al. Special Sessions -Emerging Scope and Design Challenges for Approximate Computing: Optimizing Accuracy-PPA trade-offs and Beyond. ESWEEK 2025 - Embedded Systems Week, Tei-Wei Kuo; Andy Pimentel, Sep 2025, TAIPEI, Taiwan. pp.11-20, 10.1145/3742872.375705. hal-05404759

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# Special Sessions - Emerging Scope and Design Challenges for Approximate Computing: Optimizing Accuracy-PPA trade-offs and Beyond

Siva Satyendra Sahoo¹, Bastien Deveautour², Marcello Traiola³, Chongyan Gu⁴, Yun Wu⁴, Aditya Japa⁵, Salim Ullah⁶, Akash Kumar⁶

IMEC, Leuven, Belgium¹, Nantes Université, CNRS, Nantes, France², Univ Rennes, CNRS, Inria, Rennes, France³, Queen's University Belfast, U.K.⁴, Ulster University, Derry, U.K.⁵, Ruhr-Universität Bochum, Germany⁶
siva.satyendra.sahoo@imec.be,bastien.deveautour@univ-nantes.fr,marcello.traiola@inria.fr
{c.gu,yun.wu}@qub.ac.uk,a.japa@ulster.ac.uk,{salim.ullah,akash.kumar}@rub.de

## Abstract

The rapid growth of AI workloads is driving interest in Approximate Computing (AxC) as a means to enable low-cost, energy-efficient inference in resource-constrained systems. By introducing controlled inaccuracies, AxC can deliver substantial gains in power, performance, and area (PPA) while leveraging the inherent error tolerance of many AI models. Achieving this potential requires adapting existing frameworks to support the design and optimization of neural networks with approximate operators. Modern AxC research extends beyond accuracy-PPA trade-offs to address reliability and security, reducing redundancy overheads and exploring the distinctive side-channel implications of approximation. Application-aware approaches, such as those for spiking neural networks, show that tailoring approximation to workload-specific error behavior can surpass generic strategies. This article examines AI-guided design methods and the interplay between efficiency, reliability, and security, highlighting how these interconnected facets can advance embedded and high-performance computing.

## CCS Concepts

* Computer systems organization → Embedded systems.

## Keywords

Approximate Computing, Reliability, Security, Energy, Power/Energy, Edge Computing, Edge AI, Fault Tolerance, Side-channel Attacks

## 1 Introduction

Modern Edge Artificial Intelligence (AI) platforms face stringent Power-Performance-Area (PPA) constraints, challenging traditional accuracy-first design strategies. While techniques such as quantization, precision scaling, and voltage-frequency tuning aim to reduce cost through conservative system-level margins, they often preserve functional exactness and leave significant optimization potential untapped. Approximate Computing (AxC) offers a more aggressive alternative by relaxing computational exactness itself, enabling disproportionate improvements in PPA. Although originally explored for energy-efficiency, AxC holds potential to mature into a broader design paradigm for AI and signal-processing workloads, where bounded inaccuracy can be exploited for system-level efficiency. As illustrated in Fig. 1, increasing approximation allows for lower PPA cost, defining a trade-off frontier between efficiency and error. Yet this frontier is not static—its shape and extent depend heavily on how approximation is applied. Emerging directions—spanning application-aware design, AI-driven exploration, reliability co-design, and security-aware approximation—actively

<figure><img src="image_2.png" /><figcaption>Fig. 1: Approximate Computing: Beyond Accuracy and PPA</figcaption></figure>

reshape and extend this frontier, unlocking new regions of the design space beyond what traditional optimization techniques allow us to explore.

To fully exploit the AxC design space, it is essential to move beyond one-size-fits-all operator libraries and embrace methods tailored to application structure and workload-level error resilience. As highlighted by the ACC-DRIVEN DESIGN and AI-DRIVEN SEARCH arrows in Fig. 1, application-aware design (Section 5) adapts Approximate Operators (AxOs) to domain-specific tolerance, shifting the frontier leftward by reducing required error for a given PPA cost. Complementing this, AI-guided exploration (Section 2) uses learning-based models and evolutionary heuristics to efficiently navigate the vast space of candidate designs, pushing the frontier downward by identifying more efficient solutions. Together, these approaches expand the trade-off space more intelligently than traditional heuristics, yielding designs better aligned with both system constraints and algorithmic robustness.

While AxC offers compelling efficiency gains, its impact on system dependability and trust must be carefully considered. As shown in Fig. 1, reliability constraints (Section 3) limit how far AxC can push PPA savings by bounding approximation to maintain/improve fault tolerance—especially in safety-critical or long-lifetime deployments. At the same time, AxC introduces new security dynamics (Section 4): aggressive approximation may amplify side-channel leakage or produce exploitable error patterns, while moderate, structured approximation can enhance obfuscation and stochastic masking. These reliability and security considerations reshape the design space vertically and orthogonally, respectively, underscoring the need for cross-layer models that can safely and systematically co-opt AxC under real-world constraints.
<figure><img src="image_3.png" /><figcaption>Fig. 2: Approximate arithmetic operator design in FPGAs using selective LUT-pruning [1]</figcaption></figure>

## 2 AI-driven Optimization of Accuracy-PPA Trade-offs

### 2.1 Approximation through Logic Pruning

A key strategy in approximate computing involves pruning redundant or less critical logic elements within arithmetic operators, significantly simplifying computational structures [2]. Logic pruning aims to reduce gate-level complexity by identifying logic paths or components whose contribution to output accuracy is minimal, enabling power and area savings with bounded error overhead. Techniques for pruning include structural analysis [2], simulation-based sensitivity tracking [3], and functional significance heuristics [4], which assess the impact of removing gates or signals on output fidelity. By aggressively reducing the internal logic of operators, pruning can reduce switching activity, logic depth, and overall footprint. However, ensuring that such reductions stay within acceptable application-level accuracy margins remains a challenge, especially for datapaths reused across multiple contexts. Prior research, including methods like EvoApprox [5], has explored evolutionary heuristics to automatically explore this pruning space for logic circuits such as adders and multipliers. Among these approaches, Lookup Table (LUT)-based pruning has emerged as particularly well-suited to Field Programmable Gate Array (FPGA) architectures due to its direct mapping onto fabric resources [2].

FPGAs, relying heavily on LUTs for logic implementation, provide unique opportunities for resource-aware pruning at the operator level. LUTs implement Boolean functions using configuration bits, with input-output mappings hardcoded in SRAM-based truth tables. As illustrated in Fig. 2, pruning the LUT configuration involves selectively invalidating low-impact input combinations (e.g., setting outputs to zero) or collapsing multiple entries to reduce switching or eliminate entire LUTs. These changes directly reduce dynamic power and logic usage. For example, suppose analysis shows certain inputs (e.g., input 6) have a negligible effect on output precision in specific contexts. In that case, these paths can be truncated to simplify the LUT usage without significant loss in accuracy. The annotated figure shows such a case, where entries corresponding to logic combinations are marked redundant and removed. Accurate modeling of the LUT structure and routing behavior is critical here, as the benefits of pruning must translate into measurable improvements in FPGA power, area, and delay. Recent works, such as [1, 2], demonstrate that the LUT-centric pruning strategies enable scalable exploration of approximate arithmetic operators tailored for FPGA targets. Effective LUT-based pruning thus forms a foundation for systematically navigating large approximate design spaces with precision and architectural alignment.

<figure><img src="image_4.png" /><figcaption>Fig. 3: Selection vs Synthesis (a) 2D Convolution using approximate multipliers (b) Approximate operator design space using Synthesis [1] and Selection approaches [5]</figcaption></figure>

### 2.2 Search Space for Approximate Operators

Traditional selection-based AxO design methodologies utilize fixed approximate operators from limited libraries, inherently restricting achievable design optimizations. This is particularly evident in convolution-based workloads such as Conv2D, where a single layer may invoke multiple instances of arithmetic operations like multiplication. As shown in Fig. 3(a), selecting AxOs from a small library (e.g., 13 pre-designed 8-bit multipliers from EvoApprox) provides only a constrained set of trade-offs across each kernel element, limiting the granularity of approximation across spatial dimensions. In a typical 3 × 3 convolution kernel, this results in a fairly large, combinatorial space of 13⁹ possible operator-level mappings – a large design space, yet often insufficient to reach Pareto-optimal designs for specific accuracy-PPA trade-offs. As kernel sizes or operator widths increase, the combinatorial space becomes both under-explored and suboptimal. Furthermore, fixed AxOs often lack tunability to application-specific constraints, leading to either over-conservative or excessively error-prone choices. Given these limitations, synthesis approaches that dynamically generate AxOs tailored to an application become necessary for a comprehensive exploration of the approximation space.

In contrast to selection methods, synthesis approaches dynamically generate approximate operators tailored explicitly to application-specific constraints, enabling deeper optimization of both accuracy and PPA. These approaches allow for fine-grained pruning of logic or LUT resources—capturing a broader spectrum of approximate behaviors not available in pre-built libraries. For example, as shown in Fig. 3(a), synthesizing a Conv2D kernel with 9 independently tunable AxOs can expose vast new design points, each represented by a unique combination of logic pruning or configuration bits. However, this flexibility introduces a significant increase in search complexity: even for moderately sized kernels and operand widths, the design space becomes intractably large for brute-force evaluation. Managing this synthesis-based space necessitates intelligent Design Space Exploration (DSE) strategies. This motivates the use of metaheuristic search methods like evolutionary algorithms, Monte Carlo Tree Search (MCTS), etc., which iteratively evolve candidate solutions using population-based search, or random simulations – efficiently identifying high-quality approximate designs that meet both PPA and error bounds.
<figure><img src="image_5.png" /><figcaption>Fig. 4: Searching for AxOs (a) Genetic Algorithms-based AxO Synthesis (b) Varying BEHAV and PPA estimation time for operator-level and application-specific exploration in [1]</figcaption></figure>

## 2.3 DSE for Approximate Operators

Genetic Algorithms (GA) are commonly employed in AxO optimization due to their robustness and flexibility in navigating complex design spaces [1, 6, 7]. GA-based DSE frameworks explore operator configurations by evolving a population of candidate designs, each represented using binary-encoded LUT usage patterns (as shown in Fig. 4(a)). Through cycles of selection, crossover, and mutation, new generations of approximate operators are synthesized and evaluated to optimize PPA, and behavioral accuracy (BEHAV) metrics. However, the effectiveness of GA is often constrained by the significant computational overhead involved in evaluating each design candidate. This is particularly prominent in operator-rich workloads where the fitness evaluation—comprising logic synthesis, power/timing analysis, and behavioral accuracy estimation—must be repeated for hundreds or thousands of candidates per generation. Prior efforts, such as AppAxO [1] and AxOTreeS [4], highlight this bottleneck, where exhaustive evaluations limit the scalability of the DSE process. As shown in Fig. 4(b), the BEHAV estimation can also increase significantly depending upon the size of the application’s dataset. To mitigate these computational overheads, Machine Learning (ML)-based surrogate models have emerged as an essential adaptation strategy and form part of tools such as AxOSyn [8].

Incorporating ML surrogate models into GA-based exploration significantly accelerates the optimization process. Surrogate models approximate expensive evaluation metrics—such as PPA and BEHAV—with high fidelity and minimal computational cost, enabling rapid assessment of large candidate populations. As illustrated in Fig. 4(a), once a sufficiently accurate surrogate is trained, it replaces full evaluations for most candidates during the evolutionary search, reserving only a small subset for ground-truth validation. Techniques like AppAxO [1] and AxOMaP [6] have demonstrated the effectiveness of this strategy, showing up to 10–50× reduction in total evaluation time without sacrificing solution quality. By providing low-cost, accurate predictions, surrogate models allow deeper search in fewer generations and significantly improve convergence speed.

<figure><img src="image_6.png" /><figcaption>Fig. 5: (a) Using AI/ML methods beyond just regression models for metrics prediction – model/data analysis (b) AI/ML-augmented GA leads to better quality of results [6] (c) Sample search tree in MCTS-based AxO optimization [4]</figcaption></figure>

## 2.4 Advanced AI/ML-based DSE

While traditional surrogate methods effectively accelerate DSE, advanced AI/ML techniques enable deeper insights into AxO behavior. Conventional regression-based surrogates often function as black-box estimators, offering limited interpretability and inflexible adaptation to varying search dynamics. In contrast, modern AI/ML strategies enable a richer characterization of the design space, providing actionable insights into feature impact, operator structure, and the application’s behavioral patterns. For instance, as shown in Fig. 5(a), AI/ML plays multiple roles beyond a fast surrogate. First, it generates candidates: SyFAxO-GeN [9] trains constraint-aware Generative Adversarial Networks (GANs) that directly emit LUT-level FPGA implementations of approximate multipliers, then uses learned estimators to rank them—improving Pareto coverage and reporting up to 49% faster GAN training with negligible accuracy loss versus related generators. This shifts ML from “predictor” to producer in the loop. Second, ML analyzes characterization data to reveal structure (e.g., LUT usage correlations) and then adapts the optimizer. AxOMaP [6] converts such statistics into MIQCP formulations whose solutions warm-start/prune evolutionary search. AxOCS [7] exploits cross-bit-width regularities to supersample larger operators from smaller ones, providing informed seeds before refinement. Together, these steps realize the flow shown in Fig. 5(a).

Fig. 5(b)-(c) illustrate two concrete, complementary search controllers. For GA-based flows (Fig. 5(b)), AI/ML augmentation improves both convergence speed and final quality: AxOMaP reports up to 21% hypervolume gain over GA-only by MIQCP-guided seeding/filtering, while AxOCS uses ML-based supersampling to transfer patterns from 8-bit to larger designs and deliver stronger initial populations for multi-objective search. For tree-based flows (Fig. 5(c)), AxOTreeS [4] formulates synthesis as MCTS guided by learned estimators and problem-specific statistics (e.g., LUT-importance), pruning unpromising branches and focusing rollouts where payoff is likely—achieving up to 1.6× hypervolume improvement vs. vanilla MCTS on tight constraints.
# 3 Balancing Efficiency and Reliability: the Role of Approximate Computing

## 3.1 Motivation and Concepts

Efficiency and reliability are often opposing goals, especially in resource-constrained safety-critical systems, where failures are unacceptable. Designers seek minimal energy, area, and latency, while reliability typically requires spatial, temporal, or data redundancy. Striking the right balance is challenging, particularly in modern neural network (NN) and edge-computing deployments.

AxC improves efficiency by relaxing exactness, deliberately introducing small errors to reduce energy, latency, and area—from circuit-level units to algorithms. This trade-off is acceptable in inherently error-resilient domains such as multimedia, machine learning, and NNs, where minor perturbations rarely harm performance. Beyond efficiency, AxC can enhance resilience by leveraging the natural fault tolerance of some workloads. When combined with techniques like fault-aware training or precision-aware design, it can enable graceful degradation and adaptive responses. While approximation may reduce redundancy and increase vulnerability, research shows that faults and approximations can sometimes mask each other's effects. This has led to *Approximation for Reliability*, where approximation is used to maintain or even improve fault tolerance alongside efficiency gains [10–12].

In the following, we review both general-purpose and domain-specific AxC-based fault-tolerance methods at design-time and runtime, showing how AxC can serve as both a performance booster and a reliability-driven design philosophy.

## 3.2 General-purpose AxC application for fault-tolerance

Conventional fault-tolerant architectures, such as Triple Modular Redundancy (TMR), replicate functional modules and use majority voting to mask faults. While effective, TMR's area, energy, and performance penalties often make it unsuitable for resource-limited systems. Approximate Triple Modular Redundancy (ATMR) reduces these costs by replacing some or all redundant modules with approximate hardware, such as low-power multipliers or adders, while still preserving fault-masking capability. This design-time approach exploits the intrinsic error resilience of workloads such as neural networks, where small deviations in computation are negligible compared to the effects of real faults. The result is a practical balance between fault resilience and resource efficiency [13].

The Quadruple Approximate Modular Redundancy (QAMR) concept extends this idea with a four-module arrangement. Each module is intentionally simplified via approximation, which reduces costs. However, the four modules are *co-approximated* so that for any given output and input, at least three replicas produce the precise value, ensuring single fault masking, exactly like in TMR. By reducing the per-module cost enough, the four approximated modules can take less area, delay, and power than three precise modules. The net result is full TMR-level reliability at a lower cost [14–17]. Compared to ATMR, QAMR improves fault coverage while still operating with fewer resources than TMR. These methods illustrate how design-time AxC can significantly reduce overhead while maintaining high resilience.

Beyond design-time strategies, AxC can enable runtime adaptation of fault tolerance. The hybrid architecture in [18] shows how reconfigurable modules can handle transient and permanent faults by switching between logic blocks. While originally implemented with three accurate combinational logic (CL) blocks, this concept could be expanded by including approximate modules—similar to ATMR—within the reconfiguration pool. The system could then adjust both redundancy and approximation level on the fly: in low-criticality or energy-constrained modes, approximate replicas could be selected to save power; in safety-critical scenarios, accurate replicas could be activated for maximum fault coverage. Such runtime flexibility, when combined with AxC, provides a scalable means to balance performance, energy, and reliability across diverse operating conditions.

## 3.3 Domain-specific AxC application for fault-tolerance

In this subsection, we explore how domain-specific considerations shape the use of AxC for fault tolerance. While the principles apply across many domains, we illustrate them through Deep Neural Networks (DNNs), a class of workloads widely deployed on specialized hardware in edge, embedded, and safety-critical systems. DNNs' high computational demands and constrained deployment environments make them promising candidates for AxC to improve efficiency. However, the interplay between approximation and reliability in such critical settings demands careful, domain-aware design. Although DNNs have some inherent fault resilience due to statistical behavior and architectural redundancy, hardware for DNNs (HW-DNN) remains vulnerable to faults from manufacturing defects, silicon aging, and environmental stress such as heat or ionizing radiation. These faults can cause operational failures with serious consequences in critical applications. As motivated in the previous section, conventional fault tolerance methods like TMR and Error Correcting Codes (ECCs) are effective in general computing but must be adapted to HW-DNNs to remain cost-effective.

A notable design-time solution is the Fault-Aware Training (FAT) framework [19], which improves DNN robustness by injecting hardware fault models into the training process. This allows the network to learn weights that are inherently more resilient to errors caused by approximate or faulty hardware during inference. By anticipating hardware unreliability during training, FAT produces models that require no additional redundancy or protection mechanisms at inference time, thereby offering a cost-effective and hardware-aware approach to enhancing reliability.

Another design-time solution is proposed by Wei et al. in [20], where AxC is combined with selective redundancy to create a fault-tolerant Convolutional Neural Network (CNN) accelerator. Their method leverages approximate arithmetic units, such as multipliers and adders, in error-resilient parts of the network while preserving accuracy in more critical sections through selective duplication and checking. The design includes integrated error detection mechanisms to handle transient or permanent faults, enabling a cost-effective balance between reliability and efficiency. This hybrid architecture demonstrates that strategic use of approximation, when guided by CNN fault sensitivity, can significantly reduce energy and area costs without compromising system dependability.
<figure><img src="image_7.png" /><figcaption>Fig. 6: (a): percentage of masked and benign faults per each campaign [22]. Bold text shows the best performance. (b): focus on critical faults per bit for mul12s_34P.</figcaption></figure>

In contrast to these design-time approaches, the AdAM architecture [21] introduces a runtime-adaptive fault-tolerant multiplier for edge DNN accelerators. AdAM detects faults using leading-one detection logic and dynamically selects between multiple approximate multipliers based on the severity of the fault and the required inference quality. This run-time adaptation allows the system to gracefully degrade precision in the presence of hardware errors, maintaining functional output, and conserving resources. By embedding AxC into a dynamic fault response, AdAM provides a flexible and efficient way to ensure reliable DNN execution in power-constrained or fault-prone environments.

## 3.4 Quantitative Results

To showcase the impact of AxC on fault tolerance in CNNs, we refer to the study conducted in [22], which investigates how different Approximate Multipliers affect the resilience of a CNN accelerator based on systolic arrays under fault conditions. The evaluation uses the LeNet-5 NN architecture trained on the MNIST dataset. The network consists of two convolutional layers, two fully connected layers, and a softmax output layer. Importantly, the network is trained without approximation: all weights and activations are computed using full-precision arithmetic during training. The approximation is introduced only during inference to isolate its effect on fault resilience. Inference is performed on a CNN accelerator implemented using a systolic array architecture. The systolic array is designed with a fixed 8-bit datapath and uses an output-stationary dataflow, where each Processing Element (PE) includes a multiplier and an adder. A total of 36 PEs (6×6 array) are used to parallelize matrix multiplications. The baseline configuration uses exact 8-bit multipliers.

To evaluate the impact of AxC, the exact multipliers in each PE are replaced with an approximate multiplier of [5]. Five multipliers were used, and are listed in Fig. 6(a). Each provides a different trade-off between hardware cost and computational accuracy. These multipliers significantly reduce area, power, and delay, but introduce increasing levels of error in their outputs. Note that the multipliers are designed to operate on 12-bit values, and the authors only used the least significant 8 bits, reducing the performance of the multipliers. Hence, fault resilience is evaluated through a bit-level fault injection campaign, using the framework described in [23]. Each configuration reported in the table was evaluated under identical fault scenarios. Results in Fig. 6(a) show the percentage of injected faults that led to a specific outcome. In particular, we report three outcomes: (i) fault does not impact the final outputs (we refer to this class as masked), (ii) the fault impacts the final outputs but

does not change the CNN top-1 accuracy (we refer to this class as benign), and (iii) the fault changes the CNN accuracy (we refer to this class as critical). The general trend is that approximation does not help or even worsens fault tolerance, i.e., fewer faults are classified as masked and benign, and more lead to critical outcomes w.r.t. the accurate version. However, for mul12s_34P we observe a 10% absolute increase in masked faults w.r.t. the accurate multiplier and of about 4% in benign faults. As also highlighted for the general-purpose case in Section 3.2, these results suggest that under particular conditions, AxC offers the opportunity to improve HW-DNN fault tolerance, and not just its efficiency.

Fig. 6(b) shows a focus on the mul12s_34P multiplier. It shows details about the number of critical outcomes resulting from injections in different output bits of the multipliers (bit 1 = MSB, i.e., sign). The height of the bars shows the critical fault percentage per injected bit position. The blue color indicates the percentage of critical injections that modify bits from value 0 to 1, while yellow reports those modifying bits from value 1 to 0. The reported values above the blue bars refer to the percentage of bitflips from value 0 to 1. In general, results show that bitflips from 0 to 1 more commonly cause critical faults (more than 90%). It indicates that the network using this multiplier is especially sensitive to faults that increase a value's magnitude, rather than those that decrease it. Moreover, fault injections in the three Least Significant Bits (LSBs) rarely caused critical faults – less than 1% per bit – which is probably the reason for increased masked and benign faults observed in Fig. 6(a). Similar observations can be used to drive the design of low-cost AxC-based fault tolerance approaches.

This analysis shows that AxC, besides improving efficiency, can enhance fault tolerance in CNN accelerators. In some cases, approximate multipliers reduce resource usage while also mitigating hardware faults through inherent error masking. Future approximate designs should explicitly target both efficiency and fault tolerance, e.g., as in the AdAM architecture [21]. Furthermore, an underexplored area is the dynamic or layer-specific approximations for adaptive resilience tuning based on workload, energy, or reliability needs. Moreover, despite AxC's potential, there is a lack of fine-grained reliability analysis for embedded FPGA-based DNN accelerators. The FPGA fault injection framework in [24] allows controlled emulation of soft errors, yet most evaluations focus on global accuracy trends, ignoring spatial fault sensitivity within architectures like systolic arrays. For example, an most-significant bit (MSB) fault in a PE near the output may be far less harmful than the same fault at the input stage, where it could propagate through subsequent computations. This positional effect is especially relevant in FPGAs, where resource distribution varies across the fabric. Addressing these location-dependent impacts is essential for selective hardening in heterogeneous approximate DNNs. Future work should integrate position-aware fault analysis and mitigation to enable truly efficient and fault-resilient hardware accelerators for DNNs tailored to both architecture and physical layout.

## 4 Hardware Security in/for Approximate Computing

Several attacks discussed or demonstrated in the literature raise concerns about Approximate Computing (AxC) [27, 28], e.g., malicious
<figure><img src="image_8.png" /><figcaption>Fig. 7: (a) Voltage scaling on processor datapath for PUF (b) Error behaviour (c) Uniqueness and reliability [25, 26].</figcaption></figure>

modifications, incorrect DRAM refresh rates, and deanonymiza-
tion. Based on reported vulnerabilities, potential attacks, including
side-channel analysis (SCA), hardware Trojan insertion, reverse
engineering, and cloning, show a large impact on all applications
that use AxC-based systems. On the other hand, AxC is also be-
ing explored to enhance the security of computational systems.
Several security solutions exploiting approximate systems, such as
information hiding, homomorphic encryption, and authentication,
have been successfully demonstrated with the additional benefit of
saving resources [28].

## 4.1 Hardware Security

*Physical Unclonable Functions* Physical unclonable function (PUF) uses manufacturing process variations to generate an unclonable digital fingerprint [29]. PUFs have been explored for several applications, including secret key generation, device identification, and authentication. Depending on additional hardware utilization, PUFs can be categorized into intrinsic PUFs and non-intrinsic PUFs [29]. Intrinsic PUFs, e.g., processor PUFs, utilize existing hardware [30] to generate the response. An overclocking-based processor PUF, scan-chain-based PUF, and a dynamic timing-aware processor PUF have been proposed recently [31, 32]. However, these PUF designs show poor uniqueness, require several design constraints, and cause an increase in power consumption.

*Side Channel Analysis* Among the wide variety of physical attacks introduced, SCA attacks have proved to be simple and effective in recovering secret information [33]. These attacks are applied to cryptographic engines to retrieve the original key information. SCA is mainly classified into power analysis, Electromagnetic (EM) signal analysis, and photonic analysis [34, 35]. Recently, SCAs have been demonstrated against neural network accelerators to retrieve weights, structure, and parameters of the network [36, 37]. The process of conducting SCAs can be simplified by the inherently lightweight nature of AxC-based systems, which often involve reduced hardware complexity and smaller computational footprints. Conversely, the intrinsic error characteristics introduced by approximation can complicate the execution and analysis of such attacks, introducing unpredictable variations in side-channel leakage. This dual effect underscores the need for further research to fully understand and address the security implications of AxC.

## 4.2 PUF Design for Approximate Computing

This section presents the benefits and utility of AxC towards
intrinsic processor PUF. The performance and metrics of PUF are
analyzed to identify the benefits for AxC. Several dedicated PUF
designs include ring oscillator PUFs, arbiter PUFs, and flip-flop-
based PUFs, which utilize dedicated hardware and show large area
and energy consumption overheads [29, 30, 39]. Intrinsic proces-
sor PUFs leveraging AxC techniques have been explored due to
their minimal additional hardware requirements and strong suit-
ability for securing AxC-based systems. The first PUF to exploit
this concept measured instruction failures induced by overclocking
a microprocessor pipeline [31]. While innovative, this approach
suffers from poor uniqueness, is constrained by multiple design
limitations, and requires numerous repeated instruction executions
to reliably estimate the error rate. Moreover, the overclocking pro-
cess increases power consumption, leading to a considerable power
overhead. A dynamic timing-aware processor PUF has been demon-
strated that utilizes the floating-point unit of a processor with much
lower power consumption [32]. However, the uniqueness of the re-
sulting PUF is very poor. More recently, a widely adopted AxC tech-
nique—voltage scaling—has been applied to processor datapaths
to elicit PUF characteristics [25, 26]. In this approach, a general-
purpose processor datapath subjected to supply voltage scaling
leverages dominant chip-to-chip delay variations to reveal unique
device signatures. Using this method, researchers have demon-
strated a PUF design in which the extracted bits from the processor
datapath under reduced supply voltage exhibit significantly higher
uniqueness compared to earlier approaches.

A systematic voltage scaling is applied on the processor datapath (as shown in Fig. 7(a)) to obtain the behaviour of PUF. With a fixed clock period ($T_{CLK}$) of 2ns (500MHz), for any sub-nominal voltage (from 0.75V to 0.5V), the design demonstrates negative slack (due to the increased delay), the design exhibits timing errors, and operates in an AxC region. The design samples exhibit a variable average error for 500 inputs and a population of 20 devices. This demonstrates the distinct inter-die difference in failure behavior even averaged over a set of inputs with chip-to-chip variations, as shown in Fig. 7(b). PUF metrics, including uniqueness and reliability, are calculated by varying the supply voltages as shown in Fig. 7(c). It is observed that the uniqueness of the PUF increases
<figure><img src="image_9.png" /><figcaption>Fig. 8: (a) ANN diagram with single neuron modeled as PE (b) Correlation power analysis mechanism (c) MTD analysis [38].</figcaption></figure>

with the reduction in supply voltage, and this region is highly suit-
able for PUF. In contrast, the reliability of PUFs is reduced with a
reduction in supply voltage. However, the optimum uniqueness and
reliability are identified for better operation of the PUF. Moreover,
depending on the application, the designer can choose the supply
voltage that can provide the required uniqueness and reliability.
In contrast to dedicated PUF designs, AxC provides several new
features to processor designs that can be utilized to improve re-
source optimization for PUF design. However, more research in
this direction is required to reap the full benefits of AxC to support
lightweight security strategies.

4.3 SCA of Approximate Computing

The growing global demand for high-performance computing
has driven the energy consumption of data centers and compute
clusters to unprecedented levels in recent years [40]. A major con-
tributor to this trend is the rapid proliferation of computation-
ally intensive Artificial Neural Networks (ANNs)-based AI applica-
tions [41]. As discussed earlier, AxC—also referred to as transparent
or inexact computing—has emerged as a promising strategy for re-
ducing energy consumption by relaxing exactness requirements
in error-tolerant workloads. Given their inherent resilience to mi-
nor computational errors, ANNs represent a natural fit for such
techniques, making approximate ANNs (AANNS) a likely candidate
for future edge deployments where energy budgets are especially
constrained. Recent studies have demonstrated that integrating
approximate circuits into the PEs of ANNs can yield substantial
savings in area, energy, and latency compared to exact implemen-
tations [42, 43]. However, as these systems increasingly operate in
security-critical environments, safeguarding their information pro-
cessing, model parameters, and architectural details from modern
SCAs has become imperative.

Side-channel attacks such as cache-timing, Electromigration (EM), and power-based techniques have all been shown to extract sensitive information from ANNs [36, 37]. Since approximation inherently modifies the power and timing characteristics of the hardware, it stands to reason that it will also influence the effectiveness and detectability of such attacks—though the nature and extent of this impact remain to be fully understood. In hardware terms, each neuron in an ANN can be implemented as a PE that computes a weighted sum. Understanding how approximation at this level

interacts with the leakage mechanisms exploited in SCAs is there-
fore a critical step toward designing secure and energy-efficient
approximate AI accelerators.

The objective is to evaluate the relative leakage of different ap-
proximate PEs (with voltage scaling, frequency scaling, and bitwise
approximation) based on the design proposed in [42], consisting
of two 4-bit multipliers and an 8-bit adder, as shown in Fig. 8(a).
Multiple versions of this PE were implemented at 45nm CMOS and
simulated using Cadence EDA tools with varying levels of bitwise
approximation from 0 bits (exact design) to 4 bits (50% approxima-
tion). For the power analysis attack, we use a Correlation Power
Analysis (CPA)-based approach, focusing on the multiply-add oper-
ation within the PE which is visualized in Fig. 8(b). Further, Fig. 8(c)
shows the measurement-to-disclosure (MTD) for each test case.
MTD is defined as the minimum number of power traces required
to retrieve the original weight information. To calculate this, the
attack was repeated using 256, 512, 768, and 1024 traces. The point
where the dotted line (original weight) becomes distinct from the
general body of potential weights is the MTD. In this test, the base-
line value is 48 for an exact PE. Voltage scaling increases this to 570
at 25% error, and above 1024 at 37% error. Frequency scaling like-
wise increases to roughly 600 at 25% error and somewhere above
1024 at 37% error. The bitwise approximation performs better than
the exact case but worse than other methods with an MTD of 200
at 25% error and roughly 512 at 37% error. The voltage scaling, fre-
quency scaling, and bitwise approximation obfuscated the power
traces' information with inherent errors. Due to this, the power
traces may become noisy, MTD is increased, and it is harder for the
attacker to obtain secret weight information.

5 Accuracy-driven Approximate Computing

5.1 Motivation and Concepts

Traditionally, AxC has been explored primarily as a paradigm
that intentionally relaxes output accuracy requirements in error-
resilient applications to reduce critical path delay (CPD), hardware
complexity, and energy consumption of the corresponding imple-
mentation. Most existing AxC research aligns with this perspective,
proposing approximation techniques across the computing stack
that trade accuracy for performance and efficiency [44–48]. Among
<figure><img src="image_10.png" /><figcaption>Fig. 9: Designs for approximate signed 7-bit adders using AppAxO model [1]. (a) Operator-level design space. (b) Application-level design space</figcaption></figure>

these techniques, AxO have received particular attention as a practical and effective solution for AI workload acceleration [49, 50]. This focus is motivated by the dominance of arithmetic operations—especially Multiply-accumulate (MAC) units—across a wide range of AI models and the inherent error tolerance of these applications. For instance, as discussed in Section 2, a commonly used strategy for AxO generation (circuit-level approximations) is the bottom-up approach, which typically involves pruning a generic operator model.

For example, Fig. 9(a) illustrates the design space of a signed 7-bit adder implemented using the AppAxO model [1]. As discussed in Section 2, unlike selection-based approaches that rely on a pre-designed library of AxOs for application-level accuracy-PPA trade-off exploration, frameworks such as AppAxO enable dynamic generation of AxOs tailored to specific application requirements. In this example, the accurate implementation—referred to as *BASE* —uses seven 6-input LUTs to add two 7-bit inputs and generate a 7-bit output, which results in arithmetic overflows for certain input combinations. To evaluate error-LUT trade-offs, its outputs are compared against an overflow-safe reference adder that also processes 7-bit inputs but produces an 8-bit result. Fig. 9(b) illustrates the use of the same AxOs as accumulators in a Spiking Neural Network (SNN) for MNIST classification. The resulting Pareto front—based on LUT utilization and classification error—shows a similar trend, with five dominant designs that trade accuracy for resource (LUTs) savings. In such AxO explorations, the highest application-level accuracy is typically achieved by the accurate operator. For instance, the *BASE* design, which utilizes 7 LUTs, yields the maximum classification accuracy i.e., the lowest classification error. However, since the base operator (the generic implementation of the adder) was not optimized for the specific computational patterns and requirements of SNN operations, the potential for application-level accuracy improvements through such generic AxO exploration remains limited. This conventional perspective of AxC raises an intriguing question: *Can AxC be leveraged not only to preserve computational efficiency but also to enhance application-level accuracy beyond that of exact computation—without incurring additional overhead in resources, latency, or energy consumption?*

Addressing this question necessitates a thorough exploration of application-specific characteristics that can be leveraged to guide the design of more effective approximations. This approach represents a shift in perspective, positioning AxC as not only a resource

<figure><img src="image_11.png" /><figcaption>Fig. 10: Neuron Model: Basic Integrate and Fire</figcaption></figure>

<figure><img src="image_12.png" /><figcaption>Fig. 11: Overflow in a 4-bit signed accumulator during weighted spike accumulation: preventing the neuron from reaching the threshold required to generate a spike</figcaption></figure>

optimization technique, but also a means to enhance accuracy in targeted, resource-constrained scenarios. To address this intriguing research question, a recent work, AxOSpike [51], considers SNNs as a benchmark application, analyzing their operational characteristics and leveraging these insights to guide the design of application-aware AxOs. The goal is to achieve improved application-level accuracy while maintaining PPA metrics comparable to those of accurate operators. In the following, we discuss the SNN-specific computational characteristics that have been analyzed to guide the design of approximate operators capable of improving application-level accuracy beyond that of accurate baseline implementations.

## 5.2 SNN Architectural Characteristics

In our work AxOSpike, we use a fully connected SNN for MNIST digit classification. The network comprises an input layer, a single hidden layer, and an output layer, and processes 28 × 28 grayscale images. For our analysis, we adopt the basic Integrate-and-Fire (IF) model, shown in Fig. 10, which excludes decay and refractory mechanisms and uses membrane voltage as the sole internal state. Furthermore, rate encoding is employed to translate input features into spike frequencies. Neurons integrate weighted input spikes over time and emit an output spike when the membrane voltage exceeds a fixed threshold. The classification of the MNIST dataset is based on spike counts at the output layer over 10 timesteps. This simplified setup enables focused analysis of the impact of variations in the accumulator operator.

As shown in Fig. 10, each SNN neuron contains an accumulator referred to as a $W \times N_N$ accumulator, where $W \le N$. This accumulator sums W-bit weights to generate an N-bit output. The output bit width, N, is a crucial design parameter since it influences the frequency of arithmetic overflows produced by the accumulator. Assigning $N = W$ can lead to frequent arithmetic overflows, which occur when the addition of two positive values results in a negative output, or two negative values produce a positive output due to limited bit width. In the SNN model used in this work, a neuron generates a spike when the accumulated sum of weighted input spikes reaches a predefined threshold. However, due to overflow,
<figure><img src="image_13.png" /><figcaption>Fig. 12: $N \times N_N$ AccMSB adder structure</figcaption></figure>

the accumulated value may wrap around—for example, a large positive sum may overflow into a negative value, or a large negative sum may wrap toward a positive value—preventing the correct threshold from being reached, as shown in Fig. 11. Although the threshold itself influences accuracy, setting it too low or too high can further degrade performance. To mitigate these effects, a larger output bit width $N$ in the $W \times N_N$ accumulator can be used. However, FPGA-optimized implementations of $W \times N_N$ and $N \times N_N$ adders exhibit comparable PPA characteristics.

To this end, we exploit approximation as a means to mitigate arithmetic overflows in the BASE adder during accumulation. To support proper accumulator behavior, including resetting to zero, our proposed overflow-safe adder guarantees that operations of the form $X + (-X)$ always yield zero. The adder functions like a conventional design (BASE adder) when the input operands have opposite signs. However, when both operands share the same sign (either positive or negative), it dynamically switches to an approximate mode, producing an output with the same sign as the inputs. Although this output may be numerically imprecise, preserving the sign helps prevent overflows in practice. Notably, the control logic required to implement this behavior introduces no additional resource overhead compared to the adder.

## 5.3 Overflow-safe Approximate Signed Adder

Fig. 13 presents the generalized architecture of the proposed overflow-safe approximate adder, denoted as $N \times N_N$ AccMSB. This architecture follows the LUT- and carry chain-based implementation described in Fig. 2. Unlike the baseline adder (in Fig. 2, this design modifies the behavior of the two most significant LUTs when both operands have the same sign. Specifically, the second most significant LUT and its associated carry chain element always generate a carry-out of 0, which is propagated to the most significant stage. This fixed carry-in is then used by the most significant LUT and its carry chain to compute the sign bit of the output. As a result, the output bit $S_{N-2}$ becomes approximate under same-sign input conditions. This approximation ensures that the output retains the input sign, effectively preventing arithmetic overflows. Furthermore, AxOSpike supports logic pruning similar to AppAxO, which typically replaces pruned computational blocks with a constant zero (Fig. 2). In contrast, AxOSpike extends this strategy by allowing pruned blocks to be replaced with either ‘0’ or ‘1’. This additional flexibility expands the AxO design space and can significantly improve output accuracy in certain scenarios.

## 5.4 Quantitative Results

Fig. 13 compares the MNIST classification accuracy using BASE and AccMSB adders as accumulators in the SNN's neurons across different threshold values. The AccMSB design consistently outperforms

<figure><img src="image_14.png" /><figcaption>Fig. 13: Accuracy vs. threshold for BASE and AccMSB $8 \times 8_8$ adders used as SNN accumulators</figcaption></figure>

<figure><img src="image_15.png" /><figcaption>Fig. 14: Classification error vs. PDPLUTs for approximate $8 \times 8_8$ adders used as accumulators in SNN neurons</figcaption></figure>

BASE design across a wide range of threshold values, demonstrating improved accuracy due to its ability to mitigate overflow-induced errors through sign-preserving approximation. Fig. 14 compares the SNN application-level accuracy achieved using state-of-the-art AxO circuits. Specifically, it includes $8 \times 8_8$ designs from EvoApprox [5] and a hybrid approach that combines AxOSpike's proposed AccMSB design with AppAxO's pruning methodology, referred to as AppAxO+AccMSB. Fig. 14 presents the corresponding Pareto fronts with respect to PDP $\times$ LUTs utilization and SNN classification accuracy. AxOSpike clearly outperforms existing methods, contributing 93 out of 98 Pareto-optimal designs, while EvoApprox and AppAxO+AccMSB contribute only 1 and 4 designs, respectively. These results underscore the value of incorporating application-specific characteristics into the design of approximate arithmetic operators.

## 6 Conclusion

In this article, we presented a comprehensive view of approximate computing as a multidimensional optimization strategy that extends beyond energy efficiency. We highlighted recent advances
in AI-guided DSE, surrogate modeling, and application-aware operator design, while also emphasizing the growing importance of reliability and security co-optimization. While significant progress has been made, several research challenges remain to unlock the full potential of approximation. Future directions include explainable ML and reinforcement learning for intelligent adaptation, integration with emerging paradigms such as quantum and neuromorphic computing, and development of standardized frameworks and toolchains supporting security, reliability, and accuracy tuning. Addressing these gaps will cement Approximate Computing as a foundational pillar in next-generation efficient, safe, and intelligent systems.

## Acknowledgments

We acknowledge financial support from the following: Deutsche Forschungsgemeinschaft (DFG) under the X-ReAp project (Project number 380524764); The Conseil régional des Pays de la Loire, Nantes Université and the Institut d'Electronique et des Technologies du numérique under the PULSAR project; Agence Nationale de la Recherche (ANR) under the RE-TRUSTING project, ANR-21-CE24-0015; EPSRC (UK) under the Grant EP/X009602/1.

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