# All-in-One Analog AI Hardware: On-Chip Training and Inference with Conductive-Metal-Oxide/HfOx ReRAM Devices

Donato Francesco Falcone, Victoria Clerico, Wooseok Choi, Tommaso

Steconi, Folkert Horst, Laura Bégon-lours, Matteo Galetta, Antonio La Porta, Nikhil Garg, Fabien Alibart, et al.

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## ► To cite this version:

Donato Francesco Falcone, Victoria Clerico, Wooseok Choi, Tommaso Steconi, Folkert Horst, et al. All-in-One Analog AI Hardware: On-Chip Training and Inference with Conductive-Metal-Oxide/HfOx ReRAM Devices. Advanced Functional Materials, 2025, pp.2504688. 10.1002/adfm.202504688. hal-05148002

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https://hal.science/hal-05148002v1

Submitted on 7 Jul 2025

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# All-in-One Analog AI Hardware: On-Chip Training and Inference with Conductive-Metal-Oxide/HfOₓ ReRAM Devices

Donato Francesco Falcone,*, Victoria Clerico, Wooseok Choi, Tommaso Stecconi, Folkert Horst, Laura Bégon-Lours, Matteo Galetta, Antonio La Porta, Nikhil Garg, Fabien Alibart, Bert Jan Offrein, and Valeria Bragaglia

Analog in-memory computing is an emerging paradigm designed to efficiently accelerate deep neural network workloads. Recent advancements have focused on either inference or training acceleration. However, a unified analog in-memory technology platform–capable of on-chip training, weight retention, and long-term inference acceleration–has yet to be reported. This work presents an all-in-one analog AI accelerator, combining these capabilities to enable energy-efficient, continuously adaptable AI systems. The platform leverages an array of analog filamentary conductive-metal-oxide (CMO)/HfOₓ resistive switching memory cells (ReRAM) integrated into the back-end-of-line (BEOL). The array demonstrates reliable resistive switching with voltage amplitudes below 1.5 V, compatible with advanced technology nodes. The array’s multi-bit capability (over 32 stable states) and low programming noise (down to 10 nS) enable a nearly ideal weight transfer process, more than an order of magnitude better than other memristive technologies. Inference performance is validated through matrix-vector multiplication simulations on a 64 × 64 array, achieving a root-mean-square error improvement by a factor of 20 at 1 s and 3 at 10 years after programming, compared to state-of-the-art. Training accuracy closely matching the software equivalent is achieved across different datasets. The CMO/HfOₓ ReRAM technology lays the foundation for efficient analog systems accelerating both inference and training in deep neural networks.

## 1. Introduction

Modern computing systems rely on von Neumann architectures, where instructions and data must be transferred between

memory and the processing unit to perform computational tasks. This data transfer, particularly recurrent and massive in prominent artificial intelligence (AI)-related workloads, results in significant latency and energy overhead.[1] Digital AI accelerators address this challenge through computational parallelism, bringing memory closer to the processing units, and exploiting application-specific processors.[2,3] This approach has demonstrated to bring significant improvements in throughput and efficiency for running deep neural networks (DNNs),[4] but the physical separation between memory and compute units persists. Analog in-memory computing (AIMC)[5] is a promising approach to eliminate this separation and so achieve further power and efficiency improvements in deep-learning workloads,[6] by enabling some arithmetic and logic operations to be performed directly at the location where the data is stored. By mapping the weights of DNNs onto crossbar arrays of resistive devices and by leveraging Ohm's and Kirchhoff's physical laws, matrix-vector multiplications (MVMs)—the most recurrent operation in AI-workloads[7]—are performed in memory with O(1) time complexity.[4,5,8] Recent demonstrations of the AIMC paradigm have primarily focused on accelerating the inference step of digitally trained DNNs.[9–12]

D. F. Falcone, V. Clerico, W. Choi, T. Stecconi, F. Horst, L. Bégon-Lours, M. Galetta, A. La Porta, B. J. Offrein, V. Bragaglia
IBM Research - Europe
Zürich, Rüschlikon 8803, Switzerland
E-mail: dof@zurich.ibm.com

The ORCID identification number(s) for the author(s) of this article can be found under https://doi.org/10.1002/adfm.202504688

© 2025 The Author(s). Advanced Functional Materials published by Wiley-VCH GmbH. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

DOI: 10.1002/adfm.202504688

N. Garg, F. Alibart
Institut Interdisciplinaire d'Innovation Technologique (3IT)
Université de Sherbrooke
Sherbrooke, Quebec QC J1K 0A5, Canada

N. Garg, F. Alibart
Institute of Electronics, Microelectronics and Nanotechnology (IEMN)
Université de Lille
Villeneuve d'Ascq 59650, France
However, the increasing computing demands of modern AI models make the training phase orders of magnitude more costly in time and expenses than inference, highlighting the need for efficient hardware acceleration based on the AIMC paradigm. For instance, Gemini 1.0 Ultra required over $5 \cdot 10^{25}$ floating-point operations (FLOPs), approximately 100 days, 24 MW of power, and an estimated cost of 30 million dollars for training.[13]

Analog training acceleration imposes even more stringent requirements on resistive devices. In addition to inference (i.e., the forward pass), the back-propagation of errors, gradient computation, and weight update steps must be performed during the learning phase. However, in the digital domain updating the weights of a matrix of size $N \times N$ requires $O(N^2)$ digital operations, leading to a significant drop in efficiency and speed. Beyond the forward pass, the AIMC approach enables acceleration of (1) backward pass through MVMs transposing the inputs and outputs, (2) gradient computation, and (3) the weight update through gradual bidirectional conductance changes upon external stimuli, all with $O(1)$ time complexity. To achieve this, the ideal analog resistive device should exhibit bidirectional, linear, and symmetric conductance updates in response to an open-loop programming pulse scheme (i.e., without the need for verification following each pulse).[4,14] Promising technologies include redox-based resistive switching memory (ReRAM),[15,16] electrochemical random access memory (ECRAM),[17] and capacitive weight elements.[18] Addressing the various non-idealities of these technologies[19] requires the co-optimization of technology and designated training algorithms.

Gokmen et al.[20] proposed an efficient, fully parallel approach that leverages the coincidence of stochastic voltage pulse trains to carry out outer-product calculations and weight updates entirely within memory, in $O(1)$ time complexity. To relax the device symmetry requirements, a novel training algorithm, known as Tiki-Taka, was designed based on this parallel scheme.[21] The primary advantage of the Tiki-Taka approach lies in reduced device symmetry constraints across the entire conductance (G) range, focusing instead on a localized symmetry point (SP) where increases and decreases in G are balanced.[21] More recently, the Tiki-Taka version 2 (TTv2) algorithm was demonstrated in hardware[22] on small-scale tasks using optimized analog ReRAM technology in a 6-Transistor-1ReRAM unit cell crossbar array configuration. A similar ReRAM-based hardware platform was also used to demonstrate DNN transfer learning using TTv2,[23] where pre-trained weights were mapped onto the ReRAM array and fine-tuned. However, TTv2 faces some convergence issues when the reference conductance is not programmed with high precision.[24] Analog gradient accumulation with dynamic reference (AGAD) learning algorithm (i.e., TTv4) was proposed to overcome the reference conductance limitation, providing enhanced and robust performance.[24,25]

From a technology perspective, the addition of an engineered conductive-metal-oxide (CMO) layer in a conventional $HfO_x$-based ReRAM metal/insulator/metal (M/I/M) stack has been shown to improve switching characteristics in terms of the number of analog states, stochasticity, symmetry point, and endurance, compared to conventional M/I/M technology.[26-28] However, while CMO/$HfO_x$ ReRAM technology has proven to meet all the fundamental device criteria for on-chip training,[26] array-level assessment and BEOL integration remain unexplored.

Furthermore, although accelerating DNN training using AIMC is more challenging than inference, a unified technology platform capable of performing on-chip training, retaining the weights, and enabling long-term inference acceleration has yet to be reported.

This work fills this gap by demonstrating an all-in-one AI accelerator based on CMO/$HfO_x$ ReRAM technology, able to perform analog acceleration of both training and long-term inference operations. Such an integrated approach paves the way for highly autonomous, energy-efficient, and continuously adaptable AI systems, opening new paths for real-time learning and inference applications. The flowchart in Figure 1a illustrates the in-situ analog training and inference acceleration enabled by CMO/$HfO_x$ ReRAM devices, eliminating the need for digital pre-training and leveraging an open-loop update scheme for training. To achieve this goal, CMO/$HfO_x$ ReRAM devices, integrated into the BEOL of a 130 nm complementary metal-oxide-semiconductor (CMOS) technology node with copper interconnects (see “Experimental Section,” paragraph “Device fabrication” for details), are arranged in an array architecture using a 1-Transistor-1ReRAM (1T1R) unit cell. Compared to implementations that use multiple transistors to control the resistive switching, the 1T1R unit cell maximizes memory density, which is crucial for storing large AI models on a single chip. Additionally, in contrast to transistor-less implementations, the integrated transistor blocks sneak path currents and provides current compliance during both electro-forming and programming of the ReRAM device.[9] Figure 1b shows an image of the all-in-one analog ReRAM-based AI core used in this work, with the corresponding 8x4 array architecture and the schematic of the BEOL integrated 1T1R cells. The CMO/$HfO_x$ ReRAM array is first studied in a quasi-static regime by statistically characterizing the devices' electro-forming step and quasi-static switching response. A physical 3D finite-element model (FEM) is developed to represent the geometry of the conductive filament and analytically describe the charge transport mechanism within these cells. Subsequently, the weight transfer accuracy and conductance relaxation are experimentally characterized on the 8x4 array. These measurements enable the demonstration of the core's inference capabilities, validated through representative MVM accuracy simulations on a 64x64 array. After demonstrating the MVM accuracy of the CMO/$HfO_x$ ReRAM core, analog switching experiments using an open-loop identical pulse scheme demonstrated the suitability of the same core for analog on-chip training acceleration. To assess the training performance, a realistic device model was used in the simulation, accounting for measured characteristics such as non-linear and asymmetric switching behavior, as well as inter- and intra-device variabilities. The training performance was validated using AGAD on fully connected and long short-term memory (LSTM) neural networks, demonstrating scalability from small to large-scale neural networks.

## 2. Results

### 2.1. Quasi-Static Array Characterization and Modeling

The quasi-static electrical characterization and analytical transport modeling of the 8x4 CMO/$HfO_x$ ReRAM array are presented here.
a AIMC training and inference acceleration

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b All-in-one analog ReRAM-based AI core

<figure><img src="image_5.png" /><figcaption>**Figure 1.** All-in-one AIMC challenge. a) Schematic representation of the key steps required to perform on-chip training and inference with analog acceleration. Each step is executed using a crossbar array of resistive devices. b) CMO/HfOₓ ReRAM AI core used in this work, consisting of an 8×4 array of 1T1R unit cells. From a fabrication perspective, each ReRAM cell is integrated into the BEOL of a 130 nm NMOS transistor with copper interconnects.</figcaption></figure>

### 2.1.1. Filament Forming

**Figure 2a** shows the current-voltage characteristic of the ReRAM devices in the array, undergoing a soft-dielectric breakdown process, commonly referred to as forming.[29] During this step, a quasi-static voltage sweep up to 3.6 V is applied to the top electrode of each ReRAM device, while grounding the source and driving the gate of the corresponding NMOS selector with a constant $V_G = 1.2$ V ensuring current compliance. This process leads to the formation of a highly defect-rich conductive filament in the HfOₓ layer. Figure S2 (Supporting Information) provides evidence for the presence of a conductive filament in CMO/HfOₓ ReRAM devices by demonstrating the area independence of the low and high resistance states (LRS and HRS). Due to the high oxygen vacancy ($V_O^*$ in Kröger–Vink notation)[30] formation energy, ranging from 2.8 eV to 4.6 eV in HfOₓ depending on the stoichiometry,[31,32] defect generation occurs with statistical relevance only during the forming sweep within the HfOₓ layer.[28] The subsequent application of a negative voltage sweep up to –1.4 V, with a constant $V_G = 3.3$ V, induces a radial redistribution of the defects within the CMO layer, consistent with findings in literature.[28] This process leads to an increase of the ReRAM conductance and is modeled by considering a constant average radius of the conductive filament, with a local electrical conductivity increase of the CMO layer on top of the filament. Refer to the “ReRAM forming modelling” section (Supporting Information) for details. To determine the experimental ReRAM forming voltage, the voltage drop across the NMOS selector must be subtracted from the voltage applied to the 1T1R cell. Figure 2b shows the experimental transistor output characteristic, from which the resistance in the triode region at $V_G = 1.2$ V is measured and used to extract the distribution of $V_{forming}^{ReRAM}$ within the CMO/HfOₓ ReRAM array (reported in Figure 2c). Refer to the “Experimental Section,” paragraph “ReRAM forming voltage extraction” for details. The highly reproducible CMO/HfOₓ ReRAM forming step exhibits a 100% yield with a narrow distribution ($\sigma = 75$ mV) around $V_{forming}^{ReRAM} \approx 3.2$ V, making it suitable

for integration with 130 nm NMOS transistors rated for 3.3 V operation.

### 2.1.2. Resistive Switching and Polarity Optimization

The underlying physical mechanism behind the resistive switching in analog CMO/HfOₓ ReRAM devices has been recently unveiled.[28,33,34] The current transport is explained by a trap-to-trap tunneling process, and the resistive switching by a modulation of the defect density within the conductive sub-band of the CMO that behaves as electric field and temperature confinement layer. In these works, the analog CMO/HfOₓ ReRAM device shows a counter-eightwise (C8W) switching polarity, according to the definition proposed in literature.[35] The intrinsically gradual *reset* (from low to high resistance) process, marked by a temperature decrease, occurs during the positive voltage sweep on the ReRAM top electrode, while the exponential *set* (from high to low resistance) process, involving a rapid temperature increase, occurs on the negative side.[28] However, when arranged in a 1T1R cell configuration based on an NMOS selector, the C8W switching polarity prevents direct control of the transistor’s $V_{GS}$ during the exponential *set* process. This results in reduced switching uniformity, which is critical for the array-level adoption of analog CMO/HfOₓ ReRAM devices.

For this reason, in this work the analog CMO/HfOₓ ReRAM devices within the 1T1R cells are optimized to exhibit the desirable 8W switching polarity by extending the current switching model in literature.[28] To achieve this, following the positive forming and the initial negative voltage sweep, each device in the array is subjected to a forward and backward voltage sweep from 0 to –1.5 V. During this process, oxygen vacancies in the CMO layer radially spread outward, depleting the CMO defect sub-band within a half-spherical volume at the interface with the conductive filament, leading to a *reset* process (Figure S5, Supporting Information shows the experimental array’s response). Conversely, a voltage sweep from 0 to 1.3 V enables the migration of oxygen
<figure><img src="image_6.png" /><figcaption>**Figure 2.** ReRAM array quasi-static electrical characterization and modelling. a) (1) Experimental positive forming sweeps (with $V_G = 1.2$ V) of the 8x4 CMO/HfOₓ ReRAM devices in the array. This process results in an average filament radius of 11 nm in the HfOₓ layer. (2) Negative voltage sweeps (with $V_G = 3.3$ V) to enable defect redistribution within the CMO layer, resulting in an increase in the conductance of the ReRAM cells. A representative sweep is shown in black. The insets illustrate a schematic representation of the defect arrangement within the stack. b) Experimental NMOS transistor output characteristic, with $V_G$ up to 3 V. c) Experimental ReRAM forming voltage distribution measured from the CMO/HfOₓ ReRAM array. The experimental data used to extract the distribution are represented as green points. d) Superposition of 5 I–V quasi-static 8W-cycles (in blue) for each of the 32 devices in the array, using $V_{set} = 1.3$ V, $V_G = 1.1$ V and $V_{reset} = -1.5$ V, $V_G = 3.3$ V for *set* and *reset* processes, respectively. The analytical trap-to-trap tunneling model effectively captures the electron transport in both the LRS and HRS (yellow dashed lines). The physical parameters characterizing the transport, extracted from the model, and a schematic representation of the defect distribution, are presented for both resistive states. e) Cumulative probability distributions for both LRS and HRS. For each array cell, the average resistance over 5 I–V cycles in LRS and HRS is defined at a read voltage of 0.2 V.</figcaption></figure>

vacancies in the CMO layer in the reverse direction, resulting in a *set* transition, controlled by the transistor gate. For each 1T1R cell within the 8x4 array, Figure 2d shows 5 quasi-static I–V cycling sweeps to experimentally assess the reproducibility of the optimized 8W switching polarity. The CMO/HfOₓ ReRAM devices

are characterized by $I_{SET} \approx I_{RESET}$ highlighting the symmetric nature of the resistive switching process. The electronic transport in both the low-resistive state (LRS) and high-resistive state (HRS) is modeled as a trap-to-trap tunneling process, described by the Mott and Gurney analytical formulation. The physical
parameters characterizing the transport in both LRS and HRS ($N_e$, $\Delta E_e$, $a_e$, $\sigma_{CMO}$ and $r_{CF}$) are shown in Figure 2d. Refer to the “Analytical ReRAM transport modelling” section (Supporting Information) for details on the LRS and HRS modelling. Figure 2e illustrates the cumulative probability distribution of the experimental LRS and HRS within the array, demonstrating device-to-device uniformity and a resistance ratio HRS/LRS of approximately 15, with absolute switching voltages $\le$1.5 V. The excellent uniformity of the forming and the optimized 8W-cycling characteristics set the groundwork for AIMC-based inference and training AI-accelerators using the CMO/HfO$_x$ ReRAM technology.

## 2.2. Analog Inference with CMO/HfO$_x$ ReRAM Core

Here, the experimental characterization of the key metrics of the CMO/HfO$_x$ ReRAM array relevant to inference performance is presented. Specifically, the continuous conductance tuning capability is demonstrated over a range spanning approximately one order of magnitude. The trade-off between weight transfer programming noise of CMO/HfO$_x$ ReRAM devices and number of required iterations for programming convergence is analyzed across different acceptance ranges. Furthermore, conductance relaxation –defined as the change in conductance over time after programming–is characterized. Finally, the combined impact of weight transfer, conductance relaxation, limited input/output quantization of the digital-to-analog converter (DAC) and analog-to-digital converter (ADC), and IR drop on the array wires is evaluated with respect to MVM accuracy.

### 2.2.1. Weight Transfer Accuracy

In memristor-based AIMC inference accelerators, pre-trained normalized weights are initially mapped into target conductances and subsequently programmed into hardware in an iterative process known as weight transfer. This iterative process, which stops once the programmed conductance converges to the target value within a defined acceptance range, inherently introduces an error due to the analog nature of conductance weights. This error, described by a normal distribution with the standard deviation referred to as programming noise ($\sigma_{prog}$), leads to a drop in MVM accuracy. To quantify this non-ideality, the non-volatile multi-level capability of the CMO/HfO$_x$ ReRAM array is characterized. Figure 3a shows the experimental cumulative distribution of conductance values for 35 representative levels, with all states sharply separated and without any overlap. Figure 3b shows a schematic representation of the closed-loop (i.e., program-verify) scheme, where identical set and reset pulse trains are employed to program each ReRAM cell to its target conductance within a desired acceptance range (see “Experimental Section,” paragraph “Identical-pulse closed-loop scheme” for details). Selecting programming conditions involves a fundamental trade-off: a narrower acceptance range can improve programming precision by reducing programming noise, but it increases the number of iterations required for convergence (see Figure 3d). Besides the longer programming time, other non-ideality to consider when choosing the acceptance range are (1) the conductance relaxation immediately after programming, which is characterized in

2.2.2 for CMO/HfO$_x$ ReRAM devices, and (2) read noise, which has already been characterized between 0.2% and 2% of $G_{target}$ for CMO/HfO$_x$ ReRAM devices[27] within a similar conductance range used in this work.

The trade-off between the programming noise and the number of iterations is characterized for two representative acceptance range intervals: 0.2% and 2% of $G_{target}$, respectively. Figure 3c illustrates the experimental number of pulses needed to converge to the $G_{target}$ using the two representative acceptance ranges. On average, each cell requires approximately 11 and 89 set/reset pulses for acceptance ranges of 2% and 0.2% of $G_{target}$, respectively. Since the acceptance range is defined as a percentage of $G_{target}$, the number of iterations required for convergence is almost independent of the target conductance value. In the Supporting Information, Figure S7a shows the experimental cumulative distribution of conductance values for the same 35 representative levels presented in Figure 3a, but using 2% $G_{target}$ as acceptance range. The standard deviation of the representative conductance levels is extracted and fitted as a linear function of the target conductance (dashed lines), as shown in Figure 3e, for both acceptance ranges. For all conductance levels, a standard deviation of less than 0.1 µS (1 µS) is achieved considering 0.2% $G_{target}$ (2% $G_{target}$) as the acceptance range. This is more than one order of magnitude lower compared to other memristive technologies, such as phase-change memory (PCM) arrays, targeting similar conductance ranges.[36–38] These results demonstrate that CMO/HfO$_x$ ReRAM cells achieve an almost ideal weight transfer during programming, enabling the distinction of more than 32 states (5 bits).

### 2.2.2. Conductance Relaxation and Matrix-Vector Multiplication Accuracy

In addition to the excellent weight transfer accuracy during programming as presented in the previous section, the characterization of temporal conductance relaxation is critical to estimate the MVM accuracy over time. In analog ReRAM devices, a significant conductance relaxation has been observed immediately after programming (within 1 s).[9] Following this initial abrupt conductance change, the relaxation process slows considerably.[9,39] The physical cause of retention degradation is attributed to the Brownian motion of defects in the resistive switching layer.[39] In this section, the conductance relaxation of the CMO/HfO$_x$ ReRAM array after programming is characterized. Figure 4a shows the relaxation of the distributions previously reported in Figure 3a, approximately 10 min after programming. The 35 levels remain distinguishable 10 min after programming, with an average overlap of 9.6% between adjacent states Gaussians, while the average standard deviation of the distributions increases to 0.6 µS, showing almost independence from the $G_{target}$ (see Figure 4b).

The stability of the CMO/HfO$_x$ ReRAM conductance states is further assessed on a longer time-scale, up to 1 h. To achieve so, a linearly spaced $G_{target}$ vector within the experimental conductance range of 10 µS to 90 µS is defined, with a fine step of 0.2 µS (400 points). Each $G_{target}$ value is programmed into a single ReRAM device within the array. Due to the size mismatch between the array (32 devices) and the $G_{target}$ vector (size 400), multiple measurement batches are needed. Figure 4c shows the
<figure><img src="image_7.png" /><figcaption>**Figure 3.** Weight transfer characterization. a) Cumulative distributions of 35 conductance states obtained using an identical-pulse closed-loop scheme with a 0.2% $G_{\text{target}}$ acceptance range. For each distribution, the entire CMO/HfO$_x$ ReRAM array was programmed to the corresponding $G_{\text{target}}$, and the conductance values measured during the final closed-loop iteration (during programming) is reported. Each dot represents a 1T1R cell. b) An example sequence of the identical-pulse closed-loop programming scheme utilized in this work. c) Experimental number of closed-loop iterations as a function of $G_{\text{target}}$ for the two representative acceptance ranges. Each semitransparent point represents a 1T1R cell, the opaque points represent the average number of iterations per $G_{\text{target}}$, and the horizontal dashed line indicates the overall average of the opaque points. d) Graphical representation of the trade-off between programming noise and the number of iterations required for convergence, as a function of the acceptance range. e) Experimental programming noise as a function of $G_{\text{target}}$ for the two representative acceptance ranges. Each point represents the standard deviation of the normal distribution measured across the entire array. The dashed lines in black indicate the corresponding linear fits.</figcaption></figure>

experimental relaxation of the 400 programmed states within the entire conductance window, 1 s and 1 h after programming, executed with the closed-loop scheme (see "Experimental Section," paragraph "Identical-pulse closed-loop scheme" for details) and with a 0.2% $G_{\text{target}}$ acceptance range. The exhibited conductance error induced by the relaxation process after 1 h, computed as $G_{1h} - G_{\text{prog.}}$, is plotted as a function of the programmed conductances in Figure 4d. After 1 h, although both positive and negative relaxation errors are recorded, an average decrease in conductance is observed across all programmed states, with a relaxation error averaging around -0.7 µS. This highlights that the relaxation process in CMO/HfO$_x$ ReRAM devices leads, on average, to a decrease in the mean and an increase in the standard deviation of the Gaussian distributions regardless of the initial conductance state. Since the absolute magnitudes of the mean decrease

and the standard deviation increase are independent of $G_{\text{target}}$, an extended characterization of the relaxation process up to 1 week is conducted for a representative conductance state (50 µS). To achieve this, the array's CMO/HfO$_x$ ReRAM devices are programmed using the identical-pulse closed-loop scheme to $G_{\text{target}}$ of 50 µS, with a 0.2% $G_{\text{target}}$ acceptance range. Figure 4e illustrates the experimental array relaxation over 1 week. The insets display the evolution of both the mean and standard deviation as a function of the logarithm of time after programming (in seconds), using a linear fit to predict the conductance distribution over a 10-year period.

To assess the accuracy of analog MVM, a comprehensive set of non-idealities–both intrinsic to CMO/HfO$_x$ ReRAM devices and at the architecture level–is considered, including finite programming resolution with 0.2% $G_{\text{target}}$ acceptance range,
<figure><img src="image_8.png" /><figcaption>**Figure 4.** Conductance relaxation and MVM accuracy. a) Probability density distributions of 35 conductance states approximately 10 minutes after programming. The black areas between adjacent Gaussian distributions represent the overlap of their tails. On average, an overlap of 9.6% is observed after 10 min. b) The standard deviations of the 35 conductance states during programming (in purple) and 10 min after it (light blue). c) Relaxation of 400 conductance states, with one device per G-state, measured 1 s and 1 h after programming. d) Relaxation error 1 h after programming. A negative and nearly G-independent average error (dashed line) indicates that relaxation in CMO/HfOₓ ReRAMs tends toward a slight conductance decrease and is state-independent. e) Experimental array relaxation of a representative 50 µS state, up to 1 week after programming with 0.2% Gₜetarget acceptance range. Each probability density distribution is normalized to its maximum for graphical representation. The experimental data used to extract the distributions are represented as points aligned to the y=0 horizontal axis. Insets show the time dependence of the mean and standard deviation. Dashed blue lines represent the conditions during programming, once the convergence to Gₜetarget is reached, while a linear fit (green dashed line) extrapolates the distribution 10 years after programming (dashed black line). f) Analog MVM accuracy simulations using a 64x64 CMO/HfOₓ ReRAM array as a function of time after programming (indicated by different colors). The inset shows the expected RMSE compared to the ideal FP result. Experimental programming noise, conductance relaxation, limited input/output quantization and IR-drop are considered in this assessment.</figcaption></figure>

conductance relaxation, limited ADC and DAC quantization, and IR-drop across array wires. Figure 4f shows the hardware-aware simulation results of the analog MVM using CMO/HfOₓ ReRAM cells, projected for up to 10 years from programming, compared to the expected floating-point (FP) result. The results are generated using a single 64×64 normally distributed random weight matrix and 100 uniformly distributed input vectors, both within the range [-1, 1] (see the “HW-aware simulation of analog MVM” section in the Supporting Information for details). Considering the input and output quantization of 6-bit and 8-bit respectively, the inset illustrates the time evolution of the root-mean-square error (RMSE) of the simulated analog MVM compared to the FP expected result. These results show that the CMO/HfOₓ ReRAM core enables accurate MVM operations, achieving an RMSE ranging from 0.03 at 1 second to 0.2 at 10 years after programming, compared to the ideal FP case. Figure S8 (Supporting Information) illustrates the impact of IR-drop and input/output quantization on the RMSE of an MVM performed on a 64×64 array. Over short time scales (within 1 h), the primary accuracy bottleneck is the limited input/output quantization of 6-bit and 8-bit, respectively.

Over longer periods, relaxation effects become the dominant source of non-ideality. In a larger 512×512 array, IR-drop emerges as the main accuracy bottleneck for analog MVM. Compared to the analog ReRAMs studied by Wan et al.,[9] who report an experimentally determined RMSE of approximately 0.58 under conditions similar to those of this work, CMO/HfOₓ ReRAMs demonstrate a potential improvement in MVM accuracy by a factor of 20 and 3, 1 s and 10 years after programming, respectively. The excellent MVM accuracy results demonstrate the suitability of CMO/HfOₓ ReRAM devices for long-term AI inference applications, and lay the foundation for AI training acceleration, where short-term forward and backward MVMs are key steps.

## 2.3. Analog Training with CMO/HfOₓ ReRAM Core

To efficiently tackle deep learning workloads, the analog AI accelerator must not only perform forward and backward passes (MVMs), but most importantly, allow for parallel weight updates.[40] During backpropagation, the synaptic weights are
updated according to the gradient of the corresponding layer, which is computed as the outer-product of the input activation x and the backpropagated error δ (W ← W − η(δ⊗x), where η is the learning rate).[21] For in-memory training accelerators, this outer-product weight update must be performed in-memory and in parallel. To achieve this, analog CMO/HfOₓ ReRAM devices need to allow for bidirectional conductance updates through a stochastic open-loop pulse scheme.[20,21] Remarkably, the parallel and open-loop update scheme significantly accelerates training compared to serial and closed-loop methods, providing efficiency gains of several orders of magnitude and advantages in system design complexity.[41] In this section, the bidirectional open-loop response of the CMO/HfOₓ ReRAM array, required during Tiki-Taka training, is characterized. Specifically, the analog conductance potentiation, depression and symmetry point are measured. Subsequently, the devices' responses are statistically reproduced in the open-source “aihwkit” simulation platform developed by IBM.[40] Finally, this hardware-aware device model, which includes device variabilities, is used to simulate the training of representative neural networks using the AGAD learning algorithm. This novel analog training algorithm relaxes the symmetry requirements of previous Tiki-Taka versions by incorporating additional digital computations on-the-fly.[24]

### 2.3.1. Open-Loop ReRAM Array Characterization

Figure 5a shows the experimental conductance change of a representative CMO/HfOₓ ReRAM device within the array upon applying identical-voltage pulse trains with alternating polarity in batches of 400. Subsequently, a sequence of 500 pulses with alternating polarity, consisting of 1-pulse-up followed by 1-pulse-down, is applied to experimentally determine the symmetry point. Notably, the device stabilizes at its SP within approximately 100 pulses, while extending the symmetry point shifting technique up to 500 pulses enables the assessment of potential perturbations or instabilities of the SP. The same open-loop programming scheme, with $V_{set} = 1.35$ V ($V_G = 1.4$ V) and $V_{reset} = -1.3$ V ($V_G = 3.3$ V), each lasting 2.5 µs, is applied to all devices in the 8x4 array. The set/reset pulse width is limited by the experimental setup, although previous work has demonstrated CMO/HfOₓ ReRAM switching with pulses as short as 60 ns.[27] Due to inter-device (device-to-device) and intra-device (cycle-to-cycle) variabilities, the experimental response of each device to a given number of identical pulses exhibits some level of variability (see Figure S9, Supporting Information). Therefore, for each pulse, a Gaussian distribution of the measured conductance states among the devices is extracted. For statistical relevance, Figure 5b shows the experimental standard deviation of the array response to the open-loop scheme as a function of the pulse number, represented in grey. To realistically assess the accuracy of analog training with CMO/HfOₓ ReRAM devices, the key figures of merit of the device training characterization–such as the number of states, the symmetry point skew, and the noise-to-signal ratio (NSR)–are first extracted from experimental data, as defined below.

$$N_{\text{states}} = \frac{G_{\text{max}} - G_{\text{min}}}{\overline{\Delta G_{\text{sp}}}} \quad (1)$$

$$SP_{\text{skew}} = \frac{G_{\text{max}} - \overline{G_{\text{sp}}}}{G_{\text{max}} - G_{\text{min}}} \quad (2)$$

$$NSR = \frac{\sigma_{\Delta G_{\text{sp}}}}{\overline{\Delta G_{\text{sp}}}} \quad (3)$$

$G_{max}$ and $G_{min}$ represent the maximum and minimum values extracted from the full conductance swings, while $\overline{G_{sp}}$, $\overline{\Delta G_{sp}}$ and $\sigma_{\Delta G_{sp}}$ denote the values of the mean conductance, mean conductance update and standard deviation of the conductance update at the symmetry point during the 1-pulse-up, 1-pulse-down procedure, respectively. Figure 5c shows the experimental Gaussian distributions of these metrics for the 32 devices within the array. The results indicate an average of 22 states, with a range from 16 to 33. A shift in the $G_{sp}$ (or $SP_{skew}$) of 61% is measured, reflecting a negative trend in the device asymmetry where the down response is steeper than the up response. An average NSR of 90% among the devices is obtained, demonstrating the capability to discriminate between pulses up and down around the symmetry point. This parameter reflects the intrinsic noise on the device's response under identical conditions, highlighting an intra-device variation.[40] Previous studies on similar CMO/HfOₓ ReRAM systems[26] extracted these metrics from isolated 1R devices using an optimized open-loop scheme tailored to each device. In contrast, this work demonstrates for the first time that a single open-loop identical pulse scheme enables reliable operation of the entire CMO/HfOₓ 1T1R array, ensuring consistent performance across the array.

### 2.3.2. Tiki-Taka Training Simulations

To perform realistic hardware-aware training simulations, the experimental device response is reproduced on software using the generalized soft bounds model implemented in the “aihwkit”,[42] which better captures the bidirectional resistive switching behavior (see Figure S10, Supporting Information) and accounts for intra- and inter-device variabilities (see cycle-to-cycle and device-to-device variations in Figure 6a). Additionally, Gaussian distributions are modeled based on parameters extracted from device characterization ($G_{max}$, $G_{min}$, $\Delta G_{sp}$, NSR, $SP_{skew}$) to account for device-to-device variability observed in the experimental characterization (see the “Intra and inter-device variability” section in the Supporting Information for details). This Gaussian fitting approach allows defining various device presets–characterized by the same model but with different parameter settings–to represent the synapses across the neural network. A realistic simulation setup is obtained by exclusively considering experimentally obtained parameters to reproduce the device trace (see the “Generalized soft bounds model” section in the Supporting Information for details). The device model is defined based on the observed conductance window and number of states, without assuming asymptotic behavior for an infinite number of pulses. This prevents overestimation of both the conductance window and the number of states (material states), enhancing the fidelity of the simulation.

To validate analog training with CMO/HfOₓ ReRAM technology and benchmark its performance against prior works, a three-layer fully connected (FC) neural network was trained on the
<figure><img src="image_9.png" /><figcaption>**Figure 5.** Open-loop array characterization for on-chip training. a) Bidirectional accumulative response and symmetry point of a representative device in the array. The top inset shows the open-loop identical pulse scheme used for the synaptic potentiation (red) and depression (blue). A conceptual illustration of the 8x4 CMO/HfOₓ ReRAM array is depicted on the left. b) Array statistical open-loop response to identical pulses. The grey area represents the standard deviation of the experimental Gaussian distributions, each corresponding to a specific pulse number. The inset shows a representative example of the experimental G-distribution at pulse number 1200. The raw data can be found in Figure S9 (Supporting Information). c) The experimental probability densities of N<sub>states</sub>, SP<sub>skew</sub> and NSR, respectively. The experimental data used to extract the distributions are represented as points aligned along the y=0 horizontal axis.</figcaption></figure>

MNIST dataset for image classification. In addition, the impact of the device's number of states, asymmetry, and noise-to-signal ratio on accuracy and convergence time is evaluated by simulating identical networks in which each property is individually enhanced, while keeping the others fixed at the experimentally derived values. Literature has shown that these device characteristics

critically influence the convergence of analog training algorithms.[24] Therefore, this method assesses the deviation of the current CMO/HfOₓ ReRAM device properties from the ideal analog resistive device scenario. Moreover, to show the scalability of the CMO/HfOₓ ReRAM technology to more computationally-intensive tasks, such as time series processing, a two-layer long
<figure><img src="image_10.png" /></figure>

<figure><img src="image_11.png" /><figcaption>c LSTM network trained using CMO/HfOₓ statistical array data</figcaption></figure>

<figure><img src="image_12.png" /><figcaption>**Figure 6.** Device model and on-chip training simulations. a) Device presets generated using the generalized soft bounds model with experimentally extracted parameters of CMO/HfOₓ devices, including inter- and intra-device variabilities. b) Training simulations of a three-layer fully-connected neural network on MNIST (235K parameters), using 32-bit FP precision trained on SGD (in green). Analog training simulations were performed using AGAD considering the empirical distribution of the parameters (in yellow), enhanced NSR (in red), increased N<sub>states</sub> (in blue), and symmetrical device configurations (in orange). c) LSTM network architecture for text forecasting on the *War and Peace* dataset (79K parameters). The architecture considers a sequence length of 100 tokens and accounts for two layers with 64 hidden units. d) Training results of the FP baseline (in green) and the analog training with AGAD on the experimental device configuration (in yellow). The training setup can be found in the Supporting Information.</figcaption></figure>

<figure><img src="image_13.png" /></figure>

short-term memory (LSTM) network was trained on *War and Peace* text sequences to predict the next token. Each network is initially trained using conventional stochastic gradient descent (SGD) based backpropagation with 32-bit FP precision, serving as the baseline performance. Figure 6b illustrates the accuracy per epoch for the FP-baseline trained with SGD (in green) and the analog network trained using AGAD, evaluated under four different parameter settings: (1) properties extracted from the experimental array (in yellow), (2) reduced NSR to 20% (in red), (3) average of N<sub>states</sub> = 100 states (in blue), and (4) zero average device asymmetry (in orange). Using symmetrical device presets, i.e. with an average SP<sub>skew</sub> of 50%, improves accuracy by 0.7% with respect to analog training with CMO/HfOₓ ReRAM experimentally derived configuration (96.9%), landing an accuracy of 97.6%, a 0.7% lower than the FP-SGD baseline (98.3%). The other two configurations show less performance improvement, indicating more resilience of the AGAD-training to device's N<sub>states</sub> and NSR.

The 2-layer LSTM network with 64 memory states each (see Figure 6c), is trained with the experimentally obtained device configuration. The performance is measured using the exponential of the cross-entropy loss, i.e., the test perplexity metric, which quantifies the certainty of the token prediction. Results in Figure 6d demonstrate the capabilities of the CMO/HfOₓ ReRAM

technology on more complex network architectures, such as LSTMs, and computationally demanding tasks, exhibiting performance comparable to the FP-equivalent, with an approximate 0.7% difference in test perplexity.

### 3. Conclusion

An all-in-one technology platform based on analog filamentary CMO/HfOₓ ReRAM devices is presented. This platform addresses critical challenges in modern digital AI accelerators by overcoming the physical separation between memory and compute units. It enables the execution of forward and backward MVMs, along with weight updates and gradient computations, directly on a unified analog in-memory platform with O(1) time complexity. This all-in-one approach fundamentally differs from DNN inference-only[9] and training-only[26,43] analog accelerators. In inference-only accelerators, DNN weights are trained in software (i.e., off-chip) using traditional digital CPUs or GPUs and then programmed once onto the analog AI hardware accelerator. In training-only accelerators, the long-term retention capabilities and overall MVM accuracy for large array tiles are not assessed. In this work, a novel all-in-one analog computing platform, capable of both on-chip training and inference acceleration,
<table><caption>**Table 1.** Device model benchmarking: From simplified to realistic approaches.</caption><thead><tr><th>ReRAM</th><th>Device asymmetry</th><th>Analog states</th><th>Experimental data origin</th><th>Algorithm</th><th>Model fidelity</th><th>MNIST accuracy</th></tr></thead><tbody><tr><td>Ti/HfO<sub>x</sub><sup>[43]</sup></td><td>Not-included</td><td>exp. states<sup>2</sup></td><td>BEOL array</td><td>TTv2</td><td>Medium</td><td>90.5 %</td></tr><tr><td>Ta/TaO<sub>x</sub><sup>[43]</sup></td><td>Not-included</td><td>exp. states<sup>2</sup></td><td>BEOL array</td><td>TTv2</td><td>Medium</td><td>96.4 %</td></tr><tr><td>TaO<sub>x</sub>/HfO<sub>x</sub><sup>[26]</sup></td><td>included</td><td>material states<sup>3</sup></td><td>Single ReRAMs</td><td>TTv2</td><td>Medium</td><td>97.4 %</td></tr><tr><td>CMO<sub>x</sub>/HfO<sub>x</sub><sup>1</sup></td><td>included</td><td>exp. states<sup>3</sup></td><td>BEOL array</td><td>AGAD</td><td>High</td><td>96.9 %</td></tr></tbody></table>

is unveiled. A complete estimation of the energy and time required for a full DNN training and inference run would require a specific AIMC chip architecture. This analysis is beyond the scope of this study. However, system-level evaluations on similar analog memristive AI hardware show an improvement of about two orders of magnitude in energy efficiency for DNN inference applications over digital accelerators.[44] Additionally, the AGAD-based weight update process during parallel analog in-memory training operates on a fast timescale of tens of nanoseconds.[24] Furthermore, a comparison of the CMO/HfOₓ ReRAM technology with other emerging memory technologies is provided in Table S2 (Supporting Information), highlighting the energy efficiency and performance potential of the presented all-in-one analog computing platform.

The CMO/HfOₓ ReRAM devices are integrated in the BEOL of a NMOS transistor platform in a scalable 1T1R array architecture. The highly reproducible forming step demonstrates compatibility with NMOS rated for 3.3 V operation, while the uniform quasi-static 8W-cycling characteristics, achieved with voltage amplitudes of less than ± 1.5 V, exhibit a significant conductance window and a low off-state. The multi-bit capability of more than 32 states (5 bits), distinguishable after 10 min with less than 10% overlap error, is experimentally demonstrated using an identical-pulse closed-loop scheme. The characterization of the weight transfer reveals record-low programming noise ranging from 10 nS to 100 nS, more than one order of magnitude lower than that of other memristive technologies targeting similar conductance ranges.[36–38] Each conductance distribution exhibits a state-independent relaxation process over time, characterized by a slight shift of the mean toward lower conductance and an increase in the standard deviation. This independence of the relaxation process from the target conductance is advantageous for implementing effective compensation schemes in the future.

Realistic MVM simulations on a 64x64 array tile, considering CMO/HfOₓ ReRAM device non-idealities such as finite weight transfer resolution, conductance relaxation, limited input/output quantization, and IR-drop across array wires, show an RMSE as low as 0.2 compared to the ideal FP-case, even 10 years after programming. This demonstrates that the CMO/HfOₓ ReRAM devices improve analog MVM accuracy by a factor of 20 and 3 compared to the state of the art,[9] 1 s and 10 years after programming, respectively. Although this study was performed at room temperature, previous characterization of a similar CMO/HfOₓ ReRAM stack demonstrated the thermal stability of the analog states at high temperature (less than 4% drift after 72 h at 85 °C).[26] Future studies will focus on integrating temperature-dependent retention stability and the experimental read noise of CMO/HfOₓ ReRAM devices—characterized between 0.2% and 2% of G<sub>target</sub> within a similar conductance range as used in this work[27]—into MVM accuracy simulations. Although read noise is not included in the MVM simulations of this study, no significant additional drop in MVM accuracy is anticipated. In fact, the magnitude of read noise is much smaller than that of the relaxation process and of the effect of reduced input/output quantization, which dominate the RMSE on different timescales. Furthermore, simulation results demonstrate the suitability of CMO/HfOₓ ReRAM technology for large 512x512 array, with the IR-drop expected to become the primary accuracy bottleneck in this case.

Finally, the electrical response of the CMO/HfOₓ ReRAM array to an open-loop scheme with identical pulses demonstrates the viability of this technology for on-chip training applications. A realistic device model, accounting for both inter- and intra-device variability, is derived from experimental data. **Table 1** benchmarks the representative device model used in this work on the MNIST dataset against other approaches, highlighting its high fidelity in reproducing experimental device responses.

The impact of the device's number of states, asymmetry and noise-to-signal ratio on training accuracy using the AGAD algorithm on MNIST is evaluated. This analysis demonstrates that, with the current device's experimental properties, AGAD analog training achieves 96.9% accuracy, comparable to the ideal FP-baseline of 98.3%. To further improve analog training performance and bring results closer to the software equivalent, the key metric to enhance in the device is the symmetry. Finally, the on-chip analog training capabilities of the CMO/HfOₓ ReRAM technology are demonstrated on a more complex two-layer LSTM network, showing comparable performance to its floating-point equivalent.

In conclusion, the novel CMO/HfOₓ ReRAM all-in-one technology platform presented in this work lays the foundation for efficient and versatile analog systems capable of combining both training and inference capabilities, enabling autonomous, energy-efficient, and adaptable AI systems.

## 4. Experimental Section

**Device Fabrication:** The CMO/HfOₓ ReRAM array is based on 1T1R unit cells. In this configuration, the bottom electrode of the ReRAM device is connected in series to the drain of an n-type metal–oxide–semiconductor (NMOS) selector transistor. The NMOS transistors, rated for 3.3 V operation, are fabricated using a standard 130 nm foundry process with copper BEOL interconnects. The ReRAM devices are integrated on metal-8 layer. To prevent the oxidation of the copper vias during the ReRAM stack deposition, the 70 nm thick silicon nitride (SiNₓ) passivation

<footnote n="1">¹This work. ²Mensured number of analog states during open-loop device characterization. ³The asymptotic number of states under an infinite number of pulses. ⁴Obtained at the 80th training epoch.</footnote>
layer from the foundry is used as a protective layer. On top of that, a 20 nm thick titanium nitride (TiN) bottom electrode and a 4 nm thick hafnium oxide (HfOₓ) layers are deposited by Plasma-Enhanced Atomic Layer Deposition (PEALD) process at 300 °C, while maintaining vacuum conditions to avoid oxidation of the TiN layer. Subsequently, a stack of layers consisting of a 20 nm thick conductive metal-oxide (CMO), a 20 nm thick titanium nitride (TiN), and a 50 nm thick tungsten (W) is deposited by sputtering and patterned through a lithography step. Figure S1 in the Supporting Information shows a transmission electron microscopy (TEM) image along with the energy-dispersive X-ray spectroscopy (EDS) elemental mapping profile of the CMO/HfOₓ ReRAM stack and its interface structure. Table S1 in the Supporting Information lists some potential candidate materials for the CMO layer in analog ReRAM applications. A 150 nm thick silicon oxide (SiOₓ) layer is sputtered as passivation. The passivation layer is then patterned to expose the W top electrode and the copper via in the metal-8 layer beneath the bottom electrode. The ReRAM fabrication is completed using a titanium/gold lift-off process. In this approach, the TiN bottom electrode is connected to the metal-8 via through its vertical sidewalls using gold. The ReRAM BEOL patterning steps are performed through mask-based photolithography performed on a 6×6 mm² die issued from a Multi Project Wafer (MPW). The area of the CMO/HfOₓ ReRAM devices presented in this work is 12×12 µm². Previous studies on CMO/HfOₓ ReRAM devices have demonstrated scalability down to 200×200 nm².[26–28] Due to their filament-type nature, the performance of the ReRAM devices presented in this work is expected to remain similar for smaller areas.

**ReRAM Forming Voltage Extraction:** The forming voltage of each 1T1R cell ($V_{forming}^{1T1R}$) is defined as the voltage required to trigger the highest current increase ($\max(\frac{di}{dV})$) during the quasi-static voltage sweep from 0 to 3.6 V (see Supporting Information, Figure S4a). The corresponding current is defined as the forming current ($I_{forming}^{1T1R}$) (see Supporting Information, Figure S4b). Being the transistor driven by a constant $V_G = 1.2$ V, it acts as a series resistor in the triode region before the forming event, when the ReRAM stack is highly insulating. After the forming event, when a conductive filament is created in the ReRAM device, the transistor ensures current compliance in the saturation region. The resistance of the transistor in the triode region at $V_G = 1.2$ V is measured to be $R_{DS} \approx 0.8$ kΩ (see Supporting Information, Figure S4c). Therefore, for each 1T1R cell, the actual ReRAM forming voltage is computed as $V_{ReRAM} = V_{forming}^{1T1R} - R_{DS}^{triode} \cdot I_{forming}^{1T1R}$ and reported in Figure 2c.

**Identical-Pulse Closed-Loop Scheme:** The procedure begins with a quasi-static voltage sweep from 0 to –1.5 V to *reset* each cell within the array to the HRS. Subsequently, a closed-loop scheme is initiated, which iteratively repeats the following two steps until convergence to $G_{target}$ within an acceptance range: (1) read the conductance of the ReRAM cell, and (2) if the measured value is below (above) the target conductance, apply a *set* (*reset*) programming pulse. During this iterative process, the cell conductance may fluctuate multiple times before eventually reaching the acceptance range. Starting from the HRS, this procedure is applied to the CMO/HfOₓ ReRAM array to sequentially program 35 representative conductance levels, ranging from approximately 10 µS to 90 µS, using acceptance ranges of both 0.2% $G_{target}$ and 2% $G_{target}$. Unlike the conventional incremental-pulse closed-loop technique previously used for ReRAM,[9,45] where the amplitudes of *set* and *reset* pulses are gradually increased to achieve convergence, this work employs an identical-pulse closed-loop scheme to simplify the pulse generation circuitry design, using only two fixed amplitude values for the *set* (1.35 V or 1.5 V) and two for the *reset* (–1.3 V or –1.5 V) pulses. Specifically, depending on $G_{target}$, three ranges are used: from approximately 10 µS to 30 µS with $V_{set} = 1.35$ V and $V_{reset} = –1.5$ V; from 30 µS to 60 µS $V_{set} = 1.35$ V and $V_{reset} = –1.3$ V; and from 60 to 90 µS $V_{set} = 1.5$ V and $V_{reset} = –1.3$ V. Figure S7b (Supporting Information) shows the flowchart of the identical-pulse closed-loop technique used in this work. The *set/reset* pulse width is fixed at 2.5 µs due to setup limitations, even though previous work has demonstrated CMO/HfOₓ ReRAM switching with pulse width as short as 60 ns.[27] The reading pulse amplitude and width are $V_{read} = 0.2$ V and 300 µs, respectively. During the *set*, *reset*, and read operations of each 1T1R cell, the

transistor's gate voltage is controlled with constant values of $V_G$ equal to 1.4 V, 3.3 V, and 3.3 V, respectively.

## Supporting Information

Supporting Information is available from the Wiley Online Library or from the author.

## Acknowledgements

The authors acknowledge the Binnig and Rohrer Nanotechnology Center (BRNC) at IBM Research Europe - Zurich. Special thanks go to Jean-Michel Portal, Eloi Muhr and Dominique Drouin for their contributions to the design of the NMOS transistors used in this work. The authors also extend their gratitude to Stephan Menzel for the fruitful discussions and to Ralph Heller for his assistance in wire-bonding the chip. This work was funded by SNSF ALMOND (grant ID: 198612), by the European Union and Swiss state secretariat SERI within the H2020 MeM-Scales (grant ID: 871371), MANIC (grant ID: 861153), PHASTRAC (grant ID: 101092096) and CHIST-ERA UNICO (20CH21-186952) projects.

## Conflict of Interest

The authors declare no competing interests.

## Author Contributions

Conceptualization was carried out by D.F.F. and V.B.; hardware fabrication was performed by D.F.F. and L.B.L.; electrical characterization was conducted by D.F.F., W.C., T.S., and F.H.; physical simulations were handled by D.F.F.; inference and training simulations were performed by V.C. and D.F.F.; NMOS transistor design was done by N.G. and F.A.; result interpretation was contributed by D.F.F., V.C., W.C., V.B., M.G., A.L.P., and B.J.O.; supervision was provided by V.B. and B.J.O.; manuscript writing was done by D.F.F. and V.C.; data curation was managed by D.F.F., V.C., and V.B.; manuscript review and editing were carried out by all authors; and funding acquisition was secured by B.J.O. and V.B.

## Data Availability Statement

The data that support the plots within this paper and other findings of this study are available from the corresponding authors upon reasonable request.

## Keywords

analog ReRAM, deep neural networks, inference, in-memory computing, training

Received: February 20, 2025

Revised: April 16, 2025

Published online:

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