# Power Cycling Reliability of Paralleled IGBT Chips Heated with Conduction and Switching Losses

James Abuogo, Josef Lutz, Thomas Basler

► To cite this version:

James Abuogo, Josef Lutz, Thomas Basler. Power Cycling Reliability of Paralleled IGBT Chips Heated with Conduction and Switching Losses. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0063. hal-05077860

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# Power Cycling Reliability of Paralleled IGBT Chips Heated with Conduction and Switching Losses

James Abuogo, Josef Lutz and Thomas Basler

CHEMNITZ UNIVERSITY OF TECHNOLOGY

Reichenhainer Street 70, 09126

Chemnitz, Germany

Tel.: +49 / (371) - 531 37289

E-Mail: james.abuogo@etit.tu-chemnitz.de

URL: https://www.tu-chemnitz.de/

## Keywords

«Switch-mode power cycling test», «DC-mode power cycling test», «IGBT module, paralleled chips», «DBC layout design», «thermal imbalance», «lifetime model»

## Abstract

The results of a power cycling test (PCT) of switches in a commercially available baseplate-less IGBT module with two paralleled chips are presented. The thermal imbalance between the two paralleled chips caused by direct bonded copper (DBC) substrate layout design was found to be the most influencing factor for lifetime of these switches. A modification of the DBC layout is suggested to homogenize thermal loading of the paralleled chips.

## Introduction

In order to increase the current carrying capacity of a semiconductor switch, multiple chips are usually paralleled in a module. These chips need to be integrated with perfect symmetry in the module to avoid imbalanced electrical loading and asymmetric thermal distribution. Otherwise, considerable de-rating has to be done to achieve significant reliability [1]. In many cases, perfect symmetry is never achieved and the paralleled devices are exposed to different thermal stresses.

Asymmetry can be caused either by the variations in electrical parameters of the chip, packaging and connecting circuit or by the differences in cooling conditions of the individual chips (thermal paths below the chips). Transient and static current sharing is mostly influenced by the asymmetry of the stray parameters of the circuit [2], [3] and the spread in device parameters [3], [4]. One of the most dominant the circuit's stray parameters influencing transient current sharing is the

common-source inductance ($L_S$) of the paralleled chips, coupled with the current slew rate ($di/dt$) [5]. Among the device parameters, differences in the on-state collector-emitter voltage ($V_{CE(sat)}$) majorly influences the static current sharing whereas gate threshold voltage ($V_{GE(th)}$) and gate input capacitances influence dynamic current sharing of paralleled IGBT chips [3], [4].

Besides the electrical parameters, mismatch in the thermal resistance ($R_{th}$) of the thermal paths of the paralleled chips also contributes to asymmetry in heating. This asymmetry in $R_{th}$ is mostly associated with the layout design of the DBC and the chip positioning. For instance, the influence of chip placement relative to the top copper layer of the DBC on lateral temperature distribution of chips in an IGBT module was analysed in [6]. Additionally, influence of thermal paths on chip's heating was demonstrated in [7], where the contribution of thermal coupling among paralleled chips in an IGBT module was analysed.

In this work, the IGBT chips packaged in a SEMITOP®4 modules (without baseplate) are subjected to power cycling tests using two approaches: heating with conduction losses only (classical DC-mode) [8] and heating with both conduction and switching losses (switch-mode) [9], [10]. It was found that the most influencing factor on the lifetime of these devices is the temperature imbalance of the paralleled chips arising from chip placement relative to the top-side copper layer of the DBC substrate. Chips with balanced thermal stress achieve higher lifetimes which were comparable to those obtained from the lifetime model presented in [11] and [12], while those with stronger thermal imbalance achieved even lower than 50 % of the expected lifetime. The two test approaches (classical DC-mode and the switch-mode) resulted in similar lifetimes and failure modes.
# Test Principles

## Test circuits and functioning

The circuit diagram for a classical DC PCT for two paralleled IGBTs is shown in Fig. 1. In the test, the devices in phase 1 are heated using conduction losses by operating them in forward conduction mode during the heating interval ($t_{on}$). During cooling interval ($t_{off}$), the current is commutated to the other phases using auxiliary switches and the devices in phase 1 are cooled by a heat exchanger upon which they are mounted.

<figure><img src="image_2.png" /><figcaption>Fig. 1: Classical DC-mode test circuit for paralleled devices</figcaption></figure>

In a switch-mode test, two devices (in this case, two switches with each switch consisting of two paralleled chips) are connected in one phase and are switched alternately at a high frequency. The inductors in the switching loop ($L_{o1}$ and $L_{o2}$) store energy and release it into the DUTs which are turning off. A boosted active clamping (BAC) circuit is used to avoid driving the DUTs into avalanche during turn-off. The BAC partially opens the channel as the voltage is clamped by a TVS diode during turn-off. Fig. 2 shows the circuit for this test principle.

<figure><img src="image_3.png" /><figcaption>Fig. 2: Switch-mode test circuit for paralleled devices</figcaption></figure>

The switching event under clamped inductive switching is shown in Fig. 3 where switching loss of 10.3 mJ is generated under $I_C$ of 50 A. The $V_{GS}$ was switched from 18 V to -5 V.

The test vehicle is a full-bridge 3-phase inverter in a SEMITOP®4 module. Two chips are paralleled for every switch as shown in Fig. 4. The two paralleled chips are tested together as one DUT. A total of 6 modules were tested.

<figure><img src="image_4.png" /><figcaption>Fig. 3: Clamped switching event showing the profiles of $V_{GE}$, $V_{CE}$ and $I_C$</figcaption></figure>

<figure><img src="image_5.png" /><figcaption>Fig. 4: Module under tests showing the placement of paralleled chips of each switch on the DBC layout</figcaption></figure>

## Power losses and sharing

When two IGBT chips are paralleled, in static operation, they share current according to their individual on-state voltage drops ($V_{CE(sat)}$) while in transient operation their current sharing is mainly determined by their gate threshold voltages ($V_{GEth}$), gate input capacitance, transconductance ($g_m$), switching delay time ($t_{delay}$) and gate resistance ($R_G$). Since the same gate driver is used for the paralleled chips, influence of $R_G$ and $t_{delay}$ can be ignored. From the transfer characteristics of the two paralleled chips shown in Fig. 5, there seems to be no significant difference in $V_{GEth}$ and $g_m$ both at low and high temperatures. Therefore, the two chips are expected to share switching losses equally. It is, however, not possible to measure the current flowing through an individual chip in this module without tampering with the packaging.

For the static current sharing, the devices are operated in the positive temperature coefficient (PTC) of $V_{CE(sat)}$ regime according to the output characteristic measured at 25 °C and 150 °C
shown in Fig. 6. With PTC, an imbalance in temperature is expected to be balanced out by redistribution of the current. However, the temperature may not be balanced out completely as the current redistribution stops as soon as $V_{CE(sat)}$ of the two chips becomes equal.

<figure><img src="image_6.png" /><figcaption>Fig. 5: Temperature dependency of transfer characteristics of the paralleled chips (Switch 1)</figcaption></figure>

<figure><img src="image_7.png" /><figcaption>Fig. 6: Temperature dependency of output characteristics of the paralleled chips (Switch 1)</figcaption></figure>

To analyse the extent to which temperature imbalance can be corrected due to PTC of $V_{CE(sat)}$, the temperature dependency of $V_{CE}$ was determined at different currents around the operating current (36 A for each chip) as shown in Fig. 7. It shows that the sensitivity of $V_{CE}$ to temperature is in the range of 0.6 mV/K to 2.3 mV/K depending on the current.

At the same time, the sensitivity of $I_C$ to $V_{CE}$ was determined from the output characteristic at 150 °C as 35.1 A/V (corresponding to $r_{CE}$ of 28.5 mΩ per chip), see Fig. 8. As an example, let's assume that the DBC layout design resulted in a temperature imbalance between the two paralleled chips of 20 K (which will be shown later with the infrared camera measurements). This 20 K imbalance should contribute to a

$V_{CE(sat)}$ imbalance of 32 mV between the two chips when each chip carries 35 A initially (from Fig. 7). To balance out this voltage, the hotter chip should redistribute about 0.56 A (according to Fig. 8) to the cooler chip (PTC of $V_{CE(sat)}$ of Fig. 5). At a common $V_{CE(sat)}$ of 2.3 V (Fig. 6), this translates to a power difference of 2.58 W at the very beginning of the mismatch. With the $R_{th(is)}$ of 0.6 K/W per switch (from test data), the compensation in temperature will be only 1.4 K which is insignificantly lower than the original imbalance caused by the layout design (20 K). This is the reason why both DC-mode and switch-mode tests resulted in similar results, as will be shown later, despite the expectation of a stronger thermal balancing effect in the DC-mode test.

<figure><img src="image_8.png" /><figcaption>Fig. 7: Temperature dependency of $V_{CE}$ under different collector currents for a single chip</figcaption></figure>

<figure><img src="image_9.png" /><figcaption>Fig. 8: Sensitivity of collector current to changes in $V_{CE}$ for a single chip at 150 °C</figcaption></figure>

## Test Conditions

Two tests were performed: switch-mode test and classical DC-mode test. Table 1 shows the test conditions for both tests. In both tests, the maximum junction temperature ($T_{j-max}$) was measured using $V_{CE(T)}$ method with a delay of
150 µs after disconnecting the load current flowing through the respective phase.

<table><caption>**Table I: Test conditions**</caption><thead><tr><th>Parameter</th><th>Switch-mode</th><th>DC-mode</th></tr></thead><tbody><tr><td>ΔT<sub>j</sub> (K)</td><td>80</td><td>80</td></tr><tr><td>T<sub>j-mean</sub> (°C)</td><td>110</td><td>110</td></tr><tr><td>t<sub>on</sub> (s)</td><td>2</td><td>2</td></tr><tr><td>t<sub>off</sub> (s)</td><td>4</td><td>4</td></tr><tr><td>I<sub>C</sub> (A)</td><td>50</td><td>72</td></tr><tr><td>f<sub>sw</sub> (kHz)</td><td>7.6 – 9</td><td>---</td></tr><tr><td>E<sub>sw</sub> (mJ)</td><td>10.3</td><td>---</td></tr><tr><td>L<sub>σ1</sub>+L<sub>σ2</sub> (μH)</td><td>4.1</td><td>---</td></tr><tr><td>P<sub>sw</sub>:P<sub>cond</sub></td><td>2:1</td><td>---</td></tr></tbody></table>

# Power Cycling Test Results

## Lifetimes

The overall test results for these power cycling tests are shown in the plot of Fig. 9. For comparison, the manufacturer's lifetime model for baseplate-less modules [12] has also been shown. The model is described by equation (1).

$$N_f = A_0 \cdot A_1 \cdot e^{\left(\frac{-\Delta T - T_0}{\lambda}\right)} \cdot \Delta T_j^{\alpha} e^{\left(\frac{-\Delta T - T_0}{\lambda}\right)} \dots \\ \cdot e^{\frac{E_a}{k_B \cdot T_{jm}}} \cdot \frac{C + t_{on}^{\gamma}}{C + 2^{\gamma}} \cdot k \quad (1)$$

Here, λ is drop constant of low ΔT extension, α is the Coffin-Manson exponent, E_a is the activation energy, k_B is the Boltzmann constant, C is the time coefficient, γ is the time exponent and k is the chip thickness factor, see [12].

<figure><img src="image_10.png" /><figcaption>**Fig. 9: Lifetime achieved by different switches**</figcaption></figure>

For better visualization, normalized lifetimes for every switching position (referred here as Switches 1 to 6) have been plotted as shown in Fig. 10. It can be seen that switches which have one chip placed on the edge of the topside copper of DBC (Switch 1, Switch 3, Switch 4 and Switch 6) fail earlier than those where both chips have a

significant overlapping edge of the top-side DBC copper (Switch 2 and Switch 5). The bottom DBC copper is common to all the chips in the module, hence presenting similar thermal impedance to all the chips. This means that it is not likely to contribute to thermal imbalance among paralleled chips. These switches can be seen in the module overview of Fig. 4.

Therefore, it seems that the R<sub>th</sub> of the thermal path directly below the individual chips is different. This leads to a difference in cooling conditions of the paralleled chips with the overall effect of an imbalanced thermal loading.

<figure><img src="image_11.png" /><figcaption>**Fig. 10: Lifetimes achieved by different switches**</figcaption></figure>

In order to compare the lifetimes achieved in switching-mode with those achieved in DC-mode, the switch-mode results were normalized to account for cooling during the V<sub>DS-hot</sub> measurement, when switching losses were eliminated. This duration was 500 µs and the switching loss was 78 W (10.3 mJ per clamping event at f<sub>sw</sub> of 7600 Hz) while conduction loss was 39 W (duty cycle was 50 %). Using ANSYS simulation, the drop in temperature was determined to be 2 K. After correction using the lifetime model in [12], the lifetimes of the two test modes appeared similar as shown in Fig. 11.

<figure><img src="image_12.png" /><figcaption>**Fig. 11: Comparison of lifetimes under switch-mode and DC-mode tests**</figcaption></figure>
This implies that the balancing of temperature by
current redistribution between the chips due to
PTC of V<sub>CE(sat)</sub> as expected in DC-mode does not
have significant effect on lifetime of these
devices.

Failure analysis

Most of the devices were found to fail through
solder delamination, see R<sub>th</sub> increase of Fig. 12,
while a few failed by bond wire lift-off (V<sub>CE</sub>
increase in Fig. 13). The test concept did not have
an influence. The devices that failed by bond wire
lift-off are those that achieved the longest
lifetimes (Switch 2 and Switch 5). It seems that
after 80,000 cycles, the devices failed by both
bond wire lift-off and solder delamination, and
the failure condition can be reached by either R<sub>th</sub>
or V<sub>CE</sub> increase. All devices whose lifetimes were
below 80,000 cycles failed by solder
delamination.

<figure><img src="image_13.png" /><figcaption>Fig. 12: V<sub>CE</sub> and R<sub>th</sub> development for a device that failed from solder degradation (here, parameters for Switch 3 tested in DC-mode are shown)</figcaption></figure>

<figure><img src="image_14.png" /><figcaption>Fig. 13: Development of V<sub>CE</sub> and R<sub>th</sub> for a device that failed with bond-wire lift-off (here, parameters for Switch 2 tested in switch-mode are shown)</figcaption></figure>

In order to determine the degradation of
individual chips in the module, scanning acoustic

microscopy (SAM) was carried out. Before test,
all chips and bond wires are visible as shown in
Fig. 14. However, after the test, the solder layer
degradations under each chip are different. Some
chips are still quite clearly visible indicating less
solder degradation while others are largely
invisible indicating severe solder degradation. As
shown in Fig. 15, Switch 5 show degradation
under both chips while in Switch 1, Switch 3,
Switch 4 and Switch 6 the solder under one of the
paralleled chips is more degraded depicting
unbalanced thermal loading during the test.
Switch 2 for the shown module was not tested.
They were tested in other modules though. The
level of degradation of the individual chip (as
shown in Fig. 15) also correlate with the extent to
which the top-side DBC copper overlaps the
chip's edges. Chips with more edges sufficiently
overlapped are less degraded than those whose
edges are not well overlapped.

<figure><img src="image_15.png" /><figcaption>Fig. 14: Scanning acoustic microscope image of the module before test</figcaption></figure>

<figure><img src="image_16.png" /><figcaption>Fig. 15: Scanning acoustic microscope image of the module after test (Switch 2 for this module was not tested but they were tested in other modules)</figcaption></figure>

Besides SAM images, microscopic images were
also made to determine the level of degradation
on the metallization surface of each of the
paralleled chips. For Switch 4, the metallization of one chip (chip 4-2) is more damaged than the other (chip 4-1) as can be seen in Fig. 16. The structure appears to have remained relatively intact for chip 4-1. For Switch 2, there seems to be relatively similar level of damage in the structure for both chips suggesting a more uniform thermal load sharing between the two paralleled chips in this switch. This again corresponds with the influence of top-side DBC copper layout on thermal load sharing.

<figure><img src="image_17.png" /><figcaption>Fig. 16: Microscopic image of the metallization surface of the chips after test. Switches with imbalanced thermal load (e.g. SW4) have metallization of one chip more degraded than of the other. Similar degradation rates can be seen in chips of switches with balanced thermal loading (e.g. SW2).</figcaption></figure>

# Discussion

## Thermal stress sharing

The thermal load sharing among the paralleled chips was determined by using an infrared camera measurement. Chips of Switch 2 and those of Switch 3 were compared. The DBC layout for these two switches are shown in Fig. 17 where switch 2 has both chips placed such that the DBC copper overlaps on both sides of the chips (marked in red). The temperature measurements from infrared (IR) camera shown in this section were determined while the devices were heated in DC-mode. However, heating in switch-mode showed nearly similar temperature distributions. More balanced cooling is expected for the two

chips of switch 2. Switch 3, on the other hand, has only one chip placed such that the DBC copper overlaps on both sides whereas the second chip has only a small edge being overlapped by the DBC top-side copper. The chips of this switch are, therefore, expected to have imbalanced cooling.

<figure><img src="image_18.png" /><figcaption>Fig. 17: Chips and DBC layouts for switches 2 and 3, red lines show edges of the chip with adequate DBC copper overlap</figcaption></figure>

It was found that the paralleled chips in switches 2 and 5 shared the thermal load almost equally with a difference in average $T_{jmax}$ between the chips being smaller than 1 K. Fig. 18 shows the temperature distribution of chips in switch 2 as an example. It was also found that there is a significant imbalance in the thermal load for chips in switches 1, 3, 4 and 6. As an example, Fig. 19 shows the temperature distribution of the chips in switch 3 where a temperature difference as high as 19 K can be noted.

<figure><img src="image_19.png" /><figcaption>Fig. 18: (a) IR camera measurement of temperature distribution for the paralleled chips in switch 2 and (b) comparison of temperature profiles for the two chips (heated in DC-mode)</figcaption></figure>
<figure><img src="image_20.png" /><figcaption>Fig. 19: (a) IR camera measurement of temperature distribution for the paralleled chips in switch 3 and (b) comparison of temperature profiles for the two chips along the shown lines (heated in DC-mode)</figcaption></figure>

Since the two paralleled chips experience different thermal loading, the Palmgren-Miner rule [13] can be applied to determine the degradation of individual chips after end of life. In Palmgren-Miner rule, the thermal stress ($\Delta T_j$) corresponds to a specific expected lifetime ($N_f$). When multiple stress levels are applied simultaneously, then each consumes a fraction of the total lifetime and the lifetime consumptions are superimposed. Fig. 20 shows how Palmgren-Miner rule can be applied for two paralleled chips under different $\Delta T$ values. The percentage degradation for each chip can be calculated using equation (2).

<figure><img src="image_21.png" /><figcaption>Fig. 20: Demonstration of application of Palmgren-Miner rule on degradation of paralleled chips</figcaption></figure>

$$ \% \text{Chip 1} = \frac{N_f}{N_{f1}} \cdot 100; \quad \% \text{Chip 2} = \frac{N_f}{N_{f2}} \cdot 100 \quad (2) $$

As an example, switch 3 in the layout whose thermal distribution has been shown before can be considered. For this switch, the temperature difference between the two paralleled chips is around 20 K. For the average $T_{jmax}$ of 150 °C, one chip can be assumed to attain a $T_{jmax}$ of 140 °C ($\Delta T = 70$ K) and another 160 °C ($\Delta T = 90$ K). Applying the lifetime model [12], chip 1 is

expected to attain a lifetime ($N_{f1}$) of about 50,095 cycles while chip 2 is expected to attain 183,448 cycles ($N_{f2}$). The measured average lifetime ($N_f$) for this switch is around 40,000 cycles (see Fig. 10) which means that chip 1 is 80% degraded while chip 2 is about 20% degraded according to Palmgren-Miner rule. This correlates with the SAM image of the solder that shows more severe degradation for chip 3-1 than for chip 3-2 (Fig. 15).

## Lifetime model for paralleled chips

In order to take the influence of thermal imbalance among paralleled chips on power cycling lifetime into account, a modification of the lifetime model of equation (1) to equation (3) is suggested for the baseplate-less modules with two paralleled chips per switch. A term with the ratio of temperature imbalance between the two chips ($\Delta T_{im}$) to the temperature swing ($\Delta T$) has been included. The parameter $m$ can be determined from test. For this work, $m$ is determined to be 2.3. By testing more devices, $m$ value can be determined more accurately and the lifetime model improved.

$$ N_f = A_0 \cdot A_1 \cdot e^{\left(\frac{-\Delta T - T_0}{\lambda}\right)} \cdot \Delta T_j^{\alpha - e^{\left(\frac{-\Delta T - T_0}{\lambda}\right)}} \dots \\ \cdot e^{\frac{E_a}{k_B \cdot T_{jm}}} \cdot \frac{C + t_{on}^{\gamma}}{C + 2^{\gamma}} \cdot k \cdot \left(1 - m \cdot \frac{\Delta T_{im}}{\Delta T}\right) \quad (3) $$

## DBC layout improvement

It is clear that the difference in thermal stress endured by the two paralleled chips is predominantly caused by the DBC layout design. If one chip is placed such that the DBC's top-side copper overlaps on all the edges of the chip, then the thermal resistance of the heat path directly below this chip is smaller than for one placed such that the DBC copper does not overlap on all edges. Therefore, thermal stress sharing can be improved by having both chips placed such that the top-side DBC copper overlaps sufficiently on all edges for both chips. This is the placement of switches 2 and 5 whose thermal sharing is balanced.

An ANSYS simulation has been performed for switch 3 using device dimensions and material parameters given by the manufacturer in [14] to show the improvement of thermal stress sharing with this minor alteration of chip placement. Fig. 21 shows the original placement of chips for switch 3 and a modification by extending the upper copper layer (gray part) to sufficiently overlap on all edges of chip 3-1. This modification leads to a more balanced $T_j$ between
the two chips. The modification should, nevertheless, take into account the placement of other components such as freewheeling diodes and gate resistors.

<figure><img src="image_22.png" /><figcaption>Fig. 21: DBC layout improvement and ANSYS simulation of thermal sharing for switch 3. Simulation performed under similar conditions as test (Table I).</figcaption></figure>

Conclusion

Power cycling test results were presented for switches in a baseplate-less IGBT module with two paralleled chips per switch. The tests were performed through both the classical DC PCT and the switch-mode PCT methods. The most important factor influencing lifetime was found to be the temperature imbalance between the paralleled chips due to DBC layout design and chip placement. However, the switch-mode test, which offers a higher degree of freedom with respect to the heating/tests conditions, gives the same results as the classical DC-mode PCT. Based on simulations, it was shown that a small modification in the DBC layout design can significantly improve the power cycling reliability of the whole module.

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