<figure><img src="image_60.png" /></figure>

Figure 4.5: Time resolution as a function of the collected charge for neutron irradiated LGADs from different producers (HPK, FBK) with a 50 µm active thickness. These measurements have been made at -30 °C, in the laboratory with a β source using a custom electronics read-out board (not the ALTIROC therefore optimistic with respect to the expected electronics jitter contribution). The typical error bar is about 3 ps. The red line shows that in these conditions better than 70 ps time resolution is obtained at 4 fC

Already, many single pads (> 1000), small arrays of 2 × 2 and 5 × 5 pads from various companies have been measured in the laboratory and test beams, showing an excellent yield. The first matrices of 15 × 15 pads, delivered by HPK, have also been characterized. They show an excellent uniformity both for the operating bias voltage (i.e breakdown voltage) and the low leakage current (see Figure 5.4).

Following almost four years of R&D activities, shared in part with the CMS timing detector and RD50, a first set of criteria for the parameters of the final sensor design has been established, constituting our baseline. These include: 50 µm active thickness, narrow and deep doping profile and a 300 µm slim edge distance with two guard rings. However, some of the parameters will need to be further validated up to the Final Design Review, scheduled for Q4 2021.

### 4.3.2 Front End ASIC

Taking into account the expected TID radiation levels and needed low jitter, the CMOS TSMC 130 nm technology has been selected. The global architecture of the ASIC, called ALTIROC, is similar to the ASICs developed for pixel detectors but with a significantly reduced number of channels and a quite different single pixel Front End optimized for the time measurement. Figure 4.6 presents the general architecture with a matrix of 225 channels organized along columns for the read-out and with common digital electronics at the bottom.
<figure><img src="image_61.png" /><figcaption>Figure 4.6: Global architecture of the ALTIROC ASIC. The schematic of one Front End electronics channel is displayed on top of the channels matrix, with the preamplifier followed by a discriminator, two TDCs, and a digital front end block.</figcaption></figure>

The analog Front End electronics of each channel is the most critical element to reach low jitter. The sensor signal is amplified using a voltage preamplifier. Taking into account the non-negligible duration of the LGAD signal (approximately 1 ns), a preamplifier with about a 1 GHz bandwidth, is enough. The preamplifier is followed by a fast discriminator. The leading edge of the output (Time Of Arrival, or TOA) provides the start of a Time to Digital Converter (TDC) using a Vernier delay line configuration. The stop is given by the clock. This start-stop structure minimizes the power dissipation when hits are absent. The quantisation step is 20 ps, which does not contribute significantly to the expected time resolution. The TOA measurements are restricted to a 2.5 ns window centered on the bunch
crossing. The expected time dispersion of the hits has a r.m.s of 300 ps so that such a window
contains all the hits of the collisions if centered with about 100 ps accuracy with a phase
shifter. The falling edge of the discriminator output provides the stop of a second TDC
(which uses also the leading edge as start), with 40 ps quantisation step, in order to measure
the Time Over Threshold (TOT), which is used as an estimate of the signal amplitude. The
TOT information is used offline to correct the TOA for time walk effect. After correction, the
residual variations are well within ±10 ps. The digital Front End is used to store the time
data up to the reception of a trigger and buffers the data in order to be read by the End Of
Column cells. This buffer is needed to cope with event to event fluctuations in the number
of hits and random arrivals of the triggers.

A four-channel prototype (ALTIROC0), bump-bonded to a sensor of 2 × 2 pads, has first
been characterized [61] to select the preamplifier and discriminator architecture. A second
25 channel prototype, including the complete pixel read-out with the TDC and SRAM, has
been produced. This second ASIC has been characterized in the laboratory first with the
ASIC wire bonded to a specific board (see Figure 4.7), or later bump bonded to a 5 × 5 pad
sensor. This figure also shows preliminary measurements of the jitter and of the TOA as a
function of an injected calibration charge. With the ASIC alone, an input capacitance of 4 pF
and injecting calibration signal, the threshold can be as low as 2 fC, allowing a measurement
of an input charge down to 4 fC. The jitter for a calibration injected charge of 10 fC (4 fC) is
about 15 ps (25 ps) with a pad capacitance of 4 pF. With a LGAD sensor connected to the
ASIC, the measured jitter on testbench is about 55 ps at 4 fC (see Section 6.7) due to the
different input LGAD signal shape. The variation of the TOA versus the input charge, about
300 ps, is compatible with the preamplifier bandwidth. To achieve the target time resolution,
this time walk effect needs to be corrected using the TOT information. The TOT has also
been measured (see Section 6.7) but it is quite sensitive to any coupling preventing its use in
testbeam condition in November 2019². Preliminary measurements with beam show that a
time resolution of 46 ps, i.e a jitter of 39 ps, can be reached with non irradiated sensors with
a charge about 20 fC. This performance is largely dominated by a noise source coming from
the DAQ board discovered after the beam period : with a filtering interface board developed
recently, the noise has been reduced by 35-40 %, so that the testbeam jitter is expected
to be to < 30 ps. Testbeam campaign with a new ASIC version and the interface board is
scheduled in 2020 to validate this expectation.

The common digital electronics must satisfy a wide variety of requirements. It first retrieves
the time information of the matched hits and the luminosity hits sum computed in the End
of Column. The luminosity hits are summed in two different windows, a 3.125 ns window
centered on the bunch crossing and a second one with a larger size configurable by slow
control. In a second step, it formats these data, and provides them to the serializer, which

<footnote n="2">² A output signal of the ASIC (TOA busy) dedicated to the testbeam was used to trigger the external SiPM. This signal induced a strong coupling on the falling edge of the preamplifier output, therefore a distorted TOT distribution)</footnote>
transfers the data on the e-link to the lpGBT. The speed of the serializer can be selected through slow control at 320 Mbit s⁻¹, 640 Mbit s⁻¹ or 1.28 Gbit s⁻¹, in order to maximize the use of the bandwidth. A control unit receives the fast commands from the lpGBT (clock, BCID, L01/L1,...) and through I²C the slow control parameters. A phase-locked loop (PLL) and a phase shifter are used to clean the jitter of the clock and adjust the clocks with a 100 ps step. This allows the time and luminosity windows to be centered on the bunch crossing clock for each individual ASIC. Finally, monitoring blocks are included to measure the temperature and the leakage current.

The next major ASIC iteration, ALTIROC2, will integrate all the functionality of the final ASIC and will have its final size. Triple redundant registers will mitigate against SEE and will be implemented for all control and signals registers but not for the read-out data. The first iteration should be submitted in 2020 and a second iteration one year later. The Final Design Review is planned in Q4 2022.

<figure><img src="image_62.png" /><figcaption>Figure 4.7: Picture of a ALTIROC1 die with 5 × 5 channels wire-bonded on the test board (left) and preliminary measurements of the average time and jitter as a function of the injected charge using calibration injection with one channel of ALTIROC1 (right).</figcaption></figure>

### 4.3.3 Module assembly

After having qualified separately the sensor and the ASIC at the wafer level, they will be connected through a flip-chip bump bonding process. Under Bump Metallization (UBM) will be deposited on the sensor wafer before dicing. UBM and solder bumps will be deposited on the ASIC wafers. The next step of the hybridisation consists in the flip-chipping during which the sensor and ASIC are aligned, heated, and compressed, so that each solder bump melts and provides the electrical contact between the sensor pad and the channel readout. With the large pad size of 1.3 mm × 1.3 mm, solder bump as large as 90 µm can be used, making
the process standard for many companies, contrary to the hybridization of the ATLAS ITk
pixel detector. The bump bonding of the prototypes has been done in collaborating Institutes
and also in industry with ALTIROC1 and 5 × 5 channel sensors (including UBM, bump
deposition and flip-chip). Satisfactory performance results have been obtained, both for
connectivity and mechanical stress. The qualification of the bump-bonding process will be
carried out with the full size ASIC and sensors when the ASICs become available in 2021.
The final design review of the bump-bonding process is planned at the end of 2022.

As shown in Figure 4.3 the bare module is glued to a small flex cable PCB, called the module flex, on which the ASIC signals and the high voltage are wire bonded. The module flex is connected to a long flex cable tail through a mini-connector for the high voltage and a separate connector for the signal transmission to the PEBs.

Taking into account the space constraints, the flex tail is expected to be a two layer design
with a maximum thickness of 220 µm. The longest readout row services 19 modules. As
displayed in Figure 4.8, each flex transfers four types of signals:

* the data to be read out (time information or luminosity) on two differential-pair e-links per ASIC. The speed of the data transmission varies from 1.28 Gbit s⁻¹ for the inner radius modules to 320 Mbit s⁻¹. For the luminosity, the speed is 640 Mbit s⁻¹.

* the fast commands from the lpGBT (clock, L0/L1 trigger, BCID and configuration parameters) and the slow control parameters through I²C.

* the ASIC power supplies (1.2 V), setting a strong constraint on the flex plane resistance to minimize the voltage drop and the power dissipation (< 300 mΩ for the longest flex). Digital and analog supply lines are separated.

* the bias voltage for the sensor (up to 800 V requiring excellent insulation).

The first flex cable prototypes, made of a single piece and longer than required, have been
manufactured in two companies and at the CERN PCB workshop. Preliminary measure-
ments satisfy the data transmission, bias voltage insulation and resistance requirements.

The R&D is still on-going on the design of both flex cables to ensure they satisfy the tight thickness constraint along Z and to identify/develop reliable mini-connectors for both the module and PEB connections. A few companies have been contacted for this specific R&D and the final design review should take place in 2022.

Tests of the glue used to attach the bare module to the module flex are ongoing in close
collaboration with the ITk Pixel community, as the requirements are similar. In a first step,
to exercise the module assembly, heaters that mimic real size modules will be mounted in
summer 2020 and later with real modules (in 2021-2022). This activity will be done in the
framework of the demonstrator activity (detailed in Chapter 14).
## 4.4 Module loading on support structure

<figure><img src="image_63.png" /><figcaption>Figure 4.8: Signal transmitted from the ASICs to the peripheral electronics. Each ASIC has a dedicated e-link for luminosity and time data transmission while the other signals are common to both ASICs. The HV line is connected to the sensor.</figcaption></figure>

## 4.4 Module loading on support structure

The modules are loaded on the cooling support plate using a support plate unit, made in carbon fibre, in which the modules are inserted in pre-defined windows and glued on each side on a small strip. This support unit, which ensures the exact position of each module and the alignment along the *x* and *y* readout row directions, as displayed in Figure 4.9, is screwed on the cooling plate. The modules have a step of 25.5 mm in a given row, corresponding to a 70% overlap between the top and bottom side modules of a layer for the inner ring. In the middle ring this step is 28.4 mm and the overlap 54%. In the outer ring the step is 34.5 mm and the overlap 20%. An independent support unit will be manufactured for each ring to allow for a fast replacement of the rings planned to take place at the surface in the long shutdowns. A thermal conductive grease is used to insure a good contact between the module and cooling plate. A simulation of the thermal behaviour of the system including the best knowledge of the thermal contacts of each material, and including the expected power dissipation of the sensor with radiation and temperature, has been done. The calculation shows that with the baseline cooling plates made of Aluminium, no thermal runaway is observed for the highest power dissipation over about a 25 °C range, guaranteeing safe operation under all conditions.
<figure><img src="image_64.png" /><figcaption>Figure 4.9: View of the modules inserted on the inner, middle and outer ring half disk support units. The modules are glued to the support units of each ring, and the support units screwed to the cooling half disk. The modules are aligned along x or y direction with a step of 25.5 mm in a given row, corresponding to a 70% overlap between the top and bottom side modules of a layer for the inner ring. In the middle ring this step is 28.4 mm and provides 54% modules overlap between top and bottom modules. In the outer ring the step is 34.5 mm and provides 20% modules overlap between top and bottom modules.</figcaption></figure>

## 4.5 Off detector electronics, calibration and luminosity

Figure 4.10 shows the data path from the front-end ASIC to the off-detector backend. Different data and control signals from the flex cable are connected to the PEBs, where the electrical signals are encoded and transmitted via optical link to the off-detector electronics located in USA15.

The off-detector electronics consist of Front End Link eXchange (FELIX) system and Data Handler and will be described in section 10.1.1. The general purpose FELIX receives event data from the on-detector electronics and transmits them to the Data Handler via multi gigabit network. In addition, FELIX interfaces to the TTC system via Local Trigger Interface (LTI) and to DCS for control, configuration and monitoring. Two different data paths are proposed: the main data stream that provides timing information per triggered event and the luminosity stream that provides bunch-by-bunch hit information. The main data stream is read out at the L0 trigger rate (about 1 MHz), while the luminosity stream is read out by dedicated FELIX boards.
### 4.5.1 Peripheral Electronics Boards

With the current design and taking into account the different read-out rows, five different PEB designs are needed for a layer quadrant but identical between quadrants. One PEB receives the data of up to 55 modules, encodes, aggregates and transmits them via optical links at $10.24 \text{ Gbit s}^{-1}$ to the off detector electronics. In the down link direction, at $2.56 \text{ Gbit s}^{-1}$, this board transmits the trigger commands and clock to the ASIC. In addition this board distributes the DC voltage to all ASICs using DC-DC regulators and the High Voltage to the sensors. The board also handles voltage and temperature monitoring, and parameter setting in the ASICs for the detector control system. Taking into account the large numbers of signals with different properties and the high component density, the layout of this board is quite complex and a two-year development phase is still needed.

Most of the components to be used have already been developed by CERN for the LHC upgrades, namely the lpGBTs, the VTRx optical receiver and transmitter, and the bPOL12V converter. A dedicated analogue multiplexer (64 to 1) has been developed also in TSMC 130 nm to support digitization of monitoring signals to the ADC in the lpGBT. The first prototype of this ASIC has been received in December 2019. Due to the strong constraints on the envelope dimension (both in z and r), further development for the flex connection (flex tail integrated in PEB PCB) and high voltage connectors is on-going. A first functional prototype of the PEB is expected by end 2020.

### 4.5.2 Luminosity

Each ASIC can provide the number of hits for each bunch crossing for luminosity measurement. Due to bandwidth, space and cost limitation, these data are transmitted to specific lpGBT on the PEB at $640 \text{ Mbit s}^{-1}$ only for the outer ring. These data are sent to dedicated

<figure><img src="image_65.png" /><figcaption>Figure 4.10: Data transmission paths for the main stream and the luminosity stream.</figcaption></figure>
FELIX boards which sum the number of hits over a large enough region to provide an accurate online luminosity measurement. It is currently planned to divide the luminosity data in sixteen different regions, but the system should remain versatile enough to modify the size of these regions and remove any ASIC not working correctly if needed (for instance an ASIC with too noisy channels creating fake hits)

### 4.5.3 $t_0$ time calibration

The $t_0$ knowledge of each individual channel (about 3.6 million channels) is crucial to achieve the expected time resolution. The irreducible and non deterministic clock contribution to the resolution is expected to be around 15 ps, coming mainly from the lpGBT clock jitter and the additional contribution from the flex cable and ASIC. However this performance assumes that all channels are ideally timed with respect to the bunch crossing clock. The use of HGTD for physics relies strongly on the relative comparison of the time of different channels within an event. Consequently the geometrical (time static) inter-calibration of the $t_0$ of all channels is the most crucial while global time drifts over large regions will have smaller impact on the performance.

Geometric effects can be corrected with the signals provided by the pulser in the ASIC described in Section 6.3.4 (different flex cable length, systematic difference between channels in one ASIC due the imperfect clock tree distribution, etc.) or computed (geometrical time of flight). Regular sets of calibration runs between LHC fills will be used to monitor these calibration constants.

The shift of the 40 MHz clock phase per BCID, and therefore of the $t_0$, can be determined and corrected in-situ using data. Such low frequency clock phase variations can arise in the HGTD, for instance with temperature variations at module level from the CO$_2$ cooling, variations from one lpGBT to another (serving a few modules), or from the known day/night effect of the LHC clock, probably common to an entire HGTD end-cap. The calibration procedure will consist in measuring the inclusive average time of each channel with the data triggered at 1 MHz in the FELIX processor. Depending on the time period of these effects, and on the affected component and area (ASIC, module, group of ASICs of same lpGBT, PEB board), they may be calibrated with a good accuracy. For instance, at the ASIC level, a preliminary study shows that by computing the $t_0$ online, a 20 ps (50 ps) contribution can be reached at low (high) radius for periodic effects with a time period beyond 20 ms. The final calibration will need an additional offline calibration combining the information from many calibration windows.
## 4.6 Power distribution and detector control system

### 4.6.1 HV system

A schematic layout of the high voltage system is shown in Figure 8.1 and detailed in Chapter 8. Each of the 8032 modules should provide a bias voltage in a range from approximately 300 V, at the start of the HL-LHC, up to 750 V, after the detector has been exposed to the expected maximum irradiation levels of 2.5x10¹⁵neq/cm², as detailed in Chapter 5. The irradiation of each module will strongly depend on its radial position in the detector, seen in Figure 4.2, with an expected maximum variation smaller than 15% inside each module. The ultimate goal is to use individual adjustable voltages for each module, to allow for optimal operation. As a compromise between cost and performance, the baseline choice is nevertheless to initially share a supply between on average two sensor modules (having low leakage current at the beginning of Run-4) with an option to later supply individually each module. The multiplexing of a HV channel to modules can be done either in the USA15 services cavern, where the HV power supplies will be located or in the patch-panel region. All HV cables will be routed from the beginning to allow, at a later stage, each module to be supplied by a separate HV channel.

Consequently HV power supplies requirements are to deliver up to 800 V and up to 6 mA current in order to feed simultaneously two modules, keeping a bit of margin on the sensor leakage current. The power supplies will be based on commercial multi-channel rack mounted units located in the service cavern.

Monitoring the leakage current and the TOT as an indicator of the collected charge will give a good estimate of the sensor gain evolution during data taking (between fills), allowing to perform the necessary HV adjustments.

### 4.6.2 LV system

A schematic layout of the Low Voltage power system is shown in Figure 8.2 and detailed in Chapter 8. The LV power supply system needed by the front-end and peripheral electronics will deliver almost 20 kW and will be provided in a three stage system. Bulk power supplies, located in USA15, will provide 300 V DC voltages to DC-DC converters to be placed in the patch panel areas (PP-EC), located around the end-cap calorimeter outer radius surface, and accessible during technical stops and shutdowns. The second-stage multi-channel DC-DC units convert 300 V to 10 V that is distributed to the radiation hard DC-DC converters located on the PEBs. The last stage converts the power to the front-end electronics (ASICs) and the peripheral electronics boards providing mainly 1.2 V DC power but also 2.5 V for the optical receivers/transmitters. The converters of the peripheral boards are based on the bPOL12V, being developed by CERN for the HL-LHC upgrades.
### 4.6.3 Monitoring and Controls

A Detector Control System (DCS) will be implemented to control and monitor the various detector parameters: the power (HV, LV) supplied to the detector; the temperatures of the modules and of the peripheral electronics, the cooling system and the pressure of the $N_2$ used to keep a dry atmosphere inside the detector volume. A Finite State Machine (FSM) structure will be implemented and integrated in the ATLAS FSM tree during data taking, and will allow to operate in stand alone mode during commissioning and maintenance. It provides the tools to monitor the operational parameters of the detector, to bring the detector into any desired operational state, and to signal any abnormal behaviour by allowing for manual and automatic actions. More details are given in Section 10.4.

## 4.7 Mechanics, Services and Infrastructure

The detector mechanics and services were designed taking into account the severe constraints of space to accommodate the detector and the services that need to be routed in the gap between the barrel and end-cap calorimeters. The use of light structures was prioritized to minimize the amount of material in front of the active layers, and to minimize the potential increase of the radiation levels, leading to a weight per end-cap of approximately 350 kg.

The hermetic vessel provides a robust support structure to the detector disks in a cold and dry volume, with radial dimensions of 100 mm < *r* < 1000 mm. It has four main components: the front and back covers, the inner ring and the outer ring (which will hold all the service feedthroughs), as illustrated in Figure 2.4. The front cover is divided in two half disks to allow its manipulation in the presence of the beam pipe. It consists of a honeycomb core placed between two thin carbon fibre reinforced panels to reduce deflection. The thickness of front and rear covers have been optimized to 13 mm and 7 mm respectively. To avoid condensation on the external face of the HGTD vessel during operation, heaters will be placed on the external face of the front and back covers, insuring a minimal temperature of at least 14 °C outside the HGTD vessel. An air gap of 3 mm will be kept between the HGTD detector and the end-cap LAr calorimeter as requested by ATLAS TC to avoid direct thermal contact with the cryostat front face.

Each double-sided layer (two per end-cap) is divided in two half circular disks of 30 kg each with 120 mm inner radius and 920 mm outer radius. This allows the detector installation to be completed later, in case of delays, even when the beam pipe is in place, provided that the back vessel cover and moderator are installed in LS3, when the beam pipe is not in place. The detector concept should facilitate rapid and safe removal of the detector to the surface while minimizing working time in the high radiation environment. This operation is envisaged at each long shutdown of the HL-LHC for the replacement of the innermost or middle rings. The rotation of the two disk layers inside the vessel by approximately 15 to 20°
with respect to each other, as seen in Figure 11.3, provides better integration of the cooling pipes inside the vessel while minimising the regions with zero hits resulting from the dead zones between the readout rows and imperfect coverage in the inner most radius.

The expected maximum power consumption of the detector, operating at -35 °C to reach the required performance, amounts to 40 kW in total (20 kW per end-cap); details of the various components are summarized in Table 11.2. An evaporative CO₂ cooling system of 50 kW will be used and part of its infrastructure and the cooling spare unit will be shared with ITk.

The evaluation of the number of services required to operate the detector, summarized in Table 12.1, and their respective routing design was subject to a careful evaluation and optimisation. This is due to the limited space in the vessel outer ring allocated to the services feedthroughs, in the barrel-end-cap calorimeter gap region and, last but not least, in the ATLAS flexible chains that allow to keep part of the services connected during the opening and closing of the end-cap calorimeters. The detector services routing on the end-cap calorimeter face is shown in Figure 4.11. The cables, exiting in four layers in the feedthroughs region, will merge into one layer at $r > 1.3$ m to fit within an envelope of 17 mm in z. At the outer radius of the end-cap calorimeter, services are routed in various layers in z but narrow slots in $\phi$ to pass in between the Tile fingers, a space also shared with ITk services. A dedicated slot in $\phi$, on the top of the calorimeter, will be used to route four CO₂ cooling pipes with a maximum diameter of 50 mm each. The priority for services installation in flexible chains will be given to optical fibres, cooling pipes, interlock and cooling temperature sensor cables. The other services need to go through fixed cable trays and should be disconnected before the extended barrel calorimeters are moved for maintenance of the ATLAS detector. For that purpose patch panel boxes (PP-EC) will be organised on the end-cap Tile calorimeter outer surface in accessible places. The patch panel boxes will be also used for re-mapping the cables to match connectors on the detector.

## 4.8 Assembly, Installation and Commissioning

The final assembly of the detector and quality assurance, e.g. mounting the modules support frames and peripheral electronics boards into the half circular disks, connecting each flex cable to the respective peripheral electronics boards, and global certification, should take place at CERN from Q3 2024 to Q4 2026 with the participation of several collaborating Institutes. After the assembly, the detector will be transported to the pit. Each end-cap, HGTD A and HGTD C, will be lowered on side A and side C respectively, directly from the surface to the minivans. The final installation of the detector should take approximately 1 month per end-cap and it is planned for Q2 2026 (HGTD A) and Q1 2027 (HGTD C).

Dedicated tools are needed for assembly, lowering, and final installation of the detector. The designs for these tools are still at a conceptual stage and where possible will use synergies
<figure><img src="image_66.png" /><figcaption>Figure 4.11: Side view of HGTD with services routed along the end-cap calorimeter face. The services design is already complete up to the outer most radius of the end-cap calorimeter for the most difficult locations, where some Tile calorimeter fingers are blocked, not allowing an approximate radial orientation of the services. The four cooling pipes are indicated in dark green straight line. The different colours indicate different type of services (HV/LV cables, optical fibres, etc.)</figcaption></figure>

with tools already developed for other sub-detectors. Extenders of cables and CO₂ cooling lines will be installed permanently to operate also the HGTD when ATLAS is in the open configuration.

The overall commissioning will start immediately after the connection of the services to the detector. Access to the detector components during the commissioning should be possible until approximately Spring 2027, close to the expected second end-cap calorimeter closure, giving about 6-months of intense commissioning for the HGTD C.

## 4.9 Next steps towards construction

The goal is to install the HGTD detector during LS3, in April 2026 and January 2027 for the A and C side, respectively. Three main schedule steps are planned:

* 2018-2021 R&D
* 2021-2026 Construction

* 2026-2027 Integration, installation and commissioning

The remaining key R&D steps needed to validate the HGTD design and performance are:

* Demonstrate the performance and radiation hardness of a full size ASIC. The first full size prototype will be available early 2021 (ALTIROC2), and most probably will necessitate a second iteration due to the complexity of the chip.

* Establish the performance of a full size HGTD module of 15x30 channels, that is to say a sensor bump bonded to two ASICs. With ALTIROC2, the hybridisation process will be tested, some modules will be assembled and a detector unit partially equipped during the demonstrator program in 2021.

* Conclude on the maximum fluence that the detector can sustain and consequently optimise the exact radial coverage of each of the 3 detector rings and rings replacement frequency. This tuning will depend on the outcome of the active R&D ongoing with new sensors by different companies, in particular with deep narrow doping implantation, C implantation and with real size sensors, to be delivered mid 2020.

* Validate the performance of CO2 cooling, including detailed thermal runaway studies with full detector size, including the integration and assembly of several modules in a readout row. The mechanical integration aspects will be validated with the heater demonstrator planned in 2020. The full demonstrator, planned for 2021 will include real size modules assembled in a realistic detector row, including flex cables, peripheral electronics and a FELIX Board to validate the entire readout chain up to the DAQ integration.
<figure><img src="image_67.png" /></figure>
# 5 Sensors

## 5.1 Sensor parameters and requirements

The HGTD sensor parameters and requirements are summarized in Table 5.1. The sensors are intended to provide a fast signal in response to charged particles for a time resolution per hit of about 35 ps at the start and 70 ps at the end of lifetime (combined performance with the electronics and other contributions). The minimum charge collected for a MIP should be at least 4 fC and the hit efficiency at least 95%. The granularity should be 1.3 mm × 1.3 mm and the physical thickness 300 µm or less. The sensor should be of total active size of 39 mm × 19.5 mm with 30 × 15 pads and bump-bonded to two readout chips (ALTIROC) of 15 × 15 pads. The inactive edge around the sensor should be maximally 500 µm. The low-gain inter-pad gap should be maximally 100 µm, corresponding to a fill factor of at least 85%. In the baseline scenario, discussed in Chapter 4, the innermost part of the detector ($r < 230$ mm) should be replaced after each $1000 \text{ fb}^{-1}$ and the middle ring within 470 mm $> r > 230$ mm should be replaced at half lifetime ($2000 \text{ fb}^{-1}$) of data-taking during the HL-LHC program. The sensors are then required to sustain a 1 MeV-neutron equivalent particle fluence of maximally $2.5 \times 10^{15} \text{ n}_{\text{eq}} \text{ cm}^{-2}$ and a TID of 1.5 MGy, including a 1.5 safety factor.

The leakage current should be maximally 5 µA per pad, the applied bias voltage maximally $800 \text{ V}^1$ and the power density less than $100 \text{ mW/cm}^2$ at an operation temperature of maximally –30 °C on-sensor. The technology chosen for the HGTD sensors is Silicon Low Gain Avalanche Detectors (LGAD) with a baseline active thickness of 50 µm. The target gain<fnref n="2" /> (charge) is 20 (10 fC) at the start and at least 8 (4 fC) at the end of lifetime.

<footnote n="1">¹ In fact, 50 µm thick sensors should be operated at maximally 750 V (see Section 5.5.2), but a margin is kept to allow for future developments of sensors with potentially different voltage requirements.</footnote>

<footnote n="2">² the collected charge for a PiN of thickness 50 µm is around 0.5 fC</footnote>
<table><caption>Table 5.1: Sensor parameters and requirements.</caption><tr><td>Technology</td><td>Silicon Low Gain Avalanche Detector (LGAD)</td></tr><tr><td>Time resolution</td><td>≈ 35 ps (start); ≈ 70 ps (end of lifetime)</td></tr><tr><td>Time resolution uniformity</td><td>No requirement</td></tr><tr><td>Min. gain</td><td>20 (start); 8 (end of lifetime)</td></tr><tr><td>Min. charge</td><td>4 fC</td></tr><tr><td>Min. hit efficiency</td><td>95%</td></tr><tr><td>Granularity</td><td>1.3 mm × 1.3 mm</td></tr><tr><td>Max. inter-pad gap</td><td>100 µm</td></tr><tr><td>Max. physical thickness</td><td>300 µm</td></tr><tr><td>Active thickness</td><td>50 µm</td></tr><tr><td>Active size</td><td>39 mm × 19.5 mm (30 × 15 pads)</td></tr><tr><td>Max. inactive edge</td><td>500 µm</td></tr><tr><td>Radiation tolerance</td><td>2.5 × 10<sup>15</sup> n<sub>eq</sub> cm<sup>-2</sup>, 1.5 MGy</td></tr><tr><td>Max. operation temperature on-sensor</td><td>-30 °C</td></tr><tr><td>Max. leakage current per pad</td><td>5 µA</td></tr><tr><td>Max. bias voltage</td><td>800 V</td></tr><tr><td>Max. power density</td><td>100 mW/cm<sup>2</sup></td></tr></table>

## 5.2 Low Gain Avalanche Detectors

### 5.2.1 Overview

LGADs are segmented planar Silicon detectors with internal gain as illustrated in Figure 5.1. The gain depends on the doping dose of the multiplication layer as seen in Figure 5.2 and diminishes with radiation fluence as shown in Section 5.5.3. They have been pioneered by the Centro Nacional de Microelectrónica (CNM) Barcelona [5] and developed during the last 5 years within the CERN-RD50 community [4] including collaboration with two other LGAD vendors: Hamamatsu Photonics (HPK, Japan) and Fondazione Bruno Kessler (FBK, Italy). An introduction to the technology is given in Chapter 4. Additional background and details are given in Reference [62].

Three major effects determine the time resolution: time walk from amplitude variations, jitter from electronic noise and “Landau fluctuations” from charge deposition non-uniformities along the particle path. Time walk and noise jitter depend on the type of readout electronics chosen. Both depend inversely on the signal slope (voltage slope at the output of the amplifier) $dV/dt$:

$$ \sigma_{\text{TimeWalk}} = \left[ \frac{V_{\text{th}}}{\frac{S}{t_{\text{rise}}}} \right]_{\text{RMS}} \qquad \sigma_{\text{Jitter}} = \frac{N}{(dV/dt)} \approx \frac{t_{\text{rise}}}{(S/N)} \qquad (5.1) $$

where S refers to the signal which is proportional to the gain, N to the noise, $t_{\text{rise}}$ to the
<figure><img src="image_68.png" /><figcaption>Figure 5.1: (a) Cross section of a 2 × 2 array including a JTE around each sub-pad (SiSi wafer, CNM design) [63]. (b) Microscope photo of an HPK-3.1 15 × 15 array.</figcaption></figure>

<figure><img src="image_69.png" /><figcaption>Figure 5.2: Gain and charge as a function of bias voltage for CNM LGADs with different doping concentration (in the legend “dose”) of the multiplication layer. The “no dose” points are corresponding to a sensor without multiplication layer (classic PiN).</figcaption></figure>

rise time and $V_{th}$ to the threshold voltage. It can be seen that the lowest noise jitter and time walk are achieved with sensors with high signal-to-noise ratio (S/N) and small rise time, i.e. with thin sensors and large gain. Time walk can usually be corrected using time reconstruction algorithms such as constant-fraction discrimination (CFD) or amplitude or time-over-threshold (ToT) corrections. The third effect, referred to as “Landau fluctuation” is due to the non-uniform charge deposition along the particle path leading to time-of-arrival fluctuations. It is a contribution depending on the thickness of the sensor (thin is beneficial) and the setting of the threshold. Adding the three contributions in quadrature yields the overall time resolution. After time walk correction, the noise jitter is the dominating contribution for low S/N and the Landau term takes over for high S/N.

An example for a measured LGAD time resolution is shown in Figure 4.5 as a function
of collected charge, with the time walk corrected using CFD. As expected from Eq. (5.1) the resolution improves with increasing gain (proportional to collected charge) due to the reduced noise jitter. Eventually it levels off to the Landau fluctuation of about 35 ps for 50 µm thickness.

This observation feeds into the plan to operate LGADs at a gain of about 20 before irra-
diation and as close as possible to that value after irradiation given restrictions from the
leakage current, the breakdown voltage, and the noise, including the excess noise from the
multiplication process. The gain target of 20 was chosen since the time resolution fulfils the
HGTD requirement of 35 ps per hit at the start of operation (see Table 2.1) and is improving
only slowly when going to higher gains as seen in Figure 4.5. Moreover, the maximum
achievable gain reduces after irradiation, hence an optimisation of the detector to higher
gains before irradiation would only benefit a short period at the start of operation. At high
fluences, operation at charges down to 4 fC corresponding to a gain of 8 becomes necessary
(see Section 5.5.3).

The field in the Silicon bulk (i.e. no-gain) region should be high enough to saturate the drift velocity of about 100 µm ns⁻¹ for a reduced rise time (the saturation field is 2 × 10⁴ V cm⁻¹, but the charge collection time starts to saturate at 1 × 10⁴ V cm⁻¹).

An LGAD active thickness of 50 µm has been adopted as the best compromise between capacitance and deposited charge (favouring a large thickness) and signal slope and Landau fluctuations (favouring a small thickness). LGADs of 30 µm active thickness have been studied as an option in the past and showed a better sensor-only performance before irradiation, but were discarded due to the higher capacitance and higher power dissipation at similar performance after irradiation compared to 50 µm. Such small active thicknesses are usually achieved by different techniques that all use a thin active high resistivity layer on top of a thicker insensitive Silicon substrate of low resistivity, such as Silicon-on-Insulator (SOI), Silicon-Silicon Wafer Bonding (SiSi) or epitaxial (Epi) wafer techniques.

Figure 5.1(a) shows the cross section of a 2 × 2 LGAD array. Each pad consists of the p-type multiplication layer underneath the $n^+$ implantation, surrounded by a Junction Termination Extension (JTE). The JTE is an $n^+$ implantation that is deeper than the one of the central pad. It controls the electric field at the edges to avoid early breakdown, but also leads to an inter-pad gap with no or reduced gain and hence worse time resolution and hit efficiency in this region. The complete sensor is surrounded by a guard ring (GR). Figure 5.1(b) shows a photo of an HPK 15 × 15 array.

As a dopant for the p-type multiplication layer, Boron (B) is typically used. Additional
Carbon (C) implantation is investigated as candidate technology for improved radiation
hardness. The substitution of B by Gallium (Ga) has been studied as well, but so far has not
demonstrated clear beneficial results, hence it is not considered as a candidate for production
at the moment.
### 5.2.2 LGAD productions

At present, LGADs have been produced in six manufacturing sites, shown in Table 5.2 along with their production capabilities: HPK, Japan; CNM, Spain; FBK, Italy; Micron, UK; Brookhaven National Lab (BNL), USA; and Novel Device Laboratory (NDL), China. Further vendors are interested in LGAD productions.

There are plans to use LGADs in three experiments at the HL-LHC (ATLAS, CMS, LHCb). There has been fruitful collaboration and coordination between ATLAS-HGTD and CMS-ETL [64] with respect to simulations, design, manufacturing and testing.

The design and production of LGADs for HGTD had two distinct phases: an early R&D phase of about 6 years with much of the activities carried out within the RD50 collaboration where the basic parameters were investigated and the suitability of LGADs for large scale application has been determined. The different manufacturers tended to concentrate on different parameters (like multiplication layer doping profile and dose, variation of the types of dopant, thickness). In general, the LGAD sensors produced by different manufacturers appear to perform similarly, with the exception of the leakage current before irradiation, and the bias voltage reach after irradiation.

In the second phase, in which the collaboration has entered, the focus is geared towards the production of sensors for the specific HGTD application, now that the sensor requirements were fixed, and thus the options are reduced. For example, the decision to fix early on the pitch of the pads in the detector arrays to 1.3 mm provided a needed stable basis so that the development of other parts of the detector (electronics, modules, mechanical layout) could proceed. At this point, the need to investigate issues of manufacturing (yield, uniformity, large arrays, fill-factor, under-bump-metalization (UBM<fnref n="3" />), etc.) and operations (bias voltage, power, reliability, breakdown) have become more important.

<table><caption>Table 5.2: LGAD manufacturers and production capabilities achieved to-date. Values in brackets (...) are for ongoing runs.</caption><thead><tr><th>Manufacturer</th><th>Wafer Size [inch]</th><th>Thickness [µm]</th><th>C Implant</th><th>Array 5 × 5</th><th>Array 15 × 15</th><th>Array 30 × 15</th><th>UBM</th></tr></thead><tbody><tr><td>CNM</td><td>4-6</td><td>30 - 300</td><td>x</td><td>x</td><td>(x)</td><td>(x)</td><td></td></tr><tr><td>FBK</td><td>6</td><td>(50) 60 - 300</td><td>x</td><td>x</td><td></td><td></td><td></td></tr><tr><td>HPK</td><td>6</td><td>20 - 80</td><td></td><td>x</td><td>x</td><td>(x)</td><td>x</td></tr><tr><td>BNL</td><td>4</td><td>50</td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>Micron</td><td>4</td><td>100 - 300</td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>NDL</td><td>6</td><td>33 (50)</td><td></td><td>x</td><td>(x)</td><td></td><td></td></tr></tbody></table>

The results in the following have been mainly obtained from the LGAD types shown in Table 5.3. For HPK-3.2 the full depletion voltage and the $V_{BD}$ at -30 °C are very close, this aspect will be optimized in the next prototypes runs as explained in Section 5.8. These runs

<footnote n="3">³ UBM is part of the hybridisation process as explained in Section 7.2.1.</footnote>
include LGAD sensors of HGTD geometry. Many more runs not mentioned here have been studied in addition for R&D purposes. Typically in a run there are sensors of varied nominal inter-pad gaps (IP) or slim edges (SE). For NDL, a run of 33 µm thickness is shown as a prototype, a 50 µm run is ongoing.

<table><caption>Table 5.3: Design, geometrical and electrical properties of LGAD types.</caption><thead><tr><th>Manufacturer</th><th>Name</th><th>Thickness [µm]</th><th>Gain layer dopant</th><th>C implant</th><th>Gain layer depth [µm]</th><th>Gain layer depletion [V]</th></tr></thead><tbody><tr><td>HPK</td><td>HPK-3.1</td><td>50</td><td>Boron</td><td>No</td><td>1.6</td><td>40</td></tr><tr><td>HPK</td><td>HPK-3.2</td><td>50</td><td>Boron</td><td>No</td><td>2.2</td><td>55</td></tr><tr><td>FBK</td><td>FBK-UFSD3-C</td><td>60</td><td>Boron</td><td>Yes</td><td>0.6</td><td>20</td></tr><tr><td>CNM</td><td>CNM-AIDA1/2</td><td>50</td><td>Boron</td><td>No</td><td>1.0</td><td>45</td></tr><tr><td>NDL</td><td>NDL-33µm</td><td>33</td><td>Boron</td><td>No</td><td>1.0</td><td>20</td></tr></tbody><thead><tr><th>Manufacturer</th><th>Name</th><th>Full depletion [V]</th><th>V<sub>BD</sub> -30 °C [V]</th><th>Nominal IP [µm]</th><th>Nominal SE [µm]</th><th>Max. Array Size</th></tr></thead><tbody><tr><td>HPK</td><td>HPK-3.1</td><td>50</td><td>200</td><td>30-95</td><td>200-500</td><td>15 × 15</td></tr><tr><td>HPK</td><td>HPK-3.2</td><td>65</td><td>70</td><td>30-95</td><td>200-500</td><td>15 × 15</td></tr><tr><td>FBK</td><td>FBK-UFSD3-C</td><td>25</td><td>170</td><td>37</td><td>200-500</td><td>5 × 5</td></tr><tr><td>CNM</td><td>CNM-AIDA1/2</td><td>50</td><td>220/50</td><td>37-57</td><td>200-500</td><td>5 × 5</td></tr><tr><td>NDL</td><td>NDL-33µm</td><td>35</td><td>70</td><td>55</td><td>450</td><td>15 × 15</td></tr></tbody></table>

## 5.3 Radiation damage and irradiations

As explained in Section 2.4, the detector has to withstand a total 1 MeV neutron equivalent particle fluence of maximally $2.5 \times 10^{15} \text{ n}_{\text{eq}} \text{ cm}^{-2}$, assuming that the innermost part of the detector ($r < 230 \text{ mm}$) should be replaced after each $1000 \text{ fb}^{-1}$ and the middle ring within $230 \text{ mm} < r < 470 \text{ mm}$ should be replaced at $2000 \text{ fb}^{-1}$. It should be noted that the total fluence is a combination of both charged and neutral hadrons with different contributions in different regions. In the innermost region, the radiation field is roughly equal for neutrons and charged hadrons (Figure 2.15), but the contribution by charged hadrons decreases steeply with radius, so that the field is dominated by neutrons in the outer regions due to backscatter from the calorimeters. The maximum fluence from charged particles is only around $1 \times 10^{15} \text{ n}_{\text{eq}} \text{ cm}^{-2}$, while for neutrons it is $2 \times 10^{15} \text{ n}_{\text{eq}} \text{ cm}^{-2}$. The energy spectrum of protons and pions has a fairly flat maximum between 50 MeV and 10 GeV, whereas the neutron spectrum peaks at about 1 MeV, but has large contributions over a large range from 0.1 eV to 100 MeV (see Appendix A).

Radiation damage in Silicon mainly results in the change of the effective doping concentration, the introduction of trapping centers that reduce the mean free path of the charge carrier, and the increase of the leakage current [4]. However for thin sensors the effect of trapping is reduced due to the smaller electrode distances. For LGADs, one of the main effects is the degradation of gain with fluence at a fixed voltage due to removal of initial acceptors in the
## 5.3 Radiation damage and irradiations

multiplication layer [65, 66], which implies the need to increase the applied bias voltage after irradiation to at least partly compensate for this.

To study the LGAD performance after irradiation, sensors have been irradiated up to fluences of $6 \times 10^{15} \text{ n}_{\text{eq}} \text{ cm}^{-2}$ at various facilities with different particle types and energies that are representative for the ones expected in HGTD. However only results up to $3 \times 10^{15} \text{ n}_{\text{eq}} \text{ cm}^{-2}$ are shown in the following sections. Table 5.4 gives an overview on the facilities, their parameters and maximum fluences as well as Total Ionising Dose (TID) achieved for different LGAD types irradiated. The hardness factor used throughout this document is used for the conversion of the actual particle fluence to the 1 MeV-neutron equivalent fluences. The irradiation campaign was mainly supported by JSI neutrons. Since the quoted fluence at JSI has an uncertainty of roughly 10%, several sensors were irradiated at least for the higher fluences. Then all sensors at the same fluence were tested and the results shown in the following sections are for representative sensors.

First prototypes were irradiated in all facilities except for CYRIC, and it was found that acceptor removal seems to be faster with respect to 1 MeV neutron equivalent fluence after irradiations with 200 MeV–23 GeV charged hadrons than with neutrons [65, 66]. However, CERN PS is in shutdown now until 2021 and access to other high energy hadron irradiation facilities like Los Alamos is limited. Hence results for LGADs with the HGTD geometry presented here are mostly after irradiations with neutrons at Ljubljana and 70 MeV protons at CYRIC. Sensors irradiated at CYRIC also show higher acceptor removal rate than neutron irradiated sensors at the same fluence. These studies will be followed up by irradiations with higher energy charged hadrons at Los Alamos when it becomes available before the end of 2020. Mixed neutron-proton irradiations for a realistic estimation of the performance with the expected final particle composition are ongoing, to do so sensors proton irradiated at CYRIC will be irradiated again with neutrons at JSI.

It should be noted that irradiations at CYRIC with 70 MeV protons led to a maximum TID of 4.0 MGy, i.e. more than the HGTD requirement of 1.5 MGy. To study in more detail the effect of TID such as changes in the surface conditions, presently there are irradiations with X-rays under way at IHEP.

The measurements with irradiated sensors were done after annealing for 80 min at 60 °C, if not noted otherwise. Dedicated annealing studies are presented in Section 5.5.7.

<table><caption>Table 5.4: Irradiation facilities and parameters and maximum achieved fluence and TID, as well as LGAD types irradiated.</caption><thead><tr><th>Facility & Abbreviation</th><th>Particle Type</th><th>Hardness Factor</th><th>TID [MGy] / 10<sup>15</sup> n<sub>eq</sub> cm<sup>-2</sup></th><th>Max. Fluence [10<sup>15</sup> n<sub>eq</sub> cm<sup>-2</sup>]</th><th>Max. TID [MGy]</th><th>LGAD Types Irradiated</th></tr></thead><tbody><tr><td>JSI Ljubljana (n)</td><td>≈1 MeV n</td><td>0.9</td><td>0.01</td><td>6</td><td>0.06</td><td>all</td></tr><tr><td>CYRIC (pCY)</td><td>70 MeV p</td><td>1.5</td><td>0.81</td><td>2.5</td><td>4.0</td><td>HPK-3.1/3.2, NDL FBK-UFSD3-C</td></tr><tr><td>Los Alamos (pLA)</td><td>800 MeV p</td><td>0.7</td><td>0.43</td><td>6</td><td>0.4</td><td>early prototypes</td></tr><tr><td>CERN PS (pPS)</td><td>23 GeV p</td><td>0.6</td><td>0.44</td><td>6</td><td>2.7</td><td>early prototypes</td></tr></tbody></table>
## 5.4 Sensor tests: methodology and experimental techniques

The LGAD sensors have been tested before and after irradiation by various HGTD groups, as well as within the RD50 community.

Electrical measurements including capacitance-voltage (C-V) and current-voltage (I-V) characteristics have been performed on laboratory probe stations. For the probing of large arrays, custom-made probe cards for the simultaneous contact of 5 × 5 pads have been developed. For the measurement of larger arrays like the 15 × 15 single-chip sensor, the probe card is applied sequentially to 5 × 5 sub-blocks. A probe card with 15 × 15 contacts is under development. An alternative is the sequential probing of one single pad after another on a semi-automatic probe station that allows to scan over an arbitrary number of pads in an array, while the neighbouring pads and the guard ring are floating.

The dynamic properties of LGADs, such as charge collection, gain and time resolutions, have been measured in response to ionising particles, both in the laboratory with $^{90}$Sr β particles [62, 65–71] and lasers, as well as in beam tests [10, 67, 68]. Beam tests have been performed by the HGTD community in more than fifteen periods between 2016 and 2020 at the H6 beam line of the CERN SPS [10] with 40 to 120 GeV pions, at SLAC with 15 GeV electrons, at FermiLab with 120 GeV protons, and at DESY with 5 GeV electrons [72]. Data were taken in two modes: stand-alone and integrated into a beam telescope that provided track position information with about 3 µm precision [73].

Most of the measurements on irradiated sensors were performed at the HGTD target on-sensor temperature of –30 °C.

The dynamic measurements in the laboratory and beam tests were all obtained using custom-made HGTD-specific readout boards with an integrated high bandwidth amplifier with a gain of about 10, followed by a second commercial 2 GHz amplifier of gain 10, allowing the recording of the pulse shape of the fast LGAD signals [10, 67] with a high bandwidth oscilloscope (1–2.5 GHz). The noise was measured as the RMS fluctuation of the base line of the oscilloscope trace. It typically amounts to 1.6 mV–2.5 mV (roughly corresponding to a charge of 0.12 fC–0.20 fC) depending on the type and vertical scale of the oscilloscope, the board type, and the physical location. Measurements at test beam facilities tend to be noisier than laboratory measurements since machinery and magnets are operated in the same areas. The performance of the sensors was evaluated with discrete electronics optimized for precision timing, large scale measurements with the ALTIROC as readout were not executed until now since the chip has not yet been available for large-scale sensor testing. However first measurements of the combined sensor-ALTIROC performance on few bump-bonded hybrid prototypes are presented in Section 6.7.2 showing a time resolution under 40 ps. The measurements presented here will be repeated with the ALTIROC as soon as enough chips are available.
## 5.5 LGAD performance before and after irradiation

Position-sensitive scans using red and infrared lasers to deposit charge carriers inside the sensors have been made at various Institutes, using the Transient Current Technique (TCT) setup.

The gain is extracted by dividing the collected charge in an LGAD device by the charge of no-gain PIN diodes of the same thickness without multiplication layer (for MIPs the signal is about 3 ke⁻ or 0.5 fC for 50 µm thickness).

Time resolutions are typically extracted from the spread of the time-of-arrival difference between two sensors when a particle passes through both. For the measurements, either at least two LGADs are used, or an LGAD, a fast Cherenkov counter (based on quartz bars) and a Silicon photo multiplier (SiPM) (with typical time resolutions of about 10 to 40 ps) are used. If at least three devices are measured simultaneously, a $\chi^2$ minimisation is used to obtain the time resolution of all devices. In case only one device under test (DUT) is measured with respect to one reference device of known resolution, the DUT resolution is obtained by subtracting quadratically the reference contribution. Time walk effects are usually corrected for using time reconstruction algorithms such as the CFD, the Zero-Crossing Discriminator (ZCD) or corrections using the amplitude or TOT of the signal [10].

LGAD behavior such as time resolution and collected charge was simulated using the software WeightField 2 (WF2) [74]. The WF2 simulations were tuned using laboratory measurements from different sensor types. Also, the software TCAD sentaurus [75] was used to optimize the design of the sensors for production.

## 5.5 LGAD performance before and after irradiation

### 5.5.1 Electrical characterisation: I-V and C-V

Figure 5.3(a) and Figure 5.3(b) show the I-V and C-V curves of 1.3 mm × 1.3 mm LGAD pads of different vendors and runs, measured with the guard ring (GR) connected to ground. Un-irradiated LGADs from most of the vendors and runs achieve nA leakage current levels or below before breakdown, well below the ALTIROC leakage current limit of 5 µA per pad. The addition of the UBM process at HPK in this prototype run led to an increased leakage current by 2 orders of magnitude with respect to wafers without UBM. The current reaches about 1 nA, which is still safe for operation and expected to improve in future productions. No influence on the C-V behavior was found. The FBK-UFSD3-C sensors with Carbon exhibits currents of about 100 nA, which are higher than HPK Boron-only sensors but are still safely below the ALTIROC limit. After irradiation, the currents of FBK-UFSD3-C become more similar to the other types. The breakdown voltage increases with decreasing multiplication layer dose.
<figure><img src="image_70.png" /><figcaption>(a) I-V for different runs.</figcaption></figure>

<figure><img src="image_71.png" /><figcaption>(b) C-V for different runs.</figcaption></figure>

<figure><img src="image_72.png" /><figcaption>(c) I-V for different types and conditions.</figcaption></figure>

<figure><img src="image_73.png" /><figcaption>(d) V<sub>BD</sub> distribution.</figcaption></figure>

<figure><img src="image_74.png" /><figcaption>(e) Current at 200 V distribution.</figcaption></figure>

Figure 5.3: Measurements of current-voltage (I-V) (a) and capacitance-voltage (C-V) (b) characteristics comparing different vendors and runs, as well as device types and biasing conditions (c). (d) and (e) show the distributions of V<sub>BD</sub> and the current at 200 V for single pads of different wafers of HPK type 3.1 (with and without UBM).
5.5 LGAD performance before and after irradiation

<figure><img src="image_75.png" /><figcaption>Figure 5.4: (a) I-V measurement of 25 pads from an unirradiated HPK-3.2 5 × 5 array without UBM measured with a 5 × 5 probe card at room temperature (all pads and GR grounded). (b) $V_{BD}$ map of a 15 × 15 HPK-3.2 array without UBM measured with an automatic probe station at room temperature (neighbors and GR floating) [76].</figcaption></figure>

Also the range of the "foot" of the C-V curve (i.e. the voltage region where C stays at high values while the multiplication layer is being depleted, starting from the n-p junction at the front) is an indicator of the multiplication layer dose. Foot values between 20 V and 60 V indicate substantial gains, as verified below. The depletion of the bulk (indicated by the sharp fall of the C-V curve) happens rather fast within a few V due to the high resistivity and the small thickness. The end capacitances of about 3 pF–4 pF for 1.3 mm × 1.3 mm LGAD pads (measured with a connected GR) are consistent with active thicknesses of 40 µm–60 µm.

Figure 5.3(c) shows the I-V curves for HPK-3.1 sensors of the LGAD pad and GR with either GR connected to ground (as the pad) or floating. For the single pad sensor, it can be seen that the current through the pad in case of floating GR is roughly the sum of pad and GR current in case the GR is connected. However, the breakdown voltage ($V_{BD}$) where the current increases rapidly, is found not to be affected by the GR biasing condition for single pads. For a pad in an HPK-3.2 array, the I-V curve is found to be almost identical to the one of a single pad in case the neighbors and the GR are connected to the same potential, as measured with a 5 × 5 probe card on a 5 × 5 array (see Figure 5.3(c) and Figure 5.4(a)). However when leaving neighboring pads and GR floating, the current level is increased by 2 orders of magnitude (presumably due to punch-through to the neighbors) and $V_{BD}$ is observed to be reduced from about 250 V to about 190 V. The reduction of breakdown was consistently measured with a probe card when connecting only one channel and an automatic probe station with only one needle (see Figure 5.3(c)). It should be noted that this behavior of shifting $V_{BD}$ in case of floating neighbors and GR was not observed for the 5 × 5 arrays of the CNM-AIDA run. This indicates that it depends on the sensor design and the exact production process.
Probing with an automatic probe station turned out to be a powerful tool to identify individual faulty pads inside an array [76] and is so far the only method to probe 15 × 15 arrays efficiently until the development of a 15 × 15 probe card is finished. In most cases all pads inside an array behave uniformly for HPK-3.1 5 × 5 and 15 × 15 arrays (see Figure 5.4). The mean $V_{BD}$ spread between pads in an array is found to be typically a few V.

The scenario of only a single floating pad in the center of a 5x5 array with the other 24 and the GR connected was also studied with a 5x5 probe card. This was to simulate the behavior of a faulty pad that needs to be disconnected to make the sensor operable. The single floating pad had an influence on the breakdown voltage of all other pads in the array by introducing a shift to $V_{BD}$ lowering it by less than 10 V and producing a more sudden and steeper breakdown.

<table><caption>Table 5.5: Number of tested devices and fraction of good pads and sensors for HPK-3.1/3.2 and CNM-AIDA1 of different sensor types, edge and inter-pad gap designs. An array of 15 × 15 pads corresponds to the final ALTIROC size and half of the full final sensor area.</caption><thead><tr><th>LGAD Type</th><th>Sensor Type</th><th>Nominal Edge [µm]</th><th>Nominal IP gap [µm]</th><th>Sensors tested</th><th>Pads tested</th><th>Fraction of Perfect Sensors [%]</th><th>Fraction of Good Pads [%]</th></tr></thead><tbody><tr><td rowspan="10">HPK-3.1</td><td rowspan="4">Single</td><td>Sum all</td><td>95</td><td>648</td><td>648</td><td>100</td><td>100</td></tr><tr><td>500</td><td>95</td><td>360</td><td>360</td><td>100</td><td>100</td></tr><tr><td>300</td><td>95</td><td>144</td><td>144</td><td>100</td><td>100</td></tr><tr><td>200</td><td>95</td><td>144</td><td>144</td><td>100</td><td>100</td></tr><tr><td rowspan="5">2 × 2</td><td>Sum all</td><td>13</td><td>13</td><td>52</td><td>100</td><td>100</td></tr><tr><td>500</td><td>30</td><td>1</td><td>4</td><td>100</td><td>100</td></tr><tr><td>300–500</td><td>50</td><td>2</td><td>8</td><td>100</td><td>100</td></tr><tr><td>300–500</td><td>70</td><td>2</td><td>8</td><td>100</td><td>100</td></tr><tr><td>200–500</td><td>95</td><td>8</td><td>32</td><td>100</td><td>100</td></tr><tr><td>5 × 5</td><td>500</td><td>95</td><td>19</td><td>475</td><td>100</td><td>100</td></tr><tr><td>15 × 15</td><td>500</td><td>95</td><td>27</td><td>6075</td><td>85.2</td><td>99.5</td></tr><tr><td rowspan="10">HPK-3.2</td><td rowspan="4">Single</td><td>Sum all</td><td>216</td><td>216</td><td>216</td><td>100</td><td>100</td></tr><tr><td>500</td><td>95</td><td>120</td><td>120</td><td>100</td><td>100</td></tr><tr><td>300</td><td>95</td><td>48</td><td>48</td><td>100</td><td>100</td></tr><tr><td>200</td><td>95</td><td>48</td><td>48</td><td>100</td><td>100</td></tr><tr><td rowspan="5">2 × 2</td><td>Sum all</td><td>26</td><td>26</td><td>104</td><td>100</td><td>100</td></tr><tr><td>500</td><td>30</td><td>2</td><td>8</td><td>100</td><td>100</td></tr><tr><td>300–500</td><td>50</td><td>4</td><td>16</td><td>100</td><td>100</td></tr><tr><td>300–500</td><td>70</td><td>4</td><td>16</td><td>100</td><td>100</td></tr><tr><td>200–500</td><td>95</td><td>16</td><td>64</td><td>100</td><td>100</td></tr><tr><td>5 × 5</td><td>500</td><td>95</td><td>6</td><td>150</td><td>100</td><td>100</td></tr><tr><td>15 × 15</td><td>500</td><td>95</td><td>23</td><td>5175</td><td>91.3</td><td>99.8</td></tr><tr><td rowspan="6">CNM-AIDA1</td><td rowspan="3">Single</td><td>500</td><td>37</td><td>84</td><td>84</td><td>69</td><td>69</td></tr><tr><td>500</td><td>47</td><td>39</td><td>39</td><td>95</td><td>95</td></tr><tr><td>500</td><td>57</td><td>42</td><td>42</td><td>100</td><td>100</td></tr><tr><td rowspan="3">5 × 5</td><td>500</td><td>37</td><td>6</td><td>150</td><td>50</td><td>66</td></tr><tr><td>500</td><td>47</td><td>6</td><td>150</td><td>83</td><td>90</td></tr><tr><td>500</td><td>57</td><td>6</td><td>150</td><td>100</td><td>100</td></tr></tbody></table>
HGTD Institutes measured a large number of single pads and arrays from different pro-
ductions, in particular HPK-3.1/3.2 and CNM-AIDA1. HPK also provides their in-house
Quality-Control (QC) results with an automatic probe station (GR floating) of each single
pad they delivered. The HPK results have been verified by HGTD Institutes. Figure 5.3(d)
and Figure 5.3(e) show the corresponding distributions of VBD and the current at 200 V for
all HPK-3.1 single pads on different wafers, with and without UBM, demonstrating a good
uniformity. The mean of VBD for all wafers is 261 V with a spread of 11 V. The per-wafer
spread varies between 5 V and 9 V. No single pad sensor has a VBD of less than 235 V or
more than 285 V. For the current at 200 V, two distinct distributions are found as expected
from the results discussed above: one for sensors without UBM with a mean of 0.17 nA, and
one after applying UBM with a mean of about 10 nA (it should be noted again that the GR
was floating), the spread is found to be about 20%.

However, in terms of performance, sensors seems to be consistent to less than the percent
level. In Figure 5.5 the spread of the C-V measurements for several HPK-3.2 sensors is
shown, measurements were taken in several HGTD Institutes. The foot, which is directly
connected to the doping concentration of the multiplication layer and the sensor gain, shows
a variation which is less than one percent.

<figure><img src="image_76.png" /><figcaption>Figure 5.5: (a) 1/C² curve measurement for 27 HPK-3.2 single pad sensors from different wafers before irradiation. (b) Extracted foot of the 27 HPK-3.2 single pad sensors, showing that the variation of the gain layer doping is half a percent.</figcaption></figure>

Table 5.5 shows the fraction of good individual pads out of all single pads and arrays, defined as having a breakdown voltage above 90% of the expected one for the respective biasing condition of GR and neighbors. Moreover, the fraction of perfect sensors is displayed, which are defined by requiring all pads in a sensor to be good. For HPK, the fraction of good pads turned out to be 99.5–100%. No dependence on the edge design between 200 µm and 500 µm edge was found. The fraction of perfect sensors is 100% for all HPK single pads, 2x2 and 5x5 arrays and 85.2% (91.3%) for HPK-3.1 (HPK-3.2) 15x15 arrays. For CNM-AIDA1 the result
was found to depend on the inter-pad gap parameter (IP): the largest inter-pad gap (IP57) is found to give 100% good sensors and pads, which reduces to about 70% good pads and 50% perfect sensors for the smallest inter-pad gap (IP37).

5.5.2 Operating bias Voltage and self-triggering

<figure><img src="image_77.png" /></figure>

Figure 5.6: Self-trigger rate as a function of threshold in collected charge for several bias voltages. (a): for HPK-3.2 sensor at $4 \times 10^{14} \text{ n}_{\text{eq}} \text{ cm}^{-2}$ of neutron irradiation. (b): same sensor after $2.5 \times 10^{15} \text{ n}_{\text{eq}} \text{ cm}^{-2}$ of neutron irradiation. (c): for FBK-UFSD3-C sensor at $2.5 \times 10^{15} \text{ n}_{\text{eq}} \text{ cm}^{-2}$ of neutron irradiation. (d): for CNM-AIDA sensor at $2.5 \times 10^{15} \text{ n}_{\text{eq}} \text{ cm}^{-2}$ of neutron irradiation. A threshold of 5 mV corresponds to roughly 0.4 fC of collected charge, represented by the vertical red line in the plots. The operating voltage ($V_{op}$) for each is written in the legend, as shown no self-triggering is present at that $V_{op}$.

As mentioned in Section 5.4, dynamic measurements in response to particles have been
performed in the laboratory and beam tests on custom-made HGTD-specific readout boards. The maximum applicable bias voltage plays a crucial role in determining the performance of the sensors before and after irradiation, since the gain depends on the bias voltage, and this dependence changes with irradiation. It is important to realize that for thin sensors the effect of trapping is reduced due to the smaller electrode distances therefore the charge collected from the bulk before charge multiplication does not change much even after irradiation to $1 \times 10^{16} \text{ neq cm}^{-2}$.

The operating voltage ($V_{op}$) is defined as a stable and safe operation voltage at which the sensor has reasonable performance in terms of time resolution and gain. To evaluate it, several aspects are taken into account. At this voltage the sensor can be operated for a prolonged period of time and under a constant flux of particles (close to the LHC repetition rate of 40 MHz) without the risk of inducing breakdown or electrical arcing between the sensor structures (see Section 5.5.7). The noise increase should be less than 20% when compared to lower voltages, plus the signal to noise ratio must be higher with respect to all lower voltages. The maximum leakage current allowed is limited to 5 µA per pad and the power less than 100 mW/cm². Furthermore at this voltage the sensor must not present self-triggering events (events caused by discharges unrelated to particle hitting the detector) with a rate higher than 1 kHz for a trigger threshold of ±5 mV or a collected charge of 0.4 fC. An excessive self-triggering would increase the dead time of the HGTD detector hindering its operation. This was studied in detail for HPK-3.2, CNM and FBK sensors (studies for other types are ongoing). The self-trigger rate increases dramatically if the sensor is operated near the breakdown with gain higher than 30. This statement is valid both for unirradiated and irradiated (with neutrons/protons) sensors of HPK-3.2, CNM and FBK as shown in Figure 5.6. For HPK-3.2 at a neutron fluence of $4 \times 10^{14} \text{ neq cm}^{-2}$ self-triggering is not observed even at higher voltages than the proposed $V_{op}$, then at $2.5 \times 10^{15} \text{ neq cm}^{-2}$ even at the highest voltage no self-triggering is observed since the gain is low. For FBK and CNM no self trigger is observed for $2.5 \times 10^{15} \text{ neq cm}^{-2}$ at $V_{op}$.

Figure 5.7 shows $V_{op}$ as a function of fluence after neutron and proton irradiation for different LGAD types. It can be seen that it increases with fluence up to values over 700 V but never surpassing 750 V for 50 µm sensors.
<figure><img src="image_78.png" /></figure>

Figure 5.7: Vop as a function of fluence after irradiation for different LGAD types for neutron (a) and proton (b) irradiation. The red horizontal line represents the maximum allowed voltage of 750 V as discussed in Section 5.5.7. Solid markers indicate n irradiation (n), open markers p irradiation at CYRIC (pCy).

5.5.3 Collected charge and gain

Figure 5.8 shows the collected charge as a function of bias voltage after neutron and proton irradiation up to $3 \times 10^{15} n_{eq} \text{ cm}^{-2}$ for different LGAD types: HPK-3.2, CNM and FBK-UFSD3-C. Several sensors were tested for each fluence and the results are displayed for a representative sensor, for the maximum fluence two representative sensors are shown for HPK-3.2. The charge at Vop, as defined in Section 5.5.2, as a function of fluence for both neutron and proton irradiations, is shown in Figure 5.9.

It is evident that by going to higher fluences the increase in bias voltage can only partially compensate for the loss in gain due to the acceptor removal. A charge of 4 fC was found to be the lower limit that still satisfies the HGTD science requirements in terms of hit efficiency (see Section 5.5.4) and time resolution taking into account the ALTIROC jitter (see Section 6.7). This level is indicated by the horizontal lines.

The following observations are made for the different types:

a. Baseline 50 µm sensor with higher doping and deep gain layer (HPK-3.2)

HPK-3.2 sensors have a deep and high-dose multiplication layer, which leads to a reduced acceptor removal rate. Hence, this type can reach the target charge of 4 fC up to the HGTD target fluence of $2.5 \times 10^{15} n_{eq} \text{ cm}^{-2}$.

b. 60 µm sensor with gain layer infused with carbon (FBK-UFSD3-C)
5.5 LGAD performance before and after irradiation

<figure><img src="image_79.png" /><figcaption>Figure 5.8: Collected charge as a function of bias voltage for different fluences for HPK-3.2 (a) and at maximum fluence for all vendors (two representative sensors with different performance for HPK-3.2 are shown) (b). The horizontal lines indicate the HGTD lower charge limit of 4 fC at all fluences. Solid markers indicate n irradiation (n), open markers p irradiation at CYRIC (pCy). Measurements were performed at -30 °C except for the pre-rad measurement that was done at 20 °C.</figcaption></figure>

The addition of Carbon in the gain layer reduces the acceptor removal. The required bias voltage is thus lower than for other types to reach the target charge of 4 fC at 2.5 × 10¹⁵ neq cm⁻².

c. 50 µm sensor with high doping concentration (CNM-AIDA)

CNM-AIDA sensors have a high-dose multiplication layer, also this type can reach the target charge of 4 fC up to 2.5 × 10¹⁵ neq cm⁻².

Studies for NDL-33 µm sensors are ongoing.
<figure><img src="image_80.png" /></figure>

Figure 5.9: The charge at $V_{op}$ as a function of fluence for neutron (a) and proton (b) irradiation. At the fluence of $2.5 \times 10^{15} n_{eq} \text{ cm}^{-2}$ two representative sensors with different performance for HPK-3.2 are shown. The horizontal lines indicate the HGTD lower charge limit of 4 fC at all fluences. Solid markers indicate n irradiation (n), open markers p irradiation at CYRIC (pCy). The maximum fluence (neutron + charged hadrons) for HGTD is $2.5 \times 10^{15} n_{eq} \text{ cm}^{-2}$, while the maximum charged hadron fluence for HGTD is $1 \times 10^{15} n_{eq} \text{ cm}^{-2}$.

### 5.5.4 Efficiency

The hit efficiency of LGAD sensors on HGTD-specific readout boards was measured in HGTD beam tests using an external telescope for reference tracks [10]. Figure 5.10 shows the efficiency in the central region of the LGAD pad as a function of most probable charge collected, compiled from 16 different single pad sensors before and after irradiation up to $3 \times 10^{15} n_{eq} \text{ cm}^{-2}$ at different bias voltages. The threshold to accept events with a hit was chosen at a measured noise occupancy of 0.1% and 0.01%, respectively.

It can be seen that a universal curve is obtained, irrespective of fluence, indicating that the charge is the main parameter on which the hit efficiency depends, given a certain noise occupancy. A hit efficiency above 99% is obtained even before the HGTD minimal allowed charge of 4 fC mentioned in Section 5.5.3. The measurements will be repeated with the ALTIROC electronics once available for large-scale testing.

2D efficiency maps are shown in Section 5.5.6 for arrays before and after irradiation. The cross talk between different pads of a 2 × 2 array was also measured and found to be below 1% before and after irradiation.
5.5 LGAD performance before and after irradiation

<figure><img src="image_81.png" /><figcaption>Figure 5.10: Hit efficiency in the central region of the LGAD pad as a function of collected charge at a measured noise occupancy of 0.1% and 0.01%.</figcaption></figure>

**5.5.5 Time resolution**

The time resolution of LGAD devices have been extensively studied in various beam tests [10, 67, 68] and $^{90}$Sr setups [62] on custom-made HGTD-specific readout boards (as stated in Section 5.4 these measurements will be repeated once the ALTIROC is available for large-scale testing). For the rest of the document (other than Chapter 5) the time resolution is not the same as the one presented here with HGTD-specific analog readout boards. Instead, the measured charge (that is independent from the readout) of the sensor was taken as an input to the ALTIROC time resolution vs. charge function (see Figure 2.13). This is to have a more realistic estimate of the final time resolution with the ALTIROC.

On custom-made HGTD-specific readout boards, it has been consistently shown that 35 ps time resolution can be achieved below the breakdown point before irradiation for sensors from all vendors with pad widths up to 1.3 mm and up to 5 pF capacitance [10, 62, 67–71].

The time resolution of HPK-3.2 was measured in the *β*-telescope after irradiation with 1 MeV neutrons at Ljubljana, and 70 MeV protons at CYRIC. The results shown in Figure 5.11(a) indicate that a resolution of 40 ps and better is achieved up to a fluence of $1.5 \times 10^{15} \text{ n}_{\text{eq}} \text{ cm}^{-2}$ except for non-irradiated sensors (because before irradiation the sensor breaks down before saturation of drift velocity, as explained halfway through Section 5.2.1 and shown in Table 5.3). As seen in Figure 5.11(b) a time resolution of around 60 ps is reached for HPK-3.2 and FBK-UFSD3-C sensors for a fluence of $2.5 \times 10^{15} \text{ n}_{\text{eq}} \text{ cm}^{-2}$. CNM-AIDA sensors show a time resolution of 40ps even at the highest fluence. In Figure 5.12 it is shown that the resolution for FBK-UFSD3-C and HPK-3.2 at $V_{\text{op}}$ changes from better than 40 ps at low fluences to 60 ps at the maximum fluence.
<figure><img src="image_82.png" /></figure>

Figure 5.11: Time resolution as a function of bias voltage for different fluences for HPK-3.2 (a) and for all vendors at the maximum HGTD fluence (b) measured on custom-made HGTD-specific readout boards. Solid markers indicate n irradiation (n), open markers p irradiation at CYRIC (pCy). The red line represents the maximum allowed time resolution (70 ps) in the lifetime of HGTD. Measurements were performed at -30 °C except for the pre-rad measurement that was done at 20 °C.

<figure><img src="image_83.png" /></figure>

Figure 5.12: The time resolution at $V_{op}$ as a function of fluence (for neutron (a) and proton (b) irradiation) measured on custom-made HGTD-specific readout boards. The red line represents the maximum allowed time resolution in the lifetime of HGTD. Solid markers indicate n irradiation (n), open markers p irradiation at CYRIC (pCy). The maximum fluence (neutron + charged hadrons) for HGTD is $2.5 \times 10^{15} n_{eq} \text{ cm}^{-2}$, while the maximum charged hadron fluence for HGTD is $1 \times 10^{15} n_{eq} \text{ cm}^{-2}$.
5.5.6 Uniformity, inter-pad gap and edge region

<figure><img src="image_84.png" /></figure>

Figure 5.13: 2D maps of efficiency (left) and time resolution (right) before (top) and after n irradiation to 6 × 10¹⁴ nₐq cm⁻² (bottom) for a 2 × 2 array from CNM-10478-50 as measured in HGTD beam tests [10]. Sometimes only 3 channels were measured. The efficiency was evaluated at a threshold of 3 times the noise. A mean efficiency in the pad center of 99% is maintained up to a threshold of 5 times the noise level. The time resolution for this sensor is 39 ps before irradiation with a spread of 3 ps in the pad center.

One critical parameter of HGTD is the sensor fill factor, corresponding to the portion of the
detector which is able to detect particles efficiently. In the original plans a fill factor of 90%
was chosen, this would correspond to an inactive region between two pads of around 70 µm
for a pad size of 1.3 mm² × 1.3 mm². Furthermore, the dead region at the edge of the arrays
including the guard ring has to be taken into account for the evaluation of the dead area.
<figure><img src="image_85.png" /><figcaption>Figure 5.14: Figure 5.14(a): Inter-Pad distances for several HPK-3.1 sensors. Figure 5.14(b): Nominal vs. measured inter-pad distances for HPK-3.1, HPK-3.2 (before and after irradiation) and CNM sensors.</figcaption></figure>

CNM and HPK provided the HGTD collaboration with multi pad LGAD arrays of different geometries (2 × 2, 3 × 3, 5 × 5, 15 × 15) with different inter-pad and edge distances (see Section 5.2.2). The nominal values quoted by the vendor corresponds to distances between structures in the design of the detector. However it does not reflect perfectly the electric field configuration of the sensors. For this reason the values of inter-pad region and edge distances have to be measured in the laboratory with a focused infra-red laser beam or at test beam facilities.

The sensors were studied at CERN's test beam facility [10]. Thanks to the tracking system it was possible to evaluate the efficiency and the time resolution (using a SiPM as timing and efficiency reference) as a function of the particle hit position. The hit efficiency and time resolution uniformity map for a 2 × 2 array is shown in Figure 5.13 before and after irradiation. It is shown that the hit efficiency is 99% across the pad before and after irradiation, furthermore the time resolution has variation of around 3 ps across the pad center.

In the laboratory the sensors were tested with an infra-red laser of 1060 nm wavelength focused to 10 µm-20 µm FWHM [76]. The light was injected through the sensor's rear opening of the metalization and scanned from one pad to the other. The two profiles of the pulse maximum are fitted with a step function smeared by the laser spot width and the distance between the pads is evaluated. The measured effective distance between the neighboring pads can be estimated as the distance where charge collection efficiency drops to 50% on the first pad and rises to 50% on the neighbor (50%-50% point). The inter-pad scans for HPK-3.1 can be seen in Figure 5.14(a). The measured values are around 40 µm higher than the nominal values quoted by the vendor. An overview of the measured vs. nominal values for the HPK-3.1/3.2 and CNM-AIDA sensors can be seen in Figure 5.14(b).
## 5.5 LGAD performance before and after irradiation

<table><caption>Table 5.6: Fill factor for different effective (i.e. not nominal) IP gap distances.</caption><tr><td>Effective IP gap</td><td>70 µm</td><td>80 µm</td><td>90 µm</td><td>100 µm</td><td>110 µm</td><td>120 µm</td></tr><tr><td>Fill factor</td><td>90 %</td><td>88 %</td><td>87 %</td><td>85 %</td><td>84 %</td><td>82 %</td></tr></table>

As shown in Table 5.6, the lowest measured values per type (roughly 70–90 µm) correspond to fill factors of 87–90%. HPK-3.2 shows an inter-pad gap that is 10 µm–20 µm larger than HPK-3.1 before irradiation. After irradiation of $1.5 \times 10^{15} \text{ n}_{\text{eq}} \text{ cm}^{-2}$ the measured inter-pad gap decreases by 20 µm–40 µm due to increased operating voltage and relatively larger multiplication at the edges of the pads.

The edge area is evaluated in a similar way by scanning over the edge of the sensor pad with a laser. Several types of HPK-3.1 with different edge distances were measured in this way and they all showed a 95%-5% drop from the maximum of around 60 µm showing no distortion induced by slimmer edges. Furthermore the guard ring of the sensor was read out and the width of it evaluated with the same technique. For an edge distance of 200 µm a width of 200 µm was seen. For nominal edges of 300 µm and 500 µm a guard ring width of around 350 µm–400 µm was measured, however the sensor with nominal edge of 500 µm has an additional smaller guard ring that is left floating and cannot be read out.

So far no change in sensor performance (collected charge, time resolution) or fragility was observed for the different IP gaps and edge distances except for a lowered breakdown voltage for HPK-3.1-IP30 sensors in case of floating neighbors.

## 5.5.7 Long term and stability tests

### Long term and high flux

HGTD sensors were typically tested to evaluate the performance at low rate, with a laboratory $^{90}$Sr source, and medium rate, at test beams. Furthermore, they were biased on the scale of several days. Nevertheless, during the running of the ATLAS experiment, the sensors will be operated continuously for days to weeks in a high particle flux. For this reason, the resilience of the sensors was tested by applying high voltage for an extended period of time. To simulate a high flux, an IR laser was pulsed continuously with a frequency of 50 MHz and the intensity of several MIPs on irradiated HPK-3.1, HPK-3.2 and FBK sensors while biased up to a voltage of 750 V. No change in the behavior of sensors was observed in the timescale of several days.
## Sensor breaking and head room

It is important to find a safe bias voltage $V_{op}$ at which the sensors can be operated, as mentioned in Section 5.5.2. During the LGAD R&D phase, these principles were explored with existing sensors listed in Section 5.2.2. As part of the learning curve to define safe operating conditions some of the sensor were broken during testing. Excluding breaking due to mishandling in the large scale lab and beam testing campaign, a few general conclusions can be reached for the four sensor types that were tested in depth.

It was observed that thin sensors would break immediately when surpassing a certain critical voltage $V_{crit}$ which depends on the sensor thickness. The distance between $V_{op}$ and $V_{crit}$ is called bias head room. Sensors with thickness of 50 µm (like HPK-3.2 and FBK-UFSD3-C) would break for bias voltages greater than 750 V. Since the bias voltage to operate the sensors increases with fluence almost all breaking occurred at high fluences. The bias head room can be seen in Figure 5.7 as the difference between the $V_{op}$ and the red line at 750 V. For HPK-3.2 the head room is over 150 V until $1.5 \times 10^{15} \text{ n}_{\text{eq}} \text{ cm}^{-2}$, while at the maximum fluence of $2.5 \times 10^{15} \text{ n}_{\text{eq}} \text{ cm}^{-2}$ it is 30 V, however this is still much higher than the power supply precision. For FBK-C the bias head room is over 100 V even at the maximum fluence. Several studies will be done to assess the sensors resilience at high voltages close to $V_{crit}$ for long periods of time (test already done are described in Section 5.5.7).

After breaking, a burn mark usually appears in the interface between pad and guard ring, most of the time at the detector corner where the fields are largest. This observation motivates future layout studies of the interface of guard ring and multiplication area. Another study investigates operation of the sensors during temperature and humidity changes and at different particle rates. These few general observations motivate us to make the increase of the bias head room between $V_{op}$ and $V_{crit}$ as one of the research areas of the next prototype run.

## Annealing

Most of the measurements with irradiated sensors were done after annealing for 80 min at 60 °C, which roughly simulates the operational conditions in one year of LHC operation since higher temperature accelerates the annealing (the Arrhenius factor between 60 °C and -30 °C is more than $1 \times 10^6$, 80 min simulates hundreds of years at -30 °C, and tens of days at room temperature).

A prolonged annealing study was carried out with CNM-10478-50 and HPK-3.1 samples with an area of 1.3 mm × 1.3 mm to check the performance in case of unpredicted situations where sensors would be exposed for longer times to elevated temperatures or when intentional annealing may be used to reduce leakage current and power dissipation.
5.5 LGAD performance before and after irradiation

<figure><img src="image_86.png" /><figcaption>Figure 5.15: Voltage dependence for different annealing times for HPK-3.1 at 8 × 10¹⁴ n<sub>eq</sub> cm⁻²: (a) collected charge, (b) time resolution and (c) leakage current.</figcaption></figure>

The dependence of collected charge on bias voltage for different annealing times is shown in Figure 5.15(a) for HPK-3.1 samples. It can be seen that the effect of the annealing is limited. There seems to be a decrease of initial acceptors in the gain layer with annealing on a time scale of tens of minutes, but thereafter the charge stays relatively constant. Even if full reverse annealing of deep acceptors takes place, the applied bias voltages are high enough to fully deplete thin detectors and also saturate drift velocity. The effect of annealing on time resolution remains limited (10–20 ps maximal spread at high voltages, with an initial increase and then decrease again) as shown in Figure 5.15(b). A much larger beneficial effect of annealing can be observed on the leakage current as shown in Figure 5.15(c).

There were no significant differences in annealing performance observed between the two producers HPK and CNM. The annealing studies will be extended further to the whole
fluence range, different temperatures and producers, so that an accurate running scenario
can be made.

5.5.8 Leakage current and power after irradiation

In standard Silicon sensors without gain, the leakage current originating from the bulk
increases linearly with fluence. However, for LGADs the situation is more complex due to
the gain and its change with fluence. The operation in gain mode leads to an increase of
the leakage current, which is given by the product of the volume generation current and
the current multiplication factor. As the gain decreases with irradiation and the generation
current increases, the leakage current does not necessarily increase monotonically with
fluence. The leakage current in multiplication mode contributes to parallel noise linearly,
hence it is of high importance to run the sensors at low temperatures since cooling decreases
the leakage current (roughly by a factor of 2 every 7 °C).

The leakage current for 1.3 mm × 1.3 mm HPK-3.2, FBK-UFSD3-C and CNM-AIDA at Vop
as a function of fluence is shown in Figure 5.16(a). The ALTIROC maximum acceptable
current is 5 µA (line in Figure 5.16(a)). All sensors satisfy this requirement up to the highest
fluence. From the current per pad the power density (power/area) can be derived. The
power can be reduced by operating the sensors at low temperature. For the assumed
operating temperature (−30 °C), Figure 5.16(b) shows the measured power density of HPK-
3.2, FBK-UFSD3-C and CNM-AIDA as a function of fluence for Vop. At the required fluence
of 2.5 × 10¹⁵ neq cm⁻² the power requirement is fullfilled. As seen in Figure 5.16(d) the
power for HPK-3.2 reduces by more than 50% for a reduction of 5% in Vop. For the same
Vop variation only a 10-20% reduction in collected charge is present, this allows a certain
elasticity in adjusting Vop. The final power dissipation in HGTD will depend on the sensor
type choice as well as the operational scenario as detailed in Section 5.6.
5.5 LGAD performance before and after irradiation

<figure><img src="image_87.png" /></figure>

Figure 5.16: (a) Leakage current at the operation bias voltage Vop for single pads at -30 °C as a function of fluence for HPK-3.2, FBK-UFSD3-C and CNM-AIDA irradiated with 1 MeV neutrons (solid markers) and 70 MeV protons (open markers). The horizontal line represents the ALTIROC maximum acceptable current of 5 µA. (c) is the same quantity but evaluated at 95% Vop.

(b) Power density as a function of fluence at the operation bias voltage Vop at -30 °C [69, 70]. The horizontal line represents the maximum acceptable power of 100 mW/cm². (d) is the same quantity but evaluated at 95% Vop.

In (a), (b), (c), (d) at the fluence of 2.5 × 10¹⁵ neq cm⁻² two representative sensors with different performance for HPK-3.2 are shown. The maximum fluence (neutron + charged hadrons) for HGTD is 2.5 × 10¹⁵ neq cm⁻², while the maximum charged hadron fluence for HGTD is 1 × 10¹⁵ neq cm⁻².
## 5.6 Operational aspects and bias voltage evolution in HGTD

As shown in Section 5.5.3, the bias voltage needs to be increased with increasing fluence, which is a function of radius and integrated luminosity (i.e. period over lifetime) in HGTD. Monitoring of the leakage current and the TOT as an indicator of collected charge will give a good estimate of the gain evolution during operation, providing the information needed to perform the necessary adjustments to the bias voltage.

For a first scenario, it is assumed that the detector is operated at operating bias voltage $V_{op}$ (see Figure 5.7). The expected dependence of the fluence on the radius (Figure 2.14) and the required bias voltage $V_{op}$ for the increasing fluence permits a prediction of the bias-voltage distribution as a function of radius. This is shown in Figure 5.17 for different integrated luminosities for HPK-3.2 sensors. It shows that the ability to connect several nearby modules to the same bias supply allowing a 10% variation in the bias to modules on one bias supply will be limited. Note that the exact behavior depends on the sensor type chosen since different sensor types require different bias voltages for the same performance (see Section 5.5.3).

A study was made to take into account the variation of fluence across the 15x30 chip, which is around 3 cm of radial difference between opposites pads in the HGTD geometry. The fluence variation for the maximum fluence $2.5 \times 10^{15} n_{eq} \text{ cm}^{-2}$ (which is the case presenting the maximum variation) is around $3 \times 10^{14} n_{eq} \text{ cm}^{-2}$ for the innermost ring, around $2.5 \times 10^{14} n_{eq} \text{ cm}^{-2}$ for the middle ring and around $1 \times 10^{14} n_{eq} \text{ cm}^{-2}$ for the outer ring. This is reflected to a change in $V_{op}$ of around 50V in the inner ring, around 30V in the middle ring and around 20V for the outer ring. In terms of performance the collected charge change from one edge of the sensor to the other is from 1 fC to 2.5 fC, which is not sufficient to cause self-triggering in the less irradiated pads. Therefore if the most irradiated edge of the 15x30 array is operated at $V_{op}$ (to achieve 4 fC at $2.5 \times 10^{15} n_{eq} \text{ cm}^{-2}$) there will be no self-triggering issues (and around 6.5 fC) on the pads at the other edge of the array.

## 5.7 Summary of present sensor design

Through the R&D program of the last few years, which involved six large LGAD suppliers, several LGAD designs have been investigated. A recommendation for the final design choices will be a “snapshot” taking into account the fact that some of the options need more investigation. So the choices will be tilted towards conservative performance and operations, making use of the operation Voltage $V_{op}$ of Figure 5.7.

* Thickness of the high resistivity bulk

**50 µm:** compared to thinner detectors, higher collected charge at high fluence, more resistant to breaking (as shown in Section 5.5.7).
<figure><img src="image_88.png" /><figcaption>Figure 5.17: $V_{op}$ as a function of the radius for different integrated luminosities for HPK-3.2 sensors. The sudden changes at 2000 fb$^{-1}$, 3000 fb$^{-1}$ and 4000 fb$^{-1}$ corresponds to the replacement of the inner and middle ring.</figcaption></figure>

* Gain layer doping profile

**Narrow and deep shows improved radiation hardness:** however, the performance before irradiation is degraded due to the low breakdown voltage. A compromise between performance before irradiation and radiation hardness needs to be developed.

* Adding Carbon to the dopant in the gain layer

**C implantation is a promising candidate that shows improved radiation hardness.** Noise and time resolution need to be understood. Moreover, it is not available yet by all vendors. Further studies are ongoing.

* Inactive distance between pads (inter-pad gap)

**80–120 µm effective inter-pad gap is feasible before irradiation.** With irradiation, the performance improves due to increased operating voltage and relatively larger multiplication at the edges of the pads. Further optimizations are ongoing.

* Slim edge distance

**300 µm:** Studies show same performance as samples with wider edge.

* Covering the pads with metal

**Complete metal cover of pads:** sensors with pads fully covered with metal showed better performance in terms of collected charge than sensors with large non-metal openings.

With this selection of parameters, the science goals will be reached up to the HGTD target fluence of 2.5 × 10$^{15}$ n$_{eq}$ cm$^{-2}$. More studies after high energy charged hadron irradiation for the innermost radius will be performed once the irradiation facilities are available again.
## 5.8 Roadmap for future sensor productions and activities

In previous years, several vendors already produced LGAD prototype runs with HGTD geometry that were studied by the sensor Institutes and demonstrated the general feasibility to fulfil the HGTD requirements as described above. In 2020, further R&D geared towards production will follow to consolidate and potentially further improve the radiation hardness and to optimize several geometrical layout issues.

The upcoming R&D will focus on the following:

* Produce first full-size 30 × 15 HGTD sensors (4 × 2 cm²) to demonstrate the feasibility and provide sensors for the HGTD demonstrator program (see Chapter 14).

* Optimize the inactive inter-pad distance without affecting yield and sensor performance.

* Implement an inactive edge of 300 µm as default.

* Optimize the LGAD technology for improved radiation hardness (reduced acceptor removal), bias voltage head room and reduced power dissipation.

* Conduct irradiation campaigns with high energy charged hadrons at Los Alamos, as well as mixed neutron-charged hadron irradiations.

* Repeat the performance after irradiation with the ALTIROC readout chip once enough prototype assemblies are available.

* Establish the robustness of LGADs under stressful operating conditions.

* Improve breakdown between guard ring and pad area.

To this end, the following R&D and prototype runs are planned in 2020 with various vendors:

* **HPK:** A 2nd shared ATLAS-CMS prototype run is ongoing and expected to finish in the middle of 2020. The main purpose is to optimize the doping concentration in the multiplication layer of HPK-3.2 to improve timing performance before irradiation. 4 doping splits with varying concentration are planned. Furthermore, full size pseudo-30 × 15 HGTD sensors (i.e. 2 closely placed 15 × 15 sensors diced out in one piece) are implemented. The default inactive edge will be 300 µm.

* **FBK:** An R&D run is ongoing to optimize the doping concentration of Carbon and to combine the beneficial effects of both Carbon and the deep implant of Boron (like HPK-3.2). Simulation of this combined technology predicts an enhanced radiation hardness due to reduced acceptor removal. Furthermore, a prototype run with large size sensors is planned.
5.8 Roadmap for future sensor productions and activities

* CNM: CNM has transferred its LGAD line to 6" production. A first 6" shared ATLAS-CMS prototype run is ongoing and expected to finish in the middle of 2020. Real 30 × 15 HGTD sensors with 300 µm inactive edge are implemented. Further tests on carbon implantation, fabrication in high resistivity epitaxial layers and possible further tests on Gallium implantation are planned.

* *Novel Device Laboratory (NDL) and Zhonghuan Advanced Semiconductor Materials Co.:* Further runs will be conducted in 2020 to produce sensors with baseline 50 µm active thickness, try higher Boron doping to improve radiation hardness, optimize the JTE to improve the breakdown voltage and optimize the inter-pad design.

* *Institute of Microelectronics of Chinese Academy of Sciences (IME):* first runs in 2020 to produce sensors with baseline 50 µm active thickness, implement Carbon implantation.

After this extended R&D and prototype phase and based on the understanding of the design issues solved, the sensor SPR will start Q3 2020, then the PDR will be submitted in Q1 2021, followed by a market survey and the FDR in Q4 2021. The sensor pre-production will take place March to August 2022, followed by the production from January 2023 to October 2024 (as seen in Figure 15.3).
<figure><img src="image_89.png" /></figure>
# 6 Front-end Electronics

This chapter describes the required performance, design, and latest prototype testing of the ASIC chip, ALTIROC, that will be bump bonded to the LGAD sensor. It will have 225 readout channels, thus two ASICs will read out each LGAD. The main challenge in the design of this ASIC is the fact that it needs to have a small enough contribution to the timing resolution, in order to match the excellent performance of the LGAD. As introduced in Section 4.2.2, this contribution comes mainly from the time walk and the jitter. The first one will be addressed by applying a correction based on the fact that the variations in the time-of-arrival (TOA) of the pulse are related to the time-over-threshold (TOT); this is presented in Section 6.3.2. The most critical aspect concerning the jitter is the design of the analog front-end electronics, which are composed of a voltage preamplifier followed by a fast discriminator. The measured TOA and time-over-threshold are digitized using two time-to-digital converters (TDCs), and stored in a local memory at the channel level. An end-of-column (EOC) logic is implemented to collect the information for each of the 15 columns (with 15 pads each). The ASIC common digital part is composed of different blocks necessary to generate and align the clocks, receive the slow control commands to configure the ASIC and transmit the digitized data.

Two iterations of this chip have been produced and tested so far: the first, ALTIROC0, integrated four pads in a 2 × 2 array, with the analog part of the single-channel readout: the preamplifier and the discriminator. The results of the test beam and test bench studies performed on this version of the ASIC can be found in [61]. The second iteration, ALTIROC1, consists of a 5 × 5 pad matrix, in which the digital components have been added to the single-channel readout.

The requirements imposed by the data taking conditions, the sensor and the targeted performance are presented first in Section 6.1. The ASIC architecture is described in Section 6.2, first going through the single-channel architecture and then the entire ASIC. Section 6.3 describes in detail the design of the single-channel readout electronics, followed by the description of the ASIC common digital part in Section 6.4. The radiation tolerance is described in Section 6.5 and the power distribution in Section 6.6. The performance results obtained so far in test bench and test beam are described in Section 6.7. The description of the monitoring can be found in Section 6.8. Lastly, a brief account is given of the future steps towards the completion of the design and testing of the ASIC in Section 6.9.
## 6.1 General requirements

The requirements of the ASIC can be divided into two types. On one side the considerations regarding the operational environment of the ASIC, its powering and electrical connections. These requirements are summarized in Table 6.1. The second group concerns the ASIC performance, driven by the targeted time resolution. A summary of these requirements is presented in Table 6.2.

* The ASIC will have to withstand high radiation levels and, as in the case of the sensors, some ASICs will have to be replaced during the HL-LHC period. As they are designed in pure CMOS technology, they are mainly sensitive to the TID. The expected radiation levels have been presented in Section 2.4, considering a 2.25 safety factor for the electronics leading to a maximal TID of 2.0 MGy (see Figure 2.14).

* Each single-channel readout needs to fit within the sensor pad, with sides of 1.3 mm. It will be capable of handling up to 5 µA leakage current from the sensor without degrading the ASIC performance

* Because the signal from the sensor will degrade due to the effects of irradiation, it should be possible to set the discriminator threshold for small enough values of input charge. The minimum threshold (2 fC) should provide an efficiency above 95% for an input charge of 4 fC (although with a jitter larger than 25 ps). To enable the possibility to set such low thresholds, the cross-talk between channels should be kept below 5%.

* The target for the electronics is to be able to read out signals from 4 fC up to 50 fC throughout the HGTD lifetime.

* The electronics jitter for an input charge of about 10 fC is required to be smaller than 25 ps, i.e smaller than the dispersion induced by the Landau fluctuations on the deposited energy which limits the time resolution to 25 ps at large sensor gain. Such charge is equivalent to the deposited charge of a MIP in a 50 µm thick LGAD with a gain of 20. A detector capacitance of about 4 pF is considered. The contribution to the time resolution from the TDC should be negligible and leads to a 20 ps TDC bin for the TOA measurement and a 40 ps TDC bin for the TOT measurement. The time walk should be smaller than 10 ps over the dynamic range after correction.

* The TOA and TOT information are transferred to the data acquisition system only upon L0/L1 trigger reception with latency up to 35 µs [77], therefore necessitating a large size memory. The trigger rate depends on the final scheme adopted. It will be 1 MHz for an L0 trigger, or 0.8 MHz (resp. 0.6 MHz) for an L1 trigger in an L0/L1 scheme with an L0 at 2 MHz (resp. 4 MHz).

* The global phase adjustment of the clock should be guaranteed to a precision of 100 ps in order to properly center the 2.5 ns measuring window at the bunch-crossing.
* The ASIC will need to handle the information to perform the luminosity measurement, computing the number of hits per ASIC on a bunch-by-bunch basis. To limit the global bandwidth required, the information of only a subset of all the ASICs is used. The current proposal is to use the sensors located at 470 mm < *r* < 640 mm, or equivalently 2.4 < |*η*| < 3.5. The use of both layers will not provide a significant increase in coverage with respect to one of the layers, but the redundancy aids in estimating and reducing the systematic uncertainty on the measured luminosity and provides contingency in the event of failures in the instrumentation.

* Finally the ASIC power dissipation should be kept as low as possible, in order to limit the size required for a single CO₂ cooling unit (for more details on the cooling system see Section 11.3).

<table><caption>Table 6.1: Geometrical, environmental, electrical and power requirements for the HGTD ASIC.</caption><tr><td>Pad size</td><td>1.3 × 1.3 mm²</td></tr><tr><td>Voltage</td><td>1.2 V</td></tr><tr><td>Power dissipation per area (per ASIC)</td><td>300 mW cm⁻² (Total: 1.2 W)</td></tr><tr><td>e-link driver bandwidth</td><td>320 Mbit s⁻¹, 640 Mbit s⁻¹, or 1.28 Gbit s⁻¹</td></tr><tr><td>Temperature range</td><td>-40 °C to 40 °C</td></tr><tr><td>TID tolerance</td><td>2.0 MGy</td></tr><tr><td>Full Chip SEU Upset probability</td><td>&lt; 5%/hour</td></tr></table>

<table><caption>Table 6.2: Performance requirements for the HGTD ASIC. The values given for the noise, minimum threshold and jitter have been specified considering a detector capacitance $C_d = 4$ pF.</caption><tr><td>Maximum leakage current</td><td>5 μA</td></tr><tr><td>Single pad noise (ENC)</td><td>&lt; 3000 e<sup>-</sup> = 0.5 fC</td></tr><tr><td>Cross-talk</td><td>&lt; 5%</td></tr><tr><td>Threshold dispersion after tuning</td><td>&lt; 10%</td></tr><tr><td>Maximum jitter</td><td>25 ps at 10 fC<br>70 ps at 4 fC</td></tr><tr><td>TDC contribution</td><td>&lt; 10 ps</td></tr><tr><td>Time walk contribution</td><td>&lt; 10 ps</td></tr><tr><td>Minimum threshold</td><td>2 fC</td></tr><tr><td>Dynamic range</td><td>4 fC–50 fC</td></tr><tr><td>TDC conversion time</td><td>&lt; 25 ns</td></tr><tr><td>Trigger rate</td><td>1 MHz L0 or 0.8 MHz L1</td></tr><tr><td>Trigger latency</td><td>10 μs L0 or 35 μs L1</td></tr><tr><td>Clock phase adjustment</td><td>100 ps</td></tr></table>
## Data transmission bandwidth requirements

The required bandwidth of the readout e-link of each ASIC strongly depends on the radial region it covers, as shown by the distribution of the average number of hits per ASIC in Figure 9.4. The number of bit per hit is 19 as described in Section 6.3.5.

Each module consisting of two ALTIROC ASICs is connected via a flex cable to a Peripheral Electronics Board (PEB), described in Chapter 9. The PEB transfers digital signals from the flex cables to optical fibres connected to the back-end DAQ. Flex cables for modules placed at a radius above 320 mm also carry two differential e-links with luminosity data. For error-free data transmission at the bandwidths required by the expected HGTD data volume, the PEB uses the low-power GigaBit Transmission chip (lpGBT [78]). A dedicated buffer is needed in each ASIC to average the rate variation and match the best speed of the e-link drivers/lpGBT transceiver inputs:

* The largest average hit rate at small radius does not exceed 20 hits per ASIC and per event, equivalent to a rate of 500 Mbit s⁻¹ (not including header). In the current design a bandwidth of up to 1.28 Gbit s⁻¹ was considered for the innermost radius ASICs (up to r ≃ 150 mm), taking into account a considerable safety margin. However if further studies confirm this, a lower maximum bandwidth could be considered, thus reducing the number of necessary lpGBTs.

* For larger radii, a 320 Mbit s⁻¹ bandwidth can be used.

* For the luminosity measurement, the 12 bits of data for the counts in the larger and smaller window is expanded to 16 bit using the 6b8b encoding (see Section 6.2.1). Therefore a 640 Mbit s⁻¹ e-link driver and lpGBT speed is needed.

## 6.2 ASIC architecture

With an area of 19.9 mm × 21.7 mm, the largest part of the chip will be occupied by the channel matrix: each pad being 1.3 mm × 1.3 mm, arranged in a matrix of 15 × 15 channels. The channel matrix will thus have an area of 19.5 mm × 19.5 mm; the additional space is needed to accommodate the end-of-column logic and the common digital blocks.

This section presents an overall description of the three main structures of the ASIC:

* the single-channel readout cell, which is repeated 225 times. It integrates the preamplification, the discrimination and the digitization of the hits as well as the local storage (or buffering) of the digitized data until an L0/L1 trigger is received.

* the EOC logic which performs the readout of the 15 columns and transfers the data to the trigger data and luminosity processing units.
* the ASIC common digital part which formats the digitized data before sending it to the peripheral off-detector electronics that will be described in Chapter 9. This stage also contains common cells such as a phase shifter, a Phase-Locked Loop (PLL) and a fast command decoder that will be described in Section 6.4.

The ASIC has been designed using 130 nm TSMC<fnref n="1" /> technology. Simulations have been performed using the 130 nm TSMC design kit provided by CERN. The TSMC 130 nm technology has been tested up to 4 MGy [79]. A radiation hard digital library is not available for this technology and the design uses the standard library. However the ASIC has been designed to ensure its radiation hardness as described in Section 6.5.

### 6.2.1 Channel architecture

A conceptual schematic for the single-channel readout is presented in Figure 6.1. Each readout channel will consist of a preamplifier followed by a discriminator, both of which are critical elements for the overall electronics time performance. A detailed characterization of the preamplifier is presented in Section 6.3. The time of the pulse will be determined using a discriminator that follows the preamplifier using a fixed threshold. As a consequence, a time walk correction needs to be applied in order to account for the dispersion in the TOA due to the different pulse heights. Since the time walk will be corrected using a Time Over Threshold architecture (described in Section 6.3.2), two TDCs are necessary to digitize the discriminator output. The first is for the digitization over 7 bits of the TOA, which corresponds to the position of the rising edge of the discriminator output. The range used is 2.5 ns, and it will be done with a bin of 20 ps. The second TDC will be used for the digitization over 9 bits of the width of the discriminator output. The bin and range of the TOT-TDC will be 40 ps and 20 ns respectively. Further details on the TDCs are presented in Section 6.3.3.

<figure><img src="image_90.png" /><figcaption>Figure 6.1: Schematic of the single-channel readout electronics. Two main blocks are identified, the analog and the digital part. The input pulse from the sensor enters the preamplifier on the left. The TOA and TOT data are read out by the column bus on the right.</figcaption></figure>

<footnote n="1">¹ TSMC stands for Taiwan Semiconductor Manufacturing Company.</footnote>
The output of the analog read-out is processed by the digital stage providing two different measurements: time and luminosity. The 16 bits of the time measurement data, combined with 1 bit for a hit flag, are then stored in a local memory (named *hit buffer*). The content of this buffer is processed by a triggered-hit selector circuit on arrival of an L0/L1 trigger signal, so this memory should allow latencies of up to 35 µs. If a trigger signal is received, the information is passed on to a secondary buffer named *matched hit buffer*, where it remains until it is retrieved for transmission to the common digital part. These local memories are further described in Section 6.3.5.

In order to measure the online bunch-by-bunch luminosity, each ASIC will report the sum of hits within two different time windows. A schematic drawing of the windows is shown in Figure 6.2. The two windows W1 and W2 are centred at the expected arrival time of the particles from the collisions with their length adjustable via configuration parameters. The window W1 is 3.125 ns wide while the second window W2 is adjustable in length in steps of 3.125 ns, and will count the number of particles arriving before and/or after those from the collisions. This sideband will provide valuable information about the background, as described in Section 10.3.4. The window generator is a control unit within the logic at the end of each column that contains a 4-bit counter running at 640 MHz and synchronized to the 40 MHz clock (both provided by the phase-shifter further described in Section 6.4.1). The length and alignment are adjustable via configuration parameters, and are performed with the phase-shifter located in the common digital part (further described in Section 6.4.1). These parameters will be optimised based on operational experience.

<figure><img src="image_91.png" /><figcaption>Figure 6.2: Illustration of the time windows used for counting hits for the luminosity data. The smaller window (W1, in red) is 3.125 ns wide and is centred at the bunch crossing time. The width and relative location of the larger window (W2, in blue) can be set in steps of 3.125 ns through the control parameters.</figcaption></figure>

The luminosity measurement is done in three steps. For the first step, performed at the single-channel level, the output of the discriminator is passed through two programmable windows to determine whether the hit happened inside these windows. The way this is done is further described in Section 6.3.6. Secondly, the number of hits per column is computed by the EOC logic, and thirdly the data is transferred. These last two steps are described in the next section and in Section 6.4.

Lastly, there are four 8-bit configuration registers per channel. They are read/written by the
slow control unit through a Wishbone bus. The configuration registers allow configuring
several features of the TDCs, to enable/disable the discriminator and preamplifier, and to
configure the per-channel threshold correction of the discriminator.

### 6.2.2 Readout architecture

Figure 6.3 shows the conceptual design of the entire HGTD ASIC with 225 channels. The channel matrix is represented on the top part by 15 × 15 small squares. The schematic of a single channel, as presented in Figure 6.1, is repeated for each small square. The readout of the channels is done by column, through an EOC cell, drawn at the bottom of the matrix. The information is passed on to the trigger and luminosity processing units. A diagram of the main ASIC common digital part is presented at the bottom.

A fast command unit receives the fast commands from the central Trigger Data Acquisition system (TDAQ) through an lpGBT chip. These commands are 8-bit long<fnref n="2" /> and are received in series at 320 Mbit/s, one per bunch crossing. The communication between the fast command unit and the lpGBT chip is done through two lines. One is for serial data, and the other to transmit a clock of 320 MHz which will be used, not only to establish the communication between the lpGBT and the ASIC, but also as a source clock from which all the internal clocks needed to operate ALTIROC will be generated. The 320 MHz clock from the lpGBT is divided by 8 and passed to a phase-locked loop (PLL) which produces clocks of 40 MHz, 80 MHz, and 640 MHz. These clocks will be centred with an accuracy of 97.6 ps using a phase shifter. Further details about the clock generation and distribution are given in Section 6.4.1.

The fast commands are processed by the Trigger Data Processing Unit (TDPU) which is responsible to read the timing information from the pixel matrix, pack these data into frames and serialize them. It is composed of a 12-bits bunch crossing counter to generate a bunch crossing identifier (BCID), a trigger table to store temporally trigger events for later processing, a data formatting unit that packs data into frames, and a serializer. More details are given in Section 6.4.2.

The TDPU performs two tasks in parallel, one is to process incoming triggers and the other to readout data associated to a triggered event from the pixel matrix. In the incoming trigger processing task, the TDPU generates an internal trigger signal and a trigger identifier (TrigID) when an L0/L1 accept command is received. These triggers are transmitted immediately to all the pixels. Then each pixel checks if it has data associated to that trigger event. If they have, the data are transferred, together with the corresponding TrigID to a secondary in-pixel buffer. They remain there until they are retrieved by the TDPU. The TrigID is used to tag a BCID with a trigger event with only 5-bits, so it is not necessary to send the 12-bits of the BCID to the pixel matrix. The trigger table is a FIFO that stores

<footnote n="2">² The 3 most significant bits contain a synchronization pattern (110), the 5 less significant bits the command code.</footnote>
<figure><img src="image_92.png" /><figcaption>Figure 6.3: Schematic of the full HGTD ASIC. The top part represents the 15 × 15 channel matrix, while the bottom part shows the ASIC common digital part.</figcaption></figure>

the correspondence between each BCID and its associated TrigID. In the readout task, the TDPU is looking for a new entry in the trigger table. When a new one is found, it requests to the EOCs to retrieve and store the data from the pixels related to the TrigID fetched from the table. Then, the data are moved into the Hit Data Formatting unit, where they are packed into frames, serialised and transmitted to the peripheral on-detector electronics through e-links. The transmission speed of the e-link will depend on the radial position of the ASIC, and will be set via an Inter-Integrated Circuit bus I²C to one of three values: 320 Mbit s⁻¹, 640 Mbit s⁻¹, and 1.28 Gbit s⁻¹. It is connected to an equal speed port in the lpGBT, described in Sec. Section 9.1.1.

As mentioned previously, the luminosity measurement is carried out in three steps, each one in a different region of the ASIC. The first step consists in determining whether the hit occurred within one or both of the time windows. This windowing process is done at the single-channel level and was described in the previous section. The windows are generated in the logic at the end of each readout column, instead of at each channel, in order to reduce power consumption. By distributing them to the channels as a clock tree, one can compensate for the delays introduced by the long metal lines needed to reach each channel and to minimize the skew between the channels in a column. In the second step, the result is collected at the EOC logic, where the number of hits in the column for each window is computed. This information is passed on to the Luminosity Processing Unit (LPU), that calculates the total number of hits in the ASIC within S1 and S2 windows. Then it performs
the subtraction of the hits within the larger and the smaller window (S1-S2). The 8 bits of S1 and the 8 bits of S2-S1 are truncated to respectively 7 and 5 bits to reduce the total bandwidth. In the third step, each 12 bits packet is transferred to the luminosity serialization where data is encoded (6b8b), leading to frames of 16-bits long. These are serialized at a rate of 40 MHz and sent to the lpGBT through a 640 Mbit s⁻¹ e-link. The measurement and data transmission can be enabled/disabled by accessing one of the configuration registers. As explained previously in Section 6.1, not all ASICs will be performing luminosity measurements. Disabling the data transmission on those not performing the measurement will allow to save power.

The common digital part also includes several programmable digital-to-analog converters (DACs) to generate different bias currents for all analog blocks of the ASIC, a band-gap, a temperature sensor and some configuration registers. The latter are used to set different features of the ASIC, such as the values of the DACs, the transmission rate of the hit data and the PLL bias currents or frequencies. As mentioned previously, 4 configuration registers are also present for each channel. The I²C link mentioned previously is also used to readout all configuration registers in order to check if single-event upsets (SEUs) have corrupted their content, and to retrieve information from the control unit about the status of the ASIC; the information related to data corruption is then passed on to the hit serialization.

The design of this ASIC is on-going but several elements (preamplifier, discriminator and TDC) were already produced and tested as described in Section 6.7.

## 6.3 Single-channel readout electronics

This section describes in detail the design of the single-channel readout electronics. As introduced previously, it will receive the pulse signal from the LGAD sensor, and transmit the TOA, TOT and luminosity information to the EOC logic. The preamplifier design is first described in Section 6.3.1, while the discriminator is presented in Section 6.3.2. Concerning the digital blocks, the working principle of the TDCs is presented in Section 6.3.3, while the designs of the local memory and the luminosity processing unit are presented in Section 6.3.5 and Section 6.3.6 respectively.

### 6.3.1 Preamplifier

The jitter due to electronics noise is often modelled as

$$ \sigma_{\text{jitter}} = \frac{N}{dV/dt} \sim \frac{t_{\text{rise}}}{S/N} \qquad (6.1) $$

where N is the noise and $dV/dt$ the slope of the signal pulse, of which S is the amplitude and $t_{\text{rise}}$ the rise time. Due to the fact that the noise scales with the bandwidth (BW) as
$\sqrt{BW}$, while the rise time grows with the amplitude as S/BW, the most common timing optimisations rely on using the fastest preamplifier.

Most timing measurements in test beam have been carried out with broadband amplifiers, which are voltage sensitive amplifiers with 50 Ω input impedance. Some prefer using a trans-impedance configuration, and timing optimisation has been published for such configuration [10, 67]. However, in silicon sensors such as LGADs, the preamplifier speed is not so crucial, due to the fact that the current duration is not negligible with respect to the preamplifier rise time and to the capacitive impedance of the sensor.

The jitter with a voltage sensitive amplifier configuration can be calculated under some simplifications and assuming that the detector current is a short pulse with a characteristic time $t_d$. The corresponding input charge $Q_{inj}$ is the integral of this current over $t_d$. The jitter of a preamplifier can then be estimated through the following formula:

$$ \sigma_{\text{jitter}} = \frac{e_n C_d}{Q_{\text{inj}}} \sqrt{\frac{t_{r,pa}^2 + t_d^2}{2t_{r,pa}}} \qquad (6.2) $$

where $e_n$ is the noise spectral density and $C_d$ the detector capacitance. The sensor drift time $t_d$ and the preamplifier rise time $t_{r,pa}$ are combined in quadrature as an estimation of the total speed. It can be seen that the jitter is minimized when the preamplifier rise time is equal to the sensor drift time: $t_{r,pa}=t_d$. In that case, the jitter can be written as:

$$ \sigma_{\text{jitter}} = \frac{e_n C_d \sqrt{t_d}}{Q_{\text{inj}}} \qquad (6.3) $$

However this dependence is small: for instance for $t_d \sim 600$ ps, reducing or increasing by a factor of two $t_{r,pa}$ with respect to the optimal matching value will deteriorate the jitter by approximately 12%. Therefore to minimize the jitter, the sensor should have a small capacitance, a small $t_d$ and provide a large charge. For a 50 µm thick active LGAD in HGTD, a $C_d = 4$ pF has been estimated when fully depleted (see Figure 5.3(b)); typically $t_d \sim 0.6$ ns, and for a gain of 20, it would give a $Q_{inj} \sim 10$ fC.

The design of the ALTIROC uses a voltage sensitive preamplifier, presented in Figure 6.4. This is a broadband preamplifier with a cascoded Common Source configuration, consisting of an input transistor (M1) and a follower transistor (M2). Both the gain and the noise depend on the current that flows into the input transistor, which is why the drain current $I_d$ is tunable through configuration parameters. For this purpose two current sources are combined: $I_{d1}$ is a fixed current source of 150 µA, while $I_{d2}$ can be varied from 0 to 850 µA. Simulation studies have shown that the improvement is small when increasing this current beyond 600 µA. The rise time of the preamplifier can be modified in order to optimize the jitter. This is done through the pole capacitance, $C_p$, that is tunable by slow control (from 0 to 175 fF) allowing to set the preamplifier rise time between 300 ps and 1 ns. As for the fall time
<figure><img src="image_93.png" /><figcaption>Figure 6.4: Schematic for the preamplifier implemented in the latest ASIC design, ALTIROC1.</figcaption></figure>

of the preamplifier output, it depends on the input impedance of the preamplifier ($R_{in}$) that is given by the resistance $R_2$ divided by the open loop gain of the preamplifier. The value of the input impedance depends therefore also on the drain current $I_d$. For example, for an $I_d$ = 300 µA and $R_2$ = 25 kΩ, the input impedance is about 1.6 kΩ. The value of the resistor $R_2$ can be either 15 kΩ or 25 kΩ. It can also absorb the sensor leakage current, estimated to be below 5 µA per channel after irradiation. The leakage current would cause the output of the preamplifier to drift by an amount of the order of $R_2 \times I_{leak}$. The threshold of the discriminator that follows the preamplifier must then be changed accordingly using the 10-bit DAC threshold common to all the channels and the 7-bit DAC threshold correction that is integrated for each channel allowing a correction within ±50 mV as described in the next section.

The preamplifier architecture, followed by a fast discriminator, has been simulated with various detector capacitances and considering that 1 MIP would deposit a 10 fC charge. A calibration signal was used in the simulation, and the result was convoluted with different input LGAD signals. The LGAD pulses for different levels of irradiation obtained using the Weightfield2 software [80] and presented in Figure 4.4(b) were used as input, and the obtained preamplifier pulses are presented in Figure 6.5.

### 6.3.2 Discriminator

The measurement of the TOA of the particles is performed by a discriminator that follows the preamplifier. The measurement of the time of the rising edge of the discriminator pulse provides the TOA, while that of the falling edge, combined with the TOA, provides the TOT. To ensure a jitter smaller than 10 ps, the discriminator is built about a high speed leading edge architecture with hysteresis to avoid re-triggering effects. Two differential stages with small input transistors are used to ensure a large gain and a large bandwidth
<figure><img src="image_94.png" /><figcaption>Figure 6.5: Post layout simulation of the preamplifier output using as input the simulated LGAD signals presented in Figure 4.4(b) for a non-irradiated sensor and after irradiation with neutrons.</figcaption></figure>

(aprox 0.7 GHz). The threshold of the discriminator ($V_{th}$) is set by a 10-bit DAC common to all channels (LSB=0.4 mV). An additional 7-bit DAC (LSB=0.8 mV) allows to make threshold corrections individually for each channel in order to compensate for differences amongst them or for different values of leakage current.

The time walk is the effect that larger signals cross a given threshold earlier than smaller ones (see [62]). The time-over-threshold is defined as the width of the discriminator signal which is a proxy to the signal amplitude and can be used to correct for the time walk effect as illustrated later in the prototype performance section (see Section 6.7).

### 6.3.3 TDC

The target quantisation step of the TDC of the TOA is 20 ps, and is below the gate-propagation delay in 130 nm technology, thus the Vernier delay line configuration is employed. This configuration consists of two lines, each composed of a series of delay cells implemented as differential shunt-capacitors, controlled by a voltage signal ($V_{ctrl}$) that determines their delay. The timing resolution is determined by the difference in the delays of the cells in each line. The TOA will be measured within a 2.5 ns window centred at the bunch-crossing. As already mentioned before, the hits have a time dispersion with an RMS of about 300 ps, so that such a window aligned with a precision of 100 ps contains all the hits. The maximum conversion time for a 2.5 ns range must be below 25 ns so that hits happening in the following bunch crossing can be converted.

A graphic representation of the working principle of the TDC can be found in Figure 6.6. In the slow line, the control voltage fixes the delay of each cell to 140 ps, while on the fast line it fixes it to 120 ps. The START signal (rising edge of the discriminator) enters the slow delay line while the STOP signal (next rising edge of the 40MHz clock) enters the 'fast' delay line. Although initially the START signal is ahead of the STOP one, each delay-cell stage brings
<figure><img src="image_95.png" /><figcaption>Figure 6.6: Graphic representation of the working principle of the TDC. The drawing on the top left shows how the START and STOP signals are generated, the first with the discriminator output upon event detection, the second corresponding to the next clock edge. The gray area indicates the 2.5 ns detection window. On the top right, the schema represents the TDC, with the 'slow' delay line (140 ps cells) that propagates the START signal, and the fast delay line (120 ps cells) in which the STOP signal is propagated. The difference between delays defines the bin. After each cell the signals are compared (QX), and the bin number provides the converted measurement.</figcaption></figure>

them closer by an amount equal to the difference between the slow and fast cell delays, i.e. 20 ps. The number of cell stages necessary for the STOP signal to surpass the START signal represents the result of the time measurement with a quantisation step of 20 ps. A cyclic structure is employed to reduce the number of cells per line and results in a smaller occupied area. Since the time measurement is initiated only upon signal detection (instead of at each time-measurement window), the reverse START-STOP scheme is used as a power-saving strategy. The conversion time of a 2.5 ns input time interval is 21 ns, finishing before the next bunch crossing.

The TOT TDC provides a 9-bit digitization of the discriminator width, on a 20 ns range. It uses an additional coarse delay line made of 160 ps delay cells to extend the measurement range to 20 ns, while a Vernier delay line provides the requested fine resolution of 40 ps. The START and STOP signals are given by the rising edge and by the falling edge of the discriminator respectively.

As mentioned before, the delay cells of both TDCs, are implemented as differential shunt-capacitor voltage-controlled delay cells. Their delay is set by a control voltage ($V_{ctrl}$) that controls the load of the cell. Three control voltages are necessary to control the three delay
lines used in the TDCs: $V_{ctrl_fast}$ to set the cell delay of fast cells to the desired value of 120 ps, $V_{ctrl_slow}$ to set the cell delay of slow cells to 140 ps for slow cells and 160 ps $V_{ctrl_coarse}$ to set the cell delay of slow cells to 160 ps. These control voltages are generated by three Delay-Locked Loops (DLLs) located in the periphery of the ASIC and built around a classical architecture (phase comparator and a charge pump current). Additional open-loop per-channel trimming is present in order to minimize timing-resolution between channels due to cells mismatches. Each DLL uses the very same delay cells as those used in the corresponding controlled delay lines: this ensures that the TDC steps (hence LSB) don't vary neither with PVT (Process Voltage Temperature) parameters nor under irradiations. Besides, as DLLs are locked onto the 40 MHz clock, the TDC steps (120 ps, 140 ps or 160 ps), only depends on the 40 MHz clock precision and of the number of delay cells, meaning that no calibration for both TOA and TOT LSB is needed. The only needed calibration is the one that gives the TOA versus the TOT in order to correct for the time walk. This calibration will be done using the internal pulser (described in Section 6.3.4) and physics events to have a reference for the time of arrival of the events. An internal phase shifter is then used to align events within the 2.5 ns acceptance window.

The TDC power consumption is dependent on the time-interval being measured. For the TOA TDC 2.5 ns (full dynamic range), the average power consumption over the 25 ns measurement period is about 5.2 mW. It will become 3.5 mW for the time-interval equal to half dynamic range. Thanks to the reverse START-STOP operation, the power consumption of the TDC is much lower in the absence of a hit over threshold. This results in an average power consumption per channel of 1.1 mW for both TDCs, assuming a time interval uniformly distributed (1.25 ns average) and a maximal channel occupancy of 10%.

### 6.3.4 Internal pulser

An internal pulser, common to all channels, is integrated to mimic input charges in phase with the 40 MHz clock. The pulser consists of a programmable DC current (tunable with an internal 6-bit DAC) that flows continuously through 50 kΩ resistor (R) until it is interrupted by a command pulse that shorts the resistor to ground (see Figure 6.7). A voltage step (Vstep) equal to $-R \times I_{DAC}$, is then generated and sent through the selected pixel internal 200 fF test capacitors ($C_{test}$) of the selected pixel. The input charge ($Q_{inj}$) is equal to $C_{test} \times V_{step}$ and the dynamic range goes from 0 to 250 mV or 0 fC up to ~50 fC (LSB = 0.8 fC). The absolute value of $C_{test}$ and R are known within 10% and its relative value between channels is within 1%. The pulser can be calibrated. The DC voltage ($R \times I_{DAC}$) is output on a dedicated PAD and so can be measured as a function of the 6-bit DAC. This PAD can also be used to inject voltages from an external generator. This PAD will be kept in the final ASIC allowing pulser calibrations during the test of the production chips.

This pulser will be used to intercalibrate the value of the phase of each channel (see Section 10.2) and also to align the thresholds of each discriminator. The command pulse
(encoded in the lpGBT fast command elink) is therefore distributed as a clock tree inside the ASIC. Since the absolute phase calibration should be measured by injecting a large charge (in order to make the time walk negligible), there is no need to know the absolute value of the injected charge with an accuracy below 10%. The pulser will also be used to perform a first order time walk correction by measuring the TOA as a function of the TOT for various input charges. The final calibration will be done using physic events that give the reference of the time of arrival.

On the test bench, the pulser is used to measure the performance of the ASIC. The input signal allows also the characterisation of the front end read-out but does not reproduce the jitter performance when having an LGAD signal as input as the signal time duration can not be neglected. Figure 6.8 shows the post layout simulation of the preamplifier output using as input a simulated LGAD signal and a Dirac signal. For the same input charge, the simulation predicts a jitter larger by a factor 1.65 when using as input the LGAD signal instead of the calibration signal. This difference is mainly attributed to a difference in the rise time. The impact on the amplitude is much smaller and a decrease of about 10% is predicted.

<figure><img src="image_96.png" /><figcaption>Figure 6.7: Pulser principle that shows the common 6-bit current DAC used to set the input charge as well as the pixel $C_{test}$ capacitor.</figcaption></figure>

### 6.3.5 Hit processor

Each electronics channel is composed of an analog part, already described, and a digital part. The latter is composed of three main blocks, as can be seen in the schematics of Figure 6.1. The hit processing unit, or hit processor, temporarily stores the data related to a hit and selects hits of events that have been triggered. The main circuit is the hit buffer which is composed of a memory of 1400 positions. Such size will allow to cope with trigger latencies of 35 µs, using one position per bunch crossing.

The size of each buffer position is 19 bits: 7 for the TOA, 9 bits for the TOT, 1 bit for the hit flag, 1 bit for detection error (CRC) and 1 bit for the TOA overflow. The hit flag bit indicates
<figure><img src="image_97.png" /><figcaption>Figure 6.8: Post layout simulation of the preamplifier output using as input a simulated LGAD signal and a Dirac signal for an injected charge of 10 fC.</figcaption></figure>

if a hit has been detected in the bunch crossing. The buffer is implemented as a circular memory in order to store data in a continuous way. It has two pointers for memory reading and writing. A control unit in the hit buffer increments the write pointer in one unit each bunch crossing. During data taking, the pointer goes from 0 to 1399 in scenario where the trigger latency is 35 µs and then goes back to position 0. If the needed latency is 10 µs, the write pointer is incremented from 0 to 399. The latency is set through a configuration register at the periphery. In each bunch crossing the control unit checks if a hit occurs. In case of a hit, the TOA and TOT measured by the TDCs in the analog front-end electronics stage are stored into the buffer and the hit flag of that position is set to 1. If not, the hit flag is set to 0 and no values are written in the TOA and TOT fields in order to save power.

The hit buffer architecture is built about a two-port SRAM design. This configuration allows simultaneous Read/Write operations within the same clock period. Six partitions of 256 words are used in order to limit the lines capacitance and to optimize the power consumption. The power consumption simulated taking into account parasitic elements and assuming a 10% occupancy with an L0 trigger signal at 1MHz is evaluated to be 1.3 mW at a temperature of 25°C and a voltage of 1.2V. This power dissipation decreases slightly down to 1.2 mW with a 2.5% occupancy. Concerning radiation tolerance, this SRAM architecture is less sensitive to SEU than DRAM as nodes levels are regenerated by the back to back inverters: ionizing radiations will significantly change the amount of charge on nodes but, assuming they don't completely flip the bits, the node levels will be restored to their normal value quite quickly, either by the feed-forward or by the feedback inverter. However, in order to improve the radiation tolerance, the memory cells are designed with large HVT transistors and with strong substrate/well contacts, sacrificing density for more robust and radiation tolerant
design. The full active area of the hit buffer is 720 µm × 1080 µm.

The reading pointer is handled by the next stage in the hit processing unit, the *trigger hit selector*. It reads the hit buffer as soon as it receives a trigger. The accessed position of the buffer is always the consecutive one of the latest written position in order to implement the latency. Only the output of the discriminator is checked. If it is high, it means that there is a matched hit and the TOT and TOA are temporarily stored in the matched hit buffer. They can remain there for longer times than the latency. The TOT and TOA data stored in this second buffer are tagged with a 5-bits identifier *TrigID* provided by the TDPU to indicate to which bunch crossing and trigger event they are associated to. The matched hit buffer operates as an average rate memory, storing the hits of triggered events until ready to be transferred. It will allow to cope with event-to-event fluctuations in the number of matched hits and to keep the bandwidth of the ASIC lower than 1.28 Gbit s⁻¹. It is implemented with a FIFO (first in first out), in which each position contains 21 bits: 16 for the TOA and TOT information, and 5 bits for the *TrigID*. The current design has a depth of 32 that could eventually be reduced in case simulations prove it possible. The writing of the data into the FIFO is done by the trigger hit selector block, while the readout is performed by the EOC logic by placing a requested trigger ID (*RqtTrigID*).

### 6.3.6 Luminosity processing unit

As already described before, the windowing process of the luminosity measurement is carried out on-channel, which is needed because of the large area of the chip. Transmitting the output of the discriminator to the luminosity block at the periphery would imply the use of a metal line of several millimetres. Such a long metal line would have large equivalent RC that would delay the signal by several nanoseconds. The length of each channel-to-luminosity block connection would vary from channel to channel and so would the delay. As a result, these delays might cause some hits inside one of the windows to be registered outside, corrupting the measurement of the luminosity. The compensation of the delay for each channel would be difficult. A simpler solution is to perform the windowing process on-channel. This avoids the need to transmit the output of the discriminator to the periphery. However, the windows must be distributed through the whole channel matrix. Again, long metal lines are needed but their delays can be compensated by distributing them as a clock tree.

A scheme of the first step in the luminosity measurement is presented in Figure 6.9. At the channel level, an AND gate evaluates if the output of the discriminator is inside the window. It generates a pulse that triggers a positive edge detector made of a flip-flop D with its D input connected to a logic '1'. When a positive edge is detected, the output of the flip-flop D goes high. This signal is asynchronous, so a synchronizer retimes the signal with a 40MHz clock. The output of the synchronizer is read out at each clock cycle and processed in the end-of-column logic.
<figure><img src="image_98.png" /><figcaption>Figure 6.9: The signal of the discriminator is compared to the luminosity window (for each window) and a signal is transmitted to the end-of-column logic.</figcaption></figure>

## 6.4 End of Column logic and digital blocks

This section describes the ASIC common digital part, including the readout process of the channels and the various blocks with specific functions.

### 6.4.1 Clock generation unit

The ASIC requires several clocks (see Figure 6.10):

* A 40 MHz clock (clk40MHzInt), necessary for the TOA TDC and for most of the digital blocks, including the I2C and the configuration registers

* A 80 MHz clock (clk80MHzInt), necessary to read out the timing data from the pixel matrix and to pack them into frames in the TDPU.

* Two 640 MHz clocks, one to serialize the data (clk640MHzInt), and one clock to generate the time windows for the luminosity measurement (clk640MHzLumInt).

A clock generator unit made of a PLL and a phase shifter (see Figure 6.11) provides these clocks while ensuring their phase alignment and their phase shifting. The 40 MHz clock input is not the one provided by the lpGBT but the one obtained from the fast commands and the lpGBT 320 MHz clock. This choice facilitates the phase alignment of all the necessary control signals used by the ASIC and also limits the number of e-links on the flex. As described in Section 6.2.2, the ASICs receive fast command signals from the lpGBT 320 Mbps e-links, along with the lpGBT 320 MHz clock. These fast commands, coded over 8 bits, contain several encoded control signals (such as the Level-1 trigger, the BCID, reset signal, 40 MHz phase...) as well as the command pulse that is necessary for the phase inter-calibration and the time walk correction (see Section 6.3.4). The 40 MHz clock input of the clock generator is obtained by dividing the lpGBT 320 MHz clock by 8. The clock divider also selects the 40 MHz phase that is encoded in the fast commands (see Figure 6.12). The phase aligned 40 MHz clock (clk40MHz) is then sent to the fast commands decoder so that all the decoded control signals are aligned on this very same phase. The PLL of the clock generator unit
uses this phase aligned 40 MHz clock as a reference clock and generates two phase aligned
and jitter cleaned clocks (jitter <10 ps) : PLL_40MHz and PLL_640MHz. These two clocks
are then sent to the phase shifter of the clock generator that provides all the necessary clocks
for the ASIC: clk40MHzInt, clk80MHzInt, clk640MHzInt and clk640MHzLumint. A
phase shifter is integrated to compensate for the cumulative latencies, in particular those
related to the flex length.

<figure><img src="image_99.png" /><figcaption>Figure 6.10: Schematic of the clock distribution.</figcaption></figure>

<figure><img src="image_100.png" /><figcaption>Figure 6.11: This schematic shows how a phase aligned clk40 MHz is extracted from the Fast command elink. The clock generator unit provides all the necessary clocks of the chip.</figcaption></figure>

The phase shifter is also used to control the position of the 2.5 ns measurement time window
of the TOA TDC compared to the bunch crossing (see Section 6.3.3). This is done by adjusting
the phase of the 40 MHz clock with 100 ps steps, keeping the jitter below 5 ps and a power
consumption around 10 mW. The design is adapted from the one designed in CMOS 65 nm
process for the lpGBT. As mentioned before, the ASIC needs two phase shifted 640 MHz
clocks (clk640MHzInt and clk640MHLumInt). The core of the phase shifter is therefore
composed of two delay-locked loops (DLL).

<figure><img src="image_101.png" /><figcaption>Figure 6.12: Simplified schematic of the clock generator made of a PLL and a phase shifter.</figcaption></figure>

Each DLL integrates 16 delay cells and is fed by the 640 MHz clock provided by the PLL.
The phase shift range is therefore 25 ns (16 * 1.562 ns), and the time shift is equal to 1/16 of
the 640 MHz clock period i.e 97.6 ps. As for the 40 MHz and the 80 MHz clocks, coarse phase
adjustment circuits are needed. Their output is then re-sampled by the clk640MHzInt clock
Consequently, clk40MHzInt, clk80MHzInt and clk640MHzInt clocks are all aligned in
phase and can be shifted compared to the clk40MHz clock with a step of 97.6 ps. All these
clocks are distributed using clock trees in order to minimize clock skews and jitters.

**6.4.2 Matrix readout process**

The matrix readout consists of two processes, reading data from timing and from luminosity, each carried out by a specific module. The TDPU is responsible of handling the readout of the time data, and the luminosity processing unit of the luminosity data. Both blocks are depicted in Figure 6.3. Each readout process is described next.

**Timing data readout**

As described previously, in order to read out the timing information it is necessary to create
a table that matches the BCID provided by the TDAQ system and the internal TrigID. The
TDPU has a 5-bits counter to tag the trigger events that are being received. The counter can be initialized with the fast command used to reset the chip. When the TDPU receives a trigger command, it stores the content of the counter together with the corresponding BCID into the trigger table and increases the counter by one unit. When the counter reaches the largest value, it wraps up to 0. The trigger table is a FIFO with 32 positions of 17-bits each one: 12 bits for the BCID and 5 bits for the TrigID. If the FIFO is full, an error message is generated and transmitted to TDAQ through an e-link. The TDPU unit also generates an internal trigger signal with a duration of one clock cycle. This is immediately transmitted to all matrix channels as well as the TrigID. Figure 6.13 shows a block diagram of the main signals involved in the TDPU and the EOC. Both, the trigger signal and the identifier are processed by the hit processor as described in Section 6.3.5.

<figure><img src="image_102.png" /><figcaption>Figure 6.13: Block diagram of the main signals involved in the communication of the EOC with the pixels and the TDPU.</figcaption></figure>

The hit data formatting unit in the TDPU continuously checks for an entry in the trigger table. When one is found in the TDPU, it fetches the entry and initiates the readout of the data stored in the matrix associated to that trigger event. The readout is carried out in two steps: first the retrieval of data associated to a given TrigID from the columns, and then the frame construction and data transmission. In the first step, the hit data formatting unit places the TrigID of the entry from the trigger table in the rqtTrigID bus and asserts the
checkMatrix signal to indicate to all the EOC to retrieve data from the pixels. Then the EOC asks to all the pixels to check if they have data associated to that TrigID by asserting the checkTrigID signal. The hit data processor checks if there is a matched hit with the same TrigID as the requested trigger. If there is, a hit flag is asserted. Once all the pixels have checked if they have data, then the EOC starts reading all the pixels that have such flag asserted, one per clock cycle. The row address, TOT and TOA of each read pixel are stored in a FIFO placed at the EOC. When the data of a pixel have been read and stored, the flag of that pixel is set to low. Once all the pixels have been read, the EOC indicates the completion to the hit data formatting block by asserting the doneMatrix signal. In the second step, the hit data formatting block starts reading the FIFO of the end of the columns since any data is available in the FIFO, not waiting for the readout to be completed. The column address is added to each FIFO entry and the data are placed at the dataOutEOC bus. The TDPU packs the data in frames and serializes them. Once all the buffers have been read and their data transmitted, the hit data formatting block waits for a new entry in the trigger table and the loop is executed again.

The design of the pixel matrix was done by trying to minimize the number of cycles needed to readout the data associated to a trigger event. For that purpose, the retrieval of data associated to a trigger event is carried out at column level so that each EOC works in parallel with the other ones. The search of data inside the matched hit buffer takes from one to few clock cycles. As mentioned before, it takes one clock cycle to move data from one pixel to the FIFO at the end of the column. Therefore, the readout of the column will take up to 15 clock cycles if all the pixels in the column have data associated with the requested trigger event. In the second step of the pixel matrix readout, data stored in the FIFOs must be passed to the TDPU where there are packed in frames and serialized. This second step doesn't wait for the completion of the data retrieval. It starts as soon as there is data available in the FIFOs, so it happens that data are being readout from one FIFO and passed to the TDPU while there are data being stored from the column to that FIFO. Therefore, data packaging and serialization start few clock cycles after the start of the data retrieval process. The FIFOs of the columns are not read in parallel but in series, that is, once the content of a FIFO has been fully read, then it read the content of the next EOC.

## Luminosity data readout

The instantaneous luminosity, that is, the number of detected hits in the pixel matrix per bunch crossing, is measured every 25 ns. The process is carried out in three different regions of the ASIC as already described in Section 6.2.2

The windowing is performed per pixel. The two windows are generated at the EOC and distributed to the whole column as a clock tree in order to minimize the skew from pixel to pixel. A trade off needs to be found between power consumption and skew. The first trials of physical synthesis show a skew of 100 ps. The windows are generated with a programmable
FSM running at 640 MHz. This FSM divides the bunch crossing into 16 equal intervals of 1.5625 ns with a 4-bits internal counter that continuously counts from 0 to 15. A control unit asserts and deasserts the two window signals called W1 and W2 as a function of the value of the counter and of the 4-bits parameters minW1, minW2, maxW1, and maxW2 as shown in Figure 6.14. The width of W1 is fixed to 3.125 ns so the default values of minW1 and maxW1 are 1 and 14. However, both values can be modified in case it would be necessary to improve the luminosity measurements. The 1.5265 ns time resolution of the window generator is not enough to center the position of the windows with respect to the beginning of the bunch crossing. In order to provide the required resolution, the phase of the 640 MHz clock used by the EOC can be adjusted through the phase shifter. This 640 MHz clock (clk640MHzLumInt) is independent from the 640 MHz clock (clk640MHzInt) used in the serializers. More details are given in Section 6.4.1 The windowing process at pixel level is described in Section 6.3.6. Every pixel produces two measurements per bunch crossing. The EOC sums the luminosity measurements of the whole column per bunch crossing. Those measurements are passed to the luminosity processing unit which sums the measurements of the columns. The number of hits in W1 (S1) is subtracted from number of hits in W2 (S2). The result S2-S1 and S1 are truncated to 5 and 7 bits respectively. Both values are encoded with 6b8b code, producing a 16-bit frame per bunch crossing. Frames are serialized at 640 MHz. The whole bandwidth is occupied with the luminosity data. In order to avoid desynchronization, a synchronization frame needs to be sent periodically. This will be transmitted during the processing of a bunch crossing reset (BCR) fast command.

The readout of the EOC cells is performed at 80 MHz instead of the nominal operating clock of the rest of the ASIC which is 40 MHz in order to be able to encode data to 8b10b and keep the desired data transmission rate. Data encoding 8b10b can be disabled through the corresponding configuration register. The readout of the hit data can be adjusted through some configuration registers. These allow to enable/disable the readout as well as to select the transmission speed of the e-link between 320Mb/s, 640Mb/s and 1.28Gb/s.

### 6.4.3 Slow control

The slow control is used to configure the ASIC as well as to retrieve information of its internal status. For such a purpose, up to 1024 configuration registers of 8-bits each have been implemented in ALTIROC. The memory map is not yet completely determined, but the first 900 positions are dedicated to the configuration of the channel registers (4 per channel). The other 124 registers will be located at the periphery and will be used to configure the hit data transmission rate, enable/disable the luminosity block, to program the length of the windows used for the luminosity, etc ... For the final ASIC, the configuration registers are read/written by using an I²C link while shift registers are used for the prototype. The I²C link in the ASIC is slave to the master in the lpGBT in the peripheral electronics, described in Section 9.1.1.
<figure><img src="image_103.png" /><figcaption>Figure 6.14: Generation of the luminosity windows W1 and W2.</figcaption></figure>

## 6.5 Radiation tolerance

Two radiation effects must be taken into account: the TID that may degrade the timing performance, and the Single Event Effects which may corrupt the configuration registers and the time data. As the ASIC is designed in pure CMOS, it is insensitive to neutron irradiation. The worst expected TID and fluence are respectively 2 MGy and $2.5 \times 10^{15} n_{\text{eq}} \text{ cm}^{-2}$ taking into account the replacement of the inner modules every $1000 \text{ fb}^{-1}$. The ASIC has been designed using TSMC 130 nm technology that has been tested up to 4 MGy, i.e. two times above the requirement. Nevertheless, known strategies have been used in the ASIC design to mitigate the radiation effects. TID degrades the performance of MOSFET by increasing their threshold and generating leakage currents. To avoid these effects, bias currents of analog blocks are set to quite large values ($> 20 \ \mu\text{A}$) compared to the expected leakage currents and low voltage threshold transistors are avoided in current sources. In addition, minimum size transistors are avoided, for PMOS transistors in particular. At the layout level, substrate contacts are used to avoid latch-up. The DLLs of the TDC part are designed to take care of radiation, temperature and voltage variations inside the chip automatically. Besides, as the TDC bins are given by the difference of two delays, it ensures compensation for variations under irradiations.

As for the digital part and the SEU tolerance, Triple Modular Redundancy (TMR) will be implemented on critical parts of the 225 channel version (ALTIROC). Simulations of SEU using CERN tools will be performed to fully evaluate the effect of SEUs on the chip functioning.
## 6.6 Power distribution and grounding

To preserve the signal integrity and the jitter performance during periods of significant digital activity, the power distribution must be done carefully at the ASIC level. Each analog block (preamplifier, discriminator, TDC) is in a deep N-well powered and grounded with its own power and ground lines. All powers and grounds are therefore separated. Great care must be taken to reduce the resistance of the power lines, especially for the preamplifier power supply. The preamplifier Power Supply Rejection (PSR) has been simulated and found to be above 17 dB for frequencies up to 1 MHz and above 30 dB for high frequencies larger than 100 MHz, meaning that the noise from power supplies is attenuated by at least 17 dB. As for the digital blocks, they are in deep N-well or directly on the substrate. The connection between all the digital grounds and the substrate will be done at the flex level. In order to find the optimal solution, tests will be performed at the system level in order to decide whether the analog ground and digital ground (gnda and gndd respectively) should be connected at the module level or at the PEB level. The same is done for the power supplies: all the analog power lines ($V_{dda_block}$) are connected together at the flex level to a common $V_{dda}$ and all the digital power lines of the digital blocks ($V_{ddd_block}$) are connected to a common $V_{ddd}$.

The power consumption of the ASIC has been estimated through both preliminary measurements and simulations for a 10% occupancy. Two operation modes can be distinguished: physics runs and calibration runs. In the latter only a 10% occupancy will be considered, so that the power consumption during calibration will not be higher than the maximum during data taking. At the single channel level, the preamplifier and discriminator give a power consumption of 1.0 mW, considering a drain current for the preamplifier of 0.6 mA. For each TDC, 0.55 mW has been estimated, while up to 2 mW have been allowed for the digital part (hit processing unit, clock and luminosity unit). This yields a total of 4.2 mW per channel. In addition, an estimated allowance of 250 mW for the common digital part seems reasonable, yielding a total power consumption per ASIC of 1.2 W.
## 6.7 Prototype performance

The performance on the first prototype version ALTIROC0 containing only the analog part of the single-channel readout (the preamplifier and the discriminator) can be found in [61]. In this section, the results concerning the second prototype ALTIROC1 are presented. This second version consists of a 5 × 5 pad matrix instead of 2 × 2, in which the digital components have been added to the single-channel readout. Two iterations of ALTIROC1 have been produced called v1 and v2. The second one, ALTIROC1v2, corrects issues found in the TDC, and only results from this iteration are presented here except the irradiation tests done with the first iteration. Among the 25 channels, only 15 channels corresponding to three columns have the readout as described in Section 6.2.1 with voltage preamplifiers. The two other columns are equipped with trans-impedance preamplifiers and their performance is not described in this document.

Section 6.7.1 describes the test bench measurements which were performed with and without a sensor bump bonded to it. More information on the assembly can be found in Section 7.2.2. In the case where no sensor is bump bonded, on channel 4 of each column, a capacitor can be connected through a programmable switch to the preamplifier input, mimicking the LGAD sensor capacitance and thus allowing to study the performance as a function of the detector capacitance $C_d$. The capacitance is tunable from 0 to 7 pF with a step of 1 pF. As described in Section 6.3.4, the test bench measurements are performed thanks to a $C_{test}$ capacitor of 200 fF that is selectable by slow control together with a calibration pulser which generates a Dirac input charge with a relative precision between channels of ~ 1%. All the measurements have been performed with only one channel activated at the same time. In order to understand the performance of the ASIC, an analog probe is integrated inside the prototype ASIC that allows to output the preamplifier signal to an oscilloscope. When this probe is enabled, the preamplifier output is not only sent to the discriminator but also to an amplifier with a gain of approximately 1.5. In a similar way, a digital probe allows to see the output of the discriminator, before going into the TDC.

Two test beam campaigns have been carried out during the year 2019 at DESY, in which data were collected with ALTIROC1v2, bump bonded to a non-irradiated 5×5 LGAD sensor. The main results are presented in Section 6.7.2. Irradiation tests were also performed at CERN using X-rays up to 3.4 MGy. The results are presented in Section 6.7.3.

### 6.7.1 Test bench measurements

The first step towards the evaluation of the full single-channel readout is the measurement of the TDC counts since the knowledge of the value of the LSB (Least Significant Bit) is needed to obtain the real values of the TOA and TOT. This is achieved by sending a square external trigger pulse, whose delay is adjustable in 10 ps steps, directly to the TDC inputs. This
bypasses the preamplifier and discriminator, allowing direct measurements of the TOA as a function of the delay, as shown in Figure 6.15(a). The measured TOA TDC quantization step for the board that has been tested is found to be around 22 ps, slightly above the nominal value of 20 ps. As a consequence, the maximum TOA that can be converted is slightly larger than the nominal window of 2.5 ns. The uniformity of the LSB for the TOA is shown on Figure 6.15(b) and is better than 5%. The external trigger has a variable width, adjustable in 10 ps steps which can be used to measure the LSB for the TOT. The averaged measured LSB is around 170 ps close to the nominal value of 160 ps and the dispersions are better than 5% as can be seen on Figure 6.15(b). All these results are already close to the nominal but they can be further improved using internal TDC slow control parameters to adjust the LSB for each channel individually.

<figure><img src="image_104.png" /><figcaption>Figure 6.15: Average Time Of Arrival measurement with the TDC as a function of the programmable delay (a) and channel LSB divided by the averaged LSB as function of the channel number for one ASIC (b). All measurements are performed with an external trigger. One point is missing for the TOT due to a faulty channel.</figcaption></figure>

The preamplifier jitter $\sigma_{jitter}$ depends on the preamplifier rise time, which depends on the drain current that flows into it. All the results below have been obtained with $I_d$ =0.6 mA. At this point, the transistor enters in the strong inversion region, the gain increases only with the square root of $I_d$ and, so the $S/N$ doesn't increase significantly. Figure 6.16(a) shows the efficiency as a function of the input charge for an ASIC alone with $C_d$ = 4 pF in order to mimick the detector capacitance and with an ASIC bump bonded to a sensor. In the later (former) case, full efficiency is achieved for charge greater than 3 fC (2 fC), which is below the minimal expected charge for irradiated sensors at $2.5 \times 10^{15} n_{eq} cm^{-2}$ which is 4 fC. These measurements are performed for a Dirac signal which is 10% lower in amplitude than an LGAD signal after the preamplifier. Even taking this effect into account, the efficiency is still 100% for a charge of 4 fC. The difference between the two curves is attributed to noise which is about 30% larger for the sensor case.
<figure><img src="image_105.png" /></figure>

Figure 6.16: Efficiency (a) and jitter (b) measured as a function of the injected charge for an ASIC alone with $C_d = 4$ pF (purple) and with an ASIC bump bonded to a sensor (blue) measured with the calibration setup. For (b), the open circle shows the jitter for an LGAD input signal estimated from the calibration data and the simulation.

Figure 6.16(b) shows the jitter variation as a function of the input charge for an ASIC alone with $C_d = 4$ pF and with an ASIC bump bonded to a sensor. For large charge a constant jitter of about 15 ps is observed, which is attributed to the command pulser and clock jitter. Even without subtracting this constant term, the jitter is smaller than 30 ps for $Q_{inj} > 6$ fC. The larger jitter with sensor is attributed to larger noise measured in the sensor case and also to a larger detector capacitance. Preliminary measurements estimate this capacitance being between 5 and 6 pF including the effect of interpad capacitance and bump bonds. The performance obtained with the calibration signal can't be transposed to an LGAD signal because the calibration signal is much faster. Based on the simulation, the jitter obtained with the calibration needs to be multiplied by 1.65 to reproduce the results obtained with an LGAD signal. Therefore, the jitter becomes smaller than 30 ps only for $Q_{inj} > 8$ fC as shown on Figure 6.16(b) and reaches ~55 ps at 4 fC which is consistent with the requirements. Figure 6.17 shows the TOT as a function of the injected charge. As expected, the TOT increases monotonically with the injected allowing to use it for time walk correction.

## 6.7.2 Test beam measurements

An ALTIROC1v2 ASIC bump bonded to a LGAD sensor array (HPK 3.1) was exposed in electron beam tests at DESY in the fall of 2019. The LGADs were operated with a bias voltage of 230 V, resulting in a MIP charge deposit of about 20 fC. For an accurate timing reference, a fast Cherenkov-light emitting quartz bar of 6×6 mm² area transverse to the beam and 20 mm length along the beam, coupled to a Silicon Photomultiplier (SiPM) is used. The time resolution of this device was measured to be 37.6±0.7 ps.
<figure><img src="image_106.png" /><figcaption>Figure 6.17: Time-over-threshold measured as a function of the injected charge.</figcaption></figure>

Figure 6.18(a) shows the TOA variation as a function of the TOT. The range of the TOT is truncated since it was not possible to measure large values of TOT because of a coupling between the busy signal of the TOA TDC and the falling edge of the preamplifier output. This coupling only occurs when this signal is output on the PCB. This TOA busy signal must be output during test beam in order to synchronize the data from ALTIROC and the oscilloscope used to record the Quartz+SiPM system waveforms. This signal won't be needed for the HGTD and is not used for test bench measurements (it is only used for debug purposes). In the next iteration, ALTIROC1v3, the busy signal will be output as a differential signal to solve this problem. Therefore, with ALTIROC1v2, only a range of the TOT can be used in test beam and Figure 6.18(a) also displays a fit in this restricted range used for the time walk correction.

Figure 6.18(b) shows the time difference between LGAD+ALTIROC and the reference time from the Quartz+SiPM system before and after time walk correction extracted from the fit in Figure 6.18(a). The distributions are Gaussian without any tails. The measured time resolution decreases from 58.3±1.6 ps to 46.3±1.4 ps after time walk correction. Subtracting the Landau contribution (about 25 ps), the remaining time resolution is about 39 ps containing contributions from the electronics jitter, TDC and clocks. This preliminary result is encouraging even though it is larger than the results obtained in test bench conditions (see Figure 6.16(b)). One reason for the non-optimal performance of ALTIROC1v2 in test beam is due to larger noise coming from the FPGA board connected to the ASIC read-out board. An interface board is used to reduce this noise and an improved version was available in January 2020 (3 months after the testbeam) to further reduce the noise. Thanks to the new interface board, the jitter was reduced by 35% compared to the old version in test bench conditions. If the same improvement factor is applied to the test beam results, we would get about 26 ps instead of 39 ps. Testbeam campaigns are planned in 2020 to confirm this prediction. Moreover, it was noticed that the noise was larger in test beam compared to test bench conditions since it was not possible to use the same thresholds. For the next test beams campaigns, detailed investigations of the noise are planned to mitigate this effect.
<figure><img src="image_107.png" /><figcaption>Figure 6.18: (a): Distribution of the TOA as a function of the TOT. The dots correspond to the mean value of the TOA distribution for a given TOT bin extracted from a Gaussian. The red line is a fit of the average TOA as a function of the TOT. (b): Distributions of the time difference between LGAD+ALTIROC and the Quartz+SiPM system before (red) and after (black) time walk correction together with Gaussian fits. The numbers are the fitted Gaussian widths where the time resolution of the Quartz+SiPM system has been subtracted quadratically.</figcaption></figure>

### 6.7.3 Irradiation tests

ALTIROC1v1 has been irradiated at the ATLAS-pixel CERN facility using an X-ray machine in July 2019 before the second version was available with improved TDCs. The very front end part of the two version (preamplifier and discriminator) are identical so this test has been focused only on their performance. As mentioned before, the ASIC has an analog probe that copies the output of the preamplifier, and a digital probe to see the output of the discriminator. During the irradiation, both were recorded with an oscilloscope in order to evaluate possible degradation of the signal caused by irradiation, that could be evidenced in the amplitude and the jitter level.

To allow debugging and performance studies, some voltage levels in the ASIC have been made accessible by connecting them to externally accessible points and a connector. The direct current level signals for the bandgap output, the $V_{ddd}$ and $V_{dda}$, the general and individual channel $V_{th}$ were recorded throughout the test.

The ASIC has been first irradiated in two periods, first with low dose rate (3.5 kGy/h) up to 0.23 MGy and then at higher rate (20.5 kGy/h) up to 3.4 MGy. No low-dose effects were observed after the first period. During the second, some of the DC levels corresponding to the bandgap output, the 10-bit DAC and 7 bit-DAC (used to set a common and the individual discriminator thresholds respectively) show a drift smaller than 20 mV (over a typical amplitude of 800 mV).
The amplitude of the preamplifier signal has been monitored using the probe output and is diplayed in Figure 6.19(a) for different input charges. The decrease in amplitude is negligible up to 2 MGy. The amplitude measured after the full irradiation was only a few percent lower than at the beginning.

The measurement of the jitter in the rising edge of the discriminator signal is presented in Figure 6.19(b). A large level of noise was introduced by the data taking conditions, which is why the plot presents the relative increase in noise as the irradiation progresses instead of its absolute value (which was quite higher than what can be achieved in more controled test bench conditions). The plot shows a relative increase in the jitter level between 10 and 15% after 2 MGy. More tests with ALTIROC1v2 and more ASICs will be conducted over 2020, monitoring also the TDC outputs.

<figure><img src="image_108.png" /><figcaption>Figure 6.19: Preamplifer amplitude (left) and relative jitter measured with the discriminator probe for a charge of 10.3 fC (right) as a function of the irradiation during high dose period. The dashed vertical line represents the maximal TID for HGTD. The step observed at 0.5 MGy is due to large temperature variations at the beginning of the measurement, which were subsequently controled.</figcaption></figure>

# 6.8 Monitoring

## 6.8.1 Temperature monitoring

An additional requirement of the ASIC is to allow monitoring two closely related aspects of the LGAD: its operating temperature and its leakage current. While the electronics themselves are not very sensitive to temperature changes, it is of utmost importance to monitor the sensors in order to detect loss of cooling and thermal run-away, as explained in
Section 5.6. This information could also be used to estimate the particle fluence, since the current increases linearly with it.

A good estimate of the temperature dependence of the leakage current of a no-gain sensor is a factor 2 increase for every 7 °C. The temperature dependence of the gain is much lower, with an increase in gain of a factor 2 for a temperature decrease of 30–40 °C. Knowledge of the sensor temperature with an accuracy of 0.5 °C would make it possible to determine the leakage current to approximately 15% (while giving no relevant information on the gain). The modules will be operated at room temperature (20-30 °C) during the R&D phase, and during detector operation at about –30 °C as required by the sensor. Considering possible temperature shifts within the chip plus some margins, two monitoring ranges have been defined, [30- 40 °C] [-40 –10 °C], given a total temperature monitoring range of 80 °C. The target resolution to determine temperature variations has been set to 0.4 °C (9-bit resolution) independantly of the absolute value of the temperature.

The temperature sensor inside ALTIROC is based on a resistor which is sensitive to variations of temperature. A constant current, delivered by the current source present at the ADC input of the lpGBT circuit, flows through this device and produces a voltage drop proportional to the temperature Four different types of resistor proposed by the TSMC technology have been evaluated for their ability to perform temperature measurements in an irradiated environment. Since they all present similar behaviours, only the performance of the N-diffusion resistor version is reported in Table 6.3. In particular, a resolution after conversion was measured to be 0.8 °C per ADC count using a current of 100 µA. It should be noted that the resolution can be doubled using a current value of 200 µA instead of 100 µA, achieving then a resolution of 0.4 °C per ADC count.

<table><caption>Table 6.3: Evaluation of a N-diffusion resistor as temperature sensor under irradiation (TID).</caption><tr><td>Technology of the resistor</td><td>N+ diffusion resistor with salicide (rnlplus)</td></tr><tr><td>Value of the resistor</td><td>5 kΩ</td></tr><tr><td>Value of current flowing during test</td><td>100 μA</td></tr><tr><td>Sensitivity</td><td>+1.3 mV/°C</td></tr><tr><td>Variation of sensitivity with radiation</td><td>+15% at TID of 3.5 MGy</td></tr><tr><td>Shift of temperature with radiation</td><td>-0.3 °C at TID of 2 MGy</td></tr><tr><td></td><td>-0.6 °C at TID of 3.5 MGy</td></tr><tr><td>Resolution after conversion with ADC of lpGBT</td><td>0.8 °C per ADC count</td></tr></table>

## 6.8.2 Supply voltages monitoring

The analog and digital supply voltages have also to be monitored in order to measure and compensate the voltage drops in the power lines caused by the parasitic resistances in the power wires of the flex cables ($R_{FLEX}$ in Figure 6.20). The $V_{dda}$ and $V_{ddd}$ voltages are sensed
through dedicated wires on the flex and digitized by the ADC of the lpGBT circuit on the
peripheral board.

<figure><img src="image_109.png" /><figcaption>Figure 6.20: Complete schematic view of the voltage monitoring of a module using the ADC of the lpGBT circuit.</figcaption></figure>

The probing of the power voltages at the module level is also useful to detect latch-up events
on an ASIC. With the resolution of 1 mV of the lpGBT ADC and a parasitic resistance of
100 mΩ on the flex cable, minimal variation of 20 mA (considering an attenuation of 1/2 on
the probing to respect the input dynamic range of the lpGBT ADC of 1V) can be detected,
much smaller than the expected current rise in a latch-up event.

**6.8.3 Complete monitoring system**

A complete schematic view of the proposed monitoring of ALTIROC using the ADC of the lpGBT circuit is given in Figure 6.20. Three signals (VddaProb, Vdddprob and GndaProb) for the monitoring of the power supply voltages inside the two chips and two signals (Vtemp1, Vtemp2) for the measurement of the temperature inside the two ASICs are connected to the
ADC of the lpGBT circuit. The signal to be converted by the ADC is selected via multiplexers controlled through the I²C interface of the lpGBT.

A view of the complete interfacing of a peripheral board with the modules is represented in Figure 6.21. The analogue signals for monitoring coming from the modules are digitized by the converter implemented inside each lpGBT circuit of the peripheral board. The number of channels of this ADC being limited to eight, a multiplexing is required at the input of each channel. Multiplexers (MUX 64:1) are thus implemented to interface the signals coming from the modules to the ADC on the peripheral board. With such multiplexer circuit, up to 8 × 64 signals can be interfaced to each lpGBT-ADC. With one multiplexer reserved for the signals coming from the DC/DC regulators, 7 mux are available to interface the monitoring signals coming from up to 84 modules, which is larger than the maximum number of modules expected per peripheral board. A full custom 64-to-1 multiplexing circuit has been developed in CMOS 130 nm technology and received in December 2019, and currently being characterised.

<figure><img src="image_110.png" /><figcaption>Figure 6.21: Interfacing of modules with a peripheral board for the monitoring.</figcaption></figure>

## 6.9 Roadmap towards production

Two iterations of the ASIC have been produced : ALTIROC0 in 2018 with the preamplifier and discriminator with 4 channels, and ALTIROC1 in 2019 including the TDCs and the SRAM with 25 channels. While the intrinsic performance of ALTIROC1 is quite good, an issue with the TOT measurements has been observed in test beam, which is attributed to a coupling between the busy signal of the TOA TDC and the falling edge of the preamplifier
output. In order to characterize the ALTIROC1 performance in test beam conditions, a third iteration of ALTIROC1 is needed before submitting the ALTIROC2 ASIC containing the 225 channels. Consequently the following R&D steps are envisaged for 2020:

* submit an ALTIROC1v3 to fully demonstrate that the TOT issue is solved for test beam by outputing the TOA busy signal as a differential signal (foreseen for Q2 2020). This version will also include a modification of the TDC and different grounding schemes for different columns.

* submit in parallel an ASIC with one complete pixel channel. This single pixel integrates the same front end as the one integrated in ALTIROC1 but also all the digital blocks (I2C, matched hit buffer, EOC, data formatting...) that will be in ALTIROC2. This ASIC will therefore validate the single pixel architecture and in particular the digital part. This ASIC can be submitted through an IN2P3 building block MPW run that is already financed in Q2 2020.

Assuming both ASICs work as expected, a Specification Review can take place in September or October 2020 before the submission of ALTIROC2. Taking into account the complexity of the chip, a second iteration of this chip is expected once the first prototype of ALTIROC2 has been intensively measured. A Preliminary Design Review would take place in Q2 2021 before the submission of ALTIROC3. The Final Design Review would take place in Q1 2022 before launching the pre-production. As ALTIROC2 should already be an engineering run, wafers of this ASIC will also be used to qualify the hybridisation process and module assembly needed for the full demonstrator program which starts in Q3 2021. A summary of the key dates can be seen in Figure 15.4.

Regarding the MUX 64-1, the prototype is currently under measurements. Taking into account the small size of this ASIC, the aim would be to include it in the production of the LAr preamplifer to save cost (end of 2021). A joint Specification Review and Preliminary Design Review will take place early 2021 followed by a Final Design Review in 2021.
<figure><img src="image_111.png" /></figure>
# 7 Module Assembly and Loading

## 7.1 Introduction

The basic component of the HGTD is the module. A detector module consists of a sensor bump-bonded to two readout chips which are in turn connected to a flexible printed circuit (FPC, flex cable) for communication, power distribution and data output. The flex cable also provides high voltage for the silicon sensor. The HGTD is made up of 8032 modules mounted on intermediate plates. This chapter describes the module and its assembly process, together with the procedure of mounting them onto the intermediate plates. Quality assurance and control plans are presented. Results of the fabrication of various prototypes are also discussed.

## 7.2 The bare module

The bare module consists of an LGAD sensor interconnected through solder bumps to two ALTIROC front-end chips. The LGAD sensors and the ALTIROC chip have been described in Chapter 5 and Chapter 6. In this section the hybridization process, called bump-bonding, is discussed.

Modules based on the 5 × 5 channel ALTIROC1 chip have already been fabricated and tested. A baseline hybridization process has been defined and the specifications agreed upon with two vendors. One of these vendors, as well as one HGTD institute, produced ALTIROC1 devices for which results were presented in Section 6.7. Full size prototypes will be produced as soon as the ALTIROC2 ASIC is available.

### 7.2.1 Bare module assembly

The LGAD sensor has a total size of 20.1 mm × 39.6 mm, with an array matrix of 15 × 30 1.3 mm × 1.3 mm pads and a dead region 0.3 mm wide around the active area. The readout ASIC has a total size of 21.7 mm × 19.9 mm and a matrix of 15 × 15 channels. The LGAD sensor has half the bump pads shifted from the central position by 250 µm, while the other half of the pads are shifted by the same distance in the opposite direction. This allows a
## 7 Module Assembly and Loading

distance of 100 µm between ASICs, with no gap in the sensor coverage or disruption from different pixel sizes (see Figure 7.1).

The LGAD sensors will be produced on 150 mm wafers, whose thicknesses will depend on the wafer and sensor providers. The wafers will be thinned to the total sensor target thickness. Currently, the baseline for the active thickness is 50 µm and 300 µm for the total thickness. The sensors will be probed at wafer level at the fabrication sites and this information will be made available to ATLAS. The under-bump metal will be deposited on the sensors at wafer level, a necessary step before bump-bonding with solder bumps. After under-bump metalization (UBM), the wafers will be diced and the selected sensors will be destined for hybridization.

The ALTIROC2 ASIC will be produced on 200 mm wafers. The wafers will be thinned down to 300 µm (current baseline). The front-end chips will then be probed to identify the good dies. This will be followed by UBM and solder bump deposition. The relatively large pad size of the HGTD sensors enables a less demanding bump-bonding technology process compared to the ITk Pixel detector. The low-cost electroless deposition of Ni/Au can be used to treat the large pads (90 µm diameter) of both sensor and ASIC wafers. Solder bumps (SnAg) with a baseline diameter of 80 µm will then be deposited on the ALTIROC pads. A number of processes are available for the deposition of the bump balls, from solder laser jetting to electroplating. The most reliable, cost-effective technology will be selected.

After UBM and bumping, the sensor and ASIC wafers have to be diced into single tiles. The next step of the hybridization process is flip-chipping. During flip-chipping, the sensor and ASIC tiles are aligned, heated and compressed so that each solder bump melts and connects the sensor and readout channels of the two substrates. It is foreseen that the bare assemblies will then be processed in a fluxless formic acid reflow oven in order to improve the connectivity of the solder bumps. The final step consists in the inspection of the bare assemblies with a high resolution (sub-micron) x-ray machine to discard devices with disconnected pad bumps. Note that electrical tests of the HGTD modules will be carried out after the bare assemblies are mounted (including noise and charge collection measurements that can reveal disconnected bumps not apparent with x-rays).

### 7.2.2 First bare module prototypes: process and results

The first ALTIROC1 devices have already been assembled. A total of 20 bare modules were produced for different types of tests (mechanical and electronic) at Barcelona. As described in Chapter 6, the ALTIROC1 ASIC is a 5 × 5 channel prototype of the HGTD chip. The pad size is 1.3 mm × 1.3 mm. The corresponding 5 × 5 pad sensors used in these first prototypes were LGADs fabricated at CNM, in the context of an AIDA production (Run 11748), and at Hamamatsu (Type 3-1, EXX28995). Both vendors deposited the UBM on the sensors (at wafer level). In the case of CNM, a Ni/Au electroless process was used for UBM.
<figure><img src="image_112.png" /><figcaption>Figure 7.1: Sketch of the bare module (sensor and ASIC). Distances are in millimeters. The bump pads on the sensor are shifted by 250 µm on each side of the sensor (see magnified view in the left), to allow a 100 µm separation between the ASICs. A more detailed bare module drawing is shown in Figure D.1 and Figure D.2.</figcaption></figure>

The Ni/Au under bump metalization was also deposited on single ALTIROC1 tiles by CNM through a chemical electroless process. SnAg solder bumps of 80 µm diameter were then placed on the chips using a laser jetting machine at IFAE. The bumps were prepared for flip-chip with a formic acid reflow cycle. The bump strength was verified to be larger than 60 gf per bump through shear tests.

The hybridization was performed by IFAE following the previous experience with the ALTIROC0 devices [61]. The same bonding cycle previously developed for the ALTIROC0 devices was used for the hybridization of the first ALTIROC1 bare modules. The devices were reflowed with no applied pressure and inspected with x-rays. Good alignment was observed as well as good connectivity in all the bumps (except those removed in one of the samples as part of the bump shear tests). CNM and HPK bare assemblies, along with the x-ray image of the bump connecting one of the readout channels, are shown in Figure 7.2. The topology of the bumps was found to be mostly cylindrical, with a diameter of about 90 µm and a height of approximately 50 µm. The hybridization specifications detailed below (see Section 7.2.3) follow the same process developed by IFAE, which is standard in the commercial sector and for which two companies have already been identified. One of these companies (in China), also produced modules with ALTIROC1.

The modules will experience thermal cycles during their lifetime, as the HGTD inner volume will be cooled with an input coolant temperature of -35 °C. In order to verify the robustness of the bare assemblies, they were subjected to a long burn-in test (some glued to a PCB using Araldite 2011, see Section 7.4.3). During a total of two weeks the modules were thermally cycled between -40 °C and 130 °C. The solder connections were then verified with x-ray imaging and shear tests were carried out on the modules. The devices were able to sustain the maximum applied shear force of 1000 gf, between the ASIC and sensor and also between PCB and ASIC. One device was verified to sustain a perpendicular (with respect to the plane of the sensor) pull test of 100 gf before and after the two week thermal cycling. Figure 7.3 shows the shear and pulling tests being carried out on an ALTIROC1 hybrid.
## 7 Module Assembly and Loading

<figure><img src="image_113.png" /></figure>

Figure 7.2: The first ALTIROC1 bare modules, with CNM and HPK sensors, and an x-ray image with a detail of a corner of one device are shown. In the x-ray image, the guard-ring solder bumps are in the periphery, while the bumps of two readout channels are visible in the center left of the image. The wire-bond pads of the ASIC are also apparent towards the lower part of the figure.

<figure><img src="image_114.png" /></figure>

Figure 7.3: Shear and pull tests being carried out on an ALTIROC1 device. After thermal cycling during two weeks the device was able to sustain a maximum shear (pull) force of 1000 gf (100 gf).

The hybridization was also performed by the National Center for Advanced Packaging (NCAP China). NCAP has more than 3200 m² of cleanroom space and can provide bump-bonding services for 6 inch, 8 inch and 12-inch wafers. Its production capacity for module hybridization can fully satisfy the requirement of the HGTD project, this is also true for the other vendor identified in Germany. Fifteen bare module prototypes with ALTIROC1 have been hybridized in NCAP. Two of them are shown in Figure 7.4. The 5 × 5 pad sensors used in these prototypes were LGADs fabricated at Hamamatsu (Type 3-1 and Type 3-2), and at NDL (Type 6 and Type 12). The solder connections were then verified with x-ray imaging. The modules sustained a maximum applied shear force of 1000 gf during shear tests.

The performance of the bare module prototypes hybridized in NCAP have been evaluated
in the testbench measurements. A typical setup of testbench measurements is shown in the left photo of Figure 7.5. Bare module prototypes are glued on a printed circuit board (test board). The signal pads, power pads and debug pads of ALTIROC1 chip on the bare module are wire-bonded to the test board. The back side of the LGAD sensor in bare module prototype is wire-bonded to the test board for the high voltage connection. The electrical connections of each channel in the bare modules were checked by measuring the analog output level in each channel of the ALTIROC1 chip during charge injection tests. The results of the testbench measurements are described in Section 6.7.1. The performance of the bare module prototypes hybridized in NCAP were evaluated in electron beam tests at DESY in autumn 2019 (see Figure 7.5). The results are described in Section 6.7.2.

<figure><img src="image_115.png" /><figcaption>Figure 7.4: The bare modules hybridized in NCAP China. Left photo: The 5 × 5 pad sensors used in these prototypes were LGADs fabricated at Hamamatsu (Type 3-2). Right photo: The 5 × 5 pad sensors used in these prototypes were LGADs fabricated at NDL (Type 6).</figcaption></figure>

<figure><img src="image_116.png" /><figcaption>Figure 7.5: Left photo: A typical setup of testbench measurements for bare module prototypes. Right photo: The electron beam test setup for bare module prototypes at DESY in autumn 2019.</figcaption></figure>

An alternative process explored during the initial R&D phase (but not intended for pro-
duction) has also been developed to assemble ALTIROC0 devices. For Au bumps, the
## 7 Module Assembly and Loading

bumps can be deposited directly on the aluminum of the front-end pads without under bump metalization. An alignment and thermo-compression cycle is used to interconnect the channels of the sensor and ASIC. Studies determined that the bump topology resembled at conical frustum with a base of about 140 µm and a height of 15 µm.

Full-size bare module prototyping will be carried out after both final sized sensor and ASIC (ALTIROC2) become available in Q1 2021. In order to verify the hybridization scheme, full-size mechanical dummy sensors and dummy ASICs are fabricated by Suzhou Institute of Nano-Tech and Nano-Bionics (SINANO) of the Chinese Academy of Sciences. As shown in Fig. 7.6, two dummy ASICs are hybridized with one dummy sensor. 70 dummy bare modules are hybridized by SINANO and the yield is larger than 97%.

<figure><img src="image_117.png" /><figcaption>Figure 7.6: Left photo: Photo of dummy module. Right photo: An x-ray image of one dummy module. The bumps and the gap between two dummy ASICs are visible in the image.</figcaption></figure>

### 7.2.3 Hybridization specifications

The baseline bump-bonding technology for HGTD is solder bumps. As described above, both solder bump and gold bump prototypes have been produced at different HGTD Institutes and a company in China. However, the gold bumping process is not scalable for large productions. Thus, solder bumps are the baseline hybridization solution.

The sensor fabrication sites will deliver silicon wafers, which may or may not include under bump metalization, depending on the vendor fabrication capabilities and the overall HGTD hybridization strategy. In any case, it is expected that a fraction of the sensor wafers may have to be prepared for bump-bonding by a different vendor than the one producing the sensors. As explained above, given the large pitch and pad size of the sensors, the selected process for UBM is electroless deposition of Ni/Au. Table 7.1 lists the relevant parameters related to the sensor wafer UBM.

The HGTD ASICs will be produced in TSMC CMOS 130 nm technology. In order to perform the hybridization process, first UBM and then solder bumps have to be deposited on the