# Advantage and Challenge of Electrical Critical Dimension Test Structures for Electroplated High Aspect Ratio Nano Structures (HARNS) on Insulating Materials

Yoshio Mita, Ayako Mizushima, Noriko Kawai, Tsuboi Shinji, Yurie Inoue, 
Etsuko Ota, Shun Yasunaga, Ryosho Nakane, David Bourrier, Amel Beghersa, 
et al.

► To cite this version:

Yoshio Mita, Ayako Mizushima, Noriko Kawai, Tsuboi Shinji, Yurie Inoue, et al. . Advantage and Challenge of Electrical Critical Dimension Test Structures for Electroplated High Aspect Ratio Nano Structures (HARNS) on Insulating Materials. ICTMS 2025, IEEE, Mar 2025, Matsue, Japan. hal-05208090

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# Advantage and Challenge of Electrical Critical Dimension Test Structures for Electroplated High Aspect Ratio Nano Structures (HARNS) on Insulating Materials

Yoshio Mita<fnref n="1" />,<fnref n="2" />*, Ayako Mizushima<fnref n="1" />, Noriko Kawai<fnref n="2" />, Tsuboi Shinji<fnref n="2" />, Yurie Inoue<fnref n="2" />,  
Etsuko Ohta<fnref n="2" />, Shun Yasunaga<fnref n="1" />, Ryosho Nakane<fnref n="2" />, David Bourrier<fnref n="3" />, Amel Beghersa<fnref n="3" />, Hugues Granier<fnref n="3" />, and Akio Higo<fnref n="2" />

**Abstract**— Electrical Critical Dimension Test Structures (ECD-TS) have been applied for development of new technology: Metallic High Aspect Ratio Nano Structures (Metal-HARNS). The HARNS refer to electro mechanical structures scaled down to submicron width (as narrow as 260nm confirmed) while keeping its thickness (up to 1500nm confirmed). Two major advantage and challenge have been confirmed through measurement: (1) insulating material showed critical advantage on ECD over Scanning Electron Microscope CD assessment and (2) seed conductive layer affected the measurement as leakage path.

**Keywords**—Electrical Critical Dimension (ECD), High Aspect Ratio Nano Structures, MEMS, Electroplating

I. INTRODUCTION

The design dimension of Micro-Electro-Mechanical-
Systems (MEMS) have been stagnated as small as a couple of
microns for decades. Due to continuous demand for new
applications such as electromechanical new computational
devices [1], we are trying to scale down the dimension by the
order(s) of magnitude(s). We may call it Metallic High Aspect
Ratio Nano Structures (Metal-HARNS) (Fig.1), which is the
extension of High Aspect Ratio Micro Structures (HARNS),
which appeared around mid-1990s. Till now our engineering
group has been successful in scaling down to 260nm wide,
1400nm-thick HARNS by electroplating of Nickel (Ni) as
shown in Fig.2 [2]. To precisely assess its critical dimension,
however, we realized that traditional CD measurement using
Scanning Electron Microscope is not appropriate. It is due to
the fact that for the applications we need Metal HARNS be
made over insulating materials such as fused silica (glass)
wafer and silicon wafer with SiO₂ insulator. The insulating
layer is necessary as sacrificial etching layer for M/NEMS
releasing; As shown in Fig 3, during the measurement the
SEM image distorts due to the charge accumulation on the
metal structures over the insulating surface (known as charge-
up). Which means that the more precise image we want, the
longer the machine takes time for image acquisition, the more
electrons are exposed on the surface then the image is
distorted during the scanning (inherent tradeoff of resolution
and precision). Therefore we tried to apply the Electrical CD
measurement and confirmed its usefulness in our process
development.

II. TEST STRUCTURE DESIGN

Two 4550 × 4850 µm<fnref n="2" /> test structure groups have been
designed. One is with Test Structures having Greek cross [3,4]

<figure><img src="image_2.png" /><figcaption>Fig. 1. “Metal-HARNS” we aim to further scale down the dimension of microsystems. For a couple of decades the feature size has been stagnated around a couple of microns; we try to scale down by factor of ten, by using metal as a structural material.</figcaption></figure>

<figure><img src="image_3.png" /><figcaption>Fig. 2. Our state-of-the-art structure: 260nm-wide, 1400nm-high, 1260nm-pitch line structure of Ni material. Note: image was acquired with seed layer existence (with no image drift)</figcaption></figure>

and Linewidth Measurement Structures (Fig.4) and the other

<footnote n="1">¹ Department of Electrical Engineering and Information Systems, the University of Tokyo</footnote>

<footnote n="2">² Systems Design Lab (d.lab), School of Engineering, the University of Tokyo</footnote>

<footnote n="3">³ LAAS-CNRS, Toulouse, France</footnote>
<figure><img src="image_4.png" /><figcaption>(a) scan speed "Slow2"</figcaption></figure>

<figure><img src="image_5.png" /><figcaption>(b) scan speed "Rapid2"</figcaption></figure>

<figure><img src="image_6.png" /><figcaption>Fig. 5. After seed layer removal, Critical Dimension is almost impossible to determine by SEM observation due to image distortion induced by "charge-up" on insulator</figcaption></figure>

<figure><img src="image_7.png" /></figure>

<figure><img src="image_8.png" /><figcaption>Fig. 4. Electrical Critical Dimension design: Greek cross, linewidth TS, and some more (such as capacitors). Minimum width was set to be 0.26µm according to previous fabrication</figcaption></figure>

<figure><img src="image_9.png" /><figcaption>Fig. 3. Critical dimension SEM observation test structures. Lines/Spaces and dots patterns having fixed spacing (to 1 µm) and 1:1 spacing have been designed.</figcaption></figure>

is SEM observation structures (Fig.5). Each test structure was designed in a 125 × 125 µm² square area, and the TS group (for ECD and SEM) was designed in a 4 × 32 (column ABCD and Rows 01-32) matrix with a pitch of 150µm, plus an extra 50 µm to put number labels (yielding 650 × 4850 µm² in area). The unit TS group was intentionally designed vertically long and 7 groups with different exposure conditions has been placed side-by-side on the wafer with 650 µm-pitch. It was because our major scope of interest was the relationship between exposure dose conditions (current density with our high speed electron beam writing apparatus) to CDs. For production phase, one unit group can be put on the wafer as scribe-line test structure.

### III. VERIFICATION WITH MEASUREMENTS

We have established a "mask-less" process for "rapid and agile" prototyping (Fig.6). We use a thick (1500nm confirmed, can be as thick as 2000nm) Direct Electron Beam

<figure><img src="image_10.png" /></figure>

<figure><img src="image_11.png" /></figure>

<figure><img src="image_12.png" /></figure>

<figure><img src="image_13.png" /></figure>

<figure><img src="image_14.png" /><figcaption>Fig. 6. Metal HARNS process: A classical lithography + electroplating process (known as LIGA – Lithographie und GALvanoformung) was applied for scaled-down dimension using rapid EBL with very thick EB resist.</figcaption></figure>

(EB) resist (tok OEBR-CAP112PM). Wafer exposure is made using our rapid EB writers (Advantest F5112+VD01 and F7000S-VD02, depending on the machine availability. Both machines are with acceleration voltage of 50kV). Dose condition has been varied from 6.2 to 6.8 µC/cm². Two types of SEMI-standard, 525µm-thick 4-inch substrates have been used: (1) fused silica (AGC) and (2) Standard silicon wafer with CVD-deposited 2.0µm-thick SiO₂. In between the EB resist and insulating SiO₂, 50nm Cu seed layer with 5nm TiN adhesion layer had been sputtered. After 1mm development with standard 2.38% TMAH developer (tok NMD-W) with care, the wafer was treated in an O₂ plasma for 10seconds for descum and surface wetting. (SAMCO RIE-10NR, 100sccm O₂, 100Pa, 150W) Then 11 minutes of electroplating (Yamamoto-MS 4" apparatus) with 90mA for designed 0.1205dm² area (yielding current density of 0.75A/dm²) resulted a 1500nm -thick Ni Structure. The seed layer was removed by Neutral Loop Discharge (NLD) plasma etcher (ULVAC NLD-5700 Si) using Ar for one minute. The process
<figure><img src="image_15.png" /><figcaption>Fig. 7. Fabricated Metal HARNS test structure (Wafer serial #73). In the photograph the Cu layer looks opaque with dark copper color, but in reality it is semi-transparent and bright.</figcaption></figure>

parameters were as follows: Ar 50sccm, chamber pressure 3Pa, NLD plasma antenna power 2000W, bias power 100W.

Figure 7 shows a photograph of one of the fabricated wafers. During the Ar milling process, the wafer was partially masked by a cleaved silicon wafer, in order to leave seed layer to comparatively assess the influence of seed layer existence.

## IV. MEASUREMENT AND DISCUSSIONS

Our SEM measurement (Hitachi High-technologies FESEM Regulus SU8230, acceleration 1kV) revealed that the TS after seed layer removal exhibited a significant image drift during observation, and we could only observe “the most reasonable” image by the faster scan condition (the mode “Rough2”, with 1.5 second/frame, Fig.3). However under such a high scan-rate the image is very noisy so smaller features could not reliably be observed. That clearly underlined that **the Electrical CD measurement is more appropriate for Metal HARNS**.

As shown in Fig. 8, Greek Cross having different Width/Length ratio was measured and assessed. Four SMUs of a semiconductor parameter analyzer (Keysight B1500) were connected to each pad. The SMU4 (@Pad4) was defined as a ground terminal and the SMU1 (@Pad1) forced the voltage. The voltages of pads 2 and 3 were independently measured by SMUs 2 and 3 by configuring them as “force currents = 0A”. During the measurement, force voltage range was limited low ($V_{14} < \pm 50$ mV for around $\pm 5$ mA) in order not to induce resistance change by device heating [5]. Note that for this time the “Greek Cross-shaped” test structure was analyzed as a “simple line structure” – two-terminal resistance was extracted as $V_{14}/I$ line slope (Fig.8) and was examined in a function of its geometry ($L/W$) Such non-standard usage is due to the practical difficulty that we encountered while using a semiconductor parameter analyzer (but the difficulty was not particularly related to the machine brand).

<figure><img src="image_16.png" /></figure>

Classical GC use
equation:

$$ \rho_{\text{sq}} = \frac{\pi V_2 - V_3}{\ln 2 I} $$

This time
Analyzed as:

$$ R_{14} = \frac{V_{14}}{I} = \rho_{\text{sq}} \frac{L}{W} + R_{\text{parasitic}} $$

<figure><img src="image_17.png" /><figcaption>Fig. 9. F or this time we analyzed the Greek Cross Test Structure as a simple linewidth structure: resistance (assuming that $R_{14}$ is proportional to $L/W$ of the GC track)..</figcaption></figure>

<figure><img src="image_18.png" /><figcaption>Fig. 8. Sheet resistance was calculated as the slope, and y-axis cross-section gave residual parasitic resistance</figcaption></figure>

As shown in Fig.9, a very good linearity has been confirmed with a residual resistance of $R_{parasitic} = 2.3\Omega$. The residual resistance can be attributed to contact resistance of the pads and the semiconductor parameter analyzer cables (3m). The measurement done in another day adding other exposure conditions confirmed the measurement within $\pm 3\%$ of relative errors (Fig.10). It should be noted that the relative error is impossible to identify by SEM photographs analyses, not only by a heavy image drift but also the pixel resolution.

Two difficulties with this particular device (Metal HARNS) have been found. The first difficulty was the relatively low resistance (total $1 - 10\Omega$). It affected voltage measurement of Greek Cross. The voltage difference at the cross point $V_2 - V_3$ is very small. According to the value obtained by Fig.10, the voltage difference yields
<table><caption>Fig. 10. Comparison of Electrical CD measurement with SEM “ground truth” images. The ECD suggested that used EB resist is insensitive to overdose (within ±3% relative error). It corresponded with SEM images (where we are almost impossible to see the difference).</caption><thead><tr><th></th><th></th><th></th><th></th><th></th><th></th><th></th><th></th></tr></thead><tbody><tr><td>Dose[µC/cm2]</td><td>I:6.2</td><td>II:6.3</td><td>III:6.4</td><td>IV:6.5</td><td>V:6.6</td><td>VI:6.7</td><td>Average</td></tr><tr><td>R<sub>14</sub> - R<sub>para</sub> [Ω]</td><td>8.829</td><td>9.105</td><td>8.652</td><td>8.740</td><td>8.581</td><td>9.108</td><td>8.836</td></tr><tr><td>Rel. Shift [%]</td><td>-0.07</td><td>+3.04</td><td>-2.09</td><td>-1.09</td><td>-2.88</td><td>+3.09</td><td>-</td></tr><tr><td>SEM</td><td colspan="7">[SEM Image]</td></tr></tbody></table>

$$V_2 - V_3 = \frac{\pi}{\ln 2} \rho_{sq} I = 0.322I$$

It means that $V_2 - V_3$ was at maximal 1.6 mV at driving voltage $V_{14} = 50$ mV, and we have lost significant bits at low driving voltage areas. This significant bit loss was one of the major reasons why we did not use four-terminal measurement possibility of the SMUs. This is a tradeoff of choosing apparatus – all-in-one easy-use SMU with significant bit loss or combining dedicated precise voltmeter and current source that requires some control programming environment development. For this time we chose the former to reduce the time.

The second issue was related to particularity of the device fabrication process by electroplating. The electrical CD measurement method was reliably applicable only to the device “after” seed layer removal due to a significant leakage path through seed layer, although we would like to extend for “in-process evaluation”. The sheet resistance $ρ_{sq}$ for 50nm-thick copper is 0.44Ω/sq (=22[nΩm]/50[nm]), so the resistance of the seed layer (=leakage path) is as small as that of the test structures. Such low sheet resistance is obliged in order to avoid the voltage drop within the wafer. Clearly we need some test structure that can separate current contributions through the test structure and parasitic one through the seed layer.

## V. CONCLUSION

Electrical Critical Dimension Test Structure, which is the heart of the ICMTS conference, has been deployed for new development of High Aspect Ratio Nano Structure (HARNS). Related to the final application (such as movable MEMS), the structure were made over an insulating material. The superiority of the ECD over SEM observation was confirmed. Two major difficulties due to the device and process were identified: (1) low resistivity due to the metal material made it difficult to work with classical sheet resistance extraction by voltage drop measurement at the Greek-Cross, (2) parasitic current path through seed layer affected precise measurement of the in-process wafer. The problem (1) was avoided by using

the GC not as the “classical” use but as a simple line track structure. The second problem is still under investigation with consideration of new test structures.

## ACKNOWLEDGMENTS

This work was supported by CREST, JST (Grants No. JP-MJCR20T2), JSPS KAKENHI Grant No. 24K17595, 23H00171, and 24H00307, Advanced Research Infrastructure for Materials and Nanotechnology in Japan (ARIM)” of the Ministry of Education, Culture, Sports, Science and Technology (MEXT), Proposal Number JPMXP1224UT1123, and MEXT Initiative to Establish Next-generation Novel Integrated Circuits Centers (X-NICS) Grant Number JPJ011438. The electron beam lithography was performed using the rapid electron beam lithography system F5112+VD01 donated by Advantest Corporation. Takeda Sentanchi Supercleanroom engineering team is highly acknowledged for their daily supports.

## REFERENCES

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[2] Noriko Kawai, Ayako Mizushima, David Bourrier, Etsuko Ota, Amel Beghersa, Hugues Granier, and Yoshio Mita, “Nano-EB LIGA Process through LAAS-RENATECH and UTokyo Engineers Exchange”, Journées Nationales sur les Technologies Emergentes en micro-nanofabrication (JNTE 2024), 27-29 Nov., St Etienne, France (2024.11.27)

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[5] S. Enderling, et al., “Quantitative analysis of Joule heating in surface micromachined Greek cross test structures”, ICMTS 2007 pp. 218-221. doi: 10.1109/ICMTS.2007.374487