# A High-Efficiency 5.5kW Battery Backup Unit for OCP Open Rack V3 Using Partial Power Conversion

Martin Wattenberg, Lars Bohländer, Ulf Schwalbe, Matthias J Kasper, Gerald

Deboy

► To cite this version:

Martin Wattenberg, Lars Bohländer, Ulf Schwalbe, Matthias J Kasper, Gerald Deboy. A High-Efficiency 5.5kW Battery Backup Unit for OCP Open Rack V3 Using Partial Power Conversion. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0108 . hal-05095905

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# A High-Efficiency 5.5kW Battery Backup Unit for OCP Open Rack V3 Using Partial Power Conversion

Martin Wattenberg*, Lars Bohländer†, Ulf Schwalbe†, Matthias J. Kasper*, Gerald Deboy*

* Infineon Technologies Austria AG, Villach, Austria

† Hochschule Fulda, Fulda, Germany

martin.wattenberg@infineon.com

http://www.infineon.com

**Abstract**—Battery Backup Units (BBUs) are key components in modern, AI-centric data centers where uptime, efficiency, and high-power capability are critical. Additionally, BBUs can help to reduce the strain on grid infrastructure, due to their peak shaving capability.

This paper presents a highly efficient BBU based on a 5.5 kW DC-DC converter using a partial power concept. The output power can be maintained for a battery voltage from 35 to 62 V according to OCP V3 (50V). A power density of 290 W/inch³ is achieved with a converter size of 75 x 128 x 36 mm while maintaining an efficiency above 99%. A prototype has been built, and experimental results are presented.

***Index Terms***—Battery, Uninterruptible Power Supply, High Frequency Power Converter, Gallium Nitride

## I. INTRODUCTION

Battery backup units (BBUs) act as temporary power supplies in the event of a power grid failure, ensuring an uptime beyond 99.999%. With the publicly available Open Compute Project (OCP) specifications [1] the design of (hyper-scale) data center infrastructure has seen significant improvements over the years. In particular, a BBU is now placed on the DC side on a 48 V DC bus, avoiding the double AC/DC - DC/AC conversion of a typical UPS placed in series of the power flow. OCP V3 also introduces the option for peak shaving, which can significantly reduce stress on the upstream infrastructure, such as fuses and breakers, as well as help reduce distortion introduced by pulsed loads. Furthermore, the advancement of artificial intelligence (AI) and in particular training of large language models (LLMs) is driving data centers to even higher power levels.

Therefore, bidirectional BBUs with ultra-high efficiency ($η > 99\%$) are required to address the challenges in the current and future data-center landscape.

A battery backup unit for the OCP Open Rack V3 is presented in [2] that provides 3 kW output power.

The implementation uses a five-phase interleaved boost topology and achieves 98.5% under half load (31.6 A) and 98% efficiency under full load (63.2 A). The overall size of the board and inductors in particular is significant, compromising the space available for the battery itself. Scaling such a topology to 5.5 kW would require more parallel phases and thus significantly increase the bill of material.

A more effective approach is presented by [3] and is commonly known as "partial power" or "fractional charging" ([4], [5]). A distinction is made between the power ($P_{dir}$) that is transferred directly from the input to the output without any significant loss and the power ($P_{ind}$) that must be processed by the converter and is subject to typical conversion losses. The smaller $P_{ind}$ in relation to $P_{dir}$ becomes, the more efficient is the overall system. This also determines the voltage-current (VA) rating of the converter, which is ideally only a fraction of that of traditional converters.

To maximize $P_{dir}$ and thus the overall efficiency, the input ($V_{in}$) and output voltages ($V_{out}$) must be closely matched. For this reason **Sec. II** will give detailed considerations about the battery design in particular with a partial-power flow in mind. Compliance with OCP Open Rack V3 specifications is maintained. Afterwards **Sec. III** gives an overview of the implemented prototype along with its design considerations. Experimental results are presented in **Sec. IV**.

## II. SIZING OF THE BATTERY PACK

For optimal performance of the BBU, the power converter and battery need to be well matched and should ideally be designed hand-in-hand. The following section discusses the overall battery design regarding the amount of cells, implications for the converter design, size and arrangement within the housing, and thermal aspects.

### A. Battery Design

Given a fixed battery size of a 18650 cell due its wide availability, two key parameters need to be identified:
the number of cells in series and the number of cells in parallel. The former defines the overall voltage range to which the converter is subjected to, the latter has an important impact on battery voltage droop when the load current successively increases.

In order to maximize the number of cells and to find the most suitable voltage range for the following partial power converter, a matrix of possible configurations was examined in Fig. 1. Those configurations were considered whose nominal voltage is between 16 V and 100 V with and without load. Furthermore, power-loss within the cells is limited to 5 kW. The cell resistance of a single 18650 cell is assumed to be 43 mΩ according to [6].

<figure><img src="image_2.png" /><figcaption>Fig. 1. Battery pack power loss at a discharge power of 5.5 kW, a cell voltage of 3.7 V and an internal resistance of 43 mΩ/cell.</figcaption></figure>

The calculation clearly shows the positive trend towards lower power loss as the number of cells increases. The benefit here is two-fold: On the one hand, stress placed on the cells by high discharge currents is reduced. On the other hand, the load is distributed among more cells and individual cells are kept cooler, which reduces cell aging.

The matrix shows several configurations with the same minimum power loss. According to the model, several cell configurations with different nominal voltages are viable: 44 V (12s10p), 55 V (15s8p), and 74 V (20s6p). Given that the optimal battery configuration for the partial power principle is a small voltage difference around the output voltage, the second configuration is the most favorable.

Although the nominal battery voltage in a 15s8p configuration is attractive, the impact of internal resistance should be closely considered. A worst-case scenario with an $R_i$ of 43 mΩ is considered to take production spread and ageing effects of the individual cells into account. Additionally, contact resistances between the cells and towards the converter are also reflected in $R_i$.

Fig. 2 shows how much voltage ($V_{aux}$) needs to be added / subtracted from the overall battery voltage to achieve the targeted output voltage of 50 V. The four continuous lines show how $V_{aux}$ is affected by different output loads as the cell voltage drop becomes more and more significant. The effect is further exacerbated as the cell ages and $R_i$ increases. In this scenario, the battery voltage ranges from 47.25 V to 63 V without load and from 33.5 V to 53.3 V at peak power.

<figure><img src="image_3.png" /><figcaption>Fig. 2. Amplitude $V_{aux}$ with a cell discharge from 4.2V to 3.15V in 8p15s configuration ($R_i$ = 80.6 mΩ) at different output powers.</figcaption></figure>

Even though the commonly used 14s configuration with a maximum voltage of 58.8 V is attractive, as it does not require contact protection, the performance of the partial power converter could degrade, esp. towards the end of life where $R_i$ is higher. If 14s is still preferred, due to the availability of other hardware components such as battery management ICs, $R_i$ and the lifetime must be chosen accordingly. Alternatively, the end-of-charge voltage in the 15s-configuration can be limited to 4.0 V further prolonging the cell life-time while maintaining a voltage below 60 V.

## B. Mechanical Design Considerations

Given the OCP V3 specifications [1], the overall design must conform to 78.1 x 87.6 x 694 mm [W x H x D],
including housing. As highlighted previously, compactness of the cells as well as the power electronics is crucial as it enables lower individual cell stress, higher efficiency, and potentially longer battery life. Fig. 3 shows the space required for 120 18650 cells in a 15s8p configuration. A 60 x 60 x 38mm fan on the intake side is a common choice, providing adequate pressure for air to flow through the cells. This leaves only 128 mm for the full power-conversion stage incl. ancillary functions such as micro-controller, disconnect switch, fan controller, and connector.

By staggering the arrangement of the battery cells (Fig. 3), a gap of 1.5 mm between each cell and 7.5 mm between the main fan and the battery pack, it is possible to place up to 120 18650-cells. To easily facilitate series connections of the cells, the orientation is alternated throughout the full length of the unit.

<figure><img src="image_4.png" /><figcaption>Fig. 3. Side-view of entire BBU with dimensions of the main components.</figcaption></figure>

The space above the power electronics can be used to further increase the output power by modifying the converter. An extension to 8 kW is conceivable.

### C. Thermal design considerations

The OCP specifications require a controllable forced air cooling as an active cooling method. In data center environments, ambient temperatures up to 40°C according to [1] present a particular challenge. Consequently, larger batteries benefit from a higher thermal capacity, lower total internal resistance, as well as lower $I^2R$ losses per cell, and increased surface area.

A mathematical model was created to evaluate the cell heating caused by the internal resistance $R_i$ and the discharge current $I_{bat}$, which is determined according to

$$I_{bat} = \frac{V_{bat,oc}}{2 \cdot R_i} - \sqrt{\left(\frac{V_{bat,oc}}{2 \cdot R_i}\right)^2 - \frac{P_{out}}{R_i}} \quad (1)$$

where $V_{bat,oc}$ is the voltage of the open circuit battery pack and $P_{out}$ is the output power.

The specific heat capacity $c_{bat}$ was set to 1091.48 J/kg/K and the mass $m_{cell}$ per individual cell at 46.6 g according to [7]. Only the lateral surface of the battery cells $A_{cell}$ was considered as the surface for heat transfer for forced air cooling. The heat transfer coefficient $h_{cW}$ was determined using an empirical equation

$$h_{cW}(v) = 12.12 - 1.16 \cdot v + 11.6 \cdot \sqrt{v} \quad (2)$$

according to [8] for a resulting airflow $v$ of 3 m/s. Power loss results from joule heating due to the battery current $I_{bat}$ and the internal resistance of the battery $R_{bat}$.

$$\Delta T(t) \quad (3)$$

$$= \begin{cases} \frac{I_{bat}^2 \cdot R_{bat} \cdot t}{c_{bat} \cdot n_{cells} \cdot m_{cell} + n_{cells} \cdot A_{cell} \cdot h_{cW} \cdot t}, & t \le t_{off} \\ \frac{I_{bat}^2 \cdot R_{bat} \cdot t_{off}}{c_{bat} \cdot n_{cells} \cdot m_{cell} + n_{cells} \cdot A_{cell} \cdot h_{cW} \cdot t}, & t > t_{off} \end{cases} \quad (4)$$

Fig. 4 shows a comparison of a 14s8p and larger 15s8p battery under the two most demanding discharge scenarios of 5.5 kW for 90 s and 4 kW for 240 s per OCP specification. Even though the difference in battery volume is only 7%, about 16% lower temperature rise can be achieved according to calculations. This difference is due not only to the increased heat capacity and surface area but also to the lower joule heating per cell. In addition, side effects of air cooling such as the formation of hotspots in the rear third of the battery pack are of secondary importance.

The detailed considerations above have outlined why for a 50 V OCP V3 bus voltage an increase in battery capacity along with a slightly higher overall battery voltage is desirable. The 15s configuration creates a sweet spot by having the cell voltage centered around the bus voltage. This approach opens the door to a more effective converter design maintaining a constant output voltage.

## III. DESIGN OF PARTIAL POWER BBU

### A. Comparison Against State-of-the-Art

The motivation for a custom battery pack design in conjunction with a partial power concept is to reduce the amount of power conversion efforts, thus achieving the desired length of 128 mm (c.f. Fig. 3).

To quantify the improvements of the proposed partial power concept, Tab. I compares the commonly used
boost topology with the partial power and buck topology as a reference. The boost topology is particularly popular as it allows the use of 60 V-rated devices, compared to a buck which would require 100 V-rated switches in case of a 20s6p battery.

The number of interleaved phases is driven by design requirements (efficiency, size, cost). To achieve similarly high efficiency as can be achieved by a partial power concept, interleaving of 9 phases is considered in **Tab. I**.

In case of the partial power concept, an implementation with wider ($n_{LLC} = 1:1$) and narrower ($n_{LLC} = 2:1$) voltage range is considered. The attainable voltage range can be calculated based on battery voltage $V_{bat}$ and DCX turns ratio $n$ as follows

$$ \frac{V_{\text{bat}} \cdot (n_{\text{LLC}} - 1)}{n_{\text{LLC}}} \le V_{\text{out}} \le \frac{V_{\text{bat}} \cdot (n_{\text{LLC}} + 1)}{n_{\text{LLC}}}. \quad (5) $$

**Tab. I** distinguishes between direct and indirect stages. Indirect conversion is only present in the partial power concept as an intermediate step driven by the fixed-frequency LLC (DCX). Although the VA-rate of the device ($V_{DS,max} \cdot I_{DS,pk}$) is not insignificant, there are effectively no switching losses. Furthermore, the DCX does not need a dedicated resonant inductor and can be highly optimized [9], [10]. Due to the ZVS-operation, the chosen device can be optimized more towards lower conduction losses. This step is crucial as it can allow for lower device rating on the following buck stage.

Based on the consideration above, **Tab. I** shows the VA-rating for the respective topologies. The buck

<figure><img src="image_5.png" /><figcaption>Fig. 4. Battery pack temperature increase comparison of 14s and 15s.</figcaption></figure>

converter performs by far the worst, due to the high breakdown voltage required, while also having to deliver the full load current. Such a converter would need to provide about 13% more VA-rating compared to the commonly used boost topology (17.4 vs. 15.1 kVA). The VA-rating of the converter stages can be smaller compared to the boost and buck topology. Increasing the DCX turns ratio leads to a significantly reduction in the VA rating, but requires a battery configuration tailored to the use case. This shows that if the battery is well matched to the topology, significant improvements in efficiency and power density can be achieved. The narrow-range partial power converter can utilize 40 V devices in the direct power conversion stage which have significantly better figure-of-merits (FOMs), occupy a

<table><caption>TABLE I
COMPARISON OF DEVICE REQUIREMENTS OF TYPICAL TOPOLOGIES FOR A BBU.</caption><thead><tr><th>topology</th><th>Buck</th><th>Boost</th><th colspan="2">Partial Power</th></tr></thead><tbody><tr><td>#switches</td><td>18</td><td>18</td><td colspan="2">16</td></tr><tr><td>#battery</td><td>20s6p</td><td>11s10p</td><td>14s8p</td><td>15s8p</td></tr><tr><td>coils</td><td>9</td><td>9</td><td colspan="2">4</td></tr><tr><td>n<sub>LLC</sub></td><td>-</td><td>-</td><td>1:1</td><td>2:1</td></tr><tr><td>voltage range</td><td>56 V / 84 V</td><td>30.8 V / 46.2 V</td><td>39.2 V / 58.8 V</td><td>42 V / 63 V</td></tr><tr><td>P<sub>max</sub></td><td>5.5 kW</td><td>5.5 kW</td><td>1.1 kW</td><td>0.79 kW</td></tr><tr><td>processed</td><td></td><td></td><td></td><td></td></tr><tr><td colspan="5" style="text-align: center; font-weight: bold;">soft switching and static stages</td></tr><tr><td></td><td>-</td><td>-</td><td colspan="2">LLC (primary)</td></tr><tr><td>V<sub>DS,max</sub></td><td>-</td><td>-</td><td>80 V</td><td>80 V</td></tr><tr><td>I<sub>rms,max</sub></td><td>-</td><td>-</td><td>23.8 A</td><td>17.8 A</td></tr><tr><td>Σ</td><td>-</td><td>-</td><td>7.6 kVA</td><td>5.7 kVA</td></tr><tr><td colspan="5" style="text-align: center; font-weight: bold;">LLC (secondary)</td></tr><tr><td>V<sub>DS,max</sub></td><td>-</td><td>-</td><td>80 V</td><td>40 V</td></tr><tr><td>I<sub>rms,max</sub></td><td>-</td><td>-</td><td>28.1 A</td><td>35.6 A</td></tr><tr><td>Σ</td><td>-</td><td>-</td><td>7.6 kVA</td><td>5.7 kVA</td></tr><tr><td colspan="5" style="text-align: center; font-weight: bold;">Totem Pole</td></tr><tr><td>V<sub>DS,max</sub></td><td>-</td><td>-</td><td>80 V</td><td>40 V</td></tr><tr><td>I<sub>rms,max</sub></td><td>-</td><td>-</td><td>110 A</td><td>110 A</td></tr><tr><td>Σ</td><td>-</td><td>-</td><td>17.6 kVA</td><td>8.8 kVA</td></tr><tr><td colspan="5" style="text-align: center; font-weight: bold;">direct conversion stage</td></tr><tr><td></td><td>Buck (×9)</td><td>Boost (×9)</td><td colspan="2">Buck (×3)</td></tr><tr><td>V<sub>DS,max</sub></td><td>100 V</td><td>60 V</td><td>80 V</td><td>40 V</td></tr><tr><td>I<sub>rms,max</sub></td><td>11.5 A / 7.8 A</td><td>15.6 A / 12.3 A</td><td>36.7 A / 36.7 A</td><td>36.7 A / 36.7 A</td></tr><tr><td>(HS/LS)</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>Σ</td><td>17.4 kVA</td><td>15.1 kVA</td><td>17.6 kVA</td><td>8.8 kVA</td></tr></tbody></table>
smaller footprint, and are more cost-effective.

## B. Implemented Prototype

Based on the considerations of Tab. I, the simplified schematic of the narrow-range DCX design is shown in Fig. 5. In series with the battery voltage $V_{bat}$ a second, smaller voltage $V_{aux}$ is placed. The amplitude and polarity of $V_{aux}$ is controlled by a 3-phase interleaved buck converter through the duty cycle $d$ and a totem pole stage to change the polarity, respectively. The input voltage of the buck converter is the floating voltage $V_{mid}$, which is directly proportional to $V_{bat}$ divided by the transformer turn-ratio $n_{LLC}$. By connecting the battery anode to the positive or negative side of $V_{mid}$ via the totem pole stage, $V_{aux}$ can be added or subtracted from the battery voltage, which can be expressed as

$$ V_{out} = V_{bat} + V_{aux} = \begin{cases} V_{bat} - (1-d) \cdot V_{mid}, & V_{bat} > V_{out} \\ V_{bat} + d \cdot V_{mid}, & V_{bat} \le V_{out} \end{cases} \quad (6) $$

Fig. 6 shows the necessary duty cycle in correlation with $V_{bat}$ to maintain a constant output voltage. In addition, the battery and output current $I_{bat}$ and $I_{out}$ are shown, as well as the unprocessed direct current $I_{dir}$ and the regulated current $I_{conv}$. The higher $I_{dir}$ in relation to $I_{conv}$ is, the more efficient the overall system operates. When $V_{bat}$ is equal to $V_{out}$, no current needs to be regulated. A drawback is that the duty cycle also experiences a discontinuity around this point, which demands suitable control strategies.

<figure><img src="image_6.png" /><figcaption>Fig. 6. Share of unregulated current $I_{dir}$ and regulated current $I_{conv}$ at $P_{out} = 5.5$ kW at $V_{out} = 49$ V.</figcaption></figure>

In particular, the operation with nearly 100% duty cycle on the high-side for $V_{bat} > 50$ V is nontrivial.

To avoid additional complexity from additional isolated supplies, a pulse-skipping scheme is implemented. Such a scheme respects the minimum on-time for the low-side in order for bootstrapping to function but is able to achieve duty-cycles very close to 100%. In effect, the switching frequency is reduced in these extreme conditions. However, this is not a problem with respect to the output-voltage ripple as it can be maintained.

The implemented prototype is shown in Fig. 7 with an isometric and bottom-side view. It precisely meets the required dimensions of 75 x 115 mm [W x D] to fit the 15s8p battery. The converter height is only 36 mm including the controller, allowing to potentially double the power on the same footprint. The power-density of the implemented converter is 290 W/in³ or 17.7 kW/lit. With such a high power density, cooling is critical, and dual-side cooled devices are used on the bottom-side of the PCB. These take advantage of the surface area provided by the PCB and can also be thermally connected to the housing for even better thermal performance.

The three interleaved buck converters use 0.4 mΩ (HS) and 0.6 mΩ (LS) MOSFETs, optimized for duty cycles below 0.5 for an input voltage $V_{bat}$ between 40 V and 50 V. The power inductors use N48-RM8 ferrites with three and a half windings and an air gap of 700 µm, giving 2.5 µH inductance per phase. With a switching frequency of 270 kHz per buck, this results in an effective switching frequency of 810 kHz. To improve efficiency in light-load, a phase-shedding scheme is implemented. Output current balancing, over-current protection and current-feedforward for improved dynamic is enabled by separate Hall current sensors (Infineon TLE4973).

The totem pole uses two 0.6 mΩ FETs in parallel for low conduction losses. In the case of $V_{bat} = V_{out}$, these devices need to handle the full output current of 112 A.

$V_{mid}$ is derived from $V_{bat}$ via the 2:1 DCX running at 510 kHz with an RM14 ferrite. The device on the primary side are 100 V GaN HEMTs in parallel with 2.5 mΩ and on the secondary side 40 V MOSFETs with 0.6 mΩ.

## IV. EXPERIMENTAL EVALUATION

The efficiency of the entire system has been measured throughout the operating range for $V_{bat}$ and $I_{out}$ and the efficiency map is shown in Fig. 8. In order to observe device temperatures, no heatsink was mounted, thus slightly higher $R_{DS(on)}$ values were tolerated due to increased junction temperature. The measurement results can therefore be considered conservative.

Across a wide operation range, the efficiency is well above 99%. It is notable that the plateau is skewed
<figure><img src="image_7.png" /><figcaption>Fig. 5. Schematic</figcaption></figure>

<figure><img src="image_8.png" /><figcaption>Fig. 7. Isometric view (top) and bottom side view (bottom) of the implemented prototype.</figcaption></figure>

towards a lower battery voltage between 40 and 50 V and not symmetric around 50 V. This is by design and is caused by the asymmetric $R_{DS(on)}$ of the buck MOSFETs, optimized for duty cycles below 0.5. In practice, the converter would not experience an input

voltage of 60 V and an output current of 110 A at the same time. Even a new and fully charged battery will experience some *IR*-drop, thus reducing the effective input voltage. However, the plateau can be shifted by using identical devices for the high and low-side on the buck if desired.

<figure><img src="image_9.png" /><figcaption>Fig. 8. Measured system efficiency at different input voltages $V_{bat}$.</figcaption></figure>

At very low input voltages ($V_{bat} < 38$ V) and high currents, the converter is thermally limited. To better understand this behavior, a thermal image of the bottom side of the PCB is shown in **Fig. 9** at 5.5 kW for two input voltage conditions. On the one hand, the bottom half of the image shows an almost ideal scenario with $V_{bat} = 48$ V and $V_{out} = 49$ V. On the other hand, the top half shows the same power level at $V_{bat} = 40$ V. What can be clearly seen is the significant temperature difference on the secondary LLC MOSFETs of about 50 K. At lower $V_{bat}$ the combination of magnetization
current and (short) deadtime is insufficient to achieve
a full ZVS-transition. Increasing the air-gap and overall
magnetization current would allow full ZVS-transition
but degrade efficiency elsewhere. Therefore, a current-
and voltage-dependent deadtime can improve perfor-
mance under these corner cases.

It should be noted that the buck converter on the left
side of the board experiences only minimal additional
heating when going from 48 to 40 V (c.f. Fig. 6) and
is not the thermal bottleneck. However, the outermost
phase becomes slightly warmer than the center one, due
to its position on the PCB.

<figure><img src="image_10.png" /><figcaption>Fig. 9. Heat development comparison at an output power of 5.5kW at input voltages of 40 V and 48V with forced air cooling (10 m/s).</figcaption></figure>

A split-of-losses was calculated in **Fig. 10** based on
measurement data for V<sub>bat</sub> from 38 to 60 V. As men-
tioned above, the losses on the LLC increase significantly
at a lower V<sub>bat</sub>, due to the lack of a complete ZVS tran-
sition. At 38 V, 50 of 150 W losses can be attributed to
the incomplete ZVS transition. This is very encouraging,
as it can almost fully be avoided by an adaptive deadtime
scheme paired with tuning the magnetization current and
possibly devices with lower output charge.

On the other hand, for V<sub>bat</sub> from 50 V to 60 V, no
unexpected behavior can be seen in the loss composition.
The amount of power that must be processed by the
partial power converter increases steadily with V<sub>bat</sub> and
so does the voltage at V<sub>mid</sub>. Higher switching losses as
well as increased hysteresis losses due to higher current
ripple are the consequence.

Lastly, note that static elements such as the PCB,
current sensor, and totem pole contribute a sizable part
of the overall losses. The entire design was implemented

<figure><img src="image_11.png" /><figcaption>Fig. 10. Split of losses at an output power of 5.5 kW and a voltage setpoint of 50 V.</figcaption></figure>

<figure><img src="image_12.png" /><figcaption>Fig. 11. Waveform during operation when transitioning for 54 to 44 V on V<sub>bat</sub>.</figcaption></figure>

on an 8-layer PCB with 2 oz copper per layer. The
totem pole uses only two MOSFETs in parallel. For
the absolute highest efficiency, more layers could be
used, and additional devices on the totem pole could be
paralleled.

An operational waveform is shown in **Fig. 11**. At the top, the switch-node voltage of the DCX primary and secondary side is shown. The 2:1 transfer ratio can be seen by the relative size of the waveforms. The battery voltage V<sub>bat</sub> is ramped down from 54 to 44 V within two milliseconds while V<sub>bat</sub> is kept steady. Such a transient would not occur in practice but was chosen for visibility of traces and tuning the control loop under worst-case conditions. Note that V<sub>bat</sub> and are AC-coupled to study the impact of totem-pole operation more closely. Furthermore, no additional output capacitors beyond what is provisioned on the PCB was
used. However, the OCP V3 specifications allows up to 20 mF per BBU. With the preliminary control-loop the voltage ripple during transition does not exceed ± 400 mV. Additional capacitance could be used to reduce this value further is needed. The three trace at the bottom show the switch-node voltage of the interleaved buck converter where this duty-cycle changed from above 99% before the trigger point to below 1% after the trigger point. Higher granularity in PWM resolution with newer controllers can further improve transient behavior.

V. CONCLUSION

Based on the rapidly growing power demand in data centers, in particular driven by the energy required for AI training, this paper presents a very compact (75 x 115 x 36 mm) 5.5 kW partial power converter for a battery backup unit capable of bidirectional energy flow and suitable for peak shaving, thus reducing strain on the upstream infrastructure.

Comprehensive consideration for the system design outlines the benefits of a 15s8p battery configuration: up to 16% lower cell losses, lower current stress, and more margin to keep cell voltage in the optimal range.

The presented 5.5 kW partial power converter is specifically designed for this battery configuration and achieves over 99% efficiency across a wide voltage range (40 to 55 V) and current range (20 to 100 A). The partial power concept allows one to use fewer and smaller devices, reducing the device VA-rating by well over 50% compared to the state-of-art.

The unused space above the converter in the pro-
totype housing offers the potential for simple scaling
of the output power to 8 kW and above. The exper-
imental evaluation has demonstrated the potential for
further enhancement of efficiency through a number of
optimizations and adjustments, particularly to the LLC.

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