Multi-stage power converter with transformless switched-capacitor converter and control

This disclosure includes novel ways of implementing a power supply that powers a load. More specifically, a power supply includes a controller. The controller controls operation of a first power converter stage and a second power converter stage to convert an input voltage into an output voltage. For example, the first power converter stage is operative to receive an input voltage and convert the input voltage into an intermediate voltage. The second power converter stage such as a transformer-less switched-capacitor converter is coupled to the first power converter stage. The second power converter stage receives the intermediate voltage and converts the intermediate voltage into an output voltage to power a load.

BACKGROUND

There are multiple types of switching power converters. For example, one type of conventional switching power converter is a buck converter. In general, to maintain an output voltage within a desired range, a controller associated with the buck converter compares the magnitude of a generated output voltage to a setpoint reference voltage. Based on a respective error voltage, the controller modifies a respective switching frequency and/or pulse width modulation associated with activating high side switch circuitry or low side switch circuitry in the buck converter.

Another type of power converter is a so-called switched-capacitor converter. In general, a switched capacitor voltage converter performs energy transfer and voltage conversion using capacitors.

Next generation communication services will include base stations having increased power demands. A typical set-up may include an AC-DC converter at the base of a telemetry tower from which a −48V bus is routed to the antenna at the top of the tower. There, the bus voltage will need to be converted to a different voltage value. Since the bus voltage may vary between the different vendors and also due to voltage drops in the cable, the input voltage of this converter may vary such as between −35V to −75V with short spikes up to −100V.

BRIEF DESCRIPTION

Implementation of clean energy (or green technology) is very important to reduce our impact as humans on the environment. In general, clean energy includes any evolving methods and materials to reduce an overall toxicity on the environment from energy consumption.

This disclosure includes the observation that raw energy, such as received from green energy sources or non-green energy sources, typically needs to be converted into an appropriate form (such as desired AC voltage, DC voltage, etc.) before it can be used to power end devices such as servers, computers, mobile communication devices, wireless base stations, etc. Regardless of whether energy is received from green energy sources or non-green energy sources, it is desirable to make most efficient use of raw energy provided by such systems to reduce our impact on the environment. This disclosure contributes to reducing our carbon footprint and better use of energy via more efficient energy conversion.

Embodiments herein include novel ways of implementing a power supply that powers a load. More specifically, embodiments herein include an apparatus and/or system including a controller. The controller controls operation of a first power converter stage and a second power converter stage to convert an input voltage into an output voltage. For example, in one embodiment, the first power converter stage is operative to receive an input voltage and convert the input voltage into an intermediate voltage. The second power converter stage such implementing as a transformer-less switched-capacitor converter is coupled to the first power converter stage. The second power converter stage receives the intermediate voltage and converts the intermediate voltage into an output voltage to power a load.

In one embodiment, the intermediate voltage produced by the first power converter stage is a negative voltage. The second power converter stage is a voltage inverter operative to convert the intermediate voltage into the output voltage, the output voltage being a positive voltage. Accordingly, embodiments herein include receiving an input voltage (of negative polarity) at a first power converter stage and converting it into an intermediate voltage of negative polarity from the first power converter stage. The second power converter stage converts the negative intermediate voltage into a positive output voltage. In still further example embodiments, a magnitude of the output voltage is substantially equal to a magnitude of the intermediate voltage. In such an instance, the second power converter stage is an inverter.

Further embodiments herein include a controller. The controller is operative to: i) receive an output voltage feedback signal derived from the output voltage, and ii) regulate generation of the intermediate voltage and/or output voltage based on a magnitude of the output voltage feedback signal.

In accordance with further example embodiments, the second power converter stage is operative to provide unregulated conversion of the intermediate voltage into the output voltage.

Further embodiments herein include a controller operative to: i) receive an intermediate voltage feedback signal derived from the intermediate voltage, and ii) regulate generation of the intermediate voltage based on the intermediate voltage feedback signal.

In still further example embodiments, the controller is operative to: i) vary a switching frequency of operating switches in the first power converter stage (such as a buck converter or other suitable entity) to convert the input voltage into the intermediate voltage, and ii) set a switching frequency of the second power converter stage to a predetermined switching frequency value. In one embodiment, the switching frequency of the second power converter stage is set to a resonant frequency associated with a switched-capacitor converter in the second power converter stage.

The second power converter stage can be configured in any suitable manner. For example, in one embodiment, the second power converter stage includes: i) a first resonant capacitor and a second resonant capacitor; and ii) an inductor coupling the first resonant capacitor and the second resonant capacitor, the inductor supporting zero voltage switching of switches in the second power converter stage to convert the intermediate voltage into the output voltage.

In further example embodiments, the second power converter stage includes: a first capacitor, multiple switches, a second capacitor, an input voltage node that receives the intermediate voltage, and an output voltage node that outputs the output voltage.

By way of non-limiting example embodiment, the multiple switches includes: a first pair of switches operative to switch between connecting a first node of the first capacitor between the output node and a ground reference voltage; a second pair of switches operative to switch between connecting a second node of the first capacitor between the ground reference voltage and the input voltage node; a third pair of switches operative to switch between connecting a first node of the second capacitor between the output node and the ground reference voltage; and a fourth pair of switches operative to switch between connecting a second node of the second capacitor between the output node and the ground reference voltage.

In still further example embodiments, the second power converter stage includes a circuit path extending between the first node of the first capacitor and the first node of the second capacitor. The inductor supports zero voltage switching of the switches in the second power converter stage to convert the intermediate voltage into the output voltage. The second power converter stage includes a third capacitor. In one embodiment, the third capacitor is a DC bias blocking capacitor such as in series with a zero voltage switching inductor. Thus, the third capacitor is disposed at any suitable location such as in series with the inductor between the first node of the first capacitor and the first node of the second capacitor.

In still further example embodiments, the first pair of switches and the second pair switches are disposed in series between the output voltage node and the input voltage node. The third pair of switches and the fourth pair switches are disposed in series between the output voltage node and the input voltage node.

Embodiments herein include one or more of the following features:Transformer-less voltage regulation and inversion capability at highest power density and efficiencyLower voltage ratings of the semiconductor devices (switches) compared to a standard inverting buck-boost converters, which allows leveraging of the superior FOM of these devices for high frequency operationHigh and flat efficiency curve over the load rangeSimple control concept by regulating the output voltage with the buck stage with standard CCM (Continuous Conduction Mode) fixed frequency operation and an unregulated ZSC (Zero Switching Current) stage for voltage inversionEasy start-up with the buck stage without requiring any additional e-fuse, etc.

These and other more specific embodiments are disclosed in more detail below.

Note that although embodiments as discussed herein are applicable to power converters, the concepts disclosed herein may be advantageously applied to any other suitable topologies as well as general power supply control applications.

Note that any of the resources as discussed herein can include one or more computerized devices, controller, mobile communication devices, servers, base stations, wireless communication equipment, communication management systems, workstations, user equipment, handheld or laptop computers, or the like to carry out and/or support any or all of the method operations disclosed herein. In other words, one or more computerized devices or processors can be programmed and/or configured to operate as explained herein to carry out the different embodiments as described herein.

Accordingly, embodiments herein are directed to methods, systems, computer program products, etc., that support operations as discussed herein.

One embodiment herein includes a computer readable storage medium and/or system having instructions stored thereon. The instructions, when executed by computer processor hardware, cause the computer processor hardware (such as one or more co-located or disparately located processor devices) to: convert a received input voltage into an intermediate voltage; and via a transformer-less second power converter stage coupled to the first power converter stage, convert the intermediate voltage into an output voltage to power a load.

The ordering of the steps above has been added for clarity sake. Note that any of the processing operations as discussed herein can be performed in any suitable order.

As discussed herein, techniques herein are well suited for use in the field of implementing one or more inductor components to deliver current to a load. However, it should be noted that embodiments herein are not limited to use in such applications and that the techniques discussed herein are well suited for other applications as well.

Also, note that this preliminary discussion of embodiments herein (BRIEF DESCRIPTION OF EMBODIMENTS) purposefully does not specify every embodiment and/or incrementally novel aspect of the present disclosure or claimed invention(s). Instead, this brief description only presents general embodiments and corresponding points of novelty over conventional techniques. For additional details and/or possible perspectives (permutations) of the invention(s), the reader is directed to the Detailed Description section (which is a summary of embodiments) and corresponding figures of the present disclosure as further discussed below.

DETAILED DESCRIPTION

Embodiments herein include novel ways of implementing a power supply that powers a load. More specifically, embodiments herein include an apparatus and/or system including a controller. The controller controls operation of a first power converter stage and a second power converter stage to convert an input voltage into an output voltage. For example, in one embodiment, the first power converter stage is operative to receive an input voltage and convert the input voltage into an intermediate voltage. The second power converter stage such as a transformer-less switched-capacitor converter is coupled to the first power converter stage. The second power converter stage receives the intermediate voltage and converts the intermediate voltage into an output voltage to power the load.

Now, more specifically,FIG.1is an example general diagram of a power system (power supply) including multiple power converters according to embodiments herein.

In this example embodiment, the power supply100includes a controller140, first power converter111(i.e., first power converter stage), and second power converter112(i.e., second power converter stage).

During operation, the controller140controls operation of the first power converter111and the second power converter112to convert an input voltage120(such as negative Vin) into an output voltage123(such as a positive output voltage value).

More specifically, in one embodiment, the first power converter111receives input voltage120and converts the input voltage120into an intermediate voltage121. The second power converter112such as a transformer-less switched-capacitor converter131is coupled to the first power converter111. The second power converter112receives the intermediate voltage121and converts the intermediate voltage121into an output voltage123to power the load118.

In one embodiment, the intermediate voltage121produced by the first power converter111is a negative voltage value. In one embodiment, the second power converter112is a voltage inverter operative to convert the intermediate voltage121(such as a DC voltage) into the output voltage123. Via inversion supplied by the switched-capacitor converter131, such as switching from −V to +V, the power converter112produces the output voltage123to be a positive voltage value (such as a DC voltage). In such an instance, embodiments herein include converting an input voltage120(of negative polarity) and converting it into an output voltage123of positive polarity.

In still further example embodiments, a magnitude of the output voltage123is substantially equal (such as within 10%) to a magnitude of the intermediate voltage121.

As previously discussed, the power supply100includes controller140. The controller140: i) receives an output voltage feedback signal123-1derived from the output voltage123, and ii) regulates generation of the intermediate voltage based on a magnitude of the output voltage feedback signal. In one embodiment, the output voltage feedback signal123-1is equal to the output voltage123. Alternatively, a magnitude of the output voltage feedback signal123-1is a fraction of the magnitude of the output voltage123.

As further shown, the controller140compares the output voltage feedback signal123-1to a reference voltage103. Based on the comparison, the controller140produces control signals104to control operation (regulation) of the first power converter111and conversion of the input voltage120into the respective intermediate voltage121.

Further embodiments herein include, in addition to or as an alternative to regulating based on the output voltage feedback signal123-1as previously discussed, a controller140operative to: i) receive an intermediate voltage feedback signal121-1derived from the intermediate voltage121, and ii) regulate generation of the intermediate voltage121based on the intermediate voltage feedback signal121-1.

In still further example embodiments, the controller140receives feedback indicating a magnitude of the currents associated with intermediate voltage121and/or the output voltage123. The controller140can be configured to use none, one, or both of the detected currents outputted from the first power converter111and/or the second power converter112to generate respective control signals104and/or105.

In addition to producing control signals104, the controller140(or other suitable entity) produces control signals105supplied to the switched-capacitor converter131. As further discussed herein, the second power converter112(and corresponding one or more switched-capacitor converter131) provides unregulated conversion of the intermediate voltage into the output voltage123.

Note that embodiments herein are useful over conventional techniques. For example, in contrast to conventional techniques, and as further discussed herein, the novel power supply as described herein provides high efficiency of converting an input voltage to a respective output voltage via unique first stage regulation (such as via power converter111) and second stage voltage conversion provided by the transformer-less switched-capacitor converter131.

FIG.2is an example diagram illustrating a first power converter stage according to embodiments herein.

In this non-limiting example embodiment, the power converter111is configured to include one or more buck converters (or other suitable power converter entities) operating in parallel.

For example, the first buck converter of power converter111in this embodiment includes switch QA1, switch QA2, and inductor L1. The second buck converter in the power converter111includes switch QB1, switch QB2, and inductor L2.

As further shown, the switch QA1is connected in between the ground reference and the node210receiving the input voltage120. For example, as further shown, the drain of switch QA1is connected to the ground reference. The source node of switch QA1is connected to the drain node of switch QA2as well as the input of the inductor L1at node211. The output of the inductor L1is connected to the node221.

The switch QB1is connected in between the ground reference and the node210receiving the input voltage120. For example, as further shown, the drain of switch QB1is connected to the ground reference. The source node of switch QB1is connected to the drain node of switch QB2as well as the input of the inductor L2at node212. The output of the inductor L2is connected to the node221.

Capacitor Cmid stores the output voltage123.

In this general manner, any number of buck converters can be connected in parallel to produce the output voltage123.

Note again that although the power converter111inFIG.2is illustrated as a buck converter configuration, the power converter111can be instantiated as any suitable type of voltage converter providing regulation as described herein.

In accordance with further example embodiments, during operation, the controller140produces control signals104(such as SA1, SA2, SA3, and SA4) to control respective switches QA1, QA2, QB1, and QB2based on the error voltage255derived from comparing the output voltage feedback signal123-1to the reference voltage102.

Control signal SA1controls switch QA1; control signal SA2controls switch QA2; control signal SB1controls switch QB1; control signal SB2controls switch QB2.

Via switching of the switches QA1and QA2based on control signals SA1and SA2, node211coupling the source node of switch QA1and the drain node of switch QA2provides current through the inductor L1, resulting in generation of the intermediate voltage121.

Via switching of the switches QB1and QB2based on control signals SA3and SA4, node212coupling the source node of switch QB1and the drain node of switch QB2provides current through the inductor L2, resulting in generation of the intermediate voltage121.

In one embodiment, the controller140controls switching of the switches QA1and QA2based on one or more feedback parameters in a manner as previously discussed. For example, as previously discussed, the controller140can be configured to receive output voltage feedback signal123-1derived from the output voltage123supplied to power the load118as previously discussed inFIG.1.

Referring again toFIG.2, in one embodiment, via the comparator250, the controller140compares the output voltage feedback signal123-1(such as output voltage123itself or derivative signal) to the reference voltage102. As previously discussed, the reference voltage102is or corresponds to a desired setpoint in which to control a magnitude of the output voltage123.

Based on the comparison as provided by comparator240, the comparator240produces a respective error voltage255indicating the difference between the output voltage feedback signal123-1and the reference voltage102. A magnitude of the error voltage varies depending upon the degree to which the magnitude of the output voltage123is in or out of regulation (with respect to a reference voltage102).

As further shown, the PWM controller260of the controller140controls operation of switching the switches QA1, QA2, QB1, and QB2based upon the magnitude of the error voltage255. For example, if the error voltage255indicates that the output voltage123(of the power converter112) is less than a magnitude of the reference voltage102, the PWM controller260increases a duty cycle of activating the high side switch QA1(thus decreasing a duty cycle of activating the low-side switch QA2) in a respective switching control cycle.

Conversely, if the error voltage255indicates that the output voltage123(of the power converter111) is greater than a magnitude of the reference voltage102, the PWM controller260decreases a duty cycle of activating the high side switch QA1(thus increasing a duty cycle of activating the low-side switch QA2) in a respective switching control cycle.

The controller140controls the second phase of the power converter111in a similar manner based on comparison of the output voltage feedback signal123-1or intermediate voltage121with respect to the reference signal102.

In one embodiment, via variations in the pulse with modulation and/or switching frequency of controlling the respective switches QA1, QA2, QB1, and QB2, the controller141controls generation of the intermediate voltage121and the output voltage123such that the output voltage123remains within a desired voltage range.

In still further example embodiments, the controller140is configured to, in a frequency modulation mode, vary a switching frequency of operating switches QA1, QA2, QB1, and QB2in the first power converter111(such as a buck converter or other suitable entity) to convert the input voltage120into the intermediate voltage121.

In a similar manner, the controller140and corresponding circuitry can be configured to control regulation of the respective power converter111based on the comparison of the intermediate voltage feedback signal121-1to the reference voltage102.

As further discussed below inFIG.3, the controller140(or other suitable entity) sets a switching frequency of the second power converter112(switched-capacitor converter131) to a predetermined switching frequency value that is efficient to convert the intermediate voltage121into the output voltage123. In one embodiment, the controller140sets the switching frequency of the switched-capacitor converter131to a value of the resonant frequency associated with the switched-capacitor converter131.

FIG.3is an example diagram illustrating a second power converter stage according to embodiments herein.

As previously discussed, the input voltage node151of the power converter112receives intermediate voltage121. As further shown, capacitor Cin is connected between the input voltage node151and ground.

The switches Q1, Q2, Q3, and Q4, are connected in series between the output voltage node152and the input voltage node151. For example, the drain node of switch Q4is connected to the output voltage node152; the source node of switch Q4is connected to the drain node of switch Q3at node351; the source node of switch Q3is connected to the drain node of switch Q2at the ground reference voltage; the source node of switch Q2is connected to the drain node of switch Q1at node352; the source node of switch Q1is connected to the input voltage node151.

The switches Q5, Q6, Q7, and Q8, are connected in series between the output voltage node152and the input voltage node151. For example, the drain node of switch Q8is connected to the output voltage node152; the source node of switch Q8is connected to the drain node of switch Q7at node361; the source node of switch Q7is connected to the drain node of switch Q6at ground; the source node of switch Q6is connected to the drain node of switch Q5at node362; the source node of switch Q5is connected to the input voltage node151.

In one embodiment, series circuit including capacitor CDC and inductor311(such as Lzvs) is connected between the node351and node361. Capacitor CDC is optional.

In one embodiment, the capacitor CDC is not present in the circuit. In such an instance, the node351is shorted with a circuit trace to node386. In other words, in one embodiment, the capacitor CDC is replaced with a zero ohm resistor or trace between the node351and node386.

Capacitor Cmid is connected between the ground reference and the input voltage node151. Capacitor Cout is connected between the output voltage node152and the ground reference.

Thus, the multiple switches Q1-Q8of the switched capacitor converter131include: a first pair of switches (such as switch Q3and Q4) operative to switch between connecting a first node351of the first capacitor CRES1between the output voltage node152and the ground reference voltage; a second pair of switches (such as switches Q1and Q2) operative to switch between connecting a second node352of the first capacitor CRES1between the ground reference voltage and the input voltage node151; a third pair of switches (such as switch Q8and switch Q7) operative to switch between connecting a first node361of the second capacitor CRES2between the output voltage node152and the ground reference voltage; and a fourth pair of switches (such as switch Q5and switch Q6) operative to switch between connecting a second node362of the second capacitor CRES2between the input voltage node151and the ground reference voltage.

As previously discussed, the power converter112(or switched capacitor converter131) includes a circuit path extending between the first node351of the first capacitor CRES1and the first node361of the second capacitor CRES2. The inductor311in the series circuit path supports zero voltage switching of the switches in the power converter112to convert the intermediate voltage121into the output voltage123.

In one embodiment, the power converter112and series circuit path further includes a capacitor CDC. In one embodiment, this third capacitor (CDC) such as a DC bias blocking capacitor. The capacitor CDC is disposed at any suitable location such as in series with the inductor311between the first node351of the first capacitor CRES1and the first node361of the second capacitor CRES2.

Thus, the second power converter112can be configured in any suitable manner. For example, in one embodiment, the second power converter112includes: i) a first resonant capacitor CRES1and a second resonant capacitor CRES2; and ii) an inductor311coupling the first resonant capacitor CRES1and the second resonant capacitor CRES2, the inductor311supporting zero voltage switching of switches (Q1-Q8) in the second power converter stage to convert the intermediate voltage121into the output voltage123.

Accordingly, in one embodiment, the power converter112includes: a first capacitor CRES1, a second capacitor CRES2, an input voltage node151that receives the intermediate voltage121, an output voltage node152that outputs the output voltage123, and multiple switches Q1-Q8.

FIG.4is an example timing diagram illustrating phase control and resonant current according to embodiments herein.

In general, as shown in graph400, the controller140produces the control signal105-2to be an inversion of control signal105-1. A pulse width of each control signal is approximately 48% of the switching period or other suitable pulse width modulation value.

Between time T0and time T1, between time T4and T5, etc., (a.k.a., mode A), when the control signal105-1(at a logic high) controls the set of switches Q1, Q3, Q6, and Q8, to an ON state (low impedance or short circuit), the control signal105-2(logic lo) controls the set of switches Q2, Q4, Q5, and Q7, to an OFF state (very high impedance or open circuit).

Conversely, between time T2and time T3, between time T6and T7), etc., (a.k.a., mode B), when the control signal105-2(logic high) controls the set of switches Q2, Q4, Q5, and Q7, to an ON state, the control signal105-1(logic low) controls the set of switches Q1, Q3, Q6and Q8, to an OFF state.

Note that the duration between times T1and time T2, between time T3and T4, between time T5and T6, etc., (a.k.a., mode C), the duration between time T3and time T4, duration between T5and T6, etc., represents so-called dead times during which each of the switches (Q1-Q8) in the power converter112is deactivated to the OFF state.

As further shown, the control signals105are cyclical. For example, the settings of control signals105for subsequent cycles is the same as those for the cycle between time T0and time T4. More specifically, in one non-limiting example embodiment, the settings of control signals105produced by the controller140between time T4and time T8is the same as settings of control signals105between time T0and time T4, and so on.

In accordance with further example embodiments, the controller140controls the frequency or ON-time duration (i.e. to avoid body diode conduction) of the control signals (period is time between T0and time T4) can be generated at any suitable frequency.

Additionally, as previously mentioned, the controller140controls the pulse duration of the control signals105to be around 48% depending on the dead-time duration, although the control signals105can be generated at any suitable pulse width modulation value.

As further discussed herein, certain embodiments include adjusting the dead time of each of one or more power converters (such as switched-capacitor converter112) operating in parallel.

In one embodiment, the design of the multiple stage power converters (power supply100) is optimized for a communication application with a so-called quarter brick size limitation. In one embodiment, all inductors are realized with planar components for cost and/or size reduction.

In still further example embodiments, an optimization of the power converter111(such as buck converter or other suitable entity) for the specific application of an antenna application includes multiple interleaved phases as previously discussed. The switches in the power converter111can be any components such as 100V GaN devices with 3 mOhm Rdson. The inductors of each phase are planar inductors with 1.9 uH consisting of a PQI core with N49 ferrite core material and a 4 layer PCB board with 105 um copper thickness and 0.4 mm air-gap. The switching frequency is set to 660 kHz.

In accordance with further example embodiments, the switched-capacitor converter131includes two or more interleaved phases as previously discussed. Each switch in the switched-capacitor converter121can be realized with two parallel 40V MOSFETs (switches) with 1.3 mOhm RDSon. The resonant capacitors are 27.7 uF, 50V, X7R capacitors and the ZVS inductor is a planar inductor with 2.5 uH. In one embodiment, the switching frequency of the switched-capacitor converter131is set to 580 kHz (or other suitable setting) with a dead-time of 100 ns or other suitable value. In one embodiment, the resonant inductors such as inductor311are implemented via PCB (Printed Circuit Board) traces or, alternatively, discreet components of other suitable form.

FIG.4further illustrates a magnitude of the resonant currents ICRES1and ICRES2over each respective cycle. Via the inductor311, the controller140supports zero voltage switching of the respective switches Q1-Q8.

FIG.5is an example diagram illustrating zero voltage switching and corresponding inductor current according to embodiments herein.

I. The stored energy in the Coss of all the switches Q1-Q8(such as MOSFETs) is as follows:

EQn=∑i=1nCavg⁢_⁢Qossi·(Vin⁢_⁢max·2)2,
where n=8 switches
II. The stored energy in the Lzvs inductor311is as follows:
EQLzvs=0.5·Lzvs·ILzvs2
EQLzvs>>EQn

In one embodiment, voltage and current conditions for the ZVS inductor311(always constant). Voltage and current is changing a little over load118, due to the load118current depending on voltage drop across the switches Q1-Q8(such as MOSFETs).

FIG.6is an example diagram illustrating operation of the second power converter stage in a first mode (mode A) according to embodiments herein.

For mode A, such as between time T0and time T1, between time T4and T5, etc., switches Q2, Q4, Q5, and Q7are turned OFF; switches Q1, Q3, Q6, and Q8are turned ON. This results in connecting node351of capacitor CRES1to ground and connecting node352of the capacitor CRES1to input voltage node151such as receiving intermediate voltage121. This also results in connecting node361of capacitor CRES2to the output voltage node152and connecting node362of the capacitor CRES2to ground.

FIG.7is an example diagram illustrating operation of the second power converter stage in a second mode (mode B) according to embodiments herein.

For mode B, between time T2and time T3, between time T6and T7, etc., switches Q2, Q4, Q5, and Q7are turned ON; switches Q1, Q3, Q6, and Q8are turned OFF. This results in connecting node361of capacitor CRES2to ground and connecting node362of the capacitor CRES2to the input voltage node151such as receiving intermediate voltage121. This also results in connecting node351of capacitor CRES1to the output voltage node152and connecting node352of the capacitor CRES1to ground.

FIG.8is an example diagram illustrating operation of the second power converter stage in a third mode (mode C or dead time) according to embodiments herein.

In this example embodiment, the switch Q1has a corresponding Coss of PC1; the switch Q2has a corresponding Coss of PC2; the switch Q3has a corresponding Coss of PC3; the switch Q4has a corresponding Coss of PC4; the switch Q5has a corresponding Coss of PC5; the switch Q6has a corresponding Coss of PC6; the switch Q7has corresponding Coss of PC7; and so on.

In one embodiment, parameter Coss (or PCx value such as one of PC1, PC2, PC3, etc.) of a respective switch represents the output capacitance of the respective switch, which in one embodiment is obtained by adding the drain-source capacitance Cds and the gate-drain capacitance Cgs, and is the total capacitance on the output side of a respective switch.

For mode C, between time T1and time T2, between time T3and T4, etc., switches Q2, Q4, Q5, and Q7are turned OFF; switches Q1, Q3, Q6, and Q8are turned OFF. This results in the inductance current provided by the inductor311charging/discharging parasitic capacitances PC1, PC2, PC3, PC4, PC5, PC6, PC7, and PC8(such as Coss) of the switches Q1-Q8, and corresponding zero voltage switching of such switches Q1-Q8. During the dead time, capacitors CRES1and CRES2may be seen as constant voltage sources.

In summary:the power converter111(such as a buck stage) is exposed to just Vin_max voltage stressthe power converter111provides flat efficiency over the full input voltage range.if desired, each of the switches in the power converter111can be 3 m Ohm 100V GaN devices or other suitable switch devicethe power converter112ZSC (Zero voltage switching Switched capacitor converter) shows benefits due to the constant value of intermediate voltage121.there is no indication of resonant frequency change due to different capacitor valuespower converter111can be configured to implement soft startLzvs inductor311is exposed to lower voltage levels, resulting lower constant core lossesresonant inductor can be implemented with parasitic, resulting in the ability to increase switching frequency fswswitches can be implemented as 40V MOSFET class devices or other suitable components

FIG.9is an example block diagram of a computer device for implementing any of the operations as discussed herein according to embodiments herein.

As shown, computer system900(such as implemented by any of one or more resources such as controller140, power converter111, power converter112, etc.) of the present example includes an interconnect911that couples computer readable storage media912such as a non-transitory type of media (or hardware storage media) in which digital information can be stored and retrieved, a processor913(e.g., computer processor hardware such as one or more processor devices), I/O interface914(e.g., to output control signals to the power converter phases, monitor current, etc.), and a communications interface917.

I/O interface914provides connectivity to any suitable circuitry such as power supply100and corresponding power converter phases111,112, etc.

Computer readable storage medium912can be any hardware storage resource or device such as memory, optical storage, hard drive, floppy disk, etc. In one embodiment, the computer readable storage medium912stores instructions and/or data used by the controller application140-1to perform any of the operations as described herein.

Further in this example embodiment, communications interface917enables the computer system900and processor913to communicate over a resource such as network190to retrieve information from remote sources and communicate with other computers.

As shown, computer readable storage media912(such as computer-readable storage hardware) is encoded with controller application140-1(e.g., software, firmware, etc.) executed by processor913. Controller application140-1can be configured to include instructions to implement any of the operations as discussed herein.

During operation of one embodiment, processor913accesses computer readable storage media912via the use of interconnect911in order to launch, run, execute, interpret or otherwise perform the instructions in controller application140-1stored on computer readable storage medium912.

Execution of the controller application140-1produces processing functionality such as controller process140-2in processor913. In other words, the controller process140-2associated with processor913represents one or more aspects of executing controller application140-1within or upon the processor913in the computer system900.

In accordance with different embodiments, note that computer system900can be a micro-controller device, logic, hardware processor, hybrid analog/digital circuitry, etc., configured to control a power supply and perform any of the operations as described herein.

Functionality supported by the different resources will now be discussed via flowchart inFIG.10. Note that the steps in the flowcharts below can be executed in any suitable order.

FIG.10is an example diagram illustrating a method of controlling a power converter according to embodiments herein.

In processing operation1010, a first power converter111converts a received input voltage120into an intermediate voltage121.

In processing operation1020, a transformer-less second power converter112coupled to the first power converter stage111converts the intermediate voltage121into an output voltage123to power a load118.

FIG.11is an example diagram illustrating assembly of a power supply and multiple interconnected power converter phases on a circuit board according to embodiments herein.

In this example embodiment, assembler1140receives a substrate1110and corresponding components of power supply100to fabricate controller140, power converter111, power converter112, etc. The assembler1140affixes (couples) the controller140and other components such as associated with the power converter phases111and112, corresponding switches, etc., to the substrate1110.

Via respective circuit paths1122as described herein, the assembler1140provides connectivity between the controller140, power converter111(a.k.a., first power converter stage), and power converter112(a.k.a., second power converter stage), controller140, etc.

Note that components such as the controller140, power converter111, power converter112, load118, and corresponding components can be affixed or coupled to the substrate1110in any suitable manner. For example, one or more of the components in power supply100can be soldered to the substrate1110, inserted into respective sockets disposed on the substrate1110, etc.

Note further that the substrate1110is optional. Any of one or more circuit paths or connectivity as shown in the drawings and as described herein can be disposed in cables or other suitable medium.

In one nonlimiting example embodiment, the load118is disposed on its own substrate independent of substrate1110; the substrate of the load118is directly or indirectly connected to the substrate1110via connectivity1123such as one or more of wires, cables, links, etc. The controller140or any portion of the power supply100and corresponding power converter phases can be disposed on a standalone smaller board plugged into a socket of the substrate1110as well.

Via one or more circuit paths1123(such as one or more traces, cables, connectors, wires, conductors, electrically conductive paths, etc.), the assembler1140couples the power supply100and corresponding power converter phases to the load118. In one embodiment, the circuit path1123conveys the output voltage123and corresponding current generated by the power converter phases to the load118.

Accordingly, embodiments herein include a system comprising: a substrate1110(such as a circuit board, standalone board, mother board, standalone board destined to be coupled to a mother board, host, etc.); a power supply system100including corresponding components as described herein; and a load118(such as a motor, winding, etc.).

Note that the load118can be any suitable circuit or hardware such as one or more CPUs (Central Processing Units), GPUs (Graphics Processing Unit) and ASICs (Application Specific Integrated Circuits such those including one or more Artificial Intelligence Accelerators), which can be located on the substrate1110or disposed at a remote location.

Note again that techniques herein are well suited for use in circuit applications such as those that that generate an output voltage to power a load. However, it should be noted that embodiments herein are not limited to use in such applications and that the techniques discussed herein are well suited for other applications as well.