Methods and systems for performing test and calibration of integrated sensors

Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.

BACKGROUND

The present disclosure relates generally to chip manufacturing, and more particularly to methods, systems and computer program products for performing test and calibration of integrated sensors on a processor chip.

The rapid densification of very-large-scale integration (VLSI) devices, incorporating complex functions operating at extreme circuit performance, has driven the designs towards integrating many diverse functional macros or cores within these large chips. These macros range from autonomous processor cores with large cache arrays occupying relatively large portions of the chip's real estate, to a multitude of small arrays used as register stacks, trace arrays, content addressable memories, phase locked loops (PLLs), and many other special purpose logic functions. In conjunction with these higher integration densities and larger devices, current system architecture is shifting, in many applications, toward massively parallel processing utilizing multiple copies of these integrated cores. The number of processing cores can range from dual-cores to hundreds of cores per chip in the near future and to thousands of core arrays at system level. The independent logic units may include register stacks, trace arrays, content addressable memories, PLLs, as well as various integrated sensors (or on-chip sensors) such as Critical Path Monitors (CPM) and Digital Temperature Sensors (DTS) used for real time monitoring and environmental optimization.

The problem addressed by this disclosure is encountered while utilizing on-chip sensors to optimize the power and performance of the device. Specifically, the problem is to accurately and rapidly test and calibrate the various sensors during test.

Therefore, heretofore unaddressed needs still exist in the art to address the aforementioned deficiencies and inadequacies.

SUMMARY

In an embodiment of the present invention, a method for performing test and calibration of one or more integrated sensors on a processor chip may include: initializing, by a tester program, an on-chip service engine of the processor chip for performing test and calibration of the integrated sensors, performing, by the on-chip service engine, test and calibration of the integrated sensors, and completing the test and calibration of the of the integrated sensors. The method may also include: loading and decoding the tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor, loading sensor test and calibration patterns and parameters, and sensor test code for the selected integrated sensor, and executing the sensor test code to test and calibrate the integrated sensor selected according to the test and calibration patterns and parameters loaded, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of the test and calibration of the integrated sensors to another predetermined location of the on-chip service engine memory, when every integrated sensor is tested and calibrated.

In another embodiment of the present invention, a computer system for performing test and calibration of one or more integrated sensors on a processor chip may include a processor, and a memory storing a tester program for the computer system. When the tester program is executed at the processor, the tester program may cause the computer system to perform: initializing, by the tester program, an on-chip service engine of the processor chip for performing test and calibration of one or more integrated sensors on the processor chip, performing, by the on-chip service engine, test and calibration of the integrated sensors, and completing the test and calibration of the of the integrated sensors. The tester program may cause the computer system to perform: loading and decoding the tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor, loading sensor test and calibration patterns and parameters, and sensor test code for the selected integrated sensor, and executing the sensor test code to test and calibrate the integrated sensor selected according to the test and calibration patterns and parameters loaded, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of the test and calibration of the integrated sensors to another predetermined location of the on-chip service engine memory, when every integrated sensor is tested and calibrated.

In yet another embodiment of the present invention, a non-transitory computer readable storage medium may store a tester program. When the tester program is executed by a processor of a computer system, the tester program causes the computer system to perform: initializing, by the tester program, an on-chip service engine of a processor chip for performing test and calibration of one or more integrated sensors on the processor chip, performing, by the on-chip service engine, test and calibration of the integrated sensors, and completing the test and calibration of the of the integrated sensors. The tester program may cause the computer system to perform: loading and decoding the tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor, loading sensor test and calibration patterns and parameters, and sensor test code for the selected integrated sensor, and executing the sensor test code to test and calibrate the integrated sensor selected according to the test and calibration patterns and parameters loaded, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of the test and calibration of the integrated sensors to another predetermined location of the on-chip service engine memory, when every integrated sensor is tested and calibrated.

DETAILED DESCRIPTION

The terms used in this specification generally have their ordinary meanings in the art, within the context of the disclosure, and in the specific context where each term is used. Certain terms that are used to describe the disclosure are discussed below, or elsewhere in the specification, to provide additional guidance to the practitioner regarding the description of the disclosure. It will be appreciated that same thing can be said in more than one way. Consequently, alternative language and synonyms may be used for any one or more of the terms discussed herein, nor is any special significance to be placed upon whether or not a term is elaborated or discussed herein. The use of examples anywhere in this specification including examples of any terms discussed herein is illustrative only, and in no way limits the scope and meaning of the disclosure or of any exemplified term. Likewise, the disclosure is not limited to various embodiments given in this specification.

As used herein, “plurality” means two or more. The terms “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to.

The term computer program, as used above, may include software, firmware, and/or microcode, and may refer to programs, routines, functions, classes, and/or objects. The term shared, as used above, means that some or all code from multiple modules may be executed using a single (shared) processor.

Referring toFIG. 1, an embodiment of a computer system100for performing test and calibration of integrated sensors in a multi-core test environment and implementing the teachings is shown. In this embodiment, the computer system100has one or more central processing units (processors)101a,101b,101c, etc. (collectively or generically referred to as processor(s)101). In one embodiment, each processor101may include a reduced instruction set computer (RISC) microprocessor. Processors101are coupled to system memory114and various other components via a system bus113. Read only memory (ROM)102is coupled to the system bus113and may include a basic input/output system (BIOS), which controls certain basic functions of the computer system100.

Thus, as configured inFIG. 1, the computer system100includes processing capability in the form of processors101, storage capability including system memory114and mass storage104, input means such as keyboard109and mouse110, and output capability including speaker111and display115. In one embodiment, a portion of system memory114and mass storage104collectively store an operating system to coordinate the functions of the various components shown inFIG. 1. In certain embodiments, the network116may include symmetric multiprocessing (SMP) bus, a Peripheral Component Interconnect (PCI) bus, local area network (LAN), wide area network (WAN), telecommunication network, wireless communication network, and the Internet.

In certain embodiments, the computer system100may be connected to a test and calibration device where a processor chip is been tested (not shown inFIG. 1).

Referring now toFIG. 2, a structure view200of a chip and a tester program for performing test and calibration of integrated sensors in a multi-core test environment is shown according to certain exemplary embodiments of the present invention.

In certain embodiments, a test and calibration device (not shown inFIG. 2) may include a tester program210, a processor chip220to be tested and calibrated by the test and calibration device, and a storage device230storing various sensor test codes, and sensor test and calibration patterns. The processor chip220may be mounted on the test and calibration for testing and calibration. The processor chip220may include an on-chip service engine222, an on-chip service engine memory224, M cores228and N integrated sensors226, where M and N are positive integers. The on-chip service engine222may be an on-chip highly optimized general purpose micro-controller. The on-chip service engine222may have its own instruction set architecture (ISA), and acts as a bridge between an external tester such as the computer system100and its intra-chip functional logic units such as various cores and integrated sensors. The on-chip service engine222is capable of performing any chip operations including test and calibration that the external tester program210wants to perform.

In certain embodiments, the on-chip service engine memory224may be a volatile memory, such as the random-access memory (RAM), for storing the data and information during the operation of test and calibration. The on-chip service engine memory224may also include a non-volatile data storage media for the tester program210and other applications. Examples of the on-chip service engine memory224may include flash memory, memory cards, USB drives, hard drives, floppy disks, optical drives, or any other types of data storage devices.

In certain embodiments, the storage device230may be a volatile memory of the computer system100, such as the random-access memory (RAM), for storing the data and information during the operation of test and calibration. The storage device230may also include a non-volatile data storage media for storing various test codes or applications for testing and calibrating one or more integrated sensors. Examples of the storage device230may include flash memory, memory cards, USB drives, hard drives, floppy disks, optical drives, or any other types of data storage devices. The storage device230may be in communication with the test and calibration device and the processor chip220through direct connection or a network.

As shown inFIG. 2, the processor chip220may include various sensors226such as a first integrated sensor226-1, a second integrated sensor226-2, . . . , and N-th integrated sensor226-N, and various cores228such as a first core228-1, a second core228-2, . . . , and M-th core228-M. In certain embodiments, the integrated sensors may include: temperature sensors, voltage sensors, current sensors, process sensors, pressure sensors, microfluidics sensors, passive infrared (PIR) sensors, gas sensors, motion sensors, light sensors, acceleration sensors, displacement sensors, magnetic field sensors, critical path monitors (CPM) sensors, digital temperature sensors (DTS), and any sensors that can be integrated on the processor chip220. The cores280may include certain number of good and fully functional cores. In certain embodiments, the cores280may even include certain number of “bad” or “not fully functional” cores.

In certain embodiments, a CPM is a sensor which is built by a series of delay elements and wires that simulate a timing critical path and is used for voltage droop sensing, timing margin detection, dynamic voltage and frequency scaling (DVFS) and other applications that are related to dynamic noise mitigation of processor chips. In utilizing integrated sensors (or on-chip sensors) to optimize the power and performance of a device, it can be challenging to accurately and quickly calibrate the various sensors during test. A serial calibration process can result in significant test time and associated costs. In addition, because the test pattern is usually implemented for specific test equipment, the test method is not easily ported to another test sector.

In certain embodiments, the hard disk103may store the tester program210for the computer system100for performing test and calibration of integrated sensors226. In certain embodiments, when the tester program210is executed at the processor101, the computer system100may perform: initializing, by the tester program210, the on-chip service engine222of the processor chip220for performing test and calibration of one or more integrated sensors226on the processor chip220, performing, by the on-chip service engine222, test and calibration of the integrated sensors226, and completing the test and calibration of the of the integrated sensors226. The tester program may cause the computer system to perform: loading and decoding the tester program210into the on-chip service engine memory224, testing and calibrating each integrated sensor226-i, i=1, 2, . . . , and N, where N is a positive integer. The testing and calibrating may include: selecting an integrated sensor, loading one or more sensor test and calibration patterns for the selected integrated sensor, one or more sensor test and calibration parameters for the selected integrated sensor, and sensor test code for the selected integrated sensor from the storage device230, executing the sensor test code to test and calibrate the integrated sensor selected according to the test and calibration patterns and parameters loaded, and writing results of the test and calibration to a predetermined location of the on-chip service engine memory224.

In certain embodiments, when every integrated sensor226-iis tested and calibrated, the on-chip service engine222may write a return code of the test and calibration of the integrated sensors to another predetermined location of the on-chip service engine memory224, indicating the completion of the testing and calibrating of the integrated sensors. The tester program, which has been polling for completion, decodes the return-code of the on-chip service engine222and then continues with its next steps.

In certain embodiments, a test and calibration of a CPM sensor is described here as an example. The processor chip222may be a multi-core integrated circuit for a microprocessor or processing unit. The on-chip service engine222may be a hardware device implemented as a micro-controller. The on-chip service engine222executes code that tests and calibrates a critical path monitor (CPM). After the tester program210initializes the on-chip service engine222, it loads one or more sensor test and calibration patterns for the CPM, and sensor test code for the CPM from the storage device230to the on-chip service engine memory224. The tester program210also may load one or more sensor test and calibration parameters for the CPM including a steady state workload to all of the processor cores228-j, where j=1, 2, . . . , M, and M is a positive integer. The tester program210may evaluate the processor cores to determine if the temperature has reached a steady state. This is a pre-requisite for the CPM calibration, which requires steady state runtime conditions.

In certain embodiments, the tester program210may initiate test and calibration of the integrated sensors226-i, i=1, 2, . . . , N, where N is a positive integer. The tester program210may initialize the on-chip service engine222of the processor chip222for performing test and calibration of the integrated sensors. The on-chip service engine222may load and decode the tester program into the on-chip service engine memory224, and may load steady state workload to the cores228-1,228-2, . . . , and228-M. The on-chip service engine222may go through each one of the one or more integrated sensors, in either sequential order or a predetermined order, test and calibrate these integrated sensors. For each of the integrated sensors, the on-chip service engine222may select one of the integrated sensors for testing and calibrating, load sensor test and calibration patterns, and sensor test and calibration parameters, and sensor test code from the storage device230for the selected integrated sensor into the on-chip service engine memory224, execute the sensor test code for the selected integrated sensors to test and calibrate the selected integrated sensor according to the test and calibration patterns and the test and calibration parameters loaded, and write results of the test and calibration to a predetermined location of the on-chip service engine memory224.

In one embodiment where a CPM is selected, the sensor test and calibration parameters may include sensor path delay parameter to the on-chip service engine222. Then the on-chip service engine222may check to see if the CPM has reached a target value. Path delay refers to the tunable delay that one can add/remove from a selected CPM path. If the target value is not reached, the on-chip service engine222may determine if the sample space has been exhausted for the CPM. The path delay is a 6-bit value with a range from 0 to 63. When all the values are swept from 0 to 63, it means the sample space has exhausted. If the sample space has not been exhausted, the on-chip service engine222may iterate through the path delay sample space until the sample space has been exhausted.

When the sample space for the CPM has been exhausted, the CPM is marked accordingly. For example, the sensor may be marked as ‘failed’ or ‘unsuccessful.’ The on-chip service engine222may determine whether current sensor under test is the last sensor. If the current sensor under test is not the last sensor, another sensor is selected, tested and calibrated. When every integrated sensor is tested and calibrated, the on-chip service engine222may write a return code of the test and calibration of the integrated sensors to another predetermined location of the on-chip service engine memory224indicating the testing and calibrating is completed.

During the testing performed above, the tester program210is in a wait loop and checks for the on-chip service engine's222return code. When the tester program210receives the return code (either success or fail), it will then proceed with test execution on its next tasks.

Thus, the exemplary processes include the ability for the on-chip service engine222to interact with the tester program210to perform any type of on-chip integrated sensor test and calibration. The sensor test code may be sensor specific, and may be changed to suit the algorithm for any type of integrated sensors.

Referring now toFIG. 3, a flow chart of an exemplary method300performing test and calibration of integrated sensors of the processor chip is shown according to certain embodiments of the present invention.

At block302, a tester program210may be provided to the computer system100, and an operator may issue a test and calibration command to start a test and calibration of a processor chip220at the computer system100. The processor chip220is mounted on a test and calibration device (not shown inFIGS. 1 and 2).

At block304, the tester program210may initialize an on-chip service engine222to start the test and calibration of integrated sensors on the processor chip220. In certain embodiments, when the tester program210is executed at the processor101of the computer system100, the computer system100may initialize the on-chip service engine222of the processor chip220for performing test and calibration of one or more integrated sensors226on the processor chip220and trigger execution of the test and calibration of integrated sensors on the processor chip220.

At block306, once the test and calibration of integrated sensors on the processor chip220is triggered and started, the on-chip service engine222may performing the test and calibration of the integrated sensors. In certain embodiments, the performing the test and calibration of the integrated sensors may include: loading and decoding the tester program210into the on-chip service engine memory224, and testing and calibrating each integrated sensor226-i, i=1, 2, . . . , and N, where N is a positive integer. The testing and calibrating may include: selecting an integrated sensor, loading one or more sensor test and calibration patterns for the selected integrated sensor, one or more sensor test and calibration parameters for the selected integrated sensor, and sensor test code for the selected integrated sensor from the storage device230, executing the sensor test code to test and calibrate the integrated sensor selected according to the test and calibration patterns and parameters loaded, and writing results of the test and calibration of the selected integrated sensor to a predetermined location of the on-chip service engine memory224. In one embodiment, the sensor test code may be generic. In another embodiment, the sensor test code may be sensor specific.

At block308, when every integrated sensor226-iis tested and calibrated, the on-chip service engine222may write a return code of the test and calibration of the integrated sensors to another predetermined location of the on-chip service engine memory224, indicating the completion of the testing and calibrating of the integrated sensors of the processor chip220. The tester program210may be in a wait loop and constantly check for the return code from the on-chip service engine222. Once the tester program210detects the return code, and decodes the return-code of the on-chip service engine222, the test and calibration of integrated sensors of the processor chip220is completed. The tester program210may continue with its next testing tasks.