Differential controlled phase locked loop circuit

Provided is a PLL circuit driven with a differential controlled voltage. The PLL circuit includes a VCO. The VCO outputs an oscillation signal in response to a difference between first and second control voltages. The PLL circuit includes a first loop for generating the first control voltage, and a second loop for generating the second control voltage having a phase opposite to the first control voltage. Intermediate generated signals of the first loop and intermediate generated signals of the second loop which respectively correspond to the intermediate generated signals of the first loop have opposed phases.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application No. 10-2010-0125022, filed on Dec. 8, 2010, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The present invention disclosed herein relates to a Phase Locked Loop (PLL) circuit, and more particularly, to a PLL circuit which is driven with a differential controlled voltage.

PLL circuits which are used in wired/wireless communication, signal processing and data processing circuits are frequency feedback circuits that generate a signal having an arbitrary frequency in synchronization with a signal having a reference frequency which is inputted from the outside. The PLL circuits are configured for the frequency of an output signal to be controlled according to a phase difference between a reference signal and an output signal. In the PLL circuits, noise characteristics such as common mode noise and spur noise largely affect performances of analog and digital signal processing circuits. Therefore, research is actively being conducted on the decrease in noises of the PLL circuits.

PLL circuits that operate in a differential control scheme are being used for removing common mode noise. In typical differential controlled PLL circuits, however, spur noises occur due to the up-down current error of a charge pump and ripples that are generated in the control voltages of a Voltage Controlled Oscillator (VCO).

SUMMARY OF THE INVENTION

The present invention provides a Phase Locked Loop (PLL) circuit which is differentially controlled by a positive loop and a negative loop, and removes ripples which are generated in positive and negative control voltages inputted to a Voltage Controlled Oscillator (VCO).

Embodiments of the present invention provide a Phase Locked Loop (PLL) circuit including: a VCO outputting an oscillation signal in response to a difference between first and second control voltages, wherein: the PLL circuit includes a first loop for generating the first control voltage and a second loop for generating the second control voltage having a phase opposite to the first control voltage, and intermediate generated signals of the first loop and intermediate generated signals of the second loop which respectively correspond to the intermediate generated signals of the first loop have opposed phases.

In some embodiments, the first loop may include a first phase frequency detector detecting phase and frequency differences between a reference signal and a division signal for the oscillation signal, and the second loop may include a second phase frequency detector detecting phase and frequency differences between an inverted reference signal and an inverted division signal.

In other embodiments, the first loop may further include a first charge pump controlling a first output current which corresponds to the first control voltage according to the detected result of the first phase frequency detector, and the second loop may further include a second charge pump controlling a second output current which corresponds to the second control voltage according to the detected result of the second phase frequency detector.

In other embodiments of the present invention, a Phase Locked Loop (PLL) circuit includes: a first phase frequency detector outputting a first differential control signal in response to a reference signal and a division signal for an oscillation signal; a second phase frequency detector outputting a second differential control signal in response to an inverted reference signal and an inverted division signal; a first charge pump outputting a first current which is controlled according to the first differential control signal; a second charge pump outputting a second current which is controlled according to the second differential control signal; a first loop filter outputting a first control voltage which corresponds to the first current; a second loop filter outputting a second control voltage which corresponds to the second current; and a VCO outputting the oscillation signal in response to a difference between the first and second control voltages.

In some embodiments, the first and second differential control signals may have opposed phases.

In other embodiments, the first and second currents may have opposed phases.

In still other embodiments, the first and second control voltages may have opposed phases.

In even other embodiments, the PLL circuit may further include a delay circuit delaying the reference signal and the division signal by a half cycle to generate the inverted reference signal and the inverted division signal, respectively.

In yet other embodiments, the PLL circuit may further include a first switch selectively connecting the first charge pump and the first loop filter in response to a first switch control signal; and a second switch selectively connecting the second charge pump and the second loop filter in response to a second switch control signal.

In further embodiments, the PLL circuit may further include a common mode feedback circuit feeding back a Direct Current (DC) voltage to the first and second charge pumps, wherein the DC voltage is outputted in response to change of the first and second currents.

In still other embodiments of the present invention, a Phase Locked Loop (PLL) circuit includes: a first phase frequency detector outputting a first differential control signal in response to a reference signal and a division signal for an oscillation signal; a second phase frequency detector outputting a second differential control signal in response to an inverted reference signal and an inverted division signal; first to third charge pumps outputting first to third currents which are controlled according to the first differential control signal, respectively; a second charge pump outputting a fourth current which is controlled according to the second differential control signal; a first loop filter outputting a first control voltage which corresponds to sum of the first and second currents; a second loop filter outputting a second control voltage which corresponds to sum of the third and fourth currents; and a VCO outputting the oscillation signal in response to a difference between the first and second control voltages.

In some embodiments, the second differential control signal may have a phase which has been further delayed by a half cycle of the reference signal than the first differential control signal.

In other embodiments, the fourth current may have a phase which has been further delayed by a half cycle of the reference signal than the first to third currents.

In still other embodiments, the first control voltage may be changed at every cycle of the reference signal, and the second control voltage may be changed at every half cycle of the reference signal.

In even other embodiments, the PLL circuit may further include a common mode feedback circuit maintaining constant sum of the first to fourth currents.

In yet other embodiments, the PLL circuit may further include a switch circuit selectively connecting the first and second charge pumps to the first loop filter, and selectively connecting the third and fourth charge pumps to the second loop filter, according to an external switch control signal.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be constructed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, a portion irrelevant to a description of the present invention will be omitted for clarity. Like reference numerals refer to like elements throughout.

In this disclosure below, when one part (or element, device, etc.) is referred to as being ‘connected’ to another part (or element, device, etc.), it should be understood that the former can be ‘directly connected’ to the latter, or ‘electrically connected’ to the latter via an intervening part (or element, device, etc.). Furthermore, when it is described that one comprises (or includes or has) some elements, it should be understood that it may comprise (or include or has) only those elements, or it may comprise (or include or have) other elements as well as those elements if there is no specific limitation.

FIG. 1is a block diagram schematically illustrating a Phase Locked Loop (PLL) circuit100according to a first embodiment of the present invention.

Referring toFIG. 1, the PLL circuit100includes Phase Frequency Detectors (PFDs)102and104, Charge Pumps (CPs)106and108, Loop Filters (LFs)110and112, a Voltage Controlled Oscillator (VCO)114, a divider116, a delay circuit118, a common mode feedback circuit CMFC, and switches SW1and SW2.

The PLL circuit100is configured in a dual feedback loop type for differential control. The first phase frequency detector102, the first charge pump106, the first switch SW1, the first loop filter110, the VCO114and the divider116configure a first loop. The second phase frequency detector104, the second charge pump108, the second switch SW2, the second loop filter112, the VCO114, the divider116and the delay circuit118configure a second loop.

AlthoughFIG. 1illustrates that the second loop includes the delay circuit118, the second loop is not limited thereto. One of the first and second loops may include the delay circuit118.

The first phase frequency detector102receives a signal having a reference frequency (FREF, hereinafter referred to as a reference signal) and a feedback signal having a divided frequency (FDIV, hereinafter referred to as a division signal). Herein, the reference signal FREF may be provided from an external system and a crystal oscillator (not shown).

The first phase frequency detector102detects phase and frequency differences between the reference signal FREF and the division signal FDIV. Furthermore, the first phase frequency detector102outputs a first up signal UP1and a first down signal DN1as a first differential control signal according to the phase and frequency differences between the reference signal FREF and the division signal FDIV. For example, the first phase frequency detector102outputs the first up signal UP1when the frequency of the division signal FDIV is lower than that of the reference signal FREF, and outputs the first down signal DN1when the frequency of the division signal FDIV is higher than that of the reference signal FREF.

The second phase frequency detector104receives an inverted reference signal FREF/ and an inverted division signal FDIV/. Herein, the inverted reference signal FREF/ may be obtained by delaying the reference signal FREF by a half cycle, and the inverted division signal FDIV/ may be obtained by delaying the division signal FDIV by a half cycle.

The second phase frequency detector104detects phase and frequency differences between the inverted reference signal FREF/ and the inverted division signal FDIV/. The second phase frequency detector104outputs a second up signal UP2and a second down signal DN2as a second differential control signal according to the phase and frequency differences between the inverted reference signal FREF/and the inverted division signal FDIV/. For example, the second phase frequency detector104outputs the second up signal UP2when the frequency of the inverted division signal FDIV/ is lower than that of the inverted reference signal FREF/, and outputs the second down signal DN2when the frequency of the inverted division signal FDIV/ is higher than that of the inverted reference signal FREF/.

The first charge pump106controls a first output current CP1in response to the first up signal UP1and the first down signal DN1. For example, the first charge pump130performs a current sourcing operation in order to increase the first output current CP1in response to the first up signal UP1, and performs a current sinking operation in order to decrease the first output current CP1in response to the first down signal DN1.

The second charge pump108controls a second output current CP2in response to the second up signal UP2and the second down signal DN2. For example, the second charge pump108performs a current sourcing operation in order to increase the second output current CP2in response to the second up signal UP2, and performs a current sinking operation in order to decrease the second output current CP2in response to the second down signal DN2.

Herein, the first and second charge pumps106and108generate the first and second output currents CP1and CP2showing complementary characteristic.

Each of the loop filters110and112may be configured as a low pass filter that includes at least one resistor and capacitor. The first loop filter110filters high frequency noise of the first output current CP1. Furthermore, the loop filter110outputs a first control voltage VCP corresponding to the filtered first output current CP1. The second loop filter112filters high frequency noise of the second output current CP2. Furthermore, the second loop filter112outputs a second control voltage VCM corresponding to the filtered second output current CP2.

The VCO114outputs an oscillation signal FOUT having a frequency which corresponds to the first and second control voltages VCP and VCM. This denotes that the VCO114is implemented in a differential type.

The divider116generates the division signal FDIV having a frequency that is obtained by lowering the frequency of the oscillation signal FOUT outputted from the VCO114to a predetermined dividing ratio.

The delay circuit118delays the reference signal FREF by a half cycle to generate the inverted reference signal FREF/, and delays the division signal FDIV by a half cycle to generate the inverted division signal FDIV/. AlthoughFIG. 1illustrates that the delay circuit118includes inverters for generating the inverted reference signal FREF/ and the inverted division signal FDIV/, the delay circuit118is not limited thereto. The delay circuit118may be variously configured for inverting and outputting an input signal.

In order to maintain the constant sum of the first and second output currents CP1and CP2, the common mode feedback circuit CMFB feeds back a Direct Current (DC) voltage, which is outputted in response to the change of the first and second output currents CP1and CP2, to the first and second charge pumps106and108. Furthermore, as the constant sum of the first and second output currents CP1and CP2is maintained by the common mode feedback circuit CMFB, the sum of the first and second control voltages VCP and VCM respectively corresponding to the first and second output currents CP1and CP2is also maintained.

The first switch SW1selectively connects the first charge pump106and the first loop filter110in response to a first switch control signal SC1provided from outside. The second switch SW2selectively connects the second charge pump108and the second loop filter112in response to a second switch control signal SC2provided from outside. Therefore, operations of the first and second loops may be selected by the first and second switches SW1and SW2.

In typical differential controlled PLL circuits, the frequency of an oscillation signal FOUT is locked, and then ripples with opposed phases may be generated in two control voltages inputted to a VCO, respectively. Since a differential controlled voltage corresponds to a difference (VCP−VCM) between the two control voltages, the ripples with opposed phases are summed and appear in the differential controlled voltage (VCP−VCM). Therefore, spur noise of the oscillation signal FOUT that is generated in response to the differential controlled voltage (VCP−VCM) increases. However, suppression of the spur noise is required for guaranteeing the stable output signal of the PLL circuit.

As described above, in the PLL circuit100according to the first embodiment of the present invention, the first and second control voltages VCP and VCM inputted to the differential VCO114have the opposed phases.

To provide more detailed description, the PLL circuit100includes the first loop for generating the first control voltage VCP, and the second loop for generating the second control voltage VCM. The first loop includes the first phase frequency detector102, the first charge pump106, the first loop filter110, etc. The second loop includes the second phase frequency detector104, the second charge pump108, the second loop filter112, etc.

One of the first and second loops includes the delay circuit118for generating phase differences between signals inputted to the first phase frequency detector102and the signals inputted to the second phase frequency detector104. For example, when the second loop includes the delay circuit118, the reference signal FREF and the division signal FDIV are inputted to the first phase frequency detector102, and the inverted reference signal FREF/ and the inverted division signal FDIV/ are inputted to the second phase frequency detector104. Herein, the inverted reference signal FREF/ is generated by delaying the reference signal FREF by a half cycle, and the inverted division signal FDIV/ is generated by delaying the division signal FDIV by a half cycle.

Such phase delay also appears in the signals UP2and DN2outputted by the second phase frequency detector104, the current CP2outputted by the second charge pump108and the control voltage VCP outputted by the second loop filter112. This denotes that the first and second control voltages VCP and VCM have the opposed phases.

According to the first embodiment of the present invention, since the first and second control voltages VCP and VCM have the opposed phases, ripples that are generated in the first and second control voltages VCP and VCM have the same phase. Therefore, the ripples of the first and second control voltages VCP and VCM are offset, only the DC components of the first and second control voltages VCP and VCM appear in the differential control voltage (VCP−VCM). As a result, the ripple of the differential control voltage (VCP−VCM) decreases, and thus the spur noise of the oscillation signal FOUT is suppressed.

FIG. 2is a diagram exemplarily showing operation characteristics of the control voltages VCP and VCM of the PLL circuit100inFIG. 1.

Referring toFIG. 2, the control voltages VCP and VCM are changed in response to the reference signal FREF that is changed at every certain cycle T.

In the PLL circuit100according to the first embodiment of the present invention, due to a dual loop configuration that generates a phase difference between signals corresponding to each other, the second control voltage VCM is delayed by a half cycle T/2 of the reference signal FREF compared to the first control voltage VCP and then changed. That is, the first and second control voltages VCP and VCM have the opposed phases.

FIG. 3is a block diagram schematically illustrating a PLL circuit200according to a second embodiment of the present invention.

Referring toFIG. 3, the PLL circuit200includes Phase Frequency Detectors (PFDs)202and204, Charge Pumps (CPs)206to209, Loop Filters (LFs)210and212, a Voltage Controlled Oscillator (VCO)214, a divider216, a delay circuit218, a common mode feedback circuit CMFC, and switches SW1to SW4. Hereinafter, repetitive description on the same elements as those ofFIG. 1will be omitted.

The first phase frequency detector202detects phase and frequency differences between a reference signal FREF and a division signal FDIV.

Furthermore, the first phase frequency detector202outputs a first up signal UP1and a first down signal DN1according to the phase and frequency differences between the reference signal FREF and the division signal FDIV.

The second phase frequency detector204detects phase and frequency differences between an inverted reference signal FREF/ and an inverted division signal FDIV/. The second phase frequency detector204outputs a second up signal UP2and a second down signal DN2according to the phase and frequency differences between the inverted reference signal FREF/ and the inverted division signal FDIV/.

The first to third charge pumps206to208control first to third output currents CP1to CP3in response to the first up signal UP1and the first down signal DN1, respectively. The fourth charge pump209controls a fourth output current CP4in response to the second up signal UP2and the second down signal DN2. The fourth output current CP4has a phase that has been further delayed by a half cycle of the reference signal FREF than the first to third output currents CP1to CP3.

Herein, the first and third charge pumps206and208generate the first and third output currents CP1and CP3showing complementary characteristic, respectively. Also, the second and fourth charge pump207and209generate the second and fourth output currents CP2and CP4showing complementary characteristic, respectively.

The first loop filter210outputs the first control voltage VCP corresponding to the sum of the filtered first and second output currents CP1and CP2. The second loop filter212outputs the second control voltage VCM corresponding to the sum of the filtered third and fourth output currents CP3and CP4.

Since the first control voltage VCP corresponds to the sum of the first and second output currents CP1and CP2having the same phase, it is changed at every cycle of the reference signal FREF. Since the second control voltage VCM corresponds to the sum of the third and fourth output currents CP3and CP4with opposed phases, it is changed at every half cycle of the reference signal FREF. That is, the first and second control voltages VCP and VCM have different change cycles. This will be described below in more detail with reference toFIG. 4.

In order to maintain the constant sum of the first to fourth output currents CP1to CP4, the common mode feedback circuit CMFB feeds back a DC voltage, which is outputted in response to the change of the first to fourth output currents CP1to CP4, to the first to fourth charge pumps206to209. Furthermore, as the constant sum of the first to fourth output currents CP1to CP4is maintained by the common mode feedback circuit CMFB, the constant sum of the first and second control voltages VCP and VCM is maintained, wherein the first control voltage VCP corresponds to the sum of the first and second output currents CP1and CP2and the second control voltage VCM corresponds to the sum of third and fourth output currents CP3and CP4.

The first switch SW1selectively connects the first charge pump206and the first loop filter210in response to a first switch control signal SC1provided from outside. The second switch SW2selectively connects the second charge pump207and the first loop filter210in response to a second switch control signal SC2provided from outside. The third switch SW3selectively connects the third charge pump208and the second loop filter212in response to a third switch control signal SC3provided from outside. The fourth switch SW4selectively connects the fourth charge pump209and the second loop filter212in response to a fourth switch control signal SC4provided from outside. Therefore, the first to fourth output currents CP1to CP4may be selectively transferred to a corresponding loop filter among the loop filters210and212by the first to fourth switches SW1to SW4.

As described above, the PLL circuit200according to the second embodiment of the present invention, the change cycles of the first and second control voltages VCP and VCM inputted to the differential VCO214differ.

According to the second embodiment of the present invention, since the change cycles of the first and second control voltages VCP and VCM differ, reference frequency component of the oscillation signal FOUT decreases. Therefore, spur noise of the oscillation signal FOUT is suppressed.

FIG. 4is a diagram exemplarily showing operation characteristics of the control voltages VCP and VCM of the PLL circuit200inFIG. 3.

InFIG. 4, it is illustrated that the control voltages VCP and VCM are changed in response to the reference signal FREF which is changed at every certain cycle T.

Referring toFIGS. 3 and 4, in the PLL circuit200according to the second embodiment of the present invention, the first and second output currents CP1and CP2having the same phase overlap and thus the first control voltage VCP is generated. The third and fourth output currents CP3and CP4having opposed phases, i.e., a phase difference equal to a half cycle T/2 of the reference signal FREF overlap and thus the second control voltage VCM is generated. Therefore, the first control voltage VCP is changed at every cycle T of the reference signal FREF, and the second control voltage VCM is changed at every half cycle T/2 of the reference signal FREF.

FIG. 5is a block diagram schematically illustrating a modification example300of the PLL circuit according to the second embodiment of the present invention.

Referring toFIG. 5, a PLL circuit300includes Phase Frequency Detectors (PFDs)302and304, Charge Pumps (CPs)306to309, Loop Filters (LFs)310and312, a Voltage Controlled Oscillator (VCO)314, a divider316, a delay circuit318, a common mode feedback circuit CMFC, and switches SW1to SW4. Hereinafter, repetitive description on the same elements as those of the PLL circuits100and200according to the first and second embodiments of the present invention will be omitted.

The first phase frequency detector302detects phase and frequency differences between a reference signal FREF and a division signal FDIV. Furthermore, the first phase frequency detector302outputs a first up signal UP1and a first down signal DN1according to the phase and frequency differences between the reference signal FREF and the division signal FDIV.

The second phase frequency detector304detects phase and frequency differences between an inverted reference signal FREF/ and an inverted division signal FDIV/. The second phase frequency detector304outputs a second up signal UP2and a second down signal DN2according to the phase and frequency differences between the inverted reference signal FREF/ and the inverted division signal FDIV/.

The first charge pump306controls a first output current CP1in response to the first up signal UP1and the first down signal. The second to fourth charge pumps307to309control second to fourth output currents CP2to CP4in response to the second up signal UP2and the second down signal DN2, respectively. Herein, the first output current CP4has a phase that has been further delayed by a half cycle of the reference signal FREF than the second to fourth output currents CP2to CP4.

Since the first control voltage VCP corresponds to the sum of the first and second output currents CP1and CP2with opposed phases, it is changed at every half cycle of the reference signal FREF. Since the second control voltage VCM corresponds to the sum of the third and fourth output currents CP3and CP4having the same phase, it is changed at every cycle of the reference signal FREF. That is, the first and second control voltages VCP and VCM have different change cycles.

Unlike the change cycle of the second control voltage VCM being controlled in the PLL circuit200according to the second embodiment of the present invention, the change cycle of the first control voltage VCP is controlled in the PLL circuit300according to the modification example of the present invention. This will be described below in more detail with reference toFIG. 6.

FIG. 6is a diagram exemplarily showing operation characteristics of the control voltages VCP and VCM of the PLL circuit300inFIG. 5.

InFIG. 6, it is illustrated that the control voltages VCP and VCM are changed in response to the reference signal FREF which is changed at every certain cycle T.

Referring toFIGS. 5 and 6, in the PLL circuit300according to the modification example of the present invention, the first and second output currents CP1and CP2having opposed phases, i.e., a phase difference equal to a half cycle T/2 of the reference signal FREF overlap and thus the first control voltage VCP is generated. The third and fourth output currents CP3and CP4having the same phase overlap and thus the second control voltage VCM is generated. Therefore, the first control voltage VCP is changed at every half cycle T/2 of the reference signal FREF, and the second control voltage VCM is changed at every cycle T of the reference signal FREF.

According to the PLL circuit according to embodiments of the present invention, by controlling the phase and frequency of one of the positive and negative control voltages, the spur noise and phase noise appearing in the output signal can decrease.