Voltage overshoot reduction circuits

Feedback circuits capable of preventing output voltage overshoot in closed-loop DC regulated power supplies are presented. The circuits employ hysteresis at the input of an operational amplifier to improve the response time of the feedback circuits to a rising output voltage reaching a threshold. The feedback circuits substantially reduce, if not prevent, output voltage overshoot during start-up and hard and soft output shorts.

BACKGROUND OF THE INVENTION

This invention relates to circuits that reduce output voltage overshoot. More particularly, this invention relates to integrated circuits that reduce output voltage overshoot in opto-coupler controlled closed-loop DC power supplies.

An output voltage overshoot is a transient rise in output voltage beyond a specified output voltage level. Excessive overshoot can cause system failure and can damage both the power supply and loads coupled to the power supply. Output overshoot typically occurs when the power supply is first turned on or when the power supply output is overloaded or inadvertently shorted to ground or to a voltage less than the regulated output voltage (i.e., shorted to an “undervoltage”) and then released. In sum, the following three conditions can cause output voltage overshoot: start-up, output short to ground (hard short), and output short to an undervoltage (soft short).

Known closed-loop isolated power supplies include feedback circuitry that regulates the output voltage (i.e., maintains the output voltage at a specified level). Such feedback circuitry commonly includes a high gain amplifier and an opto-coupler. When the power supply output voltage rises above a threshold, the amplifier drives the opto-coupler, which provides one or more signals to a power supply control circuit that stops the rise in output voltage and allows the output voltage to return to its specified level. However, the response time of basic feedback circuitry is often slow. In particular, the slew time of the amplifier output is often longer than the slew time of the rising output voltage. Slew time is the time it takes a signal to make a transition. Thus, basic feedback circuitry is generally unable to prevent potentially large output voltage overshoots from occurring, thus only belatedly being able to regulate the overshot output voltage back down to the desired level.

Improved feedback circuits are also known. For example, soft-start circuits are known that limit or prevent overshoot at start-up. Soft-start circuits gradually apply power to the output to slow the rising output voltage. The feedback circuitry then has sufficient time to respond to the output voltage as it reaches the specified level. These circuits, however, are ineffective against soft and hard output shorts.

Feedforward slew rate detector circuits and overvoltage comparator circuits are also known. These circuits generate and route signals to control circuitry via a fast-path around the slower feedback amplifier path in response to the output voltage reaching a threshold. However, output voltage ripples, which typically occur on the output of DC power supplies, are often of sufficient magnitude to exceed thresholds used in the fast-paths of such circuits and can thus cause the power supply output to oscillate.

Clamping amplifier output circuits are also known in which the voltage swing on the feedback amplifier's output is limited in order to provide a quicker response to output overshoot. However, even the limited voltage swings of known clamping circuits are still too large to allow the circuit to respond quickly enough to prevent overshoot, thus resulting in only marginal improvement.

In sum, no known closed-loop power supply feedback circuit is effective against all three common overshoot conditions mentioned above.

In view of the foregoing, it would be desirable to be able to provide a circuit that reduces, if not eliminates, output voltage overshoot in an opto-coupler controlled closed-loop isolated power supply under any of several conditions.

It would also be desirable to be able to provide an integrated circuit that responds quickly to a threshold being met.

SUMMARY OF THE INVENTION

It is an object of this invention to provide a circuit that reduces, if not eliminates, output voltage overshoot in an opto-coupler controlled closed-loop isolated power supply under any of several conditions.

It is also an object of this invention to provide an integrated circuit that responds quickly to a threshold being met.

In accordance with the invention, a circuit is provided that substantially reduces, if not eliminates, output voltage overshoot by responding quickly to a rising output voltage reaching a threshold. The circuit includes an amplifier having an input whose voltage swing indicates that an output voltage has risen to a threshold level. The invention improves response time by substantially reducing the amount of voltage swing needed on that amplifier input to indicate that the output voltage has reached the threshold. The amount of voltage swing is reduced by adding hysteresis to a reference voltage coupled to another input of the amplifier.

Methods of substantially reducing, if not eliminating, output voltage overshoot and of responding quickly to a threshold being met are also provided.

DETAILED DESCRIPTION OF THE INVENTION

To better understand the invention and its advantages, several known techniques for preventing or limiting output voltage overshoot, and their disadvantages, are first described.

FIG. 1represents a known opto-coupler controlled closed-loop switched-mode DC power supply100. Switched-mode power supplies are commonly used because of their high efficiency and good output regulation. Power supply100includes primary switching control circuit102, isolation power transformer104, output rectifiers and filter106, feedback control108, and opto-coupler110. The duty cycle of switching control circuit102controls the voltage level of the power supply output at node VOUT. Control circuit102typically converts low frequency voltage to high frequency voltage. Isolation transformer104typically steps high input voltage down to low output voltage and isolates the high voltage from the power supply output. The high frequency, low output AC voltage from transformer104is typically rectified and filtered at106to produce a DC output voltage at node VOUT. Feedback control108typically regulates the voltage at node VOUT by sensing the output voltage level and generating and forwarding one or more control signals to switching control circuit102via opto-coupler110when the voltage at node VOUT exceeds or drops below a threshold level. The control signals affect the duty cycle of control circuit102, which affects the amount of current provided to the output, which in turn affects the output voltage level. Opto-coupler110provides high primary-to-secondary circuit isolation to prevent internal high voltage potentials from reaching the power supply output. The input and output of opto-coupler110are optically coupled to each other (i.e., there is no electrical or physical connection between them). This results in extremely high input-to-output DC isolation.

FIG. 2represents known embodiments of a feedback control circuit and an opto-coupler in a closed-loop power supply. Feedback control circuit208includes output divider resistors212and214, high gain voltage amplifier VA1, resistor216and capacitor218, resistor220, optional fixed low DC gain buffer amplifier VA2, and resistors222and224. VA1and VA2may be general purpose operational amplifiers (op-amps) and may be the same off-the-shelf part. Reference voltage VREF1is coupled to the non-inverting input of amplifier VA1, while reference voltage VREF2is coupled to the non-inverting input of amplifier VA2. The gain of amplifier VA2is “K,” where the value of resistor222is equal to K times the value of resistor220. Opto-coupler210includes light emitting diode (LED)226and NPN light-sensitive transistor228. LED226and transistor228are optically coupled such that the conductance of transistor228is dependent upon the output luminance of LED226.

At start-up or during “output short release” (i.e., either a hard or soft output short), node VA1OUT is “high” (i.e., in a high voltage state, also referred to as a logical or binary “1”) and node VOPTO is “low” (i.e., in a low voltage state, also referred to as a logical or binary “0”). This drives the output of opto-coupler210low (e.g., at or near 0 volts), permitting control circuit102to operate at its maximum duty cycle. Maximum current is thus delivered to output VOUT. As VOUT rises toward the supply's specified voltage level, voltage amplifier VA1senses, pulling node VA1OUT low. Amplifier VA2then switches when node VA1OUT goes below VREF2. Node VOPTO then goes high, driving the output of opto-coupler210high, which reduces the duty cycle of control circuit102. This results in a reduction of current to node VOUT, which prevents further increases in output voltage level and ultimately maintains the output voltage at the regulated level.

However, the falling slew time at node VA1OUT is longer than the rising slew time at node VOUT. Slew time is the time it takes a signal to make a transition. Thus, feedback control circuit208does not respond quickly enough to prevent a high output overshoot from occurring at node VOUT. The slew time at node VA1OUT is limited by voltage divider resistors212and214and by compensation network resistor216and capacitor218. In particular, the discharging of capacitor218, which is required in order to pull down the voltage at node VA1OUT, is limited by resistors212and214and the voltage at node VOUT. Accordingly, feedback control circuit208is largely unable to prevent output voltage overshoot.

FIG. 3shows a known feedback control circuit that addresses output voltage overshoot at start-up. Soft-start feedback control circuit308is coupled to opto-coupler310and is typically an integrated circuit that includes output divider resistors312and314, high gain voltage amplifier VA1, resistor316and capacitor318, resistor320, optional fixed low DC gain buffer amplifier VA2and resistor322. Feedback control circuit308also includes external capacitor330coupled to a non-inverting third input of amplifier VA1. (Although not shown inFIG. 3, feedback control circuit308and opto-coupler310are coupled to a power supply's primary circuits, such as, for example, switching control circuit102, isolation power transformer104, and output rectifiers/filter106of FIG.1).

Feedback control circuit308causes output voltage at node VOUT to rise gradually. The voltage at node Vs is the reference voltage of amplifier VA1until Vs rises to the value of VREF1, at which time, VREF1becomes the reference voltage. The rising slew rate of the voltage at node VOUT is controlled by the preset current Is and capacitor330in accordance with T=C330(dV)/Is, where T is time and dV is the output voltage swing. By setting VOUT's rising slew rate slow, output voltage overshoot can be prevented or substantially limited—but only if capacitor330begins charging from a discharged state.

Feedback control circuit308has a number of disadvantages. First, because capacitor330is external to the integrated circuit, an input/output (I/O) package pin is required to connect capacitor330to feedback control circuit308. As is known, unused I/O pins can be rare in high density integrated circuit packages.

Furthermore, feedback control circuit308cannot prevent output overshoots from occurring during either a soft or hard output short, because soft-start capacitor330remains charged after start-up. This prevents the voltage at node Vs from being the low (below VREF1), slowly rising reference voltage it was during start-up. Moreover, even if capacitor330were reset (i.e., discharged) in response to an output short release, feedback circuit308still would not perform satisfactorily because the voltage at VOUT would collapse to ground following the capacitor discharge and voltage drop at Vs. This collapse could cause, for example, output oscillation or data loss.

FIG. 4shows a known feedforward slew rate detector408coupled to opto-coupler410. Detector408includes capacitor432, resistor434, amplifier VF1, diode436, and resistor438(note that resistors438and424can both be replaced with a resistor inside of opto-coupler410). Capacitor432and resistor434are typically external components coupled to the integrated circuit detector408. Reference voltage Vc is coupled to the inverting input of amplifier VF1. As the voltage at output node VOUT slews up at full speed during start-up or output short release, the voltage at node Vs will follow the voltage at node VOUT because of capacitor-coupling until capacitor432reaches the reference voltage Vc. Amplifier VF1then activates and “feeds-forward” a control signal (bypassing the slower amplifier VA1-VA2path) directly to opto-coupler410. Opto-coupler410feeds the control signal to switching control circuitry (not shown in FIG.4), which reduces current to node VOUT, thus slowing or stopping the voltage rise at node VOUT. The output slew rate (and thus the output overshoot) can be controlled by selecting appropriate values for capacitor432and resistor434in accordance with dV/dT=Is/C432, where dV/dT is the output slew rate and Is=Vc/R434.

Feedforward slew rate detector408has a number of disadvantages. First, it requires many components in addition to the amplifier VA1-VA2path components. Second, an input/output (I/O) package pin is required to connect capacitor432and resistor434to integrated circuit detector408. As mentioned previously, unused I/O pins can be rare in high density integrated circuit packages. Furthermore, output voltage ripples at node VOUT are directly coupled to the non-inverting input of amplifier VF1. As the trend in output voltage up-level magnitude continues to decrease (up-levels as low as about 1 volt are becoming more common in many electronics systems), the reference voltage at node Vc has to be set at an accordingly lower level. Voltage ripples caused by large load changes may thus be of sufficient magnitude to erroneously activate amplifier VF1, causing output oscillation.

FIG. 5shows a known overvoltage comparator circuit508coupled to opto-coupler510. In general, a comparator compares a reference voltage level to another voltage level and produces a signal when the other voltage level is different than the reference level. Comparator circuit508is an integrated circuit that includes amplifier VF1, diode536, and resistor538(note that resistors538and524can both be replaced with a resistor inside of opto-coupler510). Reference voltage Vc is coupled to the inverting input of amplifier VF1. Comparator circuit508also includes external precision voltage divider resistors532and534coupled to node VOUT and the non-inverting inverting input of amplifier VF1.

As the voltage at output node VOUT slews up at full speed during start-up or output short release, amplifier VF1trips when the VOUT voltage reaches the level preset by reference voltage Vc and voltage divider resistors532and534. A control signal is then fed directly to opto-coupler510, which forwards the signal to switching control circuitry (not shown in FIG.5), which reduces current to node VOUT. The voltage rise at node VOUT is thus either slowed or stopped.

Overvoltage comparator circuit508also has disadvantages. First, it too requires many components in addition to the amplifier VA1-VA2path components. Second, the precision voltage divider resistors532and534are expensive, and an I/O package pin is required to couple them to amplifier VF1. Moreover, as in feedforward slew rate detector408, output voltage ripples at node VOUT are directly coupled to the non-inverting input of amplifier VF1. And again, as the trend in output voltage up-levels continues to decrease, the reference voltage at node Vc has to be set accordingly lower. Thus, voltage ripples caused by large load changes may be of sufficient magnitude to erroneously activate amplifier VF1, causing output oscillation.

FIG. 6shows a known clamping amplifier output circuit608coupled to opto-coupler610. Clamping circuit608includes output divider resistors612and614, high gain voltage amplifier VA1, resistor616, diode617, capacitor618, resistor620, optional fixed low DC gain buffer amplifier VA2, resistor622, and resistor624. Reference voltage VREF1is coupled to the non-inverting input of amplifier VA1, and reference voltage VREF2is coupled to non-inverting input of amplifier VA2. The gain of amplifier VA2is “K,” where the value of resistor622is equal to K times the value of resistor620.

As the voltage at output node VOUT slews up at full speed during start-up or output short release, the voltage at node VA1OUT is clamped by diode617to about 0.7 volts higher than VREF1. This reduces the voltage swing (from a high state to a low state below VREF2). A shorter voltage swing reduces slew time, which improves response time. Improved response time is needed to prevent output voltage overshoot. However, voltage overshoot is still very likely to occur because the voltage swing at node VA1OUT (referred to hereinafter as ΔVA1OUT) is still too great. Thus, clamping circuit608is capable of limiting, but is not likely to prevent, output voltage overshoot.

In sum, none of known circuits208,308,408,508, and608provides a practical, complete solution to output voltage overshoot in an opto-coupler controlled closed-loop DC power supply.

Note that output voltage overshoot is directly proportional to ΔVA1OUT. Thus, reducing ΔVA1OUT to as little as possible, and preferably to zero, results in a feedback circuit that should be able to respond quickly enough to prevent output voltage overshoot.

FIG. 7shows feedback control circuit708that substantially reduces, if not eliminates, output voltage overshoot during start-up, hard output shorts to ground, and soft output shorts to an undervoltage in an opto-coupler controlled closed-loop power supply in accordance with the invention. Moreover, large output voltage ripples are not likely to interfere adversely with this circuit. Feedback control circuit708is preferably coupled to opto-coupler710and preferably to a closed-loop power supply's primary circuits (e.g., primary switching control circuit102, isolation power transformer104, output rectifiers and filter106of FIG.1).

Feedback control circuit708includes output divider resistors712and714, high gain voltage amplifier VA1, resistor716and capacitor718, resistor720, fixed low DC gain buffer amplifier VA2, resistor722, and resistor724(which may instead be a part of opto-coupler710). Amplifier VA2has a gain of “K,” where the value of resistor722is equal to K times the value of resistor720. Reference voltage VREF1is coupled to the non-inverting input of amplifier VA1. Amplifiers VA1and VA2can each be the same general purpose op-amp.

Feedback control circuit708also advantageously includes a hysteresis circuit740coupled to the output of amplifier VA1and to the non-inverting input of amplifier VA2in accordance with the invention. Hysteresis circuit740includes PNP transistor741; resistors742,746, and750; NPN transistor744; DC voltage748, and DC voltage V+(both are internally-generated circuit voltages). The non-inverting input of amplifier VA2is coupled to node VREF7(note that VREF7is a node and not a voltage source).

As described above with respect to feedback control circuit208, during start-up or output short release, the voltage at node VOUT is below the specified voltage level resulting in the voltage at node VA1OUT being in a high state. To minimize output overshoot, VA1OUT should be clamped to the minimum high state voltage level necessary to drive the output of opto-coupler710to the low state. The time it takes for VA1OUT to switch from its high state to a low state capable of driving the output of opto-coupler710to a high state (i.e., generating a control signal) determines the amount of output overshoot that may occur. If that slew time is substantially zero, substantially no overshoot occurs.

Advantageously, hysteresis circuit740initially clamps the voltage at VA1OUT to a value that maintains the output of opto-coupler710in a low state, yet results in substantially no VA1OUT slew time to drive opto-coupler710to a high output state in response to the output voltage at VOUT reaching a preset threshold. This is accomplished by adding hysteresis to the reference voltage coupled to the non-inverting input of amplifier VA2at node VREF7.

During normal operation (i.e., the voltage at VOUT is at its specified level), transistors744and741are OFF (i.e., non-conducting) and the voltage at node VREF7is equal to V+. When the voltage at VOUT is below the specified level for a long enough period, such as during start-up or a hard or soft output short, the voltage at node VA1OUT goes high to a first clamping level determined as follows:

If, for example, V+=1.5 volts, V748=0.5 volts, and the base-to-emitter voltage drop of transistor741is 0.7 volts, the first clamping level is 1.7 volts. As soon as VA1OUT reaches 1.7 volts, transistor741turns ON (i.e., becomes conductive). This causes transistor744to turn ON, which lowers the voltage at node VREF7as determined by the values of resistors750and746and the collector-to-emitter voltage drop across transistor744. If the total drop is about 0.3 volts, the voltage at VREF7drops to about 1.2 volts. This pulls down the voltage at VA1OUT by about 0.3 volts to about 1.4 volts.

Thus, as the output voltage rises, but before it reaches its specified level, transistors741and744are both ON, VA1OUT is 1.4 volts, VREF7is 1.2 volts, and VOPTO is about 0 volts. In response to the voltage at VOUT reaching its specified level (which is also the threshold voltage level at the inverting input of amplifier VA1preset by voltage divider resistors712and714), amplifier VA1activates, forcing the voltage at node VA1OUT to go low. Advantageously, the voltage at node VA1OUT only has to swing down by less than about 50 mV to reduce transistor741's collector current, causing transistor744to turn OFF. This causes the voltage at VREF7to jump up substantially instantaneously by about 0.3 volts to 1.5 volts. This voltage jump provides substantially instantaneous phase change at amplifier VA2's inputs, forcing the voltage at node VOPTO to jump from about 0 volts to a high state. This high state has a value determined by multiplying 0.3 volts by K, which for a K of about 6 is about 2 volts. This 2-volt jump at the input of opto-coupler710transmits substantially instantaneously a control signal to control circuitry, preventing the voltage at VOUT from overshooting.

Advantageously, by presetting the amount of hysteresis on the reference voltage at VREF7, VA1OUT can be clamped at any voltage level required to improve circuit response time such that output voltage overshoot is reduced to substantially zero.

Moreover, during normal operation, the voltage at VREF7is about 1.5 volts and the voltage at VOPTO ranges from about 1.5 volts (low state) to about 5 volts (high state) for a VA2gain (K) of about 6. VA1OUT will therefore range between 0.9 volts (low state) and 1.5 volts (high state) and is not likely to approach the 1.7 volt clamping level unless the output voltage drops below the specified level for a long enough period of time (i.e., the time required to charge capacitor718to a higher level). Hysteresis circuit740therefore remains inactive and substantially transparent to feedback control circuit708.

Should the voltage at VA1OUT drop below the specified level for the period of time required to charge capacitor718to a higher level, hysteresis circuit740will activate. Capacitor718charges to the higher level as follows: upon the voltage at VOUT dropping to an undervoltage, the voltage at the inverting input of VA1also drops. This causes the output of VA1(i.e., VA1OUT) to rise. Capacitor718now starts charging beyond its previous steady-state level. If VOUT does not return to its regulated level before VA1OUT reaches the 1.7 volt clamping level, hysteresis circuit740activates as described above.

Output voltage ripples at node VOUT advantageously should not affect the voltage at node VA1OUT because of the time constant set by capacitor718and resistor716. Amplifier VA2can therefore advantageously continue operating in amplifier mode unaffected by very large output voltage ripples at node VOUT.

FIGS. 8-11show various voltage waveforms of feedback control circuit708. In particular,FIG. 8shows the voltage waveform at node VOUT,FIG. 9shows the voltage waveform at node VA1OUT,FIG. 10shows the voltage waveform at node VREF7, andFIG. 11shows the voltage waveform at node VOPTO. As shown by waveform portion852, when the voltage at node VOUT goes below its specified or programmed level854, the voltage at node VA1OUT rises from a steady-state down level955to a first clamped level956. The voltage at node VREF7, which was initially set at voltage level1060, drops substantially immediately to voltage level1062in response to VA1OUT reaching level956. The voltage at node VA1OUT responds to VREF7's drop by dropping to voltage level958. The voltage at node VOPTO switches from a high state to low state1164in response to VA1OUT rising to level956and advantageously remains at low state1164while the voltages at both nodes VREF7and VA1OUT drop to levels1062and958, respectively. The low voltage state at node VOPTO allows the primary power supply circuits to increase current to node VOUT, driving the output voltage back to its specified level854during start-up or after output short release.

In response to the voltage at node VOUT reaching specified level854and VA1OUT dropping about 50 mV (not shown in FIG.9), the voltage at node VREF7substantially instantaneously jumps to level1060, causing the voltage at node VOPTO to jump to high state1166. This results in the primary power supply circuits substantially immediately decreasing the amount of current to node VOUT, thus substantially, if not completely, preventing output voltage overshoot at node VOUT. The voltage at VOPTO continues to rise to its steady-state level1168. The invention advantageously provides the substantially instantaneous jump from level1164to level1166. In response to the output voltage reaching its specified value, the voltage at VA1OUT returns to its steady-state down level955.

In one embodiment of the invention, the voltage levels shown inFIGS. 8-11can have the following values:level854=3.3 voltslevel956=1.7 voltslevel958=1.4 voltslevel1060=1.5 voltslevel1062=1.2 voltslevel1164=0 voltslevel1166=2.0 volts

Note that these values are merely illustrative. Different values may be used in accordance with other conditions and applications.

Also note that feedback control circuits of the invention can be used in circuits and components other than an opto-coupler controlled closed-loop power supply. For example, circuits of the invention can be included in most feedback control systems with a main loop compensating network in which the opto-coupler can be replaced with a PWM (pulse-width-modulator) comparator and amplifier VA2can be operated as a non-inverting amplifier, as shown in FIG.12.

FIG. 12shows another embodiment of a feedback control circuit in accordance with the invention. Feedback control circuit1208can be part of general purpose PWM DC-to-DC converter and includes output divider resistors1212and1214, high gain voltage amplifier VA1, and resistor1216and capacitor1218, which form a loop filter. Circuit1208also advantageously includes hysteresis circuit1240, which includes PNP transistor1241; resistors1242,1246, and1250; NPN transistor1244; DC voltage1248, DC voltage V+(both are internally-generated circuit voltages). Hysteresis circuit1240preferably also includes non-inverting amplifier VA2and resistors1220and1222. The non-inverting input of amplifier VA2is coupled to node VREF12(note that VREF12is a node and not a voltage source) and the inverting input is grounded. The output of VA2is coupled to the non-inverting input of PWM comparator1210, which controls the duty cycle of the DC-to-DC converter (primary circuits of which are not shown). The inverting input of PWM comparator1210is coupled to a sawtooth ramp signal.

The operation of hysteresis circuit1240with respect to the voltages at node VREFl2and node VA1OUT is substantially identical to hysteresis circuit740. Thus, during normal operation (VOUT is at its specified level), VA1OUT is low, VREF12is at V+, and the output of VA2is high. PWM comparator1210produces a narrow output pulse that results in a preferably minimum duty cycle (reducing current to VOUT). When the voltage at VOUT drops below its specified level for a long enough period, VA1OUT goes high, VREF12drops to a lower voltage level, the output of VA2goes low, and PWM comparator1210produces a wide output pulse that results in a preferably maximum duty cycle (increasing current to VOUT). (The terms “minimum” and “maximum” are relative, depending on the widths of the produced comparator output pulse as determined by the voltages of the sawtooth ramp signal and the output of VA2.) In response to VOUT reaching its specified voltage level, VREF12jumps substantially instantaneously back up to V+, which reduces the duty cycle, substantially preventing further increases in the voltage level at VOUT. In sum, feedback control circuit1208has the same advantages as feedback control circuit708.

Thus it is seen that circuits are provided that reduce output voltage overshoot under various conditions. One skilled in the art will appreciate that the invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the invention is limited only by the claims which follow.