Storage device and method of operating the same

The present disclosure relates to a storage device and a method of operating the same. The storage device includes a memory device including a memory cell array that stores normal data and map data, and a memory controller configured to control overall operation, including program operation, read operation, and erase operation, of the memory device in response to requests from a host. The memory device is configured to, during a map data load operation, transmit first map data to the memory controller by reading the first map data among the map data stored in the memory cell array, and transmit second map data to a page buffer group of the memory device by reading the second map data among the map data.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2020-0068098 filed on Jun. 5, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated by reference herein.

BACKGROUND

1. Technical Field

The present disclosure relates to an electronic device, and more particularly, to a storage device and a method of operating the storage device.

2. Related Art

A storage device is a device that stores data under the control of a host device such as a computer or a smartphone. A storage device may include a memory device in which data is stored and a memory controller controlling the memory device. The memory device may be a volatile memory device or a non-volatile memory device.

A volatile memory device is a device that stores data only when power is supplied and loses the stored data when the power supply is cut off. Volatile memory devices include, for example, static random access memory (SRAM), dynamic random access memory (DRAM), and the like.

A non-volatile memory device is a device that does not lose data even though power is cut off. Non-volatile memory devices include, for example, read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory, and the like.

SUMMARY

An embodiment of the present disclosure is directed to a storage device capable of increasing a loading capacity of map data and an improved operation speed, and a method of operating the storage device.

A storage device according to an embodiment of the present disclosure includes a memory device including a memory cell array that stores normal data and map data, and a memory controller configured to control overall operation, including program operation, read operation, and erase operation, of the memory device in response to requests from a host. The memory device is configured to, during a map data load operation, transmit first map data to the memory controller by reading the first map data among the map data stored in the memory cell array, and transmit second map data to a page buffer group of the memory device by reading the second map data among the map data.

A method of operating a storage device according to an embodiment of the present disclosure includes: reading first map data and second map data among map data stored in a system block of a memory cell array; transmitting the first map data to a memory controller, storing the first map data in a memory buffer of the memory controller, and storing the second map data in a page buffer group; and performing a map data search operation of searching whether search map data corresponding to a received logical block address is included in the second map data, when the logical block address is received from the memory controller to the page buffer group.

A method of operating a storage device according to an embodiment of the present disclosure includes: storing first map data among map data stored in a system block in a memory controller, and storing second map data among the map data in a page buffer group of the memory device, during a map data load operation; receiving a logical block address from the memory controller by the memory device, and searching whether search map data corresponding to the received logical block address is included in the second map data, during a map data search operation; receiving normal data and the logical block address from the memory controller by the memory device, storing the normal data in a memory cell array, and then leave remaining map data corresponding to the logical block address among the second map data in the page buffer group, during a data program operation; and storing the map data left remaining in the page buffer group, in the memory cell array during a map data flush operation.

DETAILED DESCRIPTION

Specific structural or functional descriptions of embodiments according to the concept which are disclosed in the present specification or application are illustrated only to describe the embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure may be carried out in various forms and the descriptions are not limited to the embodiments described in the present specification or application.

Hereinafter, the present disclosure will be described in detail by describing an embodiment of the present disclosure with reference to the accompanying drawings. Hereinafter, an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

FIG. 1is a diagram illustrating a storage device according to an embodiment of the present disclosure.

Referring toFIG. 1, the storage device50may include a memory device100and a memory controller200that controls an operation of the memory device. The storage device50is a device that stores data under the control of a host300such as a cellular phone, a smartphone, an MP3 player, a laptop computer, a desktop computer, a game player, a TV, a tablet PC, or an in-vehicle infotainment system.

The storage device50may be manufactured as one of various types of storage devices according to a host interface that is a communication method with the host300. For example, the storage device50may be configured as any of various types of storage devices such as an SSD, a multimedia card in a form of an MMC, an eMMC, an RS-MMC and a micro-MMC, a secure digital card in a form of an SD, a mini-SD and a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnection (PCI) card type storage device, a PCI express (PCI-E) card type storage device, a compact flash (CF) card, a smart media card, and a memory stick.

The storage device50may be manufactured as any of various types of packages. For example, the storage device50may be manufactured as any of various types of package types, such as a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), a wafer-level fabricated package (WFP), and a wafer-level stack package (WSP).

The memory device100may store normal data and map data. Normal data, for example, is data associated with the routine operation of an apparatus in which the memory device100is included. Map data is data that indicates how the normal memory is laid out in the memory device100. The memory device100operates under the control of the memory controller200. The memory device100may include a memory cell array110including a plurality of memory cells that store the normal data and the map data.

Each of the memory cells may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) storing four data bits.

The memory cell array110may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. One memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in the memory device100or reading data stored in the memory device100. A memory block may be a unit for erasing data. In an embodiment, the memory device100may include double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate4 (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR), Rambus dynamic random access memory (RDRAM), NAND flash memory, vertical NAND flash memory, a NOR flash memory device, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM), or the like. In the present specification, for convenience of description, it is assumed that the memory device100includes NAND flash memory.

The memory device100is configured to receive a command and an address from the memory controller200and access a region selected by the address of the memory cell array. That is, the memory device100may perform an operation based on a command on the region selected by the address. For example, the memory device100may perform a write operation (program operation), a read operation, and an erase operation. During the program operation, the memory device100may program data to the region selected by the address. During the read operation, the memory device100may read data from the region selected by the address. During the erase operation, the memory device100may erase data stored in the region selected by the address.

In an embodiment, the memory device100may include a page buffer group123. During the program operation, the page buffer group123receives and temporarily stores data to be programmed, and then stores the temporarily stored data in the memory cell array110. In addition, during the read operation, the page buffer group123reads the data stored in the memory cell array110and outputs the read data to the memory controller200. In addition, the page buffer group123may read and store the map data stored in the memory cell array110. The page buffer group123may perform an operation of searching map data corresponding to a logical block address (LBA) among the stored map data by receiving the LBA from the memory controller200.

The memory controller200controls an overall operation of the storage device50.

When power is applied to the storage device50, the memory controller200may execute firmware FW. When the memory device100is a flash memory device, the memory controller200may operate firmware such as a flash translation layer (FTL) for controlling communication between the host300and the memory device100.

In an embodiment, the memory controller200may receive the map data from the memory device100and store the map data. In an embodiment, the memory controller200may receive data and a logical block address (LBA) from the host300and convert the LBA into a physical block address (PBA) indicating an address of memory cells in which data included in the memory device100is to be stored, using the map data.

The memory controller200may control the memory device100to perform the program operation, the read operation, or the erase operation in response to a request from the host300. During the program operation, the memory controller200may provide a program command, the LBA, and the normal data to the memory device100. During the read operation, the memory controller200may provide a read command and the PBA to the memory device100. During the erase operation, the memory controller200may provide an erase command and the PBA to the memory device100.

In an embodiment, the memory controller200may generate and transmit the program command, the address, and the data to the memory device100regardless of the request from the host300. For example, the memory controller200may provide a command, an address, and data to the memory device100so as to perform background operations such as a program operation for wear leveling and a program operation for garbage collection.

In an embodiment, the memory controller200may control at least two memory devices100. In this case, the memory controller200may control the memory devices100according to an interleaving method so as to improve operation performance. The interleaving method may be an operation method for overlapping operation periods of at least two memory devices100.

In an embodiment, the memory controller200may include a processor210and a memory buffer220.

The processor210may control an overall operation of the memory controller200and perform a logical operation. The processor210may communicate with the external host300and communicate with the memory device100. In addition, the processor210may communicate with the memory buffer220. The processor210may control an operation of the storage device50using the memory buffer220as an operation memory, a cache memory, or a buffer memory.

The processor210may perform a function of a flash translation layer (FTL). The processor210may convert a logical block address (LBA) provided from the host300into a physical block address (PBA) through the FTL. The FTL may convert the LBA to the PBA using mapping data. The FTL may perform an address conversion operation using a mapping table stored in the memory buffer220.

For an embodiment, the processor210is configured to randomize data received from the host300. For example, the processor210may randomize the data received from the host300using a randomizing seed. The randomized data is provided to the memory device100as data to be stored and programmed in the memory cell array110.

The processor210is configured to de-randomize data received from the memory device100during the read operation. For example, the processor210may de-randomize the data received from the memory device using a de-randomizing seed. The de-randomized data may be output to the host300.

As an embodiment, the processor210may perform randomization and de-randomization using driving software or firmware.

The memory buffer220may be used as operation memory, cache memory, or buffer memory of the processor210. The memory buffer220may store codes and commands executed by the processor210. The memory buffer220may store the map data. The memory buffer220may store data processed by the processor210. The memory buffer220may include static RAM (SRAM) or dynamic RAM (DRAM).

The memory buffer220may include a write/read buffer221and a map cache buffer222.

The write/read buffer221stores the normal data received from the host300during the program operation, and transmits the stored data to the memory device100. In addition, the write/read buffer221stores the normal data received from the memory device100during the read operation, and transmits the stored data to the host300.

The map cache buffer222may receive the map data from the memory device100and store the map data. For example, during a power-up operation of the storage device, the memory device100may read some of the map data stored in the memory cell array110and transmit the read data to the memory controller200, and the memory controller200may store the map data received from the memory device100in the map cache buffer222.

The host300may communicate with the storage device50using at least one of various communication methods such as a universal serial bus (USB), a serial AT attachment (SATA), a serial attached SCSI (SAS), a high speed interchip (HSIC), a small computer system interface (SCSI), a peripheral component interconnection (PCI), a PCI express (PCIe), a nonvolatile memory express (NVMe), a universal flash storage (UFS), a secure digital (SD), a multimedia card (MMC), an embedded MMC (eMMC), a dual in-line memory module (DIMM), a registered DIMM (RDIMM), and a load reduced DIMM (LRDIMM).

The storage device50according to an embodiment of the present disclosure described above may read the first map data among the map data stored in the memory cell array110of the memory device100to store the first map data in the map cache buffer222of the memory controller200, and may read the second map data to store in the page buffer group123of the memory device100. Therefore, a data storage capacity capable of storing the read map data may be increased.

In an embodiment, the first map data may be cold data having a relatively low number of accesses among the map data stored in the memory cell array110, and the second map data may be hot data having a relatively high number of accesses among the map data stored in the memory cell array110. In addition, in an embodiment, the first map data may be map data first read by a storage capacity of the map cache buffer222among the map data stored in the memory cell array110, and the second map data may be map data read by a map data storage capacity of the page buffer group123after the first map data is read among the map data stored in the memory cell array110.

FIG. 2is a diagram illustrating a structure of the memory device ofFIG. 1.

Referring toFIG. 2, the memory device100may include a memory cell array110, a peripheral circuit120, and control logic130.

The memory cell array110includes a plurality of memory blocks BLK1to BLKz. The plurality of memory blocks BLK1to BLKz are connected to an address decoder121through row lines RL. The plurality of memory blocks BLK1to BLKz are connected to a page buffer group123through bit lines BL1to BLm. As an embodiment, at least one memory block (for example, BLK1) among the plurality of memory blocks BLK1to BLKz may be a system block. The system block may store a read reclaim table and the map data. The map data may include a plurality of map tables. A detailed description of the map data is provided later. Each of the plurality of memory blocks BLK1to BLKz includes a plurality of memory cells. As an embodiment, the plurality of memory cells are non-volatile memory cells. Memory cells connected to the same word line among the plurality of memory cells are defined as one page. That is, the memory cell array110is configured of a plurality of pages. According to an embodiment of the present disclosure, each of the plurality of memory blocks BLK1to BLKz included in the memory cell array110may include a plurality of dummy cells. At least one of the dummy cells may be connected in series between a drain select transistor and the memory cells and between a source select transistor and the memory cells.

Each of the memory cells of the memory device100may be configured as a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a triple-level cell (TLC) that stores three data bits, or a quad-level cell (QLC) that stores four data bits.

The peripheral circuit120may include an address decoder121, a voltage generator122, the page buffer group123, a data input/output circuit124, and a sensing circuit125.

The peripheral circuit120drives the memory cell array110. For example, the peripheral circuit120may drive the memory cell array110to perform a program operation, a read operation, and an erase operation.

The address decoder121is connected to the memory cell array110through the row lines RL. The row lines RL may include drain select lines, word lines, source select lines, and a common source line. According to an embodiment of the present disclosure, the word lines may include normal word lines and dummy word lines. According to an embodiment of the present disclosure, the row lines RL may further include a pipe select line.

The address decoder121is configured to operate in response to control of the control logic130. The address decoder121receives an address ADDR from the control logic130.

The address decoder121is configured to decode a block address of the received address ADDR. The address decoder121selects at least one memory block among the memory blocks BLK1to BLKz according to the decoded block address. The address decoder121is configured to decode a row address RADD of the received address ADDR. The address decoder121may select at least one word line of the selected memory block by applying voltages provided from the voltage generator122to at least one word line WL according to the decoded row address RADD.

During the program operation, the address decoder121may apply a program voltage to a selected word line and apply a pass voltage having a level less than that of the program voltage to unselected word lines. During a program verify operation, the address decoder121may apply a verify voltage to the selected word line and apply a verify pass voltage having a level greater than that of the verify voltage to the unselected word lines.

During the read operation, the address decoder121may apply a read voltage to the selected word line and apply a read pass voltage having a level greater than that of the read voltage to the unselected word lines.

According to an embodiment of the present disclosure, the erase operation of the memory device100is performed in memory block units. The address ADDR input to the memory device100during the erase operation includes a block address. The address decoder121may decode the block address and select one memory block according to the decoded block address. During the erase operation, the address decoder121may apply a ground voltage to the word lines input to the selected memory block.

According to an embodiment of the present disclosure, the address decoder121may be configured to decode a column address of the transferred address ADDR. The decoded column address may be transferred to the page buffer group123. As an example, the address decoder121may include a component such as a row decoder, a column decoder, and an address buffer.

The voltage generator122is configured to generate a plurality of operation voltages Vop by using an external power voltage supplied to the memory device100. The voltage generator122operates in response to the control of the control logic130.

As an example, the voltage generator122may generate an internal power voltage by regulating the external power voltage. The internal power voltage generated by the voltage generator122is used as an operation voltage of the memory device100.

As an embodiment, the voltage generator122may generate the plurality of operation voltages Vop using the external power voltage or the internal power voltage. The voltage generator122may be configured to generate various voltages required by the memory device100. For example, the voltage generator122may generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of selection read voltages, and a plurality of non-selection read voltages.

In order to generate the plurality of operation voltages Vop having various voltage levels, the voltage generator122may include a plurality of pumping capacitors that receive the internal voltage and selectively activate the plurality of pumping capacitors in response to the control logic130to generate the plurality of operation voltages Vop.

The plurality of generated operation voltages Vop may be supplied to the memory cell array110by the address decoder121.

The page buffer group123includes first to m-th page buffers PB1to PBm. The first to m-th page buffers PB1to PBm are connected to the memory cell array110through first to m-th bit lines BL1to BLm, respectively. The first to m-th page buffers PB1to PBm operate in response to the control of the control logic130.

The first to m-th page buffers PB1to PBm communicate data DATA with the data input/output circuit124. At a time of program, the first to m-th page buffers PB1to PBm receive the data DATA to be stored through the data input/output circuit124and data lines DL.

During the program operation, when a program pulse is applied to the selected word line, the first to m-th page buffers PB1to PBm may transfer the data DATA to be stored, that is, the data DATA received through the data input/output circuit124to the selected memory cells through the bit lines BL1to BLm. The memory cells of the selected page are programmed according to the transferred data DATA. A memory cell connected to a bit line to which a program permission voltage (for example, a ground voltage) is applied may have an increased threshold voltage. A threshold voltage of a memory cell connected to a bit line to which a program inhibition voltage (for example, a power voltage) is applied may be maintained. During the program verify operation, the first to m-th page buffers PB1to PBm read the data DATA stored in the memory cells from the selected memory cells through the bit lines BL1to BLm.

During the read operation, the page buffer group123may read the data DATA from the memory cells of the selected page through the bit lines BL and store the read data DATA in the first to m-th page buffers PB1to PBm.

During the erase operation, the page buffer group123may float the bit lines BL. As an embodiment, the page buffer group123may include a column selection circuit.

During a map data load operation, the first to m-th page buffers PB1to PBm may read the first map data among the map data stored in the system block BLK1. The read first map data is transmitted to the memory controller200ofFIG. 1through the data input/output circuit124. In addition, during the map data load operation, the first to m-th page buffers PB1to PBm read the second map data among the map data stored in the system block BLK1, and store the read second map data. During a map data search operation, the first to m-th page buffers PB1to PBm may search map data corresponding to the LBA received from the memory controller200among the stored second map data.

The data input/output circuit124is connected to the first to m-th page buffers PB1to PBm through the data lines DL. The data input/output circuit124operates in response to the control of the control logic130.

The data input/output circuit124may include a plurality of input/output buffers (not shown) that receive input data DATA. During the program operation, the data input/output circuit124receives the normal data DATA to be stored from an external controller (not shown). During the read operation, the data input/output circuit124outputs the normal data DATA transferred from the first to m-th page buffers PB1to PBm included in the page buffer group123to the external controller.

During the read operation or the verify operation, the sensing circuit125may generate a reference current in response to a signal of a permission bit VRYBIT generated by the control logic130and may compare a sensing voltage VPB received from the page buffer group123with a reference voltage generated by the reference current to output a pass signal or a fail signal to the control logic130.

The control logic130may be connected to the address decoder121, the voltage generator122, the page buffer group123, the data input/output circuit124, and the sensing circuit125. The control logic130may be configured to control all operations of the memory device100. The control logic130may operate in response to a command CMD transferred from an external device. The control logic130may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic130may be a control logic circuit operating in accordance with an algorithm and/or a processor executing control logic code.

The control logic130may generate various signals in response to the command CMD and the address ADDR to control the peripheral circuit120. For example, the control logic130may generate an operation signal OPSIG, the row address RADD, a read and write circuit control signal PBSIGNALS, and the permission bit VRYBIT in response to the command CMD and the address ADDR. The control logic130may output the operation signal OPSIG to the voltage generator122, output the row address RADD to the address decoder121, output the read and write control signal to the page buffer group123, and output the permission bit VRYBIT to the sensing circuit125. In addition, the control logic130may determine whether the verify operation has passed or failed in response to the pass or fail signal PASS/FAIL output by the sensing circuit125.

In an embodiment, the control logic130may store data received from the memory controller200in page buffers123of the page buffer group123under control of the memory controller200.

The control logic130may program the normal data or the map data stored in the page buffers123of the page buffer group123to the memory cell array110under the control of the memory controller200.

For example, when the control logic130receives a program command from the memory controller200, the control logic130may program the normal data, which is stored in the page buffers123of the page buffer group123, in the memory cell array110in response to the program command. When the control logic130receives a map data flush command from the memory controller200, the control logic130may program searched map data, which is stored in the page buffers123of the page buffer group123, in the system block BLK1of the memory cell array110in response to the map data flush command.

The control logic130may read the normal data stored in the memory cell array110under the control of the memory controller200. Specifically, the control logic130may first program the data, which is stored in the page buffers123of the page buffer group123, in the memory cell array110, and then store the data read from the memory cell array110in the page buffers123of the page buffer group123. The control logic130may provide the data stored in the page buffers of the page buffer group123to the memory controller200through the data input/output circuit124.

The control logic130may read the map data stored in the system block BLK1of the memory cell array110under the control of the memory controller200. Specifically, the control logic130may provide the first map data among the map data read from the system block BLK1to the memory controller200through the data input/output circuit124. In addition, the control logic130may store the second map data among the map data read from the system block BLK1.

FIG. 3is a diagram illustrating an embodiment of the memory cell array ofFIG. 2.

Referring toFIG. 3, the memory cell array110includes a plurality of memory blocks BLK1to BLKz. Each memory block has a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. Such plurality of memory cells are arranged along a +X direction, a +Y direction, and a +Z direction. A structure of each memory block is described in more detail with reference toFIGS. 4 and 5.

FIG. 4is a circuit diagram illustrating a memory block BLKa of the memory blocks BLK1to BLKz ofFIG. 3.

Referring toFIG. 4, the memory block BLKa includes a plurality of cell strings CS11to CS1mand CS21to CS2m. As an embodiment, each of the plurality of cell strings CS11to CS1mand CS21to CS2mmay be formed in a ‘U’ shape. In the memory block BLKa, m cell strings are arranged in a row direction (that is, the +X direction). InFIG. 5, two cell strings are arranged in a column direction (that is, the +Y direction). However, this is for convenience of description and it may be understood that three or more cell strings may be arranged in the column direction.

Each of the plurality of cell strings CS11to CS1mand CS21to CS2mincludes at least one source select transistor SST, first to n-th memory cells MC1to MCn, a pipe transistor PT, and at least one drain select transistor DST.

Each of the select transistors SST and DST and the memory cells MC1to MCn may have a similar structure. As an embodiment, each of the select transistors SST and DST and the memory cells MC1to MCn may include a channel layer, a tunneling insulating film, a charge storage film, and a blocking insulating film. As an embodiment, a pillar for providing the channel layer may be provided in each cell string. As an embodiment, a pillar for providing at least one of the channel layer, the tunneling insulating film, the charge storage film, and the blocking insulating film may be provided in each cell string.

The source select transistor SST of each cell string is connected between a common source line CSL and the memory cells MC1to MCp.

As an embodiment, the source select transistors of the cell strings arranged in the same row are connected to a source select line extending in the row direction, and the source select transistors of the cell strings arranged in different rows are connected to different source select lines. InFIG. 4, the source select transistors of the cell strings CS11to CS1mof a first row are connected to a first source select line SSL1. The source select transistors of the cell strings CS21to CS2mof a second row are connected to a second source select line SSL2.

As another embodiment, the source select transistors of the cell strings CS11to CS1mand CS21to CS2mmay be commonly connected to one source select line.

The first to n-th memory cells MC1to MCn of each cell string are connected between the source select transistor SST and the drain select transistor DST.

The first to n-th memory cells MC1to MCn may be divided into first to p-th memory cells MC1to MCp and (p+1)-th to n-th memory cells MCp+1 to MCn. The first to p-th memory cells MC1to MCp are sequentially arranged in a direction opposite to the +Z direction, and are connected in series between the source select transistor SST and the pipe transistor PT. The (p+1)-th to n-th memory cells MCp+1 to MCn are sequentially arranged in the +Z direction, and are connected in series between the pipe transistor PT and the drain select transistor DST. The first to p-th memory cells MC1to MCp and the (p+1)-th to n-th memory cells MCp+1 to MCn are connected to each other through the pipe transistor PT. Gates of the first to n-th memory cells MC1to MCn of each cell string are connected to the first to n-th word lines WL1to WLn, respectively.

A gate of the pipe transistor PT of each cell string is connected to a pipeline PL.

The drain select transistor DST of each cell string is connected between a corresponding bit line and the memory cells MCp+1 to MCn. The cell strings arranged in the row direction are connected to the drain select line extending in the row direction. The drain select transistors of the cell strings CS11to CS1mof the first row are connected to a first drain select line DSL1. The drain select transistors of the cell strings CS21to CS2mof the second row are connected to a second drain select line DSL2.

The cell strings arranged in the column direction are connected to the bit lines extending in the column direction. InFIG. 4, the cell strings CS11and CS21of the first column are connected to the first bit line BL1. The cell strings CS1mand CS2mof the m-th column are connected to the m-th bit line BLm.

The memory cells connected to the same word line in the cell strings arranged in the row direction configure one page. For example, the memory cells connected to the first word line WL1, among the cell strings CS11to CS1mof the first row configure one page. The memory cells connected to the first word line WL1, among the cell strings CS21to CS2mof the second row configure another page. The cell strings arranged in one row direction may be selected by selecting any one of the drain select lines DSL1and DSL2. One page of the selected cell strings may be selected by selecting any one of the word lines WL1to WLn.

As another embodiment, even bit lines and odd bit lines may be provided instead of the first to m-th bit lines BL1to BLm. In addition, even-numbered cell strings among the cell strings CS11to CS1mor CS21to SC2marranged in the row direction may be connected to the bit lines, and odd-numbered cell strings among the cell strings CS11to CS1mor CS21to CS2marranged in the row direction may be connected to odd bit lines, respectively.

As an embodiment, at least one of the first to n-th memory cells MC1to MCn may be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce an electric field between the source select transistor SST and the memory cells MC1to MCp. Alternatively, at least one dummy memory cell is provided to reduce an electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. As more dummy memory cells are provided, reliability of an operation for the memory block BLKa is improved, however, the size of the memory block BLKa increases. As less memory cells are provided, the size of the memory block BLKa may be reduced, however, the reliability of the operation for the memory block BLKa may be reduced.

In order to efficiently control at least one dummy memory cell, each of the dummy memory cells may have a required threshold voltage. Before or after an erase operation for the memory block BLKa, program operations for all or a part of the dummy memory cells may be performed. When the erase operation is performed after the program operation is performed, the dummy memory cells may have the required threshold voltage by controlling a voltage applied to dummy word lines connected to the respective dummy memory cells.

FIG. 5is a circuit diagram illustrating another embodiment of a memory block BLKb of the memory blocks BLK1to BLKz ofFIG. 3.

Referring toFIG. 5, the memory block BLKb includes a plurality of cell strings CS11′ to CS1m′ and CS21′ to CS2m′. Each of the plurality of cell strings CS11′ to CS1m′ and CS21′ to CS2m′ extends along a +Z direction. Each of the plurality of cell strings CS11′ to CS1m′ and CS21′ to CS2m′ includes at least one source select transistor SST, first to n-th memory cells MC1to MCn, and at least one drain select transistor DST stacked on a substrate (not shown) under the memory block BLK1′.

The source select transistor SST of each cell string is connected between a common source line CSL and memory cells MC1to MCn. The source select transistors of the cell strings arranged in the same row are connected to the same source select line. The source select transistors of the cell strings CS11′ to CS1m′ arranged in a first row are connected to a first source select line SSL1. The source select transistors of the cell strings CS21′ to CS2m′ arranged in a second row are connected to a second source select line SSL2. As another embodiment, the source select transistors of the cell strings CS11′ to CS1m′ and CS21′ to CS2m′ may be commonly connected to one source select line.

The first to n-th memory cells MC1to MCn of each cell string are connected in series between the source select transistor SST and the drain select transistor DST. Gates of the first to n-th memory cells MC1to MCn are connected to first to the n-th word lines WL1to WLn, respectively.

The drain select transistor DST of each cell string is connected between a corresponding bit line and the memory cells MC1to MCn. The drain select transistors of the cell strings arranged in the row direction are connected to a drain select line extending in the row direction. The drain select transistors of the cell strings CS11′ to CS1m′ of a first row are connected to a first drain select line DSL1. The drain select transistors of the cell strings CS21′ to CS2m′ of a second row are connected to a second drain select line DSL2.

As a result, the memory block BLKb ofFIG. 5has an equivalent circuit similar to the memory block BLKa ofFIG. 4except that the pipe transistor PT is excluded from each cell string.

As another embodiment, even bit lines and odd bit lines may be provided instead of the first to m-th bit lines BL1to BLm. In addition, even-numbered cell strings among the cell strings CS11′ to CS1m′ or CS21′ to CS2m′ arranged in the row direction may be connected to even bit lines, and odd-numbered cell strings among the cell strings CS11′ to CS1m′ or CS21′ to CS2m′ arranged in the row direction may be connected to odd bit lines, respectively.

As an embodiment, at least one of the first to n-th memory cells MC1to MCn may be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce an electric field between the source select transistor SST and the memory cells MC1to MCn. Alternatively, at least one dummy memory cell is provided to reduce an electric field between the drain select transistor DST and the memory cells MC1to MCn. As more dummy memory cells are provided, reliability of an operation for the memory block BLKb is improved, however, the size of the memory block BLKb increases. As less memory cells are provided, the size of the memory block BLKb may be reduced, however, the reliability of the operation for the memory block BLKb may be reduced.

In order to efficiently control at least one dummy memory cell, each of the dummy memory cells may have a required threshold voltage. Before or after an erase operation for the memory block BLKb, program operations for all or a part of the dummy memory cells may be performed. When the erase operation is performed after the program operation is performed, the dummy memory cells may have the required threshold voltage by controlling a voltage applied to the dummy word lines connected to the respective dummy memory cells.

FIG. 6is a diagram illustrating a region division of the memory cell array according to the program operation.

Referring toFIG. 6, the memory cell array110may divide a storage space into a static SLC region, a dynamic SLC region, and a TLC region according to a program method during the program operation.

For example, the static SLC region and the dynamic SLC region are regions programmed in an SLC program method during the program operation, and the TLC region is a region programmed in a TLC program method during the program operation.

In order to improve a program operation speed and stability during the program operation, the memory device receives data to be programmed, and then programs the received data in the static SLC region or the dynamic SLC region in the SLC program method. Thereafter, during the background operation of the memory device, the data stored in the static SLC region or the dynamic SLC region is read, and the read data is programmed in the TLC region.

Therefore, the program operation speed and data reliability may be improved by performing the program operation in the SLC program method during a program operation, and data storage efficiency may be improved by programming the data, which is stored in the static SLC region or the dynamic SLC region, in the TLC region in the TLC program method during the background operation (for example, the garbage collection operation.

The static SLC region is a region fixed as much as a set data capacity of the memory cell array110, and the dynamic SLC region is a region variable according to a capacity of data to be programmed. Accordingly, the dynamic SLC region may be adjacent to the static SLC region or may be disposed between the TLC regions.

FIG. 7is a diagram illustrating the page buffers included in the page buffer group ofFIG. 2.

Each of the plurality of page buffers PB1to PBm may include a main buffer Main Buffer, a cache buffer Cache Buffer, a first map buffer 1st Map Buffer, and a second map buffer 2nd Map Buffer.

The main buffer Main Buffer of each of the page buffers PB1to PBm may be referred to as a main buffer stage123A, the cache buffer Cache Buffer of each of the page buffers PB1to PBm may be referred to as a cache buffer stage123B, the first map buffer 1st Map Buffer of each of the page buffers PB1to PBm may be referred to as a first map buffer stage123C, and the second map buffer 2nd Map Buffer of each of the page buffers PB1to PBm may be referred to as a second map buffer stage123D.

During the program operation, the main buffer stage123A may adjust a potential level of the bit lines BL1to BLm ofFIG. 2according to stored data. During the read operation, the main buffer stage123A may sense a potential or a current amount of the bit lines BL1to BLm and store the sensed data.

During the program operation, the cache buffer stage123B may receive data to be programmed, which is received from the outside of the memory device100(for example, the memory controller200ofFIG. 1), temporarily store the data, and transmit the temporarily stored data to the main buffer stage123A. During the read operation, the cache buffer stage123B may receive the sensed data from the main buffer stage123A and transmit the sensed data to the outside of the memory device100(for example, the memory controller200ofFIG. 1).

During the map data load operation, the first map buffer stage123C stores the second map data among the map data stored in the system block.

During the map data search operation, the second map buffer stage123D stores a logical block address (LBA) received from the outside of the memory device100(for example, the memory controller200ofFIG. 1).

During the map data search operation, each of the page buffers PB1to PBm may search whether the map data corresponding to the LBA stored in the second map buffer stage123D is stored in the first map buffer stage123C.

FIG. 8is a diagram illustrating a load operation of the map data according to an embodiment of the present disclosure.

Referring toFIG. 8, during the load operation of the map data, the map data stored in a system block System Block of the memory device may be read and stored in the map cache buffer222of the memory controller and the page buffer group123of the memory device.

For example, first map data G1among the map data stored in the system block System Block of the memory device may be read by the page buffer group123of the memory device, and the read first map data G1may be transmitted to the map cache buffer222of the memory controller and stored. Second map data G2among the map data stored in the system block System Block may be read by the page buffer group123and may be stored.

For example, the first map data G1may be cold data having a relatively low number of accesses among the map data stored in the system block System Block, and the second map data G2may be hot data having a relatively high number of accesses among the map data stored in the system block System Block.

In another embodiment, the first map data G1may be map data first read by the storage capacity of the map cache buffer222among the map data stored in the system block System Block, and the second map data G2may be map data read by the map data storage capacity of the page buffer group123after the first map data G1is read among the map data stored in the system block System Block.

FIG. 9is a flowchart illustrating the map data search operation according to an embodiment of the present disclosure.

FIG. 10is a diagram illustrating movement of the map data during the map data search operation according to an embodiment of the present disclosure.

FIG. 11is a diagram illustrating signals transmitted between the memory controller and the memory device during the map data search operation according to an embodiment of the present disclosure.

The map data search operation according to an embodiment of the present disclosure is described with reference toFIGS. 1, 2, and 9 to 11as follows.

In step S910, when a command 00h, a system address System ADDR, the logical block address LBA, and address length information Length of the logical block address are received from the memory controller200, the memory device100reads map data corresponding to the system address System ADDR among the map data stored in the system block of the memory cell array110and stores the map data in the map cache buffer222of the memory controller200and the first map buffer stage123C of the page buffer group123. For example, the first map data among the read map data may be stored in the map cache buffer, and the second map data may be stored in the first map buffer stage123C.

In addition, the logical block address LBA is stored in the second map buffer stage123D according to the received logical block address LBA and address length information Length of the logical block address.

In step S920, a command 33h corresponding to the map data search operation is received from the memory controller200, and the control logic130of the memory device100checks whether the map data corresponding to the logical block address LBA stored in the second map buffer stage123D is stored in the first map buffer stage123C, in response to the command 33h.

As a result of the check of step S920described above, when the map data corresponding to the logical block address LBA stored in the second map buffer stage123D is stored in the first map buffer stage123C, “Yes” in step S930, the control logic130of the memory device100sets a status register signal SRBUS<0> to logic high and transmits the status register signal SRBUS<0> to the memory controller200.

The memory controller200may recognize that the logical block address LBA transmitted to the memory device100is matched (corresponds) to the second map data loaded in the first map buffer stage123C, based on the status register signal SRBUS<0> of logic high.

Thereafter, a status check operation may be performed, and a result of the status check operation may be output to the memory controller200as status register information SR.

As a result of the check of step S920described above, when the map data corresponding to the logical block address LBA stored in the second map buffer stage123D is not stored in the first map buffer stage123C, “No” in step S950, the control logic120of the memory device130controls the peripheral circuits120to read other map data stored in the system block (for example, BLK1). Therefore, new second map data is loaded to the first map buffer stage123C. Thereafter, the operation is repeated from step S920described above.

As described above, according to an embodiment of the present disclosure, when the logical block address LBA is received from the memory controller200, the map data corresponding to the received logical block address LBA may be searched among the second map data stored in the first map buffer stage123C of the page buffer group123.

When the memory controller200receives the logical block address LBA from the host300, the memory controller200may perform the map data search operation among the first map data stored in the map cache buffer222of the memory controller200according to the received logical block address LBA, or ay perform the map data search operation among the second map data stored in the first map buffer stage123C by transmitting the logical block address LBA to the memory device. For example, when the logical block address LBA received from the host300corresponds to the cold data, the map data search operation may be performed among the first map data stored in the map cache buffer222of the memory controller200, and when the logical block address LBA received from the host300corresponds to the hot data, the map data search operation may be performed among the second map data stored in the first map buffer stage123C.

FIG. 12is a diagram illustrating movement of data during an update operation of data according to an embodiment of the present disclosure.

FIG. 13is a diagram illustrating signals transmitted between the memory controller and the memory device during the program operation of data according to an embodiment of the present disclosure.

The program operation of data according to an embodiment of the present disclosure is described with reference toFIGS. 1, 2, 12 and 13as follows.

As a result of the map data search operation according toFIG. 9described above, when the status register signal SRBUS<0> of logic high is received from the memory device100, the memory controller200transmits a command 80h corresponding to the program operation, the logical block address LBA, the address length information Length of the logical block address, and the normal data DATA to be programmed, to the memory device100.

The page buffer group123of the memory device100receives and stores the input normal data. For example, the cache buffer stage123B of the page buffer group123receives and temporarily stores the normal data, and transmits the temporarily stored normal data to the main buffer stage123A. At this time, the map data matched with the logical block address LBA may remain among the map data stored in the first map buffer stage123C.

The memory device100performs a flush operation of the normal data stored in the main buffer stage123A, that is, a program operation of storing the normal data, which is stored in the main buffer stage123A, in a selected region of the memory cell array110, in response to the specific command 77h.

The program operation may be performed in the SLC program method. That is, the normal data is programmed in the static SLC region or the dynamic SLC region of the storage space of the memory cell array110in the SLC program method. Accordingly, during the program operation, each of the page buffers PB1to PBm of the page buffer group123may perform the program operation using only one buffer, that is, a main buffer.

Thereafter, a status check operation according to a program operation result may be performed, and a result of the status check operation may be output to the memory controller200as status register information SR.

According to the above-described embodiment of the present disclosure, when the logical block address LBA received from the host300is not matched to the map data stored in the map cache buffer222of the memory controller200and the first map buffer stage123C of the page buffer group, new map data is read and stored in the first map buffer stage123C of the page buffer group. In this case, an operation of loading the new map data to the memory controller200may be skipped after storing the new map data in the page buffer group, thereby improving the operation speed of the storage device50.

FIG. 14is a diagram illustrating movement of the map data during the flush operation of the map data according to an embodiment of the present disclosure.

FIG. 15is a diagram illustrating signals transmitted between the memory controller and the memory device during the flush operation of the map data according to an embodiment of the present disclosure.

The flush operation of the map data according to an embodiment of the present disclosure will be described with reference toFIGS. 1, 2, 14, and 15as follows.

When the update operation of the data ofFIGS. 12 and 13described above is repeatedly performed, the matched map data may be accumulated in the page buffer group123of the memory device100.

For example, a command 80h corresponding to the program operation, the logical block address LBA, and the address length information Length of the logical block address may be continuously transmitted to the memory device100, and thus the memory device100may repeatedly perform the program operation of the normal data several times.

In this case, the matched map data is accumulated in the first map buffer stage123C of the page buffer group123.

When the matched map data is accumulated in the first map buffer stage123C, the memory device100performs the flush operation of the map data stored in the first map buffer stage123C in response to a specific command 78h.

For example, the map data stored in the first map buffer stage123C is temporarily transmitted to the main buffer stage123A and is temporarily stored. The peripheral circuits120of the memory device100performs the flush operation of the map data stored in the main buffer stage123A, that is, the program operation of storing the map data in the selected region of the memory cell array110. At this time, the selected region may be a storage region other than the system block BLK1.

The program operation may be performed in the SLC program method. That is, the map data is programmed in the static SLC region or the dynamic SLC region of the storage space of the memory cell array110in the SLC program method. Accordingly, during the program operation, each of the page buffers PB1to PBm of the page buffer group123may perform the program operation using only one buffer, that is, the main buffer.

Thereafter, a status check operation according to a program operation result may be performed, and a result of the status check operation may be output to the memory controller200as status register information SR.

According to the above-described embodiment of the present disclosure, during the flush operation of the map data, the map data stored in the page buffer group123is programmed in the selected storage region of the memory cell array110. Therefore, an operation of receiving the map data from the memory controller200does not occur, and thus the operation speed of the storage device50may be improved.

FIG. 16is a diagram illustrating another embodiment of the memory controller ofFIG. 1.

Referring toFIG. 16, the memory controller1000is connected to a host Host and the memory device. The memory controller1000is configured to access the memory device in response to the request from the host Host. For example, the memory controller1000is configured to control the write, read, erase, and background operations of the memory device. The memory controller1000is configured to provide an interface between the memory device and the host Host. The memory controller1000is configured to drive firmware for controlling the memory device.

The memory controller1000may include a processor1010, a memory buffer1020, an error correction component (ECC)1030, a host interface1040, a buffer controller1050, a memory interface1060, and a bus1070.

The bus1070may be configured to provide a channel between components of the memory controller1000.

The processor1010may control an overall operation of the memory controller1000and may perform a logical operation. The processor1010may communicate with an external host through the host interface1040and communicate with the memory device through the memory interface1060. In addition, the processor1010may communicate with the memory buffer1020through the buffer controller1050. The processor1010may control an operation of the storage device using the memory buffer1020as an operation memory, a cache memory, or a buffer memory.

The processor1010may perform a function of a flash translation layer (FTL). The processor1010may convert a logical block address (LBA) provided by the host into a physical block address (PBA) through the FTL. The FTL may receive the LBA using the map data and convert the LBA into the PBA. The FTL may perform an address conversion operation using the map data stored in the memory buffer1020.

The processor1010is configured to randomize data received from the host Host. For example, the processor1010may randomize the data received from the host Host using a randomizing seed. The randomized data is provided to the memory device as data to be stored and is programmed to the memory cell array.

The processor1010is configured to de-randomize data received from the memory device during the read operation. For example, the processor1010may de-randomize the data received from the memory device using a de-randomizing seed. The de-randomized data may be output to the host Host.

As an embodiment, the processor1010may perform the randomization and the de-randomization by driving software or firmware.

The memory buffer1020may be used as an operation memory, a cache memory, or a buffer memory of the processor1010. The memory buffer1020may store codes and commands executed by the processor1010. The memory buffer1020may store the map data. The memory buffer1020may store data processed by the processor1010. The memory buffer1020may include a static RAM (SRAM) or a dynamic RAM (DRAM).

The ECC1030may perform error correction. The ECC1030may perform error correction encoding (ECC encoding) based on data to be written to the memory device through memory interface1060. The error correction encoded data may be transferred to the memory device through the memory interface1060. The ECC1030may perform error correction decoding (ECC decoding) on the data received from the memory device through the memory interface1060. For example, the ECC1030may be included in the memory interface1060as a component of the memory interface1060.

The host interface1040is configured to communicate with an external host under control of the processor1010. The host interface1040may be configured to perform communication using at least one of various communication methods such as a universal serial bus (USB), a serial AT attachment (SATA), a serial attached SCSI (SAS), a high speed interchip (HSIC), a small computer system interface (SCSI), a peripheral component interconnection express (PCI express), a nonvolatile memory express (NVMe), a universal flash storage (UFS), a secure digital (SD), a multimedia card (MMC), an embedded MMC (eMMC), a dual in-line memory module (DIMM), a registered DIMM (RDIMM), and a load reduced DIMM (LRDIMM).

The buffer controller1050is configured to control the memory buffer1020under the control of the processor1010.

The memory interface1060is configured to communicate with the memory device under the control of the processor1010. The memory interface1060may communicate a command, an address, and data with the memory device through a channel.

For example, the memory controller1000might not include the memory buffer1020and the buffer controller1050.

For example, the processor1010may control the operation of the memory controller1000using codes. The processor1010may load the codes from a non-volatile memory device (for example, a read only memory) provided inside the memory controller1000. As another example, the processor1010may load the codes from the memory device through the memory interface1060.

For example, the bus1070of the memory controller1000may be divided into a control bus and a data bus. The data bus may be configured to transmit data within the memory controller1000and the control bus may be configured to transmit control information such as a command and an address within the memory controller1000. The data bus and the control bus may be separated from each other and might not interfere with each other or affect each other. The data bus may be connected to the host interface1040, the buffer controller1050, the ECC1030, and the memory interface1060. The control bus may be connected to the host interface1040, the processor1010, the buffer controller1050, the memory buffer1202, and the memory interface1060.

FIG. 17is a block diagram illustrating a memory card system to which the storage device according to an embodiment of the present disclosure is applied.

Referring toFIG. 17, the memory card system2000includes a memory controller2100, a memory device2200, and a connector2300.

The memory controller2100is connected to the memory device2200. The memory controller2100is configured to access the memory device2200. For example, the memory controller2100may be configured to control read, write, erase, and background operations of the memory device2200. The memory controller2100is configured to provide an interface between the memory device2200and a host. The memory controller2100is configured to drive firmware for controlling the memory device2200. The memory controller2100may be implemented identically to the memory controller200described with reference toFIG. 1.

For example, the memory controller2100may include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an ECC.

The memory controller2100may communicate with an external device through the connector2300. The memory controller2100may communicate with an external device (for example, the host) according to a specific communication standard. For example, the memory controller2100is configured to communicate with an external device through at least one of various communication standards such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (MCM), a peripheral component interconnection (PCI), a PCI express (PCI-E), an advanced technology attachment (ATA), a serial-ATA, a parallel-ATA, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), integrated drive electronics (IDE), FireWire, a universal flash storage (UFS), Wi-Fi, Bluetooth, and an NVMe. For example, the connector2300may be defined by at least one of the various communication standards described above.

The memory controller2100and the memory device2200may be integrated into one semiconductor device to configure a memory card. For example, the memory controller2100and the memory device2200may be integrated into one semiconductor device to configure a memory card such as a PC card (personal computer memory card international association (PCMCIA)), a compact flash card (CF), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, or eMMC), an SD card (SD, miniSD, microSD, or SDHC), and a universal flash storage (UFS).

FIG. 18is a block diagram illustrating a solid state drive (SSD) system to which the storage device according to an embodiment of the present disclosure is applied.

Referring toFIG. 18, the SSD system3000includes a host3100and an SSD3200. The SSD3200exchanges a signal SIG with the host3100through a signal connector3001and receives power PWR through a power connector3002. The SSD3200includes an SSD controller3210, a plurality of flash memories3221to322n, an auxiliary power device3230, and a buffer memory3240.

According to an embodiment of the present disclosure, the SSD controller3210may perform the function of the memory controller200described with reference to FIG.

The SSD controller3210may control the plurality of flash memories3221to322nin response to the signal SIG received from the host3100. For example, the signal SIG may be signals based on an interface between the host3100and the SSD3200. For example, the signal SIG may be a signal defined by at least one of interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (MCM), a peripheral component interconnection (PCI), a PCI express (PCI-E), an advanced technology attachment (ATA), a serial-ATA, a parallel-ATA, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), integrated drive electronics (IDE), FireWire, a universal flash storage (UFS), Wi-Fi, Bluetooth, and an NVMe.

The auxiliary power device3230is connected to the host3100through the power connector3002. The auxiliary power device3230may receive the power PWR from the host3100and may charge the power. The auxiliary power device3230may provide power of the SSD3200when power supply from the host3100is not smooth. For example, the auxiliary power device3230may be positioned in the SSD3200or may be positioned outside the SSD3200. For example, the auxiliary power device3230may be positioned on a main board and may provide auxiliary power to the SSD3200.

The buffer memory3240operates as a buffer memory of the SSD3200. For example, the buffer memory3240may temporarily store data received from the host3100or data received from the plurality of flash memories3221to322n, or may temporarily store metadata (for example, a mapping table) of the flash memories3221to322n. The buffer memory3240may include a volatile memory such as a DRAM, an SDRAM, a DDR SDRAM, an LPDDR SDRAM, and a GRAM, or a non-volatile memory such as an FRAM, a ReRAM, an STT-MRAM, and a PRAM.

FIG. 19is a block diagram illustrating a user system to which the storage device according to an embodiment of the present disclosure is applied.

The application processor4100may drive components, an operating system (OS), a user program, or the like included in the user system4000. For example, the application processor4100may include controllers, interfaces, graphics engines, and the like that control the components included in the user system4000. The application processor4100may be provided as a system-on-chip (SoC).

The memory module4200may operate as a main memory, an operation memory, a buffer memory, or a cache memory of the user system4000. The memory module4200may include a volatile random access memory such as a DRAM, an SDRAM, a DDR SDRAM, a DDR2 SDRAM, a DDR3 SDRAM, an LPDDR SDARM, an LPDDR2 SDRAM, and an LPDDR3 SDRAM, or a non-volatile random access memory, such as a PRAM, a ReRAM, an MRAM, and an FRAM. For example, the application processor4100and memory module4200may be packaged based on a package on package (POP) and provided as one semiconductor package.

The network module4300may communicate with external devices. For example, the network module4300may support wireless communication such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution, Wimax, WLAN, UWB, Bluetooth, and Wi-Fi. For example, the network module4300may be included in the application processor4100.

The storage module4400may store data. For example, the storage module4400may store data received from the application processor4100. Alternatively, the storage module4400may transmit data stored in the storage module4400to the application processor4100. For example, the storage module4400may be implemented as a non-volatile semiconductor memory element such as a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash, a NOR flash, and a three-dimensional NAND flash. For example, the storage module4400may be provided as a removable storage device (removable drive), such as a memory card, and an external drive of the user system4000.

For example, the storage module4400may include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices may operate identically to the memory device100described with reference toFIG. 1. The storage module4400may operate identically to the storage device50described with reference toFIG. 1.

Although the detailed description of the present disclosure describes specific embodiments, various modifications may be possible without departing from the scope and technical spirit of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, and should be determined by the equivalents of the claims of the present disclosure as well as the following claims.