Resistance change memory

A resistance change memory includes a memory cell which is connected to a first node, and programmed from a first resistance state to a second resistance state, a first replica cell which is connected to a second node, generates a write voltage for programming from the first resistance state to the second resistance state, and is fixed in the first resistance state, and a first constant-current source connected to the second node, wherein when writing the second resistance state in the memory cell, a voltage of the first node is held equal to that of the second node.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2007-260241, filed Oct. 3, 2007, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a resistance change memory, e.g., a write-system circuit of a resistance change memory.

2. Description of the Related Art

A magnetoresistive element is known as a nonvolatile memory element. The magnetoresistive element includes a free layer and fixed layer as magnetic materials, and a nonmagnetic layer sandwiched between them, and takes different resistance states in accordance with the directions of magnetization in the free layer. A magnetoresistive random access memory (MRAM) is a resistance change memory that stores data by using the difference between the resistance states.

As a data write method, a so-called spin transfer torque writing method different from the conventional so-called magnetic field writing method using a current magnetic field has been proposed (e.g., U.S. Pat. No. 5,695,864).

In spin transfer torque writing, a flow of electrons spin-polarized by the magnetic moment in the fixed layer of the magnetoresistive element is supplied to the free layer. Since the magnetization direction in the free layer changes in accordance with the direction of this electron flow, specific data is written in the magnetoresistive element. Unlike the magnetic field writing method, the spin transfer torque writing method can directly act on the magnetoresistive element. Therefore, no write error occurs in any adjacent memory cell. There is another advantage that the current amount necessary for write reduces as the cell size decreases.

Data is read out by supplying a read current to the magnetoresistive element, converting the resistance value into a current value or voltage value, and comparing the value with a reference value.

The magnetic field writing method and spin transfer torque writing method use the same mechanism to hold data in the magnetoresistive element. Accordingly, a partial peripheral circuit configuration can be used in both MRAMs using the two writing methods. However, since the principles of write are different, the two writing methods require some different peripheral circuits. Therefore, demands have arisen for the implementation of a write-system circuit capable of generating a high-accuracy write voltage suited to the spin transfer torque writing method.

BRIEF SUMMARY OF THE INVENTION

A resistance change memory according to the first aspect of the present invention comprising a memory cell which is connected to a first node, and programmed from a first resistance state to a second resistance state; a first replica cell which is connected to a second node, generates a write voltage for programming from the first resistance state to the second resistance state, and is fixed in the first resistance state; and a first constant-current source connected to the second node, wherein when writing the second resistance state in the memory cell, a voltage of the first node is held equal to that of the second node.

A resistance change memory according to the second aspect of the present invention comprising a memory cell which is connected to a first node, and programmed from a first resistance state to a second resistance state; a plurality of first replica cells which are connected to a second node, generate a write voltage for programming from the first resistance state to the second resistance state, and are connected in series with each other; and a constant-current source connected to the second node, wherein when writing the second resistance state in the memory cell, a voltage of the first node is held equal to that of the second node.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be explained below with reference to the accompanying drawing. In the following explanation, the same reference numerals denote the same parts throughout the drawing.

[1] First Embodiment

The first embodiment is an example in which a write circuit includes a replica cell for generating a voltage for programming a memory cell, and the voltage of a node connected to the memory cell is made equal to that of a node connected to the replica cell and a current source during data write.

[1-1] Main Circuit Configuration

FIG. 1is a circuit diagram showing the main circuit configuration of a magnetoresistive random access memory according to the first embodiment of the present invention. The main circuit configuration of the magnetoresistive random access memory according to the first embodiment will be explained below.

As shown inFIG. 1, a memory cell11includes a magnetoresistive element1and selection transistor2connected in series. The selection transistor2is, e.g., an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The magnetoresistive element1is, e.g., an MTJ (Magnetic Tunnel Junction) element. The magnetoresistive element1is configured to take a low-resistance state or high-resistance state when a flow of spin-polarized electrons (a spin-polarized electric current) is supplied from one terminal to the other or vice versa. The magnetoresistive element1can store binary data by making one of the two resistance states correspond to data “0” and the other correspond to data “1”. Details of the magnetoresistive element1will be described later.

A memory cell array MCA is formed by arranging the memory cells11in, e.g., a matrix. The magnetoresistive random access memory is designed to be able to supply, to the magnetoresistive element1of an arbitrary memory cell11, an electric current flowing in a direction to set the magnetoresistive element1in the low-resistance state, and an electric current flowing in a direction to set the magnetoresistive element1in the high-resistance state. Various configurations can supply such electric currents, so the present invention is not limited to any configuration. An example will be explained below.

In the memory cell array MCA as shown inFIG. 1, word lines12run in the row direction, and bit lines21and24run in the column direction. In the periphery of the memory cell array MCA, a row decoder13and peripheral circuits23and26are arranged.

The gate electrodes of the selection transistors2in the same row (or column) are connected to the same word line12. The word line12in each row is connected to the row decoder13. The row decoder13specifies a word line12by using an address signal supplied from outside the magnetoresistive random access memory. When the selected word line12is activated, the selection transistor2connected to the selected word line12is turned on.

One terminal (e.g., the right terminal) of each of a plurality of memory cells11in the same column (or row) is connected to the bit line21. Each bit line21is connected to the peripheral circuit23via a switching circuit22such as a transistor. The switching circuit22is turned on or off in accordance with a signal corresponding to an address signal that specifies the memory cell11as an object of write or read. When the switching circuit22connected to the bit line21connected to the memory cell11as the object of write or read is turned on, the peripheral circuit23is electrically connected to the memory cell11as the object.

The other terminal (e.g., the left terminal) of each of a plurality of memory cells in the same column (or row) is connected to the bit line24. Each bit line24is connected to the peripheral circuit26via a switching circuit25such as a transistor. The switching circuit25is turned on or off in accordance with a signal corresponding to an address signal. When the switching circuit25connected to the bit line24connected to the memory cell11as an object is turned on, the peripheral circuit26is electrically connected to the memory cell11as the object of write or read.

The peripheral circuit23includes, e.g., a write circuit31and read circuit32. The peripheral circuit26includes, e.g., a write circuit33.

The write circuits31and33each include a current source/sink circuit. This current source/sink circuit has a function of supplying an electric current to the connected bit line21or24, and a function of extracting an electric current from the bit line21or24. More specifically, when writing data in a certain memory cell11, the selection transistor2connected to the memory cell11is turned on, and the switching circuits22and25connected to the bit lines21and24of a memory cell string including the memory cell11are turned on. One of the current source/sink circuits (write circuits31and33) which corresponds to write data functions as a current source circuit, and the other functions as a current sink circuit. Consequently, a write current flows between the write circuits31and33via the switching circuit22, bit line21, memory cell11, bit line24, and switching circuit25. The circuit functioning as a current source circuit includes a write voltage generator40. Details of the write voltage generator40will be described later.

The read circuit32has at least a supply circuit for supplying a read current and a sense amplifier. In a read operation, the supply circuit supplies, to the magnetoresistive element1, an electric current having a value that allows the magnetoresistive element1to detect data stored in accordance with the magnetization configuration. The sense amplifier determines the resistance state by supplying an electric current to the magnetoresistive element1.

Note that in the example shown inFIG. 1, the write circuits31and33are arranged in the two ends of the memory cell array MCA. However, the write circuits31and33can be implemented in any form as long as bidirectional electric currents can be supplied to the memory cell11as described above. For example, both the write circuits31and33can also be arranged on the upper or lower side of the memory cell array MCA. In this arrangement, the switching circuits22and25are also arranged on the upper or lower side of the memory cell array MCA, i.e., on the same side as the write circuits31and33.

Note also that in the example shown inFIG. 1, the read circuit32is connected to the upper end of the bit line21, but the connection form is not limited to this. The read circuit32can be implemented in any form as long as the resistance state can be determined by supplying the read current to the magnetoresistive element1. For example, the read circuit32may also be connected to the lower end of the bit line21, or to the bit line24. Furthermore, in the example shown inFIG. 1, the read circuit32is positioned such that the read current flows from the selection transistor2to the magnetoresistive element1. However, the read circuit32may also be positioned such that the read current flows from the magnetoresistive element1to the selection transistor2.

[1-2] Write Voltage Generator

When writing data in the memory cell11in this embodiment, a write current Iwrite is supplied to the memory cell11in a direction corresponding to the data to be written. For this purpose, a constant write voltage Vwrite is applied to the memory cell11. The write voltage generator40as shown inFIGS. 2 and 3generates the write voltage Vwrite. The write voltage generator40is included in each of the write circuits31and33shown inFIG. 1.

The write voltage generator40converts a base current Ibase having the same value as that of the write current Iwrite necessary for write into a voltage by using a load resistance. To supply a desired write current Iwrite to the memory cell11, the load resistance is made equal to the resistance of the memory cell11. In addition, a replica cell50as a replica of the memory cell11is formed as the load resistance in order to compensate for resistance fluctuations with respect to the manufacture and temperature of the memory cell11.

Practical examples of the write voltage generator40as described above will be explained below with reference toFIGS. 2 and 3.

Practical Example 1

As shown inFIG. 2, the write voltage generator40of practical example 1 comprises the replica cell50, switching circuits51and52, a constant-current source61, and an operational amplifier62.

The replica cell50has the same arrangement as that of the memory cell11. That is, the replica cell50includes a magnetoresistive element1and selection transistor2connected in series shown inFIG. 1. The selection transistor2is, e.g., an n-type MOSFET. The magnetoresistive element1is, e.g., an MTJ element. The replica cell50is formed simultaneously with the memory cell11in the same step by using the same materials, so as to have the same shape and structure as those of the memory cell11. In principle, therefore, the magnetoresistive element1of the memory cell11and the magnetoresistive element1of the replica cell50have the same characteristics. That is, when the difference between the characteristics caused by, e.g., variations in the manufacturing process is not taken into consideration, the two magnetoresistive elements1have the same resistance value in the same resistance state (the low- or high-resistance state). Even when the variations in characteristics of the two elements are taken into account, practically the same resistance value appears. Also, magnetization in the magnetoresistive element1of the replica cell50is set in the low- or high-resistance state in accordance with data written in the memory cell11. Details of the replica cell50will be described later.

The switching circuits51and52are transistors or the like. The switching circuit51has one terminal connected to one terminal of the replica cell50, and the other terminal connected to the constant-current source61. The switching circuit52has one terminal connected to the other terminal of the replica cell50, and the other terminal connected to a ground terminal.

The constant-current source61supplies the base current Ibase having the same value as that of the write current Iwrite flowing through the memory cell11. Temperature compensation may also be performed on the base current Ibase in order to optimize the write current Iwrite.

A positive input terminal (+) of the operational amplifier62is connected to a connection node n2between the constant-current source61and switching circuit51. An inverting input terminal (−) of the operational amplifier62is connected to a node n1of its own output terminal. The node n1is connected to one terminal of the switching circuit22connected to the memory cell11.

In the write voltage generator40of practical example 1 as described above, the voltage of the node n1connected to the memory cell11is held equal to that of the node n2connected to the constant-current source61when writing data in the memory cell11.

Practical Example 2

As shown inFIG. 3, the write voltage generator40of practical example 2 further comprises a p-type transistor (e.g., a MOSFET)63, an n-type transistor (e.g., a MOSFET)64, and an operational amplifier65in addition to the arrangement of practical example 1.

One end of the current path of the transistor63is connected to a power supply terminal. The other end of the current path of the transistor63is connected to its own gate terminal, and a connection node n4is connected to one end of the current path of the transistor64. The other end of the current path of the transistor64is connected to the switching circuit22.

A node n1is connected to a positive input terminal (+) of the operational amplifier65, and applies the write voltage Vwrite. An inverting input terminal (−) of the operational amplifier65is connected to a connection node n3between the transistor64and switching circuit22. The output terminal of the operational amplifier65is connected to the gate terminal of the transistor64.

In the write voltage generator40of practical example 2 as described above, the voltages of the nodes n1and n3connected to the memory cell11are held equal to that of the node n2connected to the constant-current source61when writing data in the memory cell11.

Note that as long as the voltage to be applied to the memory cell11is held equal to that of the node n2, it is also possible to omit the operational amplifier62and the like shown inFIGS. 2 and 3and directly connect the node n2to the switching circuit22as shown inFIG. 4. However, when the operation amplifier62, for example, is formed, the operational amplifier62charges the node n1to make its potential equal to that of the node n2. This results in the advantage that the change in potential of the node n2can be transmitted to the potential of the node n1within a time shorter than that when there is no operational amplifier62.

[1-3] Replica Cell

In this embodiment, the base current Ibase is converted into the write voltage Vwrite by using the replica cell50as a load resistance in order to generate the write voltage Iwrite required to write data in the memory cell11. To supply the desired write current Iwrite to the memory cell11, the resistance of the replica cell50is preferably made equal to that of the memory cell11. An example of the replica cell50in the write operation of this embodiment will be explained in detail below with reference toFIG. 5.

When writing 1 in the memory cell11, the memory cell11can take state 0 or state 1. Programming is necessary only when the memory cell11is in state 0. When writing 1, therefore, it is only necessary to assume the case where the memory cell11in state 0 is changed to state 1.

Accordingly, when generating a write voltage for 1 write, the replica cell50of the write voltage generator40is set in “state 0”, i.e., the same state as that of the memory cell11requiring programming. To avoid a write error in the replica cell50, the direction of an electric current to be supplied to the replica cell50is desirably “a 0-write direction”. That is, an electric current is preferably supplied to the magnetoresistive element1of the replica cell50in a direction from a free layer103to a fixed layer101.

When writing 0 in the memory cell11, the memory cell11can take state 0 or state 1. Programming is necessary only when the memory cell11is in state 1. When writing 0, therefore, it is only necessary to assume the case where the memory cell11in state 1 is changed to state 0.

Accordingly, when generating a write voltage for 0 write, the replica cell50of the write voltage generator40is set in “state 1”, i.e., the same state as that of the memory cell11requiring programming. To avoid a write error in the replica cell50, the direction of an electric current to be supplied to the replica cell50is desirably “a 1-write direction”. That is, an electric current is preferably supplied to the magnetoresistive element1of the replica cell50in a direction from the fixed layer101to the free layer103.

[1-4] Write Operation

Referring toFIGS. 6 and 7, a 0-write voltage generator40_0for generating a O-write voltage and a 1-write voltage generator40_1for generating a 1-write voltage are arranged on the two sides of the memory cell array MCA. Switching circuits71and72such as transistors are respectively arranged between the write voltage generator40_0and switching circuit22and between the write voltage generator40_1and switching circuit25. The switching circuit71can be connected to a node n1of the O-write voltage generator40_0or to the ground terminal. The switching circuit72can be connected to a node n1of the 1-write voltage generator40_1or to the ground terminal.

The write operation will be explained below with reference toFIGS. 6 and 7.

As shown inFIG. 6, when writing 0 in the memory cell11, an electric current is supplied to the memory cell11in the 0-write direction (rightward in the drawing surface). To connect the 0-write voltage generator40_0on the left side to the memory cell11, the switching circuit71is connected to the node n1of the 0-write voltage generator40_0, and the switching circuit72is connected to the ground terminal. Accordingly, a write voltage Vwrite_0for 0 write generated by the 0-write voltage generator40_0is used to write 0 in the memory cell11.

The write voltage Vwrite_0for 0 write is generated by converting a base current Ibase_0having the same value as that of an electric current required for write into a voltage by using a replica cell50_0as a load resistance. More specifically, an electric current is supplied in a direction to write 1 (a direction from the fixed layer to the free layer) to the replica cell50_0set in state 1 by the base current Ibase_0of a constant-current source61_0. Consequently, the write voltage Vwrite_0is generated in a connection node n2. Since the write voltage Vwrite_0is held at the same value in the node n1as well, the write voltage Vwrite_0having a desired value can be applied to the memory cell11. Accordingly, the write current having the desired value flows through the memory cell11, and 0 is written in it.

Note that in this case, one terminal of the switching circuit72is connected to the ground terminal, so the 1-write voltage generator40_1is not connected to the memory cell11.

As shown inFIG. 7, when writing 1 in the memory cell11, an electric current is supplied to the memory cell11in the 1-write direction (leftward in the drawing surface). To connect the 1-write voltage generator40_1on the right side to the memory cell11, the switching circuit71is connected to the ground terminal, and the switching circuit72is connected to the node n1of the 1-write voltage generator40_1. Accordingly, a write voltage Vwrite_1for 1 write generated by the 1-write voltage generator40_1is used to write 1 in the memory cell11.

The write voltage Vwrite_1for 1 write is generated by converting a base current Ibase_1having the same value as that of an electric current required for write into a voltage by using a replica cell50_1as a load resistance. More specifically, an electric current is supplied in a direction to write 0 (a direction from the free layer to the fixed layer) to the replica cell50_1set in state 0 by the base current Ibase_1of a constant-current source61_1. Consequently, the write voltage Vwrite_1is generated in a connection node n2. Since the write voltage Vwrite_1is held at the same value in the node n1as well, the write voltage Vwrite_1having a desired value can be applied to the memory cell11. Accordingly, the write current having the desired value flows through the memory cell11, and1is written in it.

Note that in this case, one terminal of the switching circuit71is connected to the ground terminal, so the O-write voltage generator40_0is not connected to the memory cell11.

Referring toFIGS. 6 and 7, the example shown inFIG. 2is used as each of the write voltage generators40_0and40_1, but the arrangement is not limited to this. The write voltage generator40shown inFIG. 3or4may also be used. Furthermore, inFIGS. 6 and 7, one of the write voltage generators40_0and40_1which generates a higher one of the 1-write voltage and 0-write voltage may also be used for both 1 write and 0 write.

[1-5] Read Operation

The read operation of this embodiment uses the magnetoresistive effect.

The transistor2of a selected cell is turned on by selecting the bit lines21and24and word line12corresponding to the selected cell. Then, a read current is supplied to the magnetoresistive element1of the selected cell. The resistance value of the magnetoresistive element1is read out on the basis of this read current, and whether the recording state is “0” or “1” is determined by an amplifying operation via a sense amplifier.

Note that in the read operation, a current value can be read out by applying a constant voltage, or a voltage value can be read out by supplying a constant current.

The magnetoresistive element1applicable to the memory cell11and replica cell50of this embodiment will be explained below with reference toFIG. 8.

The magnetoresistive element1can take two steady states in accordance with the spin transfer torque magnetization reversing method. More specifically, as shown inFIG. 8, the magnetoresistive element1has at least the fixed layer101, the free layer (recording layer)103, and an interlayer102formed between the fixed layer101and free layer103. It is also possible to form an upper electrode105on that surface of the free layer103which is away from the interlayer102, and a lower electrode106on that surface of an antiferromagnetic layer104which is away from the fixed layer101.

The fixed layer101is made of a ferromagnetic material, and has a fixed magnetization direction. For example, magnetization in the fixed layer101can be fixed by forming the antiferromagnetic layer104on that surface of the fixed layer101which is away from the interlayer102.

The free layer103is made of a ferromagnetic material. No such fixing mechanism as that for the fixed layer101is formed for the magnetization direction in the free layer103. Therefore, the magnetization direction in the free layer103is variable.

The interlayer102is made of a nonmagnetic material. The interlayer102desirably has a film thickness that spaces the fixed layer101and free layer103apart from each other to such an extent that the direct interaction acting between the fixed layer101and free layer103is negligible. At the same time, the film thickness of the interlayer102is desirably smaller than the spin diffusion length because when a write current is supplied to the magnetoresistive element1, conduction electrons transmitted through the fixed layer101must not reverse the electron spin direction before reaching the free layer103. As the interlayer102, it is possible to use, e.g., a nonmagnetic metal, nonmagnetic semiconductor, or insulating film.

Note that each of the fixed layer101and free layer103is not limited to a single layer as shown inFIG. 8. For example, at least one of the fixed layer101and free layer103may also have a stacked structure including a plurality of ferromagnetic layers.

In addition, at least one of the fixed layer101and free layer103may also have an antiferromagnetic coupling structure which includes three layers, i.e., a first ferromagnetic layer/nonmagnetic layer/second ferromagnetic layer, and in which the first and second ferromagnetic layers are magnetically coupled (by interlayer exchange coupling) so that their magnetization directions are antiparallel, or a ferromagnetic coupling structure in which the first and second ferromagnetic layers are magnetically coupled (by interlayer exchange coupling) so that their magnetization directions are parallel.

A double-junction structure may also be used. A magnetoresistive element having the double-junction structure includes a first fixed layer, a second fixed layer, a free layer, a first interlayer formed between the first fixed layer and free layer, and a second interlayer formed between the second fixed layer and free layer. Compared to a single-junction structure, the double-junction structure has the advantage that it is possible to further increase the ratio of a resistance value in the low-resistance state to that in the high-resistance state, i.e., a so-called MR ratio (Magneto-Resistance ratio).

Next, practical examples of the materials of the magnetoresistive element1will be explained.

As the ferromagnetic material of the fixed layer101and free layer103, it is possible to use, e.g., Co, Fe, Ni, or an alloy containing any of these metals.

When using a nonmagnetic metal as the interlayer102, it is possible to use any of Au, Cu, Cr, Zn, Ga, Nb, Mo, Ru, Pd, Ag, Hf, Ta, W, Pt, and Bi, or an alloy containing at least one of these metals. Note that when allowing the interlayer102to function as a tunnel barrier layer, it is possible to use an insulating oxide such as Al2O3, SiO2, MgO, or AlN.

As the material of the antiferromagnetic layer104, it is possible to use, e.g., Fe—Mn, Pt—Mn, Pt—Cr—Mn, Ni—Mn, Pd—Mn, NiO, Fe2O3, or a magnetic semiconductor.

The parallel and antiparallel magnetization configurations of the magnetoresistive element1resulting from spin transfer torque writing will be explained below with reference toFIG. 8.

When reversing the magnetization direction in the free layer103which is antiparallel to that in the fixed layer101, thereby making the former parallel to the latter, an electron flow is supplied from the fixed layer101to the free layer103. That is, a write current is supplied from the free layer103to the fixed layer101. Generally, many electrons in an electron flow passing through a certain magnetic material have spins parallel to the magnetization direction in this magnetic material. Therefore, many electrons in the electron flow having passed through the fixed layer101have spins parallel to the magnetization direction in the fixed layer101. This electron flow mainly contributes to the torque acting on magnetization in the free layer103. Not that the rest of electrons in the electron flow have spins antiparallel to the magnetization direction in the fixed layer101. Consequently, the magnetization directions in the fixed layer101and free layer103take the parallel state (low-resistance state). This case is defined as state “0” in this embodiment.

On the other hand, when reversing the magnetization direction in the free layer103which is parallel to the magnetization direction in the fixed layer101, thereby making the former antiparallel to the latter, an electron flow is supplied from the free layer103to the fixed layer101. That is, a write current is supplied from the fixed layer101to the free layer103. This electron flow is transmitted through the free layer103, and many electrons having spins antiparallel to the magnetization direction in the fixed layer101are reflected by the fixed layer101, and return to the free layer103. These electrons having spins antiparallel to the magnetization direction in the fixed layer101flow into the free layer103again, and mainly contribute to the torque acting on magnetization in the free layer103. Note that some electrons transmitted through the free layer103and having spins antiparallel to the magnetization direction in the fixed layer101are transmitted through the fixed layer101, although the number of these electrons is small. Consequently, the magnetization directions in the fixed layer101and free layer103take the antiparallel state (high-resistance state). This case is defined as state “1” in this embodiment.

In the spin transfer torque writing described above, the resistance state of the magnetoresistive element1is made to correspond to the logic level to be stored such that the case where the magnetization directions in the fixed layer101and free layer103take the parallel state (low-resistance state) is regarded as state “0”, and the case where the magnetization directions in the fixed layer101and free layer103take the antiparallel state (high-resistance state) is regarded as state “1”. However, it is of course also possible to make the parallel and antiparallel states respectively correspond to states “1” and “0”.

Referring toFIG. 8, the magnetization directions in the fixed layer101and free layer103of the magnetoresistive element1are parallel to the film surfaces, thereby forming an in-plane magnetization type element (parallel magnetization type element). However, the magnetoresistive element1may also be a perpendicular magnetization type element in which these magnetization directions are perpendicular to the film surfaces. Note that the perpendicular magnetization type element is suitable for micropatterning because the element shape need not be controlled in order to determine the magnetization direction unlike in the in-plane magnetization type element.

[1-7] Cell Structure

An example of the structure of the memory cell11and replica cell50will be explained below with reference toFIG. 9.

As shown inFIG. 9, the memory cell11and replica cell50have the same structure and shape. For example, the magnetoresistive elements1of the memory cell11and replica cell50are made of the same materials, and have, e.g., the same sectional shape, planar shape, volume, and film configuration. Also, the transistors2of the memory cell11and replica cell50are made of the same materials and have the same performance and the like.

A practical structure is as follows. A gate electrode G is formed on a semiconductor substrate81, and source/drain diffusion layers82aand82bare formed in the semiconductor substrate81on the two sides of the gate electrode G. The gate electrode G is connected to the word line12. Thus, the transistor2is formed on the semiconductor substrate81. The source/drain diffusion layer82ais connected to the bit line21via a contact83. The source/drain diffusion layer82bis connected to the magnetoresistive element1via a contact84. The free layer103of the magnetoresistive element1is connected to the bit line24. The bit lines21and24run parallel to each other.

In the first embodiment described above, the write voltage generator40for data write comprises, as a load resistance, the replica call50that is a replica of the memory cell11, in order to supply the desired write current Iwrite to the memory cell11. The memory cell11is connected to the node n1connected to the write circuit31, and the replica cell50is connected to the node n2connected to the constant-current source61. When writing data in the memory cell11in this circuit configuration, the voltages of the two nodes n1and n2are held equal to each other. This makes it possible to generate a high-accuracy write voltage Vwrite for supplying the defined write current Iwrite to the memory cell11, regardless of the resistance fluctuation with respect to the manufacture or temperature of the memory cell11. Note that the resistance fluctuation herein mentioned means the average value, and does not mean the variations of the individual memory cells.

[2] Second Embodiment

The second embodiment is an example of a write voltage generator having an arrangement different from that of the first embodiment.

[2-1] Write Voltage Generator

As shown inFIGS. 10 to 12, a write voltage generator40of the second embodiment has, as a load resistance, a replica cell group53including a plurality of replica cells50a,50b, and50cconnected in series. The replica cell group53has one terminal connected to a switching circuit51, and the other terminal connected to a switching circuit52.

In an example shown inFIG. 10, the write voltage generator40comprises the replica cell group53, the switching circuits51and52, a constant-current source61, and an operational amplifier62. In an example shown inFIG. 11, the write voltage generator40further comprises a p-type transistor (e.g., a MOSFET)63, an n-type transistor (e.g., a MOSFET)64, and an operational amplifier65in addition to the arrangement shown inFIG. 10. In an example shown inFIG. 12, the operational amplifier62and the like shown inFIGS. 10 and 11are omitted, and a node n2and switching circuit22are directly connected. Practical connection relationships shown inFIGS. 10 to 12are the same as those shown inFIGS. 2 to 4, so a repetitive explanation will be omitted.

In the second embodiment as described above, the constant-current source61generates a base current Ibase in the node n2, and the series circuit of the three replica cells50a,50b, and50cis connected to the node n2. When writing data, the voltage of the node n2is applied, via the operational amplifier62as a unity gain buffer, to a node n1connected to a memory cell11. Note that in order to equalize the resistance of the current path of the memory cell11and that of the current path of the replica cell group53as much as possible, the dummy switching circuit51is desirably inserted in the current path of the replica cell group53.

In this embodiment, the base current Ibase generated by the constant-current source61is set at a value ⅓ that of a write current Iwrite sufficient to rewrite stored data of the memory cell11. Since the three replica cells50a,50b, and50ceach having a resistance R_rep are connected in series, a voltage Vn2of the node n2is given by
Vn2=3R_rep×⅓Ibase
Vn2=R_rep×Ibase=Vwrite  (1)

Since a voltage Vn1of the node n1is equal to the voltage Vn2of the node n2, therefore, if the resistance value R_rep of each of the replica cells50a,50b, and50cand a resistance value R_cell of the memory cell11are equal, the write current Iwrite having a desired value flows through the memory cell11.

[2-2] Replica Cell

In the second embodiment, as in the first embodiment, the resistance of each of the replica cells50a,50b, and50cis desirably made equal to that of the memory cell11, in order to supply the desired write current Iwrite to the memory cell11.

More specifically, when generating a write voltage for 1 write in order to write 1 in the memory cell11, all the replica cells50a,50b, and50care set in “state 0” that is the same state as that of the memory cell11requiring programming. To avoid write errors in the replica cells50a,50b, and50c, the direction of an electric current flowing through the replica cells50a,50b, and50cis preferably set in “a 0-write direction”. That is, an electric current flowing from a free layer103to a fixed layer101is preferably supplied to a magnetoresistive element1of each of the replica cells50a,50b, and50c.

On the other hand, when generating a write voltage for 0 write in order to write 0 in the memory cell11, all the replica cells50a,50b, and50care set in “state 1” that is the same state as that of the memory cell11requiring programming. To avoid write errors in the replica cells50a,50b, and50c, the direction of an electric current flowing through the replica cells50a,50b, and50cis preferably set in “a 1-write direction”. That is, an electric current flowing from the fixed layer101to the free layer103is preferably supplied to the magnetoresistive element1of each of the replica cells50a,50b, and50c.

Note that the rest of the arrangement of the second embodiment may also be the same as that of the first embodiment. That is, in the second embodiment, the main circuit configuration of a magnetoresistive random access memory may also be the same as that shown inFIG. 1. In addition, practical write of the second embodiment may also be performed by arranging the write voltage generators40on the two sides of the memory cell11as shown inFIGS. 6 and 7. Furthermore, each of the replica cells50a,50b, and50cof the second embodiment may also have the same structure and shape as those of the memory cell11as in the first embodiment.

In the second embodiment described above, the voltages of the two nodes n1and n2are held equal to each other when writing data in the memory cell11, as in the first embodiment. This makes it possible to generate a high-accuracy write voltage Vwrite for supplying the defined write current Iwrite to the memory cell11, regardless of the resistance fluctuation with respect to the manufacture or temperature of the memory cell11.

Also, in the second embodiment, the series circuit of the three replica cells50a,50b, and50cis formed as a load resistance of the write voltage generator40. Accordingly, the base current Ibase flowing through the replica calls50a,50b, and50cis ⅓ the write current Iwrite, and the voltage applied to the replica cells50a,50b, and50cis also ⅓ the write voltage Vwrite. This makes it possible to reduce the stress to the replica cells50a,50b, and50c, and suppress deterioration of the magnetoresistive element1forming each of the replica cells50a,50b, and50c.

Note that the three replica cells50a,50b, and50care connected in series in this embodiment, but N replica cells may also be connected in series. N is a natural number of 2 or more. In this case, the same effects as above can be obtained by making the base current Ibase 1/N the write current Iwrite.

The present invention is not limited to the above embodiments, and can be variously modified without departing from the spirit and scope of the invention when practiced. For example, each embodiment is explained by taking a magnetoresistive random access memory using a magnetoresistive element as an example. However, the present invention is also applicable to resistance change memories such as a PRAM (Phase-change Random Access Memory) using a chalcogenide element, and an ReRAM (Resistance Random Access Memory) using a transition metal oxide element.