Access network for address mapping in non-volatile memories

Systems and methods for determining a physical block address (PBA) of a non-volatile memory (NVM) to enable a data access of a corresponding logical block address (LBA) are described. One such method includes generating a first physical block address (PBA) candidate from a LBA using a first function; generating a second physical block address (PBA) candidate from the LBA using a second function; and selecting either the first PBA candidate or the second PBA candidate for the data access based on information related to a background swap of data stored at the first PBA candidate and a background swap of data stored at the second PBA candidate.

FIELD

Aspects of the disclosure relate generally to mapping memory addresses, and more specifically, to address mapping in non-volatile memories.

BACKGROUND

In a variety of consumer electronics, solid state drives incorporating non-volatile memories (NVMs) are frequently replacing or supplementing conventional rotating hard disk drives for mass storage. These non-volatile memories may include one or more flash memory devices, the flash memory devices may be logically divided into blocks, and each of the blocks may be further logically divided into addressable pages. These addressable pages may be any of a variety of sizes (e.g., 512 Bytes, 1 Kilobytes, 2 Kilobytes, 4 Kilobytes), which may or may not match the logical block address sizes used by a host computing device.

During a write operation, data may be written to the individual addressable pages in a block of a flash memory device. However, in order to erase or rewrite a page, an entire block must typically be erased. Of course, different blocks in each flash memory device may be erased more or less frequently depending upon the data stored therein. Thus, since the lifetime of storage cells of a flash memory device correlates with the number of erase cycles, many solid state drives perform wear-leveling operations (both static and dynamic) in order to spread erasures more evenly over all of the blocks of a flash memory device.

To make sure that all of the physical pages in a NVM (e.g., flash memory device) are used uniformly, the usual practice is to maintain a table for the frequency of use for all of the logical pages and periodically map the most frequently accessed logical address to physical lines. However, these table indirection based methods incur significant overhead in table size. For instance to use a table approach for a 2 terabyte (TB) storage device with 512 byte pages, a 137 gigabyte (GB) table would be needed. This is clearly not practical.

SUMMARY

In one aspect, the disclosure provides a method for determining a physical block address (PBA) of a non-volatile memory (NVM) to enable a data access of a corresponding logical block address (LBA), the method comprising: generating a first physical block address (PBA) candidate from a LBA using a first function; generating a second physical block address (PBA) candidate from the LBA using a second function; and selecting either the first PBA candidate or the second PBA candidate for the data access based on information related to a background swap of data stored at the first PBA candidate and a background swap of data stored at the second PBA candidate.

In another aspect, the disclosure provides a system for determining a physical block address (PBA) of a non-volatile memory (NVM) to enable a data access of a corresponding logical block address (LBA), the system comprising: a first network configured to generate a first PBA candidate from a LBA using a first function; a second network configured to generate a second PBA candidate from the LBA using a second function; and a select logic configured to select either the first PBA candidate or the second PBA candidate for the data access based on information related to a background swap of data stored at the first PBA candidate and a background swap of data stored at the second PBA candidate.

Another aspect of the disclosure provides a system for determining a physical block address (PBA) of a non-volatile memory (NVM) to enable a data access of a corresponding logical block address (LBA), the system comprising: means for generating a first PBA candidate from a LBA using a first function; means for generating a second PBA candidate from the LBA using a second function; and means for selecting either the first PBA candidate or the second PBA candidate for the data access based on information related to a background swap of data stored at the first PBA candidate and a background swap of data stored at the second PBA candidate.

DETAILED DESCRIPTION

Referring now to the drawings, systems and methods for mapping logical block addresses (LBAs) to physical block addresses (PBAs) for non-volatile memories (NVMs) are illustrated. One such method involves determining a physical block address (PBA) of a non-volatile memory (NVM) to enable a data access of a corresponding logical block address (LBA), and includes (1) generating a first physical block address (PBA) candidate from a LBA using a first function, (2) generating a second physical block address (PBA) candidate from the LBA using a second function, and (3) selecting either the first PBA candidate or the second PBA candidate for the data access based on information related to a background swap of data stored at the first PBA candidate and a background swap of data stored at the second PBA candidate. In one example, the first function and/or the second function may include a function performed by at least one of a multi-stage interconnection network or a block cipher. In another example, the first function and/or the second function may further include an exclusive OR function.

Embodiments of these mapping systems and the corresponding methods may involve substantially less hardware, and more specifically, less storage to manage mapping LBAs to PBAs than say the indirection tables discussed above. Moreover, these mapping systems and methods may work well in conjunction with random address mapping in non-volatile memories using local and global interleaving as are illustrated inFIGS. 15-25and discussed in detail below.

FIG. 1is a block diagram of a solid state device (SSD) that can perform local address mapping in accordance with one embodiment of the disclosure. The system100includes a host102and a SSD storage device104coupled to the host102. The host102provides commands to the SSD storage device104for transferring data between the host102and the SSD storage device104. For example, the host102may provide a write command to the SSD storage device104for writing data to the SSD storage device104or read command to the SSD storage device104for reading data from the SSD storage device104. The host102may be any system or device having a need for data storage or retrieval and a compatible interface for communicating with the SSD storage device104. For example, the host102may a computing device, a personal computer, a portable computer, or workstation, a server, a personal digital assistant, a digital camera, a digital phone, or the like.

The SSD storage device104includes a host interface106, a controller108, a memory110, and a non-volatile memory112. The host interface106is coupled to the controller108and facilitates communication between the host102and the controller108. Additionally, the controller108is coupled to the memory110and the non-volatile memory112. The host interface106may be any type of communication interface, such as an Integrated Drive Electronics (IDE) interface, a Universal Serial Bus (USB) interface, a Serial Peripheral (SP) interface, an Advanced Technology Attachment (ATA) interface, a Small Computer System Interface (SCSI), an IEEE 1394 (Firewire) interface, or the like. In some embodiments, the host102includes the SSD storage device104. In other embodiments, the SSD storage device104is remote with respect to the host102or is contained in a remote computing system coupled in communication with the host102. For example, the host102may communicate with the SSD storage device104through a wireless communication link.

The controller108controls operation of the SSD storage device104. In various embodiments, the controller108receives commands from the host102through the host interface106and performs the commands to transfer data between the host102and the non-volatile memory112. The controller108may include any type of processing device, such as a microprocessor, a microcontroller, an embedded controller, a logic circuit, software, firmware, or the like, for controlling operation of the SSD storage device104.

In some embodiments, some or all of the functions described herein as being performed by the controller108may instead be performed by another element of the SSD storage device104. For example, the SSD storage device104may include a microprocessor, a microcontroller, an embedded controller, a logic circuit, software, firmware, or any kind of processing device, for performing one or more of the functions described herein as being performed by the controller108. In some embodiments, one or more of the functions described herein as being performed by the controller108are instead performed by the host102. In some embodiments, some or all of the functions described herein as being performed by the controller108may instead be performed by another element such as a controller in a hybrid drive including both non-volatile memory elements and magnetic storage elements.

The memory110may be any memory, computing device, or system capable of storing data. For example, the memory110may be a random-access memory (RAM), a dynamic random-access memory (DRAM), a static random-access memory (SRAM), a synchronous dynamic random-access memory (SDRAM), a flash storage, an erasable programmable read-only-memory (EPROM), an electrically erasable programmable read-only-memory (EEPROM), or the like. In various embodiments, the controller108uses the memory110, or a portion thereof, to store data during the transfer of data between the host102and the non-volatile memory112. For example, the memory110or a portion of the memory110may be a cache memory.

The non-volatile memory (NVM)112receives data from the controller108and stores the data. The non-volatile memory112may be any type of non-volatile memory, such as a flash storage system, a solid state drive, a flash memory card, a secure digital (SD) card, a universal serial bus (USB) memory device, a CompactFlash card, a SmartMedia device, a flash storage array, or the like.

The controller108or NVM112can be configured to perform any of the local address mapping schemes described herein.

One way to address the large indirection table issue discussed in the background section above for page based NVMs is to improve the process of mapping logical pages to physical pages, and more specifically, the process for mapping logical block addresses (LBAs) to physical block addresses (PBAs).

Local Address Mapping

FIG. 2is a block diagram of a system200for performing local address mapping including an access network202and a cumulative state computation block204that can be used to map logical block addresses (LBAs) to a physical block addresses (PBAs) in accordance with one embodiment of the disclosure. The system200further includes an initial and second memory map block206, a background swap scheduler208, and a mapping state generation and change block210. In one aspect, the access network202can be implemented in hardware (e.g., ultra-low latency with 3 cycle pipeline delay with low logic and memory equivalent of less than 10,000 logic gates) and the remaining components of the system200can be implemented in firmware.

The access network202, which will be discussed in greater detail below, receives the latest two cumulative control states in CCS1and CCS2from the cumulative control state block204along with a move index from the background swap scheduler208. Using these inputs, the access network202can determine which physical block address (PBA) a given logical block address (LBA) is mapped to using two slave networks (e.g., bitonic or Benes networks) that each receive one of the two cumulative control states to generate a possible mapping.

The cumulative state computation block204, which will be discussed in greater detail below, initially receives control states in cs1and cs2and CCS1from the initial and second memory map block206. In one aspect, the initial control states may have random values and CCS1may be set to cs1. After an initial period, the cumulative state computation block204may receive these inputs from the mapping state generation change block210. Using these inputs, the cumulative state computation block204can determine a second cumulative control state, CCS2, which is a function of CCS1and cs2. The control states, cs1and cs2, can be used as inputs to a master bitonic network, or another suitable network, and ultimately to determine the second cumulative control state, CCS2. The cumulative control states, CCS1and CCS2, can be used by the access network202to determine current LBA to PBA mappings. In one aspect, the cumulative state may be computed in firmware using the master bitonic network when the system changes the mapping periodically once the system completes all the transfers in the background. The background moves can be scheduled in firmware with another bitonic network using the new control state (e.g., cs2).

In several applications such as dynamic wear leveling, which changes its random memory map from LBA to PBA on a periodic basis, the system200may need to compute a cumulative random mapping at any given time point so that a given LBA can be precisely located at a correct PBA. In one example, assume a random map of memory of size 2{circumflex over ( )}32 with a mapping function f1(t1) at time t1, a random map of memory of size 2{circumflex over ( )}32 with a mapping function f2at time t2, a random map of memory of size 2{circumflex over ( )}32 with a mapping function f3at time t3, . . . , and a random map of memory of size 2{circumflex over ( )}32 with a mapping function fn at time tn. In operation, the system200can compute a cumulative function (cfn) at time tn, such that cfn=fn(cfm), and where cfm is cumulative function at time tm and tm=tn−1. In one aspect, the system200can generate a random mapping function (fn) using a bitonic network and a random control switch seed (e.g., using the cumulative state computation block204). The bitonic network can be configured to provide the random mapping function (fn) using a random control switch seed (e.g., cs1, cs2, . . . , csn). The cumulative function (cfn) can now be passed through a master bitonic sorter and the control switch positions are recorded in the sorting process. These control switch positions, CCSn, can now be used to program a bitonic network with a data width of 1 and a network size of 32 to generate cumulative random mapping for 2{circumflex over ( )}32 entries (e.g., using access network202). At any time, any of 2{circumflex over ( )}32 entries can be passed through this network to generate a permuted address. These operations will be described in greater detail below.

The background swap scheduler208is configured to perform periodic swaps of data stored at preselected PBAs. In one aspect, the background swap scheduler208may be configured to perform one swap per every 100 host writes. In another aspect, the background swap scheduler208may be configured to perform one swap per every X host writes, where X is a positive integer. In one aspect, the background swap scheduler208is configured to perform moves according to a new map for two pages (swap) and thus moves are scheduled for every 200 host writes. The background swap scheduler208may maintain a move counter which may be incremented by 1 for every 200 host writes. In one aspect, moves are done in structured fashion on the physical memory using a lookup of a bitonic network using the new control state (e.g., cs2). In one aspect, the move counter (e.g., move index) gets incremented from 1 to N/2. The move counter can also be referred to as move index, move_index, MOVE_INDEX, move_counter, and move counter. For each value, a swap is scheduled such that physical memory at the move counter gets swapped with the physical memory. In one embodiment, for example, the background swap scheduler208can perform the swap as follows:

In such case, f_cs2is a resulting random mapping function based on control state cs2. The determination of cs2is described in greater detail below in the discussion ofFIG. 9. In one example, cs2can be a randomly generated bit sequence of length 320 bits for a bitonic network with 32 inputs and 32 outputs.

In one embodiment, the MOVE_INDEX is set to 0 in the initial memory and second memory map block206and also in the mapping state generation and change block210. In the background swap scheduler208the MOVE_INDEX can be incremented by 1 for an arbitrary number of host writes (e.g., per every 100 host writes as inFIG. 2or per 200 host writes or another suitable number of host writes). In another embodiment, the MOVE_INDEX increment logic can be implemented in hardware as it may be easier to keep track of the host writes in hardware. In such case, MOVE_INDEX can be communicated from a new hardware logic block that implements the MOVE_INDEX increment logic to the background swap scheduler208and directly communicates MOVE_INDEX to the access network block202instead of being communicated from the background swap scheduler208(e.g., firmware) to the access network202(e.g., hardware).

In one aspect, these operations of the background swap scheduler208may result in a 1 percent write amplification. In one aspect, the swap operation is assumed to be atomic.

The mapping state generation and change block210is configured to update control states and cumulative control states once all of the swap transfers are complete. In one aspect, when the move index is equal to N/2, then all of the swap transfers from the previous map to the current map should be complete. Once completed, the mapping state generation and change block210can then generate a new map. In one aspect, the move counter (e.g., move index) can be reset (e.g., to 0 or 1). Whenever the mapping change is done, cumulative control states can be computed in firmware and can be supplied to hardware. These values can be scheduled a little in advance in the firmware (e.g., in the mapping state generation and change block210) to ensure timely communication to the hardware (e.g., access network202). In one aspect, the old control state (cs1) may be set to the new control state (cs2), and the old cumulative control state (CCS1) may be set to the new cumulative control state (CCS2).

Aspects of the access network202and the cumulative state computation block204will be discussed in greater detail below.

FIG. 3is a block diagram of an access network300, including a select logic block302that can be used in the address mapping system ofFIG. 2, to map a LBA to a PBA in accordance with one embodiment of the disclosure. In one aspect, the access network300can be used in the system ofFIG. 2as access network202. The system300further includes a first bitonic network304and a second bitonic network306. The first bitonic network304can receive the LBA and new cumulative control state (CCS2) and generate a second possible physical block address (PBA2). Similarly, the second bitonic network306can receive the LBA and old cumulative control state (CCS1) and generate a first possible physical block address (PBA1). The select logic302can then analyze the locations of the possible PBAs in the page to determine which one is correct mapping using a preselected algorithm. More specifically, the select logic302can compare PBA2to the number of PBAs in the page (N) divided by 2 (e.g., N/2). If PBA2is less than N/2, then a temporary variable (Pba_mc) is set to PBA2. Otherwise, Pba_mc is set to PBA1. If Pba_mc is less than the move index (MOVE_INDEX) from the background swap scheduler208ofFIG. 2, then the correct PBA (e.g., output PBA) is PBA2. Otherwise, the correct PBA is PBA1. The operation of the select logic302will be described further below.

In one aspect, the select logic block302can effectively determine which of two possible PBAs (e.g., PBA1and PBA2) contains the actual data that corresponds to the LBA of interest. This determination is based on a mid-point of the PBAs in the page (e.g., N/2) and the move index. In comparing the addresses of PBA1and PBA2to the mid-point and move index, the select logic block302effectively determines which of the two PBAs contains the actual data that corresponds to the LBA of interest at a given time. For example, inFIG. 5, which will be discussed in greater detail below, LBA9is stored in PBA3at time period CF0, in PBA11at CF1, in PBA8at CF2, in PBA14at CFn−1, and in PBA4at CFn. The system can keep track of the last two possible locations, PBA14and PBA4, which are the outputs of the ccs1and ccs2functions. The select logic block302can then exactly determine whether the data related to LBA9is still there at PBA14or moved to PBA4.

In one aspect, the first bitonic network304and the second bitonic network306can be replaced with a first network and a second network, respectively. In such case, the first network can be configured to generate a first PBA candidate from a LBA using a first function, and the second network can be configured to generate a first PBA candidate from a LBA using a second function. In one aspect, the first function and/or the second function may be a function performed by a multi-stage interconnection network and/or a block cipher. The multi-stage interconnection network may be implemented with one or more of a Benes network, an inverse Benes network, a Bitonic network, an inverse Bitonic network, an Omega network, an inverse Omega network, a Butterfly network, or an inverse Butterfly network. In one aspect, the first function and/or the second function may include an exclusive OR function and a function performed by a multi-stage interconnection network and/or a block cipher.

In one aspect, any one of the select logic302, the first bitonic network304, and/or the second bitonic network306can be a special purpose processor or other suitable hardware specifically (such as an application specific integrated circuit or other hardware described above) configured/programmed to perform any of the functions contained within the application, such as the functions illustrated inFIG. 4.

FIG. 4is a flow chart of a process400for mapping a LBA to a PBA in accordance with one embodiment of the disclosure. In one embodiment, the process400can be performed by the access network300ofFIG. 3, or any of the other local address mapping systems described herein. In block402, the process generates a first physical block address (PBA) candidate from a LBA using a first function. In one aspect, the first function may be a function performed by the first network (e.g., first bitonic network304ofFIG. 3) as described above. In certain aspects, the actions of block402may be effectuated with the controller108, or with the controller108in combination with the host102as illustrated inFIG. 1. In certain aspects, block402may be effectuated with the first bitonic network304ofFIG. 3, the second bitonic network306ofFIG. 3, the select logic302ofFIG. 3, the controller108ofFIG. 1, and/or any combination of those components. In one aspect, block402may be effectuated with the first bitonic network304. In one aspect, block402may represent one means for generating a first PBA candidate from a LBA using a first function.

In block404, the process generates a second physical block address (PBA) candidate from the LBA using a second function. In one aspect, the second function may be a function performed by the second network (e.g., second bitonic network306ofFIG. 3) as described above. In certain aspects, the actions of block404may be effectuated with the controller108, or with the controller108in combination with the host102as illustrated inFIG. 1. In certain aspects, block404may be effectuated with the first bitonic network304ofFIG. 3, the second bitonic network306ofFIG. 3, the select logic302ofFIG. 3, the controller108ofFIG. 1, and/or any combination of those components. In one aspect, block404may be effectuated with the second bitonic network306. In one aspect, block404may represent one means for generating a second PBA candidate from a LBA using a second function.

In block406, the process selects either the first PBA candidate or the second PBA candidate for the data access based on information related to a background swap of data stored at the first PBA candidate and a background swap of data stored at the second PBA candidate. In one aspect, the process selection may be performed by the select logic302ofFIG. 3. In certain aspects, the actions of block406may be effectuated with the controller108, or with the controller108in combination with the host102as illustrated inFIG. 1. In certain aspects, block406may be effectuated with the select logic302ofFIG. 3, the controller108ofFIG. 1, and/or any combination of those components. In one aspect, block406may be effectuated with the select logic302. In one aspect, block406may represent one means for selecting either the first PBA candidate or the second PBA candidate for the data access based on information related to a background swap of data stored at the first PBA candidate and a background swap of data stored at the second PBA candidate.

In one aspect, the information related to the background swap of data stored at the first PBA candidate and the background swap of data stored at the second PBA candidate includes a status of the background swap of data stored at the first PBA candidate and a status of the background swap of data stored at the second PBA candidate. In one aspect, the first PBA candidate and the second PBA candidate may be contained within a PBA map. In such case, examples of the status data may include a position of the second PBA candidate relative to a midpoint of all entries in the PBA map, a PBA move counter based on the position of the second PBA candidate, and/or a move index indicative of a current position of PBA swaps within the PBA map. Examples of the selection process and the use of the mapping status data will be described in further detail below.

In one aspect, the process400can also include mapping a portion of a physical address space containing the selected PBA candidate to another portion of the physical address space using at least one of a background data move or a background data swap. In one aspect, this mapping can be performed by the background swap scheduler208ofFIG. 2.

In an alternative embodiment, the selecting either the first PBA candidate or the second PBA candidate can be performed using a memory table (see for example system1100ofFIG. 11that may store various control states in a ROM or other suitable memory).

In one aspect, the process enables data access of an NVM, where the data access may be a read access or a write access.

FIGS. 5-8are diagrams of exemplary physical block addresses at discrete times illustrating operation of the select logic on mapping LBAs to PBAs for example values of the PBAs and move index variables in accordance with one embodiment of the disclosure.

FIG. 5illustrates operation of the select logic with example values of the PBAs and move index variables where the first condition (e.g., PBA2<N/2) is satisfied and the second condition (e.g., PBA_mc<move_index) is not satisfied such that the correct PBA is PBA1or slot14. The diagram500shows the physical block address (PBA) memory maps at different time stages (e.g., CF0to CFn). The select logic operates using the last two memory maps (CFn and CFn−1). Input variables include the move index (move_index=2), the number of entries in the PBA map (N=16), the local bits permuted (L=8), and the global bits permuted (G=1). While variables L and G are shown, they may or may not be used in the select logic. Since the PBA2is a location that has not been swapped since it is less than the move index (move_index=2 for this example), the select logic effectively determines that PBA2is not correct and selects PBA1which it knows to be correct. More specifically, in the first condition, the select logic determines that PBA2=4 is less than N/2=8. Thus, Pba_mc is set to PBA2=4. In the second condition, the select logic determines that Pba_mc=4 is not less than the move_index=2, and thus sets the output PBA to be PBA1=14.

In one aspect, the first condition can be changed to compare PBA1to N/2 (e.g., PBA1>=N/2).

FIG. 6illustrates operation of the select logic with example values of the PBAs and move index variables where the first condition (e.g., PBA2<N/2) is satisfied and the second condition (e.g., PBA_mc<move_index) is satisfied such that the correct PBA is PBA2or slot4. The diagram600shows the physical block address (PBA) memory maps at different time stages (e.g., CF0to CFn). The select logic operates using the last two memory maps (CFn and CFn−1). Input variables include the move index (move_index=5), the number of entries in the PBA map (N=16), the local bits permuted (L=8), and the global bits permuted (G=1). While variables L and G are shown, they may or may not be used in the select logic. Since the PBA2is a slot that has been swapped since it is less than the move index (move_index=5 for this example), the select logic effectively determines that PBA2is correct and selects it. More specifically, in the first condition, the select logic determines that PBA2=4 is less than N/2=8. Thus, Pba_mc is set to PBA2=4. In the second condition, the select logic determines that Pba_mc=4 is less than the move_index=5, and thus sets the output PBA to be PBA2=4.

FIG. 7illustrates operation of the select logic with example values of the PBAs and move index variables where the first condition (e.g., PBA2<N/2) is not satisfied and the second condition (e.g., PBA_mc<move_index) is satisfied such that the correct PBA is PBA1or slot5. The diagram700shows the physical block address (PBA) memory maps at different time stages (e.g., CF0to CFn). The select logic operates using the last two memory maps (CFn and CFn−1). Input variables include the move index (move_index=2), the number of entries in the PBA map (N=16), the local bits permuted (L=8), and the global bits permuted (G=1). While variables L and G are shown, they may or may not be used in the select logic. Since the PBA2is a slot (e.g., slot10) that has not been swapped since it is greater than the move index (move_index=2 for this example), the select logic effectively determines that PBA2is not correct and selects PBA1which it knows to be correct. More specifically, in the first condition, the select logic determines that PBA2=10 is not less than N/2=8. Thus, Pba_mc is set to PBA1=5. In the second condition, the select logic determines that Pba_mc=5 is not less than the move_index=2, and thus sets the output PBA to be PBA1=5.

FIG. 8illustrates operation of the select logic with example values of the PBAs and move index variables where the first condition (e.g., PBA2<N/2) is not satisfied and the second condition (e.g., PBA_mc<move_index) is not satisfied such that the correct PBA is PBA2or slot10. The diagram800shows the physical block address (PBA) memory maps at different time stages (e.g., CF0to CFn). The select logic operates using the last two memory maps (CFn and CFn−1). Input variables include the move index (move_index=6), the number of entries in the PBA map (N=16), the local bits permuted (L=8), and the global bits permuted (G=1). While variables L and G are shown, they may or may not be used in the select logic. Since the PBA2is a slot (e.g., slot10) that has been swapped since PBA1was swapped to PBA2(move index=6 is greater than PBA1=5), the select logic effectively determines that PBA2is correct and selects it. More specifically, in the first condition, the select logic determines that PBA2=10 is not less than N/2=8. Thus, Pba_mc is set to PBA1=5. In the second condition, the select logic determines that Pba_mc=5 is less than the move_index=6, and thus sets the output PBA to be PBA2=10.

FIG. 9is a block diagram of a cumulative state computation block900including a bitonic network902and a bitonic sorter904that can be used in the address mapping system ofFIG. 2in accordance with one embodiment of the disclosure. The cumulative state computation block900further includes an cumulative mapping block906that may generate/perform some initial mapping and receives the next output of the bitonic network902via feedback. The bitonic network902, a time varying network which can also be a master bitonic network in this system, receives the output of the cumulative mapping block906and the control state (cs) and generates a new cumulative mapping. The bitonic sorter904receives the new cumulative mapping and determines the switch settings (e.g., cumulative control states or CCS2) needed to go from the initial cumulative mapping to the new cumulative mapping.

In one aspect, at any given time, the system may store the last two values for CCS (for access determination in the hardware or access network) and the current values for CS (for moving). So in one example the control state memory is only about 960 bits (e.g., 320×3 bits). In such case, a global mapping bit for these three mappings (i.e., 3 more bits) may need to be preserved.

As to the use of a bitonic network as compared with a Benes network (described above in discussion ofFIG. 3), the bitonic network can have log 2(L/2)*(log 2(L/2)+1)/2*L/2 switches, while the Benes network can have 2*log 2(L/2)*L/2 switches. For example values of L=32 such that L/2=16, the Benes network can have 8 (=2*log 2(16)) stages of switches where each stage consists of 16 (=L/2) switches. In such case, the bitonic network has 20 (=4*(4+1)/2(=log 2(16)*(log 2(16)+1)/2) stages of switches where each stage consists of 16 (=L/2) switches. So the bitonic network may need to be pipelined more to achieve one address look up for a cycle. So the number of 2 by 2 switches needed may thus be 320 versus 128 for the Benes network, which is still small. In one aspect, each switch has two 1-bit multiplexers and each switch needs 3 gates (2 AND gates and 1 OR gate). So it appears that about 2000 gates versus about 700 gates (exact calculation is 320×6 gates versus 128×6 gates) may be used to implement each network. In one aspect, this may result in 4000 gates for the bitonic network versus 1400 gates for Benes. However, the firmware may be much simpler for the bitonic network.

Aspects of the bitonic sorter and bitonic network will be described in greater detail below.

FIG. 10is a diagram of a bitonic sorter1000including a sorter table1002and comparison type table1004in accordance with one embodiment of the disclosure. A bitonic sorter can have log 2(L/2)*(log 2(L/2)+1)/2*L/2 comparators. For an example, say L=8, and thus L/2=4. In such case, the bitonic sorter can have six stages of comparators, where log 2(8)*(log 2(8)+1)/2=3*(3+1)/2=6, and each stage consists of 4 (=L/2) comparators.

The comparison type table1004, or “cmp_type”, is a matrix of a size with the number of rows equal to log 2(L/2)*(log 2(L/2)+1)/2 (e.g., equal to number of stages of comparators=6) and the number of columns equal to L/2 (e.g., equal to number of comparators in each stage=4). So for L=8, as in the working example, cmp_type1004is a matrix of size 6×4. The first row (or in general ith row) in this cmp_type matrix1004corresponds to a comparator type of the first stage of comparators (or in general ith stage of comparators) in diagram1000. The comparator type0(e.g., row1, column1of cmp_type1004) means a comparator taking two inputs (in1, in2) and presenting the outputs (out1,out2) such that first output is the smaller number among the inputs (e.g., out1=minimum(in1,in2)) and second input is the larger number among the inputs (e.g., out2=maximum(in1,in2)). This is shown with the down arrow in diagram1000. In one aspect, the comparator also gives an output bit that is equal to 1 if a swap occurred (e.g., out1=in2, out2=in1), to 0 if no swap occurred (e.g., out1=in1and out2=in2). This aspect is not shown in diagram1000.

The comparator type1(e.g., row1, column2of cmp_type1004) means a comparator taking two inputs (in1, in2) and presenting the outputs (out1, out2) such that first output is the larger number among the inputs (e.g., out1=maximum(in1,in2)) and second input is the smaller number among the inputs (e.g., out2=minimum(in1,in2)). This is shown with the upward arrow in diagram1000. In one aspect, the comparator also gives an output bit that is equal to 1 if a swap occurred (e.g., out1=in2, out2=in1), to 0 if no swap occurred (e.g., out1=in1, out2=in2). This aspect is not shown in diagram1000.

The sorter table1002, “sorter_ind”, is a matrix of a size with a number of rows equal to log 2(L/2)*(log 2(L/2)+1)/2 (e.g., equal to number of stages of comparators or 6) and a number of columns equal to L (e.g., equal to number of inputs to each stage of comparators or 8). So for L=8, as in the working example, the sorter_ind1002is a matrix of size 6×8. The first row (or in general ith row) in this sorter_ind matrix1002corresponds to the port numbers that are connected to the inputs of each stage of bitonic network.

In one aspect, a sequence can be bitonic if it monotonically increases and then monotonically decreases, or if it can be circularly shifted to monotonically increase and then monotonically decrease.

In one aspect, a bitonic network can have the same topology as that of the bitonic sorter1000except that that comparators are replaced with 2 by 2 switches with control inputs.

FIG. 11is another block diagram of a system1100for local address mapping including an access network1102and one or more read-only memories (ROMs) (1104a,1104b,1104c) for storing pre-calculated cumulative control state values in accordance with one embodiment of the disclosure. The system1100further includes a background swap scheduler1108and a mapping state generation and change block1110. In one aspect, the access network1102and ROMs (1104a,1104b,1104c) can be implemented in hardware (e.g., ultra-low latency with 3 cycle pipeline delay with low logic and memory equivalent of less than 10,000 logic gates) and the remaining components of the system1100can be implemented in firmware. In operation, the blocks of system1100can operate similar to those of system200ofFIG. 2. A primary difference however in system1100is that the cumulative state is computed offline using a master bitonic network, or other suitable network, and then stored (e.g., in a table) in the ROMs (1104a,1104b,1104c). In one aspect, this approach can involve using a small amount of additional memory as compared to the system ofFIG. 2.

Block1104arepresents a non-volatile memory (e.g., ROM such as CCS_ROM) storing the CCS values (e.g., CCS1and CCS2). Block1104brepresents a non-volatile memory (e.g., ROM such as CS_ROM) storing the CS values (e.g., cs1and cs2). Block1104crepresents a non-volatile memory (e.g., programmable ROM such as USE_PROM) effectively storing which lines in the CS_ROM and CCS_ROM are being used in case there is a loss of power. Effectively, the USE_PROM can be used to preserve the control state in a non-volatile memory space to restore in case of power loss. The control state values stored can include MOVE_INDEX, cs2, ccs1, ccs2, bg_transfer_address_1, bg_transfer_address2, bg_transfer_status, and/or ROM_row_index. In one aspect and upon recovery of power, the system1100can perform a consistency check using the USE_PROM (e.g., use indicator) entries and control state and restore the mapping state and resume any interrupted background transfers.

FIGS. 12a, 12b, 12care schematic diagrams of ROMs for storing control state values, cumulative control state values, and use indicators that can be used in the system ofFIG. 11in accordance with one embodiment of the disclosure.

FIG. 12ais a schematic diagram of a ROM (CS_ROM)1200that can be used to store control state (CS) values used in the system ofFIG. 11in accordance with one embodiment of the disclosure.FIG. 12aillustrates one possible implementation of a non-volatile memory that can be used to store control state values. In another aspect, other implementations can also be used.

FIG. 12bis a schematic diagram of a ROM (CCS_ROM)1202that can be used to store cumulative control state (CCS) values used in the system ofFIG. 11in accordance with one embodiment of the disclosure.FIG. 12billustrates one possible implementation of a non-volatile memory that can be used to store cumulative control state values. In another aspect, other implementations can also be used.

FIG. 12cis a schematic diagram of a PROM (USE_PROM)1204that can be used to store control state (CS) values used in the system ofFIG. 11in accordance with one embodiment of the disclosure. More specifically, the USE_PROM1204can be used to store index or placeholder information relating to current positions in the CS_ROM and CCS_ROM in a non-volatile memory space to restore in case of power loss.FIG. 12cillustrates one possible implementation of a non-volatile memory that can be used to store index information into the ROMs. In another aspect, other implementations can also be used.

In one aspect, the system1100ofFIG. 11can increment a ROM_row_index by 1 every time a mapping gets used, where ROM_row_index can be the address for CS_ROM, and CCS_ROM. The system can also program a 1-bit entry in USE_PROM as 1 to indicate this line is used already.

FIG. 13is a block diagram of another access network1300including a select logic block1302that can be used in the address mapping system ofFIG. 11in accordance with one embodiment of the disclosure. In one aspect, the access network1300can be used in the system ofFIG. 11as access network1102. The system1300further includes a first bitonic network1304and a second bitonic network1306. The system1300can operate substantially the same as system300ofFIG. 3except that the cumulative control state values (CCS1, CCS2) are received from the ROMs (e.g.,1104a,1104b,1104c) rather than from a online cumulative control state block such as block204ofFIG. 2.

The systems and methods for performing local address mapping described above may be used in conjunction with wear leveling schemes employing random address mapping using local and global interleaving. The following section describes such approaches.

FIG. 14is a block diagram of indirection table1400in accordance with one embodiment of the disclosure. For example, in a drive with M pages/sectors, the indirection table has M entries as is depicted inFIG. 14. In such case, each entry is N bits where N is log 2(M). For a 2 TB drive with 512 byte pages, M=2×10{circumflex over ( )}12B/512B=3.9×10{circumflex over ( )}9 and thus N is equal to 32. As such, the memory required in bits for the table would be M×log 2M=125 GB (˜15 GB). The frequency of use table would also consume similar space (˜15 GB). So the total requirement would be around 30 GB for this meta data. In some implementations, the meta data may have to be replicated with two plus one redundancy, thereby increasing the complexity up to 90 GB. In such case, this memory usage amounts to around 4.5% of disk space. So this sort of approach would generally not be practical.

FIG. 15is a block diagram of a general system for performing random address mapping using local and global interleaving in accordance with one embodiment of the disclosure. The system1500includes a lookup table1502that can be used to store 2{circumflex over ( )}G entries with a depth of 2{circumflex over ( )}G and a width of G. The system1500also includes a multi-stage interconnection network (MIN)1504that can be used to provide permutations of data sets, and a control state block1506that can be used to control the MIN1504. The system1500illustrates a general framework for mapping an N-bit logical address space to N-bit physical space by first dividing the address bits into G bits and N−G bits. In general, any G bits out of the N bits can be selected using another fixed network. In this context, a fixed network can simply be a fixed arrangement of wires to arrive at a specific network. As compared to a multi-stage programmable interconnection network, the fixed network may not have programmability. For simplicity, the G bits selected are the most significant bits (MSBs) of the N bits. So the system can perform mapping on 2{circumflex over ( )}G entries in block1502, and perform bit permutation on N−G bits in block1504. The G bits can be mapped using a 2{circumflex over ( )}G entry mapping table1502. In one aspect, the mapping can be performed such that there is one-to-one unique mapping and the input is not equal to the output. Also, in one aspect, G is selected such that 1<=G<=N. In one aspect, the case of G<=6 may be of particular interest. If G=N, then this case can be equivalent to the conventional mapping table approach.

In one embodiment, the global mapping can satisfy one or more properties. For example, in one aspect, the global mapping can be a one to one function. In another aspect, the global mapping can be performed such that the input is not equal to the output. In another aspect, a swap can be performed such that a global mapping of a number (k) is equal to kk, while a global mapping of kk is equal to k. So suitable functions for global mapping may include bit inverse mapping, random swap, deterministic swap, and other suitable functions. Bit inverse mapping can be chosen for a simple hardware implementation. If a table is used, the maximum size of the table needed can be 2{circumflex over ( )}G entries with each entry having a width of G bits. Since G is not more than 7 in this example, the table approach is also suitable.

In one embodiment, the local mapping can satisfy one or more properties. For example, in one aspect, the local mapping can be a one to one function. So suitable functions for local mapping may include deterministic mapping and/or random mapping. In one aspect, random mapping may be selected. Deterministic or random mapping may be implemented using tables or an Omega network, a Butterfly network, a Benes network, or another suitable network. In one aspect, a Benes network (e.g., such as a master-slave Benes network) is selected as it has the lowest complexity for computing the switch state required. In this network, a bitonic sorting can be implemented on master Benes network on sequences with certain properties to derive the switch state for slave Benes network. In one embodiment, the local address mapping can be performed using any of the local address mapping schemes described above in conjunctions withFIGS. 1-13.

In one embodiment, a wear leveling algorithm implemented with the random address mapping can involve operating in an address space, set partitioning the address space, and local and global interleaving in the address space. In one aspect, the wear leveling algorithm can involve gradual deterministic transition from one memory map to another memory map.

FIG. 16is a flow chart of a process for performing random address mapping using global mapping and local interleaving in accordance with one embodiment of the disclosure. In one embodiment, the process can be used for wear leveling or other random address mapping in any of the random mapping systems described herein. In block1602, the process identifies a number of bits (N) in a physical address space of a non-volatile memory (NVM). In block1604, the process selects at least one bit (G) of the N bits of the physical address space to be used for global interleaving, where G is less than N. In block1606, the process determines a number of bits equal to N minus G (N−G) to be used for local interleaving.

In block1608, the process maps the G bit(s) using a mapping function for global interleaving. In one embodiment, the mapping function can be a bit inverse mapping function, a random swap mapping function, a deterministic swap mapping function, and/or another suitable mapping function.

In block1610, the process interleaves (N−G) bits using an interleaving function for local interleaving. In one embodiment, the interleaving function can be a deterministic interleaving function, a random interleaving function, and/or another suitable interleaving function. In one embodiment, the interleaving function can be implemented using an Omega network, a Butterfly network, a Benes network, a master-slave Benes network, and/or another suitable interleaving function.

In some embodiments, the mapping function for the global interleaving is a bit inverse mapping function, and the interleaving function is implemented using a master-slave Benes network. In one such embodiment, the G bit(s) are the most significant bit(s) of the physical address space of the NVM, and the bit inverse mapping function involves inversing each of the G bit(s).

In block1612, the process generates a combined mapping including the mapped G bit(s) and the interleaved (N−G) bits. In one embodiment, the combined mapping constitutes a mapped physical address (see for example col.806inFIG. 8as will be discussed in more detail below).

FIG. 17is a block diagram of a system for performing random address mapping with bit inverse for global mapping (G bits) and permutation for local interleaving (N−G bits) in accordance with one embodiment of the disclosure. The system1700includes a bit inverse block1702that can be used to inverse selected bits of the logical address. In one aspect, for example, the bit inverse block1702can be used to map G bits using a mapping function for global interleaving as is described in block1608ofFIG. 16, where the mapping function is a bit inversing function. The system1700also includes a multi-stage interconnection network (MIN)1704that can be used to provide permutations of data sets, such as permutations of selected bits of the logical address. In one aspect, the MIN1704can be used to interleave N−G bits using an interleaving function for local interleaving as is described in block1610ofFIG. 16. The system1700also includes a control state block1706that can be used to control the MIN1704.

The system1700further includes a processor1708which can be used to control and/or perform computations for the bit inverse block1702and the MIN1704. In this context, processor1708refers to any machine or selection of logic that is capable of executing a sequence of instructions and should be taken to include, but not limited to, general purpose microprocessors, special purpose microprocessors, central processing units (CPUs), digital signal processors (DSPs), application specific integrated circuits (ASICs), signal processors, microcontrollers, and other suitable circuitry. Further, it should be appreciated that the term processor, microprocessor, circuitry, controller, and other such terms, refer to any type of logic or circuitry capable of executing logic, commands, instructions, software, firmware, functionality, or other such information. In one aspect, the processor1708can be used to identify a number of bits (N) in a physical address space of a non-volatile memory (NVM) as is described in block1602ofFIG. 16, select at least one bit (G) of the N bits of the physical address space to be used for global interleaving, where G is less than N as is described in block1604ofFIG. 16, and/or determine a number of bits equal to N minus G (N−G) to be used for local interleaving as is described in block1606ofFIG. 16. In one aspect, the processor1708can also be used to generate a combined mapping including the mapped G bit(s) and the interleaved (N−G) bits as is described in block1612ofFIG. 16. In one embodiment, the combined mapping is instead generated by block1702and/or block1706.

In one simple example to illustrate the address space operations, and as depicted inFIG. 17, assume the number of pages (M) in the NVM is 16 (i.e., M=16 pages). In such case, the number of address bits (N) can be computed as N=log 2(M)=4 address bits. In such case, the parameters of the configuration would be as follows: G=1 (2{circumflex over ( )}G partitions), L=N−G=4−1=3 (3×3 network). This simple example will be carried throughFIGS. 18 to 20.

FIG. 18is a table1800illustrating an example of global mapping using bit inverse on G bits in accordance with one embodiment of the disclosure. In one aspect, the table1800ofFIG. 18can be viewed as an example of the global mapping shown in block1702ofFIG. 17. In the continuing simple example, G is 1 bit (i.e., the most significant bit (MSB) of the 4 address bits). In the example ofFIG. 18, the table1800illustrates the initial addresses in the left column, shown in both decimal and binary. The table1800also illustrates the final addresses, after global mapping using bit inverse on the G bits (i.e., the MSB), in the right column of addresses, shown in both decimal and binary. As can be seen inFIG. 18, the global mapping using bit inverse is a one to one function, and the input is not equal to the output. This implementation is consistent with one or more of the possible design characteristics discussed above.

FIG. 19is a table1900illustrating an example of local interleaving using a permutation on N−G bits in accordance with one embodiment of the disclosure. More specifically, for the local interleaving of address bits, assume the 3 address bits ([x2 x1 x0]) are permuted to [x2 x0 x1]. In the example ofFIG. 19, the table1900illustrates the initial addresses in the left column, shown in both decimal and binary. The table1900also illustrates the final addresses, after local mapping using the selected permutation, in the right column of addresses, shown in both decimal and binary. As can be seen inFIG. 19, the local interleaving using permutation is a one to one function. This implementation is consistent with one or more of the possible design characteristics discussed above. In one aspect, the table1900ofFIG. 19can be viewed as an example of the local interleaving as shown in block1704ofFIG. 17.

FIG. 20is a table2000illustrating an example of global mapping using bit inverse and local interleaving using permutation in accordance with one embodiment of the disclosure. The left most column2002shows the original addresses in decimal. The middle column2004shows the effect of global mapping/interleaving only and matches the final column (e.g., results) ofFIG. 18. The right most column2006shows the resulting physical addresses with both the global mapping using bit inverse and the local interleaving using a selected permutation. This simple example illustrates one possible operation of the systems and methods ofFIGS. 15-17. More specifically, the table2000ofFIG. 20can be viewed as an example of the combined mapping that can be generated by any combination of the processor1708, block1702and1704ofFIG. 17.

FIG. 21is a block diagram of a multi-stage interconnection network (MIN)2100that can be used to perform local interleaving (e.g., block1704inFIG. 17) in accordance with one embodiment of the disclosure. This MIN approach (e.g., multi-stage interconnection network or MIN with 2{circumflex over ( )}N entries) for generating random mapping from logical space and physical space is may be expensive to implement as the storage size can be large.

More specifically, in one aspect, moving items has to be done based on a certain order defined by mapping. For a read process, to differentiate which chip select (CS) has to be used, another table of 2{circumflex over ( )}N entries and each entry width needs to be maintained. In contrast, the CS chip storage is equal to log 2(N)*N/2 for an Omega network and log 2(N)*N for a Benes network.

FIG. 22is a block diagram of a butterfly MIN2200that can be used to perform local interleaving in accordance with one embodiment of the disclosure. This MIN approach (e.g., butterfly MIN on 2{circumflex over ( )}N entries) for generating random mapping from logical space and physical space is a suitable multi-stage interconnection network that may be used, for example, for the MIN1704ofFIG. 17or the MIN1504ofFIG. 15.

For the trivial case of shuffle equal to 1 for the physical address space, the network is not needed as it is easy to figure out the mapping. In this context, an address shuffle can be defined as a left cyclic shift of the physical address, which is a binary string. Consider for example stages1to M. At stage k, the physical address of a logical address is given by (xn−1, xn−2, xn−3, xn−k, . . . , x1, x0) is converted to (via inverse) (Xn−1, Xn−2, Xn−3, Xn−k−1, . . . x1, x0). In one aspect, another simpler case may include a butterfly permutation where the MSB is swapped with the LSB, a substitution permutation where any ith bit is swapped with bit 0 (e.g., the LSB), and a super permutation where any ith bit is swapped with the MSB. In another aspect, the local interleaving may involve using any switch combination for each stage.

In general a MIN may be used is one of two modes. For example, in a routing mode, the switches in MIN are configured to realize the desired mapping from input ports to output ports in one or more passes. In such case, each input port takes a multi-bit (say m-bit) word and each output port gives a m-bit word, and there are N inputs and N outputs. In a second mode, an interleaving mode, the switches in MIN are configured using a random seed. This results in a random mapping from input ports to output ports in a single pass. In several aspects, the interleavers and/or interleaving described herein can use a MIN in the interleaving mode to interleave preselected bits in a desired manner.

FIG. 23is a block diagram of a Benes MIN2300that can be used to perform local interleaving in accordance with one embodiment of the disclosure. This MIN approach (e.g., Benes MIN on 2{circumflex over ( )}N entries) for generating random mapping from logical space and physical space is a suitable multi-stage interconnection network that may be used, for example, for the MIN1704ofFIG. 17or the MIN1504ofFIG. 15.

FIG. 24is a block diagram of a Omega MIN2400that can be used to perform local interleaving in accordance with one embodiment of the disclosure. This MIN approach (e.g., Omega MIN on 2{circumflex over ( )}N entries) for generating random mapping from logical space and physical space is a suitable multi-stage interconnection network that may be used, for example, for the MIN1704ofFIG. 17or the MIN1504ofFIG. 15. In one aspect, the Omega network may only be able to provide a subset of all possible permutations of switching while the Benes network may be able provide all possible permutations. In one aspect, if a desired permutation is required, it may be difficult to solve chip select settings for the Benes network. To counter this potential issue, one implementation of the Benes network involves randomly setting the chip select settings, which can makes the chip select algorithm much simpler. That is, the randomly generated chip select settings reduce computing time requirements and/or computing challenges needed to solve the chip select settings.

FIG. 25shows a block diagram of a modified (8×8) Omega MIN2500that can be used to perform local interleaving in accordance with one embodiment of the disclosure. In general, Omega networks are (N×N) multistage interconnection networks that are sized according to integer powers of two. Thus, Omega networks have sizes of N=2, 4, 8, 16, 32, 64, 128, etc. Further, the number L of stages in an Omega network is equal to log 2(N) and the number of (2×2) switches per stage is equal to N/2.

Omega network2500is an (8×8) network that receives eight input values at eight input terminals A[0:7] and maps the eight input values to eight output terminals B[0:7]. Each input value may be any suitable value such as a single bit, a plurality of bits, a sample, or a soft value (such as a Viterbi log-likelihood ratio (LLR) value) having a hard-decision bit and at least one confidence-value bit. The eight input values are mapped to the eight output terminals using log 2(8)=3 configurable stages i, where i=1, 2, 3, each of which comprises 8/2=4 (2×2) switches.

Each stage i receives the eight input values from the previous stage, or from input terminals A[0:7] in the case of stage1, via a fixed interconnection system (e.g.,2502,2504, and2506) that implements a perfect shuffle on the eight input values. A perfect shuffle is a process equivalent to (i) dividing a deck of cards into two equal piles, and (ii) shuffling the two equal piles together in alternating fashion such that the cards in the first pile alternate with the cards from the second pile.

For example, stage1receives eight inputs values from input terminals A[0:7] via fixed interconnection system2502. Fixed interconnection system2502performs a perfect shuffle on the eight input values by dividing the eight input values received at input terminals A[0:7] into a first set corresponding to input terminals A[0:3] and a second set corresponding to input terminals A[4:7]. Similarly, fixed interconnection system2504performs a perfect shuffle on the outputs of switches from stage1and provides the shuffled outputs to the switches of stage2, and fixed interconnection system2506performs a perfect shuffle on the outputs of the switches of stage2and provides the shuffled outputs to the switches of stage3.

In addition to receiving eight input values, each configurable stage i receives a four-bit control signal Ci[0:3] from control signal memory (e.g., ROM), wherein each bit of the four-bit control signal configures a different one of the four 2×2 switches in the stage. Thus, the switches of stage1are configured based on the values of control bits C1[0], C1[1], C1[2], and C1[3], the switches of stage2are configured based on the values of control bits C2[0], C2[1], C2[2], and C2[3], and the switches of stage3are configured based on the values of control bits C3[0], C3[1], C3[2], and C3[3].

Setting a control bit to a value of one configures the corresponding switch as a crossed connection such that (i) the value received at the upper input is provided to the lower output and (ii) the value received at the lower input is provided to the upper output. Setting a control bit to a value of zero configures the corresponding switch as a straight pass-through connection such that (i) the value received at the upper input is provided to the upper output and (ii) the value received at the lower input is provided to the lower output.

In signal-processing applications, multistage interconnection networks, such as Omega network2500, are often used for routing purposes to connect processors on one end of the network to memory elements on the other end. However, multistage interconnection networks may also be used in signal-processing applications for other purposes, such as for permutating or interleaving a contiguous data stream.

FIG. 25illustrates one implementation of a suitable Omega MIN configured for interleaving. In other embodiments, other implementations of a suitable Omega MIN can be used.

While the above description contains many specific embodiments of the invention, these should not be construed as limitations on the scope of the invention, but rather as examples of specific embodiments thereof. Accordingly, the scope of the invention should be determined not by the embodiments illustrated, but by the appended claims and their equivalents.