Bipolar transistor with elevated extrinsic base and methods to form same

Aspects of the disclosure provide a bipolar transistor structure with an elevated extrinsic base, and related methods to form the same. A bipolar transistor according to the disclosure may include a collector on a substrate, and a base film on the collector. The base film includes a crystalline region on the collector and a non-crystalline region adjacent the crystalline region. An emitter is on a first portion of the crystalline region of the base film. An elevated extrinsic base is on a second portion of the crystalline region of the base film, and adjacent the emitter.

TECHNICAL FIELD

Embodiments of the disclosure relate generally to integrated circuit (IC) structures. More specifically, various embodiments of the disclosure provide a bipolar transistor having an elevated extrinsic base, and related methods.

BACKGROUND

In the microelectronics industry as well as in other industries involving construction of microscopic structures, there is a continued desire to reduce the size of structural features and microelectronic devices and/or to provide a greater amount of circuitry for a given chip size. One type of transistor architecture is the bipolar junction transistor (BJT). A BJT refers to a transistor formed of three adjacent semiconductor regions (respectively known as emitter, base, and collector) with alternating conductivity types (e.g., N-P-N or P-N-P). Conventional approaches to form a BJT on a semiconductor substrate form an extrinsic base on an intrinsic base via conventional epitaxy. Such an approach may cause unacceptably rough surface topography on the top of the extrinsic base in small scale BJTs. Rough surface topography may be associated with subsequent processing and/or performance drawbacks.

SUMMARY

Aspects of the present disclosure provide a bipolar transistor structure, including: a collector on a substrate; a base film on the collector, wherein the base film includes a crystalline region on the collector and a non-crystalline region adjacent the crystalline region; an emitter on a first portion of the crystalline region of the base film; and an elevated extrinsic base on a second portion of the crystalline region of the base film, wherein the elevated extrinsic base is adjacent the emitter.

Further aspects of the present disclosure provide an integrated circuit (IC) structure, including: a bipolar transistor stack on a substrate, the bipolar transistor stack including: a collector, a base film on the collector, wherein the base film includes a crystalline region on the collector and a non-crystalline region adjacent the crystalline region, and an emitter on a first portion of the crystalline region of the base film; an elevated extrinsic base on a second portion of the crystalline region of the base film, wherein the elevated extrinsic base is adjacent the emitter; and a trench isolation (TI) adjacent the collector and beneath the non-crystalline region of the base film, wherein a boundary between the collector and the TI is continuous with a boundary between the crystalline region of the base film and the non-crystalline region of the base film.

Yet another aspect of the present disclosure provides a method of forming an integrated circuit (IC) structure, the method including: forming a bipolar transistor stack within a substrate, the bipolar transistor stack including: a collector, a base film on the collector, wherein the base film includes a crystalline region on the collector and a non-crystalline region adjacent the crystalline region, and an emitter on a first portion of the crystalline region of the base film; and forming an elevated extrinsic base on a second portion of the crystalline region of the base film, wherein the elevated extrinsic base is adjacent the emitter.

DETAILED DESCRIPTION

In the description herein, reference is made to the accompanying drawings that form a part thereof, and in which is shown by way of illustration specific exemplary embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it is to be understood that other embodiments may be used and that changes may be made within the scope of the present teachings. The description herein is, therefore, merely illustrative.

Embodiments of the disclosure provide an integrated circuit (IC) having a bipolar transistor with an elevated extrinsic base. The elevated extrinsic base may be formed exclusively on the crystalline region(s) of the base, e.g., by selective epitaxy. The elevated extrinsic base thus is not formed on any non-crystalline regions of an existing film of base material. The bipolar transistor may include a bipolar junction transistor (BJT) stack configured to include, e.g., a NPN, PNP, heterojunction (HBT) NPN, or HBT PNP configuration. Such a structure may include a bipolar transistor stack within a substrate. The bipolar transistor stack includes a collector, a base on the collector, and an emitter on a first portion of the base. Embodiments of the disclosure are distinct from BJT stacks, by forming extrinsic base materials only on crystalline base materials instead of all exposed portions of a base. The crystalline base materials may refer to semiconductor materials grown epitaxially on semiconductor, and not on insulative material such as trench isolation (TI) structures.

BJT structures, such as those in embodiments of the disclosure, operate using multiple “P-N junctions.” The term “P-N” refers to two adjacent materials having different types of conductivity (i.e., P-type and N-type), which may be induced through dopants within the adjacent material(s). A P-N junction, when formed in a device, may operate as a diode. A diode is a two-terminal element, which behaves differently from conductive or insulative materials between two points of electrical contact. Specifically, a diode provides high conductivity from one contact to the other in one voltage bias direction (i.e., the “forward” direction) but provides little to no conductivity in the opposite direction (i.e., the “reverse” direction). In the case of the P-N junction, the orientation of a diode's forward and reverse directions may be contingent on the type and magnitude of bias applied to the material composition of one or both terminals, which affect the size of the potential barrier. In the case of a junction between two semiconductor materials, the potential barrier will be formed along the interface between the two semiconductor materials. IC structures according to the disclosure include an extrinsic base (e.g., formed of crystalline silicon and/or other semiconductor materials) on crystalline portions of the base in a BJT stack, such that non-crystalline portions of the base do not include extrinsic base material thereon. Dopants such as boron (B), and/or other p-type materials, may be formed on and/or introduced into the extrinsic base and non-crystalline region of the base. These dopants may not enter, and thus affect, the crystalline regions of the base below the extrinsic base. These structural characteristics may provide, among other things, improved operational reliability, and easier integration of vertical BJTs into an IC layout.

Referring toFIG.1, a preliminary structure100(simply “structure” hereafter) suitable to form an IC structure according to embodiments of the disclosure is shown. Preliminary structure100may be processed as described herein to yield one or more vertical BJT structures with an extrinsic base on crystalline material. However, it is understood that other techniques, ordering of processes, etc., may be implemented to yield the same BJT structure(s) or similar BJT structures in further embodiments.FIG.1shows a cross-sectional view of structure100with a substrate102including, e.g., one or more semiconductor materials. Substrate102may include but is not limited to silicon, germanium, silicon germanium, silicon carbide, or any other common IC semiconductor substrates. A portion or entire semiconductor substrate102may be strained. The entirety of substrate102or a portion thereof may be strained.

Substrate102optionally may include embedded elements for electrically separating active materials formed thereon from other regions and/or materials within substrate102. A resistive region104optionally may be formed within substrate102, e.g., by converting silicon material within substrate102into a higher-resistive material such as polycrystalline or amorphous silicon (poly-Si). Resistive region104may extend horizontally throughout substrate102, and/or may be formed selectively under locations where active materials are formed, examples of which are discussed elsewhere herein. In further implementations, resistive region104may include oxygen doping to form a dielectric insulator or a buried oxide (“BOX”) layer underneath substrate102and electrically isolate overlying active semiconductor materials. In further implementations, resistive region104may include other elements or molecules such as Ge, N, or Si. However embodied, resistive region104may be sized as narrow as possible to provide better interaction with overlying semiconductor materials, and in various embodiments may have a thickness that is at most approximately twenty-five nanometers (nm) to approximately five-hundred nm. Some portions of substrate102may not have resistive region104, and/or multiple resistive regions104may be formed within substrate102at different depths. Additionally, various conductive particles (“dopants”) may be introduced into substrate102via a process known as “pre-doping” of substrate102above resistive region104.

Embodiments of the disclosure may include forming a set of trench isolations (TIs)110by forming and filling trenches (not shown) with an insulating material such as oxide, to isolate one region of substrate102from an adjacent region of substrate102. Various portions of an IC structure, including the active semiconductor materials of a BJT and/or other devices where applicable, may be disposed within an area of substrate102that is isolated by TI(s)110. According to one example, two TIs110are formed, with one portion of substrate102being horizontally between the two TIs110. This portion of substrate102may be processed to form the doped regions of a BJT, while other portions of substrate102may be doped and/or otherwise processed to form a conductive coupling to one terminal of the BJT structure. TIs110may be formed before active materials are formed within substrate102, but this is not necessarily true in all implementations. Each TI110may be formed of any currently-known or later developed substance for providing electrical insulation, and as examples may include: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2(FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, boro-phospho-silicate glass (BPSG), silsesquioxanes, carbon (C) doped oxides (i.e., organosilicates) that include atoms of silicon (Si), carbon (C), oxygen (O), and/or hydrogen (H), thermosetting polyarylene ethers, a spin-on silicon-carbon containing polymer material, near frictionless carbon (NFC), or layers thereof.

In some implementations, selected portions of substrate102may be doped to form a doped semiconductor region114. Such portions of substrate102may be alongside and underneath TI(s)110to provide a pathway to other doped semiconductor materials. Thus, forming doped semiconductor region114may prepare substrate102for the forming of active semiconductor materials in a BJT stack. The initial doping of substrate102to form doped semiconductor region114may be P-type or N-type in a relatively low concentration, compared to subsequently formed doped materials. P-type dopants refer to elements introduced into substrate102to generate free holes by “accepting” electrons from a semiconductor atom and consequently “releasing” the hole. The acceptor atom must have one valence electron less than the host semiconductor. P-type dopants suitable for use in substrate102may include but are not limited to: boron (B), indium (In) and gallium (Ga). Boron (B) is the most common acceptor in silicon technology. Further alternatives include indium and gallium (Ga). Gallium (Ga) features high diffusivity in silicon dioxide (SiO2), and hence, the oxide cannot be used as a mask during Ga diffusion. N-type dopants are elements introduced into semiconductor materials to generate free electrons, e.g., by “donating” an electron to the semiconductor. N-type dopants must have one more valance electron than the semiconductor. Common N-type donors in silicon (Si) include, e.g., phosphorous (P), arsenic (As), and/or antimony (Sb).

Referring toFIG.2, embodiments of the disclosure include selectively forming additional doped semiconductor materials suitable to form junctions for a bipolar transistor, and thus the active regions of a vertical BJT. Continued processing thus may include forming a BJT stack116on and/or from doped semiconductor region114(FIG.1). Each layer of BJT stack116may be formed, e.g., by deposition and/or epitaxial growth of silicon germanium (SiGe), or one or more compound semiconductor materials (e.g., gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), silicon carbide (SiC), gallium nitride (GaN), and/or other compound materials with similar properties. Each of these various semiconductor or compound semiconductor materials may be formed as a single layer or film. “Depositing” may include any now known or later developed techniques appropriate for the material to be deposited including but are not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.

The forming of BJT stack116may be implemented by direct doping of doped semiconductor region114(FIG.1), and/or by removing portions of doped semiconductor region114between TI(s)110and forming new semiconductor materials therein. Such materials may be formed by at least partially selective deposition of silicon germanium (SiGe), compound semiconductor materials, and/or other materials, optionally with a mask, pad nitride, and/or other blocking structure (not shown) in place over other portions of substrate102to prevent the forming of active semiconductor material thereon. BJT stack116may include a collector116a, which may be doped N-type or P-type and more specifically may have the same polarity as doped semiconductor region114thereunder. Collector116amay have distinct dopants and/or doping concentrations relative to doped semiconductor region114, and may be doped in situ during its deposition and growth, where applicable.

Next, a base film116bof BJT stack116may be formed on collector116a, e.g., by at least partially selective deposition and etching on collector116a. Base film116bmay also be formed of SiGe, compound semiconductor materials, etc., and may have an opposite doping type with respect to collector116a, e.g., by being P-type when collector116ais N-type, or vice versa. In base film116b, the Ge concentration may be controlled to suit particular applications, and base film116bmay have a Ge concentration of, e.g., between approximately five percent and approximately fifty percent. In further implementations, base film116bmay include any currently known or later developed compound semiconductor material, e.g., GaAs, AlGaAs, SiC, GaN, etc. As with collector116a, base film116bmay be doped in situ to any desired concentration. Base film116bmay have a horizontal width that is greater than collector116athereunder, e.g., due to being formed partially on TI(s)110adjacent collector116a. As base film116bis formed, semiconductor material may be formed indiscriminately on collector116aand other materials adjacent collector116a, thereby completely covering the underling materials. Thereafter, portions of base film116bnot located on collector116aand/or TI(s)110may be removed, e.g., by masking and etching base film116bsuch that it remains only over collector116a, and partially over TI(s)110. Forming base film116bin this manner causes some portions of base film116bto have a crystalline composition, while other portions of base film116bmay be partially crystalline or non-crystalline. Forming base film116bby epitaxy and/or similar processes for growth of semiconductor material may cause base film116bto include a crystalline region117on collector116a, due to replicating the crystallographic orientation of semiconductor materials in collector116a. However, the same deposition and/or epitaxial growth may cause any semiconductor material(s) formed on TI(s)110to be non-crystalline. Thus, base film116bmay include one or more non-crystalline regions118on TI(s)110. The differences in crystallographic configuration between crystalline region117and non-crystalline region118may cause non-crystalline region118to have a greater height above substrate102than crystalline region117. Notwithstanding these differences in crystallographic structure, crystalline region117and non-crystalline region118each may be considered to be portions of base film116b.

An emitter116cmay be formed on a portion of base film116bby deposition and/or epitaxial growth, and emitter116cmay have the same doping type as collector116aof BJT stack116. Emitter116cmay include any material capable of being included within collector116aand/or other semiconductive materials, e.g., SiGe, compound semiconductor materials, and/or other materials with similar properties. Emitter116cmay be doped to any desired concentration. In some cases, emitter116cmay have a similar doping concentration as collector116a. The emitter116cmaterial may be doped in situ during epitaxial growth or may be doped after the emitter material is deposited. Some portions of emitter116cmay be removed, e.g., through controlled epitaxial growth on base film116band/or using masks. Here, the width of emitter116cis less than the width of base film116b. Together, collector116a, base film116b, and emitter116cmay form alternating P-N junctions because of their forming and doping, and thus define the three active terminals of a vertical BJT.

Continued processing may include forming a set of spacers122on sidewalls of emitter116c, and/or a spacer liner124on an upper surface of emitter116c. Spacers122may be distinguished from spacer liner124solely based on their position relative to emitter116c. That is, spacers122may be formed on the side of emitter116cwhile spacer liner124is formed on the upper surface of emitter116c. Spacers122and/or spacer liner124may be formed, e.g., by conformal deposition and etching on exposed surfaces of emitter116c. Spacer122and/or spacer liner124may be formed of a nitride insulator and/or other insulator materials described elsewhere herein with respect to TI(s)110and/or other insulative materials. Spacers122and/or spacer liner124also may be formed, e.g., on substrate102, TI(s)110, and/or on portions of base film116b. The portions of spacers122and/or spacer liners124formed on structures other than emitter116cmay be removed by vertical etching and, hence, are not shown inFIG.2. Such vertical etching may be implemented with a mask (not shown) over emitter116cto prevent removing of spacers122and/or spacer liner124from emitter116c. Spacer(s)122, once formed, electrically separates emitter116cfrom other materials formed on base film116b.

Referring toFIG.3, embodiments of the disclosure include forming at least one elevated extrinsic base126on crystalline region117of base film116b. Elevated extrinsic base(s)126may be formed as a single layer, e.g., by at least partially selective epitaxial growth on crystalline region117. Multiple layers of elevated extrinsic base(s)126may be formed on top of each other in some implementations, and elevated extrinsic base(s)126additionally or alternatively may be formed as a pair on opposite sides of emitter116c. Elevated extrinsic base(s)126may include, e.g., epitaxially grown crystalline silicon germanium (SiGe). Elevated extrinsic base(s)126may be of the same doping type as base film116b(e.g., P-type or N-type depending on whether an NPN or PNP configuration is used). The epitaxially grown elevated extrinsic base(s)126may have a Ge concentration that is different (e.g., significantly higher or lower percentage) than that of base film116b. For instance, when base film116bis approximately ten percent Ge, elevated extrinsic base(s)126may have at least a twenty percent Ge concentration, or in some cases may not have any Ge. Thus, elevated extrinsic base(s)126may have a distinct Ge concentration and electrical conductivity relative to base film116b. In cases where base film116bis formed of a compound semiconductor (e.g., Ge, As, AlGaAs, SiC, GaN, etc., as described herein), elevated extrinsic base(s)126simply may have a composition that is different from base film116bthereunder. In such cases, elevated extrinsic base(s)126may include Si, Ge, and/or other materials.

The forming of elevated extrinsic base(s)126may be highly selective, such that elevated extrinsic base(s)126will grow on, and/or extend vertically upward from, crystalline region117within the perimeter of base film116b. Epitaxy refers to a process by which crystalline material is grown on existing crystalline materials (e.g., crystalline substrate). In epitaxy, growth occurs in such a way that crystallographic structure of the existing material (including defects, where applicable) is reproduced in the newly grown material. Selective epitaxy refers to a type of epitaxial in which new material is grown only on exposed Si or SiGe, and no material is grown on exposed dielectric (e.g., silicon oxide or nitride). For instance, in the case of a crystalline semiconductor that is partially covered with oxide, or a crystalline material (e.g., base film116b) adjacent a non-crystalline material (e.g., TI(s)110), newly grown semiconductor material will solely or predominantly on the existing crystalline material, while non-crystalline material will form solely or predominantly on the existing non-crystalline material, and no material with grow on the dielectric material. By contrast, non-selective epitaxy refers to a type of epitaxial growth where new material grows on all exposed surfaces, and the resulting new material is single crystal in those regions where a single crystal Si or SiGe is exposed, and is poly-crystalline on those regions where poly-crystalline or dielectric material is exposed. Those skilled in the art will be familiar with the properties of the epitaxial growth that govern the relative process selectivity, including, e.g., applied temperature and pressure, the mixture of growth precursor (e.g. SiH4 or GeH4) vs. etchant precursor (e.g. HCl or Cl2), the composition of the epitaxial growth, and the types of seed material(s) and dielectric materials. These parameters govern the relative growth rate (or lack thereof) on crystalline vs. dielectric material, but they also govern the crystal-plane dependent growth rate on a crystalline material, as well as the relative growth rate on single crystal material versus poly-crystalline material in the case that the substrate includes both single crystal and poly-crystalline seed materials. Regardless of the amount of selectivity, the boundary between TI110and base film116bmay at least partially define a boundary between crystalline and poly-crystalline or non-crystalline materials formed thereon by partially selective epitaxial growth. In the case of highly selective epitaxy, the elevated extrinsic base(s)126may not form on non-crystalline region(s)118of base film116bwhile the elevated extrinsic base126is formed on crystalline region(s)117. Thus, elevated extrinsic base(s)126may have a width that is less than the total width of base film116bthereunder. Additionally, spacer(s)122may horizontally separate elevated extrinsic base(s)126from emitter116c.

Doping of elevated extrinsic base(s)126may not occur until the subsequent forming materials on elevated extrinsic base126. Elevated extrinsic base(s)126, furthermore, may have a different material composition from other portions of BJT stack116, in addition to having different crystallographic features and/or orientation. Due to the greater height of non-crystalline region118above substrate102relative to crystalline region107, elevated extrinsic base126may be horizontally adjacent portions of non-crystalline region118. The horizontal interface between elevated extrinsic base126and non-crystalline region118may be substantially continuous with the horizontal interface between TI110and collector116a(as indicated by line S (FIG.4)). This continuity may arise from forming elevated extrinsic base126selectively on collector116a. In cases where the junction between non-crystalline region118and extrinsic base126is substantially linear or otherwise oriented along a vertical axis, this junction may be substantially aligned with the junction between TI110and collector116a(e.g., along line S). While elevated extrinsic base(s)126, can also be doped during growth (in-situ), the doping levels that may be limited by process capability. Such limitations on doping may negatively affect device performance if elevated extrinsic base(s)126is not further processed. Such concerns may be overcome, e.g., through additional doping of elevated extrinsic base126material as discussed herein.

FIG.4depicts continued processing to affect the electrical conductivity of base film116band elevated extrinsic base126, e.g., to increase electrical conductivity to BJT stack116through these components. Methods according to the disclosure may include introducing dopants into elevated extrinsic base126and nearby portions of base film116bto a desired depth. The doping of elevated extrinsic base126and adjacent portions of non-crystalline region118may include forming an ion layer128on or within exposed portions of non-crystalline region118and/or elevated extrinsic base126. It has been determined that shallow ion doping of non-crystalline region118and elevated extrinsic base126, i.e., doping to a depth above crystalline region117, prevents these dopants from migrating into opposite polarity portions of BJT stack116(e.g., into collector116awhere they are not desired). Example techniques suitable to form ion layer128include, e.g., shallow implantation, plasma doping, gas phase doping, and/or other techniques suitable to form ion layer128on targeted surfaces (e.g., those not covered by spacer(s)122and/or spacer liner124). In a more specific example, methods of the disclosure may include forming ion layer128of boron (B) and/or other dopants (e.g., p-type materials) capable of gas deposition. Additionally, the forming of ion layer128may partially planarize any non-planar surfaces, e.g., by partially filling empty space at the interface between non-crystalline region118and elevated extrinsic base126.

Referring toFIGS.5-7together, embodiments of the disclosure may include causing dopant materials (e.g., boron or other p-type materials) to migrate from ion layer128into underlying materials to yield a doped region130(FIG.6).FIG.5provides an expanded view of non-crystalline region118, elevated extrinsic base126, and doped region130. Although ion layer128(FIG.4) initially may be formed on exposed portions non-crystalline region118and elevated extrinsic base126, subsequent processing may include causing materials within ion layer128to migrate into underlying materials, e.g., by way of diffusion. An example methodology to drive dopants from ion layer128into underlying materials may include, e.g., annealing or other types of heat treatment. Any conceivable annealing process to drive-in dopants from ion layer128may be performed, e.g., a rapid thermal anneal (RTA), to enable doping of non-non-crystalline region118and elevated extrinsic base126. In this example, dopants can migrate downward into underlying materials, e.g., along the pathways shown by arrows inFIG.5. At this stage, dopant-containing regions of non-crystalline region118and elevated extrinsic base126define doped region130(FIG.6only). In a further example illustrated inFIG.7, the migration of dopants may pass through elevated extrinsic base126to reach portions of base film116bthereunder. Although the stronger dopant migration inFIG.7to produce doped regions130of greater size may be desirable, this is not necessary in all implementations.

The combination of shallow doping and subsequent dopant migration additionally can coat, and in some cases remove, any of the dimensional features that would otherwise be present on non-crystalline region118and elevated extrinsic base126. For example, an upper surface of doped region130in non-crystalline region118and elevated extrinsic base126can be substantially planar along line T. Furthermore, the horizontal interface between non-crystalline region118and elevated extrinsic base126may be substantially continuous with the horizontal interface between TI110and collector116a(e.g., along line S), as described herein. Forming doped region130may increase electrical conductivity through doped region130to elevated extrinsic base126and portions of base film116bthereunder, after subsequent contact formation. Additionally, forming doped region130may further planarize the upper surface of elevated extrinsic base(s)126, and/or further reduce topographical differences between non-crystalline region118and elevated extrinsic base(s)126.

FIG.8depicts the forming of an inter-level dielectric (ILD) layer131above substrate102; including TI(s)110, BJT stack116, and doped region(s)130over non-crystalline region118and elevated extrinsic base126. ILD layer131may be formed, e.g., by deposition or other techniques of forming an insulative material on a structure. ILD layer131may include the same insulating material as TI(s)110, or may include a different electrically insulative material. ILD layer131and TI(s)110nonetheless constitute different components, e.g., due to TI(s)110being formed within portions of substrate102instead of being formed thereon. In further embodiments (not shown), a silicide layer as known in the art could be formed on the exposed surfaces of doped region(s)130prior to ILD layer131deposition. For example, a cobalt (Co), titanium (Ti), nickel (Ni), platinum (Pt), or similar self-aligned silicide (silicide) could be formed prior to ILD layer131deposition. Additional metallization layers (not shown) may be formed on ILD layer131during middle-of-line and/or back-end-of-line processing. To electrically couple various components discussed herein to such metallization layers, a collector contact132amay be formed within ILD131to portions of substrate102that connect to collector116aof BJT stack116. At this stage, doped semiconductor region114within substrate102may electrically couple collector contact(s)132ato collector116a. Similarly, one or more base contacts132bmay be formed within ILD131for coupling to doped region(s)130and/or silicide materials therein. Portions of spacer liner124on the upper surface of emitter116cmay be removed by vertical etching (e.g., by RIE), and an emitter contact132cwithin ILD131can be formed thereon. Other portions of spacer(s)122and/or spacer liner124may remain intact after emitter contact132cis formed.

One or more of contacts132a,132b,132cto overlying circuit elements may be formed within predetermined portions of ILD layer131by a controlled amount of vertical etching to form openings to one or more contact sites, and then filling the openings with a conductor. Each contact132a,132b,132cmay include any currently known or later developed conductive material configured for use in an electrical contact, e.g., copper (Cu), aluminum (Al), gold (Au), etc. Contacts132a,132b,132cmay additionally include refractory metal liners (not shown) positioned alongside ILD layer131to prevent electromigration degradation, shorting to other components, etc. Additionally, selected portions of substrate102, doped semiconductor region114, emitter116c, and doped region(s)130may include silicide regions (i.e., portions of semiconductor that are annealed in the presence of an overlying conductor to increase the electrical conductivity of semiconductor regions) to increase the electrical conductivity at their physical interface with contact(s)132a,132b,132c, where applicable.

Embodiments of the disclosure provide an IC structure140, in which BJT stack116within substrate102has structural features that may arise from methods described herein and/or analogous techniques. BJT stack116may include collector116a, base film116bon collector116a, and emitter116con a portion of base film116b. Elevated extrinsic base126may be located on crystalline region117of base film116b, adjacent emitter116c. Spacer(s)122may be horizontally between elevated extrinsic base126and emitter116c. The germanium concentration within upper elevated extrinsic base126may be different (i.e., significantly higher or lower percentage) than the germanium concentration of within base film116b(including crystalline region117), e.g., due to the multiple instances of deposition and/or epitaxial growth. Elevated extrinsic base126may be located only on crystalline region117(i.e., not above TI(s)110, doped semiconductor region114, and/or non-crystalline region118) due to being formed by selective epitaxy on crystalline semiconductor material. Non-crystalline region118of base film116bmay be on TI110and adjacent crystalline region117, e.g., by being grown epitaxially from portions of base film116b. The upper surface of elevated extrinsic base126along doped region130may be substantially coplanar with the upper surface of non-crystalline region118along doped region130, e.g., as indicated through line T. In this case, IC structure140is substantially free of topographical features (e.g., height differences) along the junction between base contact(s)132cand doped region(s)130thereunder.

Embodiments of the disclosure provide various technical and commercial advantages. Some advantages of the disclosure may include, e.g., providing an elevated extrinsic base that is substantially planar along its upper surface, despite the presence of non-crystalline region118adjacent elevated extrinsic base126. Embodiments of the disclosure substantially eliminate the presence of topographical features on base contacts to IC structure140, thereby improving device performance and scalability. Such benefits may arise in part from selective epitaxial growth of elevated extrinsic base126on crystalline region117(e.g., without also being formed on non-crystalline region118), as well as from shallow doping of non-crystalline region118and elevated extrinsic base126to yield doped region(s)130in each element.