Phase-locked loop with phase information multiplication

A phase-locked loop (PLL) includes a phase-frequency detector that compares a reference signal to a feedback signal. The difference in phase between the reference signal and the feedback signal is encoded as digital pulses on one or more outputs of the phase-frequency detector. The digital output pulses from the phase-frequency detector are duplicated and delayed multiple times in a non-overlapping manner before being input to the loop filter or voltage controlled oscillator (VCO) of the PLL.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG.1is a block diagram illustrating a phase-locked loop configuration with phase information multiplication.

FIG.2is a waveform illustration of phase information multiplication.

FIG.3is a block diagram illustrating a phase-locked loop configuration with late/early pulse multiplication.

FIG.4Ais a waveform illustration of late/early pulse multiplication.

FIG.4Bis a waveform illustration multiplied phase information.

FIG.5Ais a block diagram illustrating a first proportional-integral (PI) phase-locked loop configuration with phase information multiplication.

FIG.5Bis a block diagram illustrating a second proportional-integral (PI) phase-locked loop configuration with phase information multiplication.

FIG.5Cis a block diagram illustrating a third proportional-integral (PI) phase-locked loop configuration with phase information multiplication.

FIG.6is a block diagram illustrating an example inductance-capacitance (LC) voltage controlled oscillator.

FIG.7is a flowchart illustrating a method of multiplying phase information in a phase-locked loop.

FIG.8is a schematic diagram illustrating an example pulse-multiplier.

FIG.9is a schematic diagram illustrating second example of a pulse-multiplier.

FIG.10is a block diagram of a processing system.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Phase-locked loops (PLLs) are control systems that generate output signals whose phase is related (e.g., shifted, frequency multiplied, etc.) to the phase of a reference input signal. Phase-locked loops can be, for example, used to demodulate a signal (e.g., a frequency modulated signal), recover a signal from a noisy communication channel, generate a stable frequency at multiples of an input frequency (a.k.a., frequency synthesis), clock recovery, clock-data deskewing, and to distribute precisely timed clock pulses (e.g., to parts of an integrated circuit.)

In some PLL applications, phase events on the reference input signal occur relatively infrequently when compared to the output signal. For example, in a frequency synthesis/multiplication application, the reference input signal may transition only once in a given period of time while the output signal transitions thousands of times over the same period. In these situations, the PLL control loop has a low response bandwidth as compared to the output frequency.

In an embodiment, a phase-locked loop (PLL) includes a phase-frequency detector that compares a reference signal to a feedback signal. The difference in phase between the reference signal and the feedback signal is encoded as digital pulses on one or more outputs of the phase-frequency detector. The digital output pulses from the phase-frequency detector are duplicated multiple times in a non-overlapping manner before being input to the loop filter or voltage controlled oscillator (VCO) of the PLL. This repetition of phase information can increase the bandwidth of the phase-locked loop without necessarily making changes to the digital logic levels, supply voltage, VCO capacitance/inductance, etc.

Pulse-width phase-frequency detector110receives a reference signal (REF) and a feedback compare signal (FBC). PW-PFD110operates to compare the phase of the reference signal (REF) to the feedback compare signal (FBC) and, based on that comparison, generate one or more signals that correspond the difference in phase between the two signals (e.g., both magnitude of phase difference and direction of phase difference—i.e., early or late). In an embodiment, PW-PFD110outputs digital pulses that convey information about the phase difference between the input reference signal (REF) and the feedback compare signal (FBC). The pulses output by PW-PFD110are carried on one or more phase-detector output (PDO) signals.

In an embodiment, PW-PFD110outputs pulses whose width corresponds to the phase difference between the reference signal (REF) the feedback compare signal (FBC). For example, if a particular edge of the reference signal (REF) arrives at PW-PFD110an amount of time (ΔT) before the corresponding edge of the feedback compare signal (FBC), PW-PFD110may output a pulse that is (effectively) the same amount of time, ΔT. Thus, the earlier the reference signal (REF) arrives when compared to the feedback compare signal (FBC), the longer the pulse that is output by PW-PFD110. Accordingly, in this example, the length of the pulses output by PW-PFD110convey information about the amount of phase difference between REF and FBC.

One or more phase-detector output signals (PDO) are input to pulse multiplier120. Pulse multiplier120duplicates and offsets in time the digital pulses output by phase-frequency detector110. Pulse multiplier120duplicates the digital pulses output by phase-frequency detector110and offsets the duplicates (or optionally the originals) in time from the original pulses such that the duplicated pulses do not overlap with the original (input) pulses, other duplicated pulses, or the next pulse to be output by phase-frequency detector110. The pulses output by pulse multiplier120are carried on one or more pulse multiplier output (PMO) signals. By multiplying the digital pulses output by phase-frequency detector110, the effect of the phase information carried by a single pulse is likewise multiplied. This effectively increased the proportional gain of the PLL100feedback loop without modifying the other components.

The pulse multiplier120output pulses on PMO are provided to charge pump160, if present. The output of charge pump160(CPO), if present, is provided to loop filter130. Charge pump160receives the pulses output by pulse multiplier120and converts them to a current and/or voltage that is suitable for loop filter130. If charge pump160is not present, pulse multiplier output pulses on PMO are provided directly to loop filter130. Thus, if charge pump160is not present, loop filter130is adapted (e.g., by using digital logic, an internal charge pump, switched capacitors, digital filtering, etc.) to receive the pulses from pulse multiplier120directly. The output of loop filter130controls the frequency of the signal (OUT) output by VCO140. In an embodiment, loop filter130may be part of VCO140. The output of VCO140(OUT) is typically the output of phase-locked loop configuration100.

VCO140may comprise voltage controlled capacitors that are part of an inductance-capacitance resonant circuit (a.k.a., LC circuit, LC tank circuit, LC tuned circuit, etc.) The bias voltage on one or more voltage controlled capacitors of VCO140may be based on the signal received from loop filter130(and/or pulse multiplier120.)

VCO140may comprise capacitors that are selectively switched in and out of an inductance-capacitance resonant circuit. These capacitors may be selectively switched in to, and out of, the inductance-capacitance resonant circuit based on digital control signals. These digital control signals may be based on one or more analog and/or digital values received from loop filter130and/or pulse multiplier120.

The output of VCO140(OUT) is fed back to the input of phase-frequency detector110. Optionally, the frequency of the output of VCO140may be divided down to a lower frequency by feedback divider150. The output of feedback divider150, when present, is feedback compare signal, FBC. When feedback divider150divides by 1, the frequency of FBC is the same as the frequency of OUT. When feedback divider150is not present at all, the feedback compare signal FBC is also the output of VCO140(OUT).

FIG.2is a waveform illustration of phase information multiplication. The waveforms illustrated inFIG.2may correspond to one or more signals of phase-locked loop configuration100. InFIG.2, the rising edge of a reference signal (REF) leads the rising edge of a feedback compare signal (FBC). In other words, the feedback compare signal (FBC) has a later phase than the reference signal. The amount of phase difference (i.e., phase information) between the reference signal (REF) and the feedback compare signal (FBC) is reflected by a pulse on the PDO signal (e.g., an output from PW-PFD110.) The width of the pulse on the PDO signal (i.e., phase information) is determined by the difference in time (i.e., phase) between the rising edge of REF and the rising edge of FBC. This is illustrated inFIG.2by arrows202and204.

InFIG.2, the pulse on the PDO signal is output three times on the signal PMO (e.g., an output from pulse multiplier120.) This is an example number of replications/duplications. It should be understood that the maximum number of output pulses is determined by the maximum pulse duration and period of the reference signal (REF). The pass-through and/or replication of the pulses on the PDO signal is illustrated inFIG.2by arrows206-208.

Pulse-width phase-frequency detector310receives a reference signal (REF) and a feedback compare signal (FBC). PW-PFD310operates to compare the phase of the reference signal (REF) to the feedback compare signal (FBC) and, based on that comparison, generate signals PDUP and PDDN that correspond the difference in phase between the two signals (i.e., PDUP and PDDN, collectively convey the magnitude of phase difference and direction of phase difference—i.e., early or late). In an embodiment, PW-PFD310outputs digital pulses on PDUP and PDDN that convey information about the phase difference between the input reference signal (REF) and the feedback compare signal (FBC).

The pulses output by PW-PFD310are carried on PDUP and PDDN. For example, when the reference signal (REF) is earlier than the feedback compare signal (FBC), PW-PFD310will output at least one pulse on the PDUP signal that leads (or is longer than, or both) the pulse on the PDDN by an amount that is equal to, or proportional to, or corresponds to, the amount of time the reference signal (REF) leads the feedback compare signal (FBC). Likewise, when the reference signal (REF) is later than the feedback compare signal (FBC), PW-PFD310will output at least one pulse on the PDDN signal that leads (or is longer than, or both) the pulse on the PDUP by an amount that is equal to, or proportional to, or corresponds to, the amount of time the reference signal (REF) lags the feedback compare signal (FBC). Thus, PW-PFD310outputs pulses on PDUP and PDDN that convey information corresponding to the phase difference between the reference signal (REF) the feedback compare signal (FBC).

In an embodiment, the pulses on both signals PDUP and PDDN may have a minimum pulse width, and extra width is added to one of them to indicate the phase difference and lag/lead. Thus, in this embodiment, the phase difference is conveyed by the difference between the two pulse widths. In other words, PW-PFD310outputs pulses on PDUP and PDDN whose lengths convey the phase difference between the reference signal (REF) the feedback compare signal (FBC)—but are not equal to the amount of phase difference. The phase difference is conveyed by the difference between the two pulse widths on PDUP and PDDN. In another embodiment where there is no minimum pulse width on PDUP and PDDN, the signal the pulses appear on, PDUP or PDDN, may convey the direction (early or late) of the phase difference.

For example, if a particular edge of the reference signal (REF) arrives at PW-PFD310an amount of time (ΔT) before the corresponding edge of the feedback compare signal (FBC), PW-PFD310may output a pulse that is (effectively) the same amount of time, ΔT on PDUP (or a minimum length pulse that is increased by ΔT.) Thus, the earlier the reference signal (REF) arrives when compared to the feedback compare signal (FBC), the longer the pulse that is output by PW-PFD310on PDUP. Likewise, if a particular edge of the reference signal (REF) arrives at PW-PFD310an amount of time (ΔT) after the corresponding edge of the feedback compare signal (FBC), PW-PFD310may output a pulse that is (effectively) the same amount of time, ΔT on PDDN (or a minimum length pulse that is increased by ΔT). Thus, the later the reference signal (REF) arrives when compared to the feedback compare signal (FBC), the longer the pulse that is output by PW-PFD310on PDDN. Accordingly, in this example, the length of the pulses output by PW-PFD310on PDUP and PDDN convey information about the amount of phase difference between REF and FBC.

The PDUP phase-detector output signal is input to up pulse multiplier321. Up pulse multiplier321duplicates and offsets in time the pulses on PDUP output by phase-frequency detector310. Up pulse multiplier321duplicates the digital pulses on PDUP output by phase-frequency detector310and offsets the duplicates (or optionally the originals) in time from the original pulses such that the duplicated pulses on PDUP do not overlap with the original (input) pulses, other duplicated pulses on PDUP, or the next PDUP pulse to be output by phase-frequency detector310.

Likewise, The PDDN phase-detector output signal is input to down pulse multiplier322. Down pulse multiplier322duplicates and offsets in time the pulses on PDDN output by phase-frequency detector310. Down pulse multiplier322duplicates the digital pulses on PDDN output by phase-frequency detector310and offsets the duplicates (or optionally the originals) in time from the original pulses such that the duplicated pulses on PDDN do not overlap with the original (input) pulses, other duplicated pulses on PDDN, or the next PDDN pulse to be output by phase-frequency detector310.

The pulses output by up pulse multiplier321are carried on one or more up pulse multiplier output (PMUP) signals. By multiplying the up direction digital pulses output by phase-frequency detector310, the effect of the phase information carried by a single up direction pulse is likewise multiplied. This can effectively increase the proportional gain of the PLL300feedback loop without necessarily requiring modification of the other components.

Likewise, the pulses output by down pulse multiplier322are carried on one or more down pulse multiplier output (PMDN) signals. By multiplying the down direction digital pulses output by phase-frequency detector310, the effect of the phase information carried by a single down direction pulse is likewise multiplied. This can effectively increase the proportional gain of the PLL300feedback loop without necessarily requiring modification of other components.

The pulse multiplier output pulses on PMUP and PMDN are provided to charge pump360, if present. The outputs of charge pump360(CPUP, CPDN), if present, are provided to loop filter330. Charge pump360receives the pulses output by up pulse multiplier321and down pulse multiplier322. Charge pump360converts the pulses on PMUP and PMDN to currents and/or voltages on CPUP and CPDN that are suitable for loop filter330. If charge pump360is not present, the pulse multiplier output pulses on PMUP and PMDN are provided directly to loop filter330. Thus, if charge pump360is not present, loop filter330is adapted (e.g., by using digital logic, an internal charge pump, switched capacitors, digital filtering, etc.) to receive the pulses from up pulse multiplier321and down pulse multiplier322directly. The output of loop filter330controls the frequency of the signal (OUT) output by VCO340. In an embodiment, loop filter330may be part of VCO340. The output of VCO340(OUT) is typically the output of phase-locked loop configuration300.

VCO340may comprise voltage controlled capacitors that are part of an inductance-capacitance resonant circuit (a.k.a., LC circuit, LC tank circuit, LC tuned circuit, etc.) The bias voltage on one or more voltage controlled capacitors of VCO340may be based on the signals received from loop filter330(and/or pulse multipliers321-322.)

VCO340may comprise capacitors that are selectively switched in and out of an inductance-capacitance resonant circuit. These capacitors may be selectively switched in to, and out of, the inductance-capacitance resonant circuit based on digital control signals. These digital control signals may be based on one or more analog and/or digital values received from loop filter330and/or pulse multipliers321-322.

The output of VCO340(OUT) is fed back to the input of phase-frequency detector310. Optionally, the frequency of the output of VCO340may be divided down to a lower frequency by feedback divider350. The output of feedback divider350, when present, is feedback compare signal, FBC. When feedback divider350divides by 1, the frequency of FBC is the same as the frequency of OUT. When feedback divider350is not present at all, the feedback compare signal FBC is also the output of VCO340(OUT).

FIG.4Ais a waveform illustration of late/early pulse multiplication. The waveforms illustrated inFIGS.4A and4Bmay correspond to one or more signals of phase-locked loop configuration300. InFIG.4A, the rising edge of a reference signal (REF) leads the rising edge of a feedback compare signal (FBC). In other words, the feedback compare signal (FBC) has a later phase than the reference signal. The amount of phase difference (i.e., phase information) between the reference signal (REF) and the feedback compare signal (FBC) is reflected by a portion of the pulse on the PDUP signal. The difference between the rising edge of a pulse on the PDUP signal and the corresponding rising edge of a pulse on the PDDN signal carries the phase information. This difference is determined by the difference in time (i.e., phase) between the rising edge of REF and the rising edge of FBC. This is illustrated inFIG.4Aby arrows402and403.

InFIG.4A, the pulse on the PDUP signal is output three times on the signal PMUP. Likewise, the pulse on the PDDN signal is output three times on the signal PMDN. Thus, the difference in time between the rising edges of the PDUP and PDDN signals (phase information) is output three times. This is an example number of replications. The pass-through and/or replication of the pulses on the PDUP signal is illustrated inFIG.4Aby arrows404-406. The pass-through and/or replication of the pulses on the PDDN signal is illustrated inFIG.4Aby arrows407-409.

The replication of the phase information is further illustrated inFIG.4B.FIG.4Bis a waveform illustration multiplied phase information.FIG.4Bhas the same waveform relationships asFIG.4A. However, the difference in time between the rising edges of the PDUP and PDDN signals (phase information) is emphasized by areas410,411, and420. Likewise, the difference in time (multiplied phase information) between the rising edges of the pulses on the PMUP and PMDN signals is emphasized by areas411-413and421-422.

Pulse-width phase-frequency detector510receives a reference signal (REF) and a feedback compare signal (FBC). PW-PFD510operates to compare the phase of the reference signal (REF) to the feedback compare signal (FBC) and, based on that comparison, generate signals PDUP and PDDN that correspond the difference in phase between the two signals (i.e., PDUP and PDDN, collectively convey the magnitude of phase difference and direction of phase difference—i.e., early or late). In an embodiment, PW-PFD510outputs digital pulses that convey information about the phase difference between the input reference signal (REF) and the feedback compare signal (FBC).

The pulses output by PW-PFD510are carried on PDUP and PDDN. For example, when the reference signal (REF) is earlier than the feedback compare signal (FBC), PW-PFD510will output at least one pulse on the PDUP signal that leads (or is longer than, or both) the pulse on the PDDN by an amount that is equal to, or proportional to, or corresponds to, the amount of time the reference signal (REF) leads the feedback compare signal (FBC). Likewise, when the reference signal (REF) is later than the feedback compare signal (FBC), PW-PFD510will output at least one pulse on the PDDN signal that leads (or is longer than, or both) the pulse on the PDUP by an amount that is equal to, or proportional to, or corresponds to, the amount of time the reference signal (REF) lags the feedback compare signal (FBC). Thus, PW-PFD510outputs pulses on PDUP and PDDN that convey information corresponding to the phase difference between the reference signal (REF) the feedback compare signal (FBC).

In an embodiment, the pulses on both signals PDUP and PDDN may have a minimum pulse width, and extra width is added to one of them to indicate the phase difference and lag/lead. Thus, in this embodiment, the phase difference is conveyed by the difference between the two pulse widths. In other words, PW-PFD510outputs pulses on PDUP and PDDN whose lengths convey the phase difference between the reference signal (REF) the feedback compare signal (FBC)—but are not equal to the amount of phase difference. The phase difference is conveyed by the difference between the two pulse widths on PDUP and PDDN. In another embodiment where there is no minimum pulse width on PDUP and PDDN, the signal the pulses appear on, PDUP or PDDN, may convey the direction (early or late) of the phase difference.

For example, if a particular edge of the reference signal (REF) arrives at PW-PFD510an amount of time (ΔT) before the corresponding edge of the feedback compare signal (FBC), PW-PFD510may output a pulse that is (effectively) the same amount of time, ΔT on PDUP (or a minimum length pulse that is increased by ΔT.) Thus, the earlier the reference signal (REF) arrives when compared to the feedback compare signal (FBC), the longer the pulse that is output by PW-PFD510on PDUP. Likewise, if a particular edge of the reference signal (REF) arrives at PW-PFD510an amount of time (ΔT) after the corresponding edge of the feedback compare signal (FBC), PW-PFD510may output a pulse that is (effectively) the same amount of time, ΔT on PDDN (or a minimum length pulse that is increased by ΔT.) Thus, the later the reference signal (REF) arrives when compared to the feedback compare signal (FBC), the longer the pulse that is output by PW-PFD510on PDDN. Accordingly, in this example, the length of the pulses output by PW-PFD510on PDUP and PDDN convey information about the amount of phase difference between REF and FBC.

The PDUP phase-detector output signal is input to up pulse multiplier521. Up pulse multiplier521duplicates and offsets in time the pulses on PDUP output by phase-frequency detector510. Up pulse multiplier521duplicates the digital pulses on PDUP output by phase-frequency detector510and offsets the duplicates (or optionally the originals) in time from the original pulses such that the duplicated pulses on PDUP do not overlap with the original (input) pulses, other duplicated pulses on PDUP, or the next PDUP pulse to be output by phase-frequency detector510.

Likewise, The PDDN phase-detector output signal is input to down pulse multiplier522. Down pulse multiplier522duplicates and offsets in time the pulses on PDDN output by phase-frequency detector510. Down pulse multiplier522duplicates the digital pulses on PDDN output by phase-frequency detector510and offsets the duplicates (or optionally the originals) in time from the original pulses such that the duplicated pulses on PDDN do not overlap with the original (input) pulses, other duplicated pulses on PDDN, or the next PDDN pulse to be output by phase-frequency detector510.

The pulses output by up pulse multiplier521are carried on one or more up pulse multiplier output (PMUP) signals. By multiplying the up direction digital pulses output by phase-frequency detector510, the effect of the phase information carried by a single up direction pulse is likewise multiplied. This can effectively increase the proportional gain of the PLL500feedback loop without necessarily requiring modification of other components.

Likewise, the pulses output by down pulse multiplier522are carried on one or more down pulse multiplier output (PMDN) signals. By multiplying the down direction digital pulses output by phase-frequency detector510, the effect of the phase information carried by a single down direction pulse is likewise multiplied. This effectively increases the proportional gain of the PLL500feedback loop without modifying the other components.

The pulse multiplier output pulses on PMUP and PMDN are provided to charge pump560, if present. The outputs of charge pump560(CPUP, CPDN), if present, are provided to proportional loop filter530and integral loop filter531. Charge pump560receives the pulses output by up pulse multiplier521and down pulse multiplier522. Charge pump560converts the pulses on PMUP and PMDN to currents and/or voltages on CPUP and CPDN that are suitable for loop filter530and integral loop filter531. If charge pump560is not present, pulse multiplier output pulses on PMUP and PMDN are provided directly to proportional loop filter530and integral loop filter531. Thus, if charge pump560is not present, loop filter530and integral loop filter531are adapted (e.g., by using digital logic, an internal charge pump, switched capacitors, digital filtering, etc.) to receive the pulses from up pulse multiplier521and down pulse multiplier522directly. The output of loop filter530is summed with the output of integral loop filter531to produce one or more signals that control the frequency of the signal (OUT) output by VCO540. In an embodiment, loop filter530and/or integral loop filter531may be part of VCO540. The output of VCO540(OUT) is typically the output of phase-locked loop configuration500.

VCO540may comprise voltage controlled capacitors that are part of an inductance-capacitance resonant circuit (a.k.a., LC circuit, LC tank circuit, LC tuned circuit, etc.) The bias voltage on one or more voltage controlled capacitors of VCO540may be based on the signals received from summing operation535.

VCO540may comprise capacitors that are selectively switched in and out of an inductance-capacitance resonant circuit. These capacitors may be selectively switched in to, and out of, the inductance-capacitance resonant circuit based on digital control signals. These digital control signals may be based on one or more analog and/or digital values received from loop filter summing operation535.

The output of VCO540(OUT) is fed back to the input of phase-frequency detector510. Optionally, the frequency of the output of VCO540may be divided down to a lower frequency by feedback divider550. The output of feedback divider550, when present, is feedback compare signal, FBC. When feedback divider550divides by 1, the frequency of FBC is the same as the frequency of OUT. When feedback divider550is not present at all, the feedback compare signal FBC is also the output of VCO540(OUT).

FIG.5Bis a block diagram illustrating a second proportional-integral phase-locked loop configuration with phase information multiplication. InFIG.5B, phase-locked loop configuration501comprises pulse-width output phase-frequency detector (PW-PFD or PFD)510, up pulse multiplier (PM)521, down pulse multiplier522, integral loop filter532, voltage-controlled oscillator (VCO)541, (optionally) feedback divider550, and (optionally) charge pump561. VCO541includes capacitors542and capacitors543that may be selectively switched in to, and out of, or biased in, an inductance-capacitance resonant circuit to determine the frequency of the output of VCO541.

Pulse-width phase-frequency detector510receives a reference signal (REF) and a feedback compare signal (FBC). PW-PFD510operates to compare the phase of the reference signal (REF) to the feedback compare signal (FBC) and, based on that comparison, generate signals PDUP and PDDN that correspond the difference in phase between the two signals (i.e., PDUP and PDDN, collectively convey the magnitude of phase difference and direction of phase difference—i.e., early or late). In an embodiment, PW-PFD510outputs digital pulses that convey information about the phase difference between the input reference signal (REF) and the feedback compare signal (FBC).

The pulses output by PW-PFD510are carried on PDUP and PDDN. For example, when the reference signal (REF) is earlier than the feedback compare signal (FBC), PW-PFD510will output at least one pulse on the PDUP signal that leads (or is longer than, or both) the pulse on the PDDN by an amount that is equal to, or proportional to, or corresponds to, the amount of time the reference signal (REF) leads the feedback compare signal (FBC). Likewise, when the reference signal (REF) is later than the feedback compare signal (FBC), PW-PFD510will output at least one pulse on the PDDN signal that leads (or is longer than, or both) the pulse on the PDUP by an amount that is equal to, or proportional to, or corresponds to, the amount of time the reference signal (REF) lags the feedback compare signal (FBC). Thus, PW-PFD510outputs pulses on PDUP and PDDN that convey information corresponding to the phase difference between the reference signal (REF) the feedback compare signal (FBC).

In an embodiment, the pulses on both signals PDUP and PDDN may have a minimum pulse width, and extra width is added to one of them to indicate the phase difference and lag/lead. Thus, in this embodiment, the phase difference is conveyed by the difference between the two pulse widths. In other words, PW-PFD510outputs pulses on PDUP and PDDN whose lengths convey the phase difference between the reference signal (REF) the feedback compare signal (FBC)—but are not equal to the amount of phase difference. The phase difference is conveyed by the difference between the two pulse widths on PDUP and PDDN. In another embodiment where there is no minimum pulse width on PDUP and PDDN, the signal the pulses appear on, PDUP or PDDN, may convey the direction (early or late) of the phase difference.

For example, if a particular edge of the reference signal (REF) arrives at PW-PFD510an amount of time (ΔT) before the corresponding edge of the feedback compare signal (FBC), PW-PFD510may output a pulse that is (effectively) the same amount of time, ΔT on PDUP (or a minimum length pulse that is increased by ΔT.) Thus, the earlier the reference signal (REF) arrives when compared to the feedback compare signal (FBC), the longer the pulse that is output by PW-PFD510on PDUP. Likewise, if a particular edge of the reference signal (REF) arrives at PW-PFD510an amount of time (ΔT) after the corresponding edge of the feedback compare signal (FBC), PW-PFD510may output a pulse that is (effectively) the same amount of time, ΔT on PDDN (or a minimum length pulse that is increased by ΔT.) Thus, the later the reference signal (REF) arrives when compared to the feedback compare signal (FBC), the longer the pulse that is output by PW-PFD510on PDDN. Accordingly, in this example, the length of the pulses output by PW-PFD510on PDUP and PDDN convey information about the amount of phase difference between REF and FBC.

The PDUP phase-detector output signal is input to up pulse multiplier521. Up pulse multiplier521duplicates and offsets in time the pulses on PDUP output by phase-frequency detector510. Up pulse multiplier521duplicates the digital pulses on PDUP output by phase-frequency detector510and offsets the duplicates (or optionally the originals) in time from the original pulses such that the duplicated pulses on PDUP do not overlap with the original (input) pulses, other duplicated pulses on PDUP, or the next PDUP pulse to be output by phase-frequency detector510.

Likewise, The PDDN phase-detector output signal is input to down pulse multiplier522. Down pulse multiplier522duplicates and offsets in time the pulses on PDDN output by phase-frequency detector510. Down pulse multiplier522duplicates the digital pulses on PDDN output by phase-frequency detector510and offsets the duplicates (or optionally the originals) in time from the original pulses such that the duplicated pulses on PDDN do not overlap with the original (input) pulses, other duplicated pulses on PDDN, or the next PDDN pulse to be output by phase-frequency detector510.

The pulses output by up pulse multiplier521are carried on one or more up pulse multiplier output (PMUP) signals. By multiplying the up direction digital pulses output by phase-frequency detector510, the effect of the phase information carried by a single up direction pulse is likewise multiplied. This effectively increases the proportional gain of the PLL501feedback loop without modifying the other components.

Likewise, the pulses output by down pulse multiplier522are carried on one or more down pulse multiplier output (PMDN) signals. By multiplying the down direction digital pulses output by phase-frequency detector510, the effect of the phase information carried by a single down direction pulse is likewise multiplied. This effectively increases the proportional gain of the PLL501feedback loop without modifying the other components.

The pulse multiplier output pulses on PMUP and PMDN are provided to capacitors542of VCO541. PW-PFD510outputs PDUP and PDDN are provided to charge pump561, if present. The outputs of charge pump561(CPUP, CPDN), if present, are provided to integral loop filter532. Charge pump561receives the pulses output by PW-PFD510. Charge pump561converts the pulses on PDUP and PDDN to currents and/or voltages on CPUP and CPDN that are suitable for integral loop filter532. If charge pump560is not present, the PW-PFD outputs PDUP and PDDN are provided directly to integral loop filter532. Thus, if charge pump561is not present, integral loop filter532is adapted (e.g., by using digital logic, an internal charge pump, switched capacitors, digital filtering, etc.) to receive the pulses from PW-PFD510directly. The pulses on PMUP and PMDN control the frequency of the signal (OUT) output by VCO541by determining which (and how many) of capacitors542are selectively switched in to, and out of, the inductance-capacitance resonant circuit that determines the frequency of the output of VCO541. Likewise, the output of integral loop filter532determines which (and how many) of capacitors543are selectively switched in to, and out of, or biased in, the inductance-capacitance resonant circuit that determines the frequency of the output of VCO541. The output of VCO541(OUT) is typically the output of phase-locked loop configuration501.

The output of VCO541(OUT) is fed back to the input of phase-frequency detector510. Optionally, the frequency of the output of VCO541may be divided down to a lower frequency by feedback divider550. The output of feedback divider550, when present, is feedback compare signal, FBC. When feedback divider550divides by 1, the frequency of FBC is the same as the frequency of OUT. When feedback divider550is not present at all, the feedback compare signal FBC is also the output of VCO541(OUT).

FIG.5Cis a block diagram illustrating a third proportional-integral phase-locked loop configuration with phase information multiplication. InFIG.5C, phase-locked loop configuration502comprises pulse-width output phase-frequency detector (PW-PFD or PFD)510, up pulse multiplier (PM)521, down pulse multiplier522, integral loop filter533, voltage-controlled oscillator (VCO)541, (optionally) feedback divider550, and (optionally) charge pump562. VCO541includes capacitors542and capacitors543that may be selectively switched in to, and out of, or biased in, an inductance-capacitance resonant circuit to determine the frequency of the output of VCO541.

Pulse-width phase-frequency detector510receives a reference signal (REF) and a feedback compare signal (FBC). PW-PFD510operates to compare the phase of the reference signal (REF) to the feedback compare signal (FBC) and, based on that comparison, generate signals PDUP and PDDN that correspond the difference in phase between the two signals (i.e., PDUP and PDDN, collectively convey the magnitude of phase difference and direction of phase difference—i.e., early or late). In an embodiment, PW-PFD510outputs digital pulses that convey information about the phase difference between the input reference signal (REF) and the feedback compare signal (FBC).

The pulses output by PW-PFD510are carried on PDUP and PDDN. For example, when the reference signal (REF) is earlier than the feedback compare signal (FBC), PW-PFD510will output at least one pulse on the PDUP signal that leads (or is longer than, or both) the pulse on the PDDN by an amount that is equal to, or proportional to, or corresponds to, the amount of time the reference signal (REF) leads the feedback compare signal (FBC). Likewise, when the reference signal (REF) is later than the feedback compare signal (FBC), PW-PFD510will output at least one pulse on the PDDN signal that leads (or is longer than, or both) the pulse on the PDUP by an amount that is equal to, or proportional to, or corresponds to, the amount of time the reference signal (REF) lags the feedback compare signal (FBC). Thus, PW-PFD510outputs pulses on PDUP and PDDN that convey information corresponding to the phase difference between the reference signal (REF) the feedback compare signal (FBC).

In an embodiment, the pulses on both signals PDUP and PDDN may have a minimum pulse width, and extra width is added to one of them to indicate the phase difference and lag/lead. Thus, in this embodiment, the phase difference is conveyed by the difference between the two pulse widths. In other words, PW-PFD510outputs pulses on PDUP and PDDN whose lengths convey the phase difference between the reference signal (REF) the feedback compare signal (FBC)—but are not equal to the amount of phase difference. The phase difference is conveyed by the difference between the two pulse widths on PDUP and PDDN. In another embodiment where there is no minimum pulse width on PDUP and PDDN, the signal the pulses appear on, PDUP or PDDN, may convey the direction (early or late) of the phase difference.

For example, if a particular edge of the reference signal (REF) arrives at PW-PFD510an amount of time (ΔT) before the corresponding edge of the feedback compare signal (FBC), PW-PFD510may output a pulse that is (effectively) the same amount of time, ΔT on PDUP (or a minimum length pulse that is increased by ΔT.) Thus, the earlier the reference signal (REF) arrives when compared to the feedback compare signal (FBC), the longer the pulse that is output by PW-PFD510on PDUP. Likewise, if a particular edge of the reference signal (REF) arrives at PW-PFD510an amount of time (ΔT) after the corresponding edge of the feedback compare signal (FBC), PW-PFD510may output a pulse that is (effectively) the same amount of time, ΔT on PDDN (or a minimum length pulse that is increased by ΔT.) Thus, the later the reference signal (REF) arrives when compared to the feedback compare signal (FBC), the longer the pulse that is output by PW-PFD510on PDDN. Accordingly, in this example, the length of the pulses output by PW-PFD510on PDUP and PDDN convey information about the amount of phase difference between REF and FBC.

The PDUP phase-detector output signal is input to up pulse multiplier521. Up pulse multiplier521duplicates and offsets in time the pulses on PDUP output by phase-frequency detector510. Up pulse multiplier521duplicates the digital pulses on PDUP output by phase-frequency detector510and offsets the duplicates (or optionally the originals) in time from the original pulses such that the duplicated pulses on PDUP do not overlap with the original (input) pulses, other duplicated pulses on PDUP, or the next PDUP pulse to be output by phase-frequency detector510.

Likewise, The PDDN phase-detector output signal is input to down pulse multiplier522. Down pulse multiplier522duplicates and offsets in time the pulses on PDDN output by phase-frequency detector510. Down pulse multiplier522duplicates the digital pulses on PDDN output by phase-frequency detector510and offsets the duplicates (or optionally the originals) in time from the original pulses such that the duplicated pulses on PDDN do not overlap with the original (input) pulses, other duplicated pulses on PDDN, or the next PDDN pulse to be output by phase-frequency detector510.

The pulses output by up pulse multiplier521are carried on one or more up pulse multiplier output (PMUP) signals. By multiplying the up direction digital pulses output by phase-frequency detector510, the effect of the phase information carried by a single up direction pulse is likewise multiplied. This effectively increases the proportional and integral gain of the PLL502feedback loop without modifying the other components.

Likewise, the pulses output by down pulse multiplier522are carried on one or more down pulse multiplier output (PMDN) signals. By multiplying the down direction digital pulses output by phase-frequency detector510, the effect of the phase information carried by a single down direction pulse is likewise multiplied. This effectively increases the proportional and integral gain of the PLL502feedback loop without modifying the other components.

The pulse multiplier output pulses on PMUP and PMDN are provided to capacitors542of VCO541. The pulse multiplier output pulses on PMUP and PMDN are provided to charge pump562, if present. Charge pump562receives the pulses output by up pulse multiplier521and down pulse multiplier522. Charge pump562converts the pulses on PMUP and PMDN to currents and/or voltages on CPUP and CPDN that are suitable for integral loop filter533. The outputs of charge pump562, if present, are provided to integral loop filter533. If charge pump562is not present, the pulse multiplier output pulses on PMUP and PMDN are provided directly to integral loop filter533. Thus, if charge pump562is not present, integral loop filter533is adapted (e.g., by using digital logic, an internal charge pump, switched capacitors, digital filtering, etc.) to receive the pulses from up pulse multiplier521and down pulse multiplier522directly. The pulses on PMUP and PMDN control the frequency of the signal (OUT) output by VCO541by determining which (and how many) of capacitors542are selectively switched in to, and out of, the inductance-capacitance resonant circuit that determines the frequency of the output of VCO541. Likewise, the output of integral loop filter533determines which (and how many) of capacitors543are selectively switched in to, out of, or biased, in the inductance-capacitance resonant circuit that determines the frequency of the output of VCO541. The output of VCO541(OUT) is typically the output of phase-locked loop configuration502.

The output of VCO541(OUT) is fed back to the input of phase-frequency detector510. Optionally, the frequency of the output of VCO541may be divided down to a lower frequency by feedback divider550. The output of feedback divider550, when present, is feedback compare signal, FBC. When feedback divider550divides by 1, the frequency of FBC is the same as the frequency of OUT. When feedback divider550is not present at all, the feedback compare signal FBC is also the output of VCO541(OUT).

FIG.6is a block diagram illustrating an example inductance-capacitance (LC) voltage controlled oscillator. Voltage controlled oscillator600may be used as, or be part of, VCO140, VCO340, VCO540, and/or VCO541. InFIG.6, voltage controlled oscillator600comprises positive feedback circuitry610, variable capacitance circuitry620, and inductance circuitry630. Inductance circuitry630may comprise an on-chip and/or an off-chip inductor. Variable capacitance circuitry620may comprise one or more voltage controlled capacitors. Variable capacitance circuitry620may comprise one or more voltage static capacitors that are switched in to, or out of, the capacitance presented by variable capacitance circuitry620.

Variable capacitance circuitry620is in parallel with inductance circuitry630to form an inductance-capacitance resonant circuit. Positive feedback circuit610is connected to variable capacitance circuitry620and inductance circuitry630to maintain the oscillation of VCO600. A frequency control input is received by variable capacitance circuitry620. In response to changes to the frequency control input, the amount of capacitance provided by variable capacitance circuitry620to the inductance-capacitance resonant circuit is changed—thereby changing the frequency output by VCO600.

FIG.7is a flowchart illustrating a method of multiplying phase information in a phase-locked loop. The steps illustrated inFIG.7may be performed by one or more elements of phase-locked loop configuration100, phase-locked loop configuration300, and/or phase-locked loop configuration500,501and502. From a phase frequency detector, an input signal comprising a phase indicator pulse is received (702). For example, pulse multiplier120may receive a pulse with phase information from phase frequency detector110. In another example, up pulse multiplier321and down pulse multiplier322may receive pulses whose relationship to each other (e.g., timing) convey phase information from phase frequency detector310.

A plurality of replica phase indicator pulses that do not overlap each other in time are produced (704). For example, pulse multiplier120may replicate pulses received from phase frequency detector110at least two times. In another example, up pulse multiplier321and down multiplier322may replicate pulses received from phase frequency detector310at least two times.

The plurality of replica phase indicator pulses are provided to at least a proportional control input that affects a frequency output by a controllable variable frequency oscillator that is included in a phase locked loop configuration (706). For example, the replicated pulses output by pulse multiplier120may be provided to loop filter130which is coupled to control the frequency output by VCO140. In another example, the pulses output by up pulse multiplier321and down multiplier322may be provided to (optionally present) charge pump360or (as appropriate) loop filter330which is coupled to control the frequency output by VCO340. In another example, the pulses output by up pulse multiplier521and down multiplier522may be provided to proportional loop filter530which is coupled to affect the frequency output by VCO540. In another example, the pulses output by pulse multiplier521and down multiplier522may be coupled directly to capacitors542to affect the frequency output of VCO541, while the pulses output by PW-PFD510are provided to charge pump561and integral loop filter532and couple to capacitors543to affect the frequency output of VCO541.

FIG.8is a schematic diagram illustrating an example pulse-multiplier. Pulse multiplier800may be used as, or be part of, pulse multiplier120, up pulse multiplier321, down pulse multiplier322, up pulse multiplier521, and/or down pulse multiplier522. InFIG.8, pulse multiplier800comprises N number of delay elements891-893, which may have fixed or adjustable delay, and OR gate895. The input signal to be multiplied (e.g., PDUP or PDDN) is operatively coupled to a first input of OR gate895. The input signal to be multiplied is also operatively coupled to the inputs of delay elements891-893. Each of delay elements891-893has an enable input (EN) that controls whether that respective delay element will provide a delayed version of the signal at its input. This enable input allows the number of replicas provided by pulse multiplier800to be controlled. The outputs of delay elements891-893are provided to respective inputs of OR gate895. The output of OR-gate895is also the output of pulse multiplier800.

FIG.9is a schematic diagram illustrating second example of a pulse-multiplier. Pulse multiplier900may be used as, or be part of, pulse multiplier120, up pulse multiplier321, down pulse multiplier322, up pulse multiplier521, and/or down pulse multiplier522. InFIG.9, pulse multiplier900comprises N number of delay elements991-993, which may have fixed or adjustable delay, and OR gate995. The input signal to be multiplied (e.g., PDUP or PDDN) is operatively coupled to a first input of OR gate995. The input signal to be multiplied is also operatively coupled to the input of delay elements991. The output of delay element991is operatively coupled to the input of delay element992. The output of delay element992is input to the next delay element (not shown inFIG.9), and so on in a daisy chain fashion. Each of delay elements991-993has an enable input (EN) that controls whether that respective delay element will provide a delayed version of the signal at its input. This enable input allows the number of replicas provided by pulse multiplier900to be controlled. The outputs of delay elements991-993are provided to respective inputs of OR gate995. The output of OR-gate995is also the output of pulse multiplier900.

The methods, systems and devices described above may be implemented in computer systems, or stored by computer systems. The methods described above may also be stored on a non-transitory computer readable medium. Devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. This includes, but is not limited, to one or more elements of phase-locked loop configuration100, phase-locked loop configuration300, phase-locked loop configuration500, phase-locked loop configuration501, phase-locked loop configuration502, and their components. These software descriptions may be: behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves.

Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email. Note that physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 10 mm magnetic tape, 3½ inch floppy media, CDs, DVDs, and so on.

FIG.10is a block diagram illustrating one embodiment of a processing system1000for including, processing, or generating, a representation of a circuit component1020. Processing system1000includes one or more processors1002, a memory1004, and one or more communications devices1006. Processors1002, memory1004, and communications devices1006communicate using any suitable type, number, and/or configuration of wired and/or wireless connections1008.

Processors1002execute instructions of one or more processes1012stored in a memory1004to process and/or generate circuit component1020responsive to user inputs1014and parameters1016. Processes1012may be any suitable electronic design automation (EDA) tool or portion thereof used to design, simulate, analyze, and/or verify electronic circuitry and/or generate photomasks for electronic circuitry. Representation1020includes data that describes all or portions of phase-locked loop configuration100, phase-locked loop configuration300, phase-locked loop configuration500, phase-locked loop configuration501, phase-locked loop configuration502, and their components, as shown in the Figures.

Representation1020may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, representation1020may be stored on storage media or communicated by carrier waves.

Data formats in which representation1020may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email

User inputs1014may comprise input parameters from a keyboard, mouse, voice recognition interface, microphone and speakers, graphical display, touch screen, or other type of user interface device. This user interface may be distributed among multiple interface devices. Parameters1016may include specifications and/or characteristics that are input to help define representation1020. For example, parameters1016may include information that defines device types (e.g., NFET, PFET, etc.), topology (e.g., block diagrams, circuit descriptions, schematics, etc.), and/or device descriptions (e.g., device properties, device dimensions, power supply voltages, simulation temperatures, simulation models, etc.).

Memory1004includes any suitable type, number, and/or configuration of non-transitory computer-readable storage media that stores processes1012, user inputs1014, parameters1016, and circuit component1020.

Communications devices1006include any suitable type, number, and/or configuration of wired and/or wireless devices that transmit information from processing system1000to another processing or storage system (not shown) and/or receive information from another processing or storage system (not shown). For example, communications devices1006may transmit circuit component1020to another system. Communications devices1006may receive processes1012, user inputs1014, parameters1016, and/or circuit component1020and cause processes1012, user inputs1014, parameters1016, and/or circuit component1020to be stored in memory1004.