Delay locked loops with calibration for external delay

Provided herein are delay locked loops (DLLs) with calibration for external delay. In certain embodiments, a timing alignment system includes a DLL including a detector that generates a delay control signal based on comparing a reference clock signal to a feedback clock signal, and a controllable delay line configured to generate the feedback clock signal by delaying the reference clock signal based on the delay control signal. The timing alignment system further includes a delay compensation circuit that provides an adjustment to the controllable delay line to compensate for a delay of the feedback clock signal in reaching the detector.

FIELD OF THE DISCLOSURE

Embodiments of the invention relate to electronic systems, and more particularly to, delay locked loops (DLLs).

BACKGROUND

Delay locked loops (DLLs) operate with feedback to phase lock an output signal to an input signal. In contrast to phase locked loops (PLLs) in which feedback sets the oscillation frequency of a controllable oscillator, DLLs use feedback to set a delay of a controllable delay line to lock the output signal to the input signal. DLLs offer lower sensitivity to supply noise and/or lower phase noise relative to PLLs.

DLLs can be used in a wide variety of applications including, but not limited to, timing alignment, clock and data recovery, and/or clock generation.

SUMMARY OF THE DISCLOSURE

Provided herein are delay locked loops (DLLs) with calibration for external delay. In certain embodiments, a timing alignment system includes a DLL including a detector that generates a delay control signal based on comparing a reference clock signal to a feedback clock signal, and a controllable delay line configured to generate the feedback clock signal by delaying the reference clock signal based on the delay control signal. The timing alignment system further includes a delay compensation circuit that provides an adjustment to the controllable delay line to compensate for a delay of the feedback clock signal in reaching the detector. For example, in certain implementations, the feedback clock signal propagates through an external delay circuit to reach the detector. Additionally, the external delay compensation circuit can measure a delay through the external delay circuit, and adjust the controllable delay line based on the measured delay to provide delay compensation. Absent compensation for external delay, a DLL may not operate over a full range of operating constraints and/or suffer from extensive design constraints and/or trade-offs. Furthermore, such delay compensation reduces or eliminates an amount of laboratory efforts for characterization, evaluation, and/or test.

In one aspect, a timing alignment system with calibration for loop delay is provided. The timing alignment system includes a delay locked loop (DLL) including a detector configured to generate a delay control signal based on comparing a reference clock signal to a feedback clock signal, and a controllable delay line configured to generate the feedback clock signal by delaying the reference clock signal based on the delay control signal. The timing alignment system further includes a delay compensation circuit configured to provide an adjustment to the controllable delay line to compensate for a delay of the feedback clock signal in reaching the detector.

In another aspect, a method of calibration for external delay in a timing alignment system is provided. The method includes generating a delay control signal based on comparing a reference clock signal to a feedback clock signal using a detector of a delay locked loop (DLL), generating the feedback clock signal by delaying the reference clock signal based on the delay control signal using a controllable delay line of the DLL, and providing an adjustment to the controllable delay line to compensate for a delay of the feedback clock signal in reaching the detector using a delay compensation circuit.

In another aspect, a time of flight system includes a receiver configured to provide a reference clock signal, a driver circuit configured to generate a driver signal, and a timing alignment system comprising a delay-locked loop configured to control timing of the driver signal based on the reference clock signal. The delay-locked loop includes a detector configured to generate a delay control signal based on comparing a reference clock signal to a feedback clock signal, and a controllable delay line configured to generate the feedback clock signal by delaying the reference clock signal based on the delay control signal. The timing alignment system further includes a delay compensation circuit configured to provide an adjustment to the controllable delay line to compensate for a delay of the feedback clock signal in reaching the detector.

DETAILED DESCRIPTION

The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be embodied in a multitude of different ways. In this description, reference is made to the drawings where like reference numerals may indicate identical or functionally similar elements. It will be understood that elements illustrated in the figures are not necessarily drawn to scale. Moreover, it will be understood that certain embodiments can include more elements than illustrated in a drawing and/or a subset of the elements illustrated in a drawing. Further, some embodiments can incorporate any suitable combination of features from two or more drawings.

Provided herein are delay locked loops (DLLs) with calibration for external delay. In certain embodiments, a timing alignment system includes a DLL including a detector that generates a delay control signal based on comparing a reference clock signal to a feedback clock signal, and a controllable delay line configured to generate the feedback clock signal by delaying the reference clock signal based on the delay control signal. The timing alignment system further includes a delay compensation circuit that provides an adjustment to the controllable delay line to compensate for a delay of the feedback clock signal in reaching the detector.

For example, in certain implementations, the feedback clock signal propagates through an external delay circuit to reach the detector. Additionally, the external delay compensation circuit can measure a delay through the external delay circuit, and adjust the controllable delay line based on the measured delay to provide delay compensation.

Absent compensation for external delay, a DLL may not operate over a full range of operating constraints and/or suffer from extensive design constraints and/or trade-offs. Furthermore, such delay compensation reduces or eliminates an amount of laboratory efforts for characterization, evaluation, and/or test.

The delay compensation systems herein can be used in a wide range of applications.

In one specific example, delay compensation can be used for one or more DLLs used in a time of flight (ToF) application. Time of flight measurement techniques are attractive for a wide range of emerging 3D imaging applications including, but not limited to, facial recognition, augmented reality, machine vision, industrial automation and/or autonomous driving.

Although delay compensation can be used in time of flight systems, the teachings herein are applicable to a wide range of timing alignment systems.

FIG.1Ais a schematic diagram of a time of flight system10according to one embodiment.FIG.1Bis one example of a timing diagram for the time of flight system10ofFIG.1A.

The time of flight system10includes a two-chip architecture including an imager chip1and a laser driver chip2connected by an interface (low-voltage differential signaling or LVDS, in this example). The imager chip1serves as a master chip that sends a signal pulse (for instance, an LVDS signal) to the laser driver chip2.

The laser driver chip2controls emission of light output (using light emitting element4, in this example) to an object5, and the reflected light arrives at the receiver of the imager chip1sometime later. The light emitting element4can correspond to a wide variety of light emitting components including, but not limited to, a laser emitting element such as a vertical-cavity surface-emitting laser (VCSEL).

The imager chip1then calculates the distance to the object5by measuring the time or phase difference between the transmitted LVDS signal and the reflected light, with knowledge of the speed of light. The total delay (seeFIG.1B) is the sum of the driver's own propagation delay and the actual time of flight. The driver delay is typically calibrated out for each part at a certain temperature and voltage. However, it is complicated and costly to calibrate its drift over temperature and voltage, reducing its market viability.

FIG.2is a schematic diagram of a time of flight system30according to another embodiment. The time of flight system30ofFIG.2includes an imager chip1and a laser driver chip20connected by an interface3.

The time of flight system30ofFIG.2is similar to the time of flight system of10ofFIG.1Aexcept that the time of flight system30depicts a specific implementation of laser driver circuitry.

In particular, the laser driver chip20ofFIG.2includes a receiver11, a pair of DLLs12, an edge combiner15, a driver signal chain (pre-driver/driver circuitry)16, a transimpedance amplifier (TIA)17, and a replica receiver18operating on various feedback options (for instance, gate/drain replica/cathode/TIA). The laser driver chip20is coupled to a transmitting light element19aand to a receiving light element19b. For the TIA path (corresponding to an optical feedback option), the laser driver chip20uses a feedback path utilizing the transmitting light element19aand the receiving light element19b. The time of flight from the transmitting light element19ato the receiving light element19bis negligible (for instance, TVCSEL_PDabout equal to 0 ns) because they are normally placed very close together in a module.

In the illustrated embodiment, the pair of DLLs12are used to align both the rising and falling edges of the output to the input signal, regardless if the signal itself is single-ended or differential. The loop forces the input signal (INP, INN) to be aligned with one of the selected feedback signals (VG, VD, VC, VTIA). In certain implementations, the laser driver chip20is further implemented with calibration for variation in one or more of the gate/drain replica/cathode/TIA nodes.

The pair of DLLs12operate as part of a dual DLL timing alignment system for controlling timing of the emission of light from the time of flight system30.

In certain implementations, the dual DLL timing alignment system supports one or more of the following performance specifications: (1) alignment of both the output rising and falling edges to the input signal; (2) support of wide range frequency and multiple feedback options and corresponding support for a large amount of combinations of signal period and external delay (TEXT), corresponding to the propagation delay around the loop outside the DLL's voltage controlled delay line (VCDL); (3) signal must reliably propagate through multiple input signal periods; (4) low alignment phase error drift over temperature and supply; (5) well controlled bandwidth for fast locking/spread spectrum purpose; and/or (6) good tuning range to track TEXTdelay variation (for instance, due to laser diode driver's self-heating).

The dual DLL timing alignment system ofFIG.2can operate with a relatively long length of TEXTcompared with the input reference signal period TREF.

In certain implementations, a dual DLL timing alignment system is implemented in accordance with one or more of the calibration schemes disclosed herein. For example, either or both of the depicted DLLs can be implemented with self-calibration for an external delay path to the DLL, thereby enabling robust operation of the DLL and ensuring low risk, low engineering cost, and/or fast time to market.

AlthoughFIG.2depicts a dual DLL timing alignment system that can be implemented with calibration for external delay of a DLL, the teachings herein are also applicable to other DLL systems, including single DLL systems.

FIG.3Ais a schematic diagram of an example implementation of a DLL50. The DLL50includes a reference divider41, a feedback divider42, a phase frequency detector (PFD)43, an up current source44, a down current source45, a loop capacitor46, a voltage controlled delay line47, and an output buffer48.

As shown inFIG.3A, a reference signal REF is provided to the voltage-controlled delay line47and to the reference divider41, which divides the reference signal REF to generate a PFD reference signal REF_PFD. The PFD43compares the PFD reference signal REF_PFD to a PFD feedback signal FB_PFD to generate an up signal UP for controlling the up current source44and a down signal DN for controlling the down current source45. The up current source44and the down current source45provide currents to the loop capacitor46to thereby set a control voltage VCTRL (also referred to herein as a loop voltage) for controlling a delay of the voltage controlled delay line47. The voltage controlled delay line47delays the reference signal REF to generate a delayed output signal VCDL, which is buffered by the output buffer48to generate a feedback signal FB. The feedback divider42divides the feedback signal FB to generate the PFD feedback signal FB_PFD.

The DLL50is annotated to include various delays including a VCDL delay (TVCDL), an external delay (TEXT), and a total loop delay (TLOOP).

Typical DLLs operate with TEXTthat is always shorter or much shorter than TREFas shown inFIG.3B.

In the context of certain DLL applications, such as the dual DLL timing alignment system ofFIG.2, TEXTis not very well defined. It can be shorter or longer than TREF. In general, we could see the length of TEXTas an integer multiple of the reference periods, TREFM=TREF×M (M=0, 1, 2 . . . ), plus a fraction of the reference period, TFRAC.FIG.3CandFIG.3Dshow two examples of possible alignment diagrams. Note that TPFDcould be a multiple of TREFwhen the division ratio of the frequency divider is greater than one. Although various alignment diagrams are depicted, other scenarios are possible, including, but not limited to, scenarios in which TPFDis greater than the total time length.

Absent compensation, large variations in TEXTcan lead to a number of operating issues in a DLL. For example, without compensation, variation in TEXTcan lead to one or more of the following: (1) difficulty in partitioning the VCDL delay (TVCDL), the external delay (TEXT) and/or frequency division ratio for all the combinations of signal frequency and use case over process, voltage and temperature (PVT) variation to guarantee the functionality and performance robustly, particularly with poorly defined TEXT; (2) runt pulses or disappearing signal issues when the loop forces the VCDL's unit cell delay, TTAP, to be too long; (3) targeted TTAPcould be shorter than the VCDL's minimum delay such that the DLL is falsely locked; (4) forcing the charge pump into a non-ideal operating point associated with increased alignment phase error; (5) out of control loop bandwidth; and/or (6) malfunctioning during phase acquisition resulting in no lock in some certain scenarios (for instance, based on the relationship between TEXT, TVCDLand TPFD).

FIG.4is a schematic diagram of a DLL120with calibration according to one embodiment. The DLL120ofFIG.4is implemented with a TDC-based self-calibration scheme to ensure robust operation of the DLL over a wide range of performance requirements. The DLL120is implemented with single edge locking, in this example. However, the teachings herein are also applicable to DLLs implemented with dual edge locking.

In the illustrated embodiment, the DLL120includes a VCDL102, a reference clock multiplexer107, a feedback clock multiplexer108, a reference divider109, a feedback divider110, a PFD/CP/LF111, a delay measurement circuit115, a DLL reconfiguration circuit116, and a delay circuit117. Although one example of a DLL is shown, the teachings herein are applicable to DLLs implemented in a wide variety of ways including to other implementations of analog DLLs as well as to digital DLLs. Accordingly, other implementations of DLLs are possible.

As shown inFIG.4, the DLL120has been annotated with various delays including a delay TVCDLthrough the VCDL102and a delay TEXTfrom the output of the VCDL102to an input of the feedback clock multiplexer108.

In the illustrated embodiment, the delay measurement circuit115measures the delay TEXTusing a TDC, as will be discussed in detail further below. Additionally, the DLL120is reconfigured (including an adjustment to the VCDL102) to account for the delay TEXTusing the DLL reconfiguration circuit116.

Thus, the DLL120ofFIG.4provides calibration for TEXTsuch that the VCDL102and the charge pump (within the PDF/CP/LF111) operate around a desired operation point regardless the length of TEXTcompared with a reference period TREFof the DLL's reference clock REF, thereby ensuring robustness and compliance with phase error, bandwidth, and/or flexibility specifications. Thus, TEXTis calibrated such that the impact of TEXTis trimmed out and the DLL120operates similar to a DLL operating without an external loop. For example, after calibration, in certain implementations the DLL120can operate as if TEXTis about 0 ns.

Moreover, the self-calibration alleviates a need for an end user (for instance, characterization, evaluation, test program, and/or customer) to manually configure the DLL's loop to account for external delay. Furthermore, the self-calibration allows a DLL design (for instance, the DLL's circuit blocks) to be migrated to a new design with low engineering cost and risk and/or short time to market by avoiding a need for custom DLL design tweaks to account for a particular external delays associated with the new design. In addition, when used in the context of a dual DLL timing alignment systems, the risk of dual loop malfunction acquisition is eliminated.

In certain embodiments, calibration is performed by first configuring the VCDL output (VCDL[x]) as the feedback input of the detector (a PFD, in this example) to form the internal loop, and allowing it to lock. For example, the feedback could be taken from VCDL_INT with the propagation delay of TMXI, which could represent a delay of a multiplexer, additional buffer, and/or other circuit, with a matching propagation delay of TMXRincluded in the reference path for enhanced delay matching.

Once locked, the VCDL tap output edges can be evenly distributed over one PFD reference period, for instance, TVCDL[x]≈TPFD≈TTAP*(x+1), where TVCDL[X]means the VCDL output is taken from VCDL[x]. The value of x could be an integer between 0 and n. When locking the internal DLL, TPFDcan be equal to or a multiple of TREF(for instance, based on a division value between the reference and the input to the PFD).

Secondly, calibration continues by measuring at least a fractional portion (TFRAC) of an actual external delay TEXTfrom VCDL[y] to a feedback (FB) node when the internal loop is locked or close to lock. For example, actual external delay TEXTcan correspond to an integer number (0, 1, 2, etc.) of periods of the PFD reference period plus TFRAC. In certain implementations, TFRACcan be measured using a TDC of which the references are taken from the VCDL tap outputs (VCDL[0:x]). Additionally, VCDL[y] could be the same as VCDL[x] in this step so that TLOOP=TVCDL[x]+TEXT=TVCDL[y]+TEXT. TLOOPcan be of any length at this stage. Moreover, TREFMcan also be measured in certain implementations.

Thirdly, once at least the fractional portion (TFRAC) of TEXTis known, the VCDL102of the DLL120is reconfigured/adjusted such that the new TLOOP, which is the new TVCDL[y]plus the unchanged TEXT, is about equal to an integer multiple of TPFD. Thereafter the DLL's loop is switched or transitioned by bringing the actual feedback point to the PFD input to form the external loop and allow it to lock.

In certain implementations, the loop bandwidth of the DLL is also adjusted to account for the adjustment to the VDCL length. For example, the loop bandwidth of the DLL can be changed (for instance, by adjusting a strength of a charge pump current and/or a capacitance of a loop filter) to maintain the calibrated VCDL's control voltage (VCTRL) close to that of the internal loop, for instance, TTAPhas enough margin to increase or decrease and charge pump performance is well controlled.

To reconfigure the VCDL102, the number of taps of the VCDL could be increased or decreased (for instance, the value of y can be greater or smaller than x), which could involve using a multiplexer with propagation delay of TMXE. Additionally, or alternatively, TVCDLcan be adjusted by changing the VCDL's bias current, load capacitance, and/or by using an inversion phase of the VCDL taps. The teachings herein are applicable to any suitable manner of reconfiguring a VCDL.

Moreover, the frequency divider ratio of a divider (for example, the feedback divider110) can be changed during calibration (effectively changing TPFD) so that the external loop's TPFDis equal or longer than TLOOP. The information of TLOOPcould be based on the accurately measured TREFMand/or TFRAC, or rough estimation.

Furthermore, since, reconfiguring the VCDL length and/or TPFDmay change the loop bandwidth of the DLL120, the loop bandwidth can also be adjusted (for instance, by reconfiguring the charge pump and/or loop filter) to compensate for this. Moreover, the charge pump could be biased using the control voltage VCTRL to further control the loop bandwidth.

For dual DLL operation (for instance, the dual DLL timing alignment system ofFIG.2), each DLL could go through such internal loop locking and TEXTmeasurement independently. Thus, when switching to the external loops, both DLLs will start from close to lock position.

By providing calibration in this manner, a universal methodology is provided for external delay measurement and compensation of a DLL. Absent compensation for external delay, a DLL may not operate over a full range of operating constraints and/or suffer from extensive design constraints and/or trade-offs made with the hope of improving robustness and performance. Furthermore, such compensation reduces or eliminates an amount of laboratory efforts for characterization, evaluation, and/or test.

FIG.5Ais a first example of a timing diagram for a DLL.FIG.5Bis a second example of a timing diagram for a DLL.FIG.5Cis a third example of a timing diagram for a DLL.FIG.5Dis a fourth example of a timing diagram for a DLL.

For certain DLL applications, such as dual DLL timing alignment systems for time of flight, the length of external delay (or un-controlled delay, or feedback path delay) between VCDL1/VCDL2 to FB1/FB2 (marked as TEXT) with respect to the TVCDLis not very well defined.

For example, in applications with multiple feedback path options for a DLL and/or varying signal frequency, TEXTcould be from one half to a few times of the input clock periods.

With reference back toFIGS.3A to3D, for a basic type-I DLL50, the inputs of the PFD43and the VCDL47are the same clock signal. Additionally, as shown inFIG.3A, the DLL50includes a PFD/CP/LF path (through the PFD43, the up current source44/down current source45, and loop capacitor46, in this example) and a signal propagation path from REF to FB nodes.FIG.3Bshows the type-I DLL50locked, in which the total signal propagation delay TLOOP(the sum of TVCDLand TEXT) is one input clock cycle period, and TEXTis much shorter than TVCDLsuch that the TVCDLdelay range variation capacity to cope with TEXTspread is well bounded and the constraints on the VCDL47are low. In contrast,FIG.3Cdepicts a scenario in which TEXTis more than one input clock period, such that the feedback signal FB is locked with a few clock periods delay of the input signal REF, referred to as harmonic locking as shown inFIG.3C.FIG.3Dis a slightly different scenario where the PFD period TPFDis an integer multiple of the input signal period TREF, and TPFD=TLOOP.

For such a DLL to lock from a give initial condition (for instance, the time relationship between the REF and FB), the VCDL delay TVCDLcan be increased or decreased such that FB can move towards the next or the previous REF signal.FIGS.5A to5Ddepict various DLL timing diagrams depicting how the design of a PFD and/or frequency divider can control the preferred moving direction associated with lock. For example, if it is desired for FB to lock to the next REF clock, the TVCDLlength could be increased by a range from a small amount to about a signal period as shown inFIG.5AandFIG.5B. However, if it is desired for FB to lock to the previous REF clock, the TVCDLcould be reduced by a range from a small amount to about one signal cycle, as shown inFIG.5CandFIG.5D

Absent compensation for TEXT, TVCDLrange could vary by one input clock cycle depending on the initial TLOOP. For example, TVCDLcan include a chain of cascaded unit delay cell with the delay of TTAP, such that TVCDL=N×TTAP, where N is the number of delay cells. If the desired TTAPof the VCDL is too long it is likely to result in runt pulses (pulse width is too narrow or wide) or the signal may even disappear through the delay line, particularly at higher frequency, when the input clock duty cycle is not 50%, and/or when the unit delay cell has unequal rising/falling time. Conversely, if the desired TTAPof the VCDL needs to be too short, the unit delay cells may saturate and not reach the desired short delay. In a laser driver application (for instance, for time of flight), this issues worsens when TEXTincreases during operation due to self-heating of the laser driver and a corresponding desire for TVCDLto further decrease after the DLL has initially locked.

Although more delay cells can be increased to widen TTAPrange (for instance, increasing N, and allow it to pass multiple signal periods), such an approach is also susceptible to runt pulse phenomenon with longer delay chain especially when the DLL's feedback loop is increasing the delay of TTAPfrom a certain point.

FIG.6depicts one example of simulation results for a runt pulse through a DLL. The simulation results correspond to a simulation of a 400 MHz, 0.45% duty cycle input signal passing through a VCDL with unit cell propagation delay about 312.5 ps and only 10 ps rise/fall time difference. As shown inFIG.6, the delay chain struggles to pass 4-5 cycles.

In additional to the functional robustness issue, even if a carefully designed DLL without calibration manages to lock, it still suffers from performance issues.

For example, firstly, the VCDL control voltage (VCTRL) or the charge pump output voltage range is expected to vary to cover the required TTAPrange to compensate TEXT, this varies the gain of the VCDL, and hence the loop bandwidth. This in turn results in wide spread of locking time, temperature tracking and spread spectrum capability. Although the charge pump current could be designed to be correlated to the control voltage VCTRL, it is not clear that this can always guarantee the bandwidth robustly over the entire delay range for all VCDL implementations.

Secondly, large VCTRL could cause more locking error spread. For example, a DLL's locking error is a function of the charge pump up/down current mismatch, the PFD's anti-backlash pulse width, the charge pump's leakage current, and the sampling frequency, as shown by the two equations below. Wide spread of the charge pump output voltage could cause the charge pump up/down current mismatch and the leakage current variation, hence increase the spread of the locking error.

Moreover, even if the VCDL and charge pump are carefully designed and optimized to allow a single DLL to be functional, a dual PLL timing alignment system provides additional complexities.

For example, for the time of flight system of30ofFIG.2, two sets of PFD/CP/LF and VCDL blocks are included to align both rising and falling edges. One set aligns the rising edges of the reference and feedback clock signals, and the other set aligns the falling edges (or equivalently, the rising edges of the complementary signals for a differential signal system). As shown inFIG.2, at the output of the two VCDLs of the DLLs12, there is an edge combiner that generates rising and falling edges triggered by the two VCDLs' output edges respectively.

Depending on the initial status (for instance, the timing relationships of REF1/FB1 and REF2/FB2), the dual edge loop may fail to operate.

FIG.7is one example of a timing diagram for a dual DLL timing alignment system. As shown at the start ofFIG.7, TV1(the VCDL1's TVCDL) is the same as TV2, but the external delay TEXT1and TEXT2may not be the same. In this case, when TEXT1and TEXT2are slightly different such that FB1 and FB2 are at two sides of REF1 and REF2, respectively, the two DLL loops would behave differently. In this example, FB1 needs to move over almost one signal period while the FB2 only needs to move slightly. At some point, the DLL2 is locked and the DLL1 is still moving, later on the VCDL1 edge will be moved very close to the VCDL2 edge, the edge combiner either fails to operate or generates very narrow pulses, as shown in the first box141ofFIG.7. Moreover, even if the DLL and edge combiner are still functional by some chance, as the VCDL1 going past the VCDL2 edge, there will be a missing FB2 edge as shown in the second box142ofFIG.7. The result is that the DLL2 will start to move in a wrong direction from the next cycle as shown in the third box143ofFIG.7, and the DLL fails to lock properly in this scenario. This is similar to a cycle slip phenomenon in a PLL, but unlike PLLs, the VCDL in a DLL cannot recover from this situation. Although dividing down the PFD frequency can provide some help, dividing the PFD frequency also leads to more stringent range requirement for each DLL's VCDL and causes reliability issues.

FIG.8is a schematic diagram of a DLL170with calibration according to another embodiment. The DLL170includes a VCDL102′, which includes a main delay chain (corresponding to a cascade of controllable delay cells with a delay controlled by VCTRL, in this embodiment) and two multiplexers MXI and MXE for outputting the signal from a selected controllable delay cell. The DLL170further includes a multiplexer stage106, a reference clock multiplexer107, a feedback clock multiplexer108, a reference divider109, a feedback divider110, a PFD/CP/LF111′ (including PFD43, up current source44, down current source45, and loop capacitor46), a delay measurement circuit151, a state machine and calculation circuit152, a DLL reconfiguration or adjustment circuit153, and a delay circuit117. Although one example of a DLL is shown, the teachings herein are applicable to DLLs implemented in a wide variety of ways including to other implementations of analog DLLs as well as to digital DLLs. Accordingly, other implementations of DLLs are possible.

The self-calibrated DLL170ofFIG.8operates with a three-step calibration.

The first step is to configure the DLL170to lock to its own VCDL output, as indicated by the internal loop inFIG.8. To form this internal loop, the multiplexer107selects REF_MXR, which is the REF signal delayed by the multiplexer stage106, while the multiplexer108selects VCDL_INT, which is the internal VCDL propagation delay plus a delay of an internal loop multiplexer stage (MXI). The output of each buffered VCDL stage is called VCDL[x]. MXR is a replica multiplexer of MXI (internal multiplexer) and MXE (external multiplexer), which can be implemented as two identical (replica) multiplexers that select which VCDL[x] node to pass to the outputs, VCDL_INT and VCDL_EXT, independently. When the input signal frequency is known, one can choose to program VCDL number of delay cells to allow TTAPto be roughly the same for all frequencies shown in the equation below.
TVCDL[sec]=TREF[sec]=N×TTAP[sec]

For example, if TTAP=260 ps, we need roughly 24 stages to for a 160 MHz signal (period=6.25 ns) or 48 stages for an 80 MHz signal (12.5 ns). Also note that the VCDL gain is proportional to the number of taps as shown in the equation below, where KVCDLis the total gain through the delay line and KTAPis the gain of a single delay cell.
KVCDL[sec/V]=N×KTAP[sec/V]

So if the unit delay cell is fixed, the loop bandwidth is constant for all frequencies as the equation shown below.

Frequency programming can be optionally performed here, with the goal to allow the two VCDLs' outputs lock to their inputs in a manner similar to traditional DLLs.

In certain implementations, loop bandwidth is adjusted to compensate for a change in loop bandwidth arising from an adjustment to the VCDL.

For the self-calibration purpose, MXR replicates the delay of MXI, i.e. TMXI=TMXR, such that when the VCDL loop is locked, VCDL_IN locks to REF_MXR, hence VCDL[sel_mxi] locks to ref, where sel_mxi is the number of stages plus 1 in this example because the index number starts from 0. Now one PFD period (TPFD) is equal to the length of TTAP*(sel_mxi+1)+TBUF, and in practice TBUFis small compared with TTAP. Thus, the impact of the TBUFwithin TPFDcan be reasonably ignored. Now all the VCDL tap outputs, VCDL[0]˜VCDL[sel_mxi] are almost evenly distributed over a PFD signal period and they form the references of the self-calibration.

FIG.9is a first example of a graph of delay cell unit delay versus control voltage. The graph depicts that self-calibration of a DLL allows VCDL delay cells to operate over a narrower range of the DLL's loop control voltage relative to an implementation without such calibration.

FIG.10is one example of a timing diagram for the DLL170ofFIG.8. TPFDcan be equal to TREFor a multiple of TREFdepending on the frequency divider's configuration in front of the PFD. For example, see the internal loop locked section in the timing diagram shown inFIG.10.

As shown inFIG.10, the second step is to measure the external delay TEXTwith a coarse time-to-digital-converter (TDC) of which the LSB roughly equals to TTAP, in this example. As shown in the second step ofFIG.10, TEXTis the sum of TMXEand TREST, where TRESTis the rest of the propagation delay before FB. In certain implementations, TMXEand TMXIare about equal. Thus, MXE is enabled to allow signal to propagate to the FB node, and thereafter the length of the feedback delay using the VCDL[0]˜VCDL[sel_mxi] nodes is measured.

The total length of TEXTis composed of TREF×M, an integer multiple of the TPFD(which could be 0), and TFRAC, the fractional delay with respect to the TPFD. The step 2 can be enabled as early as when step 1 starts if the TDC can measure periodically, because this fraction is constant once the internal loop and external feedback nodes are stable.

FIG.11is one embodiment of a time-to-digital converter (TDC)210.

The TDC210can be implemented in a wide variety of ways, including by using an array of D-flip-flops201d0,201d1, . . .201dN of which the D terminals are connected to VCDL[0], VCDL[1], . . . VCDL[N] and the clock CK terminals are connected to the common node FB as shown inFIG.11. Although one example TDC implementation is shown, TDCs can be implemented in a wide variety of ways.

The output of the TDC210contains the information of how long the TFRACcompared with TPFD(or TREFin the example shown inFIG.10). The TDC measurement can be processed by digital circuitry to calculate an updated number of VCDL unit delay cells that changes TVCDL, such that TLOOPis roughly equal to an integer number of TPFD.

Such adjustment to the VCDL can be performed in a wide variety of ways, including number increasing or decreasing the number of unit cells, changing VCDL bias, varying VCDL's load capacitance, and/or selecting inverted phase when unit cells provide non-inverted and inverted outputs. Changing the number of delay cells scales the KVCDLproportionally, so an adjusted charge pump current could also be calculated accordingly to keep ICP*KVCDLconstant.

With reference toFIGS.8to11, the third step is to switch from the internal loop to the external loop and allow it to lock eventually. The MXE can be first adjusted to select the correct VCDL tap to the output so that REF and FB are almost aligned, with an error limited by LSB. Note that this if this is done asynchronously, it may take some cycles for the edge combiner's output to settle. Then the multiplexer107and108switch the loop from the internal loop to the external.

FIG.12is a second example of a timing diagram for the DLL170ofFIG.8.

Charge pump current can be switched at the same time. Because REF and FB are already close to each other, they are expected to be aligned within short period of time.FIG.12depicts a complete timing diagram, and shows an example of the VCDL number of cells being reduced.

Standard VCDL and PFD/CP/LF circuits can be used here to avoid extensive analog design engineering cost and risk, and to guarantee the robustness of operation and time to market. Depending on the bandwidth accuracy specification, one could choose to bias the charge pump current with the VCDL control voltage to further control the loop bandwidth. In this architecture, since the VCDL delay cells' operating point spread is tightly controlled, such benefits can be readily achieved without much difficulty.

FIG.13is a third example of a timing diagram for the DLL170ofFIG.8.

One could choose to keep TPFD=TREFto get a reasonable locking behavior. However since the TLOOPcould be more than one TPFD, the effect of any adjustment at a PFD sampling instance won't be propagated to the FB node within TPFD, so the next PFD sampling instance doesn't response to the outcome of this sampling, instead it responses to one of the previous ones. This additional delay may not be desired. And for a non-ideal PFD/CP transfer function, this means the locking error could fluctuation around its mean value. In some cases this may not be a concern, but the simplest solution to improve is to configure the frequency divider in the front of the PFD to a value such that the PFD sampling interval, TPFD, is equal to or longer than TLOOP, as long as we can guarantee the sampling frequency is much larger than the loop bandwidth from the stability perspective, such that the PFD/CP adjustment effect is propagated to the FB node before the next sampling event.

Thus,FIG.13depicts an example where the TLOOPfrom REF to FB is three cycles of REF period and the PFD frequency is four times lower than the reference signal. In this example, a phase error is introduced at some point, and the DLL will response to this from the next PFD sampling event immediately. Once we do this, the charge pump current could be scaled with the sampling frequency to keep the loop bandwidth constant.

FIG.14is one example of a graph of control voltage versus time for a dual DLL timing alignment system. The graph shows simulation result of VCDL control voltage versus time for DLL1 and DLL2 at 300 MHz. In step 1 and 2, the internal loop for DLL1 and DLL2 operates independently. Once the new DLL configurations are calculated, the DLLs are switched to external loops in step 3. The control voltage spread is small because any TEXTvariation is calibrated out by the DLL itself.

FIG.15is one example of a graph of DLL locking behavior. The example DLL locking is shown for 300 MHz and 40 MHz input frequency. The final control voltage spread is the same for the two frequencies, in this example. Also note that the control voltage movement in step 3 is very small so the final locking is reasonably fast.

As shown in the example ofFIG.15, roughly the same control voltage can be locked for different frequencies, as a result of the DLL frequency programming

Applications

Devices employing the above described schemes can be implemented into various electronic devices. Examples of the electronic devices can include, but are not limited to, consumer electronic products, parts of the consumer electronic products, electronic test equipment, communication infrastructure applications, etc. Further, the electronic device can include unfinished products, including those for communication, industrial, medical, automotive, radar, and aerospace applications.

CONCLUSION

Although the claims presented here are in single dependency format for filing at the USPTO, it is to be understood that any claim may depend on any preceding claim of the same type except when that is clearly not technically feasible.