Semiconductor device having transistor and method of manufacturing the same

One embodiment of inventive concepts exemplarily described herein may be generally characterized as a semiconductor device including an isolation region within a substrate. The isolation region may define an active region. The active region may include an edge portion that is adjacent to an interface of the isolation region and the active region and a center region that is surrounded by the edge portion. The semiconductor device may further include a gate electrode on the active region and the isolation region. The gate electrode may include a center gate portion overlapping a center portion of the active region, an edge gate portion overlapping the edge portion of the active region, and a first impurity region of a first conductivity type within the center gate portion and outside the edge portion. The semiconductor device may further include a gate insulating layer disposed between the active region and the gate electrode.

BACKGROUND

Embodiments of inventive concepts exemplarily described herein relate generally to semiconductor devices including transistors and methods of manufacturing such semiconductor devices. More particularly, embodiments of inventive concepts exemplarily described herein relate to a semiconductor device including a transistor that includes a gate electrode extending throughout an isolation region and an active region, and a method of manufacturing such a semiconductor device.

SUMMARY

Embodiments of inventive concepts exemplarily described herein may be generally characterized as providing a semiconductor device including a transistor that can prevent an undesired hump from generating in a drain current that depends upon a gate voltage, which is caused by a parasitic transistor formed on an edge portion of an active region that is close to an interface between an isolation region and the active region.

Embodiments of inventive concepts exemplarily described herein may also be generally characterized as providing a method of manufacturing a semiconductor device including a transistor that can prevent an undesired hump from generating in a drain current that depends upon a gate voltage, which is caused by a parasitic transistor formed on an edge portion of an active region that is close to an interface between an isolation region and the active region.

One embodiment of inventive concepts exemplarily described herein may be generally characterized as a semiconductor device including an isolation region within a substrate. The isolation region may define an active region. The active region may include an edge portion that is adjacent to an interface of the isolation region and the active region and a center region that is surrounded by the edge portion. The semiconductor device may further include a gate electrode on the active region and the isolation region. The gate electrode may include a center gate portion overlapping a center portion of the active region, an edge gate portion overlapping the edge portion of the active region, and a first impurity region of a first conductivity type within the center gate portion and outside the edge portion. The semiconductor device may further include a gate insulating layer disposed between the active region and the gate electrode.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments of inventive concepts will be exemplarily described with reference to accompanying drawings as follows.

FIG. 1Ais a plan view of a semiconductor device according to an embodiment,FIG. 1Bis a cross-sectional view of the semiconductor device taken along line Ib-Ib′ ofFIG. 1AandFIG. 1Cis a cross-sectional view of the semiconductor device taken along line Ic-Ic′ ofFIG. 1A.

Referring toFIGS. 1A,1B, and1C, the semiconductor device100may, for example, include an active region114defined by an isolation region112formed in a substrate110.

The active region114includes an edge portion114E that is adjacent to an interface between the active region114and the isolation region112and a center portion114C surrounded by the edge portion114E.

A gate electrode120is formed on the active region114and the isolation region112of the substrate110. A gate insulating layer118is disposed between the active region114and the gate electrode120.

A source region132and a drain region142are formed respectively on both sides of the gate electrode120in the active region114. The source region132and the drain region142are doped with a high concentration of impurities. In addition, the active region114includes a source drift region130and a drain drift region140, which respectively surround the source and drain regions132and142. The source drift region130and the drain drift region140are doped with a lower concentration of impurities than the source region132and drain region142. The source drift region130and the drain drift region140function as buffer regions to improve a junction breakdown voltage when high voltages are applied to the source region132and the drain region142. In one embodiment, a distance D1between the gate electrode120and the drain region142may be greater than a distance D2between the gate electrode120and the source region132to ensure that the breakdown voltage between the drain region142and the substrate110is greater than a high voltage applied to the drain region142.

An insulating spacer124is formed on a side wall of the gate electrode120. A contact plug170penetrating an interlayer dielectric160, which covers the gate electrode120, is electrically connected to the source region132and the drain region142.

The gate electrode120is formed to have a length GLand a width GW. In one embodiment, the gate electrode120extends from the active region114to the isolation region112in a direction substantially perpendicular to the length GLdirection, that is, substantially along the width GWdirection of the gate electrode120. The gate electrode120includes a first side wall122aand a second side wall122bon opposing end portions thereof in the width GWdirection. The first and second side walls122aand122bare located on the isolation region112. The first and second side walls122aand122bmay be collectively referred to as a “first pair of opposing sidewalls.” In addition, the gate electrode120includes a third side wall122cand a fourth side wall122don opposing end portions thereof in the length GLdirection. The third and fourth side walls122cand122dare located on the active region114. The third and fourth side walls122cand122dmay be collectively referred to as a “second pair of opposing sidewalls.”

The gate electrode120includes a center gate portion120C overlapping the center portion114C of the active region114, and an edge gate portion120E surrounding the center gate portion120C. The edge gate portion120E includes a first edge gate portion120E_1and a second edge gate portion120E_2overlapping the edge portion114E of the active region114on opposing end portions, which are respectively adjacent to the first and second side walls122aand122b. InFIGS. 1A and 1B, the edge gate portion120E extends along the first and second side walls122aand122band the third and fourth side walls122cand122din the length GLdirection and the width GWdirection to surround the center gate portion120C (e.g., as a ring-shaped edge gate portion120E). However, embodiments of inventive concepts described herein are not limited to the above description. For example, the edge gate portion120E may simply extend along the first and second side walls122aand122bin the length GLdirection and, therefore, include the first edge gate portion120E_1and the second edge gate portion120E_2.

In one embodiment, the gate electrode120may be formed of a material such as polysilicon. In another embodiment, the center gate portion120C of the gate electrode120may be doped with impurities and the edge gate portion120E of the gate electrode120may not be doped with impurities. That is, the edge gate portion120E of the gate electrode120may be undoped. The impurities doped in the center gate portion120C of the gate electrode120may be of a first conductivity type, which may be the same as the conductivity type of impurities doped in the source region132and the drain region142(e.g., N type impurities). Accordingly, the center gate portion120C may include a first impurity region of a first conductivity type, the first impurity region containing a first concentration of impurities. In one embodiment, the first impurity region may be an N+ type impurity region.

According to one embodiment, the center gate portion120C of the gate electrode120may be doped with impurities of the first conductivity type, which may be the same as the source region132and the drain region142, and the edge gate portion120E may be doped with impurities of a second conductivity type that is opposite to the first conductivity type. Accordingly, the edge gate portion120E may include a second impurity region of a second conductivity type. However, the conductivity types of the impurities may be opposite in the above example. In addition, in the edge gate portion120E, the doping concentration of impurities (i.e., the “impurity concentration”) in the first edge gate portion120E_1may be the same as or different from the doping concentration of impurities in the second edge gate portion120E_2.

In another embodiment, the center gate portion120C and the edge gate portion120E of the gate electrode120may be doped with impurities of the same conductivity type. Accordingly, the edge gate portion120E may include a second impurity region of the first conductivity type. The doping concentration of impurities in the center gate portion120C may be different from the doping concentration of impurities in edge gate portion120E. For example, the impurities of first conductivity type, which are doped in the source region132and the drain region142, can be doped in the center gate portion120C at a relatively high concentration while the impurities of the first conductivity type can be doped in the edge gate portion120E at a relatively low concentration.

In another embodiment, the center gate portion120C of the gate electrode120may be doped with the impurities of the first conductivity type, which is the same as the conductivity type of the impurities doped in the source region132and the drain region142, one of the first edge gate portion120E_1and the second edge gate portion120E_2may not be doped with impurities, and the other of the first edge gate portion120E_1and the second edge gate portion120E_2may be doped with impurities of the second conductivity type. Accordingly, one of the first edge gate portion120E_1and the second edge gate portion120E_2may be undoped and the other of the first edge gate portion120E_1and the second edge gate portion120E_2may include a second impurity region of a second conductivity type.

The transistor illustrated inFIGS. 1A,1B, and1C is an N type transistor, including an N+ type source region132and an N+ type drain region142. However, embodiments of the inventive concepts are not limited to the above example, and a P type transistor including a P+ type source region132and a P+ type drain region142may be also be provided.

If first and second edge gate portions120E_1and120E_2of the gate electrode120are doped with impurities in the same manner as the center gate portion120C, a depletion effect occurs at the first and second edge gate portions120E_1and120E_2located on the edge portion114E of the active region114, which is adjacent to the interface between the isolation region112and the active region114. According to embodiments of inventive concepts exemplarily described herein, however: impurities may not be doped in at least one of the first and second edge gate portions120E_1and120E2; a conductivity type of impurities doped in at least one of the first and second edge gate portions120E_1and120E_2may be the same as the conductivity type of impurities doped in the center gate portion120C, but impurities may be doped in the at least one of the first and second edge gate portions120E_1and120E_2at a relatively lower concentration than impurities doped in the center gate portion120C; and/or a conductivity type of impurities doped in at least one of the first and second edge gate portions120E_1and120E_2may be opposite to the conductivity type of impurities doped in the center gate portion120C. Accordingly, an equivalent oxide thickness may be increased, and a potential difference (Φms) between work functions of the gate electrode120and the substrate110can be reduced. Therefore, a threshold voltage of the edge portion114E of the active region114, which is located under the first and second edge gate portions120E_1and120E_2of the gate electrode120, increases. As a result, a hump phenomenon caused by undesired parasitic transistor does not occur on the edge portion114E of the active region114.

FIGS. 2A through 4Bare cross-sectional views illustrating processes of manufacturing the semiconductor device according to an embodiment. Specifically,FIGS. 2A,3A, and4A are cross-sectional views of the semiconductor device taken along line Ib-Ib′ ofFIG. 1AandFIGS. 2B,3B, and4B are cross-sectional views of the semiconductor device taken along line Ic-Ic′ ofFIG. 1A. InFIGS. 2A through 4B, the same reference numerals as those of FIGS.1A through1C denote the same components, and detailed descriptions of those components will not be repeated.

Referring toFIGS. 2A and 2B, an isolation region112is formed on the substrate110, on which a well of a predetermined conductivity type is formed to define the active region114. In one embodiment, the substrate110may be a silicon substrate. When an N type transistor is formed on the active region114, the well is a P type well. When a P type transistor is formed on the active region114, the well is N type well. For purposes of discussion only, the formation of an N type transistor will be described. It will be appreciated that the principles described herein may be applied to form a P type transistor.

After forming the isolation region112, a low concentration of impurities are injected into a part of the active region114to form the source drift region130and the drain drift region140of N− type. For example, to form the source drift region130and the drain drift region140, N type impurities such as phosphorous (P) can be injected into the active region at a dosage amount of about 5×1011˜5×1013atoms/cm2.

Then, a gate pattern120P including the gate insulating layer118and a polysilicon layer that is not doped with impurities is formed on the active region114of the substrate110. The insulating spacer124is also formed on a side wall of the gate pattern120P. The first side wall122aand the second side wall122bof the gate pattern120P, located on opposing end portions of the gate pattern120P in the width GWdirection, is located on the isolation region112. Therefore, opposing end portions of the gate pattern120P in the width GWdirection cover the interface between the isolation region112and the active region114. A third side wall122cand the fourth side wall122d, located on opposing end portions of the gate pattern120P in the length GLdirection, are located on the active region114.

Referring toFIGS. 3A and 3B, a mask pattern150is formed on the gate pattern120P and the substrate110. The mask pattern150may cover the center portion114C of the active region114and include a first opening150athat exposes a center portion of the gate pattern120P as well as a plurality of second openings150bthat expose some parts of the source drift region130and the drain drift region140. In one embodiment, the mask pattern150can be a photoresist pattern.

Referring toFIGS. 4A and 4B, a high concentration of impurities of the first conductivity type (N type impurities) are injected into the gate pattern120P and the active region114through the first opening150aand the plurality of second openings150bformed in the mask pattern150. As a result, the source region132and the drain region142of are formed at the same time as a center gate portion120C, which is formed in the center portion of the gate pattern120P, which are all doped with impurities of the first conductivity type. Accordingly, the gate electrode120, including the center gate portion120C doped with the impurities and the edge gate portion120E that is not doped with impurities, is formed. To form the source region132, the drain region142and the center gate portion120C, N type impurities such as phosphorous (P) ions can be injected into the active region114and the gate pattern120P at dosage of about 1×1015˜about 2×1016atoms/cm2, thereby forming N+ type impurity regions.

Subsequently, the mask pattern150is removed and, as shown inFIGS. 1B and 1C, the interlayer dielectric160is formed between the gate electrode120and the substrate110. In one embodiment, some parts of the interlayer dielectric160may be removed to form a plurality of contact holes exposing the source region132and the drain region142and contact plugs170may be formed in the contact holes to be electrically connected to the source region132and the drain region142.

Although not shown in the drawings, a conductive layer for wiring that is electrically connected to the contact plugs170can be formed on the interlayer dielectric160.

FIGS. 5A and 5Bare cross-sectional views illustrating processes of manufacturing a semiconductor device according to another embodiment. Specifically,FIG. 5Ais a cross-sectional view of the semiconductor device taken along line Ib-Ib′ ofFIG. 1AandFIG. 5Bis a cross-sectional view of the semiconductor device taken along line Ic-Ic′ ofFIG. 1A. InFIGS. 5A and 5B, the same reference numerals as those ofFIGS. 1A,1B,1C, andFIGS. 2A through 4Bdenote the same components, and detailed descriptions of the components will be omitted.

Referring toFIGS. 5A and 5B, the gate electrode220, including the center gate portion120C that is doped with impurities and the edge gate portion120E that is not doped with impurities, is formed on the substrate110according to the method of manufacturing the semiconductor device exemplarily described with reference toFIGS. 2A through 4B. Subsequently, a mask pattern250including openings250aand250b, which selectively expose the first and second edge gate portions220E_1and220E_2of the gate electrode220, is formed on the gate electrode220and the substrate110. The mask pattern250can be a photoresist pattern.

Next, impurities of a second conductivity type opposite to the first conductivity type (e.g., P type impurities) are doped in the first and second edge gate portions220E_1and220E_2of the gate electrode220through the openings250aand250bformed in the mask pattern250. Thus, first and second edge gate portions220E_1and220E_2doped with the impurities of second conductivity type can be formed as P or P+ type impurity regions. Accordingly, a gate electrode220, including the center gate portion120C doped with impurities of the first conductivity type and the first and second edge gate portions220E_1and220E_2doped with impurities of the second conductivity type, can be formed.

In one embodiment, the ion implantation process for forming the first and second edge gate portions220E_1and220E_2can be performed simultaneously with the ion implantation process for forming other regions of the substrate110, for example, source and drain regions of a P type transistor on a PMOS transistor region (not shown), using the same mask pattern.

In another embodiment, the method of forming first and second edge gate portions220E_1and220E_2doped with impurities of the second conductivity type, which is described with reference toFIGS. 5A and 5B, can be performed before forming the center gate portion120C, which is described with reference toFIGS. 4A and 4B, if necessary.

In one embodiment, the first and second edge gate portions220E_1and220E_2can have the same doping concentrations as each other. In another embodiment, the first and second edge gate portions220E_1and220E_2can have different doping concentrations from each other. In one embodiment the first and second edge gate portions220E_1and220E_2can be formed to have different doping concentrations from each other by performing a first ion implantation process using a mask pattern that selectively exposes one of the first and second edge gate portions220E_1and220E_2, instead of using the mask pattern250, and then performing a second ion implantation process using a mask pattern that selectively exposes the other of the first and second edge gate portions220E_1and220E_2. The dose amounts in the first and second ion implantation processes can be set to be different from each other.

Although not shown in the drawings, instead of using the mask pattern250shown inFIGS. 5A and 5B, a mask pattern (not shown) including an opening that selectively exposes one of the first edge gate portion220E_1and the second edge gate portion220E_2can be formed and impurities of second conductivity type (e.g., P type or P+ type impurities) can then be selectively doped in one of the first edge gate portion220E_1and the second edge gate portion220E_2, while no impurities are doped in the other of the first edge gate portion220E_1and the second edge gate portion220E_2.

Although not shown in the drawings, impurities of the first conductivity type (e.g., N type impurities) may be injected through the openings250aand250bof the mask pattern250into the first and second edge gate portions220E_1and220E_2at a lower concentration than impurities of the first conductivity type that are injected into the center gate portion120C.

After injecting impurities into the first and second edge gate portions220E_1and220E_2, the interlayer dielectric160and the contact plugs170are formed on the gate electrode220and substrate110according to the process exemplarily described with respect toFIGS. 1B and 1C.

FIGS. 6 through 9are graphs showing electrical characteristics of a transistor in a semiconductor device according to inventive concepts described herein with a transistor in a comparative semiconductor device.

For measuring the electrical characteristics shown inFIGS. 6 through 9, an N type transistor for a high voltage transistor was fabricated by forming an N+ type impurity region in the center gate portion of the gate electrode and leaving the edge gate portion of the gate electrode undoped, as exemplarily described above. A transistor in a comparative semiconductor device is provided as a high voltage N type transistor having fabricated under the same conditions as those of the semiconductor device of the present invention, except that an N+ impurity region is formed in the edge gate portion and the center gate portion of the gate electrode.

FIG. 6is a graph comparing Id characteristics, transconductance (Gm) characteristics and Vg characteristics, when Vd is 0.1V, of a transistor in a semiconductor device according to inventive concepts described herein with those of a transistor in a comparative semiconductor device.

Referring to the graph ofFIG. 6, even when the gate electrode of the transistor in the semiconductor device according to inventive concepts described herein includes dopant of the same conductivity type as that of the channel of the transistor only in the center gate portion of the gate electrode, Id, Gm and Vg characteristics that are similar to those of a transistor in a comparative semiconductor device can be obtained. When a threshold voltage Vth is defined using a Gm-Vg plot shown inFIG. 6, the Vth characteristic of the transistor is not affected even though dopant of the same conductivity type as that of the transistor channel is doped only in the center gate portion of the gate electrode, which corresponds to the center portion of the active region.

FIG. 7is a graph comparing Id-Vd characteristics, when Vg is 30V, of a transistor in a semiconductor device according to inventive concepts described herein with those of a transistor in a comparative semiconductor device.

Referring toFIG. 7, even when the gate electrode of the transistor in the semiconductor device according to inventive concepts described herein includes dopant of the same conductivity type as that of the channel of the transistor only in the center gate portion of the gate electrode, which is located on the center portion of the active region, a saturation current characteristic that is the same as that of a transistor in a comparative semiconductor device can be obtained.

FIG. 8is a graph comparing Id-Vd characteristics in order to measure off-current (Ioff) characteristic, when Vg is 0V, of a transistor in a semiconductor device according to inventive concepts described herein with those of a transistor in a comparative semiconductor device.FIG. 9is a graph comparing the Id-Vg characteristics, when a back bias voltage (Vb) is set as 0V, −2V, and −4V under a condition that Vd is 0.1V, of a transistor in a semiconductor device according to inventive concepts described herein with a transistor in a comparative semiconductor device.

According to According toFIGS. 8 and 9, even when the gate electrode of the transistor in the semiconductor device according to inventive concepts described herein includes dopant of the same conductivity type as that of the channel of the transistor only in the center gate portion of the gate electrode, which is located on the center portion of the active region, the Ioff characteristic of the present invention is reduced lower than that of the comparative example, and generation of the hump phenomenon can be restrained in the present invention.

According to embodiments exemplarily described above, impurities are not doped in the edge gate portion of the gate electrode, impurities of the same conductivity type are doped in the edge gate portion of the gate electrode and the center gate portion of the gate electrode but the edge gate portion of the gate electrode contains a relatively lower concentration of the impurities, or is doped with impurities of the same conductivity type as impurities that are doped in the, or impurities doped in the edge gate portion of the gate electrode have a different conductivity type than impurities doped in the center gate portion of the gate electrode. Therefore, the equivalent oxide thickness increases around the edge gate portion that is located on the edge portion of the active region, which is close to the interface between the isolation region and the active region, and a potential difference (Φms) between the work functions of the gate electrode and the substrate is reduced. Therefore, the threshold voltage Vth increases on the edge portion of the active region, which is located under the edge gate portion of the gate electrode. Therefore, the generation of hump phenomenon in the drain current Id in response to the gate voltage Vg, which is caused by the parasitic transistor on the edge portion of the active region, can be prevented.

It will be appreciated that embodiments of the inventive concepts exemplarily described herein may be practiced in many ways. What follows below is a general discussion of some exemplary embodiments.

One embodiment of the inventive concepts exemplarily described herein may be characterized as a semiconductor device including an active region defined by an isolation region in a substrate, and including an edge portion that is close to an interface between the isolation region and the active region and a center portion surrounded by the edge portion; a gate electrode formed on the active region and the isolation region, and including a center gate portion covering a center portion of the active region, an edge gate portion covering the edge portion of the active region, and a first impurity region of a first conductive type formed only in the center gate portion; and a gate insulating layer disposed between the active region and the gate electrode.

The edge gate portion may not be doped with impurities. The edge gate portion may include a second impurity region of a second conductive type, which is opposite to the first conductive type.

The semiconductor device may further include: a source region and a drain region, which are respective formed on the active region at both sides of the gate electrode, wherein the source region and the drain region are doped with impurities of the first conductive type.

The gate electrode may include a first end portion and a second end portion, which respectively extend to the isolation region, on both sides of the first impurity region. The edge gate portion may include a first edge gate portion formed in the first end portion and a second edge gate portion formed in the second end portion.

The first and second edge gate portions may not be doped with impurities. Each of the first edge gate portion and the second edge gate portion may include a second impurity region doped with impurities of a second conductive type that is opposite to the first conductive type. Impurities concentrations of the first edge gate portion and the second edge gate portion may be different from each other.

One of the first edge gate portion and the second edge gate portion may not be doped with impurities, and the other of the first edge gate portion and the second edge gate portion may include a second impurity region of a second conductive type that is opposite to the first conductive type.

The gate electrode may include: a pair of first side walls located on both sides of the first impurity region in a first direction and located on the isolation region; and a pair of second side walls located on both sides of the first impurity region in a second direction that is perpendicular to the first direction and located on the active region.

The first impurity region may be separated from the pair of first side walls and the pair of second side walls.

Another embodiment of the inventive concepts exemplarily described herein may be characterized as a method of manufacturing a semiconductor device. The method may include: forming an isolation region within a substrate to define an active region including an edge portion that is adjacent to an interface of the isolation region and the active region and a center portion that is surrounded by the edge portion; forming a gate insulating layer on the active region; forming a gate pattern on the gate insulating layer, the gate pattern overlapping the center portion and the edge portion of the active region and the isolation region; and forming a first impurity region of a first conductivity type selectively within a center portion of the gate pattern overlapping the center portion of the active region with respect to an edge portion of the gate pattern overlapping the edge portion of the active region.

The edge gate portion may include a first edge gate portion and a second edge gate portion formed at opposite sides of the center gate portion.

The method may further include: forming a low concentration impurity region of a first conductivity type on the active region before forming the gate insulating layer; and forming a high concentration impurity region of the first conductivity type in the lower concentration impurity region of the first conductivity type during the forming the first impurity region.

The method may further include: forming a second impurity region of a second conductivity type opposite the first conductivity type within the edge portion of the gate pattern. The second impurity region may be formed before or after the first impurity region is formed.