Non-volatile SRAM with multiple storage states

Technologies are generally described herein for a non-volatile static random access memory device with multiple storage states. The multi-storage state non-volatile random access memory device has two or more memory cells. Each memory cell may include one or more programmable resistive devices that may be dynamically programmed to configure the memory cell in a particular logic state.

BACKGROUND

Static random-access memory (SRAM) is a semiconductor memory device that uses various mechanisms to store a state. For example, an SRAM can store a logic low, or “0,” state in one configuration and a logic high, or “1,” state in another configuration. An SRAM may be utilized in computer design because of its relatively low power consumption, speed, and simple operation. One application of an SRAM is as a configuration memory for a field-programmable gate array (FPGA). Other non-volatile FPGAs may use flash memories to store configuration data. SRAMs may typically be more expensive and less dense than dynamic random-access memory (DRAM). Thus, the use of SRAMs can be limited based on size and cost considerations.

SUMMARY

Briefly stated, technologies are generally described herein for a non-volatile static random-access memory (nvSRAM) device with multiple storage states. In some examples, the multi-storage state non-volatile static random access memory device may have two or more memory cells. Each memory cell may include one or more programmable resistive devices having resistance values that may be dynamically programmed during a write operation to configure the memory cell to a particular logic state. During a read operation, the resistance value of the particular pair of programmable resistive devices may be sensed as an indication of the logic state of the memory cell.

In one configuration, a multi-storage state non-volatile random access memory device is described. The multi-bit non-volatile random access memory device may include a first node, a first multi-bit storage circuit, a second multi-bit circuit, a reference circuit and a write enable circuit. The first multi-bit circuit may include a first transistor and a first programmable resistive device. The first terminal of the first transistor may be coupled to a second node, a control terminal of the first transistor coupled to a first write line, and a second terminal of the first transistor coupled to a third node. The first programmable resistive device may be coupled between the third node and a first bit line. A second multi-bit storage circuit may include a second transistor and a second programmable resistive device. The first terminal of the second transistor may be coupled to the second node, a control terminal of the second transistor coupled to a second write line, and a second terminal of the second transistor coupled to a fourth node. The second programmable resistive device may be coupled between the fourth node and the first bit line. The reference circuit may include a third transistor. The first terminal of the third transistor coupled to a second bit line, a second terminal of the third transistor coupled to the first node, and a control terminal of the third transistor coupled to a common write line. The write enable circuit may include a fourth transistor having a first terminal coupled to the first node, a second terminal coupled to the second node, and a control terminal coupled to a write enable line. The write enable circuit may be configured to activate in response to a write enable signal on the write enable line such that current flows either from the first bit line to the second bit line, or from the second bit line to the first bit line. A logic high state or a logic low state in may be stored in one or more of the first multi-bit storage circuit or the second multi-bit storage circuit.

In another configuration, a multi-bit non-volatile static random access memory device is described. The multi-bit non-volatile static random access memory device may include a write enable circuit, a common resistive circuit and a plurality of multi-bit storage circuits. The write enable circuit may be coupled to a first node and a second node, and an input terminal of the write enable circuit may be coupled a write enable line. The common resistive circuit may be coupled to a first bit line and to the first node. The plurality of multi-bit storage circuits may each include a first transistor that includes a first terminal coupled to the second node, a second terminal coupled to a first programmable resistive device, and a control terminal coupled to a write line. The first programmable resistive device may be coupled between the second terminal and a second bit line. A relative resistance value between the first programmable resistive device and the common resistive circuit may represent a value of a binary bit stored by one or more of the multi-bit storage circuits.

In yet another configuration, a multi-bit non-volatile random access memory device is described. The multi-bit non-volatile random access memory device may include a cross coupled inverter pair, a first series transistor-resistor pair, a second series transistor-resistor pair and a write circuit. The cross coupled inverter pair may be coupled between a first node and a second node. The first series transistor-resistor pair may include a first transistor coupled in series with a first resistive device. The first series transistor-resistor pair may be coupled between the first node and a first bit line and a control terminal of the first transistor coupled to a first word line. The second series transistor-resistor pair may include a second transistor coupled in series with a second resistive device. The second series transistor-resistor pair may be coupled between the second node and a second bit line and the control terminal of the second transistor may be coupled to a second word line. A write circuit may include a third transistor coupled between the first node and the first bit line and a fourth transistor coupled between the second node and the second bit line. The control terminals of the third transistor and the fourth transistor may be coupled to a write enable word line. The write circuit may be configured to activate to write a logic state to the memory device. The logic state may be represented by a differential resistance between the first series coupled transistor-resistor pairs and the second series coupled transistor-resistor pair.

In still yet another configuration a method operating a multi-bit non-volatile random access memory device is described. The method may include asserting a first signal to a first transistor to enable a current path between a first terminal of a first transistor and a first terminal of a second transistor. A second signal may be asserted to the first transistor and the second transistor to activate the first transistor and the second transistor. A voltage may be asserted to a first bit or a second bit line. Asserting the voltage to a first bit line may cause current flow from the first bit line through a first programmable resistive device, the first transistor, the second transistor, a second resistive device and out to a second bit line to store a first logic state. Asserting the voltage to the second bit line may case cause current flow from the second bit line through the second resistive device, the second transistor, the first transistor, the first programmable resistive device and out to the first bit line to store a second logic state.

In yet another configuration, a method to program an antifuse multi-bit non-volatile SRAM device is described. The method may include writing desired data into the SRAM device to make the inverter node that couples to the selected antifuse to a low voltage state. A wordline transistor of a selected antifuse may be activated and a programming voltage may be asserted to a first bit line to cause the selected antifuse to breakdown in a manner that reduces a resistance value of the selected antifuse.

In still yet another configuration, a multi-bit non-volatile static random access memory device is described. The device may include a cross coupled inverter pair coupled between a first node and a second node. A plurality of first transistor-resistor pairs may be coupled in series between the first node and a third node and coupled to a respective first word line. The third node may be coupled to a supply line through an enable transistor. A plurality of second transistor-resistor pairs may be coupled in series between the second node and the third node and coupled to a respective second word line. A first write transistor may be coupled between the first node and a first bitline, and a first control terminal coupled to a write enable word line. A second write transistor may be coupled between the second node and a second bitline, and a second control terminal coupled to the write enable word line. One or more of the first write transistor or the second write transistor can be activated to write a logic state to the memory device, the logic state represented by a differential resistance between at least one of the first series coupled transistor-resistor pairs and at least one of the second series coupled transistor-resistor pairs.

DETAILED DESCRIPTION

This disclosure is generally drawn, inter alia, to technologies for a multi-storage state nvSRAM which has a plurality of storage circuits (e.g., “memory cells”). In some embodiments, the memory cells in the multi-storage state nvSRAM may have the same logic state or different logic states. For example, a memory cell in the multi-storage state nvSRAM may have programmed therein one programmable resistive device with a high resistive state corresponding to a first logic value (e.g., logic high “1”) and another programmable resistive device with a low resistive state corresponding to a second logic value (e.g., logic low “0”), and variations thereof. Example logic values for the first and second logic values may correspond to high/high, low/low, high/low, and low/high combination of the resistive values. The terms “low” and “high” may be used in a relative sense and do not connote, and are not intended to specify, any particular measurement or degree.

In some additional configurations, memory cells in the multi-storage state nvSRAM may have two or more storage states depending on the number of programmable resistive devices (such as programmable resistors or programmable non-volatile memory transistors) that are used. As used herein, a “storage state” may be used in reference to the logic state of a memory cell in the nvSRAM. The term “storage state” as used herein generally is not an operational (or active) state of an nvSRAM device or one or more of nvSRAM cells, such as “standby,” “sensing,” and “writing.”

FIG. 1is a schematic circuit diagram illustrating an example multi-storage state nvSRAM device100that is arranged in accordance with at least some embodiments described herein. The nvSRAM device100may have a plurality of storage circuits, identified as a storage circuit101A, a storage circuit101B and storage circuit101C (and which may be generically referred to herein as “storage circuit[s]101”). Each of the storage circuits101may provide at least two storage or logic states. The circuit illustrated in dashed line110may also be a storage circuit101. AlthoughFIG. 1describes three different storage circuits, more or less storage circuits may be used according to various configurations described herein.

As illustrated, the nvSRAM device100may include transistors T1, T2, T3, T0, and T10, inverters I1and I2, and resistive devices R1, R2, R3, R0, and R10. Inverter I1may include an input terminal coupled to a node N2and an output terminal coupled to a node N1. Inverter I2may include an input terminal coupled to node N1and an output coupled to node N2.

Transistor T1may include a first terminal coupled to node N2, a second terminal coupled to resistive device R1, and a control terminal coupled to a first write line WL1. Transistor T2may include a first terminal coupled to node N2, a second terminal coupled to resistive device R2, and a control terminal coupled to a second write line WL2. Transistor T3may include a first terminal coupled to node N2, a second terminal coupled to resistive device R3, and a control terminal coupled to a third write line WL3. Transistor T10may include a first terminal coupled to resistive device R10, a second terminal coupled to node N1, and a control terminal coupled to the first write line WL1. Transistor Te may include a first terminal coupled to node N1, a second terminal coupled to node N2, and a control terminal coupled to a write enable line WE. Transistor T0may include a first terminal coupled to resistive device R0, a second terminal coupled to node N1, and a control terminal coupled to a common write line WLcom.

As illustrated inFIG. 1, resistive device R1may be coupled in series between transistor T1and bit line BL2. Resistive device R2may be coupled in series between transistor T2and bit line BL2. Resistive device R3may be coupled in series between transistor T3and bit line BL2. Resistive device R10may be coupled between transistor T10and bit line BL1. Resistive device R0may be coupled between transistor T0and bit line BL1.

The nvSRAM device100may be powered by a supply voltage Vdd. According to some examples, the logic state of an SRAM cell may be represented by a difference in the voltages of node N1and N2. For example, when N1is at the ground voltage, N2may be at the supply voltage Vdd due at least in part by the actions of the cross coupled inverters I1and I2. This state may be designated as a logic state “0” of an SRAM cell, which may be referred to herein as a logic low state. Conversely when N1is at Vdd, N2may be ground, and this state may be designated as a logic “1” state which may be referred to herein as a logic high state.

For the sake of simplicity of explanation herein, inversion circuitry will be generally described in the context of various inverters. Other types of inversion circuitry configured to provide inversion capability may be used, alternatively or additionally to inverters. Such other types of inversion circuitry may include, for example, inversion logic configurations and logic gates (NAND, NOR, AND, OR etc. suitably coupled to provide inversion), analog and/or digital inversion circuits, transformers, flip-flops, bistable latches, and/or others.

Various types of transistors may also be used. The following disclosure may use, for purposes of illustration, metal-oxide semiconductor field effect transistors (MOSFET). A MOSFET may have a source terminal (e.g., a first terminal), a drain terminal (e.g., a second terminal), and a control terminal. When an appropriate level of bias signal is applied to the control terminal, the transistor may be activated (e.g., biased into active operation) wherein conduction between the source terminal and the drain terminal may be facilitated. Depending on the type of transistor (e.g., N-type or P-type), an appropriate level of bias signal may be applied, or previously applied bias signal may be removed, to cause the transistor to be deactivated wherein conduction between the source and the drain may be abated. A MOSFET “terminal” may also be termed a “port.”

The following description describes one or more examples of the storing of logic states in the nvSRAM device100, in accordance with various configurations. The resistive devices (e.g., R0, R10, R1, R2, or R3) may be of fixed value or programmable type of resistors or a mixture thereof. According to some examples, the resistive devices, R1, R2, R3and R10may include magnetic tunnel junction (MTJ) programmable resistors, and resistive device R0may include a fixed value resistor with a resistance value between that of a low resistance state (“LRS”) and a high resistance state (“HRS”). In other configurations, the resistive devices may include one or more programmable non-volatile memory transistors that can be programmable to at least two resistance states (e.g., a LRS and a HRS). The characteristic of a MTJ programmable resistor may be such that when a current that exceeds a critical current density is passed through the MTJ programmable resistor in one direction, the MTJ programmable resistor may be in a LRS.

If a current is passed in the opposite direction, the MTJ programmable resistor may turn from a LRS to a HRS. The use of a magnetic tunnel junction resistor is for purposes of illustration only, and other types of programmable resistive devices may be used. The resistive devices may also be based on a conductive-bridge resistor, a metal-oxide bipolar filament, a metal-oxide bipolar interface effect, or an amorphous silicon switching medium. Other resistive devices may be used, including those that can be placed into a high resistance state or a low resistance state depending upon the voltage polarity and magnitude applied across two nodes. In some configurations, a relative resistance value between a first programmable resistive device and a second programmable resistive device may be used to store a binary bit.

The resistance value of the MTJ programmable resistors may depend, in part, on the relative magnetization direction of a first ferromagnetic layer to a second ferromagnetic layer, as well as the magnetic and physical properties of the layers themselves. If the resistors are implement technology based on a spin transfer torque (STT) magnetic tunnel junction resistor, a current may be introduced to control the magnetization direction of a free layer. The direction of magnetization may be controlled and switched via spin exchange between the electrons in the driving current and the electrons in the free layer. In some configurations, the use of a current may not involve the application of an external magnetic field. Any suitable method of introducing a spin-polarization current or applying a spin torque may be implemented in various embodiments. For example, spin torque may be applied using an external magnetic field in magnetic communication with the magnetic field of the first ferromagnetic layer. The programmable characteristics may be used in the nvSRAM device100to store multiple states and to change those states.

According to some configurations, the following illustrative procedure may be performed to store a logic “1” state in a memory cell of the nvSRAM device100. For example, to store a “1” in the storage circuit101A, the following procedure may be utilized. First, the write enable line WE and the write line WL1may be enabled, thereby activating transistors Te, T1and T10. Next, bit line BL2may be brought to ground and bit line BL1may be brought to a high voltage Vpp. In some examples, voltage Vpp may be higher during normal operations as compared to the power supply voltage Vdd. In response to bit line BL2being brought to ground and bit line BL1being brought to voltage Vpp, current may flow from bit line BL1to bit line BL2. Based on the direction of the current flow, resistive device R10may be turned to a HRS and resistive device R1may be turned to a LRS. A logic “1” state may thereby be stored in resistive devices R1and R10(e.g., non-volatile storage elements) as represented by their differential resistance value in the LRS and HRS state, respectively.

To store a “0” state within a non-volatile storage element (e.g., a resistive device), a similar procedure may be used to as used to store the logic high state. To store a logic low state (e.g., “0”), bit line BL1may be brought to ground and bit line BL2may be brought to voltage Vpp. In this example, current may flow in the opposite direction as compared to the procedure used to store the logic high state. When the current flows in the opposite direction as compared to the procedure used to store the logic high state, resistive device R10becomes a LRS and resistive device R1becomes a HRS.

A similar procedure may be used to store a logic low state or a logic high state in the other storage circuits (e.g., storage circuit101B or101C). For example, instead of activating write line WL1, write line WL2may be activated or write line WL3may be activated. In both cases, write line WLcom may be also activated to allow current to flow between bit line BL1and bit line BL2. In some configurations, a logic state may be stored in different memory cells during the same procedure. For example, two or more write lines (e.g., write lines WL1, WL2, or WL3) may be activated in parallel.

In some configurations, the resistive device R0may have a fixed resistance value between the resistance values of the LRS and the HRS. For example, current may be configured to flow from bit line BL2to bit line BL1by turning on transistors T0, Te, and T2to turn resistive device R2to a HRS. The differential resistance pair that comprises resistive devices R2and R0(with resistance values R2>R0) may be configured to store a state that can be turned into a “0” state for the SRAM cell. Similarly, resistive device R3may be moved to a LRS state. The differential resistance pair comprised of resistive devices R0and R3, (with resistance values R3<R0), may store a state that can be turned into a “1” state for the SRAM cell.

To restore the nvSRAM device100from the stored state (e.g., as represented by resistive devices R10and R1, or resistive devices R0and R2, or resistive devices R0and R3) from a powered off state to a logic high state, bit lines BL1and BL2may be set to ground, the respective transistors (e.g., transistors T10and T1, or transistors T0and T2, or transistors T0and T3) associated with the memory cell being restored may be activated, and the power supply to the inverters I1and I2may be brought to voltage Vdd. After performing these actions, the voltage at node N1may be higher than the voltage at node N2since the path from node N1to bit line BL1may have a higher total resistance value than the resistance for the path from node N2to bit line BL2. Due at least in part to the actions of the cross coupled inverter I1and I2, when the power is restored to voltage Vdd, node N1may become near voltage Vdd and node N2at ground, thereby restoring the SRAM cell to the logic high state (e.g., logic “1” state).

To restore a SRAM cell from the stored state to a logic low state (e.g. as represented by resistive device pair R0and R2), from a powered off state, bit lines BL1and BL2may be kept at ground, transistors T0and T2may be activated, and the power supply to the inverters I1and I2may be moved to voltage Vdd. After performing these operations, the voltage at node N2may be higher than the voltage at node N1since the path from node N2to bit line BL2may have a higher total resistance value than that of the path from node N1to bit line BL1. Due at least in part to the actions of the cross coupled inverters I1and I2, when the power supply to voltage Vdd is restored, node N2may move to voltage Vdd and node N1may move to ground, thereby restoring the respective storage circuit101to a logic “0” state.

According to some configurations, the active state of the nvSRAM device100may be switched to a stored state without turning off the power to the inverters. For example, the SRAM state may be in a logic high state with node N1at voltage Vdd and node N2at ground. To switch to the state stored in the resistive devices R2/R0(e.g., “0” in the above example), where the resistance value of resistive device R2is greater than the resistance value of resistive device R0, the following example procedure might be performed. First, the bit lines BL1and BL2may be kept at ground. The write enable WE signal may then be activated. Activating the WE signal may equalize the voltage at node N1and node N2since transistor Te is turned on (e.g., activated). The word line WLcom and word line WL2may then be enabled to turn on transistors T0and T2. At approximately the same time, transistor Te may be turned off by de-activating the write enable signal WE. Based at least in part on the cross coupled inverters I1and I2, the voltage at node N2may rapidly reach voltage Vdd while node N1may be at ground.

According to some examples, the resistance values for the programmable resistive devices may be set to around 20000 ohms in a HRS and set to a value of around 10000 ohms for a LRS. Other resistance values may be utilized. In other configurations (e.g. for that of antifuse), the HRS could have resistance of more than a giga (109) ohms while LRS could have resistance as little as 10 ohms. Generally, an antifuse may refer to a device that starts with a high resistance and is designed to create an electrically conductive path (e.g., when the voltage across the antifuse exceeds a certain level).

In some examples, the resistive device R0may include a fixed value resistor having a resistance value in between that of LRS and HRS. The resistive devices may be of other types such as conductive-bridge resistor, metal-oxide bipolar filament resistor, metal-oxide bipolar interface effect resistor, or an amorphous silicon switching medium resistor, or a fuse or antifuse element.

According to some configurations, as illustrated by dashed line110, the resistive device R10and transistor T10may be removed from the nvSRAM device100. In these examples, a single transistor-resistive device pair coupled to node N1may used as the reference pair for the programmable resistor-transistor pairs coupled to node N2.

FIG. 2is a schematic circuit diagram illustrating an example multi-storage state nvSRAM device200that removes the write enable transistor that is arranged in accordance with at least some embodiments described herein.FIG. 2is a variant of multi-bit non-volatile SRAM device100illustrated inFIG. 1. As illustrated, the nvSRAM device200may include transistors T0, T1, T2, T3, Tw1and TW2, inverters I1and I2, and resistive devices R0, R1, R2, and R3.

Inverter I1may include an input terminal coupled to node N2and an output terminal coupled to node N1. Inverter I2may include an input terminal coupled to node N1and an output terminal coupled to node N2.

Transistor T1may include a first terminal coupled to node N2, a second terminal coupled to resistive device R1, and a control terminal coupled to a first write line WL1. Transistor T2may include a first terminal coupled to node N2, a second terminal coupled to resistive device R2, and a control terminal coupled to a second write line WL2. Transistor T3may include a first terminal coupled to node N2, a second terminal coupled to resistive device R3, and a control terminal coupled to a third write line WL3. Transistor T10may include a first terminal coupled to resistive device R10, a second terminal coupled to node N1, and a control terminal coupled to the first write line WL1. Transistor T0may include a first terminal coupled to resistive device R0, a second terminal coupled to node N1, and a control terminal coupled to a common write line WLcom. Transistor Tw1may include a first terminal coupled to bit line BL1, a second terminal coupled to node N1, and a control terminal coupled to a write line WL0. Transistor Tw2may include a first terminal coupled to N1, a second terminal coupled to bit line BL1, and a control terminal coupled to a write line WL0.

As illustrated inFIG. 2, resistive device R1may be coupled in series between transistor T1and bit line BL2. Resistive device R2may be coupled in series between transistor T2and bit line BL2. Resistive device R3may be coupled in series between transistor T3and bit line BL2. Resistive device R10may be coupled between transistor T10and bit line BL1. Resistive device R0may be coupled between transistor T0and bit line BL1.

Compared to nvSRAM device100, in the nvSRAM device200the write line transistor and resistors pair T10-R10may be removed. The transistor-resistor pair T10-R10, may be replaced by two write transistors Tw1and Tw2, whose control terminals may be coupled to a wordline WL0. These two transistors Tw1and Tw2may form a write port210for the nvSRAM device200through which a logic state may be written to an SRAM cell. For example, node N1can be moved to voltage Vdd while node N2can be made to be at ground by turning bit line BL1to voltage Vdd and bit line BL2to ground and enabling the write wordline WL0.

According to some configurations, the logic state of an SRAM cell may be stored to a resistive device pair (e.g., to the resistive pairs comprised of resistive devices R2and R0, R1and R0, or R3and R0) by the following example procedure. First, the power supply voltage may be brought to a voltage Vpp that may be higher than voltage Vdd. In the above example described inFIG. 1where the SRAM is in a “1’ state, node N1may be at voltage Vpp and node N2may be at ground. Both bit lines BL1and BL2may be brought to voltage Vpp/2and word lines WLcom and WL2may be activated. As a result of these operations, current may flow from node N1to bit line BL1and from bit line BL2to node N2. The direction of current flow through resistive device R2may be such that the programmable resistive device R2may change into a LRS, and have a lesser resistance value than the fixed resistive device R0.

To restore the SRAM cell from the stored state (e.g., as represented by the resistive pairs R2and R0, R1and R0, or R3and R0), from a powered off state, both bit lines BL1and BL2may be set to ground, the transistors T0and the associated transistor for the memory cell (e.g., transistors T1, T2, and/or T3) may be activated, and then the inverters (I1and I2) may be brought to voltage Vdd. Since the path from node N2to bit line BL2may have a lower total resistance value than that of the path from node N1to bit line BL1, the voltage at node N2may be lower than the voltage at node N1. Based at least in part on the actions of the cross coupled inverters I1and I2, when the power supply is restored to voltage Vdd, node N1may be at voltage Vdd and node N2at ground, thereby restoring the SRAM cell to a logic “1” state.

FIG. 3is a schematic circuit diagram illustrating another example of a multi-storage state nvSRAM device300that is arranged in accordance with at least some embodiments described herein. As illustrated, the nvSRAM device300may include transistors T0, T1, T2, T3, Tw1, Tw2and Ten, inverters I1and I2, and resistive devices R0, R1, R2, and R3.

Inverter I1may include an input terminal coupled to node N1and an output terminal coupled to node N2. Inverter I2may include an input terminal coupled to node N2and an output terminal coupled to node N2.

Transistor T0may include a first terminal coupled to resistive device R0, a second terminal coupled to node N1, and a control terminal coupled to a common write line WLcom. Transistor T1may include a first terminal coupled to node N2, a second terminal coupled to resistive device R1, and a control terminal coupled to a first write line WL1. Transistor T2may include a first terminal coupled to node N2, a second terminal coupled to resistive device R2, and a control terminal coupled to a second write line WL2. Transistor T3may include a first terminal coupled to node N2, a second terminal coupled to resistive device R3, and a control terminal coupled to a third write line WL3.

Transistor Tw1may include a first terminal coupled to bit line BL1, a second terminal coupled to node N1, and a control terminal coupled to a write line WL0. Transistor Tw2may include a first terminal coupled to N2, a second terminal coupled to bit line BL2, and a control terminal coupled to a write line WL0. Transistor Ten may include a first terminal coupled to node N310, a second terminal coupled to Vdd, and a control terminal coupled to an enable line EN.

As illustrated inFIG. 3, resistive device R1may be coupled in series between transistor T1and node N310. Resistive device R2may be coupled in series between transistor T2node N310. Resistive device R3may be coupled in series between transistor T3and node N310. Resistive device R0may be coupled between transistor T0and node N310.

As illustrated, the nvSRAM device300may comprise three non-volatile storage elements formed by transistor-resistive device pairs T1and R1, T2and R2, and T3and R3. The reference circuit, transistor-resistor pair T0-R0, may be coupled between node N1and voltage Vdd through transistor Ten.

The transistors Tw1and Tw2may be configured to form a write port for the SRAM cell through which a logic state can be written to the SRAM cell. For example node N1can be written to voltage Vdd while node N2may be made to be at ground by turning bit line BL1to voltage Vdd and bit line BL2to ground and enabling the write word line WL0. As previously discussed, the resistive devices R1, R2, R3may be of a programmable type, e.g. non-volatile memory transistors such as a floating gate transistor or a charge trapping transistor, MTJ resistors, resistive oxide memory type of resistors, or a fuse or antifuse element (and/or other resistor device types), that can have at least two possible resistance values, a HRS and a LRS. In some examples, fixed value resistive device R0may be chosen to have a resistance value that is between the HRS and LRS values.

FIG. 4is a schematic circuit diagram illustrating a multi-storage state nvSRAM device400utilizing capacitors as resistive devices, that is arranged in accordance with at least some embodiments described herein. As illustrated, the nvSRAM device400may comprise three non-volatile storage elements formed by transistor-resistive device pairs T1and C1, T2and C2, and T3and C3. As shown, the nvSRAM device400may include transistors T0, T1, T2, T3, Tw1and Tw2, inverters I1and I2, and resistive devices R0, capacitor C1, capacitor C2, and capacitor C3.

Inverter I1may include an input terminal coupled to node N2and an output terminal coupled to node N1. Inverter I2may include an input terminal coupled to node N2and an output terminal coupled to node N2.

Transistor T0may include a first terminal coupled to resistive device R0, a second terminal coupled to node N1, and a control terminal coupled to a common write line WLcom. Transistor T1may include a first terminal coupled to node N2, a second terminal coupled to resistive device C1, and a control terminal coupled to a first write line WL1. Transistor T2may include a first terminal coupled to node N2, a second terminal coupled to resistive device C2, and a control terminal coupled to a second write line WL2. Transistor T3may include a first terminal coupled to node N2, a second terminal coupled to resistive device C3, and a control terminal coupled to a third write line WL3.

Transistor Tw1may include a first terminal coupled to bit line BL1, a second terminal coupled to node N1, and a control terminal coupled to a write line WL0. Transistor Tw2may include a first terminal coupled to N2, a second terminal coupled to bit line BL2, and a control terminal coupled to a write line WL0.

Resistive device C1may be embodied as a capacitor that is coupled in series between transistor T1and bit line BL2. Resistive device R2may be embodied as a capacitor that is coupled in series between transistor T2and bit line BL2. Resistive device R3may be embodied a capacitor that is coupled in series between transistor T3and bit line BL2. Resistive device R0may be coupled between transistor T0and node N1.

According to some configurations, as an alternate to the use of programmable resistive devices for storage of logic states, capacitors (e.g., capacitors C1, C2and C3) may be utilized. Since capacitors may leak charge at a certain rate and need to be refreshed, the device may not be of non-volatile type.

During an example operation, to store a logic state in the capacitor (e.g. a logic low state “0” in capacitor C2), the corresponding wordline transistor T2may be activated by WL2, and capacitor C2may be charged to voltage Vdd. To restore the state stored in capacitor C2, nodes N1and N2may be brought to Vdd/2by setting bit lines BL1and BL2to voltage Vdd/2and enabling wordline WL0. When wordline WL0is turned off and then wordline WL2is enabled, the node N2may be at a higher voltage if a “1” is stored in capacitor C2and restored to Vdd. On the other hand, if a “0” is stored in capacitor C2, node N2may be at a lower voltage than node N1due to the extra capacitance and reset to ground, thereby restoring the SRAM cell to a “0” state.

In some examples, an equalization circuit may be utilized in the nvSRAM device400. The equalization circuit may comprise an equalization transistor Te that is placed between node N1and node N2. To restore a state stored in a capacitor (e.g. capacitor C2), the equalization transistor Te may be turned on by enabling the write enable signal WE. This may equalize the voltages at node N1and N2. Transistor Te may be turned off and then WL2may be enabled, and the node N2may be at a higher voltage if a “1” is stored in capacitor C2and restored to Vdd. On the other hand, if a “0” is stored in capacitor C2, node N2may be at a lower voltage than node N1due to the extra capacitance and reset to ground, thereby restoring the SRAM to a “0” state.

According to some configurations, one or more programmable resistors may be embodied as an antifuse. An antifuse may include a thin oxide capacitor or an amorphous Si resistor and have an effective resistance value in the giga ohm range or more. In response to applying a voltage that exceeds the breakdown voltage of the oxide, the oxide may break down and the resulting resistance value is much reduced, e.g. to 10-100 s of ohms. This type of resistor may be typically programmed only once.

Because of the high voltage to break down an antifuse, an antifuse procedure may be used to program antifuses. According to some examples, the following antifuse procedure may be utilized. InFIG. 4, assume that resistive device R0is a fixed value resistor, e.g. 1 k ohms, resistive devices C1, C2, and C3are antifuses, which are normally in the open, HRS, state. To program the capacitor C2, e.g., break the capacitor C2so that it turns into a LRS, without affecting capacitors C1and C3, capacitor C1and C3may be charged to an intermediate voltage Vm, e.g. charged to the supply voltage Vdd. This may result in the capacitors C1and C3to be at approximately voltage Vdd. The SRAM cell is then programmed to a “0” state, with node N2at ground. Write line WL2is then enabled to activate transistor T2which will bring the capacitor C2to ground as well. Bit line BL2may be ramped to a high voltage Vpp that is sufficient to breakdown capacitor C2. Since the voltage across capacitors C1and C2is less, approximately at voltage Vpp-Vm, these antifuses may be safe from breaking and may remain at HRS.

FIG. 5is a schematic circuit diagram illustrating an example multi-storage state nvSRAM device500for use in low voltage operation that is arranged in accordance with at least some embodiments described herein. As illustrated, the nvSRAM device500may include the nvSRAM device100such as previously described, a transistor Trb, and a transistor Trw.

Transistor Trb may include a first terminal coupled to a terminal of transistor Trw, a second terminal coupled to ground, and a control terminal coupled to node N1. Transistor Trw may include a first terminal coupled to a read bit line RBL, a second terminal coupled to the first terminal of transistor Trw, and a control terminal coupled to a read write line RWL. According to some configurations, the two transistors Trw and Trb may be used to read the logic state of the SRAM cell with less disturbance to an SRAM cell itself.

FIG. 6is a schematic circuit diagram illustrating an example multi-storage state nvSRAM device600including read transistors that is arranged in accordance with at least some embodiments described herein. As illustrated, the nvSRAM device600may include the nvSRAM device100as previously described, a transistor Trb1and a transistor Trb2.

InFIG. 6, an alternate set of read transistors are added to the SRAM cell. Transistor Trb1may include a first terminal coupled to a read write line RWL, a second terminal coupled to a read bit line RBL1, and a control terminal coupled to node N1. Transistor Trb2may include a first terminal coupled to the read write line RWL, a second terminal coupled to a read bit line RBL2, and a control terminal coupled to node N2. When the read word line (RWL) is enabled, the logic state of read bit lines RBL1and RBL2may take the logic state of node N1and node N2, respectively. Read bit line RBL2may normally be the inverted signal of RBL1. The circuits outside the dashed box100may be used to read the logic state of the SRAM cell with less disturbance to the SRAM cell itself. This method can be applied to all the SRAM cells disclosed in this application.

FIG. 7is a signal timing diagram showing an example write operation, such as for the first memory cell of the nvSRAM device100ofFIG. 1, arranged in accordance with at least some embodiments presented herein. InFIG. 7, the example signals may include the write enable line WE, the first write line WL1for the storage circuit101A, the first bit line BL1, and the second bit line BL2. To write a logic high, or a logical “1,” into the storage circuit101A, at time t1, the write enable line WE and the first write line WL1may be asserted (e.g., a logic high level or logic 1 level such as Vdd). The first bit line BL1may be brought to a voltage higher than the high supply voltage (e.g., voltage Vpp), while the second bit line BL2may be maintained at a low supply voltage (e.g., voltage Vss), or ground.

Transistors T10and T1may be activated in response to the asserted the first write line WL1, transistor Te may be activated in response to the asserted write enable line WE, and a conduction path may be formed between the first bit line BL1to the second bit line BL2through the first programmable resistive device R10, the transistor T10, transistor Te, the second transistor T1, and the second programmable resistive device R1. In some configurations, the first bit line BL1may be brought to the voltage at a different time than when the write enable line WE and the first write line WL1are asserted. In some examples, a delay may be inserted to help ensure that transistors are fully activated and/or deactivated.

To finalize the programming of the first programmable resistive device R10and the second programmable resistive device R1, at time t2, the first bit line BL may be brought to a low level, such as a low power supply level (e.g., voltage Vss) or ground. Either simultaneously or at a time proximate to the time at which the first bit line BL is brought to the low level, such as time t3, the write enable line WE and the first write line WL1may be de-asserted (e.g., brought to a low power supply level or ground).

In some configurations, a time delay may be inserted between the time at which the first bit line BL is brought to a low level and the time at which the write enable line WE and the first write line WL1are brought to a low level. The time delay may be used to increase the probability that the logic high was written onto the storage circuits (e.g., resistive device R10and R1). The write enable line WE and the first write line WL1may be maintained at the high level for a certain duration of time. In some implementations, the pulse width of the write enable line WE and the first write line WL1may be from approximately 5 nanoseconds to approximately 50 nanoseconds, for example.

To write a logic LOW, or logical “0,” to the storage circuit R10and R0, at time t4, the write enable line WE and the first write line WL1may be asserted (e.g., brought to a high level such as Vdd, Logic “1” or logic high). When the second bit line BL2is brought to a high voltage level, current may flow from the second bit line BL2to the first bit line BL1through a current path from the second bit line BL2, the second programmable resistive device R1, the transistor T1, the transistor T10, the first programmable resistive device R10and to the first bit line BL1. This direction of current flow may cause the second programmable resistive device R1to be programmed to a parallel configuration and the first programmable resistive device R10to be programmed to an anti-parallel configuration.

To finalize the programming of the first programmable resistive device R10and the second programmable resistive device R0, at time t5, the second bit line BL2may be brought to a low level, such as ground. Either simultaneously or at a time proximate to the time to which the second bit line BL2is brought to a low level, such as time t6, the write enable line WE and the first write line WL1may be de-asserted (e.g., brought to a low level, typically ground). In some configurations, a time delay may be inserted between the time at which the second bit line BLN is brought to a low level and the time at which the write enable line WE and the first write line WL1are brought to a low level. The time delay may be used to increase the probability that the logic low has been successfully written.

FIG. 8is a block diagram illustrating an example computing device800that is arranged to implement an nvSRAM arranged in accordance with at least some embodiments described herein. In a very basic configuration801, computing device800typically includes one or more processors810and system memory820. A memory bus830can be used for communicating between the processor810and the system memory820.

Depending on the desired configuration, processor810can be of any type including but not limited to a microprocessor (μR), a microcontroller (μC), a digital signal processor (DSP), or any combination thereof. Processor810can include one more levels of caching, such as a level one cache811and a level two cache812, a processor core813, and registers814. The processor core813can include an arithmetic logic unit (ALU), a floating point unit (FPU), a digital signal processing core (DSP core), or any combination thereof. A memory controller815can also be used with the processor810, or in some implementations the memory controller815can be an internal part of the processor810.

Depending on the desired configuration, the system memory820can be of any type including but not limited to volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.) or any combination thereof. System memory820typically includes an operating system821, one or more applications822, and program data824. Application822includes an nvSRAM implementation algorithm823that is arranged to implement or operate an nvSRAM. Program Data824includes nvSRAM implementation data825that is useful for implementing or operating an nvSRAM. In some embodiments, application822can be arranged to operate with program data824on an operating system821such that various components of the computing device can implement or operate an nvSRAM. This described basic configuration is illustrated inFIG. 8by those components within dashed line801.

Computing device800can have additional features or functionality, and additional interfaces to facilitate communications between the basic configuration801and any required devices and interfaces. For example, a bus/interface controller840can be used to facilitate communications between the basic configuration801and one or more data storage devices850via a storage interface bus841. The data storage devices850can be removable storage devices851, non-removable storage devices852, or a combination thereof. Examples of removable storage and non-removable storage devices include magnetic disk devices such as flexible disk drives and hard-disk drives (HDDs), optical disk drives such as compact disk (CD) drives or digital versatile disk (DVD) drives, solid state drives (SSDs), and tape drives to name a few. Example computer storage media can include volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data.

System memory820, removable storage devices851and non-removable storage devices852are all examples of computer storage media. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVDs) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by computing device800. Any such computer storage media can be part of computing device800.

Computing device800can also include an interface bus842for facilitating communication from various interface devices (e.g., output interfaces, peripheral interfaces, and communication interfaces) to the basic configuration801via the bus/interface controller840. Example output devices860include a graphics processing unit861and an audio processing unit862, which can be configured to communicate to various external devices such as a display or speakers via one or more A/V ports863. Example peripheral interfaces870include a serial interface controller871or a parallel interface controller872, which can be configured to communicate with external devices such as input devices (e.g., keyboard, mouse, pen, voice input device, touch input device, etc.) or other peripheral devices (e.g., printer, scanner, etc.) via one or more I/O ports873. An example communication device880includes a network controller881, which can be arranged to facilitate communications with one or more other computing devices890over a network communication via one or more communication ports882. The communication connection is one example of a communication media. Communication media may typically be embodied by computer readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave or other transport mechanism, and includes any information delivery media. A “modulated data signal” can be a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, communication media can include wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, radio frequency (RF), infrared (IR) and other wireless media. The term computer readable media as used herein can include both storage media and communication media.

For example, the series positions of the resistor-transistor pairs in one or more of the figures or in other configurations might be “swapped” in some embodiments, such that the resistor may be placed to the “right” or to the “left” of the corresponding transistor. Still in other embodiments, the internal resistance of a transistor may be used to provide the functionality of a discrete resistive device in the various configurations. Other possible implementations for a resistive device may include polysilicon resistors, diffusion resistors, carbon metal file resistors, ceramic resistors, transformers biased as a resistor, or other device(s) having resistive material.

It will be understood by those within the art that, in general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as “open” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “includes but is not limited to,” etc.). It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases “at least one” and “one or more” to introduce claim recitations.

However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim recitation to embodiments containing only one such recitation, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and/or “an” should be interpreted to mean “at least one” or “one or more”); the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the bare recitation of “two recitations,” without other modifiers, means at least two recitations, or two or more recitations).

Further, the use of the terms “first,” “second,” “third,” “fourth,” and the like is to distinguish between repeated instances of a component or a step in a process and does not impose a serial or temporal limitations unless specifically stated to require such serial or temporal order.

While various aspects and embodiments have been disclosed herein, other aspects and embodiments are possible. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.