Chip package and method for fabricating the same

A method for fabricating chip package includes providing a semiconductor chip with a bonding pad, comprising an adhesion/barrier layer, connected to a pad through an opening in a passivation layer, next adhering the semiconductor chip to a substrate using a glue material, next bonding a wire to the bonding pad and to the substrate, forming a polymer material on the substrate, covering the semiconductor chip and the wire, next forming a lead-free solder ball on the substrate, and then cutting the substrate and polymer material to form a chip package.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a chip package, and, more specifically, to a chip package with a specific pad between a bonding wire and an aluminum pad exposed by an opening in a passivation layer or between a bonding wire and an aluminum cap, leading the intermetallic compound (IMC) to be avoided.

2. Brief Description of the Related Art

Wirebonding is the process of providing electrical connection between a semiconductor chip and an external circuit using very fine bonding wires. The wire used in wirebonding is usually made either of gold (Au).

Referring toFIG. 1, in the prior art of a BGA (ball grid array) package, one end of a gold wire110is ball bonded to an aluminum cap114over a copper pad120exposed by an opening118ain a passivation layer118of a semiconductor chip112, and the other end of the gold wire110is wedge bonded to a BGA substrate116. The copper pad120of the semiconductor chip112can be electrically connected to a solder ball122under the BGA substrate116via the gold wire110and a metal trace of the BGA substrate116.

However, the intermetallic compound (IMC) could be formed the gold wire110and the aluminum cap114in the following high-temperature packaging process, such as in the lead-free ball planting process. The intermetallic compound has a brittle structure, leading a poor reliability for the BGA package. Besides, the gold wire110in a high-power application could be heated at a high temperature, which also could lead the undesired intermetallic compound (IMC) formed the gold wire110and the aluminum cap114.

SUMMARY OF THE INVENTION

It is the objective of the invention to provide a chip package for eliminating inter-metallic-compound (IMC) formation during a packaging process.

It is the objective of the invention to provide a chip package for improving the product reliability under the lead-free industrial requirement.

It is the objective of the invention to provide a chip package with a good electrical performance.

In order to reach the above objectives, the present invention provides a chip package comprising: a ball-grid-array (BGA) substrate, a glue material, such as epoxy based material or polyimide (PI), on a top surface of the BGA substrate, a semiconductor chip on the glue material, wherein the semiconductor chip comprises a passivation layer over a circuit structure, an opening in the passivation layer exposing a pad of the circuit structure, and a bonding pad over the pad exposed by the opening, a wire bonded to the bonding pad and to the BGA substrate, a polymer material, such as epoxy based material, benzocyclobutane (BCB) or polyimide, on the top surface of the BGA substrate, covering the semiconductor chip and the wire, and a lead-free solder ball on a bottom surface of the BGA substrate.

In order to reach the above objectives, the present invention provides a chip package comprising: a BGA substrate, a glue material, such as epoxy based material or polyimide (PI), on a top surface of the BGA substrate, a semiconductor chip on the glue material, wherein the semiconductor chip comprises a passivation layer over a circuit structure, an opening in the passivation layer exposing a pad of the circuit structure, and a bonding pad connected to the pad through the opening, a wire bonded to the bonding pad and to the BGA substrate, a polymer material, such as epoxy based material, benzocyclobutane (BCB) or polyimide, on the top surface of the BGA substrate, covering the semiconductor chip and the wire, and a lead-free solder ball on a bottom surface of the BGA substrate.

In order to reach the above objectives, the present invention provides a chip package comprising: a lead frame, a glue material, such as epoxy based material or polyimide (PI), on a die pad of the lead frame, a semiconductor chip on the glue material, wherein the semiconductor chip comprises a passivation layer over a circuit structure, an opening in the passivation layer exposing a pad of the circuit structure, and a bonding pad over the pad exposed by the opening, a wire bonded to the bonding pad and to a lead of the lead frame, a polymer material, such as epoxy based material, benzocyclobutane (BCB) or polyimide, enclosing the die pad, an inner partition of the lead, the semiconductor chip and the wire.

In order to reach the above objectives, the present invention provides a chip package comprising: a lead frame, a glue material, such as epoxy based material or polyimide (PI), on a die pad of the lead frame, a semiconductor chip on the glue material, wherein the semiconductor chip comprises a passivation layer over a circuit structure, an opening in the passivation layer exposing a pad of the circuit structure, and a bonding pad connected to the pad through the opening, a wire bonded to the bonding pad and to a lead of the lead frame, a polymer material, such as epoxy based material, benzocyclobutane (BCB) or polyimide, enclosing the die pad, an inner partition of the lead, the semiconductor chip and the wire.

In order to reach the above objectives, a method for fabricating a chip package comprises the following steps: providing a semiconductor chip with a bonding pad connected to a pad through an opening in a passivation layer, adhering the semiconductor chip to a top surface of a BGA substrate, bonding a wire to the bonding pad and to the BGA substrate, forming a polymer material on the top surface of the BGA substrate, covering the semiconductor chip and the wire, depositing a lead-free solder on a bottom surface of the BGA substrate, reflowing the lead-free solder at a temperature of between 200 and 300° C., and preferably between 230 and 260° C., to form a lead-free solder ball joined with the bottom surface of the BGA substrate, and cutting the polymer material and the BGA substrate.

To enable the objectives, technical contents, characteristics and accomplishments of the present invention, the embodiments of the present invention are to be described in detail in cooperation with the attached drawings below.

DETAILED DESCRIPTION OF THE INVENTION

Referring toFIG. 2A, a semiconductor substrate or semiconductor blank wafer2may be a silicon substrate or silicon wafer, a GaAs substrate or GaAs wafer, or a SiGe substrate or SiGe wafer. Multiple semiconductor devices4are formed in or over the semiconductor substrate2. The semiconductor device4may be a memory device, a logic device, a passive device, such as resistor, capacitor, inductor or filter, or an active device, such as p-channel MOS device, n-channel MOS device, CMOS (Complementary Metal Oxide Semiconductor), BJT (Bipolar Junction Transistor) or BiCMOS (Bipolar CMOS) device.

A circuit structure6, fine line metal trace structure, is formed over the semiconductor substrate2and connect to the semiconductor device4. The circuit structure6comprises multiple patterned metal layers8having a thickness t1of less than 3 micrometers (such as between 0.2 and 2 μm) and multiple metal plugs10. For example, the patterned metal layers8and the metal plugs10are principally made of copper, wherein the patterned metal layer8is a copper layer having a thickness of less than 3 μm (such as between 0.2 and 2 μm). Alternatively, the patterned metal layer8is principally made of aluminum or aluminum-alloy, and the metal plug10is principally made of tungsten, wherein the patterned metal layer8is an aluminum-containing layer having a thickness of less than 3 μm (such as between 0.2 and 2 μm).

One of the patterned metal layers8may be formed by a damascene process including sputtering an adhesion/barrier layer, such as tantalum or tantalum nitride, on an insulating layer, composed of Low-K oxide and oxynitride, and in an opening in the insulating layer, then sputtering a first copper layer on the adhesion/barrier layer, then electroplating a second copper layer on the first copper layer, then removing the first and second copper layers and the adhesion/barrier layer outside the opening in the insulating layer using a chemical mechanical polishing (CMP) process. Alternatively, one of the patterned metal layer8may be formed by a process including sputtering an aluminum-alloy layer, containing more than 90 wt % aluminum and less than 10 wt % copper, on an insulating layer, such as oxide, then patterning the aluminum-alloy layer using photolithography and etching processes.

Multiple dielectric layers12having a thickness t2of less than 3 micrometers, such as between 0.3 and 2.5 μm, are located over the semiconductor substrate2and interposed respectively between the neighboring patterned metal layers8, and the neighboring patterned metal layers8are interconnected through the metal plugs10inside the dielectric layer12. The dielectric layer12is commonly formed by a chemical vapor deposition (CVD) process. The material of the dielectric layer12may include silicon oxide, silicon oxynitride, TEOS (Tetraethoxysilane), a compound containing silicon, carbon, oxygen and hydrogen (such as SiwCxOyHz), silicon nitride (such as Si3N4), FSG (Fluorinated Silicate Glass), Black Diamond, SiLK, a porous silicon oxide, a porous compound containing nitrogen, oxygen and silicon, SOG (Spin-On Glass), BPSG (borophosphosilicate glass), a polyarylene ether, PBO (Polybenzoxazole), or a material having a low dielectric constant (K) of between 1.5 and 3, for example.

A passivation layer14is formed over the circuit structure6and over the dielectric layers12. The passivation layer14can protect the semiconductor devices4and the circuit structure6from being damaged by moisture and foreign ion contamination. In other words, mobile ions (such as sodium ion), transition metals (such as gold, silver and copper) and impurities can be prevented from penetrating through the passivation layer14to the semiconductor devices4, such as transistors, polysilicon resistor elements and polysilicon-polysilicon capacitor elements, and to the circuit structure6.

The passivation layer14is commonly made of silicon oxide (such as SiO2), silicon oxynitride, silicon nitride (such as Si3N4), or PSG (phosphosilicate glass). The passivation layer14commonly has a thickness t3of more than 0.3 μm, such as between 0.3 and 1.5 μm. In a preferred case, the silicon nitride layer in the passivation layer14has a thickness of more than 0.3 μm. Ten methods for depositing the passivation layer14are described as below.

In a first method, the passivation layer14is formed by depositing a silicon oxide layer with a thickness of between 0.2 and 1.2 μm using a CVD method and then depositing a silicon nitride layer with a thickness of 0.2 and 1.2 μm on the silicon oxide layer using a CVD method.

In a second method, the passivation layer14is formed by depositing a silicon oxide layer with a thickness of between 0.2 and 1.2 μm using a CVD method, next depositing a silicon oxynitride layer with a thickness of between 0.05 and 0.15 μm on the silicon oxide layer using a Plasma Enhanced CVD (PECVD) method, and then depositing a silicon nitride layer with a thickness of between 0.2 and 1.2 μm on the silicon oxynitride layer using a CVD method.

In a third method, the passivation layer14is formed by depositing a silicon oxynitride layer with a thickness of between 0.05 and 0.15 μm using a CVD method, next depositing a silicon oxide layer with a thickness of between 0.2 and 1.2 μm on the silicon oxynitride layer using a CVD method, and then depositing a silicon nitride layer with a thickness of between 0.2 and 1.2 μm on the silicon oxide layer using a CVD method.

In a fourth method, the passivation layer14is formed by depositing a first silicon oxide layer with a thickness of between 0.2 and 0.5 μm using a CVD method, next depositing a second silicon oxide layer with a thickness of between 0.5 and 1 μm on the first silicon oxide layer using a spin-coating method, next depositing a third silicon oxide layer with a thickness of between 0.2 and 0.5 μm on the second silicon oxide layer using a CVD method, and then depositing a silicon nitride layer with a thickness of 0.2 and 1.2 μm on the third silicon oxide using a CVD method.

In a fifth method, the passivation layer14is formed by depositing a silicon oxide layer with a thickness of between 0.5 and 2 μm using a High Density Plasma CVD (HDP-CVD) method and then depositing a silicon nitride layer with a thickness of 0.2 and 1.2 μm on the silicon oxide layer using a CVD method.

In a sixth method, the passivation layer14is formed by depositing an Undoped Silicate Glass (USG) layer with a thickness of between 0.2 and 3 μm, next depositing an insulating layer of TEOS, PSG or BPSG (borophosphosilicate glass) with a thickness of between 0.5 and 3 μm on the USG layer, and then depositing a silicon nitride layer with a thickness of 0.2 and 1.2 μm on the insulating layer using a CVD method.

In a seventh method, the passivation layer14is formed by optionally depositing a first silicon oxynitride layer with a thickness of between 0.05 and 0.15 μm using a CVD method, next depositing a silicon oxide layer with a thickness of between 0.2 and 1.2 μm on the first silicon oxynitride layer using a CVD method, next optionally depositing a second silicon oxynitride layer with a thickness of between 0.05 and 0.15 μm on the silicon oxide layer using a CVD method, next depositing a silicon nitride layer with a thickness of between 0.2 and 1.2 μm on the second silicon oxynitride layer or on the silicon oxide using a CVD method, next optionally depositing a third silicon oxynitride layer with a thickness of between 0.05 and 0.15 μm on the silicon nitride layer using a CVD method, and then depositing a silicon oxide layer with a thickness of between 0.2 and 1.2 μm on the third silicon oxynitride layer or on the silicon nitride layer using a CVD method.

In a eighth method, the passivation layer14is formed by depositing a first silicon oxide layer with a thickness of between 0.2 and 1.2 μm using a CVD method, next depositing a second silicon oxide layer with a thickness of between 0.5 and him on the first silicon oxide layer using a spin-coating method, next depositing a third silicon oxide layer with a thickness of between 0.2 and 1.2 μm on the second silicon oxide layer using a CVD method, next depositing a silicon nitride layer with a thickness of between 0.2 and 1.2 μm on the third silicon oxide layer using a CVD method, and then depositing a fourth silicon oxide layer with a thickness of between 0.2 and 1.2 μm on the silicon nitride layer using a CVD method.

In a ninth method, the passivation layer14is formed by depositing a first silicon oxide layer with a thickness of between 0.5 and 2 μm using a HDP-CVD method, next depositing a silicon nitride layer with a thickness of between 0.2 and 1.2 μm on the first silicon oxide layer using a CVD method, and then depositing a second silicon oxide layer with a thickness of between 0.5 and 2 μm on the silicon nitride using a HDP-CVD method.

In a tenth method, the passivation layer14is formed by depositing a first silicon nitride layer with a thickness of between 0.2 and 1.2 μm using a CVD method, next depositing a silicon oxide layer with a thickness of between 0.2 and 1.2 μm on the first silicon nitride layer using a CVD method, and then depositing a second silicon nitride layer with a thickness of between 0.2 and 1.2 μm on the silicon oxide layer using a CVD method.

An opening14ain the passivation layer14exposes a pad16of the circuit structure6used to input or output signals or to be connected to a power source or a ground reference. The pad16may have a thickness t4of between 0.4 and 3 μm or between 0.2 and 2 μm. For example, the pad16may be composed of a sputtered aluminum layer or a sputtered aluminum-copper-alloy layer with a thickness of between 0.2 and 2 μm. Alternatively, the pad16may include an electroplated copper layer with a thickness of between 0.2 and 2 μm, and a barrier layer, such as tantalum or tantalum nitride, on a bottom surface and side walls of the electroplated copper layer.

Therefore, the pad16can be an aluminum pad, principally made of sputtered aluminum with a thickness of between 0.2 and 2 μm. Alternatively, the pad16can be a copper pad, principally made of electroplated copper with a thickness of between 0.2 and 2 μm.

The opening14amay have a transverse dimension d, from a top view, of between 0.5 and 20 μm or between 20 and 200 μm. The shape of the opening14afrom a top view may be a circle, and the diameter of the circle-shaped opening14amay be between 0.5 and 20 μm or between 20 and 200 μm. Alternatively, the shape of the opening14afrom a top view may be a square, and the width of the square-shaped opening14amay be between 0.5 and 20 μm or between 20 and 200 μm. Alternatively, the shape of the opening14afrom a top view may be a polygon, such as hexagon or octagon, and the polygon-shaped opening14amay have a width of between 0.5 and 20 μm or between 20 and 200 μm. Alternatively, the shape of the opening14afrom a top view may be a rectangle, and the rectangle-shaped opening14amay have a shorter width of between 0.5 and 20 μm or between 20 and 200 μm. Further, there may be some of the semiconductor devices4under the pad16exposed by the opening14a. Alternatively, there may be no active devices under the pad16exposed by the opening14a.

Referring toFIG. 2B, a metal cap18having a thickness of between 0.4 and 3 μm can be optionally formed on the pad16exposed by the opening14ain the passivation layer14to prevent the pad16from being oxidized or contaminated. For example, the metal cap18may comprise a barrier layer having a thickness of between 0.01 and 0.7 μm on the pad16, such as copper pad, exposed by the opening14a, and an aluminum-containing layer having a thickness of between 0.4 and 2 μm on the barrier layer, wherein the barrier layer may be made of titanium, a titanium-tungsten alloy, titanium nitride, tantalum, tantalum nitride, chromium or alloy of refractory metal, and the aluminum-containing layer may be an aluminum layer, an aluminum-copper alloy layer or an Al—Si—Cu alloy layer. Alternatively, the metal cap18may be an aluminum-containing layer having a thickness of between 0.4 and 2 μm directly on the pad16, such as copper pad, exposed by the opening14a, without the above-mentioned barrier layer between the aluminum-containing layer and the pad16, wherein the aluminum-containing layer may be an aluminum layer, an aluminum-copper alloy layer or an Al—Si—Cu alloy layer.

For example, the metal cap18may include a tantalum-containing layer, such as tantalum layer or tantalum-nitride layer, having a thickness of between 0.01 and 0.7 μm on the pad16, principally made of electroplated copper, exposed by the opening14a, and an aluminum-containing layer, such as aluminum layer or aluminum-alloy layer, having a thickness of between 0.4 and 2 μm on the tantalum-containing layer. Alternatively, the metal cap18may include a titanium-containing layer, such as titanium layer or titanium-tungsten-alloy layer, having a thickness of between 0.01 and 0.7 μm on the pad16, principally made of electroplated copper, exposed by the opening14a, and an aluminum-containing layer, such as aluminum layer or aluminum-alloy layer, having a thickness of between 0.4 and 2 μm on the tantalum-containing layer.

The semiconductor substrate2, the circuit structure6, the dielectric layer12, the passivation layer14and the pad16are described in the above paragraphs. Below, the scheme20between the semiconductor substrate2and the passivation layer14may be any one of the structures shown inFIGS. 2A and 2Bbetween the semiconductor substrate2and the passivation layer14; the scheme20represents the combination of the semiconductor devices4, the circuit structure6(including the metal layers8and the metal plugs10) and the dielectric layers12inFIG. 2AandFIG. 2B.

Referring toFIG. 3, in the present invention, a bonding pad22having a thickness of between 1 and 20 μm, and preferably of between 3 and 5 μm, can be formed on the pad16, such as aluminum pad or copper pad, exposed by the opening14ain the passivation layer14. The bonding pad22may be used to be bonded with a wire, such as gold wire. A method of forming the bonding pad22on the pad16exposed by the opening14acan be referred toFIGS. 4A-4GAfter a semiconductor wafer is formed with the bonding pad22, the semiconductor wafer can be separated into multiple individual semiconductor chips23, integrated circuit chips, by a laser cutting process or by a mechanical cutting process.

Referring toFIG. 4A, an adhesion/barrier layer24having a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, can be sputtered on the passivation layer14and on the pad16, such as aluminum pad or copper pad, exposed by the opening14a. The material of the adhesion/barrier layer24may include titanium, a titanium-tungsten alloy, titanium nitride, chromium, tantalum, tantalum nitride, an alloy of refractory metal, or a composite of the abovementioned materials. Alternatively, the adhesion/barrier layer24can be formed by an evaporation process.

For example, the adhesion/barrier layer24may be formed by sputtering a titanium layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, on the passivation layer14and on the pad16, principally made of aluminum, exposed by the opening14a. Alternatively, the adhesion/barrier layer24may be formed by sputtering a titanium-tungsten-alloy layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, on the passivation layer14and on the pad16, principally made of aluminum, exposed by the opening14a. Alternatively, the adhesion/barrier layer24may be formed by sputtering a titanium-nitride layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, on the passivation layer14and on the pad16, principally made of aluminum, exposed by the opening14a. Alternatively, the adhesion/barrier layer24may be formed by sputtering a chromium layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, on the passivation layer14and on the pad16, principally made of aluminum, exposed by the opening14a. Alternatively, the adhesion/barrier layer24may be formed by sputtering a tantalum-nitride layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, on the passivation layer14and on the pad16, principally made of aluminum, exposed by the opening14a. Alternatively, the adhesion/barrier layer24may be formed by sputtering a tantalum layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, on the passivation layer14and on the pad16, principally made of aluminum, exposed by the opening14a.

For example, the adhesion/barrier layer24may be formed by sputtering a titanium layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, on the passivation layer14and on the pad16, principally made of copper, exposed by the opening14a. Alternatively, the adhesion/barrier layer24may be formed by sputtering a titanium-tungsten-alloy layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, on the passivation layer14and on the pad16, principally made of copper, exposed by the opening14a. Alternatively, the adhesion/barrier layer24may be formed by sputtering a titanium-nitride layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, on the passivation layer14and on the pad16, principally made of copper, exposed by the opening14a. Alternatively, the adhesion/barrier layer24may be formed by sputtering a chromium layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, on the passivation layer14and on the pad16, principally made of copper, exposed by the opening14a. Alternatively, the adhesion/barrier layer24may be formed by sputtering a tantalum-nitride layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, on the passivation layer14and on the pad16, principally made of copper, exposed by the opening14a. Alternatively, the adhesion/barrier layer24may be formed by sputtering a tantalum layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, on the passivation layer14and on the pad16, principally made of copper, exposed by the opening14a.

Referring toFIG. 4B, a seed layer26having a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, can be sputtered on the adhesion/barrier layer24. Alternatively, the seed layer26can be formed by a vapor deposition method, an electroless plating method or a PVD (Physical Vapor Deposition) method. The seed layer26is beneficial to electroplating a metal layer thereon. Thus, the material of the seed layer26varies with the material of the electroplated metal layer formed on the seed layer26. When a gold layer is to be electroplated on the seed layer26, gold is a preferable material to the seed layer26. When a copper layer is to be electroplated on the seed layer26, copper is a preferable material to the seed layer26. When a palladium layer is to be electroplated on the seed layer26, palladium is a preferable material to the seed layer26.

For example, when the adhesion/barrier layer24is formed by sputtering a titanium layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a gold layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the titanium layer. When the adhesion/barrier layer24is formed by sputtering a titanium-tungsten-alloy layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a gold layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the titanium-tungsten-alloy layer. When the adhesion/barrier layer24is formed by sputtering a titanium-nitride layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a gold layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the titanium-nitride layer. When the adhesion/barrier layer24is formed by sputtering a chromium layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a gold layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the chromium layer. When the adhesion/barrier layer24is formed by sputtering a tantalum-nitride layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a gold layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the tantalum-nitride layer. When the adhesion/barrier layer24is formed by sputtering a tantalum layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a gold layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the tantalum layer.

For example, when the adhesion/barrier layer24is formed by sputtering a titanium layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a copper layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the titanium layer. When the adhesion/barrier layer24is formed by sputtering a titanium-tungsten-alloy layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a copper layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the titanium-tungsten-alloy layer. When the adhesion/barrier layer24is formed by sputtering a titanium-nitride layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a copper layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the titanium-nitride layer. When the adhesion/barrier layer24is formed by sputtering a chromium layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a copper layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the chromium layer. When the adhesion/barrier layer24is formed by sputtering a tantalum-nitride layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a copper layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the tantalum-nitride layer. When the adhesion/barrier layer24is formed by sputtering a tantalum layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a copper layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the tantalum layer.

For example, when the adhesion/barrier layer24is formed by sputtering a titanium layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a palladium layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the titanium layer. When the adhesion/barrier layer24is formed by sputtering a titanium-tungsten-alloy layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a palladium layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the titanium-tungsten-alloy layer. When the adhesion/barrier layer24is formed by sputtering a titanium-nitride layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a palladium layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the titanium-nitride layer. When the adhesion/barrier layer24is formed by sputtering a chromium layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a palladium layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the chromium layer. When the adhesion/barrier layer24is formed by sputtering a tantalum-nitride layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a palladium layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the tantalum-nitride layer. When the adhesion/barrier layer24is formed by sputtering a tantalum layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a palladium layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the tantalum layer.

Referring toFIG. 4C, a photoresist layer28, such as positive-type photoresist layer, having a thickness of between 1 and 25 μm, and preferably of between 3 and 10 μm, is spin-on coated on the seed layer26. Referring toFIG. 4D, the photoresist layer28is patterned with the processes of exposure, development, etc., to form an opening28ain the photoresist layer28exposing the seed layer26over the pad16. A 1× stepper or 1× contact aligner can be used to expose the photoresist layer28during the process of exposure.

For example, the photoresist layer28can be formed by spin-on coating a positive-type photosensitive polymer layer having a thickness of between 1 and 25 μm, and preferably of between 3 and 10 μm, on the seed layer26, then exposing the photosensitive polymer layer using a 1× stepper or 1× contact aligner with at least two of G-line having a wavelength ranging from 434 to 438 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the photosensitive polymer layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the photosensitive polymer layer, then developing the exposed polymer layer, and then removing the residual polymeric material or other contaminants form the seed layer26with an O2plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the photoresist layer28can be patterned with an opening28ain the photoresist layer28exposing the seed layer26over the pad16.

Referring toFIG. 4E, a metal layer30having a thickness of between 1 and 20 μm, and preferably of between 3 and 5 μm, can be electroplated and/or electroless plated over the seed layer26exposed by the opening28a. The material of the metal layer30may include gold, copper, nickel or palladium.

For example, the metal layer30may be formed by electroplating a gold layer with a thickness of between 1 and 20 μm, such as between 3 and 5 μm or between 1 and 4 μm, on the seed layer26, made of gold, exposed by the opening28a. Alternatively, the metal layer30may be formed by electroplating a palladium layer with a thickness of between 1 and 20 μm, such as between 3 and 5 μm or between 1 and 4 μm, on the seed layer26, made of palladium, exposed by the opening28a. Alternatively, the metal layer30may be formed by electroplating a copper layer with a thickness of between 1 and 10 μm on the seed layer26, made of copper, exposed by the opening28a, then electroplating a nickel layer with a thickness of between 1 and 5 μm on the copper layer in the opening28a, and then electroplating a gold layer with a thickness of between 1 and 5 μm on the nickel layer in the opening28a, wherein the thickness of the copper layer, the nickel layer and the gold layer is between 1 and 20 μm, and preferably of between 3 and 5 μm. Alternatively, the metal layer30may be formed by electroplating a copper layer with a thickness of between 1 and 13 μm on the seed layer26, made of copper, exposed by the opening28a, then electroplating a nickel layer with a thickness of between 1 and 5 μm on the copper layer in the opening28a, and then electroless plating a gold layer with a thickness of between 0.05 and 2 μm on the nickel layer in the opening28a, wherein the thickness of the copper layer, the nickel layer and the gold layer is between 1 and 20 μm, and preferably of between 3 and 5 μm. Alternatively, the metal layer30may be formed by electroplating a copper layer with a thickness of between 1 and 10 μm on the seed layer26, made of copper, exposed by the opening28a, then electroplating a nickel layer with a thickness of between 1 and 5 μm on the copper layer in the opening28a, and then electroplating a palladium layer with a thickness of between 1 and 5 μm on the nickel layer in the opening28a, wherein the thickness of the copper layer, the nickel layer and the palladium layer is between 1 and 20 μm, and preferably of between 3 and 5 μm. Alternatively, the metal layer30may be formed by electroplating a copper layer with a thickness of between 1 and 13 μm on the seed layer26, made of copper, exposed by the opening28a, then electroplating a nickel layer with a thickness of between 1 and 5 μm on the copper layer in the opening28a, and then electroless plating a palladium layer with a thickness of between 0.05 and 2 μm on the nickel layer in the opening28a, wherein the thickness of the copper layer, the nickel layer and the palladium layer is between 1 and 20 μm, and preferably of between 3 and 5 μm.

Referring toFIG. 4F, after the metal layer30is formed, most of the photoresist layer28can be removed using an organic solution with amide. However, some residuals from the photoresist layer28could remain on the metal layer30and on the seed layer26. Thereafter, the residuals can be removed from the metal layer30and from the seed layer26with a plasma, such as O2plasma or plasma containing fluorine of below 200 PPM and oxygen.

Referring toFIG. 4G, the seed layer26and the adhesion/barrier layer24not under the metal layer30are subsequently removed with a dry etching method or a wet etching method. As to the wet etching method, when the seed layer26is a gold layer, it can be etched with an iodine-containing solution, such as solution containing potassium iodide; when the seed layer26is a copper layer, it can be etched with a solution containing NH4OH; when the adhesion/barrier layer24is a titanium-tungsten-alloy layer, it can be etched with a solution containing hydrogen peroxide; when the adhesion/barrier layer24is a titanium layer, it can be etched with a solution containing hydrogen fluoride; when the adhesion/barrier layer24is a chromium layer, it can be etched with a solution containing potassium ferricyanide. As to the dry etching method, when the seed layer26is a gold layer, it can be removed with an ion milling process or with an Ar sputtering etching process; when the adhesion/barrier layer24is a titanium layer or a titanium-tungsten-alloy layer, it can be etched with a chlorine-containing plasma etching process or with an RIE process. Generally, the dry etching method to etch the seed layer26and the adhesion/barrier layer24not under the metal layer30may include a chemical plasma etching process, a sputtering etching process, such as argon sputter process, or a chemical vapor etching process.

Thereby, in the present invention, the bonding pad22can be formed on the pad16exposed by the opening14a. The bonding pad22can be formed of the adhesion/barrier layer24, the seed layer26on the adhesion/barrier layer24and the electroplated metal layer30on the seed layer26. The material of bonding pad22may comprise titanium, titanium-tungsten alloy, titanium nitride, chromium, tantalum nitride, tantalum, gold, copper, palladium or nickel. Based on the above teaching, the bonding pad22may include the following fashions.

After a semiconductor wafer is formed with the bonding pad22, the semiconductor wafer can be diced into a plurality of individual semiconductor chips23, IC (integrated circuit) chips, as shown inFIG. 3.

Referring toFIGS. 5A and 5B, in the present invention, a bonding pad22having a thickness of between 1 and 20 μm, and preferably of between 3 and 5 μm, can be formed on the metal cap18. The metal cap18may comprise a tantalum-containing layer, such as tantalum layer or tantalum-nitride layer, having a thickness of between 0.01 and 0.7 μm on the pad16, such as copper pad, exposed by the opening14a, and an aluminum-containing layer, such as aluminum layer, aluminum-copper-alloy layer or Al—Si—Cu alloy layer, having a thickness of between 0.4 and 2 μm on the tantalum-containing layer. The bonding pad22may be used to be bonded with a wire, such as gold wire. The bonding pad22may be formed on the entire upper surface of the metal cap18and on the upper surface of the passivation layer14near the metal cap18, as shown inFIG. 5A. Alternatively, the bonding pad22may be formed on a portion of a top surface of the metal cap18, as shown inFIG. 5B. A method of forming the bonding pad22on the metal cap18can be referred toFIGS. 6A-6G.FIGS. 6A-6Gillustrate a process for forming the bonding pad22shown inFIG. 5Aon the metal cap18. Alternatively, the illustrations ofFIGS. 6A-6Gcan be applied to a process for forming the bonding pad22shown inFIG. 5Bon the metal cap18. After a semiconductor wafer is formed with the bonding pad22, the semiconductor wafer can be separated into multiple individual semiconductor chips31, integrated circuit chips, by a laser cutting process or by a mechanical cutting process.

Referring toFIG. 6A, an adhesion/barrier layer24having a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, can be sputtered on the passivation layer14and on the metal cap18, wherein the metal cap18may comprise a tantalum-containing layer, such as tantalum layer or tantalum-nitride layer, having a thickness of between 0.01 and 0.7 μm on the pad16, such as copper pad, exposed by the opening14a, and an aluminum-containing layer, such as aluminum layer, aluminum-copper-alloy layer or Al—Si—Cu alloy layer, having a thickness of between 0.4 and 2 μm on the tantalum-containing layer. The material of the adhesion/barrier layer24may include titanium, a titanium-tungsten alloy, titanium nitride, chromium, tantalum, tantalum nitride, an alloy of refractory metal, or a composite of the abovementioned materials. Alternatively, the adhesion/barrier layer24can be formed by an evaporation process.

For example, the adhesion/barrier layer24may be formed by sputtering a titanium layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, on the passivation layer14and on the aluminum-containing layer of the metal cap18. Alternatively, the adhesion/barrier layer24may be formed by sputtering a titanium-tungsten-alloy layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, on the passivation layer14and on the aluminum-containing layer of the metal cap18. Alternatively, the adhesion/barrier layer24may be formed by sputtering a titanium-nitride layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, on the passivation layer14and on the aluminum-containing layer of the metal cap18. Alternatively, the adhesion/barrier layer24may be formed by sputtering a chromium layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, on the passivation layer14and on the aluminum-containing layer of the metal cap18. Alternatively, the adhesion/barrier layer24may be formed by sputtering a tantalum-nitride layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, on the passivation layer14and on the aluminum-containing layer of the metal cap18. Alternatively, the adhesion/barrier layer24may be formed by sputtering a tantalum layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, on the passivation layer14and on the aluminum-containing layer of the metal cap18. Alternatively, the adhesion/barrier layer24may be formed by sputtering a tantalum layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, on the passivation layer14and on the aluminum-containing layer of the metal cap18.

Referring toFIG. 6B, a seed layer26having a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, can be sputtered on the adhesion/barrier layer24. Alternatively, the seed layer26can be formed by a vapor deposition method, an electroless plating method or a PVD (Physical Vapor Deposition) method. The seed layer26is beneficial to electroplating a metal layer thereon. Thus, the material of the seed layer26varies with the material of the electroplated metal layer formed on the seed layer26. When a gold layer is to be electroplated on the seed layer26, gold is a preferable material to the seed layer26. When a copper layer is to be electroplated on the seed layer26, copper is a preferable material to the seed layer26. When a palladium layer is to be electroplated on the seed layer26, palladium is a preferable material to the seed layer26.

For example, when the adhesion/barrier layer24is formed by sputtering a titanium layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a gold layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the titanium layer. When the adhesion/barrier layer24is formed by sputtering a titanium-tungsten-alloy layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a gold layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the titanium-tungsten-alloy layer. When the adhesion/barrier layer24is formed by sputtering a titanium-nitride layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a gold layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the titanium-nitride layer. When the adhesion/barrier layer24is formed by sputtering a chromium layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a gold layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the chromium layer. When the adhesion/barrier layer24is formed by sputtering a tantalum-nitride layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a gold layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the tantalum-nitride layer. When the adhesion/barrier layer24is formed by sputtering a tantalum layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a gold layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the tantalum layer.

For example, when the adhesion/barrier layer24is formed by sputtering a titanium layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a copper layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the titanium layer. When the adhesion/barrier layer24is formed by sputtering a titanium-tungsten-alloy layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a copper layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the titanium-tungsten-alloy layer. When the adhesion/barrier layer24is formed by sputtering a titanium-nitride layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a copper layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the titanium-nitride layer. When the adhesion/barrier layer24is formed by sputtering a chromium layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a copper layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the chromium layer. When the adhesion/barrier layer24is formed by sputtering a tantalum-nitride layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a copper layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the tantalum-nitride layer. When the adhesion/barrier layer24is formed by sputtering a tantalum layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a copper layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the tantalum layer.

For example, when the adhesion/barrier layer24is formed by sputtering a titanium layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a palladium layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the titanium layer. When the adhesion/barrier layer24is formed by sputtering a titanium-tungsten-alloy layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a palladium layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the titanium-tungsten-alloy layer. When the adhesion/barrier layer24is formed by sputtering a titanium-nitride layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a palladium layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the titanium-nitride layer. When the adhesion/barrier layer24is formed by sputtering a chromium layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a palladium layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the chromium layer. When the adhesion/barrier layer24is formed by sputtering a tantalum-nitride layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a palladium layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the tantalum-nitride layer. When the adhesion/barrier layer24is formed by sputtering a tantalum layer with a thickness of between 0.01 and 0.7 μm, and preferably of between 0.03 and 0.7 μm, the seed layer26can be formed by sputtering a palladium layer with a thickness of between 0.03 and 1 μm, and preferably of between 0.03 and 0.7 μm, on the tantalum layer.

Referring toFIG. 6C, a photoresist layer28, such as positive-type photoresist layer, having a thickness of between 1 and 25 μm, and preferably of between 3 and 10 μm, is spin-on coated on the seed layer26. Referring toFIG. 6D, the photoresist layer28is patterned with the processes of exposure, development, etc., to form an opening28ain the photoresist layer28exposing the seed layer26over the pad16. A 1× stepper or 1× contact aligner can be used to expose the photoresist layer28during the process of exposure.

For example, the photoresist layer28can be formed by spin-on coating a positive-type photosensitive polymer layer having a thickness of between 1 and 25 μm, and preferably of between 3 and 10 μm, on the seed layer26, then exposing the photosensitive polymer layer using a 1× stepper or 1× contact aligner with at least two of G-line having a wavelength ranging from 434 to 438 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the photosensitive polymer layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the photosensitive polymer layer, then developing the exposed polymer layer, and then removing the residual polymeric material or other contaminants form the seed layer26with an O2plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the photoresist layer28can be patterned with an opening28ain the photoresist layer28exposing the seed layer26over the pad16.

Referring toFIG. 6E, a metal layer30having a thickness of between 1 and 20 μm, and preferably of between 3 and 5 μm, can be electroplated and/or electroless plated over the seed layer26exposed by the opening28a. The material of the metal layer30may include gold, copper, nickel or palladium. The specification of the metal layer30shown inFIG. 6Ecan be referred to as the metal layer30illustrated inFIG. 4E. The process of forming the metal layer30shown inFIG. 6Ecan be referred to as the process of forming the metal layer30illustrated inFIG. 4E.

Referring toFIG. 6F, after the metal layer30is formed, most of the photoresist layer28can be removed using an organic solution with amide. However, some residuals from the photoresist layer28could remain on the metal layer30and on the seed layer26. Thereafter, the residuals can be removed from the metal layer30and from the seed layer26with a plasma, such as O2plasma or plasma containing fluorine of below 200 PPM and oxygen.

Referring toFIG. 6G, the seed layer26and the adhesion/barrier layer24not under the metal layer30are subsequently removed with a dry etching method or a wet etching method. The process of removing the seed layer26and the adhesion/barrier layer24not under the metal layer30, as shown inFIG. 6G, can be referred to as the process of removing the seed layer26and the adhesion/barrier layer24not under the metal layer30, as illustrated inFIG. 4G.

Thereby, in the present invention, the bonding pad22can be formed on the aluminum-containing layer of the metal cap18. The bonding pad22can be formed of the adhesion/barrier layer24, the seed layer26on the adhesion/barrier layer24and the electroplated metal layer30on the seed layer26. The material of bonding pad22may comprise titanium, titanium-tungsten alloy, titanium nitride, chromium, tantalum nitride, tantalum, gold, copper, palladium or nickel. Based on the above teaching, the bonding pad22may include the following fashions.

After a semiconductor wafer is formed with the bonding pad22, the semiconductor wafer can be diced into a plurality of individual semiconductor chips31, IC (integrated circuit) chips, as shown inFIG. 5A.

Referring toFIGS. 7A and 7B, in the present invention, a metal trace32can be formed on a polymer layer34, and the metal trace32is connected to the pad16through an opening34ain the polymer layer34, wherein the polymer layer34is formed on the passivation layer14, and the opening34a, exposing the pad16, is formed in the polymer layer34by a photolithography process, for example. The pad16may include a center portion exposed by an opening34aand a peripheral portion covered with the polymer layer34, as shown inFIG. 7A. Alternatively, the opening34amay expose the entire upper surface of the pad16exposed by the opening14ain the passivation layer14and further may expose the upper surface of the passivation layer14near the pad16, as shown inFIG. 7B.

The material of the polymer layer34may include polyimide (PI), benzocyclobutane (BCB), polyurethane, epoxy resin, a parylene-based polymer, a solder-mask material, an elastomer, or a porous dielectric material. The polymer layer34having a thickness of between 3 and 25 μm can be formed by a process including a spin-on coating process, a lamination process or a screen-printing process.

For example, the polymer layer34can be formed by spin-on coating a negative-type photosensitive polyimide layer, containing ester-typer precursor, having a thickness of between 6 and 50 μm on the passivation layer14, then baking the spin-on coated polyimide layer, then exposing the baked polyimide layer using a 1× stepper or 1× contact aligner with at least two of G-line having a wavelength ranging from 434 to 438 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the baked polyimide layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the baked polyimide layer, then developing the exposed polyimide layer, an opening in the developed polyimide layer exposing the pad16, then curing or heating the developed polyimide layer at a peak temperature of between 250 and 400° C. for a time of between 10 and 200 minutes in a nitrogen ambient or in an oxygen-free ambient, the cured polyimide layer having a thickness of between 3 and 25 μm, and then removing the residual polymeric material or other contaminants form the upper surface of the pad16exposed by the opening in the cured polyimide layer with an O2plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the polyimide layer can be patterned with at least one opening in the polyimide layer exposing at least one pad16of the circuit structure6.

The metal trace32comprises at least one bonding pad for being bonded with a wire, such as gold wire. From a top perspective view, the position of the bonding pad may be different from that of the pad16, to which the metal trace32is connected. For example, the metal trace32may comprise a first bonding pad32aand a second bonding pad32b. From a top perspective view, the position of the first bonding pad32ais the same as that of the pad16, to which the metal trace32is connected, but the position of the second bonding pad32bis different from that of the pad16, to which the metal trace32is connected. One of the first and second bonding pads32aand32bmay have a gold wire ball bonded thereto using a wirebonding process. Alternatively, both of the first and second bonding pads32aand32bmay have gold wires ball bonded thereto, respectively, using a wirebonding process.

After a semiconductor wafer is formed with the metal trace32, the semiconductor wafer can be diced into a plurality of individual semiconductor chips36, IC (integrated circuit) chips, as shown inFIGS. 7A and 7B.

Referring toFIGS. 7C and 7D, after the metal trace32shown inFIGS. 7A and 7Bis formed, a polymer layer38may be formed on the metal trace32and on the polymer layer34, and at least one opening38ais formed in the polymer layer38by a photolithography process, for example, to expose a bonding pad32aand/or32bof the metal trace32for being bonded with a wire, such as gold wire. For example, the metal trace32may include a first bonding pad32aexposed by the opening38aand a second bonding pad32bexposed by the opening38a. From a top perspective view, the position of the first bonding pad32aexposed by the opening38ais the same as that of the pad16, to which the metal trace32is connected, but the position of the second bonding pad32bexposed by the opening38ais different from that of the pad16, to which the metal trace32is connected. One of the first and second bonding pads32aand32bmay have a gold wire ball bonded thereto using a wirebonding process. Alternatively, both of the first and second bonding pads32aand32bmay have gold wires ball bonded thereto, respectively, using a wirebonding process.

The material of the polymer layer38may be polyimide (PI), benzocyclobutane (BCB), polyurethane, epoxy resin, a parylene-based polymer, a solder-mask material, an elastomer, or a porous dielectric material. The polymer layer38having a thickness of between 3 and 25 μm can be formed by a process including a spin-on coating process, a lamination process or a screen-printing process.

For example, the polymer layer38can be formed by spin-on coating a negative-type photosensitive polyimide layer, containing ester-typer precursor, having a thickness of between 6 and 50 μm on the metal trace32and on the polymer layer34, then baking the spin-on coated polyimide layer, then exposing the baked polyimide layer using a 1× stepper or 1× contact aligner with at least two of G-line having a wavelength ranging from 434 to 438 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the baked polyimide layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the baked polyimide layer, then developing the exposed polyimide layer, two openings in the developed polyimide layer exposing the gold layer of the bonding pads32aand32bor the palladium layer of the bonding pads32aand32b, then curing or heating the developed polyimide layer at a peak temperature of between 250 and 400° C. for a time of between 10 and 200 minutes in a nitrogen ambient or in an oxygen-free ambient, the cured polyimide layer having a thickness of between 3 and 25 μm, and then removing the residual polymeric material or other contaminants form the upper surface of the metal trace32exposed by the opening in the cured polyimide layer with an O2plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the polyimide layer can be patterned with two openings in the polyimide layer exposing the gold layer of the bonding pads32aand32bor the palladium layer of the bonding pads32aand32b.

After a semiconductor wafer is formed with the polymer layer38on the metal trace32, the semiconductor wafer can be diced into a plurality of individual semiconductor chips40, IC (integrated circuit) chips, as shown inFIGS. 7C and 7D.

Referring toFIG. 7E, in the present invention, the step of forming the polymer layer34on the passivation layer14, as shown inFIGS. 7A and 7B, can be omitted, that is, the metal trace32can be directly formed on the passivation layer14and on the pad16exposed by the opening14a.

The metal trace32comprises at least one bonding pad for being bonded with a wire, such as gold wire. From a top perspective view, the position of the bonding pad may be different from that of the pad16, to which the metal trace32is connected. For example, the metal trace32may comprise a first bonding pad32aand a second bonding pad32b. From a top perspective view, the position of the first bonding pad32ais the same as that of the pad16, to which the metal trace32is connected, but the position of the second bonding pad32bis different from that of the pad16, to which the metal trace32is connected. One of the first and second bonding pads32aand32bmay have a gold wire ball bonded thereto using a wirebonding process. Alternatively, both of the first and second bonding pads32aand32bmay have gold wires ball bonded thereto, respectively, using a wirebonding process.

After a semiconductor wafer is formed with the metal trace32, the semiconductor wafer can be diced into a plurality of individual semiconductor chips42, IC (integrated circuit) chips, as shown inFIG. 7E.

Referring toFIG. 7F, after the metal trace32shown inFIG. 7Eis formed, a polymer layer38may be formed on the metal trace32and on the passivation layer14, and at least one opening38ais formed in the polymer layer38by a photolithography process, for example, to expose a bonding pad32aand/or32bof the metal trace32for being bonded with a wire, such as gold wire. For example, the metal trace32may include a first bonding pad32aexposed by the opening38aand a second bonding pad32bexposed by the opening38a. From a top perspective view, the position of the first bonding pad32aexposed by the opening38ais the same as that of the pad16, to which the metal trace32is connected, but the position of the second bonding pad32bexposed by the opening38ais different from that of the pad16, to which the metal trace32is connected. One of the first and second bonding pads32aand32bmay have a gold wire ball bonded thereto using a wirebonding process. Alternatively, both of the first and second bonding pads32aand32bmay have gold wires ball bonded thereto, respectively, using a wirebonding process.

The material of the polymer layer38may include polyimide (PI), benzocyclobutane (BCB), polyurethane, epoxy resin, a parylene-based polymer, a solder-mask material, an elastomer, or a porous dielectric material. The polymer layer38having a thickness of between 3 and 25 μm can be formed by a process including a spin-on coating process, a lamination process or a screen-printing process.

For example, the polymer layer38can be formed by spin-on coating a negative-type photosensitive polyimide layer, containing ester-typer precursor, having a thickness of between 6 and 50 μm on the metal trace32and on the passivation layer14, then baking the spin-on coated polyimide layer, then exposing the baked polyimide layer using a 1× stepper or 1× contact aligner with at least two of G-line having a wavelength ranging from 434 to 438 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the baked polyimide layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the baked polyimide layer, then developing the exposed polyimide layer, two openings in the developed polyimide layer exposing the gold layer of the bonding pads32aand32bor the palladium layer of the bonding pads32aand32b, then curing or heating the developed polyimide layer at a peak temperature of between 250 and 400° C. for a time of between 10 and 200 minutes in a nitrogen ambient or in an oxygen-free ambient, the cured polyimide layer having a thickness of between 3 and 25 μm, and then removing the residual polymeric material or other contaminants from the upper surface of the metal trace32exposed by the opening in the cured polyimide layer with an O2plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the polyimide layer can be patterned with two openings in the polyimide layer exposing the gold layer of the bonding pads32aand32bor the palladium layer of the bonding pads32aand32b.

After a semiconductor wafer is formed with the polymer layer38on the metal trace32, the semiconductor wafer can be diced into a plurality of individual semiconductor chips44, IC (integrated circuit) chips, as shown inFIG. 7F.

Referring toFIG. 8A, in the present invention, a metal trace32can be formed on a polymer layer34, and the metal trace32is connected to the aluminum-containing layer of the metal cap18through an opening34ain the polymer layer34, wherein the polymer layer34is formed on the passivation layer14, and the opening34a, exposing the aluminum-containing layer of the metal cap18, is formed in the polymer layer34by a photolithography process, for example. The metal cap18may comprise a tantalum-containing layer, such as tantalum layer or tantalum-nitride layer, having a thickness of between 0.01 and 0.7 μm on the pad16, such as copper pad, exposed by the opening14a, and an aluminum-containing layer, such as aluminum layer, aluminum-copper-alloy layer or Al—Si—Cu alloy layer, having a thickness of between 0.4 and 2 μm on the tantalum-containing layer.

The material of the polymer layer34may include polyimide (PI), benzocyclobutane (BCB), polyurethane, epoxy resin, a parylene-based polymer, a solder-mask material, an elastomer, or a porous dielectric material. The polymer layer34having a thickness of between 3 and 25 μm can be formed by a process including a spin-on coating process, a lamination process or a screen-printing process.

For example, the polymer layer34can be formed by spin-on coating a negative-type photosensitive polyimide layer, containing ester-typer precursor, having a thickness of between 6 and 50 μm on the passivation layer14and on the aluminum-containing layer of the metal cap18, then baking the spin-on coated polyimide layer, then exposing the baked polyimide layer using a 1× stepper or 1× contact aligner with at least two of G-line having a wavelength ranging from 434 to 438 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the baked polyimide layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the baked polyimide layer, then developing the exposed polyimide layer, an opening in the developed polyimide layer exposing the aluminum-containing layer of the metal cap18, then curing or heating the developed polyimide layer at a peak temperature of between 250 and 400° C. for a time of between 10 and 200 minutes in a nitrogen ambient or in an oxygen-free ambient, the cured polyimide layer having a thickness of between 3 and 25 μm, and then removing the residual polymeric material or other contaminants from the upper surface of the aluminum-containing layer of the metal cap18exposed by the opening in the cured polyimide layer with an O2plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the polyimide layer can be patterned with an opening in the polyimide layer exposing the aluminum-containing layer of the metal cap18.

The metal trace32comprises at least one bonding pad for being bonded with a wire, such as gold wire. From a top perspective view, the position of the bonding pad may be different from that of the metal cap18, to which the metal trace32is connected. For example, the metal trace32may comprise a first bonding pad32aand a second bonding pad32b. From a top perspective view, the position of the first bonding pad32ais the same as that of the metal cap18, to which the metal trace32is connected, but the position of the second bonding pad32bis different from that of the metal cap18, to which the metal trace32is connected. One of the first and second bonding pads32aand32bmay have a gold wire ball bonded thereto using a wirebonding process. Alternatively, both of the first and second bonding pads32aand32bmay have gold wires ball bonded thereto, respectively, using a wirebonding process.

After a semiconductor wafer is formed with the metal trace32, the semiconductor wafer can be diced into a plurality of individual semiconductor chips46, IC (integrated circuit) chips, as shown inFIG. 8A.

Referring toFIG. 8B, after the metal trace32shown inFIG. 8Ais formed, a polymer layer38may be formed on the metal trace32and on the polymer layer34, and at least one opening38ais formed in the polymer layer38by a photolithography process, for example, to expose a bonding pad32aand/or32bof the metal trace32for being bonded with a wire, such as gold wire. For example, the metal trace32may include a first bonding pad32aexposed by the opening38aand a second bonding pad32bexposed by the opening38a. From a top perspective view, the position of the first bonding pad32aexposed by the opening38ais the same as that of the metal cap18, to which the metal trace32is connected, but the position of the second bonding pad32bexposed by the opening38ais different from that of the metal cap18, to which the metal trace32is connected. One of the first and second bonding pads32aand32bmay have a gold wire ball bonded thereto using a wirebonding process. Alternatively, both of the first and second bonding pads32aand32bmay have gold wires ball bonded thereto, respectively, using a wirebonding process. The specification of the polymer layer38shown inFIG. 8Bcan be referred to as the polymer layer38illustrated inFIGS. 7C and 7D. The process of forming the polymer layer38shown inFIG. 8Bcan be referred to as the process of forming the polymer layer38illustrated inFIGS. 7C and 7D.

After a semiconductor wafer is formed with the polymer layer38on the metal trace32, the semiconductor wafer can be diced into a plurality of individual semiconductor chips48, IC (integrated circuit) chips, as shown inFIG. 8B.

Referring toFIG. 8C, in the present invention, the step of forming the polymer layer34on the passivation layer14, as shown inFIG. 8A, can be omitted, that is, the metal trace32can be directly formed on the passivation layer14and on the aluminum-containing layer of the metal cap18.

The metal trace32comprises at least one bonding pad for being bonded with a wire, such as gold wire. From a top perspective view, the position of the bonding pad may be different from that of the metal cap18, to which the metal trace32is connected. For example, the metal trace32may comprise a first bonding pad32aand a second bonding pad32b. From a top perspective view, the position of the first bonding pad32ais the same as that of the metal cap18, to which the metal trace32is connected, but the position of the second bonding pad32bis different from that of the metal cap18, to which the metal trace32is connected. One of the first and second bonding pads32aand32bmay have a gold wire ball bonded thereto using a wirebonding process. Alternatively, both of the first and second bonding pads32aand32bmay have gold wires ball bonded thereto, respectively, using a wirebonding process.

After a semiconductor wafer is formed with the metal trace32, the semiconductor wafer can be diced into a plurality of individual semiconductor chips50, IC (integrated circuit) chips, as shown inFIG. 8C.

Referring toFIG. 8D, after the metal trace32shown inFIG. 8Cis formed, a polymer layer38may be formed on the metal trace32and on the passivation layer14, and at least one opening38ais formed in the polymer layer38by a photolithography process, for example, to expose a bonding pad32aand/or32bof the metal trace32for being bonded with a wire, such as gold wire. For example, the metal trace32may include a first bonding pad32aexposed by the opening38aand a second bonding pad32bexposed by the opening38a. From a top perspective view, the position of the first bonding pad32aexposed by the opening38ais the same as that of the metal cap18, to which the metal trace32is connected, but the position of the second bonding pad32bexposed by the opening38ais different from that of the metal cap18, to which the metal trace32is connected. One of the first and second bonding pads32aand32bmay have a gold wire ball bonded thereto using a wirebonding process. Alternatively, both of the first and second bonding pads32aand32bmay have gold wires ball bonded thereto, respectively, using a wirebonding process. The specification of the polymer layer38shown inFIG. 8Dcan be referred to as the polymer layer38illustrated inFIG. 7F. The process of forming the polymer layer38shown inFIG. 8Dcan be referred to as the process of forming the polymer layer38illustrated inFIG. 7F.

After a semiconductor wafer is formed with the polymer layer38on the metal trace32, the semiconductor wafer can be diced into a plurality of individual semiconductor chips52, IC (integrated circuit) chips, as shown inFIG. 8E.

Referring toFIG. 9A, a glue material54is first formed on multiple regions of a substrate56by a dispensing process to form multiple glue portions54on the substrate56. Next, multiple semiconductor chips23are respectively mounted onto the glue portions54to be adhered to the substrate56, and then the glue material54is baked at a temperature of between 100 and 200° C. In another word, the semiconductor substrate2of the semiconductor chip23can be adhered to the substrate56using the glue material54.

For example, the glue material54may be polyimide having a thickness of between 1 and 50 μm to adhere the semiconductor chips23to the substrate56. Alternatively, the glue material54may be epoxy resin having a thickness of between 1 and 50 μm to adhere the semiconductor chips23to the substrate56. Alternatively, the glue material54may be silver-filed epoxy having a thickness of between 1 and 50 μm to adhere the semiconductor chips23to the substrate56.

The substrate56may be a ball grid array (BGA) substrate with a thickness of between 200 and 2,000 μm. Alternatively, the substrate56may be a glass fiber reinforced epoxy based substrate with a thickness of between 200 and 2,000 μm. Alternatively, the substrate56may be a glass substrate with a thickness of between 200 and 2,000 μm. Alternatively, the substrate56may be a silicon substrate with a thickness of between 200 and 2,000 μm. Alternatively, the substrate56may be a ceramic substrate with a thickness of between 200 and 2,000 μm. Alternatively, the substrate56may be an organic substrate with a thickness of between 200 and 2,000 μm. Alternatively, the substrate56may be a metal substrate, comprising aluminum, with a thickness of between 200 and 2,000 μm. Alternatively, the substrate56may be a metal substrate, comprising copper, with a thickness of between 200 and 2,000 μm.

Referring toFIG. 9B, via a wire-bonding process, one end of a wire58can be ball bonded to a bonding pad22of the semiconductor chip23, and the other end of the wire58can be wedge bonded to a contact point57of a metal trace of the substrate56, wherein the wire58has a diameter of between 20 and 50 micrometers, and the wire58is made of gold, typically called a gold wire. For example, one end of the wire58can be ball bonded to a gold layer of the bonding pad22of the semiconductor chip23, and the other end of the wire58can be wedge bonded to the contact point57of the metal trace of the substrate56. Alternatively, one end of the wire58can be ball bonded to a palladium layer of the bonding pad22of the semiconductor chip23, and the other end of the wire58can be wedge bonded to the contact point57of the metal trace of the substrate56. Thereby, the bonding pad22of the semiconductor chip23is electrically connected to the metal trace of the substrate56.

Referring toFIG. 9C, a polymer material60having a thickness t5of between 250 and 1,000 μm is formed on the substrate56, covering the semiconductor chips23and the wires58. The polymer material60can be formed by molding benzocyclobutane (BCB), polyimide (PI) or an epoxy-based material, by dispensing benzocyclobutane (BCB), polyimide (PI) or an epoxy-based material, by coating benzocyclobutane (BCB), polyimide (PI) or an epoxy-based material, by printing benzocyclobutane (BCB), polyimide (PI) or an epoxy-based material, or by laminating benzocyclobutane (BCB), polyimide (PI) or an epoxy-based material.

For example, the polymer material60can be formed by molding an epoxy-based material having a thickness t5of between 250 and 1,000 μm on the substrate56, covering the semiconductor chips23and the wires58. Alternatively, the polymer material60can be formed by molding polyimide or benzocyclobutane having a thickness t5of between 250 and 1,000 μm on the substrate56, covering the semiconductor chips23and the wires58. Alternatively, the polymer material60can be formed by dispensing polyimide or benzocyclobutane having a thickness t5of between 250 and 1,000 μm on the substrate56, covering the semiconductor chips23and the wires58.

Referring toFIG. 9D, a lead-free solder is formed on a contact point64of the substrate56via a ball planting process or a screen printing process. Next, via a reflowing process, a lead-free solder ball62having a diameter d of between 0.25 and 1.2 mm is formed on the substrate56by heating the lead-free solder to a temperature of between 200 and 300° C., and preferably between 230 and 260° C., for a time of between 5 and 90 seconds, and preferably of between 20 and 40 seconds. The material of the lead-free solder ball62may be a tin-lead alloy, a tin-silver alloy or a tin-silver-copper alloy. The lead-free solder ball62is bonded on the contact point64of the metal trace and connected to the contact point57, for being electrically connected to the wire58.

Referring toFIG. 9E, after the lead-free solder ball62is formed, the substrate56and the polymer material60can be cutted into a plurality of chip packages66using a mechanical cutting process or using a laser cutting process. The substrate56comprises a top surface and a bottom surface opposite to the top surface. The glue material54and the polymer material60are on the top surface, and the lead-free solder ball62is on the bottom surface.

Referring toFIGS. 10A-10L, the semiconductor chip23can be replaced by the above-mentioned semiconductor chips31shown inFIGS. 5A and 5B, the semiconductor chips36shown inFIGS. 7A and 7B, the semiconductor chips40shown inFIGS. 7C and 7D, the semiconductor chip42shown inFIG. 7E, the semiconductor chip44shown inFIG. 7F, the semiconductor chip46shown inFIG. 8A, the semiconductor chip48shown inFIG. 8B, the semiconductor chip50shown inFIG. 8Cand the semiconductor chip52shown inFIG. 8D. That is, the semiconductor chip31,36,40,42,44,46,48,50or52can be adhered to the substrate56using the glue material54, which can be referred to the above description concerningFIG. 9A, followed by the steps as referred to inFIGS. 9B-9D, followed by cutting the substrate56and the polymer material60into a plurality of chip packages68,70,72,74,76,78,80,82or84using a mechanical cutting process or using a laser cutting process.

InFIGS. 10C-10D, from a top perspective view, the position of the metal trace32bonded with the wire58may be different from that of the pad16, to which the metal trace32is connected, or from that of the metal cap18, to which the metal trace32is connected. For example, the metal trace32of the chip package68,70,72,74or76can be bonded with the wire58, and from a top perspective view, the position of the metal trace32bonded with the wire58is different from that of the pad16, to which the metal trace32is connected. Alternatively, the metal trace32of the chip package78,80,82or84can be bonded with the wire58, and from a top perspective view, the position of the metal trace32bonded with the wire58is different from that of the metal cap18, to which the metal trace32is connected.

For example, the metal trace32of the chip package68,70,72,74or76can be bonded with the wire58, and from a top perspective view, the position of the metal trace32bonded with the wire58is the same as that of the pad16, to which the metal trace32is connected. Alternatively, the metal trace32of the chip package78,80,82or84can be bonded with the wire58, and from a top perspective view, the position of the metal trace32bonded with the wire58is the same as that of the metal cap18, to which the metal trace32is connected.

For example, two wires58can be bonded to one of the metal traces32of the chip package68,70,72,74or76. From a top perspective view, one of the two wires58is bonded to a first bonding pad32aof the metal trace32, the position of which is the same as that of the pad16, and the other one of the two wires58is bonded to a second bonding pad32bof the metal trace32, the position of which is different from that of the pad16. The first bonding pad32ais connected to the second bonding pad32b.

For example, two wires58can be bonded to one of the metal traces32of the chip package78,80,82or84. From a top perspective view, one of the two wires58is bonded to a first bonding pad32aof the metal trace32, the position of which is the same as that of the metal cap18, and the other one of the two wires58is bonded to a second bonding pad32bof the metal trace32, the position of which is different from that of the metal cap18. The first bonding pad32ais connected to the second bonding pad32b.

Referring toFIG. 11A, the lead frame86comprises multiple die pads86aand multiple leads86bsurrounding the die pads86a. A glue material54is first formed on the die pads86aof the lead frame86by dispensing multiple glue portions54on the die pads86a. Next, multiple semiconductor chips23are respectively mounted onto the glue portions54to be adhered to the die pads86aof the lead frame86, and then the glue material54is baked at a temperature of between 100 and 200° C. In another word, the semiconductor substrate2of the semiconductor chip23can be adhered to the die pad86aof the lead frame86using the glue material54. The lead frame86has a thickness t6of between 100 and 2,000 μm, and the material of the lead frame86may be copper or copper alloy.

For example, the glue material54may be polyimide having a thickness of between 1 and 50 μm to adhere the semiconductor chips23to the die pads86aof the lead frame86. Alternatively, the glue material54may be epoxy resin having a thickness of between 1 and 50 μm to adhere the semiconductor chips23to the die pads86aof the lead frame86. Alternatively, the glue material54may be silver-filed epoxy having a thickness of between 1 and 50 μm to adhere the semiconductor chips23to the die pads86aof the lead frame86.

Referring toFIG. 11B, via a wire-bonding process, one end of a wire58can be ball bonded to a bonding pad22of the semiconductor chip23, and the other end of the wire58can be wedge bonded to one of the leads86bof the lead frame86, wherein the wire58has a diameter of between 20 and 50 micrometers, and the wire58is made of gold, typically called a gold wire. For example, one end of the wire58can be ball bonded to a gold layer of the bonding pad22of the semiconductor chip23, and the other end of the wire58can be wedge bonded to one of the leads86bof the lead frame86. Alternatively, one end of the wire58can be ball bonded to a palladium layer of the bonding pad22of the semiconductor chip23, and the other end of the wire58can be wedge bonded to one of the leads86bof the lead frame86. Thereby, the bonding pad22of the semiconductor chip23is electrically connected to one of the leads86bof the lead frame86.

Referring toFIG. 11C, a polymer material88, such as benzocyclobutane (BCB), polyimide (PI) or an epoxy-based material, having a thickness t7of between 250 and 1,000 μm is next formed using a molding process, enclosing the die pads86a, a portion of the leads86bclose to the die pads86a, the semiconductor chips23and the wires58.

For example, the polymer material88can be formed by molding an epoxy-based material having a thickness t7of between 250 and 1,000 μm enclosing the die pads86a, a portion of the leads86bclose to the die pads86a, the semiconductor chips23and the wires58, the semiconductor chips23and the wires58. Alternatively, the polymer material88can be formed by molding polyimide or benzocyclobutane having a thickness t7of between 250 and 1,000 μm enclosing the die pads86a, a portion of the leads86bclose to the die pads86a, the semiconductor chips23and the wires58.

Referring toFIG. 11D, after the polymer material88is formed, the steps of dejunking the residual of the polymer material88, trimming dam bars and cutting and punching the leads86bcan be performed, such that the leads86bhave a designed shape and multiple lead-frame chip packages90are singularized.

The chip package90may have various types, such as small outline package (SOP), thin small outline package (TSOP), dual in-line package (DIP), ceramic dual in-line package (CDIP), glass ceramic dual in-line package (CERDIP), CERQUAD, ceramic leaded chip carrier (CLCC), quad flat package (QFP), plastic leaded chip carrier (PLCC), small outline J-lead (SOJ), small outline integrated circuit (SOIC) or zig-zag in-line package (ZIP).

Referring toFIGS. 12A-12L, the semiconductor chip23can be replaced by the above-mentioned semiconductor chips31shown inFIGS. 5A and 5B, the semiconductor chips36shown inFIGS. 7A and 7B, the semiconductor chips40shown inFIGS. 7C and 7D, the semiconductor chip42shown inFIG. 7E, the semiconductor chip44shown inFIG. 7F, the semiconductor chip46shown inFIG. 8A, the semiconductor chip48shown inFIG. 8B, the semiconductor chip50shown inFIG. 8Cand the semiconductor chip52shown inFIG. 8D. That is, the semiconductor chip31,36,40,42,44,46,48,50or52can be adhered to the die pad86aof the lead frame86using the glue material54, which can be referred to the above description concerningFIG. 11A, followed by the steps as referred to inFIGS. 11B-11C, followed by forming a plurality of chip packages92,94,96,98,100,102,104,106or108using the above-mentioned debunking, trimming, cutting and punching process.

InFIGS. 12C-12L, from a top perspective view, the position of the metal trace32bonded with the wire58may be different from that of the pad16, to which the metal trace32is connected, or from that of the metal cap18, to which the metal trace32is connected. For example, the metal trace32of the chip package92,94,96,98or100can be bonded with the wire58, and from a top perspective view, the position of the metal trace32bonded with the wire58is different from that of the pad16, to which the metal trace32is connected. Alternatively, the metal trace32of the chip package102,104,106or108can be bonded with the wire58, and from a top perspective view, the position of the metal trace32bonded with the wire58is different from that of the metal cap18, to which the metal trace32is connected.

For example, the metal trace32of the chip package92,94,96,98or100can be bonded with the wire58, and from a top perspective view, the position of the metal trace32bonded with the wire58is the same as that of the pad16, to which the metal trace32is connected. Alternatively, the metal trace32of the chip package102,104,106or108can be bonded with the wire58, and from a top perspective view, the position of the metal trace32bonded with the wire58is the same as that of the metal cap18, to which the metal trace32is connected.

For example, two wires58can be bonded to one of the metal traces32of the chip package92,94,96,98or100. From a top perspective view, one of the two wires58is bonded to a first bonding pad32aof the metal trace32, the position of which is the same as that of the pad16, and the other one of the two wires58is bonded to a second bonding pad32bof the metal trace32, the position of which is different from that of the pad16. The first bonding pad32ais connected to the second bonding pad32b.

For example, two wires58can be bonded to one of the metal traces32of the chip package102,104,106or108. From a top perspective view, one of the two wires58is bonded to a first bonding pad32aof the metal trace32, the position of which is the same as that of the metal cap18, and the other one of the two wires58is bonded to a second bonding pad32bof the metal trace32, the position of which is different from that of the metal cap18. The first bonding pad32ais connected to the second bonding pad32b.

Those described above are the embodiments to exemplify the present invention to enable the person skilled in the art to understand, make and use the present invention. However, it is not intended to limit the scope of the present invention. Any equivalent modification and variation according to the spirit of the present invention is to be also included within the scope of the claims stated below.