ELECTROSTATIC DISCHARGE PROTECTION DEVICE

Disclosed is an electrostatic discharge protection device which includes a substrate including a first well having a first conductivity type and a second well surrounding the first well, first to fifth diffusion regions formed on the first well, and sixth and seventh diffusion regions formed on the second well. The second diffusion region surrounds the first diffusion region, the fourth diffusion region surrounds the fifth diffusion region, and the fifth diffusion region surrounds the second diffusion region and the fourth diffusion region. The sixth diffusion region surrounds the fifth diffusion region, and the seventh diffusion region surrounds the sixth diffusion region. The sixth and seventh diffusion regions are connected to an anode electrode, and the first to fifth diffusion regions are connected a cathode electrode.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0032776 filed on Mar. 13, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in their entireties.

BACKGROUND

Embodiments of the present disclosure described herein relate to a thyristor-based electrostatic discharge protection device.

An electrostatic discharge protection device that is a silicon controlled rectifier (SCR) (or thyristor) is triggered by the reverse breakdown between an N-well and a P-well and has a trigger voltage of a relatively high level. In addition, a typical silicon controlled rectifier-based electrostatic discharge protection device has a holding voltage of a relatively low level due to an internal parasitic bipolar junction transistor (BJT).

Meanwhile, in some cases, a trigger voltage of a high level may be required depending on the specifications of a required product. A method of adjusting a distance between the P-well and the N-well, in which the reverse breakdown occurs, may be used to design an electrostatic discharge protection device that has a trigger voltage of a high level. However, when a value of the trigger voltage is increased by increasing the distance between the P-well and the N-well, the electrostatic discharge protection device may not operate properly due to a decrease in a current gain.

Accordingly, to meet product specifications, it is very important to design an electrostatic discharge protection device, which operates stably at a trigger voltage of a high level, in terms of reliable protection of the electronic device.

SUMMARY

Embodiments of the present disclosure provide an electrostatic discharge (ESD) protection device capable of efficiently discharging an ESD current of a high value.

In accordance with an aspect of the disclosure, an electrostatic discharge protection device includes a substrate having a first conductivity type; a first well formed on the substrate and having the first conductivity type; a second well formed on the substrate surrounding the first well in a plan view, the second well having a second conductivity type; a first diffusion region formed on the first well and having the first conductivity type; a second diffusion region formed on the first well surrounding the first diffusion region in the plan view, the second diffusion region having the second conductivity type; a third diffusion region formed on the first well and having the first conductivity type; a fourth diffusion region formed on the first well surrounding the third diffusion region in the plan view, the fourth diffusion region having the second conductivity type; a fifth diffusion region formed on the first well surrounding the second diffusion region and the third diffusion region in the plan view, the fifth diffusion region having the first conductivity type; a sixth diffusion region formed on the second well to surround the fifth diffusion region in the plan view, the sixth diffusion region having the first conductivity type; and a seventh diffusion region formed on the second well surrounding the sixth diffusion region in the plan view, the seventh diffusion region having the second conductivity type, wherein the sixth diffusion region and the seventh diffusion region are connected to a first electrode, and the first diffusion region to the fourth diffusion region are connected to a second electrode.

In accordance with an aspect of the disclosure, an electrostatic discharge protection device includes a substrate of a first conductivity type; a first well formed on the substrate and having the first conductivity type; a second well formed on the substrate surrounding the first well in a plan view, the second well having a second conductivity type; a first diffusion region and a second diffusion region formed on the first well and having the second conductivity type; a third diffusion region formed on the first well surrounding the first diffusion region and the second diffusion region in the plan view, the third diffusion region having the first conductivity type; a fourth diffusion region formed on the second well surrounding the third diffusion region in the plan view, the fourth diffusion region having the first conductivity type; and a fifth diffusion region formed on the second well surrounding the fourth diffusion region in the plan view, the fifth diffusion region having the second conductivity type, wherein the fourth diffusion region and the fifth diffusion region are connected to a first electrode, and the first diffusion region to the third diffusion region are connected to a second electrode.

In accordance with an aspect of the disclosure, an electrostatic discharge protection device includes a first well formed on a substrate and having a first conductivity type; a second well formed on the substrate surrounding the first well in a plan view, the second well having a second conductivity type; a first diffusion region and a second diffusion region formed on the first well and having the second conductivity type; a third diffusion region formed on the first well surrounding the first diffusion region and the second diffusion region in the plan view, the third diffusion region having the first conductivity type; a fourth diffusion region formed on the second well surrounding the third diffusion region in the plan view, the fourth diffusion region having the first conductivity type; a fifth diffusion region formed on the second well surrounding the fourth diffusion region in the plan view, the fifth diffusion region having the second conductivity type; a third well formed on the substrate and having the first conductivity type; a fourth well formed on the substrate surrounding the third well in the plan view, the fourth well having the second conductivity type; a sixth diffusion region and a seventh diffusion region formed on the third well and having the second conductivity type; an eighth diffusion region formed on the third well surrounding the sixth diffusion region and the seventh diffusion region in the plan view, the eighth diffusion region having the first conductivity type; a ninth diffusion region formed on the fourth well surrounding the eighth diffusion region in the plan view, the ninth diffusion region having the first conductivity type; and a tenth diffusion region formed on the fourth well surrounding the ninth diffusion region in the plan view, the tenth diffusion region having the second conductivity type, wherein the first diffusion region, the second diffusion region, the third diffusion region, the ninth diffusion region, and the tenth diffusion region are electrically connected to each other, and wherein the fourth diffusion region and the fifth diffusion region are connected to a first electrode, and the sixth diffusion region and the seventh diffusion region are connected to a second electrode.

DETAILED DESCRIPTION

Below, embodiments of the present disclosure will be described in detail and clearly to such an extent that one of ordinary skill in the art may easily carry out the present disclosure.

It will be understood that when an element is referred to as being “connected”, “coupled”, or “adjacent” to another element, it can be directly connected, coupled, or adjacent to another element or intervening element or can be “indirectly connected”, “indirectly coupled”, or “indirectly adjacent”, with another element or layer interposed therebetween. As used herein, the term “and/or” may include one or more combinations of listed items.

Even though the terms “first”, “second”, etc. may be used herein to describe various elements, it should be understood that these elements should not be limited by these terms. These terms may be used only to distinguish one element from another element. Accordingly, the term “first element”, “first section”, “first layer”, etc. used in the specification could be termed a “second element”, “second section”, “second layer”, etc. without departing from the teachings of the invention.

FIG.1illustrates a plan view of an ESD protection device100according to an embodiment of the present disclosure.FIG.2illustrates a cross-sectional view of the ESD protection device100taken along line I-I′ ofFIG.1.FIG.3illustrates a cross-sectional view of an ESD protection device100taken along line II-II′ ofFIG.1.

Referring toFIGS.1,2, and3, the ESD protection device100may include a substrate101, a high voltage N-well (HVNWELL)106, a P-well121, an N-well123, a first diffusion region131, a second diffusion region132, a third diffusion region133, a fourth diffusion region134, a fifth diffusion region135, a sixth diffusion region136, and a seventh diffusion region137.

The substrate101may be a crystalline semiconductor substrate such as a semiconductor wafer. The substrate101may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, or a silicon-germanium substrate. For example, the substrate101may include at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof. The substrate101may have a single crystal structure. The substrate101may be doped with P-type impurities (i.e., a charge carrier dopant) of a low concentration.

The N-well106may be formed on the substrate101. The dopant concentration of the N-well106may be higher than the dopant concentration of the substrate101, and the N-well106may be a high-voltage N-well.

The P-well121may be formed on the N-well106, and the N-well123may be formed on the N-well106to surround the P-well121. That is, inFIG.2, the N-well123may extend along a second direction D2; inFIG.3, the N-well123may extend along a first direction D1. The P-well121and the N-well123may be spaced from each other along the first direction D1and the second direction D2. The P-well121may be doped with P-type impurities, and the N-well123may be doped with N-type impurities. For example, the dopant concentration of the P-well121and the dopant concentration of the N-well123may be higher than the dopant concentration of the N-well106.

In an embodiment, the N-well123and the P-well121may be disposed to be spaced from each other, not adjacent to each other. For example, as the N-well123and the P-well121are disposed not to contact each other, a value of the trigger voltage of the ESD protection device100may increase compared to the case where the P-well121and the N-well123contact each other.

The first diffusion region131may be formed on the P-well121. The second diffusion region132may be formed on the P-well121, and the second diffusion region132may surround the first diffusion region131in a plan view (see, e.g.,FIG.1). The first diffusion region131may be doped with P-type impurities to have a P-type conductivity, and the second diffusion region132may be doped with N-type impurities to have an N-type conductivity. For example, the dopant concentration of the first diffusion region131and the dopant concentration of the second diffusion region132may be higher than the dopant concentration of the P-well121.

The third diffusion region133may be formed on the P-well121. The first diffusion region131and the third diffusion region133may be disposed to be spaced from each other in the first direction D1. The fourth diffusion region134may be formed on the P-well121, and the fourth diffusion region134may surround the third diffusion region133in a plan view. The second diffusion region132and the fourth diffusion region134may be disposed to be spaced from each other in the first direction D1. The third diffusion region133may be doped with P-type impurities, and the fourth diffusion region134may be doped with N-type impurities. The dopant concentration of the third diffusion region133and the dopant concentration of the fourth diffusion region134may be higher than the dopant concentration of the P-well121.

The fifth diffusion region135may be formed on the P-well121. The fifth diffusion region135may surround the second diffusion region132and the fourth diffusion region134in a plan view. For example, the fifth diffusion region135may surround each of the second diffusion region132and the fourth diffusion region134in a plan view and may extend between the second diffusion region132and the fourth diffusion region134. The dopant concentration of the fifth diffusion region135may be higher than the dopant concentration of the P-well121.

The first diffusion region131, the second diffusion region132, the third diffusion region133, the fourth diffusion region134, and the fifth diffusion region135may be electrically separated (or isolated) from each other by a shallow trench isolation STI. However, the shallow trench isolation STI does not exclude a flow of a current according to an operation of a thyristor (i.e., a silicon controlled rectifier SCR) that is formed by parasitic BJTs (e.g., Q1, Q2, Q3, and Q4) to be described later.

The sixth diffusion region136may be formed on the N-well123. The seventh diffusion region137may be formed on the N-well123. The sixth diffusion region136may surround the fifth diffusion region135in a plan view, and the seventh diffusion region137may surround the sixth diffusion region136in a plan view. The dopant concentration of the sixth diffusion region136and the dopant concentration of the seventh diffusion region137may be higher than the dopant concentration of the N-well123.

The sixth diffusion region136and the seventh diffusion region137may be electrically connected to each other. To this end, a metal interconnection and/or a via for electrical connection may be used. The sixth diffusion region136and the seventh diffusion region137may be connected to a first electrode E1and a second electrode E2. The first electrode E1and the second electrode E2may be an anode electrode receiving an electrostatic discharge (ESD) voltage.

The first diffusion region131to the fifth diffusion region135may be electrically connected to each other, for example, through a metal interconnection and/or a via. The first diffusion region131to the fifth diffusion region135may be connected to a third electrode E3and a fourth electrode E4. The third electrode E3and the fourth electrode E4may be a cathode electrode connected to a ground node.

Although the first electrode E1and the second electrode E2are illustrated as the anode electrode and the third electrode E3and the fourth electrode E4are illustrated as the cathode electrode, the number of electrodes is not limited thereto.

In an embodiment, at least one resistor may be connected between the second diffusion region132and the fifth diffusion region135. An embodiment in which a first resistor R1and a third resistor R3are connected between the second diffusion region132and the fifth diffusion region135is illustrated as an example. At least one resistor may be connected between the fourth diffusion region134and the fifth diffusion region135. An embodiment in which a second resistor R2and a fourth resistor R4are connected therebetween is illustrated. The resistors R1to R4may cause a voltage drop when the ESD current (or voltage) is introduced, thus making it easy to trigger the thyristor.

In an embodiment, a length of the fifth diffusion region135in the first direction D1may be set in advance to determine a breakdown voltage of the ESD protection device100. For example, as the length of the fifth diffusion region135in the first direction D1increases, a value of the breakdown voltage of the ESD protection device100may become greater. In contrast, as the length of the fifth diffusion region135in the first direction D1decreases, a value of the breakdown voltage of the ESD protection device100may become smaller.

Referring to an equivalent circuit diagram illustrated inFIG.2, the sixth diffusion region136connected to the first electrode E1, the N-well123, and the P-well121may constitute a PNP transistor Q1. The N-well123connected to the first electrode E1through the diffusion regions136and137, the P-well121, and the second diffusion region132may constitute an NPN transistor Q2. As in the above description, the sixth diffusion region136connected to the second electrode E2, the N-well123, and the P-well121may constitute a PNP transistor Q3, and the N-well123, the P-well121, and the fourth diffusion region134may constitute an NPN transistor Q4.

In detail, the N-well123, the sixth diffusion region136connected to the first electrode E1, and the P-well121may respectively form a base, an emitter, and a collector of the PNP transistor Q1, and the P-well121, the second diffusion region132, and the N-well123may respectively form a base, an emitter, and a collector of the NPN transistor Q2. As in the above description, the N-well123, the sixth diffusion region136connected to the second electrode E2, and the P-well121may respectively form a base, an emitter, and a collector of the PNP transistor Q3, and the P-well121, the fourth diffusion region134, and the N-well123may respectively form a base, an emitter, and a collector of the NPN transistor Q4.

To describe an operation of the ESD protection device100, assuming that the ESD voltage is input through the first electrode E1and the second electrode E2, a potential of the N-well123increases. As a result, the N-well123and the P-well121may be in a reverse bias state, and a depletion region may be formed. As the ESD current is continuously input, an electric field formed in the depletion region may exceed a threshold point; in this case, reverse breakdown (e.g., avalanche breakdown) may occur between the N-well123and the P-well121. That is, electron-hole pairs (EHPs) may be generated in the depletion region, and thus, a hole current may be generated by the generated carriers (i.e., EPHs).

As the hole current first flows through an internal resistance (not illustrated) of the P-well121, a voltage drop occurs. In this case, as a diode formed by a PN junction between the P-well121and the second diffusion region132is turned on by the voltage of the P-well121, the NPN transistor Q2may be turned on. The hole current flows through an internal resistance (not illustrated) of the N-well123, and thus, a voltage drop occurs. In this case, as a diode formed by a PN junction between the N-well123and the sixth diffusion region136formed on the N-well123is turned on by the voltage of the N-well123, the PNP transistor Q1may be turned on.

According to the above description, a positive feedback operation may be maintained while two parasitic transistors Q1and Q2mutually provide a base current, and thus, the ESD protection device100may enter a latch mode. In the latch mode of the ESD protection device100, as a current discharge path is formed through the transistors Q1and Q2, the ESD current may be discharged through the third electrode E3and the fourth electrode E4. The above operations may also occur in the transistors Q3and Q4.

According to the above embodiment, a value of the breakdown voltage of the ESD protection device100may be efficiently adjusted. For example, in a conventional ESD protection device, a value of a breakdown voltage may be adjusted by adjusting a distance between a P-well (e.g., corresponding to121) and an N-well (e.g., corresponding to123); however, when the distance between the P-well and the N-well exceeds a specific value, after the ESD protection device is triggered, a current gain of the parasitic transistor Q2may decrease. This may mean that the performance of the ESD protection device is reduced. However, as the ESD protection device100of the present disclosure is implemented such that diffusion regions (e.g.,132and135) surround other diffusion regions (e.g.,131and132), the N-well123surrounds the P-well121, and diffusion regions (e.g.,136and137) surround other diffusion regions (e.g.,131,132,133,134, and135), a thyristor operation may be induced, and thus, a high current gain may be obtained. Accordingly, an ESD protection device that discharges an ESD voltage (or current) of a great value efficiently may be implemented.

FIG.4is a graph illustrating an operating characteristic of the ESD protection device100of the present disclosure.

Referring toFIG.4, a trigger voltage of a conventional ESD protection device, in which the distance between the P-well and the N-well is extended to increase a breakdown voltage, may be “Vtrig1”. In contrast, a trigger voltage of an ESD protection device of the present disclosure may be “Vtrig2”, and a holding voltage thereof may be “Vhold2”. Herein, the trigger voltage may mean a voltage immediately before a parasitic NPN transistor (e.g., Q2and Q4ofFIG.2) in the ESD protection device is turned on. The holding voltage may mean the lowest voltage in a negative resistance region (i.e., a snapback region) in which a voltage decreases because the parasitic NPN transistor fails to sustain a high voltage after operating.

Meanwhile, referring to the graph of the conventional ESD protection device, it is understood that the ESD protection device does not operate normally after triggered. The reason is that when the distance between the P-well and the N-well is extended to increase a value of a breakdown voltage that the ESD protection device is capable of enduring, the current gain decreases. That is, the ESD protection device does not operate normally.

In contrast, according to an ESD protection device of the present disclosure, it is confirmed from the graph ofFIG.4that the ESD protection device is triggered at a relatively high voltage of Vtrig2, has the holding voltage of Vhold2after the snapback region is formed, and has a time period where a value of the ESD current increases.

FIG.5illustrates a cross-sectional view of the ESD protection device100taken along line I-I′ ofFIG.1.

The ESD protection device100ofFIG.5may be mostly similar to the ESD protection device100ofFIG.2. However, the ESD protection device100may not include the resistors R1, R2, R3, and R4illustrated inFIG.2. For example, the ESD protection device100ofFIG.2includes the resistors R1, R2, R3, and R4for making the triggering of the thyristor easy by causing a voltage drop when an ESD current (or voltage) is introduced. However, in some cases, a resistance value sufficient to make the triggering of the thyristor easy may be implemented only with self-resistances of metal interconnections and/or vias for electrically connecting the electrodes E1, E2, E3, and E4and the diffusion regions131to137. In this case, the resistors R1, R2, R3, and R4illustrated inFIG.2may not be required.

FIG.6illustrates a cross-sectional view of the ESD protection device100taken along line I-I′ ofFIG.1.

The ESD protection device100ofFIG.6may be mostly similar to the ESD protection device100ofFIG.2. However, the ESD protection device100ofFIG.6may further include gate polysilicon patterns GP compared to the ESD protection device100ofFIG.2. The ESD protection device100may be manufactured through the CMOS process, and a gate electrode (i.e., the gate polysilicon pattern GP) may be formed in the process of manufacturing the ESD protection device100. For example, the gate electrode may not be a gate electrode for forming a channel and may be formed on a device isolation layer such as STI. That is, the gate electrode illustrated inFIG.6may be a dummy gate electrode. For example, the gate polysilicon pattern GP may have a self-resistance and may cause a voltage drop when an ESD current (or voltage) is introduced.

FIG.7illustrates a cross-sectional view of the ESD protection device100taken along line I-I′ ofFIG.1.

The ESD protection device100ofFIG.7may be mostly similar to the ESD protection device100ofFIG.2. Thus, additional description will be omitted to avoid redundancy. However, the ESD protection device100ofFIG.7may further include a P-well115, a P-well125, and an eighth diffusion region138. Although the P-well115, the P-well125, and the eighth diffusion region138are not illustrated inFIG.2, it may be understood that the P-well115, the P-well125, and the eighth diffusion region138may be formed in a region outside the outermost shallow trench isolation STI.

The P-well115may be provided on the substrate101, and the P-well125may be provided on the P-well115. Herein, the dopant concentration of the P-well115may be lower than the dopant concentration of the P-well125, and the P-well115may be a high-voltage P-well (HVPW). The eighth diffusion region138doped with P-type impurities may be provided on the P-well125. In an embodiment, the P-well115, the P-well125, and the eighth diffusion region138may constitute a guard ring GR surrounding the ESD protection device100. The guard ring GR may prevent a latch-up phenomenon in which the ESD current introduced to the ESD protection device100is discharged to the outside instead of to the third and fourth electrodes E3and E4. Components associated with the guard ring GR illustrated inFIG.7may be applied to the embodiments ofFIGS.5and6.

FIG.8illustrates a cross-sectional view of the ESD protection device100taken along line I-I′ ofFIG.1.FIG.9illustrates a cross-sectional view of the ESD protection device100taken along line I-I′ ofFIG.1.FIG.10illustrates a cross-sectional view of the ESD protection device100taken along line I-I′ ofFIG.1. The ESD protection devices100ofFIGS.8to10may be mostly similar to the ESD protection devices100ofFIGS.2and4. However, the ESD protection devices100ofFIGS.8to10are similar to the ESD protection devices100ofFIGS.2,5, and6respectively, except that the P-well121and the N-well123are formed on the substrate101without including the N-well106, and thus, additional description will be omitted to avoid redundancy.

FIG.11illustrates a cross-sectional view of the ESD protection device100taken along line I-I′ ofFIG.1.

Referring toFIGS.1and11, the ESD protection device100may include the substrate101, a buried layer102, an epitaxial layer104, a P-type drift region111, an N-type drift region113, the P-well121, a P-well122, the N-well123, and the diffusion regions131to137.

The substrate101may be a semiconductor substrate such as a semiconductor wafer. The epitaxial layer104may be formed on the substrate101. The epitaxial layer104may be formed on the substrate101through selective epitaxial growth or solid phase epitaxial growth. Although the substrate101and the epitaxial layer104are illustrated inFIG.11as independent components, the epitaxial layer104may be understood as being as a portion of the substrate101. The substrate101may have a low dopant concentration of P-type conductivity, and the epitaxial layer104may have a low dopant concentration of N-type conductivity. For example, the dopant concentration of the epitaxial layer104may be lower than the dopant concentration of any other doped region, but the present invention is not limited thereto.

The buried layer102may be formed between the epitaxial layer104and the substrate101. The buried layer102may be formed by injecting N-type impurities (i.e., dopant) of a low dopant concentration between the substrate101and the epitaxial layer104. For example, the dopant concentration of the buried layer102may be higher than the dopant concentration of any other doped region, but the present invention is not limited thereto.

The P-well121and the N-well123may be formed on the epitaxial layer104. For example, the N-well123may be formed on the epitaxial layer104to surround the P-well121in a plan view. The P-type drift region111may be formed on a lower portion of the P-well121, and the N-type drift region113may be formed on a lower portion of the N-well123. For example, the N-type drift region113may be formed on the epitaxial layer104to surround the P-type drift region111in a plan view. For example, the level (i.e., height) from the substrate101, at which the N-type drift region113is formed may be mostly (or substantially) the same as the level (i.e., height) from the substrate101, at which the P-type drift region111is formed. The P-well121and the N-well123may be doped with impurities of a relatively high concentration, and the P-type drift region111and the N-type drift region113may be doped with impurities of a concentration lower than the concentration of the P-well121and the N-well123.

The P-well122may be formed in the P-well121and the P-type drift region111. The P-well122may be formed to be similar in shape to the fifth diffusion region135illustrated inFIG.1in a plan view. For example, the doping concentration of the P-well122may be lower than the doping concentration of the P-well121and the P-type drift region111. The P-well122may be a deep-well in that the P-well122is formed to be deeper than the P-well121.

The first diffusion region131may be formed on the P-well121, and the second diffusion region132may be formed on the P-well121to surround the first diffusion region131in a plan view. The third diffusion region133may be formed on the P-well121, and the fourth diffusion region134may be formed on the P-well121to surround the third diffusion region133in a plan view. The first diffusion region131and the third diffusion region133may be doped with P-type impurities of a higher concentration than the P-well121, and the second diffusion region132and the fourth diffusion region134may be doped with N-type impurities of a higher concentration than the P-well121.

The fifth diffusion region135may be formed on the P-well122. The fifth diffusion region135may be formed on the P-well122to surround the second diffusion region132and the fourth diffusion region134in a plan view. The fifth diffusion region135may be doped with P-type impurities of a higher concentration than the P-well121and the P-well122.

The sixth diffusion region136and the seventh diffusion region137may be formed on the N-well123. The sixth diffusion region136may be formed on the N-well123to surround the fifth diffusion region135in a plan view, and the seventh diffusion region137may be formed on the N-well123to surround the sixth diffusion region136in a plan view. The sixth diffusion region136may be doped with P-type impurities of a higher concentration than the N-well123, and the seventh diffusion region137may be doped with N-type impurities of a higher concentration than the N-well123.

Referring to an equivalent circuit diagram illustrated inFIG.11, the sixth diffusion region136connected to the first electrode E1, the N-well123, and the P-well121may constitute the PNP transistor Q1. The N-well123connected to the first electrode E1through the diffusion regions136and137, the P-well121, and the second diffusion region132may constitute the NPN transistor Q2. As in the above description, the sixth diffusion region136connected to the second electrode E2, the N-well123, and the P-well121may constitute the PNP transistor Q3, and the N-well123connected to the second electrode E2through the diffusion regions136and137, the P-well121, and the fourth diffusion region134may constitute the NPN transistor Q4.

In detail, the N-well123, the sixth diffusion region136connected to the first electrode E1, and the P-well121may respectively form a base, an emitter, and a collector of the PNP transistor Q1, and the P-well121, the second diffusion region132, and the N-well123may respectively form a base, an emitter, and a collector of the NPN transistor Q2. As in the above description, the N-well123, the sixth diffusion region136connected to the second electrode E2, and the P-well121may respectively form a base, an emitter, and a collector of the PNP transistor Q3, and the P-well121, the fourth diffusion region134, and the N-well123may respectively form a base, an emitter, and a collector of the NPN transistor Q4.

The ESD protection device100operates based on a first thyristor composed of the transistors Q1and Q2and a second thyristor composed of the transistors Q3and Q4. In particular, the P-type drift region111, the N-type drift region113, the P-well121, the P-well122, and the diffusion regions131to137constituting the thyristors performing the electrostatic discharge function may be referred to as “one cell”. The detailed operation of the ESD protection device100is the same as the operation of the ESD protection device100illustrated inFIG.3, and thus, additional description will be omitted to avoid redundancy.

In an embodiment, the bases and the emitters of the transistors Q1, Q2, Q3, and Q4of the ESD protection device100ofFIG.11are formed in upper layers of the buried layer102. In this case, even though the first thyristor composed of the transistors Q1and Q2and the second thyristor composed of the transistors Q3and Q4are connected in series to thyristors of another cell adjacent thereto, the buried layer102may not be shared. That is, the capacity of the ESD current capable of being discharged by electrically connecting the cell ofFIG.11and a cell adjacent thereto may increase. This will be described in detail with reference toFIGS.15and16.

FIG.12illustrates a cross-sectional view of the ESD protection device100taken along line I-I′ ofFIG.1.

The ESD protection device100ofFIG.12may be mostly similar to the ESD protection device100ofFIG.11. However, the ESD protection device100ofFIG.12may not include resistors (i.e., R1, R2, R3, and R4ofFIG.11) for making the triggering of the thyristor easy when an ESD current (or voltage) is introduced. For example, in an embodiment, a resistance value sufficient to make the triggering of the thyristor easy may be implemented only with self-resistances of metal interconnections and/or vias for electrically connecting the electrodes E1, E2, E3, and E4and the diffusion regions131to137, and thus, the resistors illustrated inFIG.11may not be required.

FIG.13illustrates a cross-sectional view of the ESD protection device100taken along line I-I′ ofFIG.1.

The ESD protection device100ofFIG.13may be mostly similar to the ESD protection device100ofFIG.11and may further include the gate polysilicon patterns GP compared to the ESD protection device100ofFIG.11. The ESD protection device100may be manufactured through the CMOS process, and a dummy gate electrode (i.e., the gate polysilicon pattern GP) may be formed in the process of manufacturing the ESD protection device100. That is, the dummy gate electrode GP may not be a gate electrode for forming a channel of a transistor (i.e., a field effect transistor (FET)) and may be formed on a device isolation layer such as STI. The dummy gate electrode GP may have a self-resistance and may cause a voltage drop when an ESD current (or voltage) is introduced.

FIG.14illustrates a cross-sectional view of the ESD protection device100taken along line I-I′ ofFIG.1.

The ESD protection device100ofFIG.14may be mostly similar to the ESD protection device100ofFIG.11. Thus, additional description will be omitted to avoid redundancy. However, the ESD protection device100ofFIG.14may further include a buried layer103, an epitaxial layer105, the P-well115, the P-well125, and the eighth diffusion region138. Although the above components are not illustrated inFIG.1, this may be understood as being formed in a region outside the outermost shallow trench isolation STI ofFIG.1.

The epitaxial layer105may be formed on the substrate101, and the buried layer103doped with P-type impurities of a high concentration may be formed between the substrate101and the epitaxial layer105. The epitaxial layer105may have a low-concentration N-type conductivity. In an embodiment, the buried layer103, the epitaxial layer105, the P-well115, the P-well125, and the eighth diffusion region138may constitute the guard ring GR, and the guard ring GR may prevent a latch-up phenomenon in which the ESD current introduced to the ESD protection device100is discharged to the outside. Components associated with the guard ring GR illustrated inFIG.14may be applied to the embodiments ofFIGS.12and13.

FIG.15is a plan view of an ESD protection device100A including a plurality of cells according to an embodiment of the present disclosure.

The ESD protection device100A may include a plurality of cells C1, C2, C3, and C4. For example, each of the plurality of cells C1, C2, C3, and C4may be any one of the cells described with reference to the above embodiments.

In an embodiment, the plurality of cells C1, C2, C3, and C4may be arranged along the first direction D1and the second direction D2. The plurality of cells C1, C2, C3, and C4may be distinguished from each other by the guard ring GR in a plan view, and the guard ring GR may surround each of the plurality of cells C1, C2, C3, and C4in a plan view. For example, the guard ring GR may extend around an outer periphery of the plurality of cells C1, C2, C3, and C4and may extend between adjacent ones of the plurality of cells C1, C2, C3, and C4. The guard ring GR may prevent the ESD current (or voltage) introduced to the plurality of cells C1, C2, C3, and C4from flowing to the outside.

FIG.16is a circuit diagram of the cells C1and C2of an ESD protection device illustrated inFIG.15.

The ESD protection device100A may include the first cell C1and the second cell C2. The first cell C1may include the transistors Q1and Q2constituting a first thyristor and the transistors Q3and Q4constituting a second thyristor. The first cell C1may include resistors Ra1, Rb1, Rc1, Rd1, Re1, Rnw1, and Rnw2. The second cell C2may include transistors Q5and Q6constituting a third thyristor and transistors Q7and Q8constituting a fourth thyristor. The second cell C2may include resistors Ra2, Rb2, Rc2, Rd2, Re2, Rnw3, and Rnw4. However, the resistors Ra1, Rb1, Rc1, Rd1, Re1, Rnw1, and Rnw2of the first cell C1and the resistors Ra2, Rb2, Rc2, Rd2, Re2, Rnw3, and Rnw4of the second cell C2are simply models and are provided as an example, and a detailed placement and a detailed connection relationship of resistors are not limited to the example illustrated inFIG.16.

The first cell C1may include the first electrode E1and the second electrode E2. The first electrode E1and the second electrode E2may be an anode electrode receiving the ESD current (or voltage). The second cell C2may include the third electrode E3and the fourth electrode E4. The third electrode E3and the fourth electrode E4may be a cathode electrode connected to a ground node. A first node N1of the first cell C1may be connected to a third node N3of the second cell C2, and a second node N2of the first cell C1may be connected to a fourth node N4of the second cell C2.

The ESD current input to the first electrode E1and the second electrode E2may be transferred to the third node N3and the fourth node N4through the first node N1and the second node N2. The ESD current input to the third node N3and the fourth node N4may flow to a ground electrode through the third electrode E3and the fourth electrode E4.

According to the above configuration, as two or more cells are connected in series, the amount of ESD current (or voltage) that the ESD protection device100A discharges may increase. Accordingly, the ESD current of a high level may be efficiently discharged. This may mean that the performance of the ESD protection device100A is improved.

FIG.17illustrates a plan view of an ESD protection device200according to an embodiment of the present disclosure.FIG.18illustrates a cross-sectional view of an ESD protection device200taken along line III-III′ ofFIG.17.

Referring toFIGS.17and18, the ESD protection device200may include a substrate201, an N-well (HVNWELL)206, a P-well221, an N-well223, a first diffusion region231, a second diffusion region232, a third diffusion region233, a fourth diffusion region234, and a fifth diffusion region235.

The substrate201may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, or a silicon-germanium substrate. The substrate201may have a single crystal structure. The substrate201may be doped with P-type impurities (i.e., dopant) of a low concentration.

The N-well206whose doping concentration is higher than that of the substrate201may be formed on the substrate201. The N-well106may be a high-voltage N-well. The P-well221may be formed on the N-well206, and the N-well223may be formed on the N-well206to surround the P-well221. The P-well221may be doped with P-type impurities of a higher doping concentration than the N-well206, and the N-well223may be doped with N-type impurities of a higher doping concentration than the N-well206.

The first diffusion region231and the second diffusion region232may be formed on the P-well221, and the first diffusion region231and the second diffusion region232may be spaced from each other in the first direction D1. The third diffusion region233may be formed on the P-well221, and the third diffusion region233may surround the first diffusion region231and the second diffusion region232in a plan view. The fourth diffusion region234and the fifth diffusion region235may be formed on the N-well223. The fourth diffusion region234may surround the third diffusion region233in a plan view, and the fifth diffusion region235may surround the fourth diffusion region234in a plan view.

The first diffusion region231, the second diffusion region232, and the fifth diffusion region235may be doped with N-type impurities, and the third diffusion region233and the fourth diffusion region234may be doped with P-type impurities. The doping concentration of the first diffusion region231to the third diffusion region233may be higher than the doping concentration of the P-well221. The doping concentration of the fourth diffusion region234and the fifth diffusion region235may be higher than the doping concentration of the N-well223.

The first diffusion region231to the fifth diffusion region235may be electrically isolated (or separated) from each other by a device isolation layer (e.g., an STI).

The fourth diffusion region234and the fifth diffusion region235may be electrically connected to each other, for example, through a metal interconnection and/or a via, and the first diffusion region231to the third diffusion region233may be electrically connected to each other, for example, through a metal interconnection and/or a via. The fourth diffusion region234and the fifth diffusion region235may be connected to a first electrode E1and a second electrode E2, and the first diffusion region231to the third diffusion region233may be connected to a third electrode E3. The first electrode E1and the second electrode E2may be an anode electrode receiving an ESD current (or voltage), and the third electrode E3may be a cathode electrode connected to a ground node.

In an embodiment, a first resistor R1may be connected between the first diffusion region231and the third diffusion region233, and a second resistor R2may be connected between the second diffusion region232and the third diffusion region233. The resistors R1and R2may cause a voltage drop when the ESD current (or voltage) is introduced, thus making the triggering of the thyristor easy.

Referring to an equivalent circuit diagram illustrated inFIG.18, the fourth diffusion region234connected to the first electrode E1, the N-well223, and the P-well221may constitute a PNP transistor Q1. The N-well223connected to the first electrode E1through the diffusion regions234and235, the P-well221, and the first diffusion region231may constitute an NPN transistor Q2. The fourth diffusion region234connected to the second electrode E2, the N-well223, and the P-well221may constitute a PNP transistor Q3, and the N-well223connected to the second electrode E2through the diffusion regions234and235, the P-well221, and the first diffusion region231may constitute an NPN transistor Q4.

In detail, the N-well223, the fourth diffusion region234connected to the first electrode E1, and the P-well221may respectively form a base, an emitter, and a collector of the PNP transistor Q1, and the P-well221, the first diffusion region231, and the N-well223may respectively form a base, an emitter, and a collector of the NPN transistor Q2. As in the above description, the N-well223, the fourth diffusion region234connected to the second electrode E2, and the P-well221may respectively form a base, an emitter, and a collector of a PNP transistor Q3, and the P-well221, the second diffusion region232, and the N-well223may respectively form a base, an emitter, and a collector of an NPN transistor Q4.

The ESD protection device200ofFIG.18is different in structure from those of the above embodiments. However, the ESD protection device200is substantially the same as the ESD protection devices100described with reference toFIGS.1to14in that the ESD protection device200includes two thyristors each including two BJTs, and the operating principle of the ESD protection device200is also the same as that of the ESD protection devices100described with reference toFIGS.1to14. Thus, additional description will be omitted to avoid redundancy.

FIG.19illustrates a cross-sectional view of the ESD protection device200taken along line III-III′ ofFIG.17.

The ESD protection device200ofFIG.19may be mostly similar to the ESD protection device200ofFIG.18. However, the ESD protection device200ofFIG.19may not include the resistors R1, R2, R3, and R4ofFIG.18, which make the triggering of the thyristor easy. Instead, a resistance value sufficient to make the triggering of the thyristor easy may be implemented only with self-resistances of metal interconnections and/or vias for electrically connecting the electrodes E1, E2, and E3and the diffusion regions231to235. In this case, the resistors R1, R2, R3, and R4illustrated inFIG.18may not be required.

FIG.20illustrates a cross-sectional view of an ESD protection device200taken along line III-III′ ofFIG.17.

The ESD protection device200ofFIG.20may be mostly similar to the ESD protection device200ofFIG.18. However, the ESD protection device200ofFIG.20may further include gate polysilicon patterns GP formed through the CMOS process, compared to the ESD protection device200ofFIG.18. For example, a gate electrode illustrated inFIG.20may be a dummy gate electrode. The gate polysilicon pattern GP may have a self-resistance and may cause a voltage drop when the ESD current (or voltage) is introduced.

FIG.21illustrates a cross-sectional view of an ESD protection device200taken along line III-III′ ofFIG.17.FIG.22illustrates a cross-sectional view of the ESD protection device200taken along line III-III′ ofFIG.17.FIG.23illustrates a cross-sectional view of an ESD protection device200taken along line III-III′ ofFIG.17. The ESD protection devices200ofFIGS.21to23may be mostly similar to the ESD protection devices200ofFIGS.18and20. However, the ESD protection devices200ofFIGS.18to210differ from the ESD protection devices200ofFIGS.18and20in that the P-well221and the N-well223are formed on the substrate201without including the N-well206, and additional description will be omitted to avoid redundancy.

FIG.24illustrates a cross-sectional view of the ESD protection device200taken along line III-III′ ofFIG.17.

Referring toFIGS.17and24, the ESD protection device200may include the substrate201, a buried layer202, an epitaxial layer204, a P-type drift region211, an N-type drift region213, the P-well221, a P-well222, the N-well223, and the diffusion regions231to235.

The substrate201may be a semiconductor substrate such as a semiconductor wafer. The epitaxial layer204may be formed on the substrate201. The epitaxial layer204may be formed on the substrate201through selective epitaxial growth or solid phase epitaxial growth. The substrate201may have a low-concentration P-type conductivity, and the epitaxial layer204may have a low-concentration N-type conductivity. The buried layer202may be formed between the epitaxial layer204and the substrate201. The buried layer202may be formed by injecting N-type impurities (i.e., dopant) of a low concentration between the substrate201and the epitaxial layer204.

The P-well221and the N-well223may be formed on the epitaxial layer204. The N-well223may be formed on the epitaxial layer204to surround the P-well221in a plan view. The P-type drift region211may be formed on a lower portion of the P-well221, and the N-type drift region213may be formed on a lower portion of the N-well223. The N-type drift region213may be formed on the epitaxial layer204to surround the P-type drift region211in a plan view. The P-well221and the N-well223may be doped with impurities of a relatively high concentration, and the P-type drift region211and the N-type drift region213may be doped with impurities of a concentration lower than the concentration of the P-well221and the N-well223.

The P-well222may be formed in the P-well221and the P-type drift region211. The P-well222may be formed to be similar in shape to the third diffusion region233illustrated inFIG.17in a plan view. For example, the doping concentration of the P-well222may be lower than the doping concentration of the P-well221and the P-type drift region211.

The first diffusion region231and the second diffusion region232may be formed on the P-well221, and the third diffusion region233may be formed on the P-well221to surround the first diffusion region231and the second diffusion region232in a plan view. The first diffusion region231and the second diffusion region232may be doped with N-type impurities of a higher concentration than the P-well221, and the third diffusion region233may be doped with P-type impurities of a higher concentration than the P-well221.

The fourth diffusion region234may be formed on the N-well223to surround the third diffusion region233, and the fifth diffusion region235may be formed on the N-well223to surround the fourth diffusion region234. The fourth diffusion region234may be doped with P-type impurities of a higher concentration than the N-well223, and the fifth diffusion region235may be doped with N-type impurities of a higher concentration than the N-well223.

Referring to an equivalent circuit diagram illustrated inFIG.24, the fourth diffusion region (e.g., an emitter)234connected to the first electrode E1, the N-well (e.g., a base)223, and the P-well (e.g., a collector)221may constitute a PNP transistor Q1. The N-well (e.g., a collector)223connected to the first electrode E1through the diffusion regions234and235, the P-well (e.g., a base)221, and the first diffusion region (e.g., an emitter)231may constitute an NPN transistor Q2.

The fourth diffusion region (e.g., an emitter)234connected to the second electrode E2, the N-well (e.g., a base)223, and the P-well (e.g., a collector)221may constitute a PNP transistor Q3, and the N-well (e.g., a collector)223connected to the second electrode E2through the diffusion regions234and235, the P-well (e.g., a base)221, and the first diffusion region (e.g., an emitter)232may constitute an NPN transistor Q4.

FIG.25illustrates a cross-sectional view of the ESD protection device200taken along line III-III′ ofFIG.17.

The ESD protection device200ofFIG.25may be mostly similar to the ESD protection device200ofFIG.24. However, the ESD protection device200ofFIG.25may not include the resistors R1and R2ofFIG.24, which make the triggering of the thyristor easy. Instead, a resistance value sufficient to make the triggering of the thyristor easy may be implemented only with self-resistances of metal interconnections and/or vias for electrically connecting the electrodes E1, E2, and E3and the diffusion regions231to235. In this case, the resistors R1and R2illustrated inFIG.24may not be required.

FIG.26illustrates a cross-sectional view of an ESD protection device200taken along line III-III′ ofFIG.17.

The ESD protection device200ofFIG.26may be mostly similar to the ESD protection device200ofFIG.24. However, the ESD protection device200ofFIG.26may further include dummy gate electrodes (i.e., gate polysilicon patterns GP) formed through the CMOS process, compared to the ESD protection device200ofFIG.24. The gate polysilicon pattern GP may have a self-resistance and may cause a voltage drop when the ESD current (or voltage) is introduced.

FIG.27illustrates a cross-sectional view of an ESD protection device200taken along line III-III′ ofFIG.17.

The ESD protection device200ofFIG.27may be mostly similar to the ESD protection device200ofFIG.24. Thus, additional description will be omitted to avoid redundancy. Compared to the ESD protection device200ofFIG.24, the ESD protection device200ofFIG.27may further include a buried layer203, an epitaxial layer205, a P-well215, a P-well225, and a sixth diffusion region236. Although the above components are not illustrated inFIG.17, this may be understood as being formed in a region outside the outermost shallow trench isolation STI ofFIG.17.

The epitaxial layer205may be formed on the substrate201, and the buried layer203doped with P-type impurities of a high concentration may be formed between the substrate201and the epitaxial layer205. The buried layer203, the epitaxial layer205, the P-well215, the P-well225, and the sixth diffusion region236may constitute the guard ring GR, and the guard ring GR may prevent a latch-up phenomenon in which the ESD current introduced to the ESD protection device200is discharged to the outside.

Meanwhile, it is possible to connect the cells described with reference toFIGS.17to27in series. For example, the cells ofFIGS.17to27may be connected to be similar to the manner described with reference toFIGS.15and16. For example, the capacity of the ESD current that an ESD protection device is capable of discharging may increase by electrically connecting a cathode electrode of a first cell to an anode electrode of a second cell adjacent to the first cell.

FIG.28illustrates a configuration of an electronic device1000including an ESD protection device1100of the present disclosure.

The electronic device1000may include the ESD protection device1100and a semiconductor chip1200. When the electronic device1000is powered on or operates, a power supply voltage VDD may be supplied to the semiconductor chip1200. An ESD current IESD may occur due to various factors. In this case, as the ESD protection device1100operates, the ESD current IESD may flow to an electrode, to which a ground voltage VSS is applied, through the ESD protection device1100.

FIG.29is a diagram of a system2000which includes the ESD protection device according to an embodiment.

Referring toFIG.29, the system2000may include a main processor2100, memories (e.g.,2200aand2200b), and storage devices (e.g.,2300aand2300b). In addition, the system2000may include at least one of an image capturing device2410, a user input device2420, a sensor2430, a communication device2440, a display2450, a speaker2460, a power supplying device2470, and a connecting interface2480.

The main processor2100may control all operations of the system2000, more specifically, operations of other components included in the system2000. The main processor2100may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

The main processor2100may include at least one CPU core2110and further include a controller2120configured to control the memories2200aand2200band/or the storage devices2300aand2300b. In some embodiments, the main processor2100may further include an accelerator2130, which is a dedicated circuit for a high-speed data operation, such as an artificial intelligence (AI) data operation. The accelerator2130may include a graphics processing unit (GPU), a neural processing unit (NPU) and/or a data processing unit (DPU) and be implemented as a chip that is physically separate from the other components of the main processor2100.

The memories2200aand2200bmay be used as main memory devices of the system2000. Although each of the memories2200aand2200bmay include a volatile memory, such as static random access memory (SRAM) and/or dynamic RAM (DRAM), each of the memories2200aand2200bmay include non-volatile memory, such as a flash memory, phase-change RAM (PRAM) and/or resistive RAM (RRAM). The memories2200aand2200bmay be implemented in the same package as the main processor2100.

The storage devices2300aand2300bmay serve as non-volatile storage devices configured to store data regardless of whether power is supplied thereto, and have larger storage capacity than the memories2200aand2200b. The storage devices2300aand2300bmay respectively include storage controllers (STRG CTRL)2310aand2310band NVMs (Non-Volatile Memory)2320aand2320bconfigured to store data via the control of the storage controllers2310aand2310b. Although the NVMs2320aand2320bmay include flash memories having a two-dimensional (2D) structure or a three-dimensional (3D) V-NAND structure, the NVMs2320aand2320bmay include other types of NVMs, such as PRAM and/or RRAM.

The storage devices2300aand2300bmay be physically separated from the main processor2100and included in the system2000or implemented in the same package as the main processor2100. In addition, the storage devices2300aand2300bmay have types of solid-state devices (SSDs) or memory cards and may be removably combined with other components of the system2000through an interface, such as the connecting interface2480that will be described below. The storage devices2300aand2300bmay be devices to which a standard protocol, such as a universal flash storage (UFS), an embedded multi-media card (eMMC), or a non-volatile memory express (NVMe), is applied, without being limited thereto.

The image capturing device2410may capture still images or moving images. The image capturing device2410may include, e.g., a camera, a camcorder, and/or a webcam.

The user input device2420may receive various types of data input by a user of the system2000and may include, e.g., a touch pad, a keypad, a keyboard, a mouse, and/or a microphone.

The sensor2430may detect various types of physical quantities, which may be obtained from the outside of the system2000, and convert the detected physical quantities into electric signals. The sensor2430may include, e.g., a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope sensor.

The communication device2440may transmit and receive signals between other devices outside the system2000according to various communication protocols. The communication device2440may include, e.g., an antenna, a transceiver, and/or a modem.

The display2450and the speaker2460may serve as output devices configured to respectively output visual information and auditory information to the user of the system2000.

The power supplying device2470may appropriately convert a power supplied from a battery (not illustrated) embedded in the system2000and/or an external power source to be supplied to each component of the system2000. For example, the power supplying device2470may include at least one power management integrated circuit (PMIC). The power supplying device2470may include the ESD protection device described with reference toFIGS.1to27.

The connecting interface2480may provide the connection between the system2000and an external device, which is connected with the system2000to exchange data with the system2000. The connecting interface2480may be implemented with various interfaces, such as an Advanced Technology Attachment (ATA) interface, a Serial ATA (SATA) interface, an external SATA (e-SATA) interface, a Small Computer System Interface (SCSI) interface, a Serial Attached SCSI (SAS) interface, a Peripheral Component Interconnection (PCI) interface, a PCI express (PCIe) interface, an NVM express (NVMe) interface, an IEEE 1394 interface, an Universal Serial Bus (USB) interface, a Secure Digital (SD) card interface, a Multi-Media Card (MMC) interface, an embedded Multi-Media Card (eMMC) interface, a Universal Flash Storage (UFS) interface, an embedded Universal Flash Storage (eUFS) interface, and a Compact Flash (CF) card interface.

According to an electrostatic discharge protection device of the present disclosure, an ESD current of a high value may be efficiently discharged.