Semiconductive device fabricated using a raised layer to silicide the gate

In one aspect, the invention provides a method of fabricating a semiconductive device 200 that comprises forming a raised layer [510] adjacent a gate [340] and over a source/drain [415], depositing a silicidation layer [915] over the gate [340] and the raised layer [510], and moving at least a portion of the silicidation layer [915] into the source/drain [415] through the raised layer [510].

TECHNICAL FIELD OF THE INVENTION

The invention is directed in general to a semiconductive device, and more specifically, to a semiconductive device fabricated using a raised layer to substantially silicide a gate.

BACKGROUND

Metal gate electrodes are currently being investigated to replace polysilicon gate electrodes in today's ever shrinking and changing transistor devices. One of the principal reasons the industry is investigating replacing the polysilicon gate electrodes with metal gate electrodes is to solve problems of poly-depletion effects and boron penetration for future CMOS devices and to get desirable threshold voltages. Traditionally, a polysilicon gate electrode with an overlying silicide was used for the gate electrodes in CMOS devices. However, as device feature sizes continue to shrink, poly depletion and gate sheet resistance become serious issues when using polysilicon gate electrodes. Accordingly, metal silicided gates have been proposed. In this approach, polysilicon is deposited over the gate. A metal is deposited over the polysilicon and reacted to completely consume the polysilicon, resulting in a fully silicided metal gate, rather than a deposited metal gate.

Complications can arise, however, during the silicidation of the gate electrodes. For example, in some conventional processes, where the gate is silicided before the source/drains are activated, the gates suffer from potential work function drift because of potential degradation of the gate dielectric/gate interface upon exposure to high thermal budgets (e.g., those in excess of 900° C.) that are required to activate the source/drains. When the gate is silicided before the source/drain activation, the high activation temperatures can drive the silicide through the gate dielectric and into the channel region.

To overcome these problems, other processes, where the gate electrodes are silicided after the activation of the source/drain, have been developed. In one such process, two different silicidation steps are performed, with a thicker metal being deposited for the gate electrode and a thinner metal being deposited for the silicidation of the source/drains. Though these processes address the problems associated with those processes where the gate is silicided before the source/drain activation, they require several different process steps. These steps include separately masking the source/drains and the gate electrode to protect them during their respective silicidation processes and using expensive chemical/mechanical polishing processes to remove the masks. These steps not only add cost and time to the manufacturing process, but they do not fully address all of the above-mentioned problems.

Additionally, in other processes, the source/drains are silicided before the gate electrodes. Given the difference in the thickness of the gate electrode and the source/drain junction depth, the silicide in the source/drains is driven deeper to the point of penetrating the source/drain junction during the silicidation of the gate. This can render the device inoperable, or cause shorts or spikes in the device.

Accordingly, what is needed in the art is a silicidation process that avoids the deficiencies of the conventional processes discussed above.

SUMMARY OF INVENTION

To overcome the deficiencies in the prior art, the invention, in one embodiment, provides a method of fabricating a semiconductive device that comprises forming a raised layer adjacent a gate and over a source/drain, depositing a silicidation layer over the gate and the raised layer, and siliciding the raised layer and substantially siliciding the gate with the silicidation layer.

In another embodiment, the invention provides a method of manufacturing a semiconductive device, comprising forming gates with a hardmask located thereover. The gate and the hardmasks are located over a semiconductive substrate. The method further includes forming source/drains adjacent the gates, forming a raised layer adjacent the gates and over the source/drains, removing the hardmask from each of the gates, depositing a silicidation layer over the gates and the raised layer, and siliciding the raised layer and substantially siliciding the gate with the silicidation layer.

DETAILED DESCRIPTION

FIG. 1is one embodiment of a semiconductive device100of the invention. The semiconductive device100may comprise a conventional semiconductive substrate110, such as a wafer. An active region115, which may also be conventional, is located over the substrate110, and includes a well120. The well120may be of conventional design and is typically located adjacent another well that is similarly or complementary doped. Isolation structures125, such as conventional shallow trenches, are also located in the active region115and electrically isolate adjacent wells120. The isolation structures125may be filled with a conventional dielectric material, such as a high density plasma oxide.

The semiconductive device100further includes a transistor130that includes a gate135, a gate oxide140, spacers145, source/drains150and suicide contacts155located over the source/drains150, all of which may be constructed with conventional materials and by conventional processes. The source/drains150may include extensions151that are formed by lightly doped drains (LDDs), and together, they form a junction profile as understood by those skilled in the art. Thus, the depth of the profile will vary. Also included is a silicided raised layer157that is located over the source/drains150. Because of the way in which the silicide contacts155are formed, the gate135can be fully silicided without causing junction penetration by the silicide within the source/drain, thereby avoiding the above-mentioned problems. One method that may be used to manufacture the semiconductive device100is discussed below.

FIG. 2shows the semiconductive device100ofFIG. 1at an early stage of manufacture. The semiconductive device200includes a semiconductive substrate210, such as silicon, silicon-germanium, or gallium arsenide, over which is located an active layer215. The active layer215may be a portion of the substrate210that is appropriately doped, or it may be a conventionally doped epitaxial layer. Wells220and225may be formed within the active layer215and are electrically isolated by isolation structures230. The wells220and225may be similarly doped with conventional p-type or n-type dopants, or they may be oppositely doped to a complementary configuration. A high quality gate oxide layer235is located over the active layer215. A gate layer240, such as a polysilicon layer, and a hardmask layer245, such as silicon nitride or an oxide, are located over the gate oxide layer235. The gate layer240may be doped with a dopant, such as boron, phosphorous, arsenic or another similar dopant, depending on whether the semiconductive device200is operating as a PMOS device or an NMOS device. In one embodiment, the gate layer240may be doped or modified to configure it to the minimum energy required to bring an electron from the Fermi level to the vacuum level or further adjust its work function. The gate layer240may be doped prior to the deposition of the hardmask layer245or at the same time that the source/drains are doped. One who is skilled in the art will understand that various integration schemes can be used to form the source/drains. The thickness of the gate layer240may vary, depending on design. The thickness of the hardmask layer245will also vary, but in most embodiments, it should be thick enough to adequately protect the gate layer240during subsequent process steps.

InFIG. 3, the layers235,240and245have been conventionally patterned to form gate electrodes310that include gate oxides335, gates340and hardmasks345. The semiconductive device200further includes LDDs350that may be conventionally formed. In other embodiments, however, the LDDs350may not be present.

FIG.4illustrates the semiconductive device200ofFIG. 3after the formation of spacers410. The spacers410may also be formed with conventional processes and be comprised of a single deposited material, such as oxide, or it may have a multi-layered configuration. For example, the spacers410may be a combination of oxide, nitride, and oxide. Deep source/drains415may be formed after the formation of the spacers410and, in an alternative embodiment, the formation of the deep source/drains415may be deferred until after the formation of a raised layer, which is discussed below. The source/drains415may be conventionally formed. The spacers410offset the source/drains415from the gates340by the desired distance. The source/drains415are appropriately doped to form a PMOS, NMOS, CMOS device, or combinations thereof.

FIG. 5shows the semiconductive device200ofFIG. 4after the formation of a raised layer510over the source/drains415. In an alternative embodiment, the deep source/drains415may be formed after the formation of the raised layer510. The raised layer510may be formed using conventional processes and, in one embodiment, the layer510may be an epitaxial layer. The raised layer510may be achieved from well-known solid-phase, liquid-phase, vapor-phase or molecular beam deposition processes. One example of a deposition process involves the use of chemical vapor deposition to form the raised layer510. Non-limiting examples of materials that can be used to form the raised layer510include silicon tetrachloride, trichlorosilane, dichlorosilane, silane, silicon, germanium, arsenide, or various combinations of these materials.

The deposition temperatures may range from about 500° C. to about 1000° C. at pressures of approximately 80 Torr. In other embodiments, the deposition parameters will vary from those just stated above, depending on the materials and the deposition process used to form raised layer510. Those who are skilled in the art would understand how to conduct these deposition processes.

One purpose of the raised layer510is to serve as an offset for the silicidation of the gates340so that the gates340can be substantially silicided without penetrating the source/drain415junction. This holds true, even at the source/drains' shallowest points, which includes the source/drains'415extensions that are formed by the above-mentioned LDDs. In certain embodiments, the raised layer510will have a thickness that is less than the thickness of the gates340. For example, in those embodiments where the gates'340thicknesses are 80 nm, the raised layers'510thicknesses will be from about 20 nm to 40 nm less.

In another embodiment, the raised layer510may also function as a raised source/drain or as part of the source/drain415. For example, the raised layer510may be appropriately doped, as indicated. Of course, in those embodiments where it does not serve as the source/drain, the raised layer510will remain undoped. If the formation of the source/drains415has been deferred, then dopants are diffused through the raised layer510and into the active layer215to form the source/drains415. Conventional processes may be used to accomplish this.

The hardmasks345protect the gates340and prevent the formation of the raised layer510directly on the gates340. The raised layer510is, however, able to form on the unprotected silicon located adjacent the gates340, which promotes the formation of the raised layer510over the source/drains415.

The thickness of the raised layer510will vary depending on the diffusion rate of the material that will be used to silicide the gates340and the source/drains415, the temperatures, and other process parameters being used for the silicidation process. For example, the thickness of the layer510may depend on or be a function of the thickness of the gates340. In such embodiments, the layers'510thicknesses should be sufficient to prevent the silicidation from penetrating the shallowest depth of the source/drain415junction, including any extension regions416adjacent the inner edge of the spacer410, during the silicidation of the gates340, and thereby avoid the above-mentioned problems. By way of example only, the silicide should not penetrate greater than 20 nm into the source/drain for 90 nm node technologies. In other embodiments, these depths will vary depending on the size of the node. Typically, the thickness of the gates340will be about 20 nm to 40 nm thicker than the deepest junction point of the source/drain415. Again, these thicknesses are stated for illustrative purposes only, and they will vary depending on the size of the technology involved. In other embodiments, however, the gates'340thicknesses may be less than the deepest junction point of the source/drains415. In such embodiments, the thickness of the raised layer510will be adjusted accordingly.

With the formation of the raised layer510complete, the hardmasks345may be conventionally removed, as shown inFIG. 6. The removal of the hardmasks345exposes the upper surface of the gates340for silicidation.

FIG. 7is the semiconductive device200ofFIG. 6following the deposition of a silicidation layer710. The silicidation layer710is a layer that is used to silicide an underlying layer, and it may be deposited using conventional deposition processes. The silicidation layer710may be any conventional metal, metal alloy or other material that can be used to silicide the gates340. The silicidation layer710is used to further adjust or tune the work function of the gates340, and the type of material used will depend on the desired work function. Non-limiting examples of the types of materials that can be used to silicide the gates340include nickel, cobalt, platinum, tungsten, or various combinations and alloys of these metals.

As mentioned above, the thickness of the silicidation layer710will also vary and depend to some extent on the metal used, the thickness of the gates340, the configuration of the source/drains415junctions, and the silicidation parameters that are used. For example, in one embodiment, the thickness of the gates340may be about 80 nm, while the thickness of the silicidation layer710will be about 60 nm.

In those embodiments where the silicidation layer710is nickel, an exemplary silicide process comprises placing a blanket of nickel over the semiconductive device200. As it takes approximately 1 nm of nickel to fully or substantially silicide approximately 1.8 nm of polysilicon, the thickness of the blanket layer of nickel should be at least about 56% of the thickness of the gates340. To be comfortable, however, it is suggested that the thickness of the layer of nickel should be about at least 60% of the thickness of the gates340. Thus, where the thickness of the gates340ranges from about 50nm to about 150 nm, the thickness of the blanket layer of nickel should range from approximately 30 nm to about 90 nm. In another embodiment, if the PMOS is realized with metal rich silicide, the nickel may be about 1.15 times the gate poly thickness.

Following the deposition of the silicidation layer710, the semiconductive device200inFIG. 8is subjected to a thermal anneal810at a temperature that ranges from about 300° C. to about 450° C. and for a period of time ranging from about 30 seconds to about 60 seconds in those embodiments where the silicidation layer710is nickel. It should be noted, however, that the silicidation process may vary depending on the amount of silicidation that is desired and the materials that are used to silicide the gates340. For example, if the gates340are silicided with a combination of cobalt, titanium, platinum, or erbium then the silicidation process parameters and percentages of materials used will be different than those just stated above. Those who are skilled in the art will understand how to achieve the desired degree of silicidation in these instances.

In one embodiment, anneal810forms a metal rich phase815located in an upper portion of the gates340and in the raised layer510, as illustrated inFIG. 8.FIG. 8also shows how the silicidation layer710has been partially driven into the gate340and substantially through the raised layer510. Depending on the initial thickness of the silicidation layer710, anneal810may leave a portion820of the silicidation layer710remaining over the semiconductive device200. In other embodiments, the silicidation layer710may be fully consumed. The raised layer510initially receives the metal during the above-mentioned anneal. Following anneal810, any portion820of the silicidation layer710that remains is conventionally removed.

After the removal of any remaining portion820, of the silicidation layer710, the semiconductive device200is subjected to another anneal910that, in one embodiment, is conducted at a temperature ranging from about 450° C. to about 550° C. for about 30 seconds. In one aspect, the anneal910forms the silicidation further into the gates340and at least partially through the raised layer510and, in some embodiments, into the source/drains415. It should be understood that the anneal910, in certain embodiments, may not necessarily drive the silicidation layer710into the source/drains415. This will depend on the thickness of the gates340, the metal used and other process parameters.

During the anneal910, the gates340are substantially silicided; that is, at least as much as 60% of the total volume of the gates340will contain a silicide. In another embodiment, however, the gates340may be fully silicided where the silicide is located within just a few (3 to 4) atomic layers distance from or right at the gate dielectric335.

As the anneal910forms the silicide further into the gates340and the source/drains415, the metal rich phase815transforms to a mono-silicide915within the gates340and the source/drains415. As seen inFIG. 9, after silicidation is complete, the silicidation within the source/drains415has not penetrated the junction of the source/drains415at any point.

Though the above-described embodiments present a process that includes two different anneal steps. It should be understood that other embodiments covered by the invention may involve only one anneal step or more than two anneal steps. In such embodiments, the anneal temperature and time is appropriately adjusted to complete the silicidation of the gates340and the source/drains415, as explained above.

FIG. 10is an integrated circuit (IC)1000that incorporates the completed semiconductive device200ofFIG. 9. The semiconductive device200may be configured into a wide variety of devices, such as CMOS devices, BiCMOS devices, Bipolar devices, as well as capacitors or other types of devices. The IC1000may further include passive devices, such as inductors or resistors, or it may also include optical devices or optoelectronic devices. Those skilled in the art are familiar with these various types of devices and their manufacture. The semiconductive device200includes the various components as discussed above, and conventional interconnect structures1010and metal lines1015electrically connect the components of the semiconductive device200to form an operative IC. The interconnect structures1110and metal lines1015may be formed in conventional dielectric layers1020that are located over the semiconductive device200. The number of dielectric layers1020and metal lines1015will vary with design.

From the foregoing, it is seen that the present invention provides a process that is less complex and involves fewer steps that the conventional processes described above. The lessened complexity is at least partially found in the fact that only one metal deposition step is required, which means that fewer masking and removal steps are involved. This reduced complexity results is a more efficient and less costly manufacturing process. Though the raised layer is used in the present invention, it is easily formed by well-known deposition techniques and requires no additional masks since the gates are adequately protected by hardmasks that are blanket deposited and patterned simultaneously with the gate layer. Moreover, the raised layer prevents the silicidation from punching through the source/drain junction and prevents the likelihood of spikes or shorts.

Those skilled in the art to which the invention relates will appreciate that other and further additions, deletions, substitutions, and modifications may be made to the described example embodiments, without departing from the invention.