A digital-to-analog converter is provided. The digital-to-analog converter includes a plurality of digital-to-analog converter cells coupled to an output node of the digital-to-analog converter. At least one of the plurality of digital-to-analog converter cells includes a capacitive element configured to generate an analog cell output signal based on a drive signal. The at least one of the plurality of digital-to-analog converter cells further includes a driver circuit configured to generate the drive signal, and a resistive element exhibiting a resistance of at least 20Ω. The resistive element is coupled between the driver circuit and the capacitive element or between the capacitive element and the output node.

FIELD

The present disclosure relates to digital-to-analog conversion. In particular, examples relate to Digital-to-Analog Converters (DACs), a transmitter, a base station and a mobile device.

BACKGROUND

Modern transmitters use DACs in order to convert digital transmit data to analog signals for radiation to the environment or injection into a waveguide medium such as a cable. The requirements for transmitters are getting tougher with each new communication standard.

DACs use driver circuits such as inverter circuits or logic circuits (e.g. a NAND gate, a NOR gate or combinations thereof) to drive output signals of the individual DAC cells. A driver circuit generally exhibits a non-linear output impedance, which may depend on the data input to the driver circuit. For example, if the driver circuit is implemented in Metal-Oxide-Semiconductor (MOS)-technology, the aspect that the on-resistance of the inverter's NMOS (n-type MOS)-components is not exactly equal to the on-resistance of the inverter's PMOS (p-type MOS)-components may lead to a non-linear output impedance of the driver circuit. Accordingly, a linearity of the DAC may suboptimal.

Hence, there may be a desire for an improved DAC architecture.

DETAILED DESCRIPTION

It will be understood that when an element is referred to as being “connected” or “coupled” to another element, the elements may be directly connected or coupled or via one or more intervening elements. If two elements A and B are combined using an “or”, this is to be understood to disclose all possible combinations, i.e. only A, only B as well as A and B, if not explicitly or implicitly defined otherwise. An alternative wording for the same combinations is “at least one of A and B” or “A and/or B”. The same applies, mutatis mutandis, for combinations of more than two elements.

FIG. 1illustrates an example of a DAC100that may allow to increase the linearity of the DAC. The DAC100comprises a plurality of DAC cells110-1, . . . ,110-N. The plurality of DAC cells110-1, . . . ,110-N may be any number N≥2 of DAC cells (e.g. related to a desired resolution of the DAC). The plurality of DAC cells110-1, . . . ,110-N are coupled to an output node120of the DAC100. Although the proposed DAC cell architecture is described below with respect to the plurality of DAC cells110-1, . . . ,110-N, it is to be noted that the proposed DAC cell architecture may as well be used for a DAC comprising only one DAC cell.

InFIG. 1, two exemplary implementations for at least one of the plurality of DAC cells110-1, . . . ,110-N are illustrated. The two exemplary DAC cells are denoted by reference numerals110-iand110-i′. Any of the plurality of DAC cells110-1, . . . ,110-N may be implemented like one of the DAC cells110-iand110-i′.

Both exemplary DAC cells110-iand110-i′ comprise a capacitive element111configured to generate an analog cell output signal114based on a drive signal115. For example, the capacitive element111may be an on-chip capacitor (e.g. implemented within metal layers or by trenches within a semiconductor substrate). However, the capacitive element111may also be any other suitable means for providing a capacitance. The capacitive element111may, e.g., exhibit a capacitance ranging from a few picofarad to a few attofarad.

The plurality of DAC cells110-1, . . . ,110-N are coupled to the output node120of the DAC100so that their analog cell output signals sum up to an analog output signal of the DAC100.

Further, both exemplary DAC cells110-iand110-i′ comprise a driver circuit112configured to generate the drive signal115for the capacitive element111. For example, the driver circuit112may be an inverter circuit or a logic circuit (e.g. a NAND gate, a NOR gate, any other logic gate, or a combination thereof). In the example ofFIG. 1, the driver circuit112is implemented as an inverter circuit. The driver circuit112is configured to receive a signal, and to invert the signal in order to generate the drive signal115.

The exemplary DAC cells110-iand110-i′ additionally comprise a resistive element113exhibiting a resistance of at least 20Ω. In other words, an element with a high resistance (compared to, e.g., a conductive trace/path coupling the driver circuit112and the capacitive element111or a conductive trace/path coupling the capacitive element111and the output node120) is arranged within the DAC cell downstream of the driver circuit112. The resistive element113is a dedicated physical component that is different from a conductive trace/path coupling the driver circuit112and the capacitive element111or a conductive trace/path coupling the capacitive element111and the output node120.

In DAC cell110-i, the resistive element113is coupled between the driver circuit112and the capacitive element111. In the alternative implementation of DAC cell110-i′, the resistive element113is coupled between the capacitive element111and the output node120of the DAC100.

The resistive element113may allow to desensitize the DAC100with respect to the resistance variations within the driver circuit112. In other words, the resistive element113may reduce the impact of the driver circuit112's non-linear output impedance on the linearity of the DAC100. Accordingly, providing the linear resistive element113in the DAC cells110-iand110-i′ may allow to linearize the output stage of the DAC cells110-iand110-i′.

In some example, the resistance of the resistive element113may be higher than 20Ω. For example, the resistance of the resistive element113may be at least 50Ω, 70Ω, 100Ω, 200Ω, 300Ω 400Ω, 500Ω, 1000Ω, 1500Ω, 2000Ω, 2500Ω, 3000Ω, 3500Ω, 4000Ω, 5000Ω, 6000Ω or 7000Ω. A higher resistance of the resistive element113results in increased linearity of the DAC cells110-iand110-i′. Accordingly, a linearity of the DAC100may be increased by selecting a higher resistance value for the resistive element113.

The resistive element113may be implemented in many different ways. For example, the resistive element113may be a thin film resistor or a polysilicon resistor. In order to accommodate a suitable resistance range (e.g. several ten Ohms to a few kilo-Ohm) in a compact layout footprint, the resistive element113may be made out of a medium to high sheet resistance material (e.g. polysilicon). In other examples, the resistive element113may be a metal resistor (e.g. a meandering shaped metal trace).

In the example ofFIG. 1, n≤N DAC cells out of the plurality of DAC cells110-1, . . . ,110-N may be identical to one of the DAC cells110-iand110-i′. In some examples, all DAC cells of the plurality of DAC cells110-1, . . . ,110-N may be identical to one of the DAC cells110-iand110-i′. In other examples, one or more DAC cells of the plurality of DAC cells110-1, . . . ,110-N may differ from the DAC cells110-iand110-i′ (e.g. comprise additional, less or different elements).

The above described DAC100is a single-ended implementation of the proposed DAC architecture. An example of a differentially implemented DAC according to the proposed architecture is illustrated inFIG. 2.FIG. 2illustrates a DAC200comprising a plurality of DAC cells110-1, . . . ,110-N.

As described above for DAC100, the exemplary DAC cell110-1comprises a (first) capacitive element111configured to generate an (first) analog cell output signal114based on a (first) drive signal115. Further, the DAC cell110-1comprises a (first) driver circuit112configured to generate the drive signal115. A (first) resistive element113exhibiting a resistance of at least 20Ω is coupled between the capacitive element111and a (first) output node120of the DAC200.

Further, the exemplary DAC cell110-1comprises a second capacitive element111′ configured to generate a second analog cell output signal114′ based on a second drive signal115′. The exemplary DAC cell110-1additionally comprises a second driver circuit112′ configured to generate the second drive signal115′. The second drive signal115′ is inverted with respect to the drive signal115. A second resistive element113′ is coupled between the second capacitive element111′ and a second output node130of the DAC200. A resistance of the second resistive element111′ is equal to the resistance of the resistive element111.

In the example ofFIG. 2, the driver circuits112,112′ are implemented as inverter circuits. The driver circuit112is configured to receive a first digital signal101representing digital data, and to invert the first digital signal101in order to generate the drive signal115. Similarly, the driver circuit112′ is configured to receive a second digital signal102representing inverted digital data, and to invert the second digital signal102in order to generate the second drive signal112′. Since the data represented by the first and second digital signals101and102are inverted with respect to each other, the resulting analog cell output signals114and114′ of the DAC cell110-1are inverted with respect to each other.

Since the analog cell output signals114and114′ are inverted with respect to each other, the summed DAC output signals at the output nodes120and130form a differential signal pair.

However, it is to be noted that the implementation of the DAC cell110-1as illustrated inFIG. 2is merely exemplary. The DAC cells of the DAC200may in some examples be implemented different from what is illustrated inFIG. 2(e.g. comprises more, less or other components and/or receive more, less or different signals). For example, the DAC cell110-1may receive a modulated oscillation signal instead of the first digital signal101.

Further illustrated inFIG. 2is a load140coupled the output nodes120and130of the DAC200. In the example ofFIG. 2, the load140is illustrated as a resistor since any load presents an impedance to the DAC200. For example, the load140may be a mixer for up-mixing one or both output signals of the DAC200, a Power Amplifier (PA) for amplifying one or both output signals of the DAC200, a filter for filtering one or both output signals of the DAC200, or an antenna for radiating one or both output signals of the DAC200to the environment.

As described above in connection withFIG. 1, one or more DAC cells of the plurality of DAC cells may be implemented different from the above described DAC cells. For example, a DAC according to the proposed architecture may comprise a first number of thermometer coded DAC cells and a second number of binary coded DAC cells. While the thermometer coded DAC cells all exhibit the same drive strength, the drive strengths of the binary coded DAC cells are only fractions of the thermometer coded DAC cells' drive strength. An example of a binary coded DAC cell310is illustrated inFIG. 3.

It can be seen fromFIG. 3that DAC cell310comprises a capacitive element311, a driver circuit312and a resistive element313like e.g. DAC cell110-idescribed above. It is to be noted that DAC cell310may optional comprise further elements such as a logic circuit described above.

In comparison to DAC cell110-i, DAC cell310additionally comprises a further capacitive element317coupled between a first node318at ground potential and a second node319arranged between the driver circuit312and the capacitive element311.

A summed capacitance of the further capacitive element317and the capacitive element311is equal to a capacitance of the capacitive element111of the DAC cell110-i. In other words, the capacitance of the capacitive element111in the DAC cell110-imay be divided into a wanted capacitance (capacitive element311) and a parasitic capacitance (further capacitive element314) for adjusting a drive strength of the DAC cell310to a fraction of the DAC cell110-i's drive strength. For example, a capacitance of the capacitive element311may be ½, ¼, ⅛, 1/16, 1/32 or 1/64 of the capacitance of the capacitive element111in the DAC cell110-i. Accordingly, a capacitance of the further capacitive element314may be ½, ¾, ⅞, 15/16, 31/32 or 63/64 of the capacitance of the capacitive element111in the DAC cell110-i.

Since the summed capacitance of the further capacitive element317and the capacitive element311is equal to a capacitance of the capacitive element111of the DAC cell110-i, the resistance of the resistive element313of the DAC cell310is equal to the resistance of the resistive element113of the DAC cell110-i.

If the summed capacitance of the further capacitive element317and the capacitive element311is different from a capacitance of the capacitive element111of the DAC cell110-i, a ratio of a resistance of the resistive element313of the DAC cell310to the resistance of the resistive element113of the DAC cell110-imay be equal to a ratio of the capacitance of the capacitive element111of the DAC cell110-ito the summed capacitance of the further capacitive element317and the capacitive element311. In other words, the ratio of resistances in the DAC cells110-iand310may be inversely proportional to the ratio of the summed capacitance of DAC cell310to the single capacitance of DAC cell110-i.

Referring back to DAC100illustrated inFIG. 1, the plurality of DAC cells110-1, . . . ,110-N may, e.g., comprise at least one DAC cell110-ias described above and at least one DAC cell310as described above. For example, DAC100may comprises 1024 thermometer coded DAC cells that are implemented like DAC cell110-iand 6 additional binary coded DAC cells that are implemented like DAC cell310. For example, a respective capacitance of the six capacitive elements311may be ½, ¼, ⅛, 1/16, 1/32 and 1/64 of the individual capacitance of the 1024 capacitive elements111.

Another example of a DAC cell410exhibiting a reduced drive strength compared to DAC cell110-idescribed above is illustrated inFIG. 4.FIG. 4illustrates a comparison between the DAC cells110-iand410.

The DAC cell110-icomprises a driver circuit112coupled to a capacitive element111. A resistive element113is coupled between the driver circuit112and the capacitive element111.

Similarly, the DAC cell410comprises a driver circuit412coupled to a capacitive element411. A resistive element413is coupled between the driver circuit412and the capacitive element411.

The capacitive element111of the DAC cell110-iexhibits a capacitance C. In comparison to the DAC cell110-i, the capacitive element411of the DAC cell410exhibits a capacitance different from the capacitance of the capacitive element111. In the example ofFIG. 4, the capacitance of the capacitive element411is C/2, i.e. half of the capacitance of the capacitive element111. However, it is to be noted that the above values are merely exemplary and do not restrict the proposed architecture (e.g. the capacitance of the capacitive element may be C/4, C/8, C/16, etc. in some examples).

In order to compensate for the different capacitances, also the resistances of the resistive elements113and413are different from each other. In particular, the resistances of the resistive elements113and413may be inversely proportional to the capacitances of the capacitive elements111and411. In the example ofFIG. 4, the resistance of the resistive element413is therefore two time the resistance of the resistive element113. In other words, a ratio of the resistance of the resistive element413of the DAC cell410to the resistance of the resistive element113of the DAC cell110-iis equal to a ratio of the capacitance of the capacitive element111of the DAC cell110-ito the capacitance of the capacitive element411of the DAC cell410.

For example, the DAC cell110-imay be used as a thermometer coded DAC cell and the DAC cell410may be used as a binary coded DAC cell in a DAC according to the proposed architecture.

In the examples described above in connection withFIGS. 1 to 4, a single resistive element is used in the DAC cell for linearizing the output stage of the DAC cell. In the following, three examples using two resistive elements instead of only one will be described in connection withFIGS. 5 to 7.

FIG. 5illustrates another DAC500comprising a plurality of DAC cells510-1, . . . ,510-N. As for the DACs described above, the plurality of DAC cells510-1, . . . ,510-N may be any number N≥2 of DAC cells (e.g. related to a desired resolution of the DAC). The plurality of DAC cells510-1, . . . ,510-N are coupled to an output node520of the DAC500so that their analog cell output signals sum up to an analog output signal of the DAC500. Although the proposed DAC cell architecture is described below with respect to the plurality of DAC cells510-1, . . . ,510-N, it is to be noted that the proposed DAC cell architecture may as well be used for a DAC comprising only one DAC cell.

For illustrative purposes, a DAC cell510-iis illustrated in detail. The DAC cell510-imay be understood to be exemplary for one or more other DAC cells of the plurality of DAC cells510-1, . . . ,510-N.

Like the DAC cells described above in connection withFIGS. 1 to 4, the DAC cell510-icomprises a capacitive element511configured to generate an analog cell output signal514based on a drive signal515. Further, the DAC cell510-icomprises a driver circuit512configured to generate the drive signal515.

Contrary to the DAC cells described above in connection withFIGS. 1 to 4, the DAC cell510-icomprises a first resistive element513-1and a second resistive element513-2, i.e. two resistive elements. The first resistive element513-1is coupled between the driver circuit512and the capacitive element511. The second resistive element513-2is coupled between the capacitive element511and the output node520. The first and the second resistive element exhibit a summed resistance of at least 20Ω. That is, two physical element with a high resistance (compared to, e.g., a conductive trace/path coupling the driver circuit512and the capacitive element511or a conductive trace/path coupling the capacitive element511and the output node520) are arranged within the DAC cell for linearizing the cell output. In other words, the single resistive element used in the DAC cells described above in connection withFIGS. 1 to 4is split up into two separate resistive elements in the example ofFIG. 5. Similar to what is described above, the first resistive element513-1and the second resistive element513-2may allow to linearize the output stage of the DAC cell510-i.

In the example ofFIG. 5, the two resistive elements are arranged outside the driver circuit512. However, in some alternative examples, the two resistive elements may be arranged within the driver circuit512. Two examples for arranging the two resistive elements within the driver circuit512are described in the following with respect toFIGS. 6 and 7.

FIG. 6illustrates a DAC600comprising a plurality of DAC cells510-1, . . . ,510-N like the DAC500. An exemplary DAC cell510-jof DAC600is illustrated. The DAC cell510-jcomprises a capacitive element511configured to generate an analog cell output signal514based on a drive signal515. Further, the DAC cell510-jcomprises a driver circuit512configured to generate the drive signal515.

The driver circuit512(e.g. an inverter or a logic circuit) comprises at least two transistors516and517of different conductivity (e.g. an NMOS and a PMOS FET) serially coupled between a (first node at a) first potential502(e.g. a supply voltage Vdd) and a (second node at a) second potential503(e.g. ground or a supply voltage Vss). An output node518of the driver circuit512for providing the drive signal515is coupled between the at least two transistors516and517. Based on a digital signal501representing digital data, the two transistors516and517selectively couple the output node518of the driver circuit512to either the first potential502or the second potential503in order to generate the drive signal515. It is to be noted that the digital signal501illustrated inFIG. 5is merely exemplary. In some examples, other signals such as a modulated oscillation signal may be provided to the control terminals of the transistors. Further, the wiring of the transistor control terminals illustrated inFIG. 5is merely exemplary. In some examples, different signals may be supplied to the control terminals of the transistors.

The first resistive element513-1is coupled between the output node518of the driver circuit512and the transistor516(i.e. a first one of the at least two transistors516and517). The second resistive element513-2is coupled between the output node518of the driver circuit512and the transistor517(i.e. a second one of the at least two transistors516and517). Each of the first resistive element513-1and the second resistive element513-2exhibits a resistance of at least 20Ω so that first and second resistive elements513-1and513-2exhibit a summed resistance of at least 40Ω.

Similar to the example ofFIG. 5, the arrangement of the two resistive elements513-1and513-2may allow to linearize the impedance of the driver circuit512so that a linearity of the DAC600may be improved.

An alternative arrangement of the two resistive elements513-1and513-2within the driver circuit512is illustrated inFIG. 7.FIG. 7illustrates another exemplary DAC700comprising a plurality of DAC cells510-1, . . . ,510-N DAC like the DAC600. An exemplary DAC cell510-kof DAC700is illustrated. Compared to the DAC cell510-j, the resistive elements are arranged between the transistors and the potentials but not between the transistors and the output node of the driver circuit.

In particular, the first resistive element513-1is coupled between the first potential502and the transistor516(i.e. a first one of the at least two transistors516and517). The second resistive element513-2is coupled between second potential503and the transistor517(i.e. a second one of the at least two transistors516and517). Each of the first resistive element513-1and the second resistive element513-2exhibits a resistance of at least 20Ω so that first and second resistive elements513-1and513-2exhibit a summed resistance of at least 40Ω.

Also the exemplary arrangement of the resistive elements513-1and513-2illustrated inFIG. 7may allow to linearize the impedance of the driver circuit512so that a linearity of the DAC700may be improved.

As indicated inFIGS. 5 to 7, the first and the second resistive element513-1and513-2may exhibit the same resistance. In particular, each of the first and the second resistive element513-1and513-2may exhibit a resistance of at least 10Ω. In other words, each resistive elements513-1and513-2may be a physical component different from a conductive trace/path coupling the driver circuit512and the capacitive element511, a conductive trace/path coupling the capacitive element511and the output node520, or an internal conductive trace/path coupling components of the driver circuit512.

The capacitive element511, the driver circuit512(apart from the arrangement of the resistive elements513-1and513-2with the driver circuit) and the resistive elements513-1and513-2may be implemented substantially similar to what is described above for the capacitive element111, the driver circuit112and the single resistive element113in connection withFIGS. 1 to 4.

For example, the summed resistance of the first and the second resistive element513-1and513-2may be higher than 20Ω. For example, the summed resistance of the first and the second resistive element513-1and513-2may be at least 50Ω, 70Ω, 100Ω, 200Ω, 300Ω 400Ω, 500Ω, 1000Ω, 1500Ω, 2000Ω, 2500Ω, 3000Ω, 3500Ω, 4000Ω, 5000Ω, 6000Ω or 7000Ω. A higher summed resistance of the first and the second resistive element513-1and513-2results in increased linearity of the DAC cells510-i,510-jand510-k. Accordingly, a linearity of the DACs500,600and700may be increased by selecting a resistance values for the resistive elements513-1and513-2.

The resistive elements513-1and513-2may be implemented in many different ways. For example, at least one of the first and the second resistive element513-1and513-2may be a thin film resistor or a polysilicon resistor. In order to accommodate a suitable resistance range (e.g. several ten Ohms to a few kilo-Ohm) in a compact layout footprint, the resistive elements513-1and513-2may be made out of a medium to high sheet resistance material (e.g. polysilicon). In other examples, at least one of the first and the second resistive element513-1and513-2may be a metal resistor (e.g. a meandering shaped metal trace).

In some examples, n≤N DAC cells out of the plurality of DAC cells may be identical to one of the DAC cells510-i,510-jand510-kin the respective DAC500,600or700. For example, all DAC cells of the DAC500,600or700may be identical to one of the DAC cells510-i,510-jand510-k. In other examples, one or more DAC cells of the DAC500,600or700may different from the DAC cells510-i,510-jand510-k(e.g. comprise additional, less or different elements).

Similarly to what is described above in connection withFIG. 3, each of the DACs500,600and700may comprise a first number of thermometer coded DAC cells and a second number of binary coded DAC cells. For example, thermometer coded DAC cells may be implemented like one of the DAC cells510-i,510-jand510-k. In comparison to the DAC cells510-i,510-jand510-k, the one or more other DAC cells used as binary coded DAC cells may, e.g., additionally comprises a further capacitive element coupled between a first node at ground potential and a second node arranged between the driver circuit and the capacitive element of the other DAC cell.

A summed capacitance of the further capacitive element and the capacitive element of the other DAC cell may be equal to a capacitance of the capacitive element511of the DAC cells510-i,510-jor510-k. Accordingly, a summed resistance of the resistive elements of the other DAC cell may be equal to the summed resistance of the resistive elements of the DAC cell510-i, or be half of the summed resistance of the resistive elements of the DAC cell510-jor510-k.

If the summed capacitance of the further capacitive element and the capacitive element of the other DAC cell is different from a capacitance of the capacitive element511of the DAC cell510-i,510-jor510-k, a ratio of a summed resistance of the resistive elements of the other DAC cell to the summed resistance of the resistive elements of the DAC cell510-i,510-jor510-kmay be proportional to a ratio of the capacitance of the capacitive element of the DAC cell510-i,510-jor510-kto the summed capacitance of the further capacitive element and the capacitive element of the other DAC cell. In other words, the ratio of resistances in the DAC cells may be inversely proportional to the ratio of the summed capacitance of the DAC cells.

Similarly to what is described above in connection withFIG. 4, each of the DACs500,600and700may comprise DAC cells comprising only a single capacitive element but with different capacitances. If the capacitive element of another DAC cell exhibits a capacitance different from a capacitance of the capacitive element511of one of the DAC cells510-i,510-jand510-k, the summed resistances of the DAC cells may be inversely proportional to the summed capacitances of the DAC cells. In other words, a ratio of a summed resistance of the resistive elements of the other DAC cell to the summed resistance of the resistive elements of the DAC cell510-i,510-jor510-kmay be proportional to a ratio of the capacitance of the capacitive element of the DAC cell510-i,510-jor510-kto the capacitance of the capacitive element of the other DAC cell.

For example, the DAC cell510-i,510-jor510-kmay be used as a thermometer coded DAC cell and the other DAC cell may be used as a binary coded DAC cell in a DAC according to the proposed architecture.

The exemplary DACs500,600and700described above in connection withFIGS. 5 to 7are single-ended DAC implementations. According to the proposed architecture, the DACs500,600and700may optionally be implemented differentially. If implemented differentially, the respective DAC cell510-i,510-jor510-kmay further comprise a second capacitive element configured to generate a second analog cell output signal based on a second drive signal, and a second driver circuit configured to generate the second drive signal. The second drive signal is inverted with respect to the drive signal. Further, the respective DAC cell510-i,510-jor510-kmay comprise a third and a fourth resistive element exhibiting the same summed resistance as the first and the second resistive element.

In the differential DAC cell510-i, the third resistive element may be coupled between the second driver circuit and the second capacitive element, and the fourth resistive element may be coupled between the second capacitive element and a second output node of the DAC.

In the differential DAC cell510-j, the second driver circuit may comprise at least two transistors (of different conductivity) serially coupled between the first potential and the second potential. An output node of the second driver circuit may be coupled between the at least two transistors of the second driver circuit. Accordingly, the third resistive element may be coupled between the output node of the second driver circuit and the first one of the at least two transistors of the second driver circuit. The fourth resistive element may be coupled between the output node of the second driver circuit and the second one of the at least two transistors of the second driver circuit.

In the differential DAC cell510-k, the third resistive element may be coupled between the first potential and a first one of the at least two transistors of the second driver circuit, and the fourth resistive element may be coupled between the second potential and a second one of the at least two transistors of the second driver circuit.

Accordingly, a differential pair of analog output signals with high linearity may be generated at the DAC output nodes.

An example of an implementation using a DAC according to one or more aspects of the architecture described above or one or more examples described above is illustrated inFIG. 8.FIG. 8schematically illustrates an example of a radio base station800(e.g. for a femtocell, a picocell, a microcell or a macrocell) comprising a DAC820as proposed.

The DAC820is part of a transmitter810. The transmitter810additionally comprises digital circuitry830(e.g. a Digital Signal Processor, DSP) configured to supply digital data as input to the DAC820. For example, the digital circuitry830may be configured to generate the digital data based on data to be wirelessly transmitted.

Further, the base station800comprises at least one antenna element850coupled to the transmitter810for radiating one or more Radio Frequency (RF) transmit signals that are based on the DAC output to the environment. For example, the DAC820may be coupled to the antenna element850via one or more intermediate elements such as a filter, an up-converter (mixer) or a PA.

Additionally, the base station800comprises a receiver840configured to receive a RF receive signal from the antenna element850or another antenna element (not illustrated) of the base station800.

To this end, a base station enabling direct generation of an RF transmit signal with improved Adjacent Channel Leakage Ratio (ACLR) and low Error Vector Magnitude (EVM) may be provided.

The base station800may comprise further elements such as, e.g., a baseband processor, an application processor, memory, a network controller, a user interface, power management circuitry, a satellite navigation receiver, a network interface controller or power tee circuitry.

In some aspects, the application processor may include one or more Central Processing Unit (CPU) cores and one or more of cache memory, a Low-DropOut (LDO) voltage regulator, interrupt controllers, serial interfaces such as Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I2C) or universal programmable serial interface module, Real Time Clock (RTC), timer-counters including interval and watchdog timers, general purpose Input-Output (IO), memory card controllers such as Secure Digital (SD)/MultiMedia Card (MMC) or similar, Universal Serial Bus (USB) interfaces, Mobile Industry Processor Interface Alliance (MIPI) interfaces and Joint Test Access Group (JTAG) test access ports.

In some aspects, the memory may include one or more of volatile memory including Dynamic Random Access Memory (DRAM) and/or Synchronous Dynamic Random Access Memory (SDRAM), and Non-Volatile Memory (NVM) including high-speed electrically erasable memory (commonly referred to as Flash memory), Phase change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM) and/or a three-dimensional crosspoint (3D XPoint) memory. The memory may be implemented as one or more of solder down packaged integrated circuits, socketed memory modules and plug-in memory cards.

In some aspects, the power management integrated circuitry may include one or more of voltage regulators, surge protectors, power alarm detection circuitry and one or more backup power sources such as a battery or capacitor. Power alarm detection circuitry may detect one or more of brown out (under-voltage) and surge (over-voltage) conditions.

In some aspects, the power tee circuitry may provide for electrical power drawn from a network cable to provide both power supply and data connectivity to the base station using a single cable.

In some aspects, the network controller may provide connectivity to a network using a standard network interface protocol such as Ethernet. Network connectivity may be provided using a physical connection which is one of electrical (commonly referred to as copper interconnect), optical or wireless.

In some aspects, the satellite navigation receiver module may include circuitry to receive and decode signals transmitted by one or more navigation satellite constellations such as the Global Positioning System (GPS), GLObalnaya NAvigatSionnaya Sputnikovaya Sistema (GLONASS), Galileo and/or BeiDou. The receiver may provide data to the application processor which may include one or more of position data or time data. The application processor may use time data to synchronize operations with other radio base stations.

In some aspects, the user interface may include one or more of physical or virtual buttons, such as a reset button, one or more indicators such as Light Emitting Diodes (LEDs) and a display screen.

Another example of an implementation using a DAC according to one or more aspects of the architecture described above or one or more examples described above is illustrated inFIG. 9.FIG. 9schematically illustrates an example of a mobile device900(e.g. mobile phone, smartphone, tablet-computer, or laptop) comprising a DAC920as proposed.

The DAC920is part of a transmitter910. The transmitter910additionally comprises digital circuitry930(e.g. a DSP) configured to supply digital data as input to the DAC920. For example, the digital circuitry930may be configured to generate the digital data based on data to be wirelessly transmitted.

Further, the mobile device900comprises at least one antenna element950coupled to the transmitter910for radiating one or more RF transmit signals that are based on the DAC output to the environment. For example, the DAC920may be coupled to the antenna element950via one or more intermediate elements such as a filter, an up-converter (mixer) or a PA.

Additionally, the mobile device900comprises a receiver940configured to receive a RF receive signal from the antenna element950or another antenna element (not illustrated) of the mobile device900.

To this end, a mobile device enabling direct generation of an RF transmit signal with improved ACLR and low EVM may be provided.

The mobile device900may comprise further elements such as, e.g., a baseband processor, memory, a connectivity module, a Near Field Communication (NFC) controller, an audio driver, a camera driver, a touch screen, a display driver, sensors, removable memory, a power management integrated circuit or a smart battery.

In some aspects, the application processor may include, for example, one or more CPU cores and one or more of cache memory, LDO regulators, interrupt controllers, serial interfaces such as SPI, I2C or universal programmable serial interface module, RTC, timer-counters including interval and watchdog timers, general purpose input-output (TO), memory card controllers such as SD/MMC or similar, USB interfaces, MIPI interfaces and JTAG test access ports.

In some aspects, the baseband module may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, and/or a multi-chip module containing two or more integrated circuits.

The wireless communication circuits using digital-to-analog conversion according to the proposed architecture or one or more of the examples described above may be configured to operate according to one of the 3GPP-standardized mobile communication networks or systems. The mobile or wireless communication system may correspond to, for example, a 5thGeneration New Radio (5G NR), a Long-Term Evolution (LTE), an LTE-Advanced (LTE-A), High Speed Packet Access (HSPA), a Universal Mobile Telecommunication System (UMTS) or a UMTS Terrestrial Radio Access Network (UTRAN), an evolved-UTRAN (e-UTRAN), a Global System for Mobile communication (GSM), an Enhanced Data rates for GSM Evolution (EDGE) network, or a GSM/EDGE Radio Access Network (GERAN). Alternatively, the wireless communication circuits may be configured to operate according to mobile communication networks with different standards, for example, a Worldwide Inter-operability for Microwave Access (WIMAX) network IEEE 802.16 or Wireless Local Area Network (WLAN) IEEE 802.11, generally an Orthogonal Frequency Division Multiple Access (OFDMA) network, a Time Division Multiple Access (TDMA) network, a Code Division Multiple Access (CDMA) network, a Wideband-CDMA (WCDMA) network, a Frequency Division Multiple Access (FDMA) network, a Spatial Division Multiple Access (SDMA) network, etc.

The examples described herein may be summarized as follows:

Example 1 is a DAC comprising a plurality of DAC cells coupled to an output node of the DAC, wherein at least one of the plurality of DAC cells comprises: a capacitive element configured to generate an analog cell output signal based on a drive signal; a driver circuit configured to generate the drive signal; and a resistive element exhibiting a resistance of at least 20Ω, wherein the resistive element is coupled between the driver circuit and the capacitive element or between the capacitive element and the output node.

Example 2 is the DAC of example 1, wherein the resistance of the resistive element is at least 100Ω.

Example 3 is the DAC of example 1 or example 2, wherein the resistive element is a thin film resistor.

Example 4 is the DAC of example 1 or example 2, wherein the resistive element is a polysilicon resistor.

Example 5 is the DAC of example 1 or example 2, wherein the resistive element is a metal resistor.

Example 6 is the DAC of any of examples 1 to 5, wherein the at least one of the plurality of DAC cells further comprises: a second capacitive element configured to generate a second analog cell output signal based on a second drive signal; a second driver circuit configured to generate the second drive signal, wherein the second drive signal is inverted with respect to the drive signal; and a second resistive element coupled between the second driver circuit and the second capacitive element or between the second capacitive element and a second output node of the DAC, wherein a resistance of the second resistive element is equal to the resistance of the resistive element.

Example 7 is the DAC of any of examples 1 to 6, wherein in comparison to the at least one of the plurality of DAC cells another one of the plurality of DAC cells additionally comprises: a further capacitive element coupled between a first node at ground potential and a second node arranged between the driver circuit and the capacitive element of the other one of the plurality of DAC cells, wherein a summed capacitance of the further capacitive element and the capacitive element of the other one of the plurality of DAC cells is equal to a capacitance of the capacitive element of the at least one of the plurality of DAC cells.

Example 8 is the DAC of example 7, wherein the resistance of the resistive element of the other one of the plurality of DAC cells is equal to the resistance of the resistive element of the at least one of the plurality of DAC cells.

Example 9 is the DAC of any of examples 1 to 6, wherein, in comparison to the at least one of the plurality of digital-to-analog converter cells, the capacitive element of another one of the plurality of DAC cells exhibits a capacitance different from a capacitance of the capacitive element of the at least one of the plurality of DAC cells, and wherein a ratio of a resistance of the resistive element of the other one of the plurality of DAC cells to the resistance of the resistive element of the at least one of the plurality of DAC cells is equal to a ratio of the capacitance of the capacitive element of the at least one of the plurality of DAC cells to the capacitance of the capacitive element of the other one of the plurality of DAC cells.

Example 10 is a DAC comprising a plurality of DAC cells coupled to an output node of the DAC, wherein at least one of the plurality of DAC cells comprises: a capacitive element configured to generate an analog cell output signal based on a drive signal; a driver circuit configured to generate the drive signal; and a first and a second resistive element exhibiting a summed resistance of at least 20Ω, wherein: the first resistive element is coupled between the driver circuit and the capacitive element, and the second resistive element is coupled between the capacitive element and the output node; or the driver circuit comprises at least two transistors serially coupled between a first potential and a second potential, the first resistive element is coupled between the first potential and a first one of the at least two transistors, and the second resistive element is coupled between the second potential and a second one of the at least two transistors; or an output node of the driver circuit is coupled between the at least two transistors, the first resistive element is coupled between the output node of the driver circuit and the first one of the at least two transistors, and the second resistive element is coupled between the output node of the driver circuit and the second one of the at least two transistors.

Example 11 is the DAC of example 10, wherein each of the first and the second resistive element exhibits a resistance of at least 10Ω.

Example 12 is the DAC of example 10 or example 11, wherein the first and the second resistive element exhibit the same resistance.

Example 13 is the DAC of any of examples 10 to 12, wherein the summed resistance of the first and the second resistive element is at least 100Ω.

Example 14 is the DAC of any of examples 10 to 13, wherein at least one of the first and the second resistive element is a thin film resistor.

Example 15 is the DAC of any of examples 10 to 13, wherein at least one of the first and the second resistive element is a polysilicon resistor.

Example 16 is the DAC of any of examples 10 to 13, wherein at least one of the first and the second resistive element is a metal resistor.

Example 17 is the DAC of any of examples 10 to 16, wherein the at least one of the plurality of DAC cells further comprises: a second capacitive element configured to generate a second analog cell output signal based on a second drive signal; a second driver circuit configured to generate the second drive signal, wherein the second drive signal is inverted with respect to the drive signal; and a third and a fourth resistive element exhibiting the same summed resistance as the first and the second resistive element, wherein: the third resistive element is coupled between the second driver circuit and the second capacitive element, and the fourth resistive element is coupled between the second capacitive element and a second output node of the DAC; or the second driver circuit comprises at least two transistors serially coupled between the first potential and the second potential, the third resistive element is coupled between the first potential and a first one of the at least two transistors of the second driver circuit, and the fourth resistive element is coupled between the second potential and a second one of the at least two transistors of the second driver circuit; or an output node of the second driver circuit is coupled between the at least two transistors of the second driver circuit, the third resistive element is coupled between the output node of the second driver circuit and the first one of the at least two transistors of the second driver circuit, and the fourth resistive element is coupled between the output node of the second driver circuit and the second one of the at least two transistors of the second driver circuit.

Example 18 is the DAC of any of examples 10 to 17, wherein in comparison to the at least one of the plurality of DAC cells another one of the plurality of DAC cells additionally comprises: a further capacitive element coupled between a first node at ground potential and a second node arranged between the driver circuit and the capacitive element of the other one of the plurality of DAC cells, wherein a summed capacitance of the further capacitive element and the capacitive element of the other one of the plurality of DAC cells is equal to a capacitance of the capacitive element of the at least one of the plurality of DAC cells.

Example 19 is the DAC of example 18, wherein a summed resistance of the resistive elements of the other one of the plurality of DAC cells is equal to the summed resistance of the resistive elements of the at least one of the plurality of DAC cells.

Example 20 is the DAC of any of examples 10 to 17, wherein the capacitive element of another one of the plurality of DAC cells exhibits a capacitance different from a capacitance of the capacitive element of the at least one of the plurality of DAC cells, and wherein a ratio of a summed resistance of the resistive elements of the other one of the plurality of DAC cells to the summed resistance of the resistive elements of the at least one of the plurality of DAC cells is proportional to a ratio of the capacitance of the capacitive element of the at least one of the plurality of DAC cells to the capacitance of the capacitive element of the other one of the plurality of DAC cells.

Example 21 is a transmitter, comprising: a DAC according to any of examples 1 to 20; and digital circuitry configured to supply digital data as input to the DAC.

Example 22 is the transmitter of example 22, wherein the digital circuitry is configured to generate the digital data based on data to be wirelessly transmitted.

Example 23 is a mobile device, comprising: a transmitter according to example 21 or example 22; and at least one antenna element coupled to the transmitter.

Example 24 is the mobile device of example 23, further comprising a receiver configured to receive a radio frequency receive signal from the antenna element.

Example 25 is a base station, comprising: a transmitter according to example 21 or example 22; and at least one antenna element coupled to the transmitter.

Example 26 is the base station of example 25, further comprising a receiver configured to receive a radio frequency receive signal from the antenna element.

The description and drawings merely illustrate the principles of the disclosure. Furthermore, all examples recited herein are principally intended expressly to be only for illustrative purposes to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to furthering the art. All statements herein reciting principles, aspects, and examples of the disclosure, as well as specific examples thereof, are intended to encompass equivalents thereof.