Filament confinement in resistive random access memory

Embodiments disclosed herein include an RRAM cell. The RRAM cell may include a first nanowire electrically connected to a first wordline electrode. The nanowire may include a first sharpened point distal from the first wordline electrode. The RRAM cell may also include a metal contact electrically connected to a bitline electrode and a high-κ dielectric layer directly between the nanowire and the metal contact.

BACKGROUND

The present invention relates generally to the field of semiconductor device fabrication, and more particularly to fabricating a resistive random access memory with a confined filament.

Resistive random-access memory (RRAM) is an emerging non-volatile (NV) random-access memory (RAM). RRAM has potential applications for both classic memory applications and neuromorphic computing.

In an RRAM semiconductor device, a memristor element is sandwiched between two electrodes. Defects such as oxygen vacancies are intentionally introduced in the memristor film, which enable memory cells to be programmed to one of two states: a set state or a reset state. In the set state, the memory cell has a “low” resistance state. In the reset state, the memory cell has a “high” resistance state. The set state and reset state of the memory cell require different threshold voltages to switch the memory cell. The reset threshold voltage is the voltage drop across the memory cell in the reset state that must be overcome to melt the memory cell by ohmic heating. The set threshold voltage is the voltage drop across the memory cell in the set state that must be overcome to melt the memory cell by ohmic heating. The threshold voltage for the memory cell in the reset state is comparatively higher than the threshold voltage for the memory cell in the set state. Therefore, it is possible to apply a program voltage that melts the memory cell in the set state but not in the reset state. Normally when the initial state of the memory cell is the reset state, a reset overwrite occurs when writing to the reset state. Reset overwrite is the process when the initial reset state in the memory cell is melted, cooled, and reprogrammed back to the reset state.

SUMMARY

Aspects of an embodiment of the present invention include a resistive random access memory (RRAM) cell. The RRAM cell may include a first nanowire electrically connected to a first wordline electrode. The nanowire may include a first sharpened point distal from the first wordline electrode. The RRAM cell may also include a metal contact electrically connected to a bitline electrode and a high-κ dielectric layer directly between the nanowire and the metal contact.

Aspects of an embodiment of the present invention include methods of fabricating a resistive random access memory (RRAM) cell. The methods may include forming a vertical fin segment comprising a wire layer between a first sacrificial layer and a second sacrificial layer, recessing lateral ends of the first sacrificial layer and the second sacrificial layer to form recesses, forming an inner spacer in the recesses of the first sacrificial layer and the second sacrificial layer, removing the first sacrificial layer and the second sacrificial layer to expose the wire layer, etching the wire layer to form a first nanowire comprising a first sharpened point and a second nanowire comprising a second sharpened point, forming a high-κ dielectric layer over the first nanowire and the second nanowire, and forming a metal contact, wherein the high-κ dielectric layer is directly between the first nanowire and the metal contact, and directly between the second nanowire and the metal contact.

Aspects of an embodiment of the present invention include a method of fabricating a resistive random access memory (RRAM) cell, where the method includes forming a wire stack comprising a wire layer supported on a first lateral end by a first inner spacer and supported on a second lateral end by a second inner spacer. The wire layer may be exposed in a region between the first inner spacer and the second inner spacer. The methods may also include isotropically etching the wire layer in the region to form a first nanowire and a second nanowire. The etching may be non-reactive to the first inner spacer and the second inner spacer.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings, which show specific examples of embodiments of the invention. These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the described embodiments. The following detailed description is, therefore, not to be taken in a limiting sense, and the included embodiments are defined by the appended claims.

With regard to the fabrication of transistors and integrated circuits, major surface refers to that surface of the semiconductor layer in and about which a plurality of transistors are fabricated, e.g., in a planar process. As used herein, the term “vertical” means substantially orthogonal with respect to the major surface and “horizontal” means substantially parallel to the major surface. Typically, the major surface is along a plane of a monocrystalline silicon layer on which transistor devices are fabricated.

Resistive random access memory (RRAM) semiconductor devices work using filament formation in a medium. Filament formation, however, is often a random process, especially along the edges of the RRAM semiconductor device. These edge effects become more pronounced in smaller RRAM semiconductor devices, and certain formation processes such as reactive ion etch can damage RRAM pillar sidewalls as the cell density for the individual devices scales up. Since demand for faster and more efficient circuits continues to increase, however, the RRAM cell density needs to be improved in the available area inside the chip. The density of RRAM arrays may be increased by improving the capability of controlling the location of filamentation during the formation process. Therefore, this invention provides a structure of, and a method for forming, RRAM cells with a nanowire that has a sharpened point that enables increased density due to a more confined filament formation, and a more direct signal flow through the RRAM cell.

Turning now to the figures,FIG.1depicts a cross-sectional side view of an RRAM cell100at a stage of the fabrication process, in accordance with one embodiment of the present invention. The RRAM cell100has a substrate102that may include unillustrated semiconductor devices such as transistors for logic operations, isolations structures, or contacts. The substrate102may also include just a monocrystalline silicon layer as is commonly used in semiconductor fabrication. In certain embodiments, the semiconductor substrate includes a semiconductor material including, but not limited to, silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), Si:C (carbon doped silicon), silicon germanium carbide (SiGeC), carbon doped silicon germanium (SiGe:C), II-V compound semiconductor or another like semiconductor. In addition, multiple layers of the semiconductor materials can be used as the semiconductor material of the substrate. The semiconductor substrate can be a bulk substrate or a semiconductor-on-insulator substrate such as, but not limited to, a silicon-on-insulator (SOI), silicon-germanium-on-insulator (SGOI) or III-V-on-insulator substrate including a buried insulating layer, such as, for example, a buried oxide or nitride layer. Above the substrate102, the RRAM cell100may include an electrode layer having a first wordline104aand a second wordline104b. The wordlines104a,104bmay be arranged as rows for multiple RRAM cells as a large array fabricated on the substrate102. Between the wordlines104a,104b, the RRAM cell100includes interlayer dielectric material (ILD)106that insulates the wordlines104a,104bfrom each other and from other wordlines. The ILD106may be a non-crystalline solid material such as silicon dioxide (SiO2), undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-κ dielectric layer, a chemical vapor deposition (CVD) low-κ dielectric layer, or any combination thereof. The term “low-κ” as used throughout the present application denotes a dielectric material that has a dielectric constant of less than silicon dioxide.

Above the wordlines104a,104b, the RRAM cell100includes a stack108that includes a first sacrificial layer110, a wire layer112, and a second sacrificial layer114. The sacrificial layers110,114may include silicon oxide or another oxide that is etch selective from the ILD106and the wire layer112. The wire layer112may include, but are not limited to, titanium-based materials (e.g., titanium nitride materials (e.g., TiN)), tantalum-based materials (e.g., tantalum nitride materials (e.g., TaN)), and tungsten-based materials (e.g., that are etch selective from the sacrificial layers110,114. Etch selective, in the context of this description, means that between two materials there exists an etch process (e.g., chemical wet etch) that can etch one of the materials without etching or otherwise degrading the other materials.

FIG.2depicts a top-down view of the RRAM cell100ofFIG.1, with like reference numerals referring to like features and at a subsequent stage of the fabrication process. The stack108is etched to create isolating trenches116and vertical fins118of the stack materials (i.e., the first sacrificial layer110, the wire layer112, and the second sacrificial layer114).FIG.2also indicates, at line A-A, the cross-sectional view of the RRAM cell100inFIG.1and subsequent figures. In embodiments of the present invention, each isolating trench116may be formed by an etching process or a selective etching process that selectively removes the stack108from within the isolating trenches116. In some embodiments, this etching can be performed using an anisotropic etch such as reactive ion etching (RIE). Masking material (not shown) may be applied to the top of the stack108prior to etching each isolating trench116, which resists etching and can be utilized to form the desired shape of the isolating trench116, such as, for example, the shape depicted inFIG.2. In some embodiments, the masking material may be a photoresist which has been patterned using photolithography.

FIG.3depicts a cross-sectional side view of the RRAM cell100ofFIG.1, with like reference numerals of previous figures referring to like features and at a subsequent stage of the fabrication process. The vertical fins118are further etched to form vertical fin segments120with the same three layers: the first sacrificial layer110, the wire layer112, and the second sacrificial layer114. Above the vertical fin segment120, the RRAM cell100may include a mandrel122and spacers124. The spacers124may be formed on opposing sides of the mandrel122, over the vertical fin segment120. The mandrel122may include, but not necessarily limited to, amorphous silicon (a-Si), amorphous carbon, polycrystalline silicon, polycrystalline silicon germanium, amorphous silicon germanium, polycrystalline germanium, and/or amorphous germanium. The spacers124may include materials that are etch selective to the rest of the RRAM cell100. In particular, the spacers124may include at least one material, but is not limited to, insulator materials such as silicon nitride (SixNy), silicon oxynitride (SiON), and/or silicon carbonide nitride (SiCN), and/or oxide materials such as silicon oxide (SiOx).

The mandrel122and spacers124may be formed by known deposition and etching techniques. For example, the mandrel122may be formed using a deposition (e.g., chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), evaporation or spin-on coating) followed by masking (e.g., photolithography) and etching as described above in relation to the formation of the isolation trenches116. The spacers124may be formed using an etch back technique wherein the material of the spacers124is applied as a blanket layer, and then a directional etch removes the more horizontal portions above the mandrel122, wordlines104a,104b, and the ILD106, while the more vertical portions on the lateral sides of the mandrel122are left as illustrated inFIG.3.

FIG.4depicts a top-down view of the RRAM cell100ofFIG.1, with like reference numerals referring to like features and at the stage of the fabrication process illustrated inFIG.3.FIG.4shows that the mandrel122and the spacers124form lengthwise with the wordlines104a,104bsuch that the space between the vertical fin segments120is filled in with the material of the mandrel122and the spacers124.

FIG.5depicts a cross-sectional side view of the RRAM cell100ofFIG.1, with like reference numerals of previous figures referring to like features and at a subsequent stage of the fabrication process. The first sacrificial layer110and the second sacrificial layer114are etched back using an etch process that is etch selective only to the sacrificial layers110,114. The etch back exposes recesses126from a first lateral end128aand a second lateral end128b. The etch process may etch enough of the sacrificial layers110,114that the recesses126expose the mandrel122at an exposure point130.

FIG.6depicts a cross-sectional side view of the RRAM cell100ofFIG.1, with like reference numerals of previous figures referring to like features and at a subsequent stage of the fabrication process. The recesses126are filled with inner spacers132such that the wire layer112is supported on a first lateral end134aby a first inner spacer132aand supported on a second lateral end134bby a second inner spacer132b.

FIG.7depicts a cross-sectional side view of the RRAM cell100ofFIG.1, with like reference numerals of previous figures referring to like features and at a subsequent stage of the fabrication process. The RRAM cell100includes further deposited ILD material136on opposing sides of the vertical fin segments120with the mandrel122and spacers124. The ILD136, the mandrel122, and the spacers124may be planarized so that the RRAM cell100is uniformly flat at a top surface138.

FIG.8depicts a cross-sectional side view of the RRAM cell100ofFIG.1, with like reference numerals of previous figures referring to like features and at a subsequent stage of the fabrication process. The mandrel122, the first sacrificial layer110, and the second sacrificial layer114are selectively etched so that the spacers124, the inner spacers132a,132b, the wire layer112, and the ILD136are not etch, degraded, or otherwise affected. The wire layer112is thus exposed in a region140between the first inner spacer132aand the second inner spacer132b. The region140exposes the wire layer112above and below, as shown inFIG.8, but also around the wire layer112so that a center portion of the wire layer112may contact fluids within the region140.

FIG.9depicts a cross-sectional side view of the RRAM cell100ofFIG.1, with like reference numerals of previous figures referring to like features and at a subsequent stage of the fabrication process. The wire layer112may be etched into two segments with a sharpened shape opposite each other using, e.g., an isotropic etch process. The term “isotropic etch” denotes an etch process that is non-directional. By “non-directional” it is meant that the etch rate is not substantially greater in any one direction in comparison to all of the etch directions. The isotropic etch may be a wet chemical etch or a dry etch. For example, the etchant may be a corrosive liquid or a chemically active ionized gas, such as a plasma. The wire layer112is etched to form a first nanowire144ahaving a first sharpened point146aand a second nanowire144bhaving a second sharpened point146b. The wire layer112may be etched using an isotropic etch such that parts of the wire layer112that are in the middle of the region140are more quickly etched than the parts of the wire layer112that are closer to the inner spacers132a,132b. The quicker etch further from the inner spacers132a,132bmeans that the wire layer112is etched away completely in the center before the remaining nanowires144a,144bare etched much at all. Thus, the first sharpened point146aprotrudes into a first side of the metal contact150, and the second sharpened point146bprotrudes into a second side of the metal contact150opposite the first side.

FIG.10depicts a cross-sectional side view of the RRAM cell100ofFIG.1, with like reference numerals of previous figures referring to like features and at a subsequent stage of the fabrication process. Within the region140(that is now between the first nanowire144aand the second nanowire144b), the RRAM cell100includes a high-κ dielectric layer148and a metal contact150. The high-κ dielectric layer148may be directly between the first nanowire144aand the metal contact150, and directly between the second nanowire144band the metal contact150. Thus, the first sharpened point146aprotrudes into a first side of the metal contact150, and the second sharpened point146aprotrudes into a second side of the metal contact150opposite the first side. The high-κ dielectric layer148may include hafnium oxide. In some embodiments, the high-κ dielectric layer148is a transitional metal oxide. Examples of materials that can be suitable for RRAM dielectric include NiOX, TayOX, TiOX, TayOX, WOX, ZrOX, AlyOX, SrTiOX, and the metal contact150may include any metal or other conductive material. The metal contact may include a stack structure (not shown) of metal nitride (for example, titanium nitride, tantalum nitride, or tungsten nitride), Al-containing alloy (for example, TiAl, TiAlC, TaAl, TaAlC), titanium, tantalum, or a combination including at least one of the foregoing. Specifically, the metal contact can include a stack structure of titanium nitride and TiAlC. The high-κ dielectric layer148may be formed by blanket deposition followed by deposition of the metal contact150. Then, both can be etched back to make room in the region140for a dielectric cap152above the metal contact150.

FIG.11depicts a cross-sectional side view of the RRAM cell100ofFIG.1, with like reference numerals of previous figures referring to like features and at a subsequent stage of the fabrication process. The RRAM cell100may include a first sidewall metal contact154athat electrically connects the first wordline104ato the first nanowire144a, and a second sidewall metal contact154bthat electrically connects the second wordline104bto the second nanowire144b. The sidewall metal contacts154a,154belectrically connect the wordlines104a,104bto the nanowires144a,144bsuch that the sharpened points146a,146bare distal from the wordlines104a,104b. The sidewall metal contacts154a,154btypically include tungsten, but may also include other metals. The sidewall metal contacts154a,154bmay be formed using a self-aligning etch process: utilizing an chemical wash or directed etch that is etch selective to the ILD136, but is not etch selective to the spacers124, inner spacers132a,132b, or the nanowires144a,144b. With this process, the sidewall metal contacts154a,154bdirectly contact the wordlines104a,104band the nanowires144a,144b, enabling an electrical connection unmitigated by material from the ILD136.

FIG.12depicts a cross-sectional side view of the RRAM cell100ofFIG.1, with like reference numerals of previous figures referring to like features and at a subsequent stage of the fabrication process. The RRAM cell100may include sidewall dielectric caps156a,156babove the sidewall metal contacts154a,154b. The sidewall dielectric caps156a,156bmay be fabricated with the same dielectric material as the dielectric cap152, or may be fabricated with different materials with etch selectivity.

FIG.13depicts a top-down see-through view of the RRAM cell100ofFIG.1, with like reference numerals referring to like features and at a subsequent stage of the fabrication process. While unillustrated inFIG.13, the metal contact150, the high-κ dielectric layer148, along with the illustrated spacers124, the dielectric cap152, and the sidewall dielectric caps156a,156bare fabricated initially as strips running parallel and above the wordlines104a,104b.FIG.13shows a fabrication stage at which the spacers124, the metal contact150, the high-κ dielectric layer148, the dielectric cap152, and sidewall dielectric caps156a,156bare etched to separate pairs of nanowires144a,144b. Specifically,FIG.13shows separating structures158that enable each nanowire144to be electrically insulated laterally from all other nanowires144. The separating structures158may be formed of the same material as the ILD136, but may also include different material, or material deposited at a different time. The first nanowires144aare electrically connected to the first wordline104a, but the separating structures158make sure that the nanowires do not short directly to one another through the metal contact150.

FIG.14depicts a cross-sectional side view of the RRAM cell100ofFIG.1, with like reference numerals of previous figures referring to like features and at a subsequent stage of the fabrication process. The RRAM cell100includes a bitline160that replaces the dielectric cap152and runs perpendicularly to the wordlines104to form an array. That is, the wordlines104are the rows of the RRAM circuit while bitlines160are the columns of the RRAM circuit.

Operation of the RRAM cell100involves signals to the wordlines104and the bitlines160. When a set signal is sent to the appropriate combination of first wordline104aand bitline160, then the first nanowire144ais set. Setting of an RRAM cell involves creating filaments162, but in the case of the first nanowire144a, the filament creation is confined to the first sharpened point146a. That is, the sharpened point146aprovides a ready path for the set signal to pass between the first wordline104aand the bitline160, where a filament is created. Additionally, the first sharpened point146aalso provides a ready path for the read signals after the filaments have been created. Similar operation is enabled for the second nanowire144bfor set and read signals between the bitline160and the second wordline104b.FIG.13shows six such nanowires in an array (i.e., three nanowires144afor the first wordline104aand three nanowires144bfor the second wordline104b) but it is known in the art that thousands or millions of RRAM cells100may be fabricated in such an array.

FIG.15depicts a cross-sectional side view of an embodiment of an RRAM cell200, at a fabrication stage of the processing method. The RRAM cell200ofFIG.15may be formed in a manner similar toFIGS.1-6, with a substrate202, wordlines204a,204b, a stack208, inner spacers232a,232b, a mandrel222, and spacers224all formed in a manner described in the first embodiment. In the embodiment described henceforth, however, sidewall metal contacts254a,254bare formed before the mandrel222is etched, and before formation of ILD236. The sidewall metal contacts254may be formed by blanket deposition followed by directed etch back that removes the more horizontal portions above the mandrel222. This leaves metal material along the more vertical portions, as illustrated.

FIG.16depicts a cross-sectional side view of the RRAM cell200ofFIG.15, with like reference numerals of previous figures referring to like features and at a subsequent stage of the fabrication process. The sidewall metal contacts254a,254bare recessed further, and ILD material236is added, after which the RRAM cell200may undergo chemical-mechanical planarization (CMP) so that the ILD236, the mandrel222, and the spacers224are all level. The ILD236may be formed in different ways. For example, the sidewall metal contacts254may be recessed before any ILD236material is deposited. On the other hand, the ILD236may be deposited beside the sidewall metal contacts254followed by etch back of the ILD236and sidewall metal contacts254and a second layer of ILD236. The ILD236, in the illustrated embodiment, takes the place of the sidewall dielectric caps156in the embodiment described above.

FIG.17depicts a cross-sectional side view of the RRAM cell200ofFIG.15, with like reference numerals of previous figures referring to like features and at a subsequent stage of the fabrication process. The mandrel222, and sacrificial layers210,214of the stack208, are removed from a region240between the spacers224and inner spacers232a,232b. Following the removal of the mandrel222and the sacrificial layers210,214, a wire layer212located within the stack208is etched to form nanowires244a,244bwith sharpened points246a,246b, as described above.

FIG.18depicts a cross-sectional side view of the RRAM cell200ofFIG.15, with like reference numerals of previous figures referring to like features and at a subsequent stage of the fabrication process. The RRAM cell200is finished with deposition of a high-κ dielectric layer248and a metal contact250that connect the sharpened points246a,246bwith a bitline260for logical operations in conjunction with the wordlines204a,204b.

As illustrated in a difference betweenFIG.17andFIG.18, one or more of the steps of forming the high-κ dielectric layer248, the metal contact250, and the bitline260may involve CMP, such that the height of the ILD236is shorter than when the nanowires244a,244bwere formed.

The RRAM cell200with ILD236insulation between the sidewall metal contact254and the bitline260operates similarly to the RRAM cell100with the sidewall dielectric caps156. That is, a set signal is sent to the first wordline204aand the bitline260, and the first nanowire244amay be set, creating filaments in the high-κ dielectric layer248. The filaments are confined to an area near the first sharpened point246a. That is, the sharpened point246aprovides a ready path for the set signal to pass between the first wordline204aand the bitline260, and a filament is created. Additionally, the first sharpened point246aalso provides a ready path for the read signals after the filaments have been created. Similar operation is enabled for the second nanowire244bfor set and read signals between the bitline260and the second wordline204b.

The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product.