Arrays of capacitors, methods used in forming integrated circuitry, and methods used in forming an array of capacitors

A method used in forming integrated circuitry comprises forming an array of structures elevationally through a stack comprising first and second materials. The structures project vertically relative to an outermost portion of the first material. Energy is directed onto vertically-projecting portions of the structures and onto the second material in a direction that is angled from vertical and that is along a straight line between immediately-adjacent of the structures to form openings into the second material that are individually between the immediately-adjacent structures along the straight line. Other embodiments, including structure independent of method, are disclosed.

TECHNICAL FIELD

Embodiments disclosed herein pertain to arrays of capacitors, to methods used in forming integrated circuitry, and to methods used in forming an array of capacitors.

BACKGROUND

Memory is one type of integrated circuitry and is used in computer systems for storing data. Memory may be fabricated in one or more arrays of individual memory cells. Memory cells may be written to, or read from, using digitlines (which may also be referred to as bitlines, data lines, or sense lines) and access lines (which may also be referred to as wordlines). The digitlines may conductively interconnect memory cells along columns of the array and the wordlines may conductively interconnect memory cells along rows of the array. Each memory cell may be uniquely addressed through the combination of a digitline and a wordline.

Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time in the absence of power. Non-volatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

A capacitor is another type of electronic component that may be used in a memory cell. A capacitor has two electrical conductors separated by electrically insulating material. Energy as an electric field may be electrostatically stored within such material. Depending on composition of the insulator material, that stored field will be volatile or non-volatile. For example, a capacitor insulator material including only SiO2will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor which has ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarized states and thereby can comprise programmable material of a capacitor and/or memory cell. The polarization state of the ferroelectric material can be changed by application of suitable programming voltages and remains after removal of the programming voltage (at least for a time). Each polarization state has a different charge-stored capacitance from the other, and which ideally can be used to write (i.e., store) and read a memory state without reversing the polarization state until such is desired to be reversed. Less desirable, in some memory having ferroelectric capacitors the act of reading the memory state can reverse the polarization. Accordingly, upon determining the polarization state, a re-write of the memory cell is conducted to put the memory cell into the pre-read state immediately after its determination. Regardless, a memory cell incorporating a ferroelectric capacitor ideally is non-volatile due to the bi-stable characteristics of the ferroelectric material that forms a part of the capacitor. Other programmable materials may be used as a capacitor insulator to render capacitors non-volatile. Regardless, a typical goal in the fabrication of capacitors is to maximize surface area of the capacitor electrodes towards maximizing capacitance of the individual capacitors.

Capacitors and transistors may of course be used in integrated circuitry other than memory circuitry. Further, arrays of structures (circuit-operative or not) other than capacitors and/or transistors can be part of integrated

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Embodiments of the invention encompass methods used in the fabrication of integrated circuitry and arrays of capacitors independent of method of manufacture. Integrated circuitry manufactured in accordance with method embodiments may have any of the attributes as described herein in structure embodiments. First example method embodiments are described with reference toFIGS. 1-14in the fabrication of integrated circuitry comprising an array of capacitors.

Referring toFIGS. 1-3, such show part of a construction10comprising an array or array area12in which capacitors will be fabricated. Construction10comprises a base substrate13having any one or more of conductive/conductor/conducting, semiconductive/semiconductor/semiconducting, or insulative/insulator/insulating (i.e., electrically herein) materials. Various materials have been formed elevationally over base substrate13. Materials may be aside, elevationally inward, or elevationally outward of theFIGS. 1-3-depicted materials. For example, other partially or wholly fabricated components of integrated circuitry may be provided somewhere above, about, or within base substrate13. Control and/or other peripheral circuitry for operating components within an array (e.g., a memory array) may also be fabricated and may or may not be wholly or partially within an array or sub-array. Further, multiple sub-arrays may also be fabricated and operated independently, in tandem, or otherwise relative one another. In this document, a “sub-array” may also be considered as an array.

Access devices15are schematically shown inFIG. 3and may be formed as part of base substrate13. By way of example only, such may comprise field effect transistors for controlling access to individual capacitors, for example in DRAM circuitry where an access device15and a capacitor comprise components of a single memory cell (e.g., a one transistor, one capacitor [1T/1C] memory cell). However, other memory and non-memory circuitry are contemplated and whether existing or yet-to-be-developed. Example base substrate13is shown as comprising insulative material16(e.g., doped and/or undoped silicon dioxide) having conductive vias18extending there-through for electrically coupling an individual access device15to an individual capacitor.

A stack22has been formed vertically outward (e.g., above) of base substrate13and comprises first material24and second material26which in one embodiment and as shown is directly against first material24. Example first material24comprises an insulative material20(e.g., silicon nitride and/or silicon oxynitride) that may have functioned as and/or will function as an etch-stop. Example first material24is also shown as comprising material28(e.g., doped or undoped silicon dioxide and which may be entirely sacrificial), intermediate material30(e.g., silicon nitride) as a horizontal layer within material28, and a material32(e.g., silicon nitride) vertically outward of an upper portion of material28. Example second materials26comprise silicon dioxide, spin-on carbon, silicon oxynitride, and existing or future-developed hard-masking materials. In the first-example-described embodiments, second material26may be sacrificial (e.g., all of it is ultimately removed at least within the array so that it does not comprise a part of the finished integrated circuitry construction).

An array of vertically-elongated first capacitor electrodes34has been formed through stack22. Such may comprise a solid pillar construction as shown or may comprise any other suitable construction, for example being in the form of an upwardly-open container shape (not shown) that may or may not be filled with sacrificial material at this point in processing. An example first capacitor electrode material is titanium nitride. First capacitor electrodes34project vertically relative to an outermost portion of first material24(e.g., from at least an uppermost portion of example material32), for example having some portion29thereof that so projects with an example vertical projecting distance of portion29being 10 to 15 nanometers.

Array12of first capacitor electrodes34may be considered as having respective straight lines38(one being so designated) that are between immediately-adjacent first capacitor electrodes34, with construction10having respective vertical cross-sections that are along straight lines38(e.g., the vertical cross-section that isFIG. 3with respect to the one designated straight line38). Note that the respective straight lines38are not necessarily between immediately-most-proximate first capacitor electrodes34within array12. Regardless, first capacitor electrodes34may be considered as having respective first sides40and respective second sides42in the vertical cross-section.

Referring toFIGS. 4 and 5, energy is directed (e.g., as indicated by arrows44) onto vertically-projecting portions29of first capacitor electrodes34and onto second material26in a direction that is angled from vertical (e.g., angle36) and that is along straight line38between immediately-adjacent first capacitor electrodes34to form openings50into second material26that are individually between immediately-adjacent first capacitor electrodes34along straight line38. In one embodiment and as shown, such directing of energy forms openings50through second material26, and in one such embodiment wherein second material26is directly against first material24, such directing of energy forms openings50to first material24. Alternately, openings50in one embodiment may be formed only partially into second material26(not shown) at least at this point of the processing. Regardless, in one embodiment and as shown, the total number of openings50within array12equals the total number of first capacitor electrodes34in array12.

FIGS. 1-5show an example embodiment wherein second material26does not cover vertically-outermost surfaces35of first capacitor electrodes34at the beginning of said directing of energy onto second material26in the direction that is angled from vertical.FIG. 6shows an alternate example embodiment construction10awherein second material26aof stack22ais covering vertically-outermost surfaces35of first capacitor electrodes34. Like numerals from the first-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “a”. Accordingly, the directing of energy as shown byFIGS. 4 and 5with respect to construction10aofFIG. 6will initially be onto second material26ato expose vertically-outermost surfaces35of first capacitor electrodes34. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

First capacitor electrodes34may be considered as an array of structures34that are formed elevationally through stack22that comprises first material24and second material26. However, embodiments of methods used in forming integrated circuitry may form any other existing or future-developed structures, and whether those structures are sacrificial or remain in a finished circuitry construction and regardless of what material such structures are made of and regardless of whether such structures are circuit-operative in the finished construction of the integrated circuitry. Regardless, in one embodiment and as shown, first capacitor electrodes/structures34are arrayed in a two-dimensional (2D) hexagonal lattice. In another embodiment, the structures are arrayed in a two-dimensional (2D) lattice having a parallelogram unit cell, with the direction that is angled from vertical being along a diagonal of the parallelogram unit cell. Other 2D arrays may be used, and which may have a Bravais lattice (i.e., no gaps or overlaps within the lattice) or have a non-Bravais lattice

In one embodiment and as shown inFIGS. 4 and 5, the directing of energy removes all of second material26from respective first sides40of vertically-projecting portions29in the vertical cross-section that is along straight line38and leaves second material26laterally over respective second sides42of vertically-projecting portions29in the vertical cross-section.

In one embodiment, such directing of energy removes second material26to form openings50at least predominately (i.e., up to and including 100%) by chemical etching of second material26and in one such embodiment which is conducted selectively relative to vertically-projecting portions29of first capacitor electrodes/structures34(e.g., using a directing chemical etching tool using an etch chemistry to anisotropically etch second material26selectively relative to different-composition projecting portions29of first capacitor electrodes/structures34, for example using the Raptor™ and other etching tools available from Applied Materials of Santa Clara, Calif.). In another example, such directing of energy removes second material26to form openings50at least predominately (i.e., up to and including 100%) by non-chemical physical removal of second material26, with one such example being using an ion beam etcher that directs a physically bombarding ion beam onto vertically-projecting portions29of first capacitor electrodes/structures34and onto second material26at such angle from vertical. Regardless, the artisan may select any suitable angle from vertical and that may impact size (e.g., maximum length along straight line38) of openings50.

In one embodiment, material32of first material24comprises an insulative support material that supports vertically-elongated first capacitor electrodes/structures34in a finished construction. In another example embodiment described below, the second material may comprise an insulative support material in the form of material32that provides such function, and which may be in the absence of using any additional second material26there-above. Alternately, embodiments of the invention may not use material32as an insulative support material that supports vertically-elongated first capacitor electrodes/structures in a finished construction.

In one embodiment and after the directing of energy as described above, at least some of first material24is removed to expose sidewalls of first capacitor electrodes/structures34(e.g., the majority of which are below material32). In one such embodiment, the directing of energy has formed second material26with openings50there-through to be a mask56(e.g., second material26in combination with material of first capacitor electrodes/structures34as designated initially inFIG. 5). In one such embodiment, and referring toFIGS. 7 and 8, mask56has been used while etching insulative support material32through openings50in mask56to extend openings50into and through insulative support material32.

In one such embodiment, and referring toFIGS. 9 and 10, the removing of at least some of first material24to expose sidewalls of first capacitor electrodes/structures34comprises etching first material24that is below insulative support material32(e.g., material28) selectively relative to insulative-support material32and first capacitor electrodes/structures34. Such may be conducted isotropically or anisotropicaily. Additionally, and as shown, such might ideally be conducted initially anisotropically to intermediate material30, and then chemistry changed to etch anisotropically through intermediate material30. Where second material26(not shown) is of the same composition as that of material28, such etching may remove all remaining second material26as shown. Regardless, and in one embodiment, all remaining second material26when sacrificial is removed.

In one embodiment, second material26initially comprises a horizontal layer58that is horizontally and vertically continuous within array12(FIG. 2). In one such embodiment, such horizontal layer58is formed to be horizontally and vertically discontinuous by or after said directing of energy, with the example embodiments ofFIGS. 1-5, 7, and 8showing the act of directing such energy forming such horizontal layer58to be horizontally and vertically discontinuous inFIGS. 7-10.

FIGS. 11 and 12show example subsequent processing wherein isotropic etching has been conducted to remove all remaining material28(not shown) to expose more of the sidewalk of first capacitor electrodes/structures34. Intermediate material30when present may also function as an insulative support material that supports vertically-elongated first capacitor electrodes/structures34in a finished construction.

Referring toFIGS. 13 and 14, a capacitor insulator60has been formed over the exposed sidewalls of first capacitor electrodes/structures34(and over insulative support materials32and30when present) and at least one second capacitor electrode62has been formed over capacitor insulator60, thus forming individual capacitors65. In one embodiment and as shown, a single second capacitor electrode62may be formed that is common to all capacitors65within array12.

Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

An example alternate embodiment is described with respect toFIGS. 15 and 16with respect to fabrication of an alternate embodiment construction10b. Like numerals from the above-described embodiment have been used where appropriate, with some construction differences being indicated with the suffix “b”. The alternate example method embodiment does not use example second material26of the first-described embodiments vertically outward of material32. Rather, inFIGS. 15 and 16, first material24may be considered as all material below material32, with material32being considered as the second material and that in one embodiment is directly against the sidewalls of first capacitor electrodes/structures34and in one embodiment with material32being insulative and supporting first capacitor electrodes34in a finished construction of an array of capacitors.FIG. 15corresponds in processing sequence to that ofFIG. 3(prior to the directing of energy at the angle from vertical) andFIG. 16corresponds in processing sequence to that ofFIG. 5(after the directing of energy at the angle from vertical).FIG. 16shows material32bof horizontal layer58bforming a mask56b. Subsequent processing may occur as described above with respect toFIGS. 7-14. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

Embodiments of the invention encompass an array of capacitors independent of method of manufacture. Nevertheless, such an array may have any of the attributes as described herein in method embodiments. Likewise, the above-described method embodiments may incorporate and form any of the attributes described with respect to device embodiments.

In one embodiment, an array of capacitors (e.g.,65) comprises a two-dimensional (2D) array (e.g.,12) of vertically-elongated first capacitor electrodes (e.g.,34). A horizontal layer (e.g.,58,58b) of insulative support material (e.g.,32) is directly against and supports the first capacitor electrodes. The horizontal layer of the insulative support material is horizontally and vertically discontinuous in the two dimensions in the 2D array (e.g., contrary to capacitor insulator60that is horizontally and vertically continuous). A capacitor insulator (e.g.,60) is directly against the horizontally and vertically discontinuous horizontal layer of the insulative support material and is directly against the vertically-elongated first capacitor electrodes. At least one second capacitor electrode (e.g.,62) is directly against the capacitor insulator. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

In one embodiment, an array of capacitors (e.g.,65) comprises a 2D array (e.g.,12) of vertically-elongated first capacitor electrodes (e.g.,34). An uppermost horizontal layer (e.g.,58,58b) of insulative support material (e.g.,32) is directly against and supports the first capacitor electrodes. Openings (e.g.,50) extend vertically through the uppermost horizontal layer of the insulative support material in the 2D array. The openings have total number within the array that equals total number of the vertically-elongated first capacitor electrodes in the 2D array. A capacitor insulator (e.g.,60) is directly against the uppermost horizontal layer of the insulative support material and is directly against the vertically-elongated first capacitor electrodes. At least one second capacitor electrode (e.g.,62) is directly against the capacitor insulator. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

The above processing(s) or construction(s) may be considered as being relative to an array of components formed as or within a single stack or single deck of such components above or as part of an underlying base substrate (albeit, the single stack/deck may have multiple tiers). Control and/or other peripheral circuitry for operating or accessing such components within an array may also be formed anywhere as part of the finished construction, and in some embodiments may be under the array (e.g., CMOS under-array). Regardless, one or more additional such stack(s)/deck(s) may be provided or fabricated above and/or below that shown in the figures or described above. Further, the array(s) of components may be the same or different relative one another in different stacks/decks. Intervening structure may be provided between immediately-vertically-adjacent stacks/decks (e.g., additional circuitry and/or dielectric layers). Also, different stacks/decks may be electrically coupled relative one another. The multiple stacks/decks may be fabricated separately and sequentially (e.g., one atop another), or two or more stacks/decks may be fabricated at essentially the same time.

The assemblies and structures discussed above may be used in integrated circuits/circuitry and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication moderns, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

Further, “directly above”, “directly below”, and “directly under” require at least some lateral overlap (i.e., horizontally) of two stated regions/materials/components relative one another. Also, use of “above” not preceded by “directly” only requires that some portion of the stated region/material/component that is above the other be elevationally outward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components). Analogously, use of “below” and “under” not preceded by “directly” only requires that some portion of the stated region/material/component that is below/under the other be devotionally inward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components).

Any of the materials, regions, and structures described herein may be homogenous or non-homogenous, and regardless may be continuous or discontinuous over any material which such overlie. Where one or more example composition(s) is/are provided for any material, that material may comprise, consist essentially of, or consist of such one or more composition(s). Further, unless otherwise stated, each material may be formed using any suitable existing or future-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implanting being examples.

The composition of any of the conductive/conductor/conducting materials herein may be metal material and/or conductively-doped semiconductive/semiconductor/semiconducting material. “Metal material” is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compound(s).

Herein, “selective” as to etch, etching, removing, removal, depositing, forming, and/or formation is such an act of one stated material relative to another stated material(s) so acted upon at a rate of at least 2:1 by volume. Further, selectively depositing, selectively growing, or selectively forming is depositing, growing, or forming one material relative to another stated material or materials at a rate of at least 2:1 by volume for at least the first 75 Angstroms of depositing, growing, or forming.

Unless otherwise indicated, use of “or” herein encompasses either and both.

CONCLUSION

In some embodiments, a method used in forming integrated circuitry comprises forming an array of structures elevationally through a stack comprising first and second materials. The structures project vertically relative to an outermost portion of the first material. Energy is directed onto vertically-projecting portions of the structures and onto the second material in a direction that is angled from vertical and that is along a straight line between immediately-adjacent of the structures to form openings into the second material that are individually between the immediately-adjacent structures along the straight line.

In some embodiments, a method used in forming an array of capacitors comprise forming an array of vertically-elongated first capacitor electrodes through a stack comprising first and second materials. The first capacitor electrodes project vertically relative to an outermost portion of the first material. Energy is directed onto vertically-projecting portions of the first capacitor electrodes and onto the second material in a direction that is angled from vertical and that is along a straight line between immediately-adjacent of the first capacitor electrodes to form openings through the second material that are individually between the immediately-adjacent first capacitor electrodes along the straight line. Said directing of energy removes all of the second material from respective first sides of the vertically-projecting portions in a vertical cross-section that is along the straight line. Said directing of energy leaves the second material laterally over respective second sides of the vertically projecting portions in the vertical cross-section. After said directing of energy, at least some of the first material is removed to expose sidewalls of the first capacitor electrodes. A capacitor insulator is formed over the exposed sidewalk of the first capacitor electrodes. At least one second capacitor electrode is formed over the capacitor insulator.

In some embodiments, an array of capacitors comprises a two-dimensional (2D) array of vertically-elongated first capacitor electrodes. A horizontal layer of insulative support material is directly against and supports the first capacitor electrodes. The horizontal layer of the insulative support material is horizontally and vertically discontinuous in the two dimensions in the 2D array. A capacitor insulator is directly against the horizontally and vertically discontinuous horizontal layer of the insulative support material and is directly against the vertically-elongated first capacitor electrodes. At least one second capacitor electrode is directly against the capacitor insulator.

In some embodiments, an array of capacitors comprises a two-dimensional (2D) array of vertically-elongated first capacitor electrodes. An uppermost horizontal layer of insulative support material is directly against and supports the first capacitor electrodes. Openings extend vertically through the uppermost horizontal layer of the insulative support material in the 2D array. The openings have total number within the array that equals total number of the vertically-elongated first capacitor electrodes in the 2D array. A capacitor insulator is directly against the uppermost horizontal layer of the insulative support material and is directly against the vertically-elongated first capacitor electrodes. At least one second capacitor electrode is directly against the capacitor insulator.