Stacked wafer-level package device

Wafer-level package devices are described that include multiple die packaged into a single wafer-level package device. In an implementation, a wafer-level package device includes a semiconductor device having at least one electrical interconnection formed therein. At least one semiconductor package device is positioned over the first surface of the semiconductor device. The semiconductor package device includes one or more micro-solder bumps. The wafer-level package device further includes an encapsulation structure disposed over and supported by the semiconductor device for encapsulating the semiconductor package device(s). When the semiconductor package device is positioned over the semiconductor device, each micro-solder bump is connected to a respective electrical interconnection that is formed in the semiconductor device.

BACKGROUND

Multi-media devices, such as smart phones, mobile gaming devices, and so forth, utilize integrated circuitry that furnish various functionalities to multi-media devices. For example, the integrated circuitry may furnish processing functionality, storage functionality, and the like to these multi-media devices. However, multi-media devices continue to have greater functionality that requires a greater amount of integrated circuitry to execute the desired functionality (as well as for storage). For instance, multi-media devices may include multiple apps (e.g., applications) that are designed to perform singular or multiple related specific tasks. Each app requires access and the ability to utilize the circuitry for the apps' desired task.

SUMMARY

Wafer-level packaging techniques are described to allow packaging of multiple die into a single semiconductor package device. In an implementation, a stacked wafer-level package device includes a semiconductor device having at least one electrical interconnection formed therein. At least one semiconductor package device is positioned over the first surface of the semiconductor device. The semiconductor package device(s) include one or more micro-solder bumps. The wafer-level package device further includes an encapsulation structure disposed over and supported by the semiconductor device for encapsulating the semiconductor package device(s). When a semiconductor package device is positioned over the semiconductor device, each of the micro-solder bumps are connected to a respective electrical interconnection that are formed in the semiconductor device. The electrical interconnections provide electrical connectivity between the semiconductor package device and the semiconductor device.

DETAILED DESCRIPTION

Overview

Multi-media devices, such as smart phones, mobile gaming devices, and so forth, include semiconductor devices that employ integrated circuitry to provide functionality to multi-media devices. The multi-media devices may include varying numbers of apps that provide specific functionality and tasks to the multi-media devices. As the number of apps grows, a greater amount of processing functionality and storage functionality provided by the integrated circuitry may be required. However, the greater the number of circuitry may correlate to a greater amount of physical space required in the multi-media devices.

Accordingly, wafer-level packaging techniques are described to allow packaging of multiple die into a single wafer-level package device. The packaging of multiple die into a single wafer-level package device allows for an increased density in a smaller amount of physical space. In an implementation, a wafer-level package device includes a semiconductor device having at least one electrical interconnection formed therein. At least one semiconductor package device is positioned over the first surface of the semiconductor device and includes one or more micro-solder bumps. Thus, the semiconductor device is also configured as a carrier device for the wafer-level package device. The wafer-level package device further includes an encapsulation structure disposed over and supported by the semiconductor device for encapsulating the semiconductor package device(s). When a semiconductor package device is positioned over the semiconductor device, each of the micro-solder bumps are connected to a respective electrical interconnection that are formed in the semiconductor device. The electrical interconnections provide electrical connectivity between the semiconductor package device and the semiconductor device.

In implementations, the wafer-level package device may employ a non-fan-out configuration or a fan-out configuration. With regards to the non-fan-out package configuration, the number of inputs/outputs (I/Os) is directly related to the size of the semiconductor device (e.g., the carrier device). With regards to the fan-out package configuration, the number of I/Os is not a function of the size of the semiconductor device. Thus, a greater number of I/Os may be utilized with the fan-out package configuration.

Example Implementations

FIGS. 1 through 3Dillustrate wafer-level package devices100in accordance with example implementations of the present disclosure. As shown, the wafer-level package devices100include one or more semiconductor package devices102(e.g., individual die package) comprised of a substrate104(e.g., silicon wafer, or the like) and one or more integrated circuits106A formed therein. The integrated circuits106A may be configured in a variety of ways. For example, the integrated circuits106may be comprised of digital circuitry. In another example, the integrated circuits106may be comprised of analog circuitry. The first semiconductor package devices102are encapsulated by a suitable protective packaging material108to minimize damage and/or corrosion to the integrated circuits106A. In one or more implementations, the material108may be ceramic, plastic, epoxy, or the like. The first semiconductor package devices102further include one or more area arrays of contact pads110deployed over a surface109of the semiconductor package device102. The number and configuration of contact pads110may vary depending on the complexity and configuration of the integrated circuits106A, the size and shape of the substrate104, and so forth. The contact pads110provide electrical contacts through which the integrated circuits106A are interconnected to external components such as other semiconductor devices, printed circuit boards, and so forth. The contact pads110may be formed in a dielectric layer111. The dielectric layer111may comprise benzocyclobutene polymer (BCB), Polyimide (PI), Polybenzoxazole (PBO), silicon dioxide (SiO2), and so forth.

One or more micro-solder bumps112are provided to furnish mechanical and/or electrical interconnection between the contact pads110and corresponding electrical interconnections described herein. In one or more implementations, the micro-solder bumps112may be fabricated of a lead-free solder such as a Tin-Silver-Copper (Sn—Ag—Cu) alloy solder (i.e., SAC), a Tin-Silver (Sn—Ag) alloy solder, a Tin-Copper (Sn—Cu) alloy solder, a Cu pillar bump, and so on. However, it is contemplated that Tin-Lead (PbSn) solders may be used. The diameter of the micro-solder bumps112may be about forty (40) micrometers to about two hundred (200) micrometers. The pitch (P1) of the micro-solder bumps112may be about sixty (60) micrometers to about three hundred (300) micrometers.

Bump interfaces114may be applied to the contact pads110of the first semiconductor package devices102to provide a reliable interconnect boundary between the contact pads110and the micro-solder bumps112. For instance, in the device102shown inFIG. 1, the bump interface114comprises under-bump metallization (UBM)116applied to the contact pads110of the first semiconductor package devices102. The UBM116may have a variety of compositions. For example, the UBM116include multiple layers of different metals (e.g., Aluminum (Al), Titanium (Ti), Nickel (Ni), Copper (Cu), etc.) that function as an adhesion layer, a diffusion barrier layer, a solderable layer, an oxidation barrier layer, and so forth. However, other UBM structures are possible.

Viewed together, the micro-solder bumps112and associated bump interfaces114(e.g., UBM116) comprise bump assemblies118that are configured to provide mechanical and/or electrical interconnection of the semiconductor package device102to the printed corresponding electrical interconnections. As illustrated inFIGS. 1 through 3D, the semiconductor package device102may include one or more arrays120of bump assemblies118depending on various design considerations.

As shown inFIG. 1, the wafer-level package device100further includes a semiconductor device122that is comprised of a substrate123. In an implementation, the semiconductor device122functions as a carrier device for the semiconductor package device102. The semiconductor device122may also include one or more integrated circuits106B formed in the substrate123. As described above, the integrated circuits106B may be digital integrated circuits and/or analog integrated circuits. In an implementation, the integrated circuit106B may be of the same type of circuitry as the integrated circuit106A. For instance, the integrated circuit106A and the integrated circuit106B may be digital circuits or analog circuits. In another implementation, the integrated circuit106A and the integrated circuit106B may comprise different types of circuitry. For instance, the integrated circuit106A may be a digital circuit while the integrated circuit106B may be an analog circuit, or vice versa. Therefore, the integrated circuits106A,106B may provide complementary functionality between each other (or other circuitry). The semiconductor device122may be greater in size than the semiconductor device104so as to provide support to the device104during fabrication and device100usage.

The semiconductor device122also includes one or more electrical interconnections124formed in the substrate123(e.g., a portion of a silicon wafer, or the like) and configured to provide electrical connectivity between the first semiconductor package device102and the semiconductor device122. The electrical interconnections124may be configured in a variety of ways. In an implementation, the electrical interconnections124may be micro-through-silicon vias (TSVs)126with a conductive material128(e.g., copper, poly-silicon, etc.) deposited therein. The micro-TSVs126may have an approximate size from about ten (10) micrometers to about fifty (50) micrometers and an approximate depth from about fifty (50) micrometers to about one hundred and fifty (150) micrometers. In another implementation, the electrical interconnections124may be a redistribution layer (RDL) structure130comprised of a thin-film (e.g., aluminum, copper, etc.) rerouting and interconnection system that redistributes electrical interconnections in the devices122. In yet another implementation, the electrical interconnections124may be a combination of the micro-TSVs and the RDL structure130.

As illustrated inFIGS. 1 and 2, the semiconductor package device102is stacked over the semiconductor device122so that the micro-solder bumps112are in contact with the electrical interconnections124of the semiconductor device122. In an implementation, the micro-solder bumps112are in contact with the micro-TSVs126. In another implementation, the micro-solder bumps112are in contact with the RDL structure130. Thus, the integrated circuits106A,106B may communicate with one another and provide greater functionality to the wafer-level package device100.

The device100further includes an encapsulation structure132that encapsulates, at least substantially, the semiconductor package device102and is supported by the semiconductor device122. The encapsulation structure132is configured to encapsulate the semiconductor package device102. The encapsulation structure132may comprise ceramic, plastic, epoxy, or the like. The semiconductor device122includes one or more area arrays of contact pads134deployed over a surface136of the device122. The number and configuration of contact pads134may vary depending on the complexity and configuration of the integrated circuits106B, the size and shape of the substrate123, and so forth. The contact pads134provide electrical contacts through which the integrated circuits106B are interconnected to external components such as other semiconductor devices, printed circuit boards, and so forth.

One or more solder bumps138are provided to furnish mechanical and/or electrical interconnection between the contact pads134and corresponding electrical interconnections described here. In one or more implementations, the solder bumps138may be fabricated of a lead-free solder such as a Tin-Silver-Copper (Sn—Ag—Cu) alloy solder (i.e., SAC), a Tin-Silver (Sn—Ag) alloy solder, a Tin-Copper (Sn—Cu) alloy solder, and so on. However, it is contemplated that Tin-Lead (PbSn) solders may be used. The diameter of the solder bumps138may be about one hundred (100) micrometers to about three hundred and fifty (350) micrometers. The pitch (P2) of the solder bumps138may be about three hundred (300) micrometers to about six hundred and fifty (650) micrometers.

Bump interfaces140may be applied to the contact pads134of the semiconductor devices122to provide a reliable interconnect boundary between the contact pads134and the solder bumps138. For instance, in the semiconductor device122shown inFIG. 1, the bump interface140comprises under-bump metallization (UBM)142applied to the contact pads134of the second semiconductor devices122. The UBM142may have a variety of compositions. For example, the UBM142includes multiple layers of different metals (e.g., Aluminum (Al), Titanium (Ti), Nickel (Ni), Copper (Cu), etc.) that function as an adhesion layer, a diffusion barrier layer, a solderable layer, an oxidation barrier layer, and so forth. However, other UBM structures are possible. In other implementations, the semiconductor devices122may not include solder bumps. Instead, the semiconductor devices122may utilize land grid array surface-mount packaging technologies to interface with other electronic components.

Viewed together, the solder bumps138and associated bump interfaces140(e.g., UBM142) comprise bump assemblies144that are configured to provide mechanical and/or electrical interconnection of the first semiconductor device122to the printed corresponding electrical interconnections. As illustrated inFIGS. 1 through 3D, the semiconductor device122may include one or more arrays146of bump assemblies144depending on various design considerations. The bump assemblies144may be formed proximate to one or more dielectric layers148. The dielectric layers148may be comprised of various materials. For example, the layers148may be benzocyclobutene polymer (BCB), Polyimide (PI), Polybenzoxazole (PBO), silicon dioxide (SiO2), and so forth.

FIG. 1illustrates a wafer-level package device100having a non-fan-out package configuration where the number of inputs/outputs (I/Os) (e.g., number of solder bumps138) is a direct function of the die size of the wafer-level package device100. However,FIG. 2illustrates a wafer-level package device100having a fan-out package configuration where the number of I/Os is not a function of the die size of the wafer-level package device100. The wafer-level package devices100having the fan-out package configuration may be fabricated utilizing suitable embedding processes described below. As shown, the encapsulating structure132extends (EW) beyond the width (DW) of the die (e.g., the width of the semiconductor device122) to allow for a greater number of solder bumps138over the surface136. For instance, solder bumps138may be positioned on the encapsulating structure132portions that extend beyond the semiconductor device122. Thus, bump interfaces140may be formed over the encapsulating structure132portion that extends beyond the width (DW) of the semiconductor device122to provide connectivity to those solder bumps138formed over the encapsulating structure132portions extending beyond the semiconductor device122.

It is understood the size of the semiconductor package device102may vary with respect to the size of the semiconductor device122. For example, the width of the semiconductor package device102may be less than the width of the semiconductor device122. In another example, the width of the semiconductor package device102may be about the same as the width of the semiconductor device122.

WhileFIGS. 1 and 2only illustrate a single semiconductor package device102stacked over the semiconductor device122.FIGS. 3A and 3Billustrate a multiple device stacked configuration. For instance, the wafer-level package device100may include a first semiconductor package device102A stacked over a second semiconductor package device102B, and the second semiconductor package device102B is stacked over the semiconductor device122. In this implementation, the second semiconductor package device102B includes one or more electrical interconnections124formed therein to allow the integrated circuits106A of the first semiconductor device102A to communicate with the integrated circuits106A of the second semiconductor device106B and/or the integrated circuits106B of the semiconductor device122through the micro-solder bumps112of the first semiconductor device102A. In one or more implementations, the electrical interconnections124may be a micro-TSV126, a RDL structure130, combinations of both, or the like.

FIGS. 3C and 3Dillustrate another wafer-level package device100configuration. As illustrated, the first semiconductor package device102A and the second semiconductor package device102B are both stacked over the semiconductor device122in a side-by-side package configuration. Thus, both semiconductor package devices102A,102B may communicate with the semiconductor device122through the electrical interconnections124formed in the device122.

Example Fabrication Processes

FIG. 4illustrates an example process200that employs wafer-level packaging techniques to fabricate wafer-level package devices300having a non-fan-out configuration. As shown, a semiconductor wafer (e.g., substrate) is first processed (Block202) to form integrated circuits therein. The integrated circuits may be configured in a variety of ways. For example, the integrated circuits may be digital integrated circuits, analog integrated circuits, mixed-signal integrated circuits, and so forth. In one or more implementations, front-end-of-line techniques may be utilized to form the integrated circuits in the semiconductor wafer, such as the wafer302illustrated inFIG. 5. One or more electrical interconnections are then formed in the wafer (Block204). The electrical interconnections are configured to provide electrical connectivity between various electrical components, such as integrated circuitry. As shown inFIG. 5, the electrical interconnections304may be micro-through-silicon vias (TSVs)306with a conductive material308(e.g., copper, poly-silicon, etc.) deposited therein. The conductive material308may be deposited through suitable deposition process, such as a copper damascene process, or the like. In one or more implementations, the micro-TSVs306may have an approximate size from about ten (10) micrometers to about fifty (50) micrometers and an approximate depth from about fifty (50) micrometers to about one hundred and fifty (150) micrometers. In another implementation, the electrical interconnections304may be a redistribution (RDL) structure as described above with reference toFIGS. 1 through 3D.

Once the electrical interconnections are formed, one or more semiconductor package devices are positioned over a first surface of the wafer (Block206). As shown inFIG. 6, the semiconductor package devices310include integrated circuits312. The integrated circuits312may also comprise digital circuitry, analog circuitry, mixed-signal circuitry, or the like. The semiconductor package devices310further include protective packaging material314that encapsulates the integrated circuits312to minimize damage and/or corrosion to the integrated circuits312. In one or more implementations, the material314may be ceramic, plastic, epoxy, or the like. The semiconductor package devices310also include one or more micro-solder bumps316, such as the micro-solder bumps112described above with respect toFIGS. 1 through 3D. As shown, the semiconductor package devices310may be positioned over the first surface318of the wafer302so that the micro-solder bumps316may be in contact with the electrical connections304. In an implementation, the electrical interconnections304provide electrical connectivity between the integrated circuits312and the integrated circuits (not shown) formed in the wafer302.

An encapsulation structure is then formed over the first surface of the wafer (Block208). As illustrated inFIG. 7, the encapsulation structure320may be formed over the first surface318so that the structure320at least substantially encapsulates the semiconductor package devices310. In one or more implementations, the encapsulation structure320may be comprised of an encapsulation material deposited over the surface318. In one or more implementations, the structure320may comprise one or more polymers, such as an epoxy material, or the like. The structure320serves to insulate the semiconductor package devices310and to at least substantially keep the devices310in place with respect to the wafer302(and respective semiconductor devices321when wafer302has been singulated).

A second surface of the wafer is then subjected to a backgrinding process (Block210). As shown inFIG. 8, a second surface322of the wafer302is then subjected to a backgrinding process to at least partially expose the electrical interconnections304(e.g., micro-TSVs306, etc.) for further processing steps. Once the electrical interconnections are at least partially exposed, one or more solder bumps are formed over the second surface of the wafer (Block212). A dielectric layer323may first be formed over the surface322. In an implementation, the dielectric layer323may be benzocyclobutene polymer (BCB), Polyimide (PI), Polybenzoxazole (PBO), silicon dioxide (SiO2), and so forth. The solder bumps324may be formed over the second surface322of the wafer302through a suitable reflow process. In one or more implementations, the electrical interconnections304provide electrical connectivity between the integrated circuits312, the integrated circuits formed within the wafer302, and/or the solder bumps324. The solder bumps324may be formed over one or more electrical interconnections326that provide electrical connectivity between the electrical interconnections304and the solder bumps324. In one or more implementations, the electrical interconnections326may comprise bump interfaces, such as bump interfaces140described above with respect toFIGS. 1 through 3D. For example, the bump interfaces may comprise a UBM structure328, or the like. As described above, in some implementations the semiconductor devices321may instead utilize land grid array technology to communicate with other electronic components.

The wafer is then subjected to a singulation process (Block214) to singulate the wafer into one or more individual die. Once the wafer302is singulated (seeFIG. 9), the device300may comprise the semiconductor package device310positioned over the surface318of the singulated portion (e.g., individual die) of the wafer302and at least substantially encapsulated by the material320. The device310may be positioned so that the micro-solder bumps316are in contact with the electrical interconnections304of the device300. The encapsulated semiconductor device310and the singulated portion of the wafer302may be viewed as a stacked chip-scale package (CSP) device having a non-fan-out configuration. It is contemplated that in some implementations the wafer may be singulated prior to depositing of the encapsulation material as described with respect to Block208.

FIG. 10illustrates an example process400that employs wafer-level packaging techniques to fabricate wafer-level package devices500having a fan-out configuration. As shown, a semiconductor wafer (e.g., substrate) is first processed (Block402) to form integrated circuits therein. The integrated circuits may be configured in a variety of ways. For example, the integrated circuits may be digital integrated circuits, analog integrated circuits, mixed-signal integrated circuits, and so forth. In one or more implementations, front-end-of-line techniques may be utilized to form the integrated circuits in the semiconductor wafer, such as the wafer502illustrated inFIG. 11. One or more electrical interconnections are then formed in the wafer (Block404). The electrical interconnections are configured to provide electrical connectivity between various electrical components, such as integrated circuitry. As shown inFIG. 11, the electrical interconnections504may be micro-through-silicon vias (TSVs)506with a conductive material508(e.g., copper, poly-silicon, etc.) deposited therein. The conductive material508may be deposited through suitable deposition process, such as a copper damascene process, or the like. In one or more implementations, the micro-TSVs506may have an approximate size from about ten (10) micrometers to about fifty (50) micrometers and an approximate depth from about fifty (50) micrometers to about one hundred and fifty (150) micrometers. In another implementation, the electrical interconnections504may be a redistribution (RDL) structure as described above with reference toFIGS. 1 through 3D.

Once the electrical interconnections are formed, one or more semiconductor package devices are positioned over a first surface of the wafer (Block406). As shown inFIG. 12, the semiconductor package devices510include integrated circuits512. The integrated circuits512may also comprise digital circuitry, analog circuitry, mixed-signal circuitry, or the like. The semiconductor package devices510further include protective packaging material514that is configured to protect the integrated circuits512from further semiconductor fabrication processes (e.g., protect the integrated circuits512from the encapsulation process described herein) and/or corrosion. In one or more implementations, the protective packaging material514may be ceramic, plastic, epoxy, or the like. The semiconductor package devices510also include one or more micro-solder bumps516, such as the micro-solder bumps112described above with respect toFIGS. 1 through 3D. The semiconductor package devices510may be positioned over the first surface518of the wafer502so that the micro-solder bumps516are in contact with the electrical connections504. In an implementation, the electrical interconnections504provide electrical connectivity between the integrated circuits512and the integrated circuits (not shown) formed in the wafer502.

The wafer is then subjected to a singulation process (Block408) to singulate the wafer into one or more individual die. The individual dies are then positioned over a reconstitution wafer (Block410). As shown inFIG. 13, the individual semiconductor devices520are positioned over the reconstitution wafer522. In one or more implementations, the reconstitution wafer522may be any type of sacrificial wafer, such as a silicon wafer, an organic wafer, or the like.

An encapsulation structure is then formed over a first surface of the wafer (Block412). As shown inFIG. 14, the encapsulation structure524may be formed over the first surface526of the reconstitution wafer522so that the structure524at least substantially encapsulates the semiconductor package devices510. In one or more implementations, the encapsulation structure524may be comprised of an encapsulation material deposited over the surface526. In one or more implementations, the structure524comprises a polymer, such as an epoxy material, or the like. The structure524serves to insulate the semiconductor package devices510and to at least substantially keep the devices510in place with respect to the semiconductor device520.

A reconstitution wafer is then subjected to a backgrinding process (Block414). The reconstitution wafer522and a portion of each semiconductor device520are subjected to a suitable backgrinding process to at least partially expose the electrical interconnections504of each semiconductor device520(seeFIG. 15). Once the electrical interconnections have been at least partially exposed, one or more solder bumps are formed over a surface of the dies (Block416). A dielectric layer527may first be formed over the surface530. In an implementation, the dielectric layer527may be benzocyclobutene polymer (BCB), Polyimide (PI), Polybenzoxazole (PBO), silicon dioxide (SiO2), and so forth. The solder bumps528are formed over the surface530of the semiconductor devices520proximate to the at least partially exposed electrical interconnections504as shown inFIG. 16. The solder bumps528are formed utilizing a suitable reflow process. In one or more implementations, the solder bumps528may be formed over one or more electrical interconnections532that are disposed over the surface530and in the dielectric layer527. As described above, the electrical interconnections532may be bump interfaces, or the like. In one or more implementations, a first solder bump528may be connected to a first electrical interconnection532(e.g., the first electrical interconnection532is dedicated to the first solder bump528), a second solder bump528may be connected to a second electrical interconnection532, a third solder bump528may be connected to a third electrical interconnection532, and so forth.

The encapsulation structure is then subjected to a singulation process (Block418) to singulate the encapsulation structure into individual stacked die (e.g., stacked semiconductor package devices). As shown inFIG. 17, once singulated, the width (EW) of the encapsulation structure524is greater than the width (DW) of the semiconductor device520. This allows the electrical interconnection532to at least partially extend over the encapsulation structure524portion as well (as compared to the device300where the electrical interconnection326can only extend over the width of the semiconductor device321). Thus, this configuration (e.g., fan-out configuration) allows for a greater number of solder bumps528and hence, a greater number of input/outputs (I/Os) for the device500. The device500comprises a stacked CSP device having a fan-out configuration.

CONCLUSION