Three-dimensional memory device with electrically isolated support pillar structures and method of making thereof

A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support openings and first memory openings are formed through the first tier structure. A dielectric material portion providing electrical isolation from the substrate is formed in each first memory openings. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed the first tier structure. Second support openings and second memory openings are formed through the second tier structure above the first support openings and the first memory openings. Memory stack structures are formed in inter-tier openings formed by adjoining the first and second memory openings. The dielectric material portions provide electrical isolation between the substrate and the vertical semiconductor layers formed within support pillar structures to prevent or reduce electrical shorts to the substrate through the support pillar structures.

FIELD

The present disclosure relates generally to the field of three-dimensional memory devices and specifically to three-dimensional memory devices including support pillar structure that are electrically isolated from a substrate and methods of making the same.

BACKGROUND

SUMMARY

According to an aspect of the present disclosure, a three-dimensional memory device is provided, which comprises: a first tier structure comprising a first alternating stack of first insulating layers and first electrically conductive layers and located over a substrate; a second tier structure comprising a second alternating stack of second insulating layers and second electrically conductive layers and located over the first tier structure; a memory opening vertically extending through an entirety of the first tier structure and the second tier structure to a top surface of the substrate; a support opening vertically extending through the entirety of the first tier structure and the second tier structure to the top surface of the substrate and laterally offset from the memory openings; a memory stack structure located within the memory opening and comprising a vertical semiconductor channel that is electrically connected to a horizontal semiconductor channel located within the substrate; and a support pillar structure located within the support opening and comprising a vertical semiconductor layer comprising a same material as the vertical semiconductor channel and a dielectric material portion that electrically isolates the vertical semiconductor layer from the substrate.

According to another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided. A first tier structure is formed over a substrate. The first tier structure comprises a first alternating stack of first insulating layers and first sacrificial material layers. A first support opening and a first memory opening are formed through the first tier structure. A dielectric material portion is formed within the first support opening. A second tier structure comprising a second alternating stack of second insulating layers and second sacrificial material layers is formed over the first tier structure. A second support opening and a second memory opening are formed through the second tier structure. The second support opening overlies the first support opening and the second memory opening overlies the first memory opening. A memory cavity extending through the second memory opening and an upper portion of the first memory opening is formed, while simultaneously forming a support cavity extending through the second support opening and bounded by a top surface of the dielectric material portion. A memory stack structure is formed in the memory cavity while forming a support pillar structure in the support cavity. The memory stack structure comprises a vertical semiconductor channel that is electrically connected to a horizontal semiconductor channel located within the substrate, and the support pillar structure comprises a vertical semiconductor layer comprising a same material as the vertical semiconductor channel electrically isolated from the substrate by the dielectric material portion.

DETAILED DESCRIPTION

As discussed above, the present disclosure is directed to three-dimensional memory devices including support pillar structure that are electrically isolated from a substrate and methods of making the same, the various aspects of which are described below. An embodiment of the disclosure can be employed to form semiconductor devices such as three-dimensional monolithic memory array devices comprising a plurality of NAND memory strings.

The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. Elements with the same reference numeral refer to a same element or a similar element, and are presumed to have the same composition unless explicitly noted otherwise.

As used herein, a first element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, a first element is located “directly on” a second element if there exist a physical contact between a surface of the first element and a surface of the second element.

Referring toFIG. 1, a first exemplary structure according to an embodiment of the present disclosure is illustrated, which can be employed, for example, to fabricate a device structure containing vertical NAND memory devices. The first exemplary structure includes a substrate, which can be a semiconductor substrate (9,10). The substrate can include a substrate semiconductor layer9. The substrate semiconductor layer9maybe a semiconductor wafer or a semiconductor material layer, and can include at least one elemental semiconductor material (e.g., single crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The substrate can have a major surface7, which can be, for example, a topmost surface of the substrate semiconductor layer9. The major surface7can be a semiconductor surface. In one embodiment, the major surface7can be a single crystalline semiconductor surface, such as a single crystalline semiconductor surface.

At least one semiconductor device700for a peripheral circuitry can be formed on a portion of the substrate semiconductor layer9. Optionally, a portion of the substrate semiconductor layer9can be vertically recessed to provide a recessed region, and the at least one semiconductor device700may be formed in the recessed region. Alternatively, an additional semiconductor material may be added to the substrate semiconductor layer9outside a region of the at least one semiconductor device700, for example, by selective epitaxy after formation of the at least one semiconductor device.

The at least one semiconductor device can include, for example, field effect transistors. For example, at least one shallow trench isolation structure120can be formed by etching portions of the substrate semiconductor layer9and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate cap dielectric layer can be formed over the substrate semiconductor layer9, and can be subsequently patterned to form at least one gate structure (150,152,154,158), each of which can include a gate dielectric150, a gate electrode (152,154), and a gate cap dielectric158. The gate electrode (152,154) may include a stack of a first gate electrode portion152and a second gate electrode portion154. At least one gate spacer156can be formed around the at least one gate structure (150,152,154,158) by depositing and anisotropically etching a dielectric liner. Active regions130can be formed in upper portions of the substrate semiconductor layer9, for example, by introducing electrical dopants employing the at least one gate structure (150,152,154,158) as masking structures. Additional masks may be employed as needed.

The active region130can include source regions and drain regions of field effect transistors. A first dielectric liner161and a second dielectric liner171can be optionally formed. Each of the first and second dielectric liners (161,171) can comprise a silicon oxide layer, a silicon nitride layer, and/or a dielectric metal oxide layer. As used herein, silicon oxide includes silicon dioxide as well as non-stoichiometric silicon oxides having more or less than two oxygen atoms for each silicon atoms. Silicon dioxide is preferred. In an illustrative example, the first dielectric liner161can be a silicon oxide layer, and the second dielectric liner171can be a silicon nitride layer. The least one semiconductor device for the peripheral circuitry can contain a driver circuit for memory devices to be subsequently formed, which can include at least one NAND device.

A dielectric material such as silicon oxide can be deposited over the at least one semiconductor device, and can be subsequently planarized to form a planarization dielectric layer170. In one embodiment the planarized top surface of the planarization dielectric layer170can be coplanar with a top surface of the dielectric liners (161,171). Subsequently, the planarization dielectric layer170and the dielectric liners (161,171) can be removed from an area to physically expose a top surface of the substrate semiconductor layer9in regions that do not include the at least one semiconductor device700.

An optional semiconductor material layer10may be formed within, or on top of, the substrate semiconductor layer9by ion implantation of electrical dopants (such as p-type dopants or n-type dopants) and/or by deposition of a single crystalline semiconductor material, for example, by selective epitaxy. The single crystalline semiconductor material of the semiconductor material layer10can be in epitaxial alignment with the single crystalline structure of the substrate semiconductor layer9. Portions of the deposited semiconductor material located above the top surface of the planarization dielectric layer170can be removed, for example, by chemical mechanical planarization (CMP). In this case, the semiconductor material layer10can have a top surface that is coplanar with the top surface of the planarization dielectric layer170.

The region (i.e., area) of the at least one semiconductor device700is herein referred to as a peripheral device region300. The region in which a memory array is subsequently formed is herein referred to as a memory array region100. A contact region200for subsequently forming stepped terraces of electrically conductive layers can be provided between the memory array region100and the peripheral device region300.

Referring toFIGS. 2A and 2B, a gate dielectric layer12can be optionally formed above the semiconductor material layer10and the planarization dielectric layer170. The gate dielectric layer12can include, for example, a silicon oxide layer and/or a dielectric metal oxide layer (such as an aluminum oxide layer and/or a hafnium oxide layer). The thickness of the gate dielectric layer12can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed.

An alternating stack of first material layers and second material layers is subsequently formed. Each first material layer can include a first material, and each second material layer can include a second material that is different from the first material. In one embodiment, the first material layers and the second material layers can be first insulating layers132and first sacrificial material layers142, respectively. In one embodiment, each first insulating layer132can include a first insulating material, and each first sacrificial material layer142can include a first sacrificial material. The alternating stack formed by the first insulating layers132and the first sacrificial material layers142is herein referred to as a first alternating stack (132,142), or a lower alternating stack (132,142). In this case, the stack can include an alternating plurality of first insulating layers132and first sacrificial material layers142. As used herein, a “sacrificial material” refers to a material that is removed during a subsequent processing step.

The first alternating stack (132,142) can include first insulating layers132composed of the first material, and first sacrificial material layers142composed of the second material, which is different from the first material. The first material of the first insulating layers132can be at least one insulating material. Insulating materials that can be employed for the first insulating layers132include, but are not limited to silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides that are commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the first insulating layers132can be silicon oxide.

The first sacrificial material layers142may comprise an insulating material, a semiconductor material, or a conductive material. The second material of the first sacrificial material layers142can be subsequently replaced with electrically conductive electrodes which can function, for example, as control gate electrodes of a vertical NAND device. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polysilicon). In one embodiment, the first sacrificial material layers142can be material layers that comprise silicon nitride or a semiconductor material including at least one of silicon and germanium.

In one embodiment, the first insulating layers132can include silicon oxide, and sacrificial material layers can include silicon nitride sacrificial material layers. The first material of the first insulating layers132can be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is employed for the first insulating layers132, tetraethylorthosilicate (TEOS) can be employed as the precursor material for the CVD process. The second material of the first sacrificial material layers142can be formed, for example, CVD or atomic layer deposition (ALD).

The thicknesses of the first insulating layers132and the first sacrificial material layers142can be in a range from 20 nm to 50 nm, although lesser and greater thicknesses can be employed for each first insulating layer132and for each first sacrificial material layer142. The number of repetitions of the pairs of a first insulating layer132and a first sacrificial material layer142can be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions can also be employed. In one embodiment, each first sacrificial material layer142in the first alternating stack (132,142) can have a uniform thickness that is substantially invariant within each respective first sacrificial material layer142.

A first-tier dielectric cap layer270can be subsequently formed over the first alternating stack (132,142). The first-tier dielectric cap layer270includes a dielectric material that is different from the material of the first sacrificial material layers142. The first-tier dielectric cap layer270includes a dielectric material that may be the same as, or different from, the material of the first insulating layers132. In one embodiment, the first-tier dielectric cap layer270can include silicon oxide. In one embodiment, the thickness of the first-tier dielectric cap layer270can be in a range from 20 nm to 100 nm, although lesser and greater thicknesses can also be employed. The first alternating stack (132,142) and the first dielectric cap layer270collectively constitutes a first tier structure (132,142,270)

The first tier structure (132,142,270) can be patterned to form first stepped surfaces. The first stepped surfaces form a first terrace region, which is located within an area of the contact region200. The contact region200includes a first stepped area in which the first stepped surfaces are formed, and a second stepped area in which additional stepped surfaces are to be subsequently formed in an second tier structure (to be subsequently formed over the first tier structure). The memory array region100is provided adjacent to the contact region200. Memory devices including memory stack structures can be subsequently formed in the memory array region100. The first stepped surfaces can be formed, for example, by forming a mask layer with an opening therein, etching a cavity within the levels of the topmost first sacrificial material layer142and the topmost first insulating layer132, and iteratively expanding the etched area and vertically recessing the cavity by etching each pair of a first insulating layer132and a first sacrificial material layer142located directly underneath the bottom surface of the etched cavity within the etched area. The first-tier dielectric cap layer270and the first alternating stack (132,142) are patterned such that each underlying first sacrificial material layer142laterally protrudes farther than any overlying first sacrificial material layer142in the etched region, and each underlying first insulating layer132laterally protrudes farther than any overlying first insulating layer132in the etched region. The contact region can be a contact region of the first alternating stack (132,142). The cavity is herein referred to as a first stepped cavity.

A dielectric material is deposited to fill the first stepped cavity. Excess portions of the dielectric material overlying the topmost surface of the first alternating stack (132,142), are removed for example, by chemical mechanical planarization. The remaining portion of the deposited dielectric material forms a first dielectric material portion, which is herein referred to as a first retro-stepped dielectric material portion165. The first retro-stepped dielectric material portion165is formed on the first stepped surfaces. The first dielectric material portion165is retro-stepped. As used herein, a “retro-stepped” element refers to an element that has stepped surfaces and a horizontal cross-sectional area that increases monotonically as a function of a vertical distance from a top surface of a substrate on which the element is present. The first tier structure, which is also referred to as a first stack structure, comprises the first alternating stack (132,142) and the first retro-stepped dielectric material portion165. The first retro-stepped dielectric material portion165is incorporated into the first tier structure (132,142,270,165).

Referring toFIGS. 3A and 3B, first openings (121,221) extending to a top surface of the substrate (9,10) are formed through the first tier structure (132,142,270,165). The first openings (121,221) include first memory openings121that are formed in the memory array region100and first support openings221that are formed in the contact region200. The first memory openings121and the first support openings221can be formed concurrently by a patterning process. To form the first openings (121,221), a lithographic material stack (not shown) including at least a photoresist layer can be formed over the first tier structure (132,142,270,165), and can be lithographically patterned to form openings within the lithographic material stack. The pattern in the lithographic material stack can be transferred through the entirety of the first tier structure (132,142,270,165) by at least one anisotropic etch that employs the patterned lithographic material stack as an etch mask. Portions of the first tier structure (132,142,270,165) underlying the openings in the patterned lithographic material stack are etched to form the first openings (121,221). In other words, transfer of the pattern in the patterned lithographic material stack through the first tier structure (132,142,270,165) forms the first openings (121,221).

In one embodiment, the chemistry of the anisotropic etch process employed to etch through the materials of the first alternating stack (132,142) can alternate to optimize etching of the first and second materials in the first alternating stack (132,142) while providing a comparable average etch rate for the first dielectric material portion165. The anisotropic etch can be, for example, a series of reactive ion etches. The sidewalls of the first openings (121,221) can be substantially vertical, or can be tapered. Subsequently, the patterned lithographic material stack can be subsequently removed, for example, by ashing. The first memory openings121and the first support openings221can be formed concurrently employing the same set of anisotropic etch processes.

In one embodiment, the substrate (9,10) can be employed as a stopping layer for the anisotropic etch process. In one embodiment, the first openings (121,221) may extend below the top surface of the substrate (9,10) by an overetch. The lateral dimensions (e.g., a diameter) of the first openings (121,221) can be from about 20 nm to 200 nm at an upper portion of each first opening (121,221), and can be about 10 nm to 150 nm at a lower portion of each first opening (121,221).

In one embodiment, the first memory openings121can be formed as an array of openings, which can be a periodic two-dimensional array of openings. The first support openings221can be formed as discrete openings that are mutually separated from one another, and may, or may not, form a periodic two-dimensional array pattern. In one embodiment, the first support openings221may form a plurality of periodic one-dimensional array patterns that are parallel among one another.

A dielectric liner (not shown) can be optionally formed within the first memory openings121and the first support openings221. For example, a thermal oxidation process, a thermal nitridation process, a plasma oxidation process, and/or a plasma nitridation process can be performed to convert surface portions of the semiconductor material layer10and/or the substrate semiconductor layer9at the bottom of each first memory opening121and each first support opening221to form the dielectric liner. Alternatively, a thin dielectric material layer can be conformally deposited to provide the dielectric liner. The thickness of the dielectric liner can be in a range from 1 nm to 3 nm, although lesser and greater thicknesses can also be employed.

Referring toFIGS. 4A and 4B, a sacrificial fill material can be deposited in the first support openings221and in the first memory openings121simultaneously. The sacrificial fill material can be an insulating material, a semiconducting material, or a conductive material. Non-limiting examples of the sacrificial fill material includes amorphous silicon, polycrystalline silicon, an amorphous silicon-germanium alloy, and a polycrystalline silicon-germanium alloy. In case a semiconductor material is employed, the semiconductor material (such as amorphous silicon) is undoped (i.e., intrinsic). Excess portions of the deposited sacrificial fill material can be removed from above the horizontal plane including the topmost surface of the first tier structure (132,142,270,165). Remaining portions of the deposited sacrificial fill material in the first openings (121,221) are herein referred to as sacrificial fill material portions (122,222).

The sacrificial fill material portions (122,222) include sacrificial memory opening fill material portions122that fill the first memory openings121and sacrificial support opening fill material portions222that fill the first support openings221. A subset of the sacrificial support opening fill material portions222extends through the first retro-stepped dielectric material portion165and the first stepped surfaces on the first alternating stack (132,142). Each instance of the sacrificial support opening fill material portions222can include a material having a composition different from the material of the first insulating layers132and from the material of the first sacrificial material layers142. For example, the sacrificial fill material portions (122,222) can include amorphous silicon, a silicon-germanium alloy, amorphous carbon, an organic polymer, or an inorganic polymer.

Referring toFIGS. 5A and 5B, top regions of the sacrificial fill material portions (122,222) can be optionally removed, for example, by a recess etch that removes the sacrificial fill material of the sacrificial fill material portions (122,222) selective to the material of the first-tier dielectric cap layer270. The recess etch can be an isotropic etch such as a wet etch or an anisotropic etch such as a reactive ion etch. For example, if the sacrificial fill material portions (122,222) include undoped silicon material, a wet etch employing KOH can be employed to recess the undoped semiconductor material of the sacrificial fill material portions (122,222) selective to the material of the first-tier dielectric cap layer270. The duration of the recess etch can be selected such that the recessed top surfaces of the sacrificial fill material portions (122,222) are formed between a first horizontal plane including the top surface of the first-tier dielectric cap layer270and a second horizontal plane including the bottom surface of the first-tier dielectric cap layer270.

Referring toFIGS. 6A-6C, an isotropic etch can be performed to recess the dielectric material of the first-tier dielectric cap layer270selective to the sacrificial fill material of the sacrificial fill material portions (122,222). The volume of each cavity overlying the sacrificial fill material portions (122,222) as recessed can be laterally expanded to increase the horizontal cross-sectional area of each cavity overlying a respective sacrificial fill material portion (122,222). In one embodiment, a concave surface having a uniform curvature with a radius of curvature R can be formed around each sacrificial fill material portions (122,222). A closed bottom periphery of the concave surface can be adjoined to a periphery of a respective sacrificial fill material portion (122or222). A closed top periphery of the concave surface can be adjoined to a substantially cylindrical sidewall of first-tier dielectric cap layer270that extends to the top surface of the first-tier dielectric cap layer270.

Referring toFIGS. 7A and 7B, the sacrificial fill materials of the sacrificial fill material portions (122,222) can be removed by an etch process. An isotropic etch or an anisotropic etch may be performed to remove the materials of the sacrificial fill material portions (122,222) selective to the materials of the first insulating layers132, the first sacrificial material layers142, and the first tier dielectric cap layer270. In case a dielectric liner is formed at the processing steps ofFIGS. 4A and 4B, the dielectric liner can function as an etch stop layer, and the etch process can be selective to the material of the dielectric liner, which can be subsequently removed by an isotropic etch (such as a wet etch). In case the sacrificial fill material portions (122,222) include a semiconductor material such as silicon or a silicon-germanium alloy, a wet etch process employing a KOH solution can be employed to remove the materials of the sacrificial fill material portions (122,222).

Referring toFIGS. 8A and 8B, epitaxial pedestals (11,11′) can be formed at the bottom portion of each first memory opening121and each first support opening221, for example, by selective epitaxy. The epitaxial pedestals (11,11′) include first epitaxial pedestals11that are formed at the bottom of the first memory openings121and second epitaxial pedestals formed at the bottom of the first support openings221. Each epitaxial pedestal (11,11′) comprises a single crystalline semiconductor material in epitaxial alignment with the single crystalline semiconductor material of the semiconductor material layer10or the substrate semiconductor layer9. In one embodiment, the epitaxial pedestal (11,11′) can be doped with electrical dopants of the same conductivity type as the semiconductor material layer10.

In one embodiment, the top surface of each epitaxial pedestal (11,11′) can be formed above a horizontal plane including the top surface of a set of at least one bottommost first sacrificial material layers142. In this case, at least one source select gate electrode can be subsequently formed by replacing each first sacrificial material layer142located below the horizontal plane including the top surfaces of the epitaxial pedestals (11,11′) with a respective conductive material layer in subsequent processing steps. The first epitaxial pedestals11can be a portion of a transistor channel that extends between a source region to be subsequently formed in the substrate (9,10) and a drain region to be subsequently formed in an upper portion of an inter-tier memory opening that includes a first memory opening121at a lower portion thereof. A cavity is present in the unfilled portion of each first memory opening121and in the unfilled portion of each first support opening221above the respective epitaxial pedestal (11,11′).

In one embodiment, each epitaxial pedestal (11,11′) can comprise single crystalline silicon. In one embodiment, each epitaxial pedestal (11,11′) can have a doping of the first conductivity type, which is the same as the conductivity type of the semiconductor material layer10that the epitaxial pedestal contacts. If a semiconductor material layer10is not present, the first epitaxial pedestals11can be formed directly on the substrate semiconductor layer9, which can have a doping of the first conductivity type.

Referring toFIGS. 9A and 9B, a patterned implantation mask layer67is formed over the first exemplary structure to cover the first memory openings121, while not covering the first support openings221. The patterned implantation mask layer67can be a photoresist layer. In this case, the photoresist layer can be applied over the entire top surface of the first exemplary structure, and can be lithographically patterned (by exposure and development) to cover the first memory openings121while not covering the first support openings221.

Ion implantation of dopants is performed into at least upper portions of second epitaxial pedestals11′ but not into the first epitaxial pedestals11because the patterned implantation mask layer67covers the first memory openings121. In one embodiment, the dopants can be p-type electrical dopants (such as boron) or n-type electrical dopants (such as phosphorus or arsenic). The ions can impinge on the second epitaxial pedestals11′ at substantially normal incidence. The dose of the dopants during the ion implantation process can be selected such that the oxidation rate of the implanted region (i.e., a doped upper portion16) of the second epitaxial pedestals11′ is enhanced relative to the oxidation rate of the material of the second epitaxial pedestals11′ prior to ion implantation. For example, the atomic concentration of the electrical dopants in the implanted regions of the second epitaxial pedestals11′ can be in a range from 5.0×1019/cm3to 2.0×1021/cm3, although lesser and greater atomic concentrations of the electrical dopants can also be employed. Subsequently, the patterned implantation mask layer67can be removed, for example, by ashing.

Referring toFIGS. 10A and 10B, an oxidation process is performed to covert surface portions of each epitaxial pedestal (11,11′) into semiconductor oxide portions (21,21′). A thermal oxidation process or a plasma oxidation process can be employed to form the semiconductor oxide portions (21,21′). The semiconductor oxide portions (21,21′) include first semiconductor oxide portions21that are formed by conversion of an upper portion of the first epitaxial pedestals11into a semiconductor oxide material (such as silicon oxide), and second semiconductor oxide portions21′ that are formed by conversion of the doped upper portion16of the second epitaxial pedestals11′ into another semiconductor oxide material (such as doped or undoped silicon oxide).

The electrical dopants present in the upper portion of each second epitaxial pedestal11′ enhances the oxidation rate of the doped semiconductor material in the doped upper portion16of each second epitaxial pedestal11′. As a consequence, the second semiconductor oxide portions21′ have a greater height (i.e., thickness) than the first semiconductor oxide portions21. In one embodiment, the ratio of the height of the second semiconductor oxide portions21′ to the height of the first semiconductor oxide portions21can be in a range from 1.2 to 5, such as from 1.4 to 3, although lesser ratios which are greater than 1 and greater ratios can also be employed. In one embodiment, the height of the first semiconductor oxide portions21can be in a range from 5 nm to 30 nm, and the height of the second semiconductor oxide portions21′ can be in a range from 6 nm to 100 nm, although lesser and greater heights can be employed for each of the first and second semiconductor oxide portions (21,21′). As a consequence, each remaining portion of the first epitaxial pedestals11has a greater height than each remaining portion of the second epitaxial pedestals11′. In one embodiment, the second semiconductor oxide portions21′ can have a greater concentration of the electrical dopants than the first semiconductor oxide portions21due to the presence of the electrical dopants in the second semiconductor oxide portions21′. Each second semiconductor oxide portion21′ within the first support openings221is a dielectric material portion.

Referring toFIGS. 11A and 11B, a fill material can be deposited in the first support openings221and in the first memory openings121simultaneously. The fill material can be an insulating material or a semiconducting material. The fill material has a composition different from the material of the first insulating layers32, and can have electrical resistivity greater than 10 Ω-cm. In one embodiment, the electrical resistivity of the fill material can be greater than 100 Ω-cm. In one embodiment, the electrical resistivity of the fill material can be greater than 1,000 Ω-cm, and may be in a range from 10,000 to 1020Ω-cm (such as 105to 1017Ω-cm). Non-limiting examples of the fill material includes amorphous silicon, polycrystalline silicon, an amorphous silicon-germanium alloy, and a polycrystalline silicon-germanium alloy. In case a semiconductor material is employed, the semiconductor material (such as amorphous silicon) is undoped (i.e., intrinsic). Excess portions of the deposited fill material can be removed from above the horizontal plane including the topmost surface of the first tier structure (132,142,270,165). Remaining portions of the deposited first fill material in the first openings (121,221) are herein referred to as fill material portions (126,226).

The fill material portions (126,226) include memory opening fill material portions126and support opening fill material portions226. The fill material is simultaneously deposited within the first support openings221and the first memory openings121to form support opening fill material portions226overlying respective second semiconductor oxide portions21′ and memory opening fill material portions126overlying the respective first semiconductor oxide portion21. Each first memory opening121is filled with a combination of a first epitaxial pedestal11, a first semiconductor oxide portion21, and a memory opening fill material portion126, which collectively constitute a first memory opening fill stack structure (11,21,126). Each first support opening221is filled with a combination of a second epitaxial pedestal11′ (which can include a remaining unoxidized part of the doped upper portion16), a second semiconductor oxide portion21′, and a support opening fill material portion226, which collectively constitute a first support opening fill stack structure (11′,21′,226), which can be referred to as the sacrificial support pillar structures228. The top surfaces of the fill material portions (126,226) can be within the same horizontal plane as the top surface of the first tier dielectric cap layer270.

Referring toFIGS. 12A and 12B, a second alternating stack (232,242) of material layers is subsequently formed on the top surface of the first tier structure (132,142,270,165). The second alternating stack (232,242) includes an alternating plurality of third material layers and fourth material layers. Each third material layer can include a third material, and each fourth material layer can include a fourth material that is different from the third material. In one embodiment, the third material can be the same as the first material of the first insulating layer132, and the fourth material can be the same as the second material of the first sacrificial material layers142.

In one embodiment, the third material layers and the fourth material layers can be second insulating layers232and second sacrificial material layers242, respectively. The third material of the second insulating layers232can be at least one insulating material. The fourth material of the second sacrificial material layers242is a sacrificial material that can be removed selective to the third material of the second insulating layers232. The second sacrificial material layers242may comprise an insulating material, a semiconductor material, or a conductive material. The fourth material of the second sacrificial material layers242can be subsequently replaced with electrically conductive electrodes which can function, for example, as control gate electrodes of a vertical NAND device.

In one embodiment, each second insulating layer232can include a second insulating material, and each second sacrificial material layer242can include a second sacrificial material. In this case, the second alternating stack (232,242) can include an alternating plurality of second insulating layers232and second sacrificial material layers242. The third material of the second insulating layers232can be deposited, for example, by chemical vapor deposition (CVD). The fourth material of the second sacrificial material layers242can be formed, for example, CVD or atomic layer deposition (ALD).

The third material of the second insulating layers232can be at least one insulating material. Insulating materials that can be employed for the second insulating layers232can be any material that can be employed for the first insulating layers132. The fourth material of the second sacrificial material layers242is a sacrificial material that can be removed selective to the third material of the second insulating layers232. Sacrificial materials that can be employed for the second sacrificial material layers242can be any material that can be employed for the first sacrificial material layers142. In one embodiment, the second insulating material can be the same as the first insulating material, and the second sacrificial material can be the same as the first sacrificial material. For example, the first and second sacrificial material layers (142,242) can include silicon nitride, and the first and second insulating layers (132,232) can include silicon oxide.

The thicknesses of the second insulating layers232and the second sacrificial material layers242can be in a range from 20 nm to 50 nm, although lesser and greater thicknesses can be employed for each second insulating layer232and for each second sacrificial material layer242. The number of repetitions of the pairs of a second insulating layer232and a second sacrificial material layer242can be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions can also be employed. In one embodiment, each second sacrificial material layer242in the second alternating stack (232,242) can have a uniform thickness that is substantially invariant within each respective second sacrificial material layer242.

A second-tier dielectric cap layer70can be subsequently formed over the second alternating stack (232,242). The second-tier dielectric cap layer70includes a dielectric material that is different from the material of the second sacrificial material layers242. The second-tier dielectric cap layer70includes a dielectric material that may be the same as, or different from, the material of the second insulating layers232. In one embodiment, the second-tier dielectric cap layer70can include silicon oxide.

The second alternating stack (232,242) and the second-tier dielectric cap layer70constitute a second tier structure (232,242,70). The sacrificial support pillar structures228extend through the first tier structure (132,142,270,165), and have respective topmost surfaces at an interface between the first tier structure (132,142,270,165) and the second tier structure (232,242,70). The topmost surfaces of the sacrificial support pillar structure228are formed within the same horizontal plane as the interface between the first tier structure (132,142,270,165) and the second tier structure (232,242,70).

Referring toFIGS. 13A and 13B, additional stepped surfaces are formed in the second alternating stack (232,242) in the contact region200. The additional stepped surfaces are herein referred to as second stepped surfaces. The second stepped surfaces are formed in a second stepped area, which is adjacent to, and does not overlie, the first stepped area of the first stepped surfaces within the first tier structure (132,142,270,165). The second stepped surfaces can be adjacent to, and do not overlie, the stepped interface between the first alternating stack (132,142) and the first retro-stepped dielectric material portion165. The second stepped surfaces overlie a subset of the sacrificial support pillar structures228that do not extend through the first stepped surfaces within the first tier structure (132,142,270,165).

The second stepped surfaces can be formed, for example, by forming a mask layer with an opening therein, etching a cavity within the levels of the topmost second sacrificial material layer242and the topmost second insulating layer232, and iteratively expanding the etched area and vertically recessing the cavity by etching a pair of a second insulating layer232and a second sacrificial material layer242located directly underneath the bottom surface of the etched cavity within the etched area. The second alternating stack (232,242) is patterned such that each underlying second sacrificial material layer242laterally protrudes farther than any overlying second sacrificial material layer242in the etched region, and each underlying second insulating layer232laterally protrudes farther than any overlying second insulating layer232in the etched region. The etched area includes the area of the contact region200, which includes the contact area for the second alternating stack (232,242) and a contact area for the first alternating stack (132,142).

Thus, the second alternating stack (232,242) is patterned to form the second stepped surfaces thereupon. The cavity formed by removal of portions of the second alternating stack (232,242) is herein referred to as a second stepped cavity. The area of the second stepped cavity includes the area of the first retro-stepped first dielectric material portion165, from which all layers of the second alternating stack (232,242) are removed. The area of the second stepped cavity further includes the area of the second stepped surfaces of the second alternating stack (232,242).

Dielectric material is deposited to fill the second stepped cavity. Excess portions of the dielectric material overlying the topmost surface of the second alternating stack (232,242) are removed, for example, by chemical mechanical planarization. The remaining portion of the deposited dielectric material is retro-stepped, and thus, forms a second dielectric material portion, which is herein referred to as a second retro-stepped dielectric material portion265. The second retro-stepped dielectric material portion265is located on, and over, the second stepped surfaces of the second alternating stack (232,242). The second retro-stepped dielectric material portion265is formed on the second stepped surfaces. The contact region200comprises a region of the first stepped surfaces and a region of the second stepped surfaces. Upon formation of the second retro-stepped dielectric material portion265, the second retro-stepped dielectric material portion265is incorporated into the second tier structure (232,242,70,265), i.e., becomes an element of the second tier structure (232,242,70,265).

The first stepped surfaces and the second stepped surfaces are collectively referred to as “stepped surfaces.” A first portion of the stepped surfaces is the first stepped surfaces located in the first tier structure (132,142,270,165). As second portion of the stepped surfaces is the second stepped surfaces located in the second tier structure (232,242,70,265). The first stepped surfaces and the second stepped surfaces are located within the contact region200.

The region of the stepped surfaces is herein referred to as a terrace region. Each sacrificial material layer (142,242) among the first and second sacrificial material layers (142,242) that is not a bottommost first sacrificial material layer142laterally extends less than any underlying layer among the first and second sacrificial material layers (142,242). The terrace region includes stepped surfaces of the first and second alternating stacks (132,142,232,242) that continuously extend from a bottommost layer within the first alternating stack (132,142) to a topmost layer within the second alternating stack (232,242).

Referring toFIGS. 14A and 14B, second openings (141,241) are formed through the second tier structure (232,242,265,70) to the top surface of the first tier structure (132,142,270,165). The second openings (141,241) include second memory openings141that are formed in the memory array region100and second support openings241that are formed in the contact region200.

The second memory openings241are formed through the second tier structure (232,242,70,265) in areas that overlap with the first memory openings121, i.e., with the memory opening fill material portions126. Thus, each second memory opening141can be formed on top of a respective memory opening fill material portion126(which is present in a first memory opening121). In one embodiment, the bottom surface of each second memory opening141can be formed within a periphery of a top surface of an underlying memory opening fill material portion126, i.e., can have an areal overlap with the top surface of the underlying memory opening fill material portion126.

The second support openings241are formed through the second tier structure (232,242,70,265) in areas that overlap with the first support openings221, i.e., with the support opening fill material portions226. Thus, each second support opening241can be formed on top of a respective support opening fill material portion226(which is present in a first support opening221). In one embodiment, the bottom surface of each second support opening241can be formed within a periphery of a top surface of an underlying support opening fill material portion226, i.e., can have an areal overlap with the top surface of the underlying support opening fill material portion226.

The second openings (141,241) can be formed by a combination of lithographic patterning and an anisotropic etch. For example, a lithographic material stack (not shown) including at least a photoresist layer can be formed over the second tier structure (232,242,265,70), and can be lithographically patterned to form openings within the lithographic material stack. The pattern in the lithographic material stack can be transferred through the entirety of the second tier structure (232,242,265,70) by at least one anisotropic etch that employs the patterned lithographic material stack as an etch mask. Portions of the second tier structure (232,242,265,70) underlying the openings in the patterned lithographic material stack are etched to form the second openings (141,241). In other words, transfer of the pattern in the patterned lithographic material stack through the second tier structure (232,242,265,70) forms the second openings (141,241).

In one embodiment, the chemistry of the anisotropic etch process employed to etch through the materials of the second alternating stack (232,242) can alternate to optimize etching of the third and fourth materials in the second alternating stack (232,242) while providing a comparable average etch rate for the second dielectric material portion265. The anisotropic etch can be, for example, a series of reactive ion etches. The sidewalls of the second openings (141,241) can be substantially vertical, or can be tapered.

A subset of the second support openings241can be formed through the second portion of the stepped surfaces (i.e., the second stepped surfaces) located on the second alternating stack (232,242). The second support opening241and the second memory openings141can be simultaneously formed employing at least one anisotropic etch process.

The lateral dimensions (e.g., a diameter) of the second openings (141,241) can be comparable to the lateral dimensions of the first openings (121,221). The second openings (141,241) can be wider than the respective first openings (121,221). For example, the lateral dimensions of the second openings (141,241) can be from about 20 nm to 200 nm at an upper portion of each second opening (141,241), and can be about 10 nm to 150 nm at a lower portion of each second opening (141,241). In one embodiment, the second memory openings141and the first memory openings121can be formed as an array of openings, which can be a periodic two-dimensional array of openings. The second support openings241and the first support openings221can be formed as discrete openings that are mutually separated from one another, and may, or may not, form a periodic two-dimensional array pattern. Subsequently, the patterned lithographic material stack can be subsequently removed, for example, by ashing.

Referring toFIGS. 15A and 15B, the fill materials of the fill material portions (126,226) can be removed from underneath the second memory openings141and from underneath the second support openings241without removing the semiconductor oxide portions (21,21′). An isotropic etch or an anisotropic etch may be performed to remove the material of the fill material portions (126,226) selective to the materials of the insulating layers (132,232), the sacrificial material layers (142,242), the second tier dielectric cap layer70, the first tier dielectric cap layer270, and the semiconductor oxide portions (21,21′). In case the fill material portions (126,226) include a semiconductor material such as silicon or a silicon-germanium alloy, a wet etch process employing a KOH solution can be employed to remove the material of the fill material portions (126,226).

Each vertically adjoined pair of a first memory opening121and a second memory opening141constitutes an inter-tier memory opening (121,141). Each vertically adjoined pair of a first support opening221and a second support opening241constitutes an inter-tier support opening (221,241). A stack of a first epitaxial pedestal11and a first semiconductor oxide portion21is located at a bottom portion of each inter-tier memory opening (121,141). A stack of a second epitaxial pedestal11′ and a second semiconductor oxide portion21′ is located at a bottom portion of each inter-tier support opening (221,241).

Each inter-tier memory opening (121,141) extends through the entirety of the first alternating stack (132,142,270,165) and the second alternating stack (232,242,70,265). Likewise, each inter-tier support opening (221,241) extends through the entirety of the first alternating stack (132,142,270,165) and the second alternating stack (232,242,70,265). Unfilled portions of the inter-tier memory openings (121,141) are herein referred to as memory cavities49. Unfilled portions of the inter-tier support openings (221,241) are herein referred to as support cavities149. Thus, simultaneous removal of the support opening fill material portions226and the memory opening fill material portions126from underneath the second memory openings141and the second support opening241forms the memory cavities49and the support cavities149.

Each memory cavity49extends through a respective second memory opening141and an upper portion of an underlying first memory opening121, while each support cavity149extends through a second support opening241and upper portion of an underlying first support opening221and bounded by a top surface of a respective second semiconductor oxide portion21′, which is a dielectric material portion. A bottommost surface of each memory cavity49is more proximal to a horizontal plane including the top surface of the substrate (9,10) than a bottommost surface of the support cavity149is to the horizontal plane including the top surface of the substrate (9,10) because the second semiconductor oxide portion21′ is thicker than the first semiconductor oxide portion21.

FIG. 16Ashows a vertical cross-sectional view of an memory cavity49in the inter-tier memory opening (121,141) after the processing steps ofFIGS. 15A and 15B.FIG. 16Bshows a vertical cross-sectional view of support cavity149in an inter-tier support opening (221,241) after the processing steps ofFIGS. 15A and 15B.

Referring toFIGS. 17A and 17B, a stack of material layers for forming a memory film and a first semiconductor channel layer601can be deposited within each of the inter-tier memory openings (121,141) and the inter-tier support opening (221,241). For example, the stack of material layers can include an optional blocking dielectric layer52, a memory material layer54, a tunneling dielectric layer56, and an optional first semiconductor channel layer601.

The blocking dielectric layer52can include a single dielectric material layer or a stack of a plurality of dielectric material layers. In one embodiment, the blocking dielectric layer can include a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material that includes at least one metallic element and at least oxygen. The dielectric metal oxide may consist essentially of the at least one metallic element and oxygen, or may consist essentially of the at least one metallic element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer52can include a dielectric metal oxide having a dielectric constant greater than 7.9, i.e., having a dielectric constant greater than the dielectric constant of silicon nitride.

Non-limiting examples of dielectric metal oxides include aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), silicates thereof, nitrogen-doped compounds thereof, alloys thereof, and stacks thereof. The dielectric metal oxide layer can be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid source misted chemical deposition, or a combination thereof. The thickness of the dielectric metal oxide layer can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. The dielectric metal oxide layer can subsequently function as a dielectric material portion that blocks leakage of stored electrical charges to control gate electrodes. In one embodiment, the blocking dielectric layer52includes aluminum oxide. In one embodiment, the blocking dielectric layer52can include multiple dielectric metal oxide layers having different material compositions.

Alternatively or additionally, the blocking dielectric layer52can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer52can include silicon oxide. In this case, the dielectric semiconductor compound of the blocking dielectric layer52can be formed by a conformal deposition method such as low pressure chemical vapor deposition, atomic layer deposition, or a combination thereof. The thickness of the dielectric semiconductor compound can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. Alternatively, the blocking dielectric layer52can be omitted, and a backside blocking dielectric layer can be formed after formation of backside recesses on surfaces of memory films to be subsequently formed.

Subsequently, the memory material layer54can be formed. In one embodiment, the memory material layer54can be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material, which can be, for example, silicon nitride. Alternatively, the memory material layer54can include a continuous layer or patterned discrete portions of a conductive material such as doped polysilicon or a metallic material that is patterned into multiple electrically isolated portions (e.g., floating gates), for example, by being formed within lateral recesses into sacrificial material layers (142,242). In one embodiment, the memory material layer54includes a silicon nitride layer. In one embodiment, the sacrificial material layers (142,242) and the insulating layers (132,232) can have vertically coincident sidewalls, and the memory material layer54can be formed as a single continuous layer.

In another embodiment, the sacrificial material layers (142,242) can be laterally recessed with respect to the sidewalls of the insulating layers (132,232), and a combination of a deposition process and an anisotropic etch process can be employed to form the memory material layer54as a plurality of memory material portions that are vertically spaced apart. While the present disclosure is described employing an embodiment in which the memory material layer54is a single continuous layer, embodiments are expressly contemplated herein in which the memory material layer54is replaced with a plurality of memory material portions (which can be charge trapping material portions or electrically isolated conductive material portions) that are vertically spaced apart.

The memory material layer54can be formed as a single memory material layer of homogeneous composition, or can include a stack of multiple memory material layers. The multiple memory material layers, if employed, can comprise a plurality of spaced-apart floating gate material layers that contain conductive materials (e.g., metal such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or a metal silicide such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or a combination thereof) and/or semiconductor materials (e.g., polycrystalline or amorphous semiconductor material including at least one elemental semiconductor element or at least one compound semiconductor material). Alternatively or additionally, the memory material layer54may comprise an insulating charge trapping material, such as one or more silicon nitride segments. Alternatively, the memory material layer54may comprise conductive nanoparticles such as metal nanoparticles, which can be, for example, ruthenium nanoparticles. The memory material layer54can be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing electrical charges therein. The thickness of the memory material layer54can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.

The optional first semiconductor channel layer601includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first semiconductor channel layer601includes amorphous silicon or polysilicon. The first semiconductor channel layer601can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the first semiconductor channel layer601can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. A memory cavity49is present in the volume of each inter-tier memory opening (121,141) that is not filled with the deposited material layers (52,54,56,601). A support cavity149can be present within each volume of the second support opening241that is not filled with the deposited material layers (52,54,56,601).

Referring toFIGS. 18A and 18B, the optional first semiconductor channel layer601, the tunneling dielectric layer56, the memory material layer54, the blocking dielectric layer52are sequentially anisotropically etched employing at least one anisotropic etch process. The portions of the first semiconductor channel layer601, the tunneling dielectric layer56, the memory material layer54, and the blocking dielectric layer52located above the top surface of the second tier dielectric cap layer70can be removed by the at least one anisotropic etch process. Further, the horizontal portions of the first semiconductor channel layer601, the tunneling dielectric layer56, the memory material layer54, and the blocking dielectric layer52at a bottom of each memory cavity49and each support cavity149can be removed to form openings in remaining portions thereof. Each of the first semiconductor channel layer601, the tunneling dielectric layer56, the memory material layer54, and the blocking dielectric layer52can be etched by anisotropic etch process.

The memory material layer54can comprise a charge trapping material or a floating gate material. In one embodiment, each memory material layer54can include a vertical stack of charge storage regions that store electrical charges upon programming. In one embodiment, the memory material layer54can be a memory material layer in which each portion adjacent to the sacrificial material layers (142,242) constitutes a charge storage region.

The duration of the anisotropic etch process after the blocking dielectric layer52is etched through is selected such that the first semiconductor oxide portions21are etched through to physically expose a surface of an underlying first epitaxial pedestal11, while second semiconductor oxide portions21′ are not etched through. In other words, the duration of the portion of the anisotropic etch process that is employed to etch the first and second semiconductor material portions (21,21′) is selected such that the vertical etch distance is greater than the thickness of the first semiconductor oxide portion21, and is less than the thickness of the second semiconductor oxide portion21′. Within each inter-tier memory opening (121,141), a surface of a respective first epitaxial pedestal11can be physically exposed underneath the opening through the first semiconductor channel layer601, the tunneling dielectric layer56, the memory material layer54, and the blocking dielectric layer52. Within each inter-tier support opening (221,241), sidewall surfaces and a recessed horizontal surface of a respective second epitaxial pedestal11′ is not physically exposed through an opening that extends through the first semiconductor channel layer601, the tunneling dielectric layer56, the memory material layer54, and the blocking dielectric layer52.

A set of a blocking dielectric layer52, a memory material layer54, and a tunneling dielectric layer56in each of the inter-tier memory openings (121,141) constitutes a memory film50, which includes a plurality of charge storage regions (as embodied as the memory material layer54) that are insulated from surrounding materials by the blocking dielectric layer52and the tunneling dielectric layer56. A set of a blocking dielectric layer52, a memory material layer54, and a tunneling dielectric layer56in each of the inter-tier support openings (221,241) constitutes a dielectric layer stack150, which includes an instance of a same set of layers as an instance of the memory film50. In one embodiment, the first semiconductor channel layer601, the tunneling dielectric layer56, the memory material layer54, and the blocking dielectric layer52can have vertically coincident sidewalls.

Referring toFIGS. 19A and 19B, a second semiconductor channel layer602can be deposited directly on the semiconductor surface of the epitaxial pedestal11, and directly on the first semiconductor channel layer601. The second semiconductor channel layer602includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the second semiconductor channel layer602includes amorphous silicon or polysilicon. The second semiconductor channel layer602can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the second semiconductor channel layer602can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. The second semiconductor channel layer602may partially fill the memory cavity49in each inter-tier memory opening (121,141), or may fully fill the memory cavity49in each inter-tier memory opening (121,141).

The materials of the first semiconductor channel layer601and the second semiconductor channel layer602are collectively referred to as a semiconductor channel material. In other words, the semiconductor channel material is a set of all semiconductor material in the first semiconductor channel layer601and the second semiconductor channel layer602.

In case the memory cavity49in each inter-tier memory opening (121,141) and/or the support cavity149in each second support opening241are not completely filled by the second semiconductor channel layer602, a dielectric core layer62L can be deposited in the memory cavities49and/or the support cavities249. The dielectric core layer62L includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer62L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process such as spin coating.

Referring toFIGS. 20A and 20B, the horizontal portion of the dielectric core layer62L can be removed, for example, by a recess etch from above the top surface of the second tier dielectric cap layer70. Remaining portions of the dielectric core layer62L constitute dielectric cores (62,162), which include first dielectric cores62formed in the inter-tier memory openings (121,141) and second dielectric cores162formed in the inter-tier support openings (221,241). Further, the horizontal portion of the second semiconductor channel layer602located above the top surface of the second tier dielectric cap layer70can be removed by a planarization process, which can employ a recess etch or chemical mechanical planarization (CMP).

Each adjoining pair of a first semiconductor channel layer601and a second semiconductor channel layer602in an inter-tier memory opening (121,141) collectively form a vertical semiconductor channel60. Each adjoining pair of a first semiconductor channel layer601and a second semiconductor channel layer602in an inter-tier support opening (221,241) collectively form a vertical semiconductor layer160. The vertical semiconductor channel60with each inter-tier memory opening (121,141) is subsequently electrically connected to a respective contact via structure (e.g., electrically connected to a respective bit line by a bit line contact via). The vertical semiconductor layer160with each inter-tier support opening (221,241) is not subsequently electrically connected to any contact via structure (and not electrically connected to any bit line), and remains electrically floating. Within each inter-tier memory opening (121,141), electrical current can flow through a vertical semiconductor channel60when a vertical NAND device including the vertical semiconductor channel60is turned on.

Within each inter-tier memory opening (121,141) and each inter-tier support opening (221,241), a tunneling dielectric layer56is surrounded by a memory material layer54, and laterally surrounds a portion of the vertical semiconductor channel60. Each adjoining set of a blocking dielectric layer52, a memory material layer54, and a tunneling dielectric layer56within the inter-tier memory openings (121,141) collectively constitute a memory film50. Each adjoining set of a blocking dielectric layer52, a memory material layer54, and a tunneling dielectric layer56within the inter-tier support openings (221,241) collectively constitute a dielectric layer stack150. Each memory film50within an inter-tier memory opening (121,141) can store electrical charges with a macroscopic retention time. Each a dielectric layer stack150within an inter-tier support opening (221,241) is an inactive component that functions merely as an insulating film. In some embodiments, a blocking dielectric layer52may not be present in the memory film50and the dielectric layer stack150at this step, and a blocking dielectric layer may be subsequently formed after formation of backside recesses. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device such as a retention time in excess of 24 hours.

In one embodiment, a first epitaxial pedestal11can be formed at a bottom portion of each first memory opening121and directly on the substrate (9,10), and a vertical semiconductor channel60can be formed directly on a portion of the first epitaxial pedestal11. A second epitaxial pedestal11′ can be formed at a bottom portion of each first support opening221concurrently with formation of the first epitaxial pedestals11, and a bottommost surface of a vertical semiconductor layer160can be formed above, and is vertically spaced from, any material of the second epitaxial pedestal11′ by the dielectric material of the second semiconductor oxide portion21′. Thus, the vertical semiconductor layer160does not electrically contact the semiconductor substrate (9,10).

Referring toFIGS. 21A and 21B, the top surface of each dielectric core (62,162) can be further recessed within each inter-tier memory opening (121,141) and within inter-tier support opening (221,241), for example, by a recess etch to a depth that is located between the top surface of the second tier dielectric cap layer70and the bottom surface of the second tier dielectric cap layer70. A doped semiconductor material can be deposited within each recessed region above the dielectric cores (62,162). The doped semiconductor material can be, for example, doped polysilicon. Excess portions of the deposited semiconductor material can be removed from above the top surface of the second tier dielectric cap layer70, for example, by chemical mechanical planarization (CMP) or a recess etch. Within the inter-tier memory openings (121,141), each remaining portion of the doped semiconductor material overlying a respective first dielectric core62constitutes a drain region63. Within the inter-tier support opening (221,241), each remaining portion of the doped semiconductor material overlying a respective second dielectric core162constitutes a dummy drain region163.

Each drain region63within an inter-tier memory opening (121,141) is a top active region of a vertical field effect transistor including a respective vertical semiconductor channel60. Each dummy drain region163within an inter-tier support opening (221,241) is electrically inactive. Each dummy drain region163in the inter-tier support openings (221,241) is not subsequently contacted by any contact via structure. The drain regions63and the dummy drain regions163can have the same material composition. In one embodiment, the drain regions63and the dummy drain regions163can be heavily doped. In one embodiment, the drain regions63and the dummy drain regions163can include electrical dopants (p-type dopants or n-type dopants) at an atomic concentration greater than 5.0×1019/cm3.

Each contiguous set of a memory film50, a vertical semiconductor channel60, and an optional first dielectric core62formed within an inter-tier memory opening (121,141) constitutes a memory stack structure55. Each contiguous set of a second semiconductor oxide portion21′, a dielectric layer stack150, a vertical semiconductor layer160, an optional second dielectric core162, and a dummy drain region163formed within an inter-tier support opening (221,241) constitutes a support pillar structure155.

Each support pillar structure155can be located within a respective support opening, i.e., an inter-tier support opening (221,241). The support pillar structure155comprises a vertical semiconductor layer160comprising the same material as a vertical semiconductor channel60, and a dielectric material portion as embodied as a second semiconductor oxide portion21′ that electrically isolates the vertical semiconductor layer160from the substrate (9,10).

In one embodiment, each support cavity149as formed at the processing steps ofFIGS. 15A and 15Bcan extend through the entirety of the second tier structure (232,242,70,265), and each dielectric material portion can be a second semiconductor oxide portion21′ that is more proximal to a horizontal plane including the bottom surface of the first tier structure (132,142,270,165) than to the horizontal plane including the top surface of the first tier structure (132,142,270,165), and the vertical semiconductor layer160protrudes into an upper region of the second semiconductor oxide portion21′ and does not extend through the second semiconductor oxide portion21′.

Referring toFIGS. 22A and 22B, the first exemplary structure is illustrated after formation of memory stack structures55and support pillar structures155, drain regions63, and dummy drain regions163. Each memory stack structure55is formed in a respective memory cavity49while elements of the support pillar structures155are formed in the support cavities149.

Referring toFIGS. 23A and 23B, a contact level dielectric layer80can be formed over the second tier structure (232,242,265,70). The contact level dielectric layer80includes a dielectric material such as silicon oxide, a dielectric metal oxide, and/or organosilicate glass. In one embodiment, the contact level dielectric layer80can be composed primarily of a silicon oxide material. The thickness of the contact level dielectric layer80can be in a range from 50 nm to 500 nm, although lesser and greater thicknesses can also be employed.

A photoresist layer (not shown) can be applied over the contact level dielectric layer80, and is lithographically patterned to form at least one elongated opening in each area in which formation of a backside contact via structure is desired. The pattern in the photoresist layer can be transferred through the contact level dielectric layer80, the second tier structure (232,242,265,70), and the first tier structure (132,142,270,165) employing an anisotropic etch to form the at least one backside trench79, which extends at least to the top surface of the substrate (9,10). In one embodiment, the at least one backside trench79can include a source contact opening in which a source contact via structure can be subsequently formed.

Referring toFIGS. 24A and 24B, an etchant that selectively etches the second material of the sacrificial material layers (142,242) with respect to the materials of the insulating layers (132,232) and the semiconductor material(s) of the substrate (9,10) can be introduced into the at least one backside trench79, for example, employing an etch process. Backside recesses (143,243) are formed in volumes from which the sacrificial material layers (142,242) are removed. Specifically, first backside recesses143are formed in the volumes from which the first sacrificial material layers142are removed, and second backside recesses243are formed in the volumes from which the second sacrificial material layers242are removed.

The removal of the second material of the sacrificial material layers (142,242) can be selective to the materials of the insulating layers (132,232), the materials of the retro-stepped dielectric material portions (165,265), the semiconductor material(s) of the substrate (9,10), and the material of the outermost layer of the memory films50. Each backside recess (143,243) can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess (143,243) can be greater than the height of the backside recess (143,243). The inter-tier memory openings containing the memory cavity49, the first support openings221, and the second support openings241are herein referred to as front side openings or front side cavities in contrast with the backside recesses (143,243). In one embodiment, the memory array region100comprises an array of monolithic three-dimensional NAND strings having a plurality of device levels disposed above the substrate (9,10). In this case, each backside recess (143,243) can define a space for receiving a respective word line of the array of monolithic three-dimensional NAND strings.

Each of the plurality of backside recesses (143,243) can extend substantially parallel to the top surface of the substrate (9,10). A backside recess (143,243) can be vertically bounded by a top surface of an underlying insulating layer32and a bottom surface of an overlying insulating layer32. In one embodiment, each backside recess (143,243) can have a uniform height throughout.

Subsequently, physically exposed surface portions of the optional epitaxial pedestals (11,11′) and the semiconductor material layer10may be converted into dielectric material portions by thermal conversion and/or plasma conversion of the semiconductor materials into dielectric materials. For example, thermal conversion and/or plasma conversion can be employed to convert a surface portion of each epitaxial pedestal (11,11′) into a tubular dielectric spacer116, and to convert each physically exposed surface portion of the semiconductor material layer10into a planar dielectric portion616.

Referring toFIGS. 25A and 25B, a backside blocking dielectric layer (not shown) can be optionally formed. The backside blocking dielectric layer, if present, comprises a dielectric material that functions as a control gate dielectric for the control gates to be subsequently formed in the backside recesses (143,243). In case the blocking dielectric layer52is present within each memory opening, the backside blocking dielectric layer is optional. In case the blocking dielectric layer52is omitted, the backside blocking dielectric layer is present.

The backside blocking dielectric layer can be formed in the backside recesses (143,243) and on a sidewall of the backside trench79. The backside blocking dielectric layer can be formed directly on horizontal surfaces of the insulating layers (132,232) and physically exposed sidewalls of the blocking dielectric52within the backside recesses (143,243). If the backside blocking dielectric layer is formed, formation of the tubular dielectric spacers and the planar dielectric portion prior to formation of the backside blocking dielectric layer is optional.

The dielectric material of the backside blocking dielectric layer can be a dielectric metal oxide such as aluminum oxide, a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one Lanthanide element, a dielectric oxide of a combination of aluminum, at least one transition metal element, and/or at least one Lanthanide element. Alternatively or additionally, the backside blocking dielectric layer can include a silicon oxide layer. The backside blocking dielectric layer can be deposited by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The thickness of the backside blocking dielectric layer can be in a range from 1 nm to 10 nm, although lesser and greater thicknesses can also be employed. A backside cavity is present within the portion of each backside trench79that is not filled with the backside blocking dielectric layer.

At least one conducive material can be deposited to form electrically conductive layers (146,246). The at least one conductive material can include a metallic liner and a conductive fill material layer. The metallic liner can include a metallic nitride material such as TiN, TaN, WN, an alloy thereof, or a stack thereof. The metallic liner functions as a diffusion barrier layer and an adhesion promotion layer. The metallic liner can be deposited by a conformal deposition method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), and can have a thickness in a range from 1 nm to 6 nm, although lesser and greater thicknesses can also be employed. The conductive fill material layer can be deposited directly on the metallic liner by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The conductive fill material layer includes a conductive material. The conductive material can include at least one elemental metal such as W, Cu, Co, Mo, Ru, Au, and Ag. Additionally or alternatively, the conductive fill material layer (146,246) can include at least one intermetallic metal alloy material. Each intermetallic metal alloy material can include at least two metal elements selected from W, Cu, Co, Mo, Ru, Au, Ag, Pt, Ni, Ti, and Ta. In one embodiment, the conductive fill material layer can consist essentially of W, Co, Mo, or Ru.

Each portion of the at least one conducive material that fills a backside recess (143or243) constitutes an electrically conductive layer (146or246). The electrically conductive layers (146,246) include first electrically conductive layers146that are formed in the first backside recesses143in the first tier structure, and second electrically conductive layers246that are formed in the second backside recesses243in the second tier structure. The portion of the at least one conductive material that excludes the electrically conductive layers (146,246) constitutes continuous metallic material layer46L. A plurality of electrically conductive layers (146,246) can be formed in the plurality of backside recesses (143,243), and the continuous metallic material layer46L can be formed on the sidewalls of each backside trench79and over the contact level dielectric layer80. A backside cavity is present in the portion of each backside trench79that is not filled with the backside blocking dielectric layer and the continuous metallic material layer46L.

Each first sacrificial material layer142can be replaced with a respective first electrically conductive layer146, and each second sacrificial material layer242can be replaced with a respective second electrically conductive layer246, while the support pillar structures155and the memory stack structures55provide structural support to the first and second insulating layers (132,232).

Referring toFIGS. 26A and 26B, the deposited metallic material of the continuous electrically conductive material layer46L is etched back from the sidewalls of each backside trench79and from above the contact level dielectric layer80, for example, by an isotropic wet etch, an anisotropic dry etch, or a combination thereof. The electrically conductive layers (146,246) in the backside recesses are not removed by the etch process. In one embodiment, the sidewalls of each electrically conductive layer (146or246) can be vertically coincident after removal of the continuous electrically conductive material layer46L.

Each electrically conductive layer (146or246) can function as a combination of a plurality of control gate electrodes located at a same level and a word line electrically interconnecting, i.e., electrically shorting, the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each electrically conductive layer (146or246) are the control gate electrodes for the vertical memory devices including the memory stack structures55. In other words, each electrically conductive layer (146or246) can be a word line that functions as a common control gate electrode for the plurality of vertical memory devices.

Referring toFIGS. 27A and 27B, an insulating material layer can be formed in the at least one backside trench79and over the contact level dielectric layer80by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer includes an insulating material such as silicon oxide, silicon nitride, a dielectric metal oxide, an organosilicate glass, or a combination thereof. In one embodiment, the insulating material layer can include silicon oxide. The insulating material layer can be formed, for example, by low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer can be in a range from 1.5 nm to 60 nm, although lesser and greater thicknesses can also be employed. An anisotropic etch is performed to remove horizontal portions of the insulating material layer from above the contact level dielectric layer80and at the bottom of each backside trench79. Each remaining portion of the insulating material layer constitutes an insulating spacer74. The anisotropic etch can continue to etch through physically exposed portions of the planar dielectric portion, if present, in each backside trench79. Thus, an insulating spacer74is formed in each backside trench79directly on physically exposed sidewalls of the electrically conductive layers (146,246).

A source region61can be formed underneath each backside trench79by implantation of electrical dopants into physically exposed surface portions of the semiconductor material layer10. Each source region61is formed in a surface portion of the substrate (9,10) that underlies a respective opening through the insulating spacer74. Due to the straggle of the implanted dopant atoms during the implantation process and lateral diffusion of the implanted dopant atoms during a subsequent activation anneal process, each source region61can contact a bottom surface of the insulating spacer74. A surface portion of the semiconductor material layer10adjoining a source region61and continuously extending to the epitaxial pedestals (11,11′) constitutes a horizontal semiconductor channel59, which is a common portion of a plurality of semiconductor channels (59,11,60) that include the vertical semiconductor channels60within the memory stack structures55.

A backside contact via structure76can be formed within each cavity. Each contact via structure76can fill a respective cavity. The backside contact via structures76can be formed by depositing at least one conductive material in the remaining unfilled volume (i.e., the backside cavity) of the backside trench79. For example, the at least one conductive material can include a conductive liner (not expressly shown) and a conductive fill material portion (not expressly shown). The conductive liner can include a metallic liner such as TiN, TaN, WN, TiC, TaC, WC, an alloy thereof, or a stack thereof. The thickness of the conductive liner can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed. The conductive fill material portion can include a metal or a metallic alloy. For example, the conductive fill material portion can include W, Cu, Al, Co, Ru, Ni, an alloy thereof, or a stack thereof.

The at least one conductive material can be planarized employing the contact level dielectric layer80overlying the alternating stacks (132,146,232,246) as a stopping layer. If chemical mechanical planarization (CMP) process is employed, the contact level dielectric layer80can be employed as a CMP stopping layer. Each remaining continuous portion of the at least one conductive material in the backside trenches79constitutes a backside contact via structure76. Each backside contact via structure76can be formed directly on a top surface of a source region61. Each backside contact via structure76can contact a respective source region61, and can be laterally surrounded by a respective insulating spacer74.

Referring toFIGS. 28A and 28B, additional contact via structures (88,86) can be formed through the contact level dielectric layer80and through the retro-stepped dielectric material portions (165,265). For example, drain contact via structures88can be formed through the contact level dielectric layer80on each drain region63. Each drain contact via structure88can be formed through the contact level dielectric layer80on each of the drain regions63, while not forming any conductive structure through the contact level dielectric layer80over the doped semiconductor material portions of the dummy drain regions163. Subsequently, bit lines (not shown) are formed in electrical contact with the drain contact via structures88.

Control gate contact via structures86can be formed in the terrace region on the electrically conductive layers (146,246) through the contact level dielectric layer80, and through the retro-stepped dielectric material portions (165,265). The control gate contact via structures86vertically extend at least through a dielectric material portion (i.e., the second retro-stepped dielectric material portion265) within the second tier structure (232,246,265,70), and contact a respective electrically conductive layer selected from the first and second electrically conductive layers (146,246). Peripheral gate contact via structures (not shown) and peripheral active region contact via structures (not shown) can be formed through the retro-stepped dielectric material portions (165,265) directly on respective nodes of the peripheral devices700illustrated inFIG. 1.

Each memory stack structure55comprises a vertical semiconductor channel60that is electrically shorted to a horizontal semiconductor channel59located within the substrate (9,10), and each of the support pillar structures155comprises a vertical semiconductor layer160comprising the same material as the vertical semiconductor channel60that is electrically isolated from the substrate (9,10) by a respective dielectric material portion as embodied as a second semiconductor oxide portion21′.

Referring toFIGS. 29A and 29B, a second exemplary structure according to a second embodiment of the present disclosure can be the same as the first exemplary structure illustrated inFIGS. 8A and 8B. Thus, a first epitaxial pedestal11is formed at a bottom portion of each first memory opening121directly on the substrate (9,10), and a second epitaxial pedestal11′ is formed at a bottom portion of each first support opening221directly on the substrate (9,10) concurrently with formation of the first epitaxial pedestals11.

Referring toFIGS. 30A and 30B, semiconductor oxide portions (21,21′) are formed by oxidation of upper portions of the epitaxial pedestals (11,11′). The processing steps ofFIGS. 10A and 10Bcan be performed to form the semiconductor oxide portions (21,21′). The semiconductor oxide portions (21,21′) include first semiconductor oxide portions21and second semiconductor oxide portions21′. Each first semiconductor oxide portion21is formed by conversion of an upper portion of a respective first epitaxial pedestal11, and each second semiconductor oxide portion21′ is formed by conversion of an upper portion of a respective second epitaxial pedestal11′. The first semiconductor oxide portions21and the second semiconductor oxide portions21′ can have the same thickness. Each remaining portion of the first epitaxial pedestal11and each remaining portion of the second epitaxial pedestal11′ can have the same thickness and the same height.

Referring toFIGS. 31A and 31B, a fill material can be simultaneously deposited within the remaining volumes of the first memory openings121and the remaining volumes of the first support openings221to form memory opening fill material portions126and support opening fill material portions226, respectively. The processing steps ofFIGS. 11A and 11Bcan be performed to form the fill material portions (126,226). In one embodiment, the memory opening fill material portions126and the support opening fill material portions226can have the same height.

Referring toFIGS. 32A and 32B, a mask layer167is formed over the second exemplary structure to cover the memory opening fill material portions126, while not covering the support opening fill material portions226. The mask layer167can be a patterned photoresist layer. In this case, the photoresist layer can be applied over the entire top surface of the second exemplary structure, and can be lithographically patterned (by exposure and development) to cover the memory opening fill material portions126in the first memory openings121while not covering the support opening fill material portions226in the first support openings221.

A recess etch process is performed to vertically recess the top portions of the support opening fill material portions226selective to the first-tier dielectric cap layer270and the first retro-stepped dielectric material portion165while the memory opening fill material portions126are masked by the mask layer167. The depth of the formed recesses can be selected such that each cavity323formed by the recess etch process has a lesser depth than the thickness of the first-tier dielectric cap layer270. The mask layer167can be subsequently removed, for example, by ashing.

Referring toFIGS. 33A-33C, a dielectric material portion326can be deposited within each cavity323formed by the recess etch process. The dielectric material portion326includes a dielectric material that is more etch resistance to silicon oxide to an etch process to be subsequently employed to etch memory films. In one embodiment, the dielectric material portions326can include a dielectric metal oxide such as aluminum oxide, hafnium oxide, tantalum pentoxide, etc. The dielectric material portions326can be formed, for example, by depositing a dielectric material to fill the recessed cavities overlying remaining portions of the support opening fill material portions226, and by performing a planarization process such as CMP or etch back, i.e., by removing excess portions of the deposited dielectric material from above the horizontal plane including the top surface of the first-tier dielectric cap layer270. In one embodiment, an optional anneal process can be performed after the planarization process to enhance etch resistivity of the material of the dielectric material portions326. For example, the dielectric material of the dielectric material portions can be deposited as an amorphous material (such as amorphous aluminum oxide) and can be converted into a polycrystalline material (such as polycrystalline aluminum oxide) by an anneal process after the planarization process.

Each dielectric material portion326can be formed within a recess cavity323in a respective first support opening221, and directly on a remaining portion of a respective support opening fill material portion226. In one embodiment, the top surfaces of the dielectric material portions326and the top surfaces of the memory opening fill material portion126can be within the same horizontal plane as the top surfaces of the first tier structure (132,142,270,165). In one embodiment, the dielectric material portions326can comprise a dielectric metal oxide.

Referring toFIGS. 34A and 34B, the processing steps of FIS.12A and12B can be performed to form a second alternating stack of second insulating layers232and second sacrificial material layers242and a second-tier dielectric cap layer70as in the first embodiment.

Referring toFIGS. 35A and 35B, the processing steps ofFIGS. 13A and 13Bcan be performed to form second stepped surfaces and a second retro-stepped dielectric material portion265as in the first embodiment. A second tier structure (232,242,70,265) is formed, which includes a second alternating stack of the second insulating layers232and the second sacrificial material layers242, a second-tier dielectric cap layer70, and the second retro-stepped dielectric material portion265.

Referring toFIGS. 36A and 36B, the processing steps ofFIGS. 14A and 14Bcan be formed to form second memory openings141and second support openings241as in the first embodiment. The second support openings241overlie the first support openings221and the dielectric material portions326therein, and the second memory openings overlies the first memory openings121and the memory opening fill material portions126therein.

Referring toFIGS. 37A and 37B, the memory opening fill material portions126can be removed from underneath the second memory openings141without removing the dielectric material portions326. An isotropic etch or an anisotropic etch may be performed to remove the memory opening fill material portions126selective to the materials of the insulating layers (132,232), the sacrificial material layers (142,242), the second tier dielectric cap layer70, the first tier dielectric cap layer270, and the dielectric material portions326. In case the memory opening fill material portions126include a semiconductor material such as silicon or a silicon-germanium alloy, a wet etch process employing a KOH solution can be employed to remove the memory opening fill material portions126.

Each vertically adjoined pair of a first memory opening121and a second memory opening141constitutes an inter-tier memory opening (121,141). Each vertically adjoined pair of a first support opening221and a second support opening241constitutes an inter-tier support opening (221,241). A stack of a first epitaxial pedestal11and a first semiconductor oxide portion21is located at a bottom portion of each inter-tier memory opening (121,141). A stack of a second epitaxial pedestal11′, a second semiconductor oxide portion21′, a support opening fill material portion226, and a dielectric material portion326is located in each first support opening221, which is a lower portion of a respective inter-tier support opening (221,241).

Each inter-tier memory opening (121,141) extends through the entirety of the first alternating stack (132,142,270,165) and the second alternating stack (232,242,70,265). Likewise, each inter-tier support opening (221,241) extends through the entirety of the first alternating stack (132,142,270,165) and the second alternating stack (232,242,70,265). Unfilled portions of the inter-tier memory openings (121,141) are herein referred to as memory cavities49. Unfilled portions of the inter-tier support openings (221,241) coincide with the second support openings241. Thus, removal of the support opening fill material portions226from underneath the second memory openings141forms the memory cavities49, while the volume of each second memory opening241remains unchanged. The unfilled volume of each inter-tier support opening (221,241) is herein referred to as a support cavity149. In one embodiment, the dielectric material of the dielectric material portions326can act as etch stop portions that provide sufficient etch resistivity to the etch processes that form the second memory openings141and that remove the fill material of the memory opening fill material portions126so that collateral etch of the dielectric material portions326is negligible. In this case, the volume of each support cavity149can substantially coincide with the volume of a respective second support opening241.

Each memory cavity49extends through a respective second memory opening141and an upper portion of an underlying first memory opening121, while each support cavity149is bounded by a top surface of a respective dielectric material portion326. A bottommost surface of each memory cavity49is more proximal to a horizontal plane including the top surface of the substrate (9,10) than a bottommost surface of each support cavity149is to the horizontal plane including the top surface of the substrate (9,10).

FIG. 38Ashows a vertical cross-sectional view of the memory cavity49in the inter-tier memory opening (121,141) after the processing steps ofFIGS. 37A and 37B.FIG. 38Bshows a vertical cross-sectional view of the support cavity149in the inter-tier support opening (221,241) after the processing steps ofFIGS. 37A and 37B.

Referring toFIGS. 39A and 39B, the processing steps ofFIGS. 17A and 17Bcan be performed to form a layer stack of material layers (52,54,56) for forming a memory film and a first semiconductor channel layer601as in the first embodiment. The layer stack of material layers (52,54,56) can include a blocking dielectric layer52, a memory material layer54, and a tunneling dielectric layer56as in the first embodiment.

Referring toFIGS. 40A and 40B, the processing steps ofFIGS. 18A and 18Bcan be performed to remove horizontal portions of the first semiconductor channel layer601and the layer stack of the material layers (52,54,56). The dielectric material portions326can be etch stop portions which are more etch-resistant to the anisotropic etch employed to remove horizontal portions of the first semiconductor channel layer601and the layer stack of the material layers (52,54,56) than the first semiconductor oxide portions21. Additionally or alternatively, the dielectric material portions326can be thicker than the first semiconductor oxide portions21. The duration of the anisotropic etch process after the blocking dielectric layer52is etched through is selected such that the first semiconductor oxide portions21are etched through to physically expose a surface of an underlying first epitaxial pedestal11, while dielectric material portions326are not etched through.

A set of a blocking dielectric layer52, a memory material layer54, and a tunneling dielectric layer56in each of the inter-tier memory openings (121,141) constitutes a memory film50, which includes a plurality of charge storage regions (as embodied as the memory material layer54) that are insulated from surrounding materials by the blocking dielectric layer52and the tunneling dielectric layer56. A set of a blocking dielectric layer52, a memory material layer54, and a tunneling dielectric layer56in each of the inter-tier support openings (221,241) constitutes a dielectric layer stack150, which includes an instance of a same set of layers as an instance of the memory film50. In one embodiment, the first semiconductor channel layer601, the tunneling dielectric layer56, the memory material layer54, and the blocking dielectric layer52can have vertically coincident sidewalls.

Referring toFIGS. 41A and 41B, the processing steps ofFIGS. 19A and 19Bcan be performed to form a second semiconductor channel layer602and a dielectric core layer62L.

Referring toFIGS. 42A and 42B, the processing steps ofFIGS. 20A and 20Bcan be performed to remove portions of the dielectric core layer62L and the second semiconductor channel layer602located above the horizontal plane including the top surface of the second-tier dielectric cap layer70.

Each adjoining pair of a first semiconductor channel layer601and a second semiconductor channel layer602in an inter-tier memory opening (121,141) collectively form a vertical semiconductor channel60. Each adjoining pair of a first semiconductor channel layer601and a second semiconductor channel layer602in an inter-tier support opening (221,241) collectively form a vertical semiconductor layer160. The vertical semiconductor channel60with each inter-tier memory opening (121,141) is subsequently electrically connected to a respective contact via structure. The vertical semiconductor layer160with each inter-tier support opening (221,241) is not subsequently electrically connected to any contact via structure, and remains electrically floating. Within each inter-tier memory opening (121,141), electrical current can flow through a vertical semiconductor channel60when a vertical NAND device including the vertical semiconductor channel60is turned on.

Within each inter-tier memory opening (121,141) and each inter-tier support opening (221,241), a tunneling dielectric layer56is surrounded by a memory material layer54, and laterally surrounds a portion of the vertical semiconductor channel60. Each adjoining set of a blocking dielectric layer52, a memory material layer54, and a tunneling dielectric layer56within the inter-tier memory openings (121,141) collectively constitute a memory film50. Each adjoining set of a blocking dielectric layer52, a memory material layer54, and a tunneling dielectric layer56within the inter-tier support openings (221,241) collectively constitute a dielectric layer stack150. Each memory film50within an inter-tier memory opening (121,141) can store electrical charges with a macroscopic retention time. Each a dielectric layer stack150within an inter-tier support opening (221,241) is an inactive component that functions merely as an insulating film. In some embodiments, a blocking dielectric layer52may not be present in the memory film50and the dielectric layer stack150at this step, and a blocking dielectric layer may be subsequently formed after formation of backside recesses.

In one embodiment, a first epitaxial pedestal11can be formed at a bottom portion of each first memory opening121and directly on the substrate (9,10), and a vertical semiconductor channel60can be formed directly on a portion of the first epitaxial pedestal11. A second epitaxial pedestal11′ can be formed at a bottom portion of each first support opening221concurrently with formation of the first epitaxial pedestals11, and a bottommost surface of a vertical semiconductor layer160can be formed above, and is vertically spaced from, any material of the second epitaxial pedestal11′ by the second semiconductor oxide portion21′, the support opening fill material portion226, and the dielectric material portion (i.e., etch stop)326.

In one embodiment, each memory stack structure55comprises a memory film50including a first layer stack (52,54,56), and each support pillar structure comprises a second layer stack (52,54,56) such that each layer within the second layer stack (52,54,56) has a same thickness and a same material composition as a corresponding layer within the first layer stack (52,54,56). Each second layer stack (52,54,56) can be formed directly on a top surface of a respective dielectric material portion326.

Referring toFIGS. 43A and 43B, the processing steps ofFIGS. 21A and 21Bcan be performed to form first dielectric cores62, second dielectric cores162, drain regions63, and dummy drain regions163. Each drain region63within an inter-tier memory opening (121,141) is a top active region of a vertical field effect transistor including a respective vertical semiconductor channel60. Each dummy drain region163within an inter-tier support opening (221,241) is electrically inactive. Each dummy drain region163in the inter-tier support openings (221,241) is not subsequently contacted by any contact via structure. The drain regions63and the dummy drain regions163can have the same material composition. In one embodiment, the drain regions63and the dummy drain regions163can be heavily doped. In one embodiment, the drain regions63and the dummy drain regions163can include electrical dopants (p-type dopants or n-type dopants) at an atomic concentration greater than 5.0×1019/cm3.

Each contiguous set of a memory film50, a vertical semiconductor channel60, and an optional first dielectric core62formed within an inter-tier memory opening (121,141) constitutes a memory stack structure55. Each contiguous set of a second semiconductor oxide portion21′, a support opening fill material portion226, a dielectric material portion326, a dielectric layer stack150, a vertical semiconductor layer160, an optional second dielectric core162, and a dummy drain region163formed within an inter-tier support opening (221,241) constitutes a support pillar structure155.

Each support pillar structure155can be located within a respective support opening, i.e., an inter-tier support opening (221,241). The support pillar structure155comprises a vertical semiconductor layer160comprising the same material as a vertical semiconductor channel60, and a dielectric material portion326that electrically isolates the vertical semiconductor layer160from the substrate (9,10). In one embodiment, the dielectric material portions326can be dielectric metal oxide portions that are embedded within a topmost layer within the first tier structure (132,142,270,165) such as the first-tier dielectric cap layer270.

In one embodiment, each support cavity149as formed at the processing steps ofFIGS. 37A and 37Bcan extend through the entirety of the second tier structure (232,242,270,265) but not below the horizontal plane including the top surface of the topmost first sacrificial material layer142(i.e., the horizontal plane including the bottom surface of the first-tier dielectric cap layer270), and each vertical semiconductor layer160does not extend through an underlying dielectric material portion326. The vertical semiconductor layers160may, or may not, protrude into the dielectric material portions326.

Referring toFIGS. 44A and 44B, the second exemplary structure is illustrated after formation of memory stack structures55and support pillar structures155, drain regions63, and dummy drain regions163. Each memory stack structure55is formed in a respective memory cavity49while elements of the support pillar structures155are formed in the support cavities149.

Referring toFIGS. 45A and 45B, the processing steps ofFIGS. 23A, 23B, 24A, 24B, 25A, 25B, 26A, 26B, 27A, and 27Bare performed to replace the first and second sacrificial material layers (142,242) with first and second electrically conductive layers (146,246), and to form a contact level dielectric layer80, a source region61, an insulating spacer74, and a backside contact via structure76as in the first embodiment.

Referring toFIGS. 46A and 46B, the processing steps ofFIGS. 28A and 28Bcan be performed to form additional contact via structures (86,88) as in the first embodiment.

The various exemplary structures of the present disclosure can include a three-dimensional memory device. The three-dimensional memory device can include a first tier structure (132,146,270,165) comprising a first alternating stack of first insulating layers132and first electrically conductive layers146and located over a substrate (9,10); a second tier structure (232,246,70,265) comprising a second alternating stack of second insulating layers232and second electrically conductive layers246and located over the first tier structure (132,1466,270,165); a memory opening (121,141) vertically extending through an entirety of the first tier structure (132,146,270,165) and the second tier structure (232,246,70,265) to a top surface of the substrate (9,10); a support opening (221,241) vertically extending through the entirety of the first tier structure (132,146,270,165) and the second tier structure (232,246,70,265) to the top surface of the substrate (9,10) and laterally offset from the memory openings (121,141); a memory stack structure55located within the memory opening (121,141) and comprising a vertical semiconductor channel60that is electrically connected (i.e., directly or indirectly shorted) to a horizontal semiconductor channel59located within the substrate (9,10); and a support pillar structure155located within the support opening (221,241) and comprising a vertical semiconductor layer160comprising a same material as the vertical semiconductor channel60and a dielectric material portion (21′ or326) that electrically isolates the vertical semiconductor layer160from the substrate (9,10) (e.g., from the a horizontal semiconductor channel59in the substrate (9,10)).

In one embodiment, a bottommost surface of the vertical semiconductor channel60is more proximal to a horizontal plane including to the top surface of the substrate (9,10) than a bottommost surface of the vertical semiconductor layer160is to the horizontal plane including to the top surface of the substrate (9,10).

In one embodiment, the three-dimensional memory device can further include a first epitaxial pedestal11located at a bottom portion of the memory opening (121,141) and contacting the vertical semiconductor channel60and the substrate (9,10), and a second epitaxial pedestal11′ located at a bottom portion of the support opening (221,241) and comprising a same material as the first epitaxial pedestal11and vertically spaced from a bottommost surface of the vertical semiconductor layer160.

In one embodiment, the first epitaxial pedestal11has a greater height than the second epitaxial pedestal11′, and the vertical semiconductor layer160vertically extends through each of the second electrically conductive layers246and a subset of the first electrically conductive layers146as illustrated in the first exemplary structure. In one embodiment, the vertical semiconductor layer160does not extend through all of the first electrically conductive layers146.

In one embodiment, the first epitaxial pedestal11can have a substantially same height as the second epitaxial pedestal11′, and the vertical semiconductor layer160vertically extends through each of the second electrically conductive layers246and does not extend below a horizontal plane including a top surface of a topmost first electrically conductive layer146as illustrated in the second exemplary structure.

In one embodiment, the three-dimensional memory device can include a first semiconductor oxide portion21having an annular shape and laterally surrounding a bottom portion of the vertical semiconductor channel60that extends through the opening in the first semiconductor oxide portion21. The dielectric material portion (21′,326) in this embodiment comprises the second semiconductor oxide portion21′ underlying the vertical semiconductor layer160and having a same composition as the first semiconductor oxide portion21and embodied as, or underlies, the dielectric material portion (21′ or326).

In the first exemplary structure, the dielectric material portion21′ has a greater height than the first semiconductor oxide portion21, and the vertical semiconductor layer160vertically extends through each of the second electrically conductive layers246and a subset of the first electrically conductive layers146.

In some embodiments, the top surface of the dielectric material portion (as embodied as a second semiconductor oxide portion21′) is located between a topmost layer among the first electrically conductive layers146and a bottommost layer among the first electrically conductive layers146as in the first exemplary structure. In one embodiment, the dielectric material portion21′ comprises a semiconductor oxide material doped with electrical dopants.

In the second exemplary structure, the dielectric material portion (21′,326) comprises the dielectric metal oxide etch stop portion326. In this embodiment, the second semiconductor oxide portion21′ underlies the dielectric material portion326and has a substantially same height as the first semiconductor oxide portion21, and the vertical semiconductor layer160vertically extends through each of the second electrically conductive layers246and does not extend below a horizontal plane including a top surface of a topmost first electrically conductive layer146, which can be the horizontal plane including the bottom surface of the first-tier dielectric cap layer270.

In one embodiments, the memory stack structure55comprises a memory film50including a first layer stack ((52,54,56), and the support pillar structure155comprises a second layer stack (52,54,56). Each layer within the second layer stack (52,54,56) has a same thickness and a same material composition as a corresponding layer within the first layer stack (52,54,56). In one embodiment, a bottommost surface of the second layer stack (52,54,56) contacts a top surface of the dielectric material portion326.

In some embodiments, the top surface of the dielectric material portion (as embodied as a dielectric material portion326of the second exemplary structure) is within a same horizontal plane as an interface between the first tier structure (132,146,275,165) and the second tier structure (232,246,75,265). In one embodiment, the dielectric material portion326comprises a dielectric metal oxide, such as aluminum oxide. A support opening fill material portion226(which can include an undoped semiconductor material, i.e., a semiconductor material that is not intentionally doped) and an epitaxial pedestal11′ can underlie the dielectric material portion326, and can be located within the support opening (221,241).

In one embodiment, a terrace region can be provided, in which each electrically conductive layer (146,246) other than a topmost electrically conductive layer within the first and second alternating stacks (132,146,232,246) laterally extends farther than any overlying electrically conductive layer within the first and second alternating stacks (132,146,232,246). The terrace region includes stepped surfaces of the first and second alternating stacks (132,146,232,246) that continuously extend from a bottommost layer within the first and second alternating stacks (132,146,232,246) to a topmost layer within the first and second alternating stacks (132,146,232,246). Each of the support pillar structures155can extend through the stepped surfaces and through a respective retro-stepped dielectric material portion (165or265) that overlies the stepped surfaces. Each of the word line contact via structures86can contact a respective electrically conductive layer among the first and second electrically conductive layers (146,246) in the terrace region.

Each of the first and second exemplary structures can include a three-dimensional memory device. In one embodiment, the three-dimensional memory device comprises a vertical NAND memory device. The electrically conductive layers46can comprise, or can be electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device. The substrate (9,10) can comprise a silicon substrate. The vertical NAND memory device can comprise an array of monolithic three-dimensional NAND strings over the silicon substrate. At least one memory cell (as embodied as a portion of a memory material layer54at a level of an electrically conductive layer46) in a first device level of the array of monolithic three-dimensional NAND strings can be located over another memory cell (as embodied as another portion of the memory material layer54at a level of another electrically conductive layer46) in a second device level of the array of monolithic three-dimensional NAND strings. The silicon substrate can contain an integrated circuit comprising a driver circuit for the memory device located thereon. The electrically conductive layers46can comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate (9,10), e.g., between a pair of backside trenches79. The plurality of control gate electrodes comprises at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level. The array of monolithic three-dimensional NAND strings can comprise: a plurality of semiconductor channels (59,11,60), wherein at least one end portion60of each of the plurality of semiconductor channels (59,11,60) extends substantially perpendicular to a top surface of the substrate (9,10); and a plurality of charge storage elements (as embodied as portions of the memory material layer located at levels of the electrically conductive layers46). Each charge storage element can be located adjacent to a respective one of the plurality of semiconductor channels (59,11,60).

The exemplary structures of the present disclosure electrically isolates the vertical semiconductor layers160of the support pillar structures155from the substrate (9,10) by dielectric material portions (21′ or326), thereby eliminating, or reducing, leakage current from the electrically conductive layers (146,246) to the substrate (9,10) through the support pillar structures155. Thus, the exemplary structures of the present disclosure can be advantageously employed to enhance device performance and/or to increase yield and/or reliability of a three-dimensional memory device.