Dynamic reference current sensing

A circuit comprises a first path, a second path, a current generating circuit, and a sense amplifier. The first path has a first current having a first current value. The second path has a second current having a second current value. The current generating circuit is configured to generate a reference current having a reference current value based on the first current value and the second current value. The sense amplifier is configured to receive a third current having a third current value and to generate a logical value based on the reference current value and the third current value.

FIELD

The present disclosure is related to sensing data based on a dynamic reference current.

BACKGROUND

In an approach, a fixed value of a reference current is used in sensing data for a metal-oxide nitride-oxide semiconductor (MONOS) flash memory cells. For illustration, a flash memory cell is called a flash cell, a memory cell, etc. Further, a sense amplifier compares the value of the flash cell current with the value of the reference current. If the value of the cell current is higher than that of the reference current, the data stored in the flash cell is logically high. But if the value of the cell current is lower than that of the reference current, the data stored in the flash cell is logically low. After the flash cell is programmed and erased many times, such as over about 10,000 times, the flash cell experiences a charge loss. As a result, the cell current decreases. In contrast, the fixed value of the reference current stays the same. Consequently, the data revealed by the sense amplifier could be inaccurate.

DETAILED DESCRIPTION

Embodiments, or examples, illustrated in the drawings are disclosed below using specific language. It will nevertheless be understood that the embodiments and examples are not intended to be limiting. Any alterations and modifications in the disclosed embodiments, and any further applications of the principles disclosed in this document are contemplated as would normally occur to one of ordinary skill in the pertinent art.

Some embodiments have one or a combination of the following features and/or advantages. In some embodiments, data sensing is based on a dynamic reference current. The reference current is dynamic because it varies as the current in a corresponding flash memory cell varies. As a result, the sense or read margin increases.

FIG. 1is a diagram of a circuit100, in accordance with some embodiments. Circuit100is used to illustrate operations of a sense amplifier120, which senses a current Icell of a flash memory cell Fcell10based on a reference current Iref generated by a reference current generating circuit110.

Flash Memory Cell

In some embodiments, flash memory cell Fcell10is manufactured based on metal-oxide nitride-oxide semiconductor (MONOS) technology. After Fcell10is manufactured, Fcell10stores a “neutral” logical value, which is not a low logical nor a high logical value. So that Fcell10stores a low logical value, electrons are injected into the source side of flash cell Fcell10. In other words, injecting electrons into Fcell10programs Fcell10with a low logical value. So that Fcell10stores a high logical value, Fcell10is programmed with a low logical value, and the low logical value is then erased to result in a high logical value.

When Fcell10is accessed, Fcell10draws a current Icell. A value of Icell depends on a logical value stored in Fcell10. For example, if Fcell10stores a low logical value, Icell is relatively low, compared with reference current Iref. In contrast, if current Fcell10stores a high logical value, Icell is relatively high compared with Iref. In some embodiments, sense amplifier120compares a value of Icell with a value of Iref. If the value of Icell is less than the value of Iref, Fcell10stores a low logical value. But if the value of Icell is greater than the value of Iref, Fcell10stores a high logical value.

A line185corresponds to bit line BL inFIG. 4. Details of flash memory cells are explained with reference toFIG. 4.

Reference Current Generating Circuit

Current generating circuit110generates current Iref based on a current Iref0and a current Irfef1.

A reference cell CRef010generates a current Iref0corresponding to current Icell when Fcell stores a low logical value. In some embodiments, reference cell CRef010includes a flash cell Fcell inFIG. 4programmed to store a low logical value. A line177corresponds to bit line BL inFIG. 4.

A stabilization circuit130including an inverter INV10and a transistor N15stabilizes current Iref0. In some embodiments, inverter INV10includes a PMOS transistor (not shown) and an NMOS transistor (not shown). A size in terms of a width W and length L ratio of transistor N15is selected such that a voltage at the gate and at the source of transistor N15is at a specific value. As a result, a voltage drop across the gate and the source of transistor N15is stabilized. A current through transistor N15or current Iref0is therefore stabilized.

A PMOS transistor P10and a PMOS transistor P20generate a current IP20having half a value of current Iref0. Current IP20is a current provided by transistor P20. Current Iref0has the same value as a current drawn by PMOS transistor P10. For illustration, PMOS transistor P10and PMOS transistor P20are configured as a current mirror having a ratio 2:1. As a result, IP20=½ IRef0. In some embodiments, to select a 2:1 ratio, a size of PMOS transistor P20is designed to be about ½ that of PMOS transistor P10.

A reference cell CRef110generates a current Iref1corresponding to current Icell of Fcell10when Fcell10stores a high logical value. In some embodiments, reference cell CRef110includes a flash cell Fcell inFIG. 4programmed to store a high logical value. A line187corresponds to bit line BL inFIG. 4.

A stabilization circuit140with reference to current Iref1corresponds to stabilization circuit130with reference to current Iref0. For example, stabilization circuit140stabilizes current Iref1. Stabilization circuits130and140are shown in current generating circuit110for illustration. Embodiments of the disclosure are not limited to a location of stabilization circuit130or140. For example, at least one of stabilization circuit130or140is not part of current generating circuit110. Further, in some embodiments, at least one of stabilization circuit130or140is not used.

A PMOS transistor P30and a PMOS transistor P40with reference to current Iref1correspond to PMOS transistors P10and P20with reference to current Iref1, respectively. For example, PMOS transistors P30and P40generate a current IP40having half a value of current Iref1. In some embodiments, PMOS transistor P30and PMOS transistor P40are configured as a current mirror having a ratio 2:1. As a result, IP40=½ IRef1. In some embodiments, to select a 2:1 ratio, a size of PMOS transistor P40is designed to be about ½ that of PMOS transistor P30.

Current Iref is the sum of currents IP20and IP40. Mathematically expressed:

Current Iref is thus an average of current Icell when Fcell stores a high and a low logical value. Expressed in another way, current Iref is at the middle point of current Iref0and current Iref1.

An NMOS transistor N10of circuit110and an NMOS transistor N20of sense amplifier120function as a current mirror so that a current IN20is equal to current Iref. Current IN20is a current drawn by NMOS transistor N20. Explained in a different way, NMOS transistor N10converts current Iref to a voltage Vref on a line175provided to a gate of transistor N20. In some embodiments, voltage Vref is provided to a plurality of transistors N20of corresponding sense amplifiers120to sense a plurality of corresponding memory cells Fcells. For example, voltage Vref is provided to 16 transistors N20of corresponding 16 amplifiers120as illustrated with reference toFIG. 2. In such a condition, a pair of reference cells CRef010and CRef110functions with 16 sense amplifiers120and 16 memory cells Fcell inFIG. 4.

Sense Amplifier Circuit

A stabilization circuit150of sense amplifier120stabilizes current Icell in the same manner as stabilization circuit130stabilizing current Iref0. Inverter INV30and NMOS transistor N35correspond to inverter INV10and NMOS transistor N15, respectively. Stabilization circuit150is shown in sense amplifier120for illustration. Embodiments of the disclosure are not limited to a location of stabilization circuit150. For example, stabilization circuit150is not part of sense amplifier120. Further, in some embodiments, stabilization circuit150is not used.

A PMOS transistor P50and a PMOS transistor P60mirror current Icell such that a current IP60equals to current Icell. Current IP60is a current drawn by PMOS transistor P60.

A node NO receives current IP60and current IN20. When current IP60is greater than current IN20, a voltage at node NO increases such that an output circuit160generates an output SO having a high logical value. When current IP60is less than current IN20, however, a voltage at node NO decreases such that output circuit160generates output SO having a low logical value. Because current IP60equals current Icell and current IN20equals current Iref, effectively, when current Icell is greater than current Iref, output SO is logically high. But when current Icell is less than current Iref, output SO is logically low.

Various embodiments of the present disclosure are advantageous over other approaches. For example, both reference cells CRef010and CRef110each includes a flash cell Fcell inFIG. 4. In operation, when flash cell Fcell10is erased, reference cells CRef010and CRef110are also erased. As a result, when characteristics of Fcell10change, characteristics of reference cells CRef010and CRef110change in a similar manner. Further, because reference current Iref is an average of currents Iref0and Iref1, reference current Iref is consistently greater than current Iref0and lesser than current Iref1regardless of whether current Iref0and/or current Iref1changes. Consequently, if a value of cell current Icell changes due to a charge loss of repeated usages over the years, reference current Iref changes accordingly. In other words, a change in the value of current Icell is compensated by a change in the value of current Iref. As a result, a result of comparison by sense amplifier120between reference current Iref and cell current Iref reveals appropriate data.

In the above illustration, a value of current Iref is an average of currents Iref0and Iref1. Expressed differently, current Iref is at the middle point of current Icell when Fcell stores a low and a high logical value. Different values of current Iref are within the scope of the present disclosure. The values of current Iref are adjusted by adjusting the size of transistors P10, P20, P30, and/or P40. Effectively, the size ratio between transistors P10and P20and/or between transistors P30and P40change accordingly. For example, based on a ratio 3:1, IP20=⅓ IP10=⅓ Iref0, and IP40=⅓ IP30=⅓ Iref1. As a result, Iref=IP20+IP40=⅓ (Iref0+Iref1). In some embodiments, based on a predetermined value of current Iref, the size ratio between transistor P10and P20and/or between transistor P30and P40is determined accordingly. In other words, the sizes of transistors P10, P20, P30, and P40are determined accordingly to provide the predetermined current Iref.

Because current Iref is an average of current Iref0and Iref1, current Iref changes as current Iref0and/or current Iref1changes. As a result, current Iref is a dynamic current, and sensing the data of Fcell10based on current Iref is called dynamic current sensing.

Memory Array

FIG. 2is a block diagram of a memory array200, in accordance with some embodiments. Memory array200uses the dynamic current sensing mechanism illustrated inFIG. 1. Memory array200includes column segments GC1to GC16, and current reference segments Ref0and Ref1.

With reference to column segments GC1to GC16, for simplicity, details of only segment GC1are shown, but are also applicable to segments GC2to GC16. In some embodiments, segment GC1includes 64 columns divided into 8 (sub) segments GC1-1to GC1-8. Further, each segments GC1-1to GC1-8includes 8 columns (not shown).

Also for simplicity, details of reference current segment Ref0are shown, but are also applicable to current reference segment Ref1. In some embodiments, segment Ref0includes 8 columns Ref0-1to Ref0-8. Similarly, segment Ref1also includes 8 columns Ref1-1to Ref1-8(not shown).

In some embodiments, in operation, one column in each of a corresponding segment GC1to GC16is active at a time and functions with a corresponding pair of columns of corresponding current reference segments Ref0and Ref1. Effectively, 16 columns from 16 segments GC1to GC16function with a pair of columns of segments Ref0and Ref1. For example, one column in segment Ref0and one column in segment Ref1operate as a pair and function with a corresponding segment GC1-1to GC1-8of segment GC1, a corresponding segment GC2-1to GC2-8(not shown) of segment GC2, a corresponding segment GC3-1to GC3-8(not shown) of segment GC3, etc., for a total of 16 columns of segments GC1to GC16. For simplicity of discussion, one column in a segment is described, but the description is applicable to the other 15 columns. For example, a pair comprising columns Ref0-1and Ref1-1function with segment GC1-1of GC1. A pair comprising columns Ref0-2and Ref1-2function with segment GC1-2of GC1, and a pair comprising columns Ref0-3and Ref1-3function with segment GC1-3of GC1, etc.

For another example, when any one of 8 columns in segment GC1-1is active, a corresponding pair of Ref0-1and Ref1-1is selected to function with the active column in segment GC1-1. For another example, when any one of 8 columns in segment GC1-2is active, a corresponding pair of Ref0-2and Ref1-2is selected to function with the active column in segment GC1-2, and when any one of 8 columns in segment GC1-3is active, a corresponding pair of Ref0-3and Ref1-3is selected to function with the active column in segment GC1-3, etc.

Memory Array and Sense Amplifier Circuit

FIG. 3is a diagram of a circuit300, in accordance with some embodiments. Circuit300is used to illustrate how circuit100inFIG. 1is used in conjunction with memory array200inFIG. 2. For illustration, segment GC1-1of segment GC1of memory array200is used with segments Ref0and Ref1, and is shown. Segments GC1-2to GC1-8of GC1used with segments Ref0and Ref1are in a manner similar to segment GC1-1being used with segments Ref0and Ref1. In some embodiments, segments GC1-2to GC1-8of segment GC1are also input into a multiplexer310as segment GC1-1. Effectively, 8 segments GC1-1to GC1-8of segments GC1are input into multiplexer310. Segments GC1-2to GC1-8are used with segments Ref0and Ref1in a manner similar to segment GC1-1being used with segments Ref0and Ref1. Segments GC2to GC16used with segments Ref0and Ref1are in a similar manner as segment GC1being used with segments Ref0and Ref1. Effectively, in some embodiments, 16 multiplexers310correspond to 16 segments GC1to GC16.

Segment GC1-1includes 8 columns each corresponding to a bit line BL inFIG. 4. As illustratively shown, segment GC1-1includes 8 bit line BL1to BL8. In some embodiments, each bit line BL1to BL8is coupled with 64 flash memory cells Fcell. For simplicity, flash memory cells Fcell coupled with bit line BL1are shown, and one memory cell Fcell of bit line BL1is labeled.

Effectively, in the illustration ofFIG. 3, the flash memory cells coupled with bit lines BL1to BL8form an array having 8 columns and 64 rows. Flash memory cells in a row are coupled with a word line WL inFIG. 4. As illustratively shown, 64 rows of GC1-1correspond to 64 word lines WL1to WL64.

Similarly, segment Ref0includes 8 bit line RBL1to RBL8. In some embodiments, each bit line RBL1to RBL8of segment Ref0is also coupled with 64 reference cells CRef0. For simplicity, reference cells of bit line RBL1of section Ref0are shown, and one reference cell CRef0is labeled. In some embodiments, a reference cell CRef0includes a flash memory cell Fcell programmed with a low logical value. Effectively, the reference cells CRef0coupled with bit lines RBL1to RBL8of segment Ref0form an array with 8 columns and 64 rows. Reference cells in a row of section Ref0are coupled with a word line of section Ref0. As illustratively shown, 64 rows in segment Ref0correspond to 64 word lines RWL1to RWL64.

Segment Ref1also includes 8 bit lines RBL1to RBL1. Each bit line RBL1to RBL8of Ref1is coupled with 64 reference cells CRef1. For simplicity, reference cells coupled with bit line RBL1of segment Ref1are shown, and one reference cell CRef1is labeled. In some embodiments, a reference cell CRef1includes a flash memory cell Fcell programmed with a high logical value. Effectively, the reference cells CRef1coupled with bit line RBL1to RBL8of segment Ref1form an array with 8 columns and 64 rows. Reference cells CRef1in a row of section Ref1are coupled with a word line of section Ref1. As illustratively shown, 64 rows in segment Ref1correspond to 64 word lines RWL1to RWL64. Because each of word lines RWL1to RWL64also controls a row of reference cells CRef0, each of word lines RWL1to RWL64controls the same row of Ref0and Ref1.

InFIG. 3, 64 rows in segment GC1-1and segments Ref0, Ref1are used for illustration. A different number of rows is within the scope of the present disclosure.

In operation, a multiplexer310selects a memory cell Fcell in a column and a row of segment GC1-1to be sensed. For illustration, multiplexer310selects memory cell Fcell10represented by a dashed box that is coupled with word line WL1and bit line BL1of segment GC-1.

A multiplexer320selects a reference cell CRef0in a column and a row of segment Ref0to be used in sensing the selected memory cell Fcell10. For illustration, multiplexer320selects reference cell CRef010represented by a dashed box that is coupled with word line RWL1and bit line RBL1of segment Ref0.

In some embodiments, the column of the selected reference cell CRef010corresponds to the selected column of the selected memory cell Fcell10. For example, because the selected memory cell Fcell10is coupled with bit lint BL1of segment GC1-1, the selected reference cell CRef010is also coupled with bit line RBL1of segment Ref0. But if the selected memory cell Fcell10is coupled with another bit line of segment GC1-1, such as bit line BLi where i is an integer number, the selected reference cell CRef010is also coupled with a corresponding read bit line RBLi of segment Ref0.

A multiplexer330selects a reference cell CRef1in a column and a row of segment Ref1to be used with the selected reference cell CRef010to sense the selected memory cell Fcell10. For illustration, multiplexer330selects reference cell Cref110represented by a dashed box. Further, because the selected memory cell Fcell10and reference cell CRef010are coupled with corresponding bit lines BL1and RBL1, in some embodiments, the selected reference cell CRef110is also coupled with corresponding read bit line RBL1of section Ref1.

Multiplexers310,320, and330are used for illustration. Other ways to identify a corresponding flash memory cell Fcell, reference cell CRef010, or CRef100are within the scope of various embodiments. For example, in some embodiments, a flash memory cell, a reference cell CRef010, or CRef110is identified by a decoder based on corresponding address of the corresponding cell.

Flash Memory Cell, Circuit Diagram

FIG. 4is a circuit diagram of a flash memory cell Fcell, in accordance with some embodiments. Memory cell Fcell includes a transistor410having four terminals serving as a bit line BL, a source line SL, a word line WL, and a control gate CG. Memory cell Fcell has a split gate region in which a first half of the gate region is coupled with word line WL and a second half of the gate region is coupled with control gate CG. When both word line WL and control gate CG are activated, for example with a high logical value, memory cell Fcell is activated. Source line SL is grounded.

In some embodiments, memory cell Fcell is programmed with a low logical value to generate reference cell CRef010, or is programmed with a high logical value to generate reference cell CRef110. In such a situation, word line WL corresponds to one of word line RWL1to RWL64inFIG. 3, and bit line BL corresponds to one of bit line RBL1to RBL8.

Flash memory cell Fcell inFIG. 4is used for illustration. Other memory cells and/or other configurations of flash memory cells are within the contemplated scope of the present disclosure.

Method

FIG. 5is a flowchart of a method500, in accordance with some embodiments. Method500is used to illustrate operations of circuit300inFIG. 3.

In operation510, flash memory cell Fcell10is selected to be sensed. In some embodiments, a word line and a bit line corresponding flash memory cell Fcell10are activated, and multiplexer310selects flash memory cell Fcell10.

In operation520, a pair of reference cells CRef010and CRef110is selected to be used in sensing the selected memory cell Fcell10. In some embodiments, a word line and a bit line corresponding to reference cell CRef010are activated, and multiplexer320selects reference cell CRef010. Further, a word line and a bit line corresponding to reference cell CRef110are activated, and multiplexer330selects reference cell CRef110.

In operation530, current generating circuit100inFIG. 1, based on reference cells CRef010and CRef110, generates current Iref and voltage Vref for use by sense amplifier120.

In operation540, sense amplifier120, based on current Icell generated by flash memory cell Fcell10and reference current Iref, generates output SO. The logical value on output SO indicates a corresponding logical value stored in flash memory cell Fcell10.

In some embodiments, a circuit comprises a first path, a second path, a current generating circuit, and a sense amplifier. The first path has a first current having a first current value. The second path has a second current having a second current value. The current generating circuit is configured to generate a reference current having a reference current value based on the first current value and the second current value. The sense amplifier is configured to receive a third current having a third current value and to generate a logical value based on the reference current value and the third current value.

In some embodiments, in a method, a first current and a second current are generated. A reference current is generated based on the first current and the second current. A logical value is generated based on a value of the reference current and a value of a current of a device. The first current has a first value corresponding to a value of the current of the device when the device is in a first state. The second current has a second value corresponding to a value of the current of the device when the device is in a second state different from the first state.

In some embodiments, a circuit comprises a plurality of cells, a plurality of first reference cells, a plurality of second reference cells, a first selection circuit, a second selection circuit, a third selection circuit, a current generating circuit, and a sense amplifier. The plurality of first reference cells is programmed to a first logical value of a cell of the plurality of the cells. The plurality of second reference cells is programmed to a second logical value of the cell of the plurality of the cells, wherein the first logical value is different from the second logical value. The first selection circuit is configured to select the cell of the plurality of cells. The second selection circuit is configured to select a first reference cell of the plurality of first reference cells. The third selection circuit is configured to select a second reference cell of the plurality of second reference cells. The current generating circuit is configured to generate a reference current based on the selected first reference cell and the selected second reference cell. The sense amplifier is configured to compare a value of the reference current and a value of a current of the selected cell of the plurality of cells.

A number of embodiments have been described. It will nevertheless be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, various transistors being shown as a particular dopant type (e.g., N-type or P-type Metal Oxide Semiconductor (NMOS or PMOS)) are for illustration purposes. Embodiments of the disclosure are not limited to a particular type. Selecting different dopant types for a particular transistor is within the scope of various embodiments. The low or high logical value of various signals used in the above description is also for illustration. Various embodiments are not limited to a particular logical value when a signal is activated and/or deactivated. Selecting different logical values is within the scope of various embodiments. In various embodiments, a transistor functions as a switch. A switching circuit used in place of a transistor is within the scope of various embodiments. In various embodiments, a source of a transistor can be configured as a drain, and a drain can be configured as a source.

The above illustrations include exemplary operations, but the operations are not necessarily performed in the order shown. Operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of disclosed embodiments.