Auxiliary output driver

A BiCMOS auxiliary output driver is provided to maintain output logic signal levels when integrated circuit chip power supply voltage is outside its nominal range. When the power supply voltage level is within design tolerance for a MOSFET output driver stage, the auxiliary output driver is off; when below design tolerance, the auxiliary output driver is turned on. Driver stage output pad signal level is maintained at a desired state level by the auxiliary output driver whenever the power supply slips below its design tolerance range.

CROSS-REFERENCE TO RELATED APPLICATIONS

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REFERENCE TO AN APPENDIX

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BACKGROUND

1. Technical Field

The technology described herein is generally related to the field of integrated circuits (“IC”); IC structures and devices are also referred to hereinafter as “chip(s),” and “dice” or “die.”

2. Description of Related Art

The integrated circuit field of technology is well established. Many publications describe the details of commonly known techniques used in the fabrication of integrated circuits that can be generally employed in the fabrication of complex, three-dimensional, IC structures and devices; see e.g.,Silicon Processes, Vol. 1–3, copyright 1995, Lattice Press, Lattice Semiconductor Corporation, Hillsboro, Oreg. Moreover, the individual steps of such a process can be performed using commercially available IC fabrication machines. The use of such machines and commonly used fabrication step techniques will be referred to hereinafter as simply: “in a known manner.” As specifically helpful to an understanding of the present invention, approximate technical data are disclosed herein based upon current technology; future developments in this art may call for appropriate adjustments as would be apparent to one skilled in the art.

Certain commercial products employing IC chips require the state of a digital output signal stays at a predetermined logic signal, “HIGH” or “LOW,” even when supply voltages are below the threshold voltage of the output stage driver field effect transistors (“FETs”). For example, a voltage monitoring instrument needs to transmit accurately the true output of the circuitry being monitored. Other examples of such products are power-on reset generators, microprocessor supervisors, and chip-select drivers.

Known manner complementary metal-oxide-semiconductor (“CMOS”) circuit designs may not result in a “guaranteed” output state when the supply voltage falls below a threshold voltage of the output stage driver FETs. On the other hand, lowering the threshold voltage may improve performance of an IC, but generally requires a change to the wafer-level IC dice fabrication processes. However, lowering the threshold voltage may have undesired electrical effects such as increasing leakage currents. Therefore, there are competing interests for the IC designer to consider.

There is a need for improved electronic circuits for commercial products where output stage signals are a critical factor of performance.

BRIEF SUMMARY

The present invention generally provides for an integrated circuit output driver stage for ensuring a predetermined output when power supply voltage falls below an expected level.

The foregoing summary is not intended to be inclusive of all aspects, objects, advantages and features of the present invention nor should any limitation on the scope of the invention be implied therefrom. This Brief Summary is provided in accordance with the mandate of 37 C.F.R. 1.73 and M.P.E.P. 608.01(d) merely to apprise the public, and more especially those interested in the particular art to which the invention relates, of the nature of the invention in order to be of assistance in aiding ready understanding of the patent in future searches.

Like reference designations represent like features throughout the drawings. The drawings in this specification should be understood as not being drawn to scale unless specifically annotated as such.

DETAILED DESCRIPTION

FIG. 1is an electrical schematic diagram for a circuit100in accordance with a first exemplary embodiment of the present invention. Standard electrical engineering symbols and conventions are shown in this layout such that a person skilled in the art will recognize the components and their respective interconnections. While the exemplary embodiments described herein is illustrative of using semiconductor devices having a specific transistor polarity implementation, it will be recognized by those skilled in the art that an implementation of reverse polarity devices can be made. No limitation on the scope of the invention is intended by the exemplary embodiments and none should be implied therefrom. An experimental implementation was constructed in a BiCMOS technology process; device sizes and the like may be adjusted as would be evident to persons skilled in the art for scaling the components and adapting the present invention to a specific implementation.

A CMOS Output Driver101is a typical known manner, output driver having four metal oxide semiconductor field effect transistors (“MOSFET”) MP1, MP2, MN1, MN2and forming an output driver stage on-board a chip, not shown. The Driver101is designed for receiving digital logic signals—represented by “In” symbol105—at an input node103from on-board chip circuitry, not shown, and providing an amplified output signal at the output driver stage output node107. A power supply voltage, Vss, for example, a known manner DC volt source, not shown, provide a nominal design voltage, or can be an electrical ground. A drain-source bias voltage, VDD, for the MOSFETs MP1, MP2, MN1, MN2of this embodiment is, for example, a known manner 3.3 volt ±0.3 DC source, not shown.

Generally, when the voltage VDDis at its design nominal value, it is well above the threshold voltage for the MOSFETs MP1, MP2, MN1, MN2, the voltage at the output driver stage output node107will be LOW when the signal In105is LOW and HIGH when the signal In105is HIGH. However, when the signal In105is LOW and the voltage VDDapproaches or falls below the threshold voltage, the state of the output driver stage at output node107can float up from the LOW state since there is not enough voltage on the gate line109of MOSFET MN2to keep MOSFET MN2in the ON state.

In accordance with the exemplary embodiment of the present invention in a bipolar-CMOS (“BiCMOS”) implementation, an Auxiliary Driver111is added to the chip output stage. The function of the Auxiliary Driver111is to supplement output signal driving at low VDDvoltages and to ensure that output at the output pad113of the chip remains LOW. The output pad113of the chip is connected to CMOS Output Driver101output node107via line115and Auxiliary Driver output node117.

When the voltage VDDis at or above its design nominal value, the gate119of Auxiliary Driver MOSFET MN4is pulled up; that is, it may be considered at a logic HIGH level. This removes the base drive signal from npn-type bipolar transistor Q3. Removing the base drive signal from bipolar transistor Q3removes the base drive signal from pnp-type bipolar transistor Q2. Therefore, for VDD=HIGH, the Auxiliary Driver111is OFF and so it does not influence the state of the output signal at output pad113.

When the voltage VDDdrops below the threshold voltage for Auxiliary Driver MOSFET MN4, the drain121is pulled up by the voltage drop across bias resistor R16, sized appropriately to the specific implementation. The current, “I,” through resistor R16, represented by arrow123, is forced on a circuit path to the base125of npn-type bipolar transistor Q3. The collector127of bipolar transistor Q3draws current out of the base126of the transistor Q2. The collector129of transistor Q2pushes current into the base131of npn-type bipolar transistor Q1. The collector133of transistor Q1now draws node117LOW. Thus, the output pad113LOW condition is maintained appropriately. In other words, by turning on the Auxiliary Driver111whenever the voltage VDDfalls below the design threshold voltage for driving the CMOS Output driver101, a LOW output signal is guaranteed at the associated output pad113.

Note that another advantage of the circuit100of the present invention is that the output pad113LOW condition remains at the LOW digital signal value even if there is significant external impedance from the device output to the positive supply, such as via a pull-up resistor, not shown.

In the preferred embodiment, the threshold voltage of Auxiliary Driver MOSFET MN4should be substantially equivalent to the threshold voltage of CMOS Output Driver MOSFET MN2. In this manner, the Auxiliary Driver111begins to operate at the supply voltage when it is most needed.

In the preferred embodiment, another MOSFET transistor M13is connected in Auxiliary Driver111so that leakage current from the collector127to the emitter128will not erroneously turn transistors Q1and Q2ON.

Similarly, in the preferred embodiment, another MOSFET transistor M12is connected in Auxiliary Driver111so that leakage current in transistor Q2from the collector129to the emitter130will not erroneously turn transistor Q1ON.

In the preferred embodiment a resistor, “Resd,”133, is provided to protect the gate of Auxiliary Driver MOSFET MN4from electrostatic discharge into the supply voltage VDDor VSS.

Thus, it can be recognized that the circuit100is capable of providing a substantial amount of sink current so that the output voltage will be a logic LOW even when the voltage VDDfalls lower that specified. Any pull-up resistance voltage drop that this circuit100may have to drive will also be established at logic LOW. The maximum amount of drive is determined by the gains of the bipolar transistors and the value of the bias resistor R16.

FIG. 2is an electrical schematic diagram in accordance with another exemplary embodiment. It will be recognized by those skilled in the art that this is a complementary version of the circuit100shown inFIG. 1, built to guarantee that an output213stays HIGH at node217at low power supply voltage levels.

As withFIG. 1, a CMOS Output Driver101is a typical known manner, output driver having four metal oxide semiconductor field effect transistors (“MOSFET”) MP1, MP2, MN1, MN2and forming an output driver stage on-board a chip, not shown. It may similarly be advantageous to ensure a logic signal HIGH on the Output Driver output signal line115. Again, however, when the In signal105is HIGH and the voltage VDDapproaches or falls below output driver MOSFET MP1, MP2, MN1, MN2threshold voltage, the state of the output of the CMOS Output Driver101can float down on its output line115as there will then not be enough voltage on the gate209of driving MOSFET MP2to maintain an ON condition. The Auxiliary Driver211is added to supplement the CMOS Output Driver101when the voltage VDDfalls below the threshold voltage level needed for the output driver stage MOSFETs MP1, MP2, MN1, MN2.

When the voltage VDDis at its design nominal level, the gate219of auxiliary driver MOSFET MP4is pulled down, viz., to a logic LOW level. This removes base drive signal from a pnp-type bipolar transistor Q3′. Consequently, the base drive signal is removed from a npn-type bipolar transistor Q2′ which in turn remove the base drive signal from a pnp-type bipolar transistor Q1′. Thus, for voltage VDDat its nominal level, the Auxiliary Driver remains in an OFF condition.

When the voltage VDDdrops below its design nominal level and, therefore is not sufficient for operation of the CMOS Output Drive101, the drain221of transistor MP4is pulled down by bias resistor R16′. The current, represented by arrow223labeled “I,” through R16′ can come from nowhere else but the base225of bipolar transistor Q3′. The collector227of transistor Q3′ then pushes current into the base226of transistor Q2′. In turn, the collector229of transistor Q2′ pulls current out of the base231of transistor Q1′. The collector233of transistor Q1′ is pulled to a logic level HIGH; this occurs even if there is significant external impedance, such as a pull-down resistor, not shown, from the output pad213to ground.

As with the embodiment ofFIG. 1, the threshold voltage for Auxiliary Driver211transistor MP4should be substantially the same as the threshold voltage for CMOS Output Driver201transistor MP2in order for the Auxiliary Driver211to begin to operate only when the supply voltage VDDis out of its nominal design value.

In a preferred embodiment, electrostatic discharge protection resistor, “Resd,”232is provided to protect the gate219of transistor MP4.

In a preferred embodiment, an auxiliary driver MOSFET transistor M13′ is connected so that leakage current from the emitter228to collector227of transistor Q3′ will not errantly turn transistor Q2′ and Q1′ ON.

In a preferred embodiment, an auxiliary driver MOSFET transistor M12′ is connected so that leakage current from collector230to emitter229in Q2′ will not erroneously turn transistor Q1′ ON.

Thus, it can be recognized that the circuit200is capable of providing a substantial amount of source current so that the output voltage will be a logic HIGH even when the supply voltage VDDfalls lower that specified. Any pull-down resistance voltage drop that this circuit200may have to drive will also be established at logic HIGH. The maximum amount of drive is determined by the gains of the bipolar transistors and the value of the bias resistor R16′.

It is important to note for both described exemplary embodiments that once the supply voltage drops to the level where the Auxiliary Driver111or211becomes activated, the output state113,213, respectively, will be at the desired state—namely, LOW inFIG. 1or HIGH in FIG.2—independent of the input state. In many cases, once the supply voltage gets too low, whatever is driving the input105may no longer be a known, defined state.