IMAGING DEVICE AND ELECTRONIC APPARATUS

An imaging device according to an embodiment of the present disclosure includes: a first substrate; and a second substrate. The first substrate includes one or more sensor pixels that each perform photoelectric conversion. The second substrate is stacked on the first substrate and electrically coupled to the first substrate. The second substrate includes a transistor that operates in a full depletion mode.

TECHNICAL FIELD

The present disclosure relates to an imaging device having a three-dimensional structure and an electronic apparatus including the imaging device.

BACKGROUND ART

For example, PTL 1 discloses an imaging device in which a wafer provided with a plurality of solid-state imaging elements and a wafer provided with a memory circuit, a logic circuit, and the like are stacked.

CITATION LIST

Patent Literature

SUMMARY OF THE INVENTION

Incidentally, an imaging device is requested to be miniaturized.

It is desirable to provide an imaging device and an electronic apparatus that each make it possible to achieve miniaturization.

An imaging device according to an embodiment of the present disclosure includes: a first substrate; and a second substrate. The first substrate includes one or more sensor pixels that each perform photoelectric conversion. The second substrate is stacked on the first substrate and electrically coupled to the first substrate. The second substrate includes a transistor that operates in a full depletion mode.

An electronic apparatus according to an embodiment of the present disclosure includes the imaging device according to the embodiment of the present disclosure described above.

In the imaging device according to the embodiment of the present disclosure and the electronic apparatus according to the embodiment, the transistor that operates in the full depletion mode is used as a transistor provided in the second substrate stacked on the first substrate including the one or more sensor pixels. This reduces a thickness of the second substrate.

MODES FOR CARRYING OUT THE INVENTION

The following describes an embodiment of the present disclosure in detail with reference to the drawings. The following description is a specific example of the present disclosure, but the present disclosure is not limited to the following modes. In addition, the present disclosure is not also limited to the disposition, dimensions, dimension ratios, and the like of the respective components illustrated in the respective diagrams. It is to be noted that description is given in the following order.

1. First Embodiment (an example of an imaging device in which an analog circuit provided in a second substrate includes a transistor that operates in a full depletion mode)

1-1. Configuration of Imaging Device

1-2. Method of Manufacturing Imaging Device

1-3. Workings and Effects

2. Modification Examples

2-1. Modification Example 1 (another example of a structure of a transistor provided in a second substrate)
2-2. Modification Example 2 (an example in which a plurality of second substrates is stacked)
2-3. Modification Example 3 (an example in which one of a plurality of second substrates is provided with a pixel circuit)
2-4. Modification Example 4 (an example in which a second substrate is provided with a functional element)
2-5. Modification Example 5 (an example in which a first substrate and a second substrate are bonded face to face)
3. Second Embodiment (an example of an imaging device in which an analog circuit and a logic circuit are electrically coupled to each other for each of pixels)
4. Third Embodiment (an example of wafer on wafer on wafer (WoWoW))

5. Application Example

6. Practical Application Examples

1. FIRST EMBODIMENT

FIG.1schematically illustrates an example of a cross-sectional configuration of an imaging device (imaging device1) according to a first embodiment of the present disclosure.FIG.2is an exploded perspective view of a schematic configuration of the imaging device1illustrated inFIG.1. The imaging device1has a three-dimensional structure in which three substrates including a first substrate100, a second substrate200, and a third substrate300are stacked in this order. The imaging device1is a back-illuminated imaging device in which light comes from a back surface side of the first substrate100. The imaging device1according to the present embodiment includes a transistor that operates in a full depletion mode as a transistor of the second substrate200.

(1-1. Configuration of Imaging Device)

In the imaging device1, the first substrate100, the second substrate200, and the third substrate300are stacked in this order as described above. The first substrate100includes a pixel array unit110in which a plurality of sensor pixels11is disposed in an array. The second substrate200is provided, for example, with an analog circuit210that is electrically coupled to the pixel array unit110. This analog circuit210includes a transistor that operates in the full depletion mode. The third substrate300is provided, for example, with logic circuits (logic circuits310and320) and memories such as a Magnetoresistive Random Access Memory (MRAM)330and a Dynamic Random Access Memory (DRAM)340that are electrically coupled to the analog circuit210described above.

The first substrate100includes a semiconductor substrate10and a wiring layer40. The semiconductor substrate10has a first surface (front surface)10S1and a second surface (back surface or light incidence surface)10S2that are opposed to each other. The wiring layer40is provided on the first surface10S1side of the semiconductor substrate10. The second surface10S2side of the semiconductor substrate10is provided, for example, with a color filter51and a light receiving lens52. The second substrate200includes a semiconductor substrate20and wiring layers60and70. The semiconductor substrate20has a first surface (front surface)20S1and a second surface (back surface)20S2that are opposed to each other. The first surface20S1side and the second surface20S2side of the semiconductor substrate20are respectively provided with the wiring layer70and the wiring layer60. The first substrate100and the second substrate200are stacked with the wiring layer40and the wiring layer60interposed in between. The wiring layer40is provided on the first surface10S1side of the semiconductor substrate10. The wiring layer60is provided on the second surface20S2side of the semiconductor substrate20. In other words, the first substrate100and the second substrate200are stacked face to back. In the third substrate300, a semiconductor substrate30and a wiring layer80are stacked on a support substrate350in this order. The third substrate300and the second substrate200are stacked with the wiring layer70and the wiring layer80interposed in between. The wiring layer70is provided on the first surface20S1side of the semiconductor substrate20. The wiring layer80is provided on a first surface (front surface)30S1side of the semiconductor substrate30. In other words, the second substrate200and the third substrate300are stacked face to face.

As described above, the first substrate100includes the pixel array unit110in which the plurality of sensor pixels11is disposed in an array. For example, photodiodes PD (light receiving elements12) are formed in the plurality of sensor pixels11to be buried in the semiconductor substrate10. The photodiodes PD (light receiving elements12) each perform photoelectric conversion. Although not illustrated, the semiconductor substrate10is further provided, for example, with one floating diffusion FD, one transfer transistor TR, or the like for each of the sensor pixels11. Alternatively, the semiconductor substrate10is further provided with the one floating diffusion FD, the one transfer transistor TR, or the like for the plurality of sensor pixels11. In the wiring layer40, for example, a wiring line that is coupled to the floating diffusion FD, a wiring line including a gate of the transfer transistor TR, and the like are formed in an interlayer insulating layer42. One or more pad electrodes41are exposed on a surface (specifically, a surface of the interlayer insulating layer42) of the wiring layer40. The one or more pad electrodes41are used, for example, to bond and electrically couple the first substrate100to the second substrate200. Although not illustrated, these pad electrodes41are each coupled to the floating diffusion FD and the gate of the transfer transistor TR, for example, through a via V1.

The second substrate200is provided with the analog circuit210as described above. The analog circuit210is, for example, a portion of an analog digital converter (ADC) of the imaging device1, a control section that controls each of sections in the imaging device1, or the like. The analog circuit210includes a circuit component that is supplied with a power supply voltage for the analog circuit. Specifically, the analog circuit210includes a variety of transistors (pixel circuits), a vertical drive circuit, a comparator and a counter of the ADC, a reference voltage supply section, a Phase Locked Loop (PLL) circuit, and the like. The variety of transistors (pixel circuits) read out analog pixel signals from the sensor pixels11. The vertical drive circuit drives the sensor pixels11row by row. The sensor pixels11are two-dimensionally arranged in a lattice in row and column directions. The reference voltage supply section supplies the comparator with a reference voltage.

In the present embodiment, a transistor provided in the second substrate200has a transistor structure in which the transistor operates in the full depletion mode. Examples of the transistor that operates in the full depletion mode include Fin-FET. The Fin-FET includes a plurality of fins211and a gate711. The plurality of fins211includes, for example, the semiconductor substrate20.

Fins221each have a flat plate shape. For example, the plurality of fins221stands, for example, on the semiconductor substrate20. In other words, the plurality of fins221is each supported by the semiconductor substrate20. The plurality of fins221is disposed, for example, in an X axis direction and each extends in a Y axis direction. There is provided an insulating film including, for example, SiO2on the semiconductor substrate20. The insulating film is included in an element isolation region212described below. The fins221stand to penetrate this insulating film. In other words, a portion of each of the fins221is buried in the insulating film. A side surface and an upper surface of the fin221exposed from the insulating film are covered with a gate insulating film (not illustrated) including, for example, HfSiO, HfSiON, TaO, TaON, or the like. The gate711extends across the plurality of fins221in the X axis direction intersecting an extending direction (Y axis direction) of the fins221. A channel region is formed at a portion of each of the fins221at which the fin221intersects the gate711. Source/drain regions are formed at both ends of the fin221with the channel region interposed in between.

The semiconductor substrate20is divided into a plurality of portions, for example, by the element isolation region212having, for example, a Shallow Trench Isolation (STI) structure, a Deep Trench Isolation (DTI), or Full Trench Isolation (FTI) structure. The respective portions of the semiconductor substrate20divided by the element isolation region212are provided with transistors that each operate in the full depletion mode like the Fin-FET described above. A thickness (h) of the semiconductor substrate20that couples the plurality of fins221to each other is, for example, 1 μm or less (FIG.1).

It is to be noted that the semiconductor substrate20extending in an XY plane direction is for supporting the plurality of fins221as described above. The thickness (h) of the semiconductor substrate20is not therefore limited to the above. The thickness (h) of the semiconductor substrate20may be, for example, 100 nm or less. Alternatively, the thickness (h) of the semiconductor substrate20may be 20 nm or less. In a case where the semiconductor substrate20has a thickness of about 20 nm, it is possible for the semiconductor substrate20to sufficiently support the plurality of fins. In addition, in the present embodiment, no impurity region is formed in the semiconductor substrate20extending in the XY plane direction, but an impurity region may be formed by implanting ions.

One or more pad electrodes61are exposed on a surface of the wiring layer60. The one or more pad electrodes61are used, for example, to bond and electrically couple the second substrate200to the first substrate100. In the wiring layer70, a wiring line71or the like is formed in an interlayer insulating layer73. The wiring line71includes the gate711of the Fin-FET described above. One or more pad electrodes72are exposed on a surface (specifically, a surface of the interlayer insulating layer73) of the wiring layer70. The one or more pad electrodes72are used, for example, to bond and electrically couple the second substrate200to the third substrate300. These pad electrodes61and72exposed on the surfaces of the second substrate200on the first substrate100side and the third substrate300side are electrically coupled to each other by a via V2, the wiring line71, and a via V3. The via V2penetrates the element isolation region212. The wiring line71is provided in the same layer as that of the gate711. The via V3is provided between the wiring line71and the pad electrode72.

As described above, in the third substrate300, the semiconductor substrate30and the wiring layer80are stacked on the support substrate350in this order. The first surface30S1of the semiconductor substrate30is provided, for example, with the logic circuits310and320, the MRAM330, the DRAM340, and the like. The logic circuits310and320are different from each other in technology node. Each of the logic circuits is provided with a circuit that performs various kinds of signal processing on data resulting from photoelectric conversion or data resulting from an imaging operation by the imaging device1. In addition, the logic circuit may include a circuit component that is a portion of the ADC, the control section, or the like and is supplied with a power supply voltage for the logic circuit.

It is to be noted that the power supply voltages for the circuits (e.g., the logic circuits310and320) provided in the third substrate300are preferably lower than the power supply voltage for the circuit (e.g., the analog circuit210) provided in the second substrate200. In other words, it is preferable that the third substrate300be provided with the logic circuits310and320each of which includes a transistor that is driven by using a power supply voltage lower than a power supply voltage of a transistor included in the analog circuit210provided in the second substrate200. This is not, however, limitative. The third substrate300may be further provided with a circuit (e.g., an analog circuit) including a transistor that is driven by using a higher power supply voltage than the power supply voltage of the transistor provided in the second substrate200. Alternatively, a circuit including a transistor that is driven by using a lower power supply voltage than the power supply voltage of the transistor provided in the third substrate300may be further formed in the second substrate200.

The wiring layer80is provided on the first surface30S1side of the semiconductor substrate30. One or more pad electrodes81are exposed on a surface (specifically, a surface of an interlayer insulating layer82) of the wiring layer80. The one or more pad electrodes81are used, for example, to bond and electrically couple the third substrate300to the second substrate200. Each of the plurality of pad electrodes81is coupled to the logic circuit310or320, the MRAM330, or the DRAM340, for example, through a via V4.

The first substrate100, the second substrate200, and the third substrate300are joined together and electrically coupled by bonding pad electrodes to each other that are exposed on the surfaces opposed to each other. Each of the pad electrodes (the pad electrodes41,61,72, and81) is formed by using, for example, metal such as Cu (copper). In other words, the first substrate100and the second substrate200, and the second substrate200and the third substrate300are bonded to each other by metal bonding (e.g., Cu—Cu bonding).

(1-2. Method of Manufacturing Imaging Device)

It is possible to manufacture the imaging device1according to the present embodiment, for example, as follows.

First, as illustrated inFIG.3A, a silicon (Si) substrate is, for example, prepared as the semiconductor substrate20. Subsequently, as illustrated inFIG.3B, a fragile layer213is formed at a predetermined depth in the semiconductor substrate20, for example, by implanting hydrogen (H) ions. Specifically, the fragile layer213is formed, for example, at a position that is about 30 nm to 50 nm deeper than lower portions of the fins211.

Next, as illustrated inFIG.3C, the semiconductor substrate20is processed to form the plurality of fins211. Subsequently, as illustrated inFIG.3D, the element isolation region212and the wiring layer70are formed on the first surface20S1of the semiconductor substrate20. The wiring layer70includes the wiring line71, the via V3, and the interlayer insulating layer73. The wiring line71includes the gate711. The pad electrode72is exposed on the front surface of the interlayer insulating layer73.

Next, as illustrated inFIG.3E, the third substrate300is separately fabricated on the support substrate350. The semiconductor substrate30and the wiring layer80are stacked in the third substrate300in this order. The semiconductor substrate30is provided with the logic circuits310and320, the MEAM330, and the DRAM340. The wiring layer80includes the plurality of pad electrodes81. Subsequently, as illustrated inFIG.3E, the wiring layer70of the second substrate200and the wiring layer80of the third substrate300are disposed face to face. The pad electrodes72and81exposed on the respective surfaces are bonded.

Next, as illustrated inFIG.3F, the semiconductor substrate20above the fragile layer213is peeled off. Subsequently, as illustrated inFIG.3G, the semiconductor substrate20is decreased in thin film to a predetermined thickness (e.g., 1 μm or less), for example, by chemical mechanical polishing (CMP). Next, as illustrated inFIG.3H, the semiconductor substrate20is divided into a plurality of portions. The element isolation region212is formed between the respective portions.

Subsequently, as illustrated inFIG.3I, the via V2is formed that penetrates the element isolation region212and comes into contact with the wiring line71and the wiring layer60including the pad electrode61is then formed on the second surface20S2of the semiconductor substrate20including the element isolation region212.

Next, as illustrated inFIG.3J, the first substrate100is separately fabricated on the first surface1051of the semiconductor substrate10in which the photodiode PD (light receiving element12) is formed to be buried. The first substrate100is provided with the wiring layer40. The wiring layer40includes the via V1and the like therein. In addition, the wiring layer40includes the interlayer insulating layer42. The pad electrode41is exposed on the front surface of the interlayer insulating layer42. Subsequently, as illustrated inFIG.3J, the wiring layer40of the first substrate100and the wiring layer60of the second substrate200are disposed face to face. The pad electrodes41and61exposed on the respective surfaces are bonded. After that, the color filter51and the light receiving lens52are formed on the second surface10S2side of the first substrate100. The imaging device1illustrated inFIG.1is thus completed.

It is to be noted that the method of manufacturing the imaging device1described above is an example, but this is not limitative. For example, a Silicon on Insulator (SOI) substrate may be used as the semiconductor substrate20. A silicon oxide layer between a Si substrate and a Si layer of a surface may be used as the fragile layer213. In addition, the fragile layer213does not necessarily have to be provided. The semiconductor substrate20may be decreased in thin film by CMP alone. In addition, the semiconductor substrate20may be decreased in thin film by using dry etching, wet etching, or the like.

In the imaging device1according to the present embodiment, the analog circuit210provided in the second substrate200includes a transistor that operates in the full depletion mode. The second substrate200is stacked on and electrically coupled to the first substrate100including the plurality of sensor pixels11. This reduces a thickness of the second substrate200. The following describes this.

In recent years, an image sensor has adopted a structure in which a sensor section and a control circuit section (logic circuit) are formed on different wafers and the wafers are stacked. For this reason, the sensor has tended to include a larger number of signal processing circuits and the like for correction and include a larger number of necessary memories for holding information to be processed. To address this, an imaging device has been developed that has a structure in which chips are stacked in three or more layers or a wafer (a multichip in which a variety of functions are integrated in one chip) provided with a memory circuit, a logic circuit, and the like is stacked on a wafer provided with a plurality of solid-state imaging elements as described above.

However, in a case where the multichip is stacked on the image sensor in which the wafer provided with the sensor section and the wafer provided with the control circuit section described above are stacked, an intermediate wafer and upper and lower wafers are electrically coupled to each other by a through electrode (TSV). TSV provided in a typical image sensor having a three-layer stacked structure has a depth of 10 μm or more. The TSV having a depth of 10 μm or more has, for example, a diameter (φ) of 3 μm or more. This leads to an increase in circuit area in the image sensor. Alternatively, the TSV having a diameter (φ) of 3 μm or more prevents a circuit pitch from being reduced. In addition, the TSV penetrates the Si substrate. This adds parasitic capacitance. This increase in parasitic capacitance may decrease characteristics of the sensor section and the circuit provided in the intermediate wafer.

To form TSV having a small diameter (φ) or decrease an aspect ratio of TSV, a substrate of the intermediate wafer may be decreased in thin film. It is, however, necessary to hold a well to guarantee an operation of a transistor (bulk transistor) provided in the intermediate wafer. Further, a film thickness of about 10 μm is typically necessary to avoid a short circuit or the like caused by a circuit operation or a substrate interface defect after the thin film is decreased. Decreasing the substrate in thin film thus has a limit.

In contrast, in the imaging device1according to the present embodiment, a transistor that operates in the full depletion mode or Fin-FET, for example, is used as a transistor included in the analog circuit210provided in the second substrate200. This makes it possible to reduce the thickness of the semiconductor substrate20extending in the XY plane direction of the second substrate200as compared with a case where the transistor provided in the analog circuit210is a typical transistor having a planar structure or a so-called bulk transistor. In other words, it is possible to reduce the thickness of the second substrate200.

It is thus possible to considerably reduce formation area of a through wiring line (e.g., TSV) for electrically coupling, for example, the first substrate100and the third substrate300in the imaging device1according to the present embodiment. This makes it possible to achieve miniaturization.

In addition, it is possible in the imaging device1according to the present embodiment to significantly reduce the parasitic capacitance caused by the through wiring line.

The following describes modification examples (modification examples 1 to 5) of the first embodiment described above and second and third embodiments. It is to be noted that the following description denotes the same components as those of the first embodiment described above with the same signs and the descriptions thereof are omitted as appropriate.

2. MODIFICATION EXAMPLES

FIG.4schematically illustrates an example of a cross-sectional configuration of an imaging device (imaging device1A) according to the modification example 1 of the present disclosure. In the first embodiment described above, the example has been described in which the plurality of fins211stands on the semiconductor substrate20as a transistor that is included in the analog circuit210provided in the second substrate200and operates in the full depletion mode. The plurality of fins211may be, however, independent of each other as illustrated inFIG.4. This makes it possible to further reduce the thickness of the second substrate200.

In addition, in the first embodiment described above, a transistor having the Fin-FET structure has been exemplified as the transistor that operates in the full depletion mode, but this is not limitative. It is possible to use a transistor having another three-dimensional structure.

FIG.5schematically illustrates a structure of a transistor having a gate-all-around (GAA) structure as an example of the transistor having the other three-dimensional structure. The transistor having the GAA structure is provided with the fin211, for example, on the semiconductor substrate20. The fin211serves as a base. There are provided channels213A and213B each having a nano-wire shape above this fin211. The channels213A and213B each extend, for example, in the Y axis direction. The gate711is provided around the channels213A and213B with a gate insulating film (not illustrated) interposed in between. It is to be noted that the transistor having the GAA structure illustrated inFIG.5may also be sometimes referred to as a nano-wire, a nanosheet, or a nanoribbon as another name.

Further, the transistor included in the analog circuit210provided in the second substrate200is not limited to the transistor having the three-dimensional structure. It is also possible to use, for example, a so-called planar transistor as long as the planar transistor operates in the full depletion mode.

Still further, in the first embodiment described above, the example has been described in which the wiring line71provided in the same layer as that of the gate711of a transistor (Fin-FET inFIG.1) included in the analog circuit210provided in the second substrate200is used as a portion of the wiring line that electrically couples the first substrate100and the third substrate300, but this is not limitative. For example, as illustrated inFIG.6, the gate711of a transistor included in the analog circuit210may be extended to cause the gate711and the via V2to be coupled. The via V2is coupled to the pad electrode61. This makes it possible to increase the number of electrical coupling points between the first substrate100and the second substrate200and between the second substrate200and the third substrate300. In other words, finer contacts are possible.

FIG.7schematically illustrates an example of a cross-sectional configuration of an imaging device (imaging device1B) according to the modification example 2 of the present disclosure. In the first embodiment described above, the example has been described in which the one second substrate200including the analog circuit210including a transistor that operates in the full depletion mode is provided between the first substrate100and the third substrate300. The two or more second substrates200(second substrates200A and200B) may be, however, stacked as illustrated inFIG.7. This makes it possible to further facilitate miniaturization.

FIG.8schematically illustrates an example of a cross-sectional configuration of an imaging device (imaging device1C) according to the modification example 3 of the present disclosure. In the modification example 2 described above, the plurality of second substrates200may be stacked, but one of the plurality of second substrates200may be provided with a pixel circuit as the analog circuit.

The pixel circuit outputs a pixel signal based on electric charge outputted from each of the sensor pixels11. The pixel circuit includes, for example, three transistors. Specifically, the pixel circuit includes an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL. In each of the sensor pixels11, for example, a cathode of the photodiode PD (light receiving element12) is electrically coupled to a source of the transfer transistor TR. An anode of the photodiode PD (light receiving element12) is electrically coupled to a reference potential line (e.g., a ground line GND). A drain of the transfer transistor TR is electrically coupled to the floating diffusion FD.

The floating diffusion FD is electrically coupled to an input end of the pixel circuit. Specifically, the floating diffusion FD is electrically coupled, for example, to a gate of the amplification transistor AMP and a source of the reset transistor RST. A drain of the reset transistor RST is coupled to a power supply line VDD and a gate of the reset transistor RST is coupled, for example, to a drive signal line. A drain of the amplification transistor AMP is coupled to the power supply line VDD and a source of the amplification transistor AMP is coupled to a drain of the selection transistor SEL. A source of the selection transistor SEL is coupled to a vertical signal line and a gate of the selection transistor SEL is coupled, for example, to the drive signal line.

In a case where the transfer transistor TR is turned on, the transfer transistor TR transfers electric charge of the photodiode PD to the floating diffusion FD.

The reset transistor RST resets a potential of the floating diffusion FD to a predetermined potential. In a case where the reset transistor RST is turned on, the reset transistor RST resets the potential of the floating diffusion FD to the power supply line VDD.

The selection transistor SEL controls a timing at which a pixel signal is outputted from the pixel circuit.

The amplification transistor AMP generates, as the pixel signal, a signal of a voltage corresponding to a level of the electric charge held in the floating diffusion FD. The amplification transistor AMP is included in a source follower type amplifier. The amplification transistor AMP outputs the pixel signal of the voltage corresponding to the level of the electric charge generated in the photodiode PD (light receiving element12). In a case where the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential, for example, to a logic circuit through the vertical signal line. The logic circuit is described below.

The amplification transistor AMP, the reset transistor RST, and the selection transistor SEL are provided on a first surface20SA1of a semiconductor substrate20A. The second substrate200A is stacked with the first surface20SA1of the semiconductor substrate20A opposed to the first substrate100. In other words, the first substrate100and the second substrate200A are stacked face to face.

It is possible to manufacture the imaging device1C, for example, as follows. It is to be noted that a method of manufacturing the imaging device1described below is an example, but this is not limitative.

First, as illustrated inFIG.9A, the second substrate200A provided with the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL is formed as in the diagrams up toFIG.3Din the first embodiment described above.

Subsequently, as illustrated inFIG.9B, the first substrate100is separately fabricated on the first surface10S1of the semiconductor substrate10that is provided on a support substrate910and has the photodiode PD (light receiving element12) formed to cause the photodiode PD (light receiving element12) to be buried therein. The first substrate100is provided with the wiring layer40. The wiring layer40includes the via V1and the like. In addition, the wiring layer40includes the interlayer insulating layer42. The pad electrode41is exposed on the front surface of the interlayer insulating layer42. Subsequently, as illustrated inFIG.9B, the wiring layer40of the first substrate100and the wiring layer70A of the second substrate200A are disposed face to face. The pad electrodes41and72A exposed on the respective surfaces are bonded.

Next, as illustrated inFIG.9C, the semiconductor substrate20A above the fragile layer213is peeled off and the semiconductor substrate20A is then decreased in thin film to a predetermined thickness (e.g., 1 μm or less), for example, by CMP. Next, the semiconductor substrate20A is divided into a plurality of portions. The element isolation region212is formed between the respective portions. Subsequently, as illustrated inFIG.9D, a via V2A is formed that penetrates the element isolation region212and a wiring layer60A including a pad electrode61A is then formed on a second surface20AS2of the semiconductor substrate20A including the element isolation region212.

Next, as illustrated inFIG.9E, the second substrate200B is formed and then bonded to the separately fabricated third substrate300at pad electrodes72B and81exposed on the respective surfaces as in the diagrams up toFIG.3Din the first embodiment described above. After that, the pad electrodes61A and61B exposed on the respective surfaces of the second substrate200A and the second substrate200B are bonded and the support substrate910is then peeled off. The color filter51and the light receiving lens52are formed on the first surface10S1side of the first substrate100. The imaging device1C illustrated inFIG.8is thus completed.

FIG.10schematically illustrates an example of a cross-sectional configuration of an imaging device (imaging device1D) according to the modification example 4 of the present disclosure. The wiring layer60on the second surface20S2side of the semiconductor substrate20may be further provided with a functional element610. Examples of the functional element610include a capacitance element such as a passive element, a Metal-Insulator-Metal (MIM), a Metal-Oxide-Metal (MOM), a ferroelectric memory (FeRAM), and DRAM, an inductor element, and a variable resistance element such as MRAM, a Resistive Random Access Memory (ReRAM), and a Phase Change Random Access Memory (PCRAM). In addition, the wiring layer60may be provided with wiring lines62such as the power supply line VDD, the ground line GND, and the signal line. Each of the wiring lines62may be provided in a single layer or may be provided over a plurality of layers.

FIG.11schematically illustrates a cross-sectional configuration in which the wiring layer60is provided with the power supply line VDD and the ground line GND as another example of the present modification example. In a typical imaging device, the wiring layer70is provided with an inverter Inv, a NAND circuit (FIG.12), a NOR circuit, or a flip-flop obtained by combining them as a standard cell (logic circuit block). Specifically, a PMOS formation region721illustrated inFIG.13is provided, for example, with a circuit portion X1that is illustrated inFIG.12and includes PMOS. An NMOS formation region722illustrated inFIG.13is provided, for example, with a circuit portion X2that is illustrated inFIG.12and includes NMOS. The wiring layer70is further provided with the power supply line VDD, the ground line GND, the signal line, and the like. The power supply line VDD and the ground line GND are respectively disposed at ends of the PMOS formation region721and the NMOS formation region as illustrated inFIG.13by taking into consideration the IR drop, a contact between wiring lines, and the like. This is a cause of a limit on the wiring layout, an increase in layout area, and an increase in cost caused by increasing wiring layers.

In contrast, in the present modification example, as illustrated inFIGS.11and14, the wiring layer60on the first substrate100side is also provided with the power supply line VDD and the ground line GND as the wiring lines62. This makes it possible to make a width w2of a standard cell provided in the wiring layer70smaller than a width w1(FIG.13) of a standard cell in a typical imaging device. In other words, it is possible to further facilitate miniaturization.

In addition, providing the wiring layer60with the power supply line VDD and the ground line GND makes it possible to decrease, as compared with a typical imaging device, a wiring line length of a wiring line that electrically couples the power supply line VDD and the ground line GND, and a transistor provided in the second substrate200. This makes it possible to reduce the influence of the IR drop and reduce the number of layers for the wiring lines provided, for example, in the wiring layer70.

It is to be noted thatFIGS.11and14each illustrate the example in which the power supply line VDD and the ground line GND extend side by side, but this is not limitative. For example, a layout may be adopted in which the power supply line VDD and the ground line GND cross each other. In other words, it is possible to increase a degree of freedom of the wiring layout. In addition,FIG.11illustrates the example in which the power supply line VDD and the ground line GND are provided in different layers, but this is not limitative. The power supply line VDD and the ground line GND may be provided in the same layer. This makes it possible to further reduce the influence of the IR drop and further reduce the number of layers for the wiring lines.

FIG.15schematically illustrates an example of a cross-sectional configuration of an imaging device (imaging device1E) according to the modification example 5 of the present disclosure. In the first embodiment described above, the example has been described in which the first substrate100and the second substrate200are stacked face to back and the second substrate200and the third substrate300are stacked face to face, but this is not limitative. As illustrated inFIG.15, the first substrate100and the second substrate200may be stacked face to face and the second substrate200and the third substrate300may be stacked face to back.

The configuration described above makes it possible to reduce parasitic capacitance caused by a wiring line (through wiring line) that electrically couples the second substrate200and the third substrate300and extends in a stack direction (Z axis direction).

3. SECOND EMBODIMENT

FIG.16is an exploded perspective view of a schematic configuration of an imaging device (imaging device2) according to the second embodiment of the present disclosure.FIG.17illustrates an example of a circuit configuration of the imaging device2. In the imaging device2according to the present embodiment, the analog circuit210provided in the second substrate200and the logic circuit310provided in the third substrate300are each coupled for each of the sensor pixels11through a pad electrode.

In the first embodiment described above, the example has been described in which the one analog circuit210is coupled to the plurality of sensor pixels11through the pad electrodes (FIG.2). The analog circuit210, however, includes a transistor that operates in the full depletion mode as a transistor included in the analog circuit210provided in the second substrate200, thereby making it possible to bond the first substrate100and the second substrate200and the second substrate200and the third substrate300to each other at fine pitches by metal bonding. Specifically, as illustrated inFIG.18A, it is possible to subject the one sensor pixel11and the analog circuit210provided in the second substrate200to metal bonding (e.g., Cu—Cu bonding) and subject this one analog circuit210provided in the second substrate200and the one logic circuit310provided in the third substrate300to metal bonding (e.g., Cu—Cu bonding). This makes it possible in the imaging device2according to the present embodiment to perform control in units of sensor pixels.

It is to be noted thatFIG.16illustrates the example in which the third substrate300is provided with the logic circuit320and the DRAM340. The logic circuit320is different from the logic circuit310in technology node. The logic circuit320and the DRAM340, and the logic circuit310may be, however, coupled in a rewiring layer (RDL). In addition, as illustrated inFIG.16, the second substrate200may be provided with a logic circuit220different from the logic circuit310in technology node. In that case, for example, as illustrated inFIG.18B, the logic circuit220of the second substrate200, and the logic circuit320and the DRAM340provided in the third substrate300may be electrically coupled to each other by metal bonding (e.g., Cu—Cu bonding).

In addition,FIG.17illustrates the example in which there is provided a latch memory section in the third substrate300. The latch memory section may, however, include, for example, MRAM and be provided in the second substrate200, for example, as in the modification example 4. In addition, the latch memory section may include a nonvolatile element such as ReRAM or PCRAM.

FIG.19is an exploded perspective view of a schematic configuration of an imaging device (imaging device3) according to the third embodiment of the present disclosure. In any of the first and second embodiments and the modification examples 1 to 5 described above, the example has been described in which the third substrate300has a chip-on-wafer (CoW) structure in which the third substrate300includes a mixture of a plurality of chips of the logic circuits310and320, the MRAM330, the DRAM340, and the like, but this is not limitative. As illustrated inFIG.19, the third substrate300may be, for example, a wafer provided with the logic circuit310alone. In other words, the imaging device3is an imaging device having a wafer-on-wafer-on-wafer (WoWoW) structure.

5. APPLICATION EXAMPLE

FIG.20illustrates an example of a schematic configuration of an imaging system4including the imaging device (e.g., the imaging device1) according to any of the first to third embodiments and the modification examples 1 to 5 described above.

The imaging system4is an electronic apparatus including, for example, a camera such as a digital still camera or a video camera, a portable terminal apparatus such as a smartphone or a tablet-type terminal, or the like. The imaging system4includes, for example, the imaging device (e.g., the imaging device1) according to any of the first to third embodiments described above and the modification examples thereof, an optical system241, a shutter device242, a DSP circuit243, a frame memory244, a display section245, a storage section246, an operation section247, and a power supply section248. In the imaging system4, the imaging device1according to any of the embodiments described above and the modification examples thereof, the DSP circuit243, the frame memory244, the display section245, the storage section246, the operation section247, and the power supply section248are coupled to each other through a bus line249.

The imaging device (e.g., the imaging device1) according to any of the first to third embodiments described above and the modification examples thereof outputs image data corresponding to incident light. The optical system241includes one or more lenses. The optical system241guides light (incident light) from an object to the imaging device1to form an image on a light receiving surface of the imaging device1. The shutter device242is disposed between the optical system241and the imaging device1. The shutter device242controls a period in which the imaging device1is irradiated with light and a period in which light is blocked under the control of a drive circuit. The DSP circuit243is a signal processing circuit that processes a signal (image data) outputted from the imaging device1. The frame memory244temporarily holds the image data processed by the DSP circuit243in units of frames. The display section245includes, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel. The display section245displays a moving image or a still image captured by the imaging device1. The storage section246records image data of the moving image or the still image captured by the imaging device1in a recording medium such as a semiconductor memory or a hard disk. The operation section247issues operation instructions for a variety of functions of the imaging system4in accordance with an operation by a user. The power supply section248appropriately supplies various kinds of power for operation to the imaging device1, the DSP circuit243, the frame memory244, the display section245, the storage section246, and the operation section247that are supply targets.

Next, an imaging procedure of the imaging system4is described.

FIG.21illustrates an example of a flowchart of the imaging operation of the imaging system4. A user issues an instruction to start imaging by operating the operation section247(step S101). The operation section247then transmits an imaging instruction to the imaging device1(step S102). The imaging device1(specifically, a system control circuit) executes imaging in a predetermined imaging method upon receiving the imaging instruction (step S103).

The imaging device1outputs image data obtained through imaging to the DSP circuit243. Here, the image data refers to data for all of the pixels of pixel signals generated on the basis of electric charge temporarily held in the floating diffusions FD. The DSP circuit243performs predetermined signal processing (e.g., a noise reduction process or the like) on the basis of the image data inputted from the imaging device1(step S104). The DSP circuit243causes the frame memory244to hold the image data subjected to the predetermined signal processing and the frame memory244causes the storage section246to store the image data (step S105). In this way, the imaging of the imaging system4is performed.

In the present application example, the imaging device (e.g., the imaging device1) according to any of the first to third embodiments described above and the modification examples thereof is applied to the imaging system4. This allows the imaging device1to be smaller or higher in definition. It is thus possible to provide the small or high-definition imaging system4.

6. PRACTICAL APPLICATION EXAMPLES

(Example of Practical Application to Mobile Body)

The technology (the present technology) according to the present disclosure is applicable to a variety of products. For example, the technology according to the present disclosure may be achieved as a device mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a vessel, or a robot.

The above has described the example of the mobile body control system to which the technology according to the present disclosure may be applied. The technology according to the present disclosure may be applied to the imaging section12031among the components described above. Specifically, the imaging device1according to any of the embodiments described above and the modification examples thereof is applicable to the imaging section12031. The application of the technology according to the present disclosure to the imaging section12031makes it possible to obtain a high-definition shot image with less noise and it is thus possible to perform highly accurate control using the shot image in the mobile body control system.

(Example of Practical Application to Endoscopic Surgery System)

The technology (the present technology) according to the present disclosure is applicable to a variety of products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

FIG.25is a block diagram depicting an example of a functional configuration of the camera head11102and the CCU11201depicted inFIG.24.

The above has described the example of the endoscopic surgery system to which the technology according to the present disclosure may be applied. The technology according to the present disclosure may be favorably applied to the image pickup unit11402provided to the camera head11102of the endoscope11100among the components described above. The application of the technology according to the present disclosure to the image pickup unit11402makes it possible to make the image pickup unit11402smaller or higher in definition and it is thus possible to provide the small or high-definition endoscope11100.

Although the present disclosure has been described above with reference to the first to third embodiments and the modification examples 1 to 5, and the application example and the practical application examples, the present disclosure is not limited to the embodiments or the like described above. A variety of modifications are possible. For example, in any of the embodiments and the like described above, the example has been described in which the three substrates are stacked, but this is not limitative. For example, the imaging device1B according to the modification example 2 described above in which the first substrate100, the second substrate200A, and the second substrate200B are stacked may be further provided with the third substrate300on the second substrate200B.

It is to be noted that the effects described herein are merely illustrative. The effects according to the present disclosure are not limited to the effects described herein. The present disclosure may have effects other than the effects described herein.

It is to be noted that the present disclosure may also have configurations as follows. According to the present technology having the following configurations, a transistor that operates in a full depletion mode is used as a transistor provided in a second substrate stacked on a first substrate including one or more sensor pixels. This makes it possible to reduce a thickness of the second substrate. It is thus possible to decrease, for example, area of a wiring line in an in-plane direction, achieving miniaturization. The wiring line electrically couples the first substrate and the second substrate.

An imaging device including:a first substrate including one or more sensor pixels that each perform photoelectric conversion; anda second substrate that is stacked on the first substrate and electrically coupled to the first substrate, the second substrate including a transistor that operates in a full depletion mode.
(2)

The imaging device according to (1), in which the transistor has a three-dimensional structure.

The imaging device according to (1) or (2), in which the transistor has a Fin-FET structure in which the transistor includes a plurality of fins.

The imaging device according to (3), in which the plurality of fins is coupled to each other by a semiconductor layer having a thickness of 1 μm or less.

The imaging device according to (4), in which no ion is implanted into the semiconductor layer.

The imaging device according to any one of (3) to (5), in which the plurality of fins is independent of each other.

The imaging device according to any one of (1) to (6), in which the transistor has a gate-all-around structure.

The imaging device according to any one of (1) to (7), in which the first substrate and the second substrate are electrically coupled through a gate of the transistor or a wiring line formed in a same layer as a layer of the gate.

The imaging device according to any one of (1) to (8), in which the second substrate has a first surface provided with a gate of the transistor and a second surface opposite to the first surface and the second substrate is joined to the first substrate with the second surface interposed in between.

The imaging device according to any one of (1) to (8), in which the second substrate has a first surface provided with a gate of the transistor and a second surface opposite to the first surface and the second substrate is joined to the first substrate with the first surface interposed in between.

The imaging device according to any one of (1) to (10), in which the second substrate has a first surface provided with a gate of the transistor and a second surface opposite to the first surface and the second substrate is further provided with a multilayer wiring layer on the second surface side.

The imaging device according to (11), in which the multilayer wiring layer is provided with at least one of a power supply line, a ground line, a signal line, a resistance element, a capacitance element, an inductor element, or a memory element.

The imaging device according to (11) or (12), in whichthe second substrate further includes a logic circuit block, anda power supply line and a ground line are disposed in the multilayer wiring layer, the power supply line and the ground line being included in the logic circuit block.
(14)

The imaging device according to any one of (1) to (13), in which two or more layers each provided with the transistor are stacked in the second substrate.

The imaging device according to any one of (1) to (14), in whichthe second substrate includes a pixel circuit that outputs a pixel circuit based on electric charge outputted from the sensor pixel, andthe pixel circuit includes the transistor.
(16)

The imaging device according to any one of (1) to (15), in which the second substrate includes an analog circuit including the transistor.

The imaging device according to any one of (1) to (16), further including a third substrate including a logic circuit.

The imaging device according to (17), in which a circuit including the transistor of the second substrate and the logic circuit of the third substrate are each provided for each of the sensor pixels.

The imaging device according to (17) or (18), in which the logic circuit includes a plurality of logic sections having different technology nodes.

The imaging device according to any one of (17) to (19), in which the logic circuit includes a memory section.

The imaging device according to any one of (17) to (20), in which the logic circuit includes a transistor that is driven by using a lower power supply voltage than a power supply voltage of the transistor.

The imaging device according to (9) or any one of (11) to (21), further including a third substrate including a logic circuit, in whichthe third substrate is joined to the first surface of the second substrate by metal bonding.
(23)

The imaging device according to any one of (10) to (21), further including a third substrate including a logic circuit, in whichthe third substrate is joined to the second surface of the second substrate by metal bonding.
(24)

An electronic apparatus includingan imaging device includinga first substrate including one or more sensor pixels that each perform photoelectric conversion, anda second substrate that is stacked on the first substrate, the second substrate including a transistor that operates in a full depletion mode.

This application claims the priority on the basis of Japanese Patent Application No. 2020-174497 filed with Japan Patent Office on Oct. 16, 2020, the entire contents of which are incorporated in this application by reference.