Display with system-on-panel design

A display adopting system-on-panel (SOP) design comprising a pixel array, a driving unit, a timing controller, and a first synchronization unit is provided. The pixel array is electrically connected with the driving unit. The timing controller generates a first set of timing signals to the driving unit. The first synchronization unit is set adjacent to an input of the driving unit for synchronizing the first set of timing signals.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a display adopting system-on-panel (SOP) design, and more particularly to a liquid crystal display (LCD) adopting SOP design capable of synchronizing control signals.

2. Description of Related Art

Liquid crystal displays (LCDs) with the advantages of slim size, low power consumption, and low radiation showing the potential to replace traditional cathode ray tube (CRT) displays are widely applied to electronic products such as desktop computer, personal digital assistant (PDA), notebook (NB), digital camera (DC), cell phone, etc. nowadays.

FIG. 1is a block diagram showing a traditional active matrix LCD1. The LCD1comprises a display panel10and a driving system20. A pixel array12with a plurality of pixel capacitors122is formed on the display panel10. Each of the pixel capacitors122is connected with a thin film transistor (TFT)124. The TFT124is utilized as a switch to control the illumination of the pixel capacitor122. The driving system20includes a control circuit22, a source driver24, and a scan driver26. The source driver24is electrically connected to the source electrodes of the TFTs124. The scan driver26is electrically connected to the gate electrodes of the TFTs124. The control circuit22is utilized for translating the original displaying signals DS into display data D and control signals CS. The display data D and the control signals CS are applied to the source driver24and the scan driver26to generate source driving voltages Vs and gate driving voltages Vg. The source driving voltages Vs and the gate driving voltages Vg are then applied to the source electrodes and the gate electrodes of the TFTs124through the data lines32and the scan lines34respectively to form images on the display panel10.

As shown, the TFTs124connected to the pixel capacitors122for switching the pixel capacitors122are arrayed on the display panel10. In the past, restricted by the temperature limit of the glass substrate composing the display panel10, only the amorphous thin film transistor (a-TFT) adopting an amorphous silicon layer specified with low temperature fabrication processes is able to be used to prevent the deformation of the display panel10.

By contrast to the TFT124for switching the pixel capacitors122, the transistor within the driving system20dealing with complicated display data needs a higher switching rate for a sufficiently high calculation speed, and the proper choice is polysilicon TFT. However, the polysilicon TFT cannot be fabricated on the glass substrate through the traditional semiconductor processes. The glass substrate cannot tolerate. Therefore, in a case shown inFIG. 2, the driving system20is fabricated on several silicon chips rather than on the display panel10. The silicon chips are electrically connected to the pixel array12on the display panel10through some pipelines.

As the development of advance low temperature polysilicon (LTPS) process such as laser crystallization, the formation of polysilicon TFT on the glass-based display panel becomes possible. In the case shown inFIG. 3, by using the LTPS process, the source driver24and the scan driver26may be formed on the display panel10to simplify the fabrication process and reduce the weight of the LCD.

The case ofFIG. 3still has a silicon chip for allocating control circuit22, and some assembling steps for electrically connecting the control circuit22to the driver24,26on the display panel10through some pipelines are demanded. For further reducing the weight of the LCD, in the case shown inFIG. 4, the control circuit22is integrated on the display panel10to result a system-on-panel (SOP) display.

The signals applied to the source driver24and the scan driver26must have perfect synchronization to make sure the pixel array12displays images correctly. However, in the SOP display shown inFIG. 4, the control circuit22cannot lean to the source driver24and the scan driver26simultaneously due to the width limitation of the frame region in the display panel10. Therefore, a large signal transmitting distance between the control circuit22and the drivers24,26is unpreventable and may result a significant timing delay or signal mismatch to degrade the image quality.

Accordingly, how to make sure a good synchronization of all the signals applied to the drives is quite important for a correct and good image quality especially for a display adopting SOP design.

SUMMARY OF THE INVENTION

The present invention focuses on the problem of timing delay and signal mismatch as signals transmit from the control circuit to the drivers on a system-on-panel (SOP) display panel.

An SOP display panel provided in the present invention comprises a pixel array, a driving unit, a timing controller, and a first synchronization unit. The driving unit is electrically connected to the pixel array. The timing controller is configured to apply a first set of timing signals to the driving unit. The first synchronization unit is electrically connected to an input of the driving unit for synchronizing the first set of timing signals.

DETAIL DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 5shows a first embodiment of a system-on-panel (SOP) display panel100in accordance with the present invention. This display panel100includes a pixel array110, a source driver120, a scan driver130, a first synchronization unit150, a second synchronization unit160, and a timing controller140formed on a glass substrate (not shown in this figure). Each pixel capacitors within the pixel array110is electrically connected to a TFT (not shown). The TFT with a source electrode electrically connected to the source driver120and a gate electrode electrically connected to the scan driver130acts as a switch for controlling the operation of the pixel array110.

The timing controller140is configured to generate a first set of timing signals, which includes a first clock signal HCK and a first starting signal HST, and a second set of timing signals, which includes a second clock signal VCK and a second starting signal VST. The first set of timing signals and the second set of timing signals are transmitted to the source driver120and the scan driver130respectively. In addition, a display data signal D having the content of images is applied to the source driver120. The source driver120samples the display data signal D with the timing decided by the first clock signal HCK and the first starting signal HST to generate a source driving voltage Vs. The source driving voltage Vs is then applied to the pixel array110column by column. The scan driver130generates a gate driving voltage Vg with the timing decided by the second clock signal VCK and the second starting signal VST. The gate driving voltage Vg is then applied to the pixel array110row by row.

In addition to the first set of timing signals and the second set of timing signals, the timing controller140is capable of generating some additional timing signals and starting signals for the need of different source driver120designs.

In order to prevent the mismatch among the timing of the first clock signal HCK, the first starting signal HST, and the display data signal D to result a wrong source driving voltage Vs, the first synchronization unit150is set adjacent and electrically connected to an input120aof the source driver120and is configured to synchronize the first clock signal HCK with the first starting signal HST before they entering the source driver120. In order to prevent the mismatch between the second clock signal VCK and the second starting signal VST to result a wrong gate driving voltage Vg, the second synchronization unit160is set adjacent and electrically connected to an input130aof the scan driver130and is configured to synchronize the second clock signal VCK with the second starting signal VST before they entering the scan driver130.

It is noted that in this embodiment, two synchronization units150and160are used for synchronizing the signals HCK, HST, VCK, VST applied to the source driver120and the scan driver130respectively. However, as the source driver120is adjacent to the timing controller140, the first clock signal HCK, the first starting signal HST, and the display data signal D may maintain a good synchronization due to a short signal transmitting distance. Thus, the first synchronization unit150may be removed. On the other hand, as the scan driver130is adjacent to the timing controller140, the second clock signal VCK and the second starting signal HST may maintain a good synchronization due to a short signal transmitting distance. Thus, the second synchronization unit160may be removed.

FIG. 6shows a typical synchronization unit200adopted in the present invention. As shown, the synchronization unit200has a synchronization clock210and a plurality of D flip-flops220. The synchronization clock210provides a standard timing signal SS to the D flip-flops220. The D flip-flops220adjust the timing of the input signals S1and S2according to the standard timing signal SS. As the first synchronization unit150in the first embodiment is concerned, the input signals are the first clock signal HCK and the first starting signal HST. As the second synchronization unit160in the first embodiment is concerned, the input signals are the second clock signal VCK and the second starting signal VST.

FIG. 7shows a second embodiment of the SOG display panel100in the present invention. The timing controller140in this embodiment is configured to generate a synchronizing signal Sync in addition to the first clock signal HCK, the first starting signal HST, the second clock signal VCK, and the second starting signal VST. A display data signal D is applied to the source driver120through the first synchronization unit150. The synchronizing signal Sync is applied to the first synchronization unit150and the second synchronization unit160acting as a timing standard for adjusting the first clock signal HCK, the first starting signal HST, the display data signal D, the second clock signal VCK, and the second starting signal VST. That is, the synchronization clock210within the synchronization unit200may be functional replaced by the synchronizing signal Sync, so that the first synchronization unit150and the second synchronization unit160in this embodiment can be simplified but maintain a good synchronization output.

FIG. 8shows a third embodiment of the SOG display panel100in the present invention. By contrast to the first embodiment, an additional third synchronization unit170is integrated in this embodiment. The third synchronization unit170is located adjacent and electrically connected to an output of the timing controller140to make sure the first set of timing signals, including the first clock signal HCK and the first starting signal HST, and the second set of timing signals, including the second clock signal VCK and the second starting signal VST, performing a good synchronization when leaving the timing controller140. The additional third synchronization unit170may reduce the mismatch among the timing of the first clock signal HCK, the first starting signal HST, the second clock signal VCK, and the second starting signal VST when reaching the first synchronization unit150and the second synchronization unit160, so as to prevent the wrong operation of the first synchronization unit150and the second synchronization unit160as the timing mismatch is too large to be adjusted.

FIG. 9shows a fourth embodiment of the SOG display panel100in the present invention. By contrast to the first embodiment, an additional fourth synchronization unit180is integrated in this embodiment. The first synchronization unit150is adjacent and electrically connected to an input120aof the source driver120, and the fourth synchronization unit180is adjacent and electrically connected to another input120bof the source driver120. The first set of timing signals, including the first clock signal HCK and the first starting signal HST, and the display data signal D are synchronized by the first synchronization unit150and the fourth synchronization unit180respectively before applying to the source driver120. The first synchronization unit150and the fourth synchronization unit180may have synchronization clocks with identical timing to synchronize the first set of timing signals with the display data signal D, or the timing controller140may generate a synchronizing signal to the first synchronization unit150and the fourth synchronization unit180as a synchronizing standard for matching the timing of the first set of timing signals and the display data signal D.

FIG. 10shows a fifth embodiment of the SOG display panel100in the present invention. By contrast to the first embodiment, this embodiment needs merely a fifth synchronization unit190. The fifth synchronization unit190is located adjacent and electrically connected to the left side input120bof the source driver120and the upper side input130aof the scan driver130. The first set of timing signals, including the first clock signal HCK and the first starting signal HST, the second set of timing signals, including the second clock signal VCK and the second starting signal VST, and the display data signal D are all synchronized by the fifth synchronization unit190. Then, the display data signal D, the first clock signal HCK, and the first starting signal HST are applied to the source driver120through the left side input120bof the source driver120, and the second clock signal VCK and the second starting signal VST are applied to the scan driver130through the upper side input130aof the scan driver.

By contrast to the traditional SOG display panel shown inFIG. 4, which has a main problem of timing delay due to large signal transmitting distance to result signal mismatch, the SOG display panel100in the present invention shown inFIG. 5synchronizes the signals HCK, HST, VCK, VST before they are applied to the source driver120and the scan driver130. The synchronized signals HCK, HST, VCK, VST are thus translated to correct source driving voltages Vs and gate driving voltages Vg applying to the pixel array110. In addition, the synchronized signals HCK, HST, VCK, VST also guarantee a perfect matching between the source driving voltage Vs and the gate driving voltage Vg to form correct and clear images.

With the example and explanations above, the features and spirits of the invention will be hopefully well described. Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made when retaining the teaching of the invention. Accordingly, the appended claims are intended to cover all embodiments without departing from the spirit and scope of the present invention.