Non-volatile memory device and interface configuration method

An FMD including a plurality of FM chips and an FM-CTL equipped with a flash I/F for executing I/O processes to and from the FM chips, wherein the FM-CTL is provided with a flash I/F in correspondence with each of a plurality of channels, and the FM-CTL is configured to: acquire a higher-level operating frequency between a DKC and the FM-CTL; determine an operating frequency of the flash I/F such that a total transfer rate to and from the FM chips produced by the flash I/Fs of the respective channels should be a transfer rate that equals a higher-level transfer rate corresponding to the higher-level operating frequency or a transfer rate that approximates the higher-level transfer rate; and perform a configuration of an operating frequency determined with respect to each of the flash I/Fs.

CROSS-REFERENCE TO PRIOR APPLICATION

This application relates to and claims the benefit of priority from Japanese Patent Application No. 2018-111929 filed on Jun. 12, 2018, the entire disclosure of which is incorporated herein by reference.

BACKGROUND

The present invention relates to a non-volatile memory device and the like which includes a plurality of non-volatile memory chips and a non-volatile memory controller equipped with an interface for executing I/O processes of data to and from the non-volatile memory chips.

Conventionally, non-volatile memory devices including a plurality of non-volatile memory chips have been known. A NAND-type flash memory chip has been known as an example of a non-volatile memory chip.

NAND-type flash memory chips are available as a wide variety of products and flash memory chips of different types may conceivably be mounted to a non-volatile memory device. When such a configuration is envisaged, various parameters in interfaces (flash I/Fs) respectively provided in a flash memory controller which controls I/O processes to and from the flash memory chips inside the non-volatile memory device and in the flash memory chips must be optimized for each type of the flash memory chips.

When optimizing the various parameters in a flash I/F, for example, a transmission waveform produced by the flash I/F may conceivably be evaluated with an oscilloscope to retrieve optimal parameters.

For example, as a method of optimizing parameters of an I/F for performing transmission between LSIs, a technique has been known, which involves preparing a table of power-supply voltage and a configuration parameter for each of a plurality of operating frequency bands and selecting a configuration parameter from the table (for example, refer to Japanese Patent Application Publication No. 2011-41109).

SUMMARY

For example, optimizing parameters by evaluating a transmission waveform produced by a flash I/F with an oscilloscope requires many man-hours.

In addition, even when used flash memory chips are chips of a same type, a wiring length and/or a coupling relationship between the flash memory chips and a flash memory controller may differ depending on individual variability, mounting positions, and the like of the flash memory chips and, consequently, the same parameters are not necessarily always optimal. Therefore, even in such cases, the parameters in a flash I/F must be optimized.

Furthermore, the optimal values of parameters in a flash I/F may also vary depending on a state of use and the like of the non-volatile memory device and, therefore, parameters must be optimized even in such cases.

The present invention has been made in consideration of the circumstances described above, and an object of the present invention is to provide a technique that enables parameters in an interface used for I/O processes between a non-volatile memory controller and a non-volatile memory chip to be configured in an easy and appropriate manner.

In order to achieve the object described above, a non-volatile memory device according to an aspect is a non-volatile memory device including a plurality of non-volatile memory chips and a non-volatile memory controller equipped with an interface for executing I/O processes of data to and from the non-volatile memory chips, wherein the non-volatile memory controller is coupled to the plurality of non-volatile memory chips via a plurality of channels and the interface is provided in correspondence to each of the plurality of the channels, and the non-volatile memory controller is configured to: acquire higher-level transfer rate information related to a data transfer rate between a higher-level apparatus and the non-volatile memory controller; determine transfer rate information related to a transfer rate of the interfaces such that a total transfer rate which is a sum of transfer rates to and from the non-volatile memory chips produced by the respective interfaces corresponding to the plurality of channels should be a transfer rate that equals a higher-level transfer rate corresponding to the higher-level transfer rate information or a transfer rate that approximates the higher-level transfer rate; and perform a configuration related to a transfer rate on the basis of the determined transfer rate information with respect to each of the interfaces.

According to the present invention, parameters in an interface used for I/O processes between a non-volatile memory controller and a non-volatile memory chip can be configured in an easy and appropriate manner.

DETAILED DESCRIPTION OF THE EMBODIMENT

An embodiment will be described with reference to the drawings. It should be noted that the embodiment described below is not intended to limit the invention as set forth in the accompanying claims and that all of the elements and combinations thereof described in the embodiment are not necessarily essential to solutions proposed by the invention.

Although information will be described below using expressions such as an “AAA table”, information may be expressed using any kind of data structure. In other words, an “AAA table” can also be referred to as “AAA information” in order to show that information is not dependent on data structure.

In addition, in the following description, “RAID” is an abbreviation of Redundant Array of Independent (or Inexpensive) Disks.

FIG. 1is an overall configuration diagram of a computer system according to the embodiment.

A computer system1includes one or more hosts2, one or more storage systems3, and a SAN (Storage Area Network)4which couples the hosts2and the storage systems3to each other. The SAN4may be replaced with a communication network of another type.

The host2transmits, to the storage system3, I/O (input/output) requests with respect to the storage system3or, more specifically, a read request to read data stored in the storage system3and a write request to write data to the storage system3.

The storage system3includes one or more disk controllers (DKCs)10as examples of a higher-level apparatus and one or more FMDs (flash memory devices)20.

The FMD20is a storage device (a non-volatile memory device) which stores data written from the host2and the like and which adopts a non-volatile memory such as a flash memory as a storage medium.

The FMD20includes a plurality of FM chips (flash memory chips: non-volatile memory chips)40and an FM-CTL (a flash memory controller: a non-volatile memory controller)30. A detailed configuration of the FMD20will be described later. The FMD20is coupled to the disk controller10by, for example, a transmission line (an SAS link) conforming to the SAS (Serial Attached SCSI) standard or a transmission line (a PCI link) conforming to the PCI (Peripheral Component Interconnect) standard.

The disk controller10receives an I/O request from the host2and, in accordance with the I/O request, executes an I/O process (a read process of reading data from the FMD20or a write process of writing data to the FMD20). It should be noted that the disk controller10may be configured to manage a RAID group (a parity group) constituted by a plurality of FMDs20and execute a read process or a write process with respect to the RAID group in accordance with a RAID level associated with the RAID group.

Next, the FMD20will be described in detail.

FIG. 2is a configuration diagram of a flash memory device according to the embodiment.

The FMD20includes the FM-CTL30, the plurality of FM chips40, a main memory50, and a firmware memory60. The FM-CTL30is coupled to the main memory50and the firmware memory60. In addition, the FM-CTL30is coupled to the plurality of FM chips40via a transmission line (a bus: FM-BUS)70. In the present embodiment, the transmission line70has a plurality of channels (inFIG. 2, for example, four channels), and a plurality of FM chips40are coupled to each channel. Each channel is capable of independently performing data transfer.

The FM-CTL30executes various processes by executing a program stored in the main memory50. For example, the FM-CTL30controls I/O processes of data to and from the FM chips40. In addition, the FM-CTL30executes a parameter update process of updating parameters of interfaces (flash I/Fs32and42) which execute communication between the FM-CTL30and the FM chips40, and the like.

The FM chip40is, for example, a non-volatile semiconductor memory chip such as a NAND-type flash memory. Examples of the FM chip40include a QLC FM chip, a TLC FM chip, and an SLC (Single Level Cell) FM chip.

The main memory50may be constituted by a volatile storage medium such as a DRAM or an SRAM or by a non-volatile memory. The main memory50stores programs executed by the FM-CTL30and necessary information.

The firmware memory60is, for example, a non-volatile memory such as a flash memory and stores programs executed by the FM-CTL30, various tables, and the like. Programs, tables, and the like can be stored in the firmware memory60from an apparatus outside of the FMD20(via the FM-CTL30or without involving the FM-CTL30).

The firmware memory60stores an update condition table61, a voltage value table62, a configuration value table63, a configuration management table64, and a per-command timing table65. Configurations of the respective tables will be described later. The firmware memory60is an example of an update condition storage unit.

Next, a configuration related to transmission of data between the FM-CTL30and the FM chip40will be described.

FIG. 3is an explanatory diagram of a configuration related to transmission of data between an FM-CTL and an FM chip according to the embodiment.

The FM-CTL30includes a CPU31as an example of a processor, one or more flash interfaces (Flash I/Fs)32, a voltage monitor unit35, an I/O error monitor unit36, and a temperature monitor unit37.

The CPU31executes various processes by executing a program stored in the main memory50. The CPU31controls I/O processes of data to and from the FM chips40. In addition, the CPU31executes a parameter update process of updating parameters of interfaces (the flash I/Fs32and42) which execute communication between the FM-CTL30and the respective FM chips40, and the like.

Each flash I/F32is provided in association with each channel in the transmission line70and includes an I/O control unit33and a command control unit34. The I/O control unit33controls I/O processes of data to and from the plurality of FM chips40coupled to a corresponding channel. The command control unit34controls transmission and reception of commands to and from the FM chips40coupled to a corresponding channel.

The voltage monitor unit35measures voltage of a signal line between each flash I/F32and each FM chip40and notifies the CPU31of a measurement result. The I/O error monitor unit36monitors I/O errors with respect to data transmitted from the FM chip40and notifies the CPU31of a monitoring result. The I/O error monitor unit36may be a functional unit configured by an execution of a prescribed program by the CPU31. The temperature monitor unit37detects a temperature of the FM-CTL30, an intake temperature to the FMD20, an exhaust temperature from the FMD20, and the like and notifies the CPU31of a detection result. It should be noted that at least one of the voltage monitor unit35, the I/O error monitor unit36, and the temperature monitor unit37may be provided outside of the FM-CTL30.

The FM chip40includes a control unit41, a flash interface (a flash I/F)42, a voltage monitor unit45, an I/O error monitor unit46, and a temperature monitor unit47.

The control unit41executes various processes.

The flash I/F42includes an I/O control unit43and a command control unit44. The I/O control unit43controls I/O processes of data to and from the flash I/F32of the FM-CTL30. The command control unit44controls transmission and reception of commands to and from the FM-CTL30.

The voltage monitor unit45measures voltage of a signal line between the FM-CTL30and each FM chip40and notifies the CPU31of the FM-CTL30of a measurement result. The I/O error monitor unit46monitors I/O errors with respect to data transmitted from the FM-CTL30and notifies the CPU31of the FM-CTL30of a monitoring result. The I/O error monitor unit46may be a functional unit configured by an execution of a prescribed program by the control unit41. The temperature monitor unit47detects a temperature of the FM chip40and the like and notifies the CPU31of the FM-CTL30of a detection result. At least one of the voltage monitor unit45, the I/O error monitor unit46, and the temperature monitor unit47may be provided outside of the FM chip40.

Next, a configuration related to a signal voltage of a transmission line between the FM-CTL30and the FM chip40will be described.

FIG. 4is an explanatory diagram of a configuration related to a signal voltage of a transmission line between an FM-CTL and an FM chip according to the embodiment.

Power is supplied from a power supply (not illustrated) to the FM-CTL30. In each flash I/F32of the FM-CTL30, one or more pairs of a resistor32aand a switch (SW)32bare arranged between a signal line70aand a positive-side power supply Vdd of the transmission line70, and one or more pairs of a resistor32cand a switch (SW)32dare arranged between the signal line70aand a negative-side power supply Vss of the transmission line70. WhileFIG. 4illustrates a configuration related to one signal line70aof the transmission line70, other signal lines of the transmission line70are configured in a similar manner.

In such a configuration, by controlling opening and closing of the switch32bto control a resistance value between the signal line70aand the positive-side power supply, the voltage (output voltage) of a signal when the signal is transmitted from the flash I/F32can be adjusted. In addition, by controlling opening and closing of the switch32dto control a resistance value between the signal line70aand the negative-side power supply, a terminal resistance value when receiving a signal from the flash I/F42of the FM chip40can be adjusted.

Power is supplied from a power supply (not illustrated) to the FM chip40. In each flash I/F42of the FM chip40, one or more pairs of a resistor42aand a switch (SW)42bare arranged between the signal line70aand the positive-side power supply Vdd of the transmission line70and one or more pairs of a resistor42cand a switch (SW)42dare arranged between the signal line70aand the negative-side power supply Vss of the transmission line70.

In such a configuration, by controlling opening and closing of the switch42bto control a resistance value between the signal line70aand the positive-side power supply Vdd, the voltage (output voltage) of a signal when the signal is transmitted from the flash I/F42can be adjusted. In addition, by controlling opening and closing of the switch42dto control a resistance value between the signal line70aand the negative-side power supply Vss, a terminal resistance value when receiving a signal from the flash I/F32of the FM-CTL30can be adjusted.

While a value of resistors coupled to the signal line70aare adjusted by controlling opening and closing of the switch32b, the switch32d, the switch42b, the switch42d, and the like in the configuration described above, for example, variable resistors may be provided in place of the pairs of a switch and a resistor.

Next, the various tables stored in the firmware memory60will be described.

FIG. 5is a configuration diagram of an update condition table according to the embodiment.

The update condition table61manages entries corresponding to conditions (update conditions) under which a parameter update process of updating parameters of the flash I/Fs32and42are executed. An entry of the update condition table61includes fields of condition61a, contents61b, reference (previous value)61c, and error61d.

Condition61astores a name of a condition corresponding to the entry. Contents61bstores contents of the condition corresponding to the entry. Reference (previous value)61cstores a reference in the condition corresponding to the entry or a previous value (a value upon a previous execution of the parameter update process). Error61dstores, when contents of the condition are inconsistent with a prescribed value, a range of error in which inconsistency is not determined.

In the update condition table61, an entry611corresponds to a condition of a temperature change of the FM-CTL30and indicates that the parameter update process is executed when the temperature of the FM-CTL30is inconsistent with the previous value or, in other words, when the temperature of the FM-CTL30deviates from a range of ±0.5° C. (error) relative to the previous value (in the example shown inFIG. 5, 70° C.), an entry612corresponds to a condition of a temperature change of the intake temperature of the FMD20and indicates that the parameter update process is executed when the intake temperature of the FMD20is inconsistent with the previous value or, in other words, when the intake temperature of the FMD20deviates from a range of ±0.5° C. (error) relative to the previous value (in the example shown inFIG. 5, 25° C.), an entry613corresponds to a condition of a temperature change of the exhaust temperature of the FMD20and indicates that the parameter update process is executed when the exhaust temperature of the FMD20is inconsistent with the previous value or, in other words, when the exhaust temperature of the FMD20deviates from a range of ±0.5° C. (error) relative to the previous value (in the example shown inFIG. 5, 50° C.), and an entry614corresponds to a condition of a voltage change of the flash I/Fs and indicates that the parameter update process is executed when read voltage (voltage of a read signal) of the flash I/Fs32and42is inconsistent with the previous value or, in other words, when the read voltage of the flash I/Fs32and42deviates from a range of ±0.02 V (error) relative to the previous value (in the example shown inFIG. 5, 1.80 V).

In addition, an entry615corresponds to a condition of a temperature change of the FM chips40and indicates that the parameter update process is executed when an average temperature of the plurality of FM chips40is inconsistent with the previous value or, in other words, when the average temperature of the plurality of FM chips40deviates from a range of ±0.5° C. (error) relative to the previous value (in the example shown inFIG. 5, 30° C.), an entry616corresponds to a condition of I/O errors and indicates that the parameter update process is executed when the number of occurrences of I/O errors in I/O processes to and from the FM chips40is equal to or larger than a reference (in the example shown inFIG. 5, 5 times/hour), an entry617corresponds to a start time of the FMD20and indicates that the parameter update process is executed when an elapsed time from a previous parameter update process in the FMD20is equal to or longer than a reference (in the example shown inFIG. 5, 30 minutes), and an entry618corresponds to a condition of an initial start of the FMD20and indicates that the parameter update process is executed when it is the first start after the power supply of the FMD20had been turned on (the parameter update process has not yet been executed). The update conditions are not limited to the examples shown in FIG.5and other conditions may be adopted instead. For example, while the entry615represents an inconsistency between the average temperature of the plurality of FM chips40and a previous value thereof, the entry615may alternatively represent an inconsistency between a temperature of a specific FM chip40among the plurality of FM chips40and a previous value thereof or an inconsistency between a maximum temperature of the plurality of FM chips40and a previous value thereof.

Next, the voltage value table62will be described.

FIG. 6is a configuration diagram of a voltage value table according to the embodiment.

The voltage value table62stores entries related to voltage values of signals in the flash I/F. An entry of the voltage value table62includes parameter62a, symbol62b, minimum value (Min)62c, reference value (Typ)62d, maximum value (Max)62e, and unit62f.

Parameter62astores a type of a parameter of a voltage value corresponding to the entry. In the present embodiment, examples of parameters of a voltage value include a high-side (high potential-side) voltage of an input signal (input high voltage) and a low-side (low potential-side) voltage of an input signal (input low voltage). Symbol62bstores a symbol indicating the parameter corresponding to the entry. Minimum value62cstores a minimum value of a reference value of the parameter corresponding to the entry. Reference value62dstores a reference value of the parameter corresponding to the entry. Maximum value62estores a maximum value of the reference value of the parameter corresponding to the entry. Unit62fstores a unit of the parameter corresponding to the entry.

FIG. 7is a configuration diagram of a per-command timing table according to the embodiment.

The per-command timing table65stores entries for each control command output by the flash I/F32. An entry of the per-command timing table65includes the fields of command65a, minimum value (Min)65b, maximum value (Max)65c, and unit65d. Command65astores a name of a control command. Minimum value65bstores a minimum value (in the example shown inFIG. 7, a shortest time) necessary as the control command corresponding to the entry. Maximum value65cstores a maximum value as the control command corresponding to the entry. Unit65dstores a unit of minimum value65band maximum value65cof the control command corresponding to the entry.

A signal of a control command will now be described.

FIG. 8is a diagram showing signal configurations and timings of control commands according to the embodiment.FIG. 8shows Command Latch among control commands as an example.

Command latch is expressed by a CLE (Command Latch Enable) signal and a WE (Write Enable) signal. Command latch is constituted by a time (tCLS: CLE Setup Time) to setup the CLE signal and a time (tCLH: CLE Hold Time) to hold the CLE signal. The time required by command latch is a sum of tCLS and tCLH.

Next, the configuration value table63will be described.

FIG. 9is a configuration diagram of a configuration value table according to the embodiment.

The configuration value table63is a table for managing configurations with respect to various parameters that are configurable in the flash I/Fs32. A separate configuration value table63may be provided with respect to each of the flash I/Fs32or a single shared configuration value table63may be provided. In the present embodiment, a configuration value table similar to the configuration value table63with respect to the flash I/F42of each FM chip40is stored in a memory, a register, or the like in the FM chip40.

An entry of the configuration value table63includes fields of configuration number (configuration #)63a, parameter63b, symbol63c, configuration value63d, and unit63e.

Configuration number63astores a number (a configuration number) indicating a configuration corresponding to the entry. Parameter63bstores a name of a type of a parameter corresponding to the entry. Types of parameters include a “frequency” indicating an operating frequency (which corresponds to a transfer rate and which is an example of transfer rate information) of the flash I/F32, an “output resistance” indicating a resistance value on a side of a positive potential Vdd when performing output (transmission), and an “input resistance” indicating a resistance value on a side of a negative potential Vss when performing input (reception). Symbol63cstores a symbol indicating the parameter corresponding to the entry. In symbol63c, “F” is configured when the parameter type is “frequency”, “Ron” is configured when the parameter type is “output resistance”, and “Rodt” is configured when the parameter type is “input resistance”. Configuration value63dstores a configuration value of the parameter in the configuration corresponding to the entry. Unit63estores a unit of the configuration value in configuration value63dcorresponding to the entry. As the unit to be stored in unit63e, for example, “MHz” is configured when the entry corresponds to frequency, and “Q” is configured when the entry corresponds to output resistance or input resistance.

Next, the configuration management table64will be described.

FIG. 10is a configuration diagram of a configuration management table according to the embodiment.

The configuration management table64is a table for managing current configurations of the parameters of the flash I/Fs32. At least one configuration management table64is provided for each flash I/F32. For example, with respect to each flash I/F32, the configuration management table64may be provided for each FM chip40to be an I/O target. In other words, different parameter configurations can be made manageable for each FM chip40to be an I/O target.

An entry of the configuration management table64includes fields of frequency64a, output resistance64b, and input resistance64c. Frequency64astores the configuration number of an entry of the configuration value table63storing a configuration value to be configured as an operating frequency of the flash I/F32. Since an operating frequency and a transfer rate correspond to each other, the configuration value of the operating frequency can be considered a configuration value of the transfer rate. Output resistance64bstores the configuration number of an entry of the configuration value table63storing a configuration value to be configured as an output resistance of the flash I/F32. Input resistance64cstores the configuration number of an entry of the configuration value table63storing a configuration value to be configured as an input resistance of the flash I/F32.

In each FM chip40, a configuration management table with a similar structure to the configuration management table64which manages current configurations of the parameters of the flash I/F42are stored in a memory or a register.

Next, processing operations of the computer system1according to the present embodiment will be described.

First, the parameter update process will be described.

FIG. 11is a flow chart of the parameter update process according to the embodiment.

For example, the parameter update process is executed immediately after starting up the FMD20. First, the CPU31of the FM-CTL30refers to the update condition table61and determines whether or not a current state corresponds to an update condition of a parameter (step S10). As a result, when the current state corresponds to the update condition (S10: yes), the CPU31executes a training process (refer toFIG. 12) (step S11) and advances processing to step S10. On the contrary, when the current state does not correspond to the update condition (S10: no), the CPU31advances processing to step S10. According to the parameter update process, when the current state corresponds to update conditions managed in the update condition table61, the training process is appropriately executed and various parameters used by the flash I/Fs32and42of the FM-CTL30and the FM chip40can be configured to appropriate values.

Next, the training process (S11) will be described in detail.

FIG. 12is a sequence diagram of the training process according to the embodiment.

In the training process, the CPU31of the FM-CTL30first executes a frequency training process (refer toFIG. 13) of determining a frequency (corresponding to a transfer rate) in the FM-CTL30and in each channel between the FM-CTL30and the FM chips40(S21).

Next, the CPU31executes a command timing training process (refer toFIG. 14) of determining timings of control commands in the flash I/Fs of the FM-CTL30and the respective FM chips40(S22).

Next, the CPU31executes a voltage value training process (refer toFIG. 15) related to transmission from the FM-CTL30to the FM chips40in the flash I/Fs32and42of the FM-CTL30and the respective FM chips40(S23).

Next, the CPU31executes a voltage value training process (refer toFIG. 16) related to transmission from the FM chips40to the FM-CTL30in the flash I/Fs32and42of the respective FM chips40and the FM-CTL30(S24), and ends the training process.

According to the training process, the frequency in each channel between the FM-CTL30and the FM chips40, timings of control commands, a voltage value related to transmission from the FM-CTL30to the FM chips40, and a voltage value related to transmission from the FM chips40to the FM-CTL30can be configured to appropriate values.

Next, the frequency training process (S21) will be described.

FIG. 13is a flow chart of the frequency training process according to the embodiment.

The CPU31of the FM-CTL30acquires an operating frequency (a transfer rate: a higher-level I/F frequency: higher-level transfer rate information) in a higher-level I/F (in other words, an interface with the DKC10) (S31). At this point, as a method of acquiring the higher-level I/F frequency, the CPU31may make an inquiry to the DKC10to acquire the higher-level I/F frequency or the CPU31may acquire a higher-level I/F frequency configured in the FM-CTL30by the DKC10.

Next, the CPU31determines whether or not there is a designation of a new higher-level I/F frequency from the DKC10(for example, a designation of a higher-level I/F frequency based on an input by a manager with respect to the DKC10) (S32). As a result, when there is a designation of a higher-level I/F frequency (S32: yes), the CPU31performs a configuration for replacing the higher-level I/F frequency in the FM-CTL30with the DKC10with the designated frequency (S33).

When there is no designation of a higher-level I/F frequency (S32: no) or when the higher-level I/F frequency has been changed to the frequency designated in step S33, based on the higher-level I/F frequency, the CPU31determines an operating frequency of each of the flash I/Fs32and42and registers the operating frequency in the configuration management table64and, configures each of the flash I/Fs32and42to operate at the determined operating frequency (S34). The CPU31refers to an entry (an entry of which parameter63bis “frequency”) in the configuration value table63to specify operating frequencies (transfer rate information) at which the flash I/F32(or42) is operable and determines the operating frequency from the frequencies.

In the determination of the operating frequency, specifically, the CPU31determines the operating frequency (the transfer rate information) of the flash I/F32so that a total value (a total transfer rate) of transfer rates based on operating frequencies of the plurality of flash I/Fs32for the respective channels of the transmission line (FM-BUS)70equals a transfer rate (a higher-level transfer rate) based on the higher-level I/F frequency or approximates the higher-level transfer rate.

More specifically, for example, the CPU31determines the operating frequency of the flash I/F32so that the following expression (1) is satisfied and the total transfer rate of the plurality of flash I/Fs32for the respective channels is maximized. Expression (1) represents an example that adopts the operating frequencies of the respective flash I/Fs32being equalized as a condition. Alternatively, the operating frequencies of the respective flash I/Fs32being equalized need not be adopted as a condition, in which case a right side of expression (1) represents a total transfer rate of the plurality of flash I/Fs32coupled to the plurality of channels.
X(Mbps)≥Y(Mbps)*n(1)

In expression (1), X denotes a transfer rate (a higher-level transfer rate) corresponding to the higher-level I/F frequency, Y denotes a transfer rate corresponding to the operating frequency of one flash I/F32or42, and n denotes the number of channels in the transmission line70or, in other words, a maximum number of the FM chips40with respect to which the FM-CTL30is capable of executing I/O processes in parallel.

According to the frequency training process described above, the operating frequency of each flash I/F32can be configured to an appropriate value based on the higher-level I/F frequency or, in other words, a frequency at which data can be efficiently transferred.

Next, the command timing training process (S22) will be described.

FIG. 14is a flow chart of the command timing training process according to the embodiment. The command timing training process is executed for each flash I/F32in charge of each channel of the transmission line70with, as a target, a command timing with respect to at least one FM chip40coupled to the channel of which the flash I/F32is in charge. When only a command timing with respect to a part of the FM chips40of a channel is to be trained, the command timing obtained by the training may be adopted as the command timing with respect to the other FM chips40coupled to the same channel.

The CPU31of the FM-CTL30instructs the flash I/F32that is a processing target to issue one command (control command) in the per-command timing table65to the flash I/F42of the FM chip40coupled to a channel of which the flash I/F32is in charge (S41).

Next, the flash I/F32having received the instruction issues the designated command to the flash I/F42of the FM chip40in accordance with a timing (for example, a minimum value (a shortest time) of the command) in an entry corresponding to the designated command in the per-command timing table65(S42). In response thereto, the flash I/F42of the FM chip40returns a value in accordance with a command recognized by the flash I/F42to the flash I/F32that is an issuance source.

Next, the flash I/F32receives the value in accordance with the command having been returned from the flash I/F42that is an issuance destination of the command (S43), and the CPU31determines whether or not values of the issued command and the received command are consistent (S44).

As a result, when the CPU31determines that the values of the issued command and the received command are consistent (S44: yes), since this means that the command can be appropriately transmitted at this timing, the CPU31updates a timing of an entry corresponding to the designated command in the per-command timing table65to a shorter time (so that, for example, the timing is shortened by a prescribed time) (S45) and advances the processing to step S42. The CPU31is to temporarily hold a value of the timing prior to update in the main memory50or the like.

On the contrary, as a result, when the CPU31determines that the values of the issued command and the received command are not consistent (S44: no), since this means that the command cannot be appropriately transmitted at this timing, the CPU31restores the timing of the entry corresponding to the designated command in the per-command timing table65to a previous value (in other words, the value temporarily held in the main memory50or the like) (S46) and advances the processing to step S47.

In step S47, the CPU31determines whether or not training (S42to S46) has been completed with respect to all of the commands in the per-command timing table65as targets. As a result, when the training has not been completed with respect to all of the commands (S47: no), the CPU31instructs the flash I/F32that is the processing target to issue another command for which training has not been performed (S48) and advances the processing to step S42. On the contrary, when the training has been completed with respect to all of the commands (S47: yes), the CPU31ends the command timing training process with respect to the flash I/F32that is the processing target.

The command timing training process described above may be executed with respect to all of the FM chips40coupled to each channel of the transmission line70. In this case, the per-command timing table65may be stored in correspondence with each of the FM chips40or, based on command timings with respect to all of the FM chips40, a command timing (for example, an average value of a plurality of command timings) to be commonly used in same channels may be determined and the determined command timing may be configured to the per-command timing table65.

According to the command timing training process described above, an appropriate timing when issuing a command between each of the flash I/Fs32and the flash I/F42can be specified and configured.

Next, the voltage value training process (S23) related to transmission from the FM-CTL30to the FM chip40will be described.

FIG. 15is a flow chart of the voltage value training process related to transmission from an FM-CTL to an FM chip according to the embodiment.

The voltage value training process related to transmission from the FM-CTL30to the FM chip40is executed for each flash I/F32in charge of each channel of the transmission line70in order to configure a voltage value (specifically, in order to configure a resistance value to be used) upon transmission to at least one FM chip40coupled to the channel of which the flash I/F32is in charge. Alternatively, the voltage value training process may be executed with respect to all of the FM chips40coupled to the channel of which the flash I/F32is in charge. In addition, when the voltage value training process is executed with respect to a part of the FM chips40of a channel, the configuration of the voltage value obtained by the training may be adopted as the configuration of the voltage value upon transmission to the other FM chips40coupled to the same channel.

First, the CPU31transmits a prescribed waveform from the flash I/F32to the FM chip40(S51) and acquires a voltage value (an input voltage value) of the waveform input to the flash I/F42from the FM chip40(S52). The input voltage value can be acquired from the voltage monitor unit45of the FM chip40.

Next, the CPU31determines whether or not a maximum voltage and a minimum voltage of the input voltage value are in appropriate states with respect to respective reference values (for example, within a range of ±5% relative to reference values) (S53). Specifically, with respect to a maximum potential, the CPU31determines whether or not parameter62ain the voltage value table62is in an appropriate state with respect to the reference value of reference value62din an entry of input high potential voltage and, with respect to a minimum potential, the CPU31determines whether or not parameter62ain the voltage value table62is in an appropriate state with respect to the reference value of reference value62din an entry of input low potential voltage.

As a result, when the CPU31determines that the maximum voltage and the minimum voltage of the input voltage value are in appropriate states with respect to respective reference values (S53: yes), since this means that the configuration of the resistance value at the time point is appropriate, the voltage value training process related to transmission from the FM-CTL30to the FM chip40is ended.

On the contrary, when the CPU31determines that the maximum voltage and the minimum voltage of the input voltage value are not in appropriate states with respect to respective reference values (S53: no), since this means that the configuration of the resistance value at the time point is not appropriate, the CPU31changes a resistance value (an internal output resistance value) on an output side (on a positive-side power supply Vdd side of the signal line) of the flash I/F32and registers a configuration number of the output resistance in the configuration management table64(S54). At this point, the CPU31changes the resistance value to a larger value when the maximum voltage value of the input voltage value is higher than the reference value but changes the resistance value to a smaller value when the maximum voltage value of the input voltage value is lower than the reference value. The internal output resistance value can be changed by changing opening and closing of the switch32bof the flash I/F32or the like. When there are a plurality of candidates that can be changed as internal output resistance values, the processes of S54to S57may be executed with respect to each candidate as a target.

Next, the CPU31transmits a prescribed waveform from the flash I/F32to the FM chip40(S55) and acquires a voltage value (an input voltage value) of the waveform input to the flash I/F42from the FM chip40(S56).

Next, the CPU31determines whether or not the maximum voltage and the minimum voltage of the input voltage value are in appropriate states with respect to respective reference values (for example, within a range of ±5% relative to reference values) (S57), and when the CPU31determines that the maximum voltage and the minimum voltage of the input voltage value are in appropriate states with respect to respective reference values (S57: yes), since this means that the configuration of the resistance value at the time point is appropriate, the voltage value training process related to transmission from the FM-CTL30to the FM chip40is ended.

On the contrary, when the CPU31determines that the maximum voltage and the minimum voltage of the input voltage value are not in appropriate states with respect to the respective reference values (S57: no), since this means that the configuration of the resistance value at the time point is not appropriate, the CPU31transmits an instruction to the FM chip40to change a resistance value (an internal input resistance value) on an input side (on a negative-side power supply Vss side of the signal line) of the flash I/F42(S58). At this point, the CPU31issues an instruction to change the resistance value to a larger value when the minimum voltage value of the input voltage value is higher than the reference value but to change the resistance value to a smaller value when the minimum voltage value of the input voltage value is lower than the reference value. When there are a plurality of candidates that can be changed as internal input resistance values, the processes of S58to S61may be executed with respect to each candidate as a target. When the FM chip40receives the change instruction to change the resistance value, the FM chip40changes the internal input resistance value by changing opening and closing of the switch42dof the flash I/F42or the like and registers a configuration number of the input resistance in the configuration management table in the FM chip40.

Next, the CPU31transmits a prescribed waveform from the flash I/F32to the FM chip40(S59) and acquires a voltage value (an input voltage value) of the waveform input to the flash I/F42from the FM chip40(S60).

Next, the CPU31determines whether or not the maximum voltage and the minimum voltage of the input voltage value are in appropriate states with respect to respective reference values (for example, within a range of ±5% relative to reference values) (S61), and when the CPU31determines that the maximum voltage and the minimum voltage of the input voltage value are in appropriate states with respect to respective reference values (S61: yes), since this means that the configuration of the resistance value at the time point is appropriate, the voltage value training process related to transmission from the FM-CTL30to the FM chip40is ended.

On the contrary, when the CPU31determines that the maximum voltage and the minimum voltage of the input voltage value are not in appropriate states with respect to respective reference values (S61: no), since this means that the configuration of the resistance value at the time point is not appropriate, the CPU31changes the reference values related to the input voltage value in the voltage value table62within ranges of the maximum value and the minimum value of the reference values and advances the processing to step S51(S62).

According to the voltage value training process related to transmission from an FM-CTL to an FM chip described above, a voltage value of a signal when transmitting the signal from the FM-CTL30to the FM chip40can be configured to an appropriate value.

Next, the voltage value training process (S24) related to transmission from an FM chip to an FM-CTL will be described.

FIG. 16is a flow chart of a voltage value training process related to transmission from an FM chip to an FM-CTL according to the embodiment.

The voltage value training process related to transmission from the FM chip40to the FM-CTL30is executed for each flash I/F32in charge of each channel of the transmission line70in order to configure a voltage value (specifically, in order to configure a used resistance value) upon reception from at least one FM chip40coupled to the channel of which the flash I/F32is in charge. It should be noted that the voltage value training process may be executed with respect to all of the FM chips40coupled to the channel of which the flash I/F32is in charge. In addition, when the voltage value training process is executed with respect to a part of the FM chips40of a channel, the configuration of the voltage value obtained by the training may be adopted as the configuration of the voltage value upon reception from the other FM chips40coupled to the same channel.

First, the CPU31issues an instruction to the FM chip40to transmit a prescribed waveform to the FM-CTL30(S71). The FM chip40having received the instruction is to transmit the prescribed waveform from the flash I/F42. The CPU31acquires, from the voltage monitor unit35, a voltage value (an input voltage value) of the waveform input to the flash I/F32from the flash I/F42(S72).

Next, the CPU31determines whether or not a maximum voltage and a minimum voltage of the input voltage value are in appropriate states with respect to respective reference values (for example, within a range of ±5% relative to reference values) (S73). Specifically, with respect to a maximum potential, the CPU31determines whether or not parameter62ain the voltage value table62is in an appropriate state with respect to the reference value of reference value62din an entry of input high potential voltage and, with respect to a minimum potential, the CPU31determines whether or not parameter62ain the voltage value table62is in an appropriate state with respect to the reference value of reference value62din an entry of input low potential voltage.

As a result, when the CPU31determines that the maximum voltage and the minimum voltage of the input voltage value are in appropriate states with respect to respective reference values (S73: yes), since this means that the configuration of the resistance value at the time point is appropriate, the voltage value training process related to transmission from the FM chip40to the FM-CTL30is ended.

On the contrary, when the CPU31determines that the maximum voltage and the minimum voltage of the input voltage value are not in appropriate states with respect to the respective reference values (S73: no), since this means that the configuration of the resistance value at the time point is not appropriate, the CPU31transmits an instruction to the FM chip40to change a resistance value (an internal output resistance value) on an output side (on a positive-side power supply Vdd side of the signal line70a) of the flash I/F42(S74). At this point, the CPU31issues an instruction to change the resistance value to a larger value when the maximum voltage value of the input voltage value is higher than the reference value but to change the resistance value to a smaller value when the maximum voltage value of the input voltage value is lower than the reference value. When the FM chip40receives the change instruction to change the resistance value, the FM chip40changes the internal output resistance value by changing opening and closing of the switch42bof the flash I/F42or the like and registers a configuration number of the output resistance in the configuration management table in the FM chip40. When there are a plurality of candidates that can be changed as internal output resistance values, the processes of S74to S77may be executed with respect to each candidate as a target.

Next, the CPU31issues an instruction to the FM chip40to transmit a prescribed waveform to the FM-CTL30(S75). Next, the CPU31acquires, from the voltage monitor unit35, a voltage value (an input voltage value) of the waveform input to the flash I/F32from the flash I/F42(S76).

Next, the CPU31determines whether or not the maximum voltage and the minimum voltage of the input voltage value are in appropriate states with respect to respective reference values (for example, within a range of ±5% relative to reference values) (S77), and when the CPU31determines that the maximum voltage and the minimum voltage of the input voltage value are in appropriate states with respect to respective reference values (S77: yes), since this means that the configuration of the resistance value at the time point is appropriate, the voltage value training process related to transmission from the FM chip40to the FM-CTL30is ended.

On the contrary, when the CPU31determines that the maximum voltage and the minimum voltage of the input voltage value are not in appropriate states with respect to respective reference values (S77: no), since this means that the configuration of the resistance value at the time point is not appropriate, the CPU31changes a resistance value (an internal input resistance value) on an input side (on a negative-side power supply Vss side of the signal line) of the flash I/F32and registers a configuration number of the input resistance in the configuration management table64(S78). At this point, the CPU31changes the resistance value to a larger value when the maximum voltage value of the input voltage value is higher than the reference value but changes the resistance value to a smaller value when the maximum voltage value of the input voltage value is lower than the reference value. The internal input resistance value can be changed by changing opening and closing of the switch32dof the flash I/F32or the like.

Next, the CPU31issues an instruction to the FM chip40to transmit a prescribed waveform to the FM-CTL30(S79). Next, the CPU31acquires, from the voltage monitor unit35, a voltage value (an input voltage value) of the waveform input to the flash I/F32from the flash I/F42(S80).

Next, the CPU31determines whether or not the maximum voltage and the minimum voltage of the input voltage value are in appropriate states with respect to respective reference values (for example, within a range of ±5% relative to reference values) (S81), and when the CPU31determines that the maximum voltage and the minimum voltage of the input voltage value are in appropriate states with respect to respective reference values (S81: yes), since this means that the configuration of the resistance value at the time point is appropriate, the voltage value training process related to transmission from the FM chip40to the FM-CTL30is ended.

On the contrary, when the CPU31determines that the maximum voltage and the minimum voltage of the input voltage value are not in appropriate states with respect to respective reference values (S81: no), since this means that the configuration of the resistance value at the time point is not appropriate, the CPU31changes the reference values related to the input voltage value in the voltage value table62within ranges of the maximum value and the minimum value of the reference values and advances the processing to step S71(S82).

According to the voltage value training process related to transmission from an FM chip to an FM-CTL described above, a voltage value of a signal when transmitting the signal from the FM chip40to the FM-CTL30can be configured to an appropriate value.

Next, a computer system according to a modification will be described. In the following description, differences from the computer system1presented above will be described using reference signs of the computer system1for the sake of convenience.

The firmware memory60further stores a per-signal timing table66.

FIG. 17is a configuration diagram of the per-signal timing table according to the modification.

The per-signal timing table66is a table for managing one or more timings according to specifications of respective signals constituting a control command. The per-signal timing table66manages an entry for each timing of each signal constituting a control command. An entry of the per-signal timing table66includes fields of parameter66a, symbol66b, minimum value (Min)66c, maximum value (Max)66d, and unit66e.

Parameter66astores a type of a timing of a signal corresponding to the entry. In the present embodiment, examples of types of timings of a signal include a setup time (CLE Setup Time) of a CLE signal and a hold time (CLE Hold Time) of a CLE signal. Symbol66bstores a symbol indicating the parameter corresponding to the entry. Minimum value66cstores a minimum value of the parameter corresponding to the entry. Maximum value66dstores a maximum value of the parameter corresponding to the entry. Unit66estores a unit of the parameter corresponding to the entry. According to the first and second entries of the per-signal timing table66, it is revealed that timings of a CLE signal constituting a command latch include a setup time of the CLE signal and a hold time of the CLE signal, a shortest time of the setup time of the CLE signal is 12 us (microseconds), and a shortest time of the hold time of the CLE signal is 5 us. As a result, it is revealed that a shortest time of the command latch is the time obtained as a sum of the shortest times of the setup time of the CLE signal and the hold time of the CLE signal or, in other words, 12+5=17 us.

With a command timing training process according to the modification, in the command timing training process shown inFIG. 14, when the values of the issued command and the received command are consistent (S44: yes), the CPU31refers to the per-signal timing table66, specifies a shortest time of a signal required by the issued command, and advances the processing to step S47when the current configuration is consistent with the shortest time, but when the current configuration is not consistent with the shortest time, the CPU31updates the timing in S45so as to shorten the time of the command within a range in which the time of the command does not become shorter than the shortest time.

According to this modification, parameters can be optimized while ensuring that signals of a command do not become shorter than the shortest time according to specifications.

It is to be understood that the present invention is not limited to the embodiment described above and that various modifications can be made in the invention without departing from the spirit and scope thereof.

For example, although in the embodiment described above, when the input voltage value is not an appropriate value (no in S53, no in S73), a process of changing an output resistance value (S54to S56, S74to S76) is first executed, and when the input voltage value is still not an appropriate value (no in S57, no in S77), a process of changing an input resistance value (S58to S60, S78to S80) is executed, the present invention is not limited thereto and, for example, when the input voltage value is not an appropriate value, a process of changing an input resistance value may be first executed, and when the input voltage value is still not an appropriate value, a process of changing an output resistance value may be executed. In addition, when the input voltage value is not an appropriate value, only one of the process of changing an output resistance value and the process of changing an input resistance value may be executed. Furthermore, while the voltage value training process related to transmission from the FM-CTL to the FM chip is first executed and the voltage value training process related to transmission from the FM chip to the FM-CTL is next executed, the present invention is not limited thereto and the processes may be executed in a reverse order.

In addition, while a frequency between the FM-CTL30and the DKC10is used as a higher-level I/F frequency of the FM-CTL30in the embodiment described above, the present invention is not limited thereto and, for example, when temporarily storing data from the DKC10in the main memory50and subsequently reading the data from the main memory50and storing the data in the FM chip40(the main memory50is also an example of a higher-level apparatus) and an operating frequency of the main memory50is lower than a frequency between the DKC10and the FM-CTL30or, in other words, when a transfer rate between the FM-CTL30and the main memory50is lower than a transfer rate between the DKC10and the FM-CTL30, the operating frequency of the main memory50may be used as the higher-level I/F frequency.

Furthermore, while a case in which the FMD20is provided in the storage system3or, in other words, a case in which the FMD20executes I/O processes to and from the DKC10is described as an example in the embodiment presented above, the present invention is not limited thereto and a configuration in which the FMD20is connected to a CPU via a PCIe bus may be adopted. In this case, the example of a higher-level apparatus of the FMD20is the CPU.

In addition, a part of or all of the processes performed by the CPU31of the FM-CTL30in the embodiment described above may be performed by a hardware circuit. Furthermore, the programs in the embodiment described above may be installed from a program source. The program source may be a program distribution server or a storage medium (for example, a portable storage medium).