Addition of pre-last transfer acknowledge signal to bus interface to eliminate data bus turnaround on consecutive read and write tenures and to allow burst transfers of unknown length

A mechanism is provided in a microprocessor bus interface to eliminate the turnabout in those cases where the same slave is involved in consecutive read data bus tenures or where the same master and slave are involved in consecutive write data bus tenures. A new optional signal is added to the bus interface, called pre-last transfer acknowledge. The signal is asserted by the slave one cycle before the last transfer acknowledge signal is asserted. The signal is intended to be received by the system's bus arbiter. If the current data tenure and the next data tenure are both read operations directed to the same slave (such as the memory controller) or both write operations from the same master to the same slave, then the arbiter may grant the data bus to the master of the next data tenure the cycle following the assertion of the pre-last transfer acknowledge indicator. This allows the arbiter to grant the bus a cycle earlier than it normally could (where it would have to see the final transfer acknowledge signal before it could grant the bus). Thus, the bus turnaround cycle is eliminated and data bus bandwidth is increased by up to twenty percent.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention generally relates to data transfers from a memory 
unit to a microprocessor and, more particularly, to a slave-to-arbiter 
signal which indicates that the end of a data tenure will be the next 
cycle, thus eliminating a bus turnaround cycle and increasing the 
effective bandwidth of the data bus by up to twenty percent. 
2. Description of the Prior Art 
The bus interface for modern microprocessors often specifies one or more 
bus cycles of dead time between data tenures to allow the previous master 
and slave to restore control signals and get off the system bus. This 
allows handoff between the previous master/slave pair and the next 
master/slave pair without any bus contention problems. Assuming that burst 
transfers require four bus cycles to complete, the dead cycle between 
transfers reduces maximum bus bandwidth by 20%. In cases where the same 
slave is involved in consecutive read data bus tenures or when the same 
master and slave are involved in multiple write data bus tenures, this 
turnaround cycle is unnecessary and reduces the potential performance of 
the microprocessor. A mechanism is needed to eliminate the turnaround in 
these cases. 
SUMMARY OF THE INVENTION 
It is therefore an object of the present invention to provide a mechanism 
in a microprocessor bus interface to eliminate the turnaround in those 
cases where the same slave is involved in consecutive read data bus 
tenures or when the same master and slave are involved in consecutive data 
bus write tenures. 
It is another object of the invention to provide a mechanism to allow burst 
transfers where the length of the transfer is unknown at the start of the 
transfer. 
According to the invention, there is provided a new optional signal to a 
bus interface, called a pre-last transfer acknowledge or a pre-last data 
valid signal which, in a preferred embodiment of the invention, is denoted 
as the PLTA signal. The signal is asserted by the slave one cycle before 
the last transfer acknowledge or data valid signal is asserted. In a 
preferred embodiment of the invention, this transfer acknowledge signal is 
denoted as the TA signal. The pre-last transfer acknowledge signal is 
intended to be received by the system's bus arbiter. If the current data 
tenure and the next data tenure are both read operations directed to the 
same slave (such as the memory controller) or both write operations from 
the same master to the same slave, then the arbiter may grant the data bus 
to the master of the next data tenure the cycle following the assertion of 
the pre-last transfer acknowledge indicator. This allows the arbiter to 
grant the bus a cycle earlier than it normally could (where it would have 
to see the final transfer acknowledge signal before it could grant the 
bus). Thus, the bus turnaround cycle is eliminated and data bus bandwidth 
is increased by up to twenty percent.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION 
The invention is described in terms of the bus design for the PowerPC.RTM. 
microprocessor. The PowerPC.RTM. microprocessor was jointly developed by 
Motorola and International Business Machines (IBM) Corporation and is a 
reduced instruction set computer (RISC). However, it will be understood by 
those skilled in the art that the bus for the PowerPC.RTM. microprocessor 
is applicable to other and different microprocessors and, furthermore, the 
invention is not limited to the PowerPC.RTM. bus. 
Referring now to the drawings, and more particularly to FIG. 1, there is 
shown a block diagram of a microprocessor, such as the PowerPC.RTM., on 
which the present invention may be implemented. The microprocessor 10 is 
connected via its system interface 101 to a system bus 12 comprising a 
64-bit data bus 121 and a 32-bit address bus 122. The system bus 12 is 
connected to a variety of input/output (I/O) adapters and a system memory 
(not shown). The microprocessor 10 uses the system bus 12 for performing 
reads and writes to system memory, among other things. Arbitration for 
both address and data bus mastership is performed by a central, external 
arbiter (not shown). 
The system interface 101 is connected to a memory unit 102, which consists 
of a read queue 1021 and a write queue 1022. The read queue 1021 contains 
addresses for read operations, and the write queue 1022 contains addresses 
and data for write operations. The memory unit 102 is connected to a cache 
104 which stores both instructions and data. The cache may be split into 
instruction and data sections. Instructions and data (operands) in cache 
104 are accessed by the instruction unit 105, consisting of an instruction 
queue 1051, program counter 1052, and issue logic 1053. There is at least 
one execution unit and, in some microprocessors there are a plurality of 
execution units, here represented by an integer unit (IU) 106 and a 
floating point unit (FPU) 107. The issue logic 1053 determines the type of 
instruction and dispatches it to a corresponding execution unit. The IU 
106 includes an arithmetic logic unit (ALU) 1061 which performs scalar 
operations, and the FPU 107 includes an ALU 1071 which performs floating 
point operations. The data outputs from each of the IU 106 and the FPU 107 
may be written to cache 104 from where the data is transferred to the 
memory unit 102 for writing to system memory. 
Instructions and operands are automatically fetched from the system memory 
via the cache 104 into the instruction unit 105 where they are dispatched 
to the execution units. Load and store instructions specify the movement 
of operands to and from the integer and floating-point units and the 
memory system. When an instruction or data access is received, the address 
is calculated. The calculated address is used to check for a hit in the 
cache. If the access misses in the cache 104, the address is used to 
access system memory. All read and write operations are handled by the 
memory unit 102. Memory is accessed through an arbitration mechanism that 
allows devices to compete for bus mastership. 
FIG. 2 is a high level block diagram showing a computer system having a 
plurality of processors 10.sub.0 to 10.sub.N connected to the system bus 
12 together with a main memory 14, typically a random access memory (RAM), 
an input/output (I/O) channel 16, and an arbiter 18. One or more of the 
processors may operate as the central processing unit (CPU), while others 
may be co-procesors having dedicated processing functions, such as video 
display. The I/O channel 16 may connect to one or more direct access 
storage devices (DASDs), such as a hard disk drive. The arbiter 18 
controls access to the system bus 12 by granting control to one potential 
master at a time. Each such potential master has its own unique bus grant. 
Memory accesses in the PowerPC.RTM. microprocessor are divided into address 
and data tenures. There are three phases of each tenure; bus arbitration, 
transfer, and termination, as shown in FIG. 3. Note that address and data 
tenures are distinct from one another and that they can overlap. Having 
independent address and data tenures allows address pipelining and 
split-bus transactions to be implemented at the system level in 
multi-processor systems. FIG. 3 shows a data transfer that consists of a 
single-beat transfer of as many as 64 bits. Four-beat burst transfers of 
32-byte cache sectors require data transfer termination signals for each 
bit of data. 
To begin the data tenure, the PowerPC.RTM. microprocessor arbitrates for 
mastership of the data bus. After the PowerPC.RTM. microprocessor is the 
data bus master, it samples the data bus for read operations or drives the 
data bus for write operations. The data parity and data parity error 
signals ensure the integrity of the data transfer. Data termination 
signals are required for each data beat in a data transfer. In a 
single-beat transaction, the data termination signals also indicate the 
end of the tenure, while in burst accesses, the data termination signals 
apply to individual beats and indicate the end of the tenure only after 
the final data beat. 
In the PowerPC.RTM. microprocessor, four signals are used to terminate data 
bus transactions; TA, DRTRY (data retry), TEA (transfer error 
acknowledge), and in some cases ARTRY. The TA signal indicates normal 
termination of data transactions. The DRTRY signal indicates invalid read 
data in the previous bus clock cycle. The TEA signal indicates a 
non-recoverable bus error event. A DRTRY signal can also terminate a data 
bus transaction, but only if it occurs before the first assertion of the 
TA signal. 
Normal termination of a single-beat data read operation occurs when the TA 
signal is asserted by a responding slave, as shown in FIG. 4. Normal 
termination of a single-beat write transaction occurs when the TA signal 
is asserted by a responding slave, as shown in FIG. 5. For read bursts, 
the DRTRY signal may be asserted one bus clock cycle after the TA signal 
is asserted to signal that the data presented with TA is invalid and that 
the processor must wait for the negation of DRTRY before forwarding data 
to the processor, as shown in FIG. 6. Thus, a data beat can be 
speculatively terminated with TA and then one bus clock cycle later 
confirmed with the negation of DRTRY. The DRTRY signal is valid only for 
read transactions. TA must be asserted one bus clock cycle before the 
first bus clock cycle; otherwise, the results are undefined. FIG. 7 shows 
the effect of using DRTRY during a burst read. It also shows the effect of 
using TA to pace the data transfer rate. The PowerPC.RTM. microprocessor 
data pipeline is interrupted in bus cycle 3 and does not proceed until bus 
clock cycle 4 when the TA signal is reasserted. 
In the context of the PowerPC.RTM. microprocessor, the present invention is 
concerned with the TA signal, and no further description will be given of 
the DRTRY (data retry), TEA (transfer error acknowledge), and ARTRY 
signals. For more information on the PowerPC.RTM. microprocessor, the 
reader is referred to PowerPC 601 RISC Microprocessor User's Manual. 
Since the PowerPC.RTM. microprocessor bus defines burst transfers that 
require a minimum of four bus cycles to complete, the dead cycle between 
transfers reduces maximum bus bandwidth by twenty percent. The data bus 
transition according to the protocol of the PowerPC.RTM. microprocessor 
protocol is summarized in FIG. 8. As clearly illustrated, the data bus has 
a turnaround cycle which limits the bus bandwidth. In cases where the same 
slave is involved in consecutive read data bus tenures or the same master 
and same slave are involved in consecutive write data bus tenures, this 
turnabout cycle is unnecessary. Moreover, the data bus of the PowerPC.RTM. 
microprocessor interface is defined to have one dead bus cycle between 
data tenures in all cases. Where the majority of the data tenures are 
reads from memory or where the same slave is involved in consecutive read 
data tenures or the same master and same slave are involved in consecutive 
write data bus tenures, no bus turnaround cycle is necessary. 
According to the present invention, a new optional signal is added to the 
bus interface, called pre-last transfer acknowledge (PLTA). The signal is 
asserted by the slave one cycle before the last TA is asserted, as 
illustrated in FIG. 9. This signal is intended to be received by the 
system's bus arbiter 18 (shown in FIG. 2). If the current data tenure and 
the next data tenure are both read operations directed to the same slave 
(such as the memory controller) or both write operations from the same 
master to the same slave, then the arbiter may grant the data bus to the 
master of the next data tenure the cycle following the assertion of PLTA 
indicator, allowing the arbiter to grant the bus a cycle earlier than it 
normally could (where it would have to see the final TA before it could 
grant the bus). Thus, the bus turnaround cycle is eliminated and data bus 
bandwidth is increased by up to twenty percent. 
Also according to the present invention, burst transfers of initially 
unknown length can be created. This is illustrated in FIG. 10, to which 
reference is now made. When a read (or write) transfer begins at address 
A, it will be a transfer of some number of bytes (32 for the 
PowerPC.RTM.). The address for block A+1 could be broadcast during the 
data tenure of A, and the PLTA signal could then be asserted the cycle 
before the last TA signal of the data tenure for address A, effectively 
extending the data bus tenure to two burst blocks. This sequence can be 
repeated any number of times, within some possible system restrictions. 
Therefore, a block of memory has been moved, and the length of the block 
was unknown at the start of the tenure. 
While the invention has been described in terms of a single preferred 
embodiment, those skilled in the art will recognize that the invention can 
be practiced with modification within the spirit and scope of the appended 
claims.