Fractional divider based phase locked loops with digital noise cancellation

A PLL includes a fractional divider to generate a periodic PLL output signal in response to REFHF. The fractional divider includes a digital control circuit (DDC) responsive to a digital control input signal and a multi-modulus divider (MMD), which is responsive to REFHF and a first digital control output signal generated by the DDC. A feedback divider (FD) is provided to generate a FD output signal in response to an MMD output signal generated by the MMD. A phase detector (PD) is provided to generate a PD output signal in response to the FD output signal and REF_CLK. A loop filter is provided to generate the digital control input signal in response to the PD output signal as modified by a noise cancellation signal (NCS). The NCS is generated to at least partially compensate for non-random deterministic noise in the MMD output signal.

FIELD

The present invention relates to frequency synthesizer circuits and, more particularly, to frequency synthesizer circuits that perform fractional division of high frequency reference signals.

BACKGROUND

Fractional-N frequency synthesizers can be used to overcome many limitations associated with integer-N frequency synthesizers. In fractional-N frequency synthesizers, the effective frequency divide ratio is a fractional number, which enables a relatively high frequency reference signal to be used to achieve fine resolution of frequencies in synthesizer output signals. This fractional number is typically achieved by periodically changing an integer divide ratio so that a desired fractional number can be approximated. One typical disadvantage associated with fractional-N frequency synthesis is the generation of unwanted low-frequency “spurs” by a dual-modulus (or multi-modulus) divider. These spurs make fractional-N frequency synthesizers impractical for many applications unless they are suppressed to a negligible level. Conventional spur reduction techniques include: (i) digital-to-analog (DAC) phase estimation, (ii) random jittering, which randomizes a divide ratio, (iii) sigma-delta (ΣΔ) noise shaping, which modulates a divide ratio, (iv) phase interpolation; and (v) pulse generation. Some of these spur reduction techniques are disclosed in articles by: S. Pamarti et al., entitled “A Spur Elimination Technique for Phase Interpolation-Based Fractional-N PLLs”, IEEE Trans. on Circuits and Systems, Vol. 55, No. 6, pp. 1639-1647, July (2008); and Li Zhang et al., entitled “A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops”, IEEE Journal of Solid-State Circuits, Vol. 44, No. 11, pp. 2922-2934, November (2009).

As illustrated byFIG. 1A, a frequency synthesizer10may include a fractional-N divider12within a feedback path of a phase-locked loop (PLL), which filters jitter in the output of the divider12. This fractional-N divider12may operate by modulating between two or more integer values. The phase-locked loop of FIG.1A contains a phase detector14, which receives an input reference signal (e.g., 25 MHz), a charge pump16, a loop filter18and a voltage-controlled oscillator (VCO)20. This VCO20generates an output signal having a frequency that is a non-integer multiple of the frequency of the input reference signal. An integer divider22may also be provided for generating an output signal at a reduced frequency relative to the VCO output signal. Examples of the frequency synthesizer10ofFIG. 1Aare disclosed at U.S. Pat. No. 7,532,081 to Partridge et al., entitled “Frequency and/or Phase Compensated Microelectromechanical Oscillator,” and FIG. 3 of U.S. Pat. No. 7,417,510 to Huang, entitled “Direct Digital Interpolative Synthesis”.

FIG. 1Billustrates a frequency synthesizer10′, which includes an integer divider12′ within a feedback path of a phase-locked loop (PLL). This phase-locked loop contains a phase detector14, which receives an input reference signal (e.g., 25 MHz), a charge pump16, a loop filter18and a voltage-controlled oscillator (VCO)20, which generates an output signal having a frequency that is an integer multiple of the frequency of the input reference signal. Multiple fractional-N dividers22a-22dmay be provided for generating output signals having different frequencies, which do not have integer relationships with the output frequency of the VCO20. As will be understood by those skilled in the art, additional circuitry may be needed to reduce jitter in the signals generated by the dividers22a-22d. The dividers22a-22dmay be provided as interpolative dividers as disclosed at FIGS. 4-6 of the '510 patent to Huang. For example, as shown by FIG. 5 of Huang, an interpolative divider can include a fractional-N divider, which receives a VCO clock. A first order delta sigma modulator receives a digital divide ratio (M/N). The integer portion of the digital divide ratio is supplied to the fractional-N divider as a divide control signal, which can be a stream of integers that approximate the fractional divide ratio. A digital quantization error, which corresponds to the fractional portion of the divide ratio, is supplied to a digitally controlled phase interpolator. The jitter introduced by the fractional-N divider can be canceled by interpolation in the phase interpolator, which is based on the digital quantization error supplied by the delta sigma modulator. In this manner, the input clock from the VCO is first divided down by the fractional-N divider according to the control information provided by the delta sigma modulator and then the phase interpolator operates to cancel quantization errors in the output of the fractional-N divider.

Additional examples of fractional-N frequency synthesizers, which utilize an accumulator within a numerically-controlled oscillator and a phase interpolator, are disclosed at FIG. 6 of the '510 patent to Huang and in U.S. Pat. No. 7,724,097 to Carley et al., entitled “Direct Digital Synthesizer for Reference Frequency Generation.” Digitally-controlled oscillators containing interpolative dividers are also disclosed in U.S. Pat. No. 8,441,291 to Hara et al., entitled “PLL Using Interpolative Divider as Digitally Controlled Oscillator,” and U.S. Pat. No. 8,248,175 to Hara, entitled “Oscillator with External Voltage Control and Interpolative Divider in the Output Path.”

Still further examples of fractional-N frequency synthesizers are disclosed in commonly assigned U.S. Pat. No. 8,559,587 to Buell et al., entitled “Fractional-N Dividers Having Divider Modulation Circuits Therein with Segmented Accumulators,” the disclosure of which is hereby incorporated herein by reference. In particular, in FIGS. 2A-2B of the '587 patent, a fractional-N divider circuit100is illustrated as including a multi-modulus divider102, which is configured to perform at least /N and /N+1 frequency division of a first reference signal (REFHF) received at a first input thereof, where N is an integer greater than one. This multi-modulus divider102selectively performs a /N and /N+1 division according to a value of an overflow signal (OVERFLOW) received at a second input thereof. This overflow signal is generated by a divider modulation circuit and phase error calculator104, which is shown as the divider modulation circuit104aand the phase error calculator104b. In particular, the overflow signal is generated in response to a digital code that specifies the sequence of division moduli to be used by the multi-modulus divider102when performing the /N and /N+1 frequency division of the first reference signal REFHF.

The divider modulation circuit and phase error calculator104ofFIG. 2Aincludes an accumulator106having multiple serially-cascaded accumulator segments106a-106ntherein. These segments106a-106ngenerate a corresponding plurality of segments of a count value having at least one period of clock latency therebetween, in response to corresponding bits (LSB, . . . , MSB) of a digital code and corresponding segment overflow signals. The segments106a-106nmay be synchronized with a clock signal, which is shown as a signal (f1) generated by the divider102. For example, a relatively wide 16-bit segmented accumulator, which is typically needed for high resolution, may be defined by a cascaded arrangement of four 4-bit accumulator segments. The segmented accumulator106may provide advantages over typical accumulators within conventional delta-sigma modulators because the per cycle delay through the divider modulation circuit104ais equivalent to the delay through a single segment (106a, . . . ,106n) of the accumulator106, which may need to run at twice a frequency of an output signal (e.g., FOUT). In this manner, the segments of the accumulator106operate collectively as an adder with at least one cycle (and typically many cycles) of latency. This segmented “adder” does not generate accurate counts with each clock signal, but ultimately yields a correct, albeit delayed, sequence of final overflow signals (from segment106n) at a potentially much higher frequency rate. As further illustrated byFIG. 2A, the phase error calculator104bincludes a segment (e.g., four-bit) delay block105athat compensates for the latency between the accumulator segment values associated with segments106n-1and106n. An additional accumulator segment107and delay block105b, which are optional, may be used within the phase error calculator104bto produce a delta-sigma modulated signal that represents the value in the lower accumulator segments that do not directly feed a phase correction circuit110.

This phase correction circuit110is configured to generate a second reference signal (FOUT) in response to the divider output signal (f1) generated by the multi-modulus divider102. The phase correction circuit110includes a D-type flip-flop112, which has a data terminal responsive to the second reference signal FOUTand a synchronization terminal responsive to the divider output signal and a pulse-width locked loop114. This pulse-width locked loop114may include, among other things, an analog phase interpolator and a digital phase selection circuit, as shown byFIG. 2B.

The phase correction circuit110is illustrated as including a pulse-width locked loop114that utilizes a delay line containing a plurality of voltage-controlled delay cells116a-116eto achieve a delay of one VCO period and an additional VCO cell116fto provide equivalent loading. The pulse-width locked loop114further includes an XOR gate118, which operates as a pulse generator to generate a pulse having a width of four delay blocks from the delay line, a charge pump120and capacitive loop filter CL. As shown by the four inputs to each of the pair of multiplexers122a-122b, digital phase selection in fine steps of TVCO/4 can be achieved with analog phase interpolation being performed between these finer steps by an output multiplexer124. This configuration yields two (2) bits of resolution allocated to the multiplexers and additional bits of resolution in the analog phase interpolator. Although not wishing to be bound by any theory, because the edges of the signals provided to the phase interpolator are closely spaced, they typically do not need to be filtered. The close spacing may also yield greater linearity and preclude any need for trimming.

Referring now toFIG. 3, another conventional fractional-N divider circuit100′ is shown as including a multi-modulus divider102, which is configured to perform at least /N and /N+1 frequency division of a first reference signal (REFHF) received at a first input thereof, where N is an integer greater than one. This multi-modulus divider102selectively performs a /N and /N+1 division according to a value of an overflow signal (OVERFLOW) received at a second input thereof. This overflow signal is generated by a divider modulation circuit and phase error calculator104. In particular, the overflow signal is generated in response to a digital code that specifies the sequence of division moduli to be used by the multi-modulus divider102when performing the /N and /N+1 frequency division of the first reference signal REFHF.

The divider modulation circuit104aincludes an accumulator106having multiple serially-cascaded accumulator segments106a-106ntherein. These segments106a-106ngenerate a corresponding plurality of segments of a count value having at least one period of clock latency therebetween, in response to corresponding bits (LSB, . . . , MSB) of a digital code and corresponding segment overflow signals. The phase error calculator104bincludes a plurality of delay elements105a-150band an additional accumulator segment107, which collectively generate multiple bits of a digital phase error that is provided to a phase correction circuit110′. The accumulator segments106a-106nand107are synchronized with a high frequency clock signal, which may be generated by a frequency multiplier109.

This phase correction circuit110′ is configured to generate a second reference signal (FOUT) in response to a divider output signal (f1) generated by the multi-modulus divider102. The phase correction circuit110′ is configured so that the second reference signal (FOUT) has a substantially jitter-free and uniform duty cycle. The phase correction circuit110′ is illustrated as including a pair of latches (e.g., D-type flip-flops)112a-112b, which have data terminals responsive to the second reference signal FOUTand synchronization terminals (e.g., clock terminals) responsive to true and complementary versions of the divider output signal f1, which operates as a duty cycle adjustment circuit, and an analog phase interpolator114′. This phase interpolator114′ may be configured as an analog multiplexer, which combines two edges of the signals generated by the flip-flops112a-112bthat are separate by one VCO period. Programmable filters117a-117care also provided for adjusting the edge rates of the input and output signals and, therefore, the linearity of the analog phase interpolator114′.

SUMMARY OF THE INVENTION

Fractional divider based phase-locked loops (FDPLLs) according to some embodiments of the invention include a fractional divider configured to generate a periodic PLL output signal in response to a first periodic reference signal (REFHF). The fractional divider includes a digital control circuit responsive to a digital control input signal and a multi-modulus divider (MMD), which is responsive to the first periodic reference signal and a first digital control output signal generated by the digital control circuit. A feedback divider (FD) is provided, which is configured to generate a periodic FD output signal in response to a periodic MMD output signal generated by the MMD. A digital phase detector (PD) is provided, which is configured to generate a PD output signal in response to the FD output signal and a second periodic reference signal (REF_CLK). A digital loop filter is provided, which is configured to generate the digital control input signal in response to the phase detector output signal as modified by a noise cancellation signal, which is generated by the digital control circuit. This noise cancellation signal is generated to at least partially compensate for non-random deterministic noise in the MMD output signal, which may be a relatively noisy signal relative to the PLL output signal.

According to still further embodiments of the invention, the first digital control output signal is synchronized to the MMD output signal and the noise cancellation signal is synchronized to the FD output signal, which has a lower frequency relative to the MMD output signal. In some of these embodiments, the fractional divider includes a phase interpolator, which is responsive to a second digital control output signal generated by the digital control circuit. This second digital control output signal may also be synchronized to the MMD output signal.

According to still further embodiments of the invention, the digital control circuit includes a register having a data input responsive to (at least) the second digital control output signal and the noise cancellation signal is derived from a digital signal generated at an output of the register. This register may utilize the FD output signal as a clock signal that synchronizes the frequency at which the noise cancellation signal is updated.

According to still further embodiments of the invention, a phase-locked loop (PLL) integrated circuit includes a fractional divider configured to generate a periodic PLL output signal in response to a first periodic reference signal (REFHF). The fractional divider includes: (i) a digital control circuit, which is responsive to a digital control input signal, (ii) a multi-modulus divider (MMD), which is responsive to the first periodic reference signal and a first digital control output signal generated by the digital control circuit; and (iii) an analog phase interpolator responsive to a second digital control output signal generated by the digital control circuit. A feedback divider (FD) is also provided, which is configured to generate a periodic FD output signal in response to a periodic MMD output signal generated by the MMD. A digital phase detector (PD) is provided, which is configured to generate a PD output signal in response to the FD output signal and a second periodic reference signal. A digital loop filter is provided, which is configured to generate the digital control input signal in response to the phase detector output signal, as modified by a digital noise cancellation signal that varies in response to changes in the second digital control output signal. According to some embodiments of the invention, the noise cancellation signal can be an M-bit digital signal and the second digital control output signal can be an N-bit digital signal, where M and N are positive integers greater than four (4) and M is greater than N. In addition, changes in the second digital control output signal can be synchronized to the MMD output signal. In particular, the digital control circuit may include an accumulator that is synchronized to the MMD output signal and generates the second digital control output signal at an output thereof. The MMD output signal is typically “noisier” than the PLL output signal. Nonetheless, the noise in the MMD output signal may be treated as non-random deterministic digital noise that can be corrected/cancelled at the output of the digital phase detector and before the digital loop filter.

DETAILED DESCRIPTION OF EMBODIMENTS

As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising”, “including”, having” and variants thereof, when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof.

As illustrated byFIG. 4, a fractional divider may be utilized in a forward signal path of a phase-locked loop (PLL) integrated circuit, by adding a feedback signal path utilizing a digital phase detector122, a digital loop filter124and a feedback divider120, connected as illustrated. This embodiment of a fractional divider is illustrated as including a digital control circuit126, a multi-modulus divider (MMD)102and a phase correction circuit110′. The operations of these components of the fractional divider are more fully described hereinabove with respect to FIGS. 2A-2B and 3 and in the aforementioned commonly assigned '587 patent, which is hereby incorporated herein by reference. One potential limitation in the performance of the fractional divider based PLL ofFIG. 4stems from the fact that the potentially high fidelity PLL analog output signal (Fout) may be fed back to produce a lower frequency and relatively noise free (e.g., jitter free) feedback signal to an input of the digital phase detector122, which performs phase comparison operations relative to REF_CLK. As will be understood by those skilled in the art, a less active signal(s) at the input(s) of the digital phase detector122can increase a likelihood of “dead-zone” operation therein, which can limit performance of the PLL.

Referring now toFIG. 5A, a fractional divider based phase-locked loop (FDPLL) according to some embodiments of the invention is illustrated as including a modified digital control circuit126′ within a fractional divider, and a feedback circuit including a feedback divider120, a digital phase detector122, a digital adder125and a digital loop filter124, connected as illustrated. As shown, the digital adder125operates to combine a digital noise cancellation signal generated by the digital control circuit126′ with a signal generated at an output of the digital phase detector122.

As will now be described with respect toFIGS. 5A-5B, a fractional divider based phase-locked loop (FDPLL) according to an embodiment of the invention is less susceptible to “dead-zone” operation within the digital phase detector122and may have higher resolution and better linearity compared to the PLL ofFIG. 4. To achieve this enhanced level of operation, a more “active” signal is provided as feedback to an input of the digital phase detector122. This more active input signal is derived from an output signal (f1) generated by the multi-modulus divider (MMD)102, which is passed through a feedback frequency divider120to a first input of the digital phase detector122, as illustrated. This higher degree of “activity” in the feedback signal provided to the digital phase detector122is a consequence of a higher level of non-random deterministic “noise” (e.g., jitter) in the MMD output signal (f1), which is created as a direct consequence of the modulus control (i.e., /N versus /N+1) provided by the digital control circuit126′. Because this modulus control results in deterministic “noise” (e.g., known jitter) in the MMD output signal (f1), it can be digitally removed from an output of the digital phase detector122, as described more fully hereinbelow.

InFIG. 5A, the feedback divider120within the feedback circuit generates a reduced frequency output signal in response the MMD output signal (f1). This feedback divider120, which may be an integer or fractional divider, also provides the reduced frequency output signal as a synchronizing signal to the digital control circuit126′, as explained more fully hereinbelow with respect toFIG. 5B. Using known operations, the digital phase detector122generates a phase detector output signal in response to determining a phase difference between a reference clock (REF_CLK) and the reduced frequency output signal generated by the feedback divider120. The phase detector output signal is provided to the digital adder125and modified by the noise cancellation signal generated by the digital control circuit126′, as shown. The digital loop filter124receives the modified phase detector output signal and performs a digital filtering operation using known techniques. An output signal generated by the digital loop filter124is provided as an input data signal to the digital control circuit126′. As shown byFIG. 5B, the multi-bit signal generated by the digital loop filter124includes integer and fractional components, which are provided to the digital adder127and accumulator130, respectively. Using known techniques, such as those described in the aforementioned '587 patent, the digital adder127combines the integer component of the output signal generated by the digital loop filter124with an overflow signal generated by the accumulator130. As will be understood by those skilled in the art, the accumulator is synchronized to the MMD output signal (f1).

As further shown byFIG. 5B, the most significant bits (e.g., 8 MSBs) of the accumulator value signal generated by the accumulator130are provided to control operation of the analog phase interpolator114′ within the fractional divider. In contrast, the most significant bits and least significant bits (LSBs) of the accumulator value signal are provided to an M-bit register132, which may be configured from D-type flip-flops (DFFs) that are synchronized to the reduced frequency output signal generated by the feedback divider120. Based on calibration operations during start-up, etc., a programmable non-unity digital scaling operation (e.g., normalization) may be performed on the M-bit output of the register132to thereby yield a digital noise cancellation signal, which is provided to the digital adder125. Although not wishing to be bound by any theory, an accumulator value calculated within a circuit that controls operation of the MMD102and analog phase interpolator114′ can be used to provide digital noise cancellation in the PLL feedback circuit. This noise cancellation, as described herein, can have higher resolution and better linearity compared with “analog” noise cancellation, which can be achieved by feeding back the PLL output signal, as shown byFIG. 4.