Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a lower gate electrode disposed in a dielectric structure. A first ferroelectric structure overlies the lower gate electrode. A first floating electrode structure overlies the first ferroelectric structure. A channel structure overlies the first floating electrode structure. A second floating electrode structure overlies the channel structure. A second ferroelectric structure overlies the second floating electrode structure. An upper gate electrode overlies the second ferroelectric structure.

BACKGROUND

Many modern electronic devices contain electronic memory configured to store data. Electronic memory may be volatile memory or non-volatile memory. Volatile memory stores data while it is powered, while non-volatile memory is able to keep data when power is removed. Some promising candidates for next generation memory technology utilize ferroelectricity to store data, such as ferroelectric field-effect transistor (FeFET) memory, ferroelectric random-access memory (FeRAM), and the like.

DETAILED DESCRIPTION

Some integrated chips (ICs) comprise memory devices. For example, some ICs comprise ferroelectric memory devices (e.g., ferroelectric field-effect transistor (FeFET) memory, ferroelectric random-access memory (FeRAM), etc.) that include a plurality of ferroelectric memory cells (e.g., FeFET memory cell, FeRAM memory cell). Some ferroelectric memory cells comprise a gate electrode (e.g., a metal gate), a ferroelectric structure, a channel structure, and a pair of source/drain regions (e.g., metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMIS-FET)). A selectively-conductive channel is disposed in the channel structure and extends laterally between the source/drain regions.

The ferroelectric memory cell is configured to store data (e.g., binary “0” or binary “1”) based on a polarization state of the ferroelectric structure. For example, the ferroelectric memory cell may have a high conductive state (e.g., a high conductive ON-state) associated with a first data state (e.g., binary “1”) or a low conductive state (e.g., a low conductive OFF-state) associated with a second data state (e.g., binary “0”). In the high conductive state, the ferroelectric structure has a first polarization state (e.g., ferroelectric polarization pointing upward (P-up state)). In the low conductive state, the ferroelectric structure has a second polarization state (e.g., ferroelectric polarization pointing downward (P-down state)).

The ferroelectric memory cell can be programmed into either the high conductive state or the low conductive state by applying corresponding voltages to the gate electrode (e.g., applying corresponding voltages across the ferroelectric structure). For example, a first voltage (e.g., a positive voltage pulse) is applied to the gate electrode to place the ferroelectric structure into the first polarization state, thereby programming the ferroelectric memory cell to the high conductive state. A second voltage (e.g., a negative voltage pulse) is applied to the gate electrode to place the ferroelectric structure into the second polarization state (e.g., switch from the first polarization state to the second polarization state), thereby programming the ferroelectric memory cell to the low conductive state. The ferroelectric memory cell may be read by applying a read voltage to the gate electrode to sense the conductivity of the selectively-conductive channel, thereby determining whether the ferroelectric memory cell is in the high conductive state or the low conductive state (e.g., thereby sensing the current conductive state of the ferroelectric memory cell).

One challenge with the above ferroelectric memory cell is a relatively low ON current (e.g., the current (ION) between the source/drain regions when the ferroelectric memory cell is in the ON-state). The low ON current may negatively affect the performance of the ferroelectric memory device (e.g., the low ON current may cause slow read and/or write speeds). As such, the low ON current may limit the applications in which ferroelectric memory may be employed (e.g., high speed data applications).

Various embodiments of the present disclosure are related to a double gate metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMIS-FET) structure. The double gate MFMIS-FET structure comprises a lower gate electrode disposed in a dielectric structure. A first ferroelectric structure overlies the lower gate electrode. A first floating electrode structure overlies the first ferroelectric structure. A channel structure overlies the first floating electrode structure. A second floating electrode structure overlies the channel structure. A second ferroelectric structure overlies the second floating electrode structure. An upper gate electrode overlies the second ferroelectric structure. A pair of source/drain structures are electrically coupled to the channel structure. A selectively-conductive channel is disposed in the channel structure and extend laterally between the source/drain structures.

In some embodiments, the lower gate electrode is a first gate electrode of the double gate MFMIS-FET, and the upper gate electrode is a second gate electrode of the double gate MFMIS-FET (e.g., the lower gate electrode and the upper gate electrode are configured to control the conductivity of the selectively-conductive channel by setting the polarization state of the first ferroelectric structure and the second ferroelectric structure). For example, the lower gate electrode is utilized (e.g., a voltage pulse applied to the lower gate electrode) to place the first ferroelectric structure into either the first polarization state or the second polarization state, and the upper gate electrode is utilized (e.g., a voltage pulse applied to the upper gate electrode) to place the second ferroelectric structure into either the first polarization state or the second polarization state. As such, the double gate MFMIS-FET can be programmed into either the high conductive state or the low conductive state.

Because the double gate MFMIS-FET comprises the lower gate electrode and the upper gate electrode, the double gate MFMIS-FET may have a high ON current (e.g., the IONof the double gate MFMIS-FET may be twice as large as a typical MFMIS-FET). In some embodiments, the double gate MFMIS-FET may have the high ON current due to the lower gate electrode and the upper gate electrode being able to place the first ferroelectric structure and the second ferroelectric structure into the same polarization state (e.g., P-up state), thereby resulting in the selectively-conductive channel having a relatively high conductivity (e.g., relatively low resistivity). Accordingly, the double gate MFMIS-FET may increase the applications in which ferroelectric memory may be employed (e.g., high speed data applications).

FIG.1illustrates a cross-sectional view100of some embodiments of an integrated chip (IC) comprising a double gate metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMIS-FET) structure. In some embodiments, a ferroelectric memory cell of a ferroelectric memory device comprises the double gate MFMIS-FET structure ofFIG.1.

As shown in the cross-sectional view100ofFIG.1, the IC comprises a first dielectric layer102. A lower gate electrode104is disposed in the first dielectric layer102. A first ferroelectric structure106is disposed over the lower gate electrode104. A first floating electrode structure108is disposed over the first ferroelectric structure106. A first insulating structure109is disposed over the first floating electrode structure108. A channel structure110is disposed over the first insulating structure109. The first insulating structure109electrically isolates the first floating electrode structure108from the channel structure110.

A second insulating structure111is disposed over the channel structure110. A second floating electrode structure112is disposed over the channel structure110. The second insulating structure111electrically isolates the second floating electrode structure112from the channel structure110. A second ferroelectric structure114is disposed over the second floating electrode structure112. An upper gate electrode116is disposed over the second ferroelectric structure114. The upper gate electrode116is disposed in a second dielectric layer118.

A first pair of source/drain (S/D) structures120are disposed over the channel structure110. For example, a first S/D structure120aand a second S/D structure120bare disposed over the channel structure110. The first S/D structure120ais laterally spaced from the second S/D structure120b. A selectively-conductive channel122is disposed in the channel structure110and extends laterally between the first S/D structure120aand the second S/D structure120b.

The upper gate electrode116is disposed laterally between the first S/D structure120aand the second S/D structure120b. The second ferroelectric structure114is disposed laterally between the first S/D structure120aand the second S/D structure120b. The second floating electrode structure112is disposed laterally between the first S/D structure120aand the second S/D structure120b. The second insulating structure111is disposed laterally between the first S/D structure120aand the second S/D structure120b. In some embodiments, portions of the second dielectric layer118are disposed laterally between (e.g., directly laterally between) the first pair of S/D structures120and the upper gate electrode116. The first pair of S/D structures120extend vertically through the second dielectric layer118to the channel structure110. The first pair of S/D structures120are electrically coupled to the channel structure110.

A first plurality of spacer structures124are disposed over the channel structure110. For example, a first spacer structure124aand a second spacer structure124bare disposed over the channel structure110. The first plurality of spacer structures124are disposed along sidewalls of the first pair of S/D structures120. The first plurality of spacer structures124extend vertically along sidewalls of the first pair of S/D structures120. The first plurality of spacer structures124are disposed laterally between the pair or S/D structures120and surrounding structural features (e.g., the second ferroelectric structure114, the second floating electrode structure112, the upper gate electrode116, etc.). The first plurality of spacer structures124are configured to provide electrical isolation between the pair or S/D structures120and the surrounding structural features.

For example, the first spacer structure124ais disposed along outer sidewalls of the first S/D structure120a. The first spacer structure124aextends vertically along the outer sidewalls of the first S/D structure120a. The first spacer structure124ais disposed laterally between the first S/D structure120aand the second floating electrode structure112(and the second ferroelectric structure114), and the first spacer structure124aelectrically isolates the first S/D structure120afrom the second floating electrode structure112(and the second ferroelectric structure114). Likewise, the second spacer structure124bis disposed along outer sidewalls of the second S/D structure120b. The second spacer structure124bextends vertically along the outer sidewalls of the second S/D structure120b. The second spacer structure124bis disposed laterally between the second S/D structure120band the second floating electrode structure112(and the second ferroelectric structure114), and the second spacer structure124belectrically isolates the second S/D structure120bfrom the second floating electrode structure112(and the second ferroelectric structure114). In some embodiments, the portions of the second dielectric layer118are disposed laterally between (e.g., directly laterally between) the first plurality of spacer structures124and the upper gate electrode116. In other embodiments, the first plurality of spacer structures124contact (e.g., directly contact) the upper gate electrode116.

The lower gate electrode104, the first ferroelectric structure106, the first floating electrode structure108, the first insulating structure109, the channel structure110, the second insulating structure111, the second floating electrode structure112, the second ferroelectric structure114, the upper gate electrode116, the first pair of S/D structures120, and the selectively-conductive channel122are parts of a double gate MFMIS-FET structure. The double gate MFMIS-FET structure is configured to store data (e.g., binary “0” or binary “1”) based on a polarization state of the first ferroelectric structure106and/or a polarization state of the second ferroelectric structure114. For example, the double gate MFMIS-FET structure may have a high conductive state (e.g., a high conductive ON-state) associated with a first data state (e.g., binary “1”) or a low conductive state (e.g., a low conductive OFF-state) associated with a second data state (e.g., binary “0”). In the high conductive state, the first ferroelectric structure106and the second ferroelectric structure114may have a first polarization state (e.g., P-up state), and thus the selectively-conductive channel122has a relatively high conductivity (e.g., relatively low resistivity). In the low conductive state, the first ferroelectric structure106and the second ferroelectric structure114may have a second polarization state (e.g., P-down state), and thus the selectively-conductive channel122has a relatively low conductivity (e.g., relatively high resistivity).

The MFMIS-FET structure can be programmed into either the high conductive state or the low conductive state by applying corresponding voltages to the upper gate electrode116and/or the lower gate electrode104(e.g., applying a voltage across the second ferroelectric structure114and across the first ferroelectric structure106). In some embodiments, the lower gate electrode104is a first gate electrode of the double gate MFMIS-FET, and the upper gate electrode116is a second gate electrode of the double gate MFMIS-FET (e.g., the lower gate electrode104and the upper gate electrode116are configured to control the conductivity of the selectively-conductive channel122by setting the polarization state of the first ferroelectric structure106and the second ferroelectric structure114). For example, a first voltage (e.g., a positive voltage pulse) is applied to the upper gate electrode116(e.g., via a metal interconnect wire that is electrically coupled to the upper gate electrode116) to place the second ferroelectric structure114into the first polarization state and applied to the lower gate electrode104(e.g., via a metal interconnect wire that is electrically coupled to the lower gate electrode104) to place the first ferroelectric structure106into the first polarization state, thereby programming the double gate MFMIS-FET structure to the high conductive state. On the other hand, a second voltage (e.g., a negative voltage pulse) may be applied to the upper gate electrode116to place the second ferroelectric structure114into the second polarization state (e.g., switch from the first polarization state to the second polarization state) and applied to the lower gate electrode104to place the first ferroelectric structure106into the second polarization state, thereby programming the double gate MFMIS-FET structure to the low conductive state. The double gate MFMIS-FET structure may be read by applying a read voltage to the upper gate electrode116and/or the lower gate electrode104to sense the conductivity of the selectively-conductive channel122, thereby determining whether the double gate MFMIS-FET structure is in the high conductive state or the low conductive state (e.g., thereby sensing the conductive state of the ferroelectric memory cell).

Because the double gate MFMIS-FET comprises the lower gate electrode104and the upper gate electrode116, the double gate MFMIS-FET may have a high ON current (e.g., the current (ION) between the first pair of S/D structures120of the double gate MFMIS-FET may be twice as large as a typical MFMIS-FET when in the ON-state). In some embodiments, the double gate MFMIS-FET may have the high ON current due to the lower gate electrode104and the upper gate electrode116being able to place the first ferroelectric structure106and the second ferroelectric structure114into the same polarization state (e.g., the first polarization state), thereby resulting in the selectively-conductive channel having a relatively high conductivity (e.g., relatively low resistivity) in comparison to a typical MFMIS-FET. The high ON current may improve the device performance of the ferroelectric memory (e.g., decreased read/write times). As such, the double gate MFMIS-FET may increase the applications in which ferroelectric memory may be employed (e.g., high speed data applications).

FIG.2illustrates a cross-sectional view200of some other embodiments of the double gate MFMIS-FET structure ofFIG.1.

As shown in the cross-sectional view200ofFIG.2, the lower gate electrode104is buried in the first dielectric layer102. In some embodiments, the lower gate electrode104has an upper surface that is co-planar with an upper surface of the first dielectric layer102. The first dielectric layer102may be or comprise, for example, a low-k dielectric (e.g., a dielectric material with a dielectric constant less than about 3.9), an oxide (e.g., silicon dioxide (SiO2)), a nitride (e.g., silicon nitride (SiN)), an oxy-nitride (e.g., silicon oxy-nitride (SiON)), undoped silicate glass (USG), doped silicon dioxide (e.g., carbon doped silicon dioxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), a spin-on glass (SOG), or the like. In some embodiments, the first dielectric layer102is an intermetal dielectric (IMD) layer.

The lower gate electrode104may be or comprise, for example, platinum (Pt), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), gold (Au), iron (Fe), nickel (Ni), beryllium (Be), chromium (Cr), cobalt (Co), antimony (Sb), iridium (Jr), molybendum (Mo), osmium (Os), thorium (Th), vanadium (V), some other metal or metal nitride, or a combination of the foregoing. In some embodiments, the lower gate electrode104may have a a0lattice constant of about 4 angstrom (Å) to about 5 angstrom (Å). In some embodiments, the lower gate electrode104may have a thickness between about 50 nanometers (nm) and about 1000 nm.

In some embodiments, a stress layer202is disposed over the lower gate electrode104and the first dielectric layer102. In other embodiments, the stress layer202is omitted. The stress layer202overlies, at least partially, the lower gate electrode104. The stress layer202is configured to apply a tensile stress on the first ferroelectric structure106. The tensile stress stabilizes the orthorhombic crystal phase (o-phase) of the first ferroelectric structure106. The stress layer202may apply the tensile stress by having a lattice mismatch between the stress layer202and the first ferroelectric structure106and/or having a different coefficient of thermal expansion (CTE) than the first ferroelectric structure106. In some embodiments, the tensile stress is an a-axis tensile stress and/or an in-plane tensile stress that is applied to stabilize the o-phase of the first ferroelectric structure106. In further embodiments, the stress layer202is configured to cause, at least partially, a crystal phase transition in the first ferroelectric structure106from a [100]-oriented tetragonal grain to a [001]-oriented out-of-plane polarized orthorhombic grain (e.g., due to the stress layer202being formed with a predefined set of lattice parameters).

In some embodiments, the stress layer202has a different CTE than the first ferroelectric structure106(e.g., a lower CTE than the lower gate electrode104). In some embodiments, the CTE of the stress layer202is less than about 4×10−6/K. In further embodiments, the stress layer202applies the tensile stress to the first ferroelectric structure106due to a thermal annealing process (e.g., between about 400° C. and about 700° C.) being performed on the stress layer202. In some embodiments, the stress layer202may have a thickness between about 0.5 nm and about 5 nm. The stress layer202may be or comprise, for example, tantalum oxide (Ta2O5), potassium oxide (K2O), rubidium oxide (Rb2O), strontium oxide (SrO), barium oxide (BaO), amorphous vanadium oxide (a-V2O3), amorphous chromium oxide (a-Cr2O3), amorphous gallium oxide (a-Ga2O3), amorphous iron oxide (Fe2O3), amorphous titanium oxide (a-Ti2O3), amorphous indium oxide (a-In2O3), yttrium aluminum oxide (YAlO3), bismuth oxide (Bi2O3), ytterbium oxide (Yb2O3), dysprosium oxide (Dy2O3), gadolinium oxide (Gd2O3), strontium titanium oxide (SrTiO3), dysprosium scandium oxide (DyScO3), terbium scandium oxide (TbScO3), gadolinium scandium oxide (GdScO3), neodymium scandium oxide (NdScO3), neodymium gallium oxide (NdGaO3), lanthanum strontium aluminum tantalum oxide (LSAT), lanthanum strontium manganese oxide (LSMO), some other material capable of applying a tensile stress to the first ferroelectric structure106, or a combination of the foregoing. In some embodiments, the stress layer202is a bi-layer structure comprising two of the above described materials (e.g., LSMO/SrTiO3, LSMO/DySCO3, LSMO/TbScO3, LSMO/GdScO3, LSMO/NdScO3, LSMO/NdGaO3, LSMO/LSAT, etc.).

In some embodiments, the stress layer202may apply about 1.8 percent (%) to about 3.5 percent (%) tensile stress to the first ferroelectric structure106. If the stress layer202applies a tensile stress between about 1.8% and about 3.5%, the o-phase of the first ferroelectric structure106may be better stabilized. In some embodiments, the stress layer202is epi-Gd/ScO3with a lattice constant of about 3.91 angstrom (Å) and provides about 2.5% tensile stress to the first ferroelectric structure106. In further embodiments, the stress layer202has a a0lattice constant that is larger than the in-plane lattice constant of the first ferroelectric structure106.

The first ferroelectric structure106is disposed over the stress layer202. The first ferroelectric structure106overlies, at least partially, the stress layer202. The first ferroelectric structure106overlies, at least partially, the lower gate electrode104. The first ferroelectric structure106may be or comprise, for example, hafnium zirconium oxide (HfZrO), scandium-doped aluminum nitride (AlScN), some other ferroelectric material, or a combination of the foregoing. In some embodiments, the first ferroelectric structure106is hafnium zirconium oxide (HfZrO). The first ferroelectric structure106may be hafnium zirconium oxide (HfZrO) and comprise oxygen vacancies. In some embodiments, the first ferroelectric structure106is hafnium zirconium oxide (HfZrO) that is doped with aluminum (Al), silicon (Si), lanthanum (La), scandium (Sc), calcium (Ca), barium (Ba), gadolinium (Gd), yttrium (Y), strontium (Sr), or the like. In some embodiments, the first ferroelectric structure106may have a thickness between about 0.1 nm and about 100 nm.

In some embodiments, the first ferroelectric structure106is hafnium zirconium oxide (HfxZr1−xOy), where X is between zero (0) and one (1). In further embodiments, the first ferroelectric structure106is hafnium zirconium oxide (Hf0.5Zr0.5O2). In yet further embodiments, the first ferroelectric structure106may have four different crystal phases: an orthorhombic phase (o-phase), a monoclinic phase (m-phase), a tetragonal phase (t-phase), and a cubic phase (cubic-phase). In yet further embodiments, the monoclinic phase may be less than fifth percent (50%) of a combination of the four crystal phases of the first ferroelectric structure106.

The first floating electrode structure108is disposed over the first ferroelectric structure106. The first floating electrode structure108overlies, at least partially, the first ferroelectric structure106. The first floating electrode structure108may be or comprise, for example, titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), platinum (Pt), gold (Au), or the like. In some embodiments, the first floating electrode structure108has a thickness between about 1 nm and about 50 nm.

The first insulating structure109is disposed over the first floating electrode structure108. In some embodiments, the first insulating structure109is omitted. The first insulating structure109overlies, at least partially, the first floating electrode structure108. The first insulating structure109electrically isolates the first floating electrode structure108from the channel structure110. The first insulating structure109may be or comprise, for example, hafnium oxide (HfO2), silicon doped hafnium oxide (HSO), hafnium zirconium oxide (HfZrO), silicon oxide (SiO2), aluminum oxide (Al2O3), yttrium oxide (Y2O3), zirconium oxide (ZrO2), magnesium oxide (MgO), or the like. In some embodiments, the first insulating structure109has a thickness between about 0.1 nm and about 10 nm. In some embodiments, the first insulating structure109is silicon doped hafnium oxide (HSO) and comprises at least 10% silicon atoms. In some embodiments, the first insulating structure109is a bi-layer structure comprising a silicon doped hafnium oxide (HSO) layer and a hafnium zirconium oxide (HfZrO) layer. In such embodiments, the hafnium zirconium oxide (HfZrO) layer may have a thickness of about 1 nm.

The channel structure110is disposed over the first insulating structure109. The channel structure110overlies, at least partially, the first insulating structure109. In some embodiments, the channel structure110is or comprises a semiconductor material. In further embodiments, the channel structure110is or comprises, for example, indium gallium zinc oxide (IGZO); amorphous indium gallium zinc oxide (a-IGZO); tin gallium zinc oxide (SnGaZnO); gallium oxide (GaO); indium oxide (InO); zinc oxide (ZnO); gallium arsenide (GaAs); gallium nitride (GaN); aluminum gallium arsenide (AlGaAs); some indium-zinc-oxide compound containing hafnium (Hf), zirconium (Zr), titantium (Ti), aluminum (Al), tantalum (Ta), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La), gadolinium (Gd); a group III-V semiconductor; a compound semiconductor; amorphous silicon (a-Si); polycrystalline silicon; or some other suitable material. In some embodiments, the channel structure110has a thickness of about 3 nm to about 100 nm.

The second insulating structure111is disposed over the channel structure110. The second insulating structure111overlies, at least partially, the channel structure110. In some embodiments, the second insulating structure111is omitted. The second insulating structure111electrically isolates the channel structure110from the second floating electrode structure112. The second insulating structure111may be or comprise, for example, hafnium oxide (HfO2), silicon doped hafnium oxide (HSO), hafnium zirconium oxide (HfZrO), silicon oxide (SiO2), aluminum oxide (Al2O3), yttrium oxide (Y2O3), zirconium oxide (ZrO2), magnesium oxide (MgO), or the like. In some embodiments, the second insulating structure111has a thickness between about 0.1 nm and about 10 nm. In some embodiments, the second insulating structure111is silicon doped hafnium oxide (HSO) and comprises at least 10% silicon atoms. In some embodiments, the second insulating structure111is a bi-layer structure comprising a silicon doped hafnium oxide (HSO) layer and a hafnium zirconium oxide (HfZrO) layer. In such embodiments, the hafnium zirconium oxide (HfZrO) layer may have a thickness of about 1 nm. In some embodiments, the first insulating structure109and the second insulating structure111comprise a same material(s) and/or have a same thickness. In some embodiments, because the first insulating structure109and the second insulating structure111comprise a same material(s) and have a same thickness, the double gate MFMIS-FET may be utilized in a redundancy configuration.

The second floating electrode structure112is disposed over the second insulating structure111. The second floating electrode structure112overlies, at least partially, the second insulating structure111. The second floating electrode structure112may be or comprise, for example, titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), platinum (Pt), gold (Au), or the like. In some embodiments, the second floating electrode structure112has a thickness between about 1 nm and about 50 nm. In some embodiments, the second floating electrode structure112and the first floating electrode structure108comprise a same material(s) and/or have a same thickness. In some embodiments, because the second floating electrode structure112and the first floating electrode structure108comprise a same material(s) and have a same thickness, the double gate MFMIS-FET may be utilized in a redundancy configuration.

The second ferroelectric structure114is disposed over the second floating electrode structure112. The second ferroelectric structure114overlies, at least partially, the second floating electrode structure112. The second ferroelectric structure114may be or comprise, for example, hafnium zirconium oxide (HfZrO), scandium-doped aluminum nitride (AlScN), some other ferroelectric material, or a combination of the foregoing. In some embodiments, the second ferroelectric structure114is hafnium zirconium oxide (HfZrO). The second ferroelectric structure114may be hafnium zirconium oxide (HfZrO) and comprise oxygen vacancies. In some embodiments, the second ferroelectric structure114is hafnium zirconium oxide (HfZrO) that is doped with aluminum (Al), silicon (Si), lanthanum (La), scandium (Sc), calcium (Ca), barium (Ba), gadolinium (Gd), yttrium (Y), strontium (Sr), or the like. In some embodiments, the second ferroelectric structure114may have a thickness between about 0.1 nm and about 100 nm.

In some embodiments, the second ferroelectric structure114is hafnium zirconium oxide (HfxZr1−xOy), where X is between zero (0) and one (1). In further embodiments, the second ferroelectric structure114is hafnium zirconium oxide (Hf0.5Zr0.5O2). In yet further embodiments, the second ferroelectric structure114may have four different crystal phases: an orthorhombic phase, a monoclinic phase, a tetragonal phase, and a cubic phase. In yet further embodiments, the monoclinic phase may be less than fifth percent (50%) of a combination of the four crystal phases of the second ferroelectric structure114. In some embodiments, the second ferroelectric structure114and the first ferroelectric structure106comprise a same material(s) and/or have a same thickness. In some embodiments, because the second ferroelectric structure114and the first ferroelectric structure106comprise a same material(s) and have a same thickness, the double gate MFMIS-FET may be utilized in a redundancy configuration.

The second dielectric layer118is disposed over the second ferroelectric structure114. In some embodiments, the second dielectric layer118overlies, at least partially, the second ferroelectric structure114. The second dielectric layer118may be or comprise, for example, a low-k dielectric (e.g., a dielectric material with a dielectric constant less than about 3.9), an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiON), undoped silicate glass (USG), doped silicon dioxide (e.g., carbon doped silicon dioxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), a spin-on glass (SOG), or the like. In some embodiments, the second dielectric layer118is an IMD layer.

The upper gate electrode116is disposed in the second dielectric layer118. In some embodiments, the upper gate electrode116has an upper surface that is substantially coplanar with an upper surface of the second dielectric layer118. The upper gate electrode116overlies, at least partially, the second ferroelectric structure114. The upper gate electrode116may be or comprise, for example, platinum (Pt), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), gold (Au), iron (Fe), nickel (Ni), beryllium (Be), chromium (Cr), cobalt (Co), antimony (Sb), iridium (Ir), molybendum (Mo), osmium (Os), thorium (Th), vanadium (V), some other metal or metal nitride, or a combination of the foregoing. In some embodiments, the upper gate electrode116may have a a0lattice constant of about 4 Å to about 5 Å. In some embodiments, the upper gate electrode116may have a thickness between about 50 nm and about 1000 nm. In some embodiments, the upper gate electrode116and the lower gate electrode104comprise a same material(s) and/or have a same thickness. In some embodiments, because the upper gate electrode116and the lower gate electrode104comprise a same material(s) and have a same thickness, the double gate MFMIS-FET may be utilized in a redundancy configuration.

The first pair of S/D structures120overlies the channel structure110. The first pair of S/D structures120may be or comprise, for example, titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), platinum (Pt), gold (Au), or the like. In some embodiments, the first pair of S/D structures120may have a thickness between about 50 nm and about 1000 nm. For example, the first S/D structure120amay have a thickness between about 50 nm and about 1000 nm, and the second S/D structure120bmay also have a thickness between about 50 nm and about 1000 nm.

The first plurality of spacer structures124overlie, at least partially, the channel structure110. The first plurality of spacer structures124extend vertically along the sidewalls of the first pair of S/D structures120. In some embodiments, the first plurality of spacer structures124extend laterally around the first pair of S/D structures120, respectively, in closed loop paths. For example, the first spacer structure124aextends laterally around the first S/D structure120ain a closed loop path. The first plurality of spacer structures124may be or comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiON), some other dielectric material, or a combination of the foregoing.

Also shown in the cross-sectional view200ofFIG.2, the upper gate electrode116overlies, at least partially, the second ferroelectric structure114, the second floating electrode structure112, the second insulating structure111, the channel structure110, the selectively-conductive channel122, the first insulating structure109, the first floating electrode structure108, the first ferroelectric structure106, the stress layer202, and/or the lower gate electrode104. In some embodiments, the lower gate electrode104is disposed laterally between the first S/D structure120aand the second S/D structure120b. In further embodiments, the lower gate electrode104is disposed laterally between the first spacer structure124aand the second spacer structure124b.

FIG.3illustrates a cross-sectional view300of some other embodiments of the double gate MFMIS-FET structure ofFIG.2.

As shown in the cross-sectional view300ofFIG.3, in some embodiments, a first seed layer302is disposed vertically between the stress layer202and the first ferroelectric structure106. The first seed layer302may improve the polarization (e.g., 2Pr) of the double gate MFMIS-FET. In some embodiments, the first seed layer302is disposed vertically between the lower gate electrode104and the first ferroelectric structure106. The first seed layer302may be or comprise, for example, zirconium oxide (ZrO2), yttrium oxide (Y2O3), zirconium yttrium oxide (ZrYO), hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium zirconium oxide (HfxZr1−xOy), some other suitable material, or a combination of the foregoing. In some embodiments, the first seed layer302may be cubic-phase, t-phase, and/or o-phase zirconium oxide (Zr); cubic-phase, t-phase, and/or o-phase yttrium oxide (ZrYO); cubic-phase, t-phase, and/or o-phase hafnium oxide (HfO2); cubic-phase, t-phase, and/or o-phase aluminum oxide (Al2O3); or the like. In further embodiments, the first seed layer302may have a thickness between about 0.1 nm and about 5 nm. In yet further embodiments, the first seed layer302may comprise one or more layers (e.g., a multi-layered seed layer).

FIG.4illustrates a cross-sectional view400of some other embodiments of the double gate MFMIS-FET structure ofFIG.3.

As shown in the cross-sectional view400ofFIG.4, in some embodiments, a second seed layer402is disposed vertically between the first ferroelectric structure106and the first floating electrode structure108. In some embodiments, a third seed layer404is disposed vertically between the second ferroelectric structure114and the second floating electrode structure112. In some embodiments, a fourth seed layer406is disposed vertically between the second ferroelectric structure114and the upper gate electrode116. The second seed layer402, the third seed layer404, and the fourth seed layer406may further improve the polarization (e.g., 2Pr) of the double gate MFMIS-FET.

In some embodiments, the second seed layer402, the third seed layer404, and the fourth seed layer406may be or comprise, for example, zirconium oxide (ZrO2), yttrium oxide (Y2O3), zirconium yttrium oxide (ZrYO), hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium zirconium oxide (HfxZr1−xOy), some other suitable material, or a combination of the foregoing. In further embodiments, the second seed layer402, the third seed layer404, and the fourth seed layer406may be cubic-phase, t-phase, and/or o-phase zirconium oxide (Zr); cubic-phase, t-phase, and/or o-phase yttrium oxide (ZrYO); cubic-phase, t-phase, and/or o-phase hafnium oxide (HfO2); cubic-phase, t-phase, and/or o-phase aluminum oxide (Al2O3); or the like. In further embodiments, the second seed layer402, the third seed layer404, and the fourth seed layer406may each have a thickness between about 0.1 nm and about 5 nm. In yet further embodiments, the second seed layer402, the third seed layer404, and the fourth seed layer406each may comprise one or more layers (e.g., a multi-layered seed layer).

FIG.5illustrates a cross-sectional view500of some other embodiments of the double gate MFMIS-FET structure ofFIG.4.

As shown in the cross-sectional view500ofFIG.5, the channel structure110comprises a plurality of channel layers. For example, the channel structure110comprises a plurality of first channel layers502, a plurality of second channel layers504, and a third channel layer506. The first channel layers502comprise a mixture of a first material and a second material. The second channel layers504comprise a third material different than the first and second materials. The third channel layer506comprises a mixture of the first, second, and third materials. In some embodiments, because the channel structure110comprises the plurality of first channel layers502, the plurality of second channel layers504, and the third channel layer506, the double gate MFMIS-FET structure may have improved reliability and switching speeds (e.g., due to the plurality of channel layers reducing defects and increasing charge mobility in the channel structure110).

The third channel layer506is disposed vertically between a first stack508of first and second channel layers and a second stack510of first and second channel layers. The first stack508of first and second channel layers comprises a first set of the first channel layers502and a first set of the second channel layers504, which are stacked vertically in alternating order. The second stack510of first and second channel layers comprises a second set of the first channel layers502and a second set of the second channel layers504, which are stacked vertically in alternating order. In some embodiments, a lowermost layer of the first stack508of first and second channel layers is one of the plurality of first channel layers502. In further embodiments, an uppermost layer of the first stack508of first and second channel layers is one of the plurality of second channel layers504. In some embodiments, an uppermost layer of the second stack510of first and second channel layers is one of the plurality of first channel layers502. In some embodiments, a lowermost layer of the second stack510of first and second channel layers is one of the plurality of second channel layers504. While the cross-sectional view500ofFIG.5illustrates the first stack508of first and second channel layers and the second stack510of first and second channel layers each comprising four layers (two first channel layers502and two second channel layers504), it will be appreciated that the first stack508of first and second channel layers and the second stack510of first and second channel layers may comprise any number of stacked first and second channel layers.

In some embodiments, the first material comprises gallium oxide (GaO), hafnium oxide (HfO), zirconium oxide (ZrO), titanium oxide (TiO), aluminum oxide (AlO), tantalum oxide (TaO), strontium oxide (SrO), barium oxide (BaO), scandium oxide (ScO), magnesium oxide (MgO), lanthanum oxide (LaO), gadolinium oxide (GdO), or the like. In some embodiments, the second material comprises indium oxide (InO), tin oxide (SnO), arsenic oxide (AsO), zinc oxide (ZnO), or the like. In some embodiments, the third material comprises zinc oxide (ZnO). Thus, for example, in some embodiments, the first material comprises gallium oxide (GaO); the second material comprises indium oxide (InO); and the third material comprises zinc oxide (ZnO), such that the first channel layers502comprise a mixture of gallium oxide (GaO) and indium oxide (InO), the second channel layers504comprise zinc oxide (ZnO), and the third channel layer506is indium gallium zinc oxide (IGZO). In further embodiments, the third channel layer506is amorphous indium gallium zinc oxide (a-IGZO).

FIG.6illustrates a cross-sectional view600of some other embodiments of the double gate MFMIS-FET structure ofFIG.5.

As shown in the cross-sectional view600ofFIG.6, the channel structure110may overlie the first pair of S/D structures120. In some embodiments, the lower gate electrode104is disposed laterally between the first S/D structure120aand the second S/D structure120b. The stress layer202may be disposed laterally between the first S/D structure120aand the second S/D structure120b. The first seed layer302may be disposed laterally between the first S/D structure120aand the second S/D structure120b. The first ferroelectric structure106may be disposed laterally between the first S/D structure120aand the second S/D structure120b. The second seed layer402may be disposed laterally between the first S/D structure120aand the second S/D structure120b. The first floating electrode structure108may be disposed laterally between the first S/D structure120aand the second S/D structure120b. The first insulating structure109may be disposed laterally between the first S/D structure120aand the second S/D structure120b.

Further, the first spacer structure124amay laterally separate the first S/D structure120afrom the stress layer202, the first seed layer302, the first ferroelectric structure106, the second seed layer402, the first floating electrode structure108, and/or the first insulating structure109. Likewise, the second spacer structure124bmay laterally separate the second S/D structure120bfrom the stress layer202, the first seed layer302, the first ferroelectric structure106, the second seed layer402, the first floating electrode structure108, and/or the first insulating structure109.

A first conductive structure602and a second conductive structure604are disposed in the first dielectric layer102. The first S/D structure120ais electrically coupled to the first conductive structure602and the channel structure110. The second S/D structure120bis electrically coupled to the second conductive structure604and the channel structure110. In some embodiments, the first conductive structure602and the second conductive structure604are conductive structures of an interconnect structure (e.g., copper interconnect structure) that is at least partially embedded in the first dielectric layer102. For example, the first conductive structure602may be a conductive via (e.g., metal via) or a conductive wire (e.g., metal wire) of the interconnect structure. In some embodiments, the first conductive structure602and the second conductive structure604may be or comprise, for example, copper (Cu), aluminum (Al), tungsten (W), tantalum (Ta), titanium (Ti), gold (Au), some other metal, or a combination of the foregoing.

FIG.7illustrates a cross-sectional view700of some other embodiments of the double gate MFMIS-FET structure ofFIG.6.

As shown in the cross-sectional view700ofFIG.7, a second pair of S/D structure702overlies the channel structure110. For example, a third S/D structure702aand a fourth S/D structure702boverlie the channel structure110. The third S/D structure702ais laterally spaced from the fourth S/D structure702b. The selectively-conductive channel122is disposed in the channel structure110and extends laterally between the third S/D structure702aand the fourth S/D structure702b.

The upper gate electrode116is disposed laterally between the third S/D structure702aand the fourth S/D structure702b. The second ferroelectric structure114is disposed laterally between the third S/D structure702aand the fourth S/D structure702b. The second floating electrode structure112is disposed laterally between the third S/D structure702aand the fourth S/D structure702b. The second insulating structure111is disposed laterally between the third S/D structure702aand the fourth S/D structure702b. In some embodiments, portions of the second dielectric layer118are disposed laterally between (e.g., directly laterally between) the second pair of S/D structures702and the upper gate electrode116. The second pair of S/D structures702extend vertically through the second dielectric layer118to the channel structure110. The second pair of S/D structures702are electrically coupled to the channel structure110.

The second pair of S/D structures702may be or comprise, for example, titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), platinum (Pt), gold (Au), or the like. In some embodiments, the second pair of S/D structures702may have a thickness between about 50 nm and about 1000 nm. For example, the third S/D structure702amay have a thickness between about 50 nm and about 1000 nm.

In some embodiments, the lower gate electrode104, the stress layer202, the first seed layer302, the first ferroelectric structure106, the second seed layer402, the first floating electrode structure108, and/or the first insulating structure109are disposed laterally between the third S/D structure702aand the fourth S/D structure702b. In further embodiments, the upper gate electrode116, the fourth seed layer406, the second ferroelectric structure114, the third seed layer404, the second floating electrode structure112, and/or the second insulating structure111are disposed laterally between the first S/D structure120aand the second S/D structure120b. In some embodiments, the third S/D structure702aoverlies, at least partially, the first S/D structure120a. In further embodiments, the fourth S/D structure702boverlies, at least partially, the second S/D structure120b.

A second plurality of spacer structures704overlie, at least partially, the channel structure110. For example, a third spacer structure704aand a fourth spacer structure704boverlies the channel structure110. The second plurality of spacer structures704are disposed along sidewalls of the second pair of S/D structures702. The second plurality of spacer structures704extend vertically along the sidewalls of the second pair of S/D structures702. The second plurality of spacer structures704are disposed laterally between the pair or S/D structures702and surrounding structural features (e.g., the second ferroelectric structure114, the second floating electrode structure112, the upper gate electrode116, etc.). The second plurality of spacer structures704are configured to provide electrical isolation between the pair or S/D structures702and the surrounding structural features.

For example, the third spacer structure704ais disposed along outer sidewalls of the third S/D structure702a. The third spacer structure704aextends vertically along the outer sidewalls of the third S/D structure702a. The third spacer structure704ais disposed laterally between the third S/D structure702aand the second floating electrode structure112(and the second ferroelectric structure114), and the third spacer structure704aelectrically isolates the third S/D structure702afrom the second floating electrode structure112(and the second ferroelectric structure114). Likewise, the fourth spacer structure704bis disposed along outer sidewalls of the fourth S/D structure702b. The fourth spacer structure704bextends vertically along the outer sidewalls of the fourth S/D structure702b. The fourth spacer structure704bis disposed laterally between the fourth S/D structure702band the second floating electrode structure112(and the second ferroelectric structure114), and the fourth spacer structure704belectrically isolates the fourth S/D structure702bfrom the second floating electrode structure112(and the second ferroelectric structure114).

In some embodiments, portions of the second dielectric layer118are disposed laterally between (e.g., directly laterally between) the second plurality of spacer structures704and the upper gate electrode116. In other embodiments, the second plurality of spacer structures704contact (e.g., directly contact) the upper gate electrode116. In some embodiments, the second plurality of spacer structures704extend laterally around the second pair of S/D structures702, respectively, in closed loop paths. For example, the third spacer structure704aextends laterally around the third S/D structure702ain a closed loop path. The second plurality of spacer structures704may be or comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiON), some other dielectric material, or a combination of the foregoing.

In some embodiments, the lower gate electrode104, the stress layer202, the first seed layer302, the first ferroelectric structure106, the second seed layer402, the first floating electrode structure108, and/or the first insulating structure109are disposed laterally between the third spacer structure704aand the fourth spacer structure704b. In some embodiments, the upper gate electrode116, the fourth seed layer406, the second ferroelectric structure114, the third seed layer404, the second floating electrode structure112, and/or the second insulating structure111are disposed laterally between the first spacer structure124aand the second spacer structure124b. In further embodiments, an outer perimeter of the third spacer structure704aoverlaps an outer perimeter of the first spacer structure124a(e.g., the third spacer structure704aoverlies, at least partially, the first spacer structure124a). In yet further embodiments, an outer perimeter of the fourth spacer structure704boverlaps an outer perimeter of the second spacer structure124b(e.g., the fourth spacer structure704boverlies, at least partially, the second spacer structure124b).

Because the double gate MFMIS-FET comprises the lower gate electrode104, the upper gate electrode116, the first pair of S/D structures120, and the second pair of S/D structures702, the double gate MFMIS-FET may be utilized in a redundancy configuration (e.g., the upper gate electrode116and the second pair of S/D structures702are used as a back-up for the lower gate electrode104and the first pair of S/D structures120, or vice versa). As such, the double gate MFMIS-FET may increase the yield of ferroelectric memory devices, thereby lowering the cost to fabricate ferroelectric memory devices. Further, in some embodiments, the double gate MFMIS-FET may still have a high ON current in the redundancy configuration (e.g., due to the double gate MFMIS-FET comprising both the upper and lower gate electrodes). Thus, the double gate MFMIS-FET may lower the cost to fabricate ferroelectric memory and improve the performance of the ferroelectric memory (e.g., decreased read/write times).

FIG.8illustrates a cross-sectional view800of some other embodiments of the double gate MFMIS-FET structure ofFIG.7.

As shown in the cross-sectional view800ofFIG.8, a third dielectric layer802is disposed over the first dielectric layer102. The stress layer202, the first seed layer302, the first ferroelectric structure106, the second seed layer402, the first floating electrode structure108, the first insulating structure109, the first pair of S/D structure120, and the first plurality of spacer structures124may be disposed in the third dielectric layer802. A fourth dielectric layer804is disposed over the third dielectric layer802. The channel structure110may be disposed in the fourth dielectric layer804. In some embodiments, the upper gate electrode116, the fourth seed layer406, the second ferroelectric structure114, the third seed layer404, the second floating electrode structure112, the second insulating structure111, the second pair of S/D structures702, and the second plurality of spacer structures704may be disposed in the second dielectric layer118.

In some embodiments, a fifth dielectric layer806overlies the second dielectric layer118. A third conductive structure808, a fourth conductive structure810, and a fifth conductive structure812are disposed in the fifth dielectric layer806. The third S/D structure702ais electrically coupled to the third conductive structure808and the channel structure110. The fourth S/D structure702bis electrically coupled to the fourth conductive structure810and the channel structure110. The fifth conductive structure812is electrically coupled to the upper gate electrode116. In some embodiments, the third conductive structure808, the fourth conductive structure810, and the fifth conductive structure812are conductive structures of the interconnect structure (e.g., the copper interconnect structure) that is at least partially embedded in the first dielectric layer102, the second dielectric layer118, the third dielectric layer802, the fourth dielectric layer804, and the fifth dielectric layer806. For example, the third conductive structure808may be a conductive via (e.g., metal via) or a conductive wire (e.g., metal wire) of the interconnect structure.

In some embodiments, the third conductive structure808, the fourth conductive structure810, and the fifth conductive structure812may be or comprise, for example, copper (Cu), aluminum (Al), tungsten (W), tantalum (Ta), titanium (Ti), gold (Au), some other metal, or a combination of the foregoing. The third dielectric layer802, the fourth dielectric layer804, and the fifth dielectric layer806may be or comprise, for example, a low-k dielectric (e.g., a dielectric material with a dielectric constant less than about 3.9), an oxide (e.g., silicon dioxide (SiO2)), a nitride (e.g., silicon nitride (SiN)), an oxy-nitride (e.g., silicon oxy-nitride (SiON)), undoped silicate glass (USG), doped silicon dioxide (e.g., carbon doped silicon dioxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), a spin-on glass (SOG), or the like. In some embodiments, the third dielectric layer802, the fourth dielectric layer804, and the fifth dielectric layer806may be IMD layers.

Also shown in the cross-sectional view800ofFIG.8, in some embodiments, a first plurality of remnant structures are disposed on opposite sides of the first pair of S/D structures120. The first plurality of remnant structures are a same material as corresponding structural features disposed laterally between the first S/D structure120aand the second S/D structure120b. For example, the first plurality of remnant structures comprise first, second, third, and fourth remnant structures. The first remnant structure and the third remnant structure are disposed on a first side of the first S/D structure120a, and the second remnant structure and the fourth remnant structure are disposed on a second side of the second S/D structure120bopposite the first side of the first S/D structure120a. The first remnant structure, the second remnant structure, and the first ferroelectric structure106are disposed in a first lateral plane; and the third remnant structure, the fourth remnant structure, and the first floating electrode structure108are disposed in a second lateral plane. As such, the first remnant structure and the second remnant structure corresponds to the first ferroelectric structure106, and the third remnant structure and the fourth remnant structure correspond to the first floating electrode structure108. Accordingly, the first remnant structure and the second remnant structure comprise a same material as the first ferroelectric structure106, and the third remnant structure and the fourth remnant structure comprise a same material as the first floating electrode structure108.

Also shown in the cross-sectional view800ofFIG.8, in some embodiments, a second plurality of remnant structures are disposed on opposite sides of the second pair of S/D structures702. The second plurality of remnant structures are a same material as corresponding structural features disposed laterally between the third S/D structure702aand the fourth S/D structure702b. For example, the second plurality of remnant structures comprise fifth, sixth, seventh, and eighth remnant structures. The fifth remnant structure and the seventh remnant structure are disposed on a first side of the third S/D structure702a, and the sixth remnant structure and the eighth remnant structure are disposed on a second side of the fourth S/D structure702bopposite the first side of the third S/D structure702a. The fifth remnant structure, the sixth remnant structure, and the second ferroelectric structure114are disposed in a third lateral plane; and the seventh remnant structure, the eighth remnant structure, and the second floating electrode structure112are disposed in a fourth lateral plane. As such, the fifth remnant structure and the sixth remnant structure corresponds to the second ferroelectric structure114, and the seventh remnant structure and the eighth remnant structure correspond to the second floating electrode structure112. Accordingly, the fifth remnant structure and the sixth remnant structure comprise a same material as the second ferroelectric structure114, and the seventh remnant structure and the eighth remnant structure comprise a same material as the second floating electrode structure112.

FIGS.9A-9Billustrate various views of some embodiments of the double gate MFMIS-FET structure ofFIG.8. More specifically,FIG.9Aillustrates a cross-sectional view900aof some embodiments of the double gate MFMIS-FET structure ofFIG.8, andFIG.9Billustrates a circuit diagram900bof an equivalent circuit of the double gate MFMIS-FET structure illustrated inFIG.9A.

As shown in the cross-sectional view900aofFIG.9A, a first selectively-conductive channel902aand a second selectively-conductive channel902bare disposed in the channel structure110. The first selectively-conductive channel902aextends laterally between the first S/D structure120aand the second S/D structure120b. The first selectively-conductive channel902ais configured to selectively provide an electrical path between the first S/D structure120aand the second S/D structure120b. The second selectively-conductive channel902bextends laterally between the third S/D structure702aand the fourth S/D structure702b. The second selectively-conductive channel902bis configured to selectively provide an electrical path between the third S/D structure702aand the fourth S/D structure702b.

As shown in the circuit diagram900bofFIG.9B, the equivalent circuit has a first source terminal902, a first drain terminal904, a first gate terminal906, a second source terminal908, a second drain terminal910, and a second gate terminal912. In some embodiments, the first source terminal902corresponds to, or is electrically coupled to, the first S/D structure120a. In some embodiments, the first drain terminal904corresponds to, or is electrically coupled to, the second S/D structure120b. In some embodiments, the first gate terminal906corresponds to, or is electrically coupled to, the lower gate electrode104. In some embodiments, the second source terminal908corresponds to, or is electrically coupled to, the third S/D structure702a. In some embodiments, the second drain terminal910corresponds to, or is electrically coupled to, the fourth S/D structure702b. In some embodiments, the second gate terminal912corresponds to, or is electrically coupled to, the upper gate electrode116. In some embodiments, the equivalent circuit illustrated in the circuit diagram900bofFIG.9Bmay be referred to as a separated FeFET circuit.

While the circuit diagram900bofFIG.9Billustrates the first selectively-conductive channel902aand the second selectively-conductive channel902bas electrically isolated from one another (e.g., a depletion region exists between the first and second selectively-conductive channel), it will be appreciated that, in some embodiments, the first selectively-conductive channel902aand the second selectively-conductive channel902bare a single selectively-conductive channel (see, e.g.,FIG.8). In embodiments in which the first selectively-conductive channel902aand the second selectively-conductive channel902bare a single selectively-conductive channel, the channel structure110may have a thickness that is less than about 60 nm (e.g., the channel structure110thickness is such that the single selectively-conductive channel meets a fully-depleted condition).

FIG.10illustrates a circuit diagram1000of an equivalent circuit of some other embodiments of the double gate MFMIS-FET structure ofFIG.8.

As shown in the circuit diagram1000ofFIG.10, the equivalent circuit has a source terminal1002, a drain terminal1004, and a gate terminal1006. In some embodiments, the source terminal1002is electrically coupled to, or corresponds to, both the first S/D structure120aand the third S/D structure702a. In some embodiments, the drain terminal1004is electrically coupled to, or corresponds to, both the second S/D structure120band the fourth S/D structure702b. In some embodiments, the gate terminal1006is electrically coupled to, or corresponds to, both the lower gate electrode104and the upper gate electrode116. In some embodiments, the equivalent circuit illustrated in the circuit diagram1000ofFIG.10may be referred to as a common gate control circuit (e.g., due to both the lower gate electrode104and the upper gate electrode116being electrically coupled together).

FIG.11illustrates a cross-sectional view1100of some other embodiments of the double gate MFMIS-FET structure ofFIG.8.

As shown in the cross-sectional view1100ofFIG.11, a sixth conductive structure1102, a seventh conductive structure1104, and an eighth conductive structure1106are disposed in the second dielectric layer118, the third dielectric layer802, and the fourth dielectric layer804. The sixth conductive structure1102, the seventh conductive structure1104, and the eighth conductive structure1106extend vertically through the second dielectric layer118, the third dielectric layer802, and the fourth dielectric layer804. It will be appreciated that, in some embodiments, the sixth conductive structure1102, the seventh conductive structure1104, and the eighth conductive structure1106may be disposed in the first dielectric layer102and/or the fifth dielectric layer806.

The sixth conductive structure1102is electrically coupled to both the second conductive structure604and the fourth conductive structure810(illustrated by dotted lines inFIG.11). As such, the fourth S/D structure702bis electrically coupled to the second S/D structure120bby, at least partially, the sixth conductive structure1102. The seventh conductive structure1104is electrically coupled to both the lower gate electrode104and the fifth conductive structure812(illustrated by dotted lines inFIG.11). As such, the lower gate electrode104is electrically coupled to upper gate electrode116by, at least partially, the seventh conductive structure1104. The eighth conductive structure1106is electrically coupled to both the first conductive structure602and the third conductive structure808(illustrated by dotted lines inFIG.11). As such, the third S/D structure702ais electrically coupled to the first S/D structure120aby, at least partially, the eighth conductive structure1106. It will be appreciated that the double gate MFMIS-FET structure ofFIG.11illustrates some structural embodiments of the double gate MFMIS-FET structure connected in a separated FeFET circuit configuration.

FIGS.12-28illustrate a series of cross-sectional views1200-2800of some embodiments of a method for forming an integrated chip (IC) comprising a double gate metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMIS-FET) structure.

AlthoughFIGS.12-28are described with reference to a method, it will be appreciated that the structures shown inFIGS.12-28are not limited to the method but rather may stand alone separate of the method.

As shown in cross-sectional view1200ofFIG.12, a lower gate electrode104is formed in a first dielectric layer102. In some embodiments, a process for forming the lower gate electrode104comprises: forming an opening in the first dielectric layer (e.g., via a photolithography/etching process); depositing a conductive layer in the opening and over an upper surface of the first dielectric layer102; and planarizing the conductive layer to localize the conductive layer to the opening. Other suitable processes are, however, amenable. The conductive layer may be deposited by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. It will be appreciated that, in some embodiments, the lower gate electrode104and the first dielectric layer102are as described in the aforementioned figures. It will also be appreciated that the lower gate electrode104is formed so that the lower gate electrode104is electrically coupled to an underlying conductive feature (e.g., a conductive feature of a copper interconnect structure).

Also shown in the cross-sectional view1200ofFIG.12, a first conductive structure602and a second conductive structure604are formed in the first dielectric layer102. In some embodiments, the first conductive structure602and the second conductive structure604are formed in a substantially similar manner as the lower gate electrode104. It will be appreciated that, in some embodiments, the first conductive structure602and the second conductive structure604are as described in the aforementioned figures. It will also be appreciated that the first conductive structure602and the second conductive structure604are formed so that the first conductive structure602and the second conductive structure604are electrically coupled to underlying conductive features, respectively (e.g., conductive features of the copper interconnect structure).

As shown in cross-sectional view1300ofFIG.13, a stress layer202is formed over the lower gate electrode104and the first dielectric layer102. In some embodiments, formation of the stress layer202is omitted. The stress layer202is configured to apply a tensile stress on a subsequently formed ferroelectric layer (e.g., to stabilize the orthorhombic crystal phase (o-phase) of the subsequently formed ferroelectric layer). In some embodiments, a process for forming the stress layer202comprises depositing the stress layer202on the lower gate electrode104and the first dielectric layer102. In further embodiments, the stress layer may be deposited on the first conductive structure602and/or the second conductive structure604. The stress layer202may be deposited by, for example, CVD, PVD, ALD, pulsed laser deposition (PLD), some other deposition process, or a combination of the foregoing. In some embodiments, the PLD process deposits quasi-monocrystalline metal oxides.

In some embodiments, the process for forming the stress layer202comprises performing an annealing process (e.g., furnace anneal, rapid thermal annealing (RTA), etc.) to enhance the crystallinity of the stress layer202. In some embodiments, the annealing process is an in-situ (e.g., occurring in the same processing chamber as the stress layer202is deposited) thermal annealing process. The in-situ thermal annealing may be, for example, performed between about 400° C. and about 700° C. In some embodiments, the in-situ thermal annealing may be, for example, performed for between about 0.5 minutes and about 10 minutes. It will be appreciated that, in some embodiments, the stress layer202is as described in the aforementioned figures.

As shown in cross-sectional view1400ofFIG.14, a first seed layer302is formed over the stress layer202. In some embodiments, formation of the first seed layer302is omitted. In some embodiments, a process for forming the first seed layer302comprises depositing the first seed layer302on the stress layer202. The first seed layer302may be deposited by, for example, CVD, PVD, ALD, some other deposition process, or a combination of the foregoing.

In some embodiments, the process for forming the first seed layer302comprises performing an annealing process (e.g., furnace anneal, rapid thermal annealing (RTA), etc.) on the first seed layer302. In some embodiments, the annealing process is an in-situ thermal annealing process. The in-situ thermal annealing may be, for example, performed between about 400° C. and about 700° C. In some embodiments, the in-situ thermal annealing may be, for example, performed for between about 0.5 minutes and about 10 minutes. It will be appreciated that, in some embodiments, the first seed layer302is as described in the aforementioned figures.

As shown in cross-sectional view1500ofFIG.15, a first ferroelectric layer1502is formed over the first seed layer302. In some embodiments, the stress layer202is configured to apply the tensile stress on the first ferroelectric layer1502. In some embodiments, a process for forming the first ferroelectric layer1502comprises depositing the first ferroelectric layer1502on the first seed layer302. The first ferroelectric layer1502may be deposited by, for example, ALD, PVD, CVD, some other deposition process, or a combination of the foregoing. The first ferroelectric layer1502may be or comprise, for example, hafnium zirconium oxide (HfZrO), scandium-doped aluminum nitride (AlScN), some other ferroelectric material, or a combination of the foregoing. In some embodiments, the first ferroelectric layer1502is hafnium zirconium oxide (HfZrO). The first ferroelectric layer1502may be hafnium zirconium oxide (HfZrO) and comprise oxygen vacancies. In some embodiments, the first ferroelectric layer1502is hafnium zirconium oxide (HfZrO) that is doped with aluminum (Al), silicon (Si), lanthanum (La), scandium (Sc), calcium (Ca), barium (Ba), gadolinium (Gd), yttrium (Y), strontium (Sr), or the like. In some embodiments, the first ferroelectric layer1502may be formed with a thickness between about 0.1 nm and about 100 nm.

As shown in cross-sectional view1600ofFIG.16, a second seed layer402is formed over the first ferroelectric layer1502. In some embodiments, formation of the second seed layer402is omitted. The second seed layer may be formed in a substantially similar manner as the first seed layer302. It will be appreciated that, in some embodiments, the second seed layer402is as described in the aforementioned figures.

As shown in cross-sectional view1700ofFIG.17, a first floating electrode layer1702is formed over the second seed layer402. In some embodiments, a process for forming the first floating electrode layer1702comprises depositing the first floating electrode layer1702on the second seed layer402. The first floating electrode layer1702may be deposited by, for example, ALD, PVD, CVD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. The first floating electrode layer1702may be or comprise, for example, titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), platinum (Pt), gold (Au), or the like. In some embodiments, the first floating electrode layer1702is formed with a thickness between about 1 nm and about 50 nm.

As shown in cross-sectional view1800ofFIG.18, a first insulating layer1802is formed over the first floating electrode layer1702. In some embodiments, a process for forming the first insulating layer1802comprises depositing or growing the first insulating layer1802on the first floating electrode layer1702. The first insulating layer1802may be deposited of grown by, for example, ALD, PVD, CVD, thermal oxidation, some other deposition process, or a combination of the foregoing. The first insulating layer1802may be or comprise, for example, hafnium oxide (HfO2), silicon doped hafnium oxide (HSO), hafnium zirconium oxide (HfZrO), silicon oxide (SiO2), aluminum oxide (Al2O3), yttrium oxide (Y2O3), zirconium oxide (ZrO2), magnesium oxide (MgO), or the like. In some embodiments, the first insulating layer1802is formed with a thickness between about 0.1 nm and about 10 nm. In some embodiments, the first insulating layer1802is silicon doped hafnium oxide (HSO) and comprises at least 10% silicon atoms. In some embodiments, the first insulating layer1802is a bi-layer structure comprising a silicon doped hafnium oxide (HSO) layer and a hafnium zirconium oxide (HfZrO) layer. In such embodiments, the hafnium zirconium oxide (HfZrO) layer may have a thickness of about 1 nm.

As shown in cross-sectional view1900ofFIG.19, a first pair of openings1902are formed in the structure illustrated in the cross-sectional view1800ofFIG.18. For example, a first opening1902aand a second opening1902bare formed in the structure illustrated in the cross-sectional view1800ofFIG.18. The first pair of openings1902are formed extending vertically through the first insulating layer1802, the first floating electrode layer1702, the first ferroelectric layer1502, the second seed layer402, the first seed layer302, and the stress layer202. The first opening1902aexposes the first conductive structure602. The second opening1902bexposes the second conductive structure604. The first opening1902ais formed on a first side of the lower gate electrode104. The second opening1902bis formed on a second side of the lower gate electrode104, which is opposite the first side of the lower gate electrode104. By forming the first pair of openings1902, a first ferroelectric structure106is formed over the lower gate electrode104, a first floating electrode structure108is formed over the first ferroelectric structure106, and a first insulating structure109is formed over the first floating electrode structure108. It will be appreciated that, in some embodiments, forming the first pair of openings1902also forms the first plurality of remnant structures (see, e.g.,FIG.8).

In some embodiments, a process for forming the first pair of opening1902comprises forming a patterned masking layer (not shown) (e.g., positive/negative photoresist, a hardmask, etc.) over the first insulating layer1802(see,FIG.18). The patterned masking layer may be formed by forming a masking layer (not shown) on the first insulating layer1802(e.g., via a spin-on process), exposing the masking layer to a pattern (e.g., via a lithography process, such as photolithography, extreme ultraviolet lithography, or the like), and developing the masking layer to form the patterned masking layer. Thereafter, with the patterned masking layer in place, an etching process is performed on the first insulating layer1802, the first floating electrode layer1702(see,FIG.17), the second seed layer402, the first ferroelectric layer1502(see,FIG.15), the first seed layer302, and the stress layer202according to the patterned masking layer.

The etching process removes unmasked portions of the first insulating layer1802, thereby forming the first insulating structure109between the first opening1902aand the second opening1902b. The etching process also removes unmasked portions of the first floating electrode layer1702, thereby forming the first floating electrode structure108between the first opening1902aand the second opening1902b. The etching process also removes unmasked portions of the first ferroelectric layer1502, thereby forming the first ferroelectric structure106between the first opening1902aand the second opening1902b. The etching process also removes unmasked portions of the second seed layer402, the first seed layer302, and the stress layer202. By removing the unmasked portions of the first insulating layer1802, the first floating electrode layer1702, the first ferroelectric layer1502, the second seed layer402, the first seed layer302, and the stress layer202, the first pair of openings1902are formed. In some embodiments, the etching process may be or comprise, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, some other etching process, or a combination of the foregoing. Subsequently, the patterned masking layer is stripped away. It will be appreciated that, in some embodiments, the first ferroelectric structure106, the first floating electrode structure108, and the first insulating structure109are as described in the aforementioned figures.

As shown in cross-sectional view2000ofFIG.20, a first plurality of spacer structures124are formed in the first pair of openings1902. For example, a first spacer structure124ais formed in the first opening1902aand over the first dielectric layer102, and a second spacer structure124bis formed in the second opening1902band over the first dielectric layer102. The first plurality of spacer structures124are formed lining sidewalls of the first pair of openings1902. In some embodiments, a process for forming the first plurality of spacer structures124comprises depositing a spacer layer (not shown) over the first insulating structure109and in (e.g., along the sidewalls) of the first pair of openings1902. The spacer layer may be deposited by, for example, CVD, PVD, ALD, some other deposition process, or a combination of the foregoing. Thereafter, horizontal portions of the spacer layer are etched away (e.g., via an anisotropic etching process), thereby leaving vertical portions of the spacer layer in place as the first plurality of spacer structures124. In some embodiments, the spacer layer may be or comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiON), some other dielectric material, or a combination of the foregoing. It will be appreciated that, in some embodiments, the first plurality of spacer structures124are as described in the aforementioned figures.

As shown in cross-sectional view2100ofFIG.21, a first pair of S/D structures120are formed in the first pair of openings1902(see,FIG.20) and between inner sidewalls of the first plurality of spacer structures124. For example, a first S/D structure120ais formed in the first opening1902aand between inner sidewalls of the first spacer structure124a, and a second S/D structure120bis formed in the second opening1902band between inner sidewalls of the second spacer structure124b. The first S/D structure120ais formed electrically coupled to the first conductive structure602. The second S/D structure120bis formed electrically coupled to the second conductive structure604. In some embodiments, the first pair of S/D structures120may be formed with a thickness between about 50 nm and about 1000 nm. For example, the first S/D structure120amay be formed with a thickness between about 50 nm and about 1000 nm.

In some embodiments, a process for forming the first pair of S/D structures120comprises depositing a conductive layer (not shown) over the first insulating structure109and in the first pair of openings1902(e.g., the remaining portions of the first pair of openings1902not occupied by the first plurality of spacer structures124). The conductive layer may be deposited by, for example, ALD, PVD, CVD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. Thereafter, a planarization process (e.g., a chemical mechanical polishing (CMP) process, an etch back process, etc.) is performed on the conductive layer, thereby forming the first pair of S/D structures120. The conductive layer may be or comprise, for example, titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), platinum (Pt), gold (Au), or the like. It will be appreciated that, in some embodiments, the first pair of S/D structures120are as described in the aforementioned figures.

As shown in cross-sectional view2200ofFIG.22, a channel structure110is formed over the first insulating structure109, the first plurality of spacer structures124, and the first pair of S/D structures120. A selectively-conductive channel122is disposed in the channel structure110. In some embodiments, the channel structure110comprises a plurality of first channel layers502, a plurality of second channel layers504, and a third channel layer506. More specifically, the channel structure110may comprise a first stack508of first and second channel layers and a second stack510of first and second channel layers. The first stack508of first and second channel layers comprises a first set of the first channel layers502and a first set of the second channel layers504, which are stacked vertically in alternating order. The second stack510of first and second channel layers comprises a second set of the first channel layers502and a second set of the second channel layers504, which are stacked vertically in alternating order. The third channel layer506is disposed vertically between the first stack508of first and second channel layers and the second stack510of first and second channel layers.

The first channel layers502comprise a mixture of a first material and a second material. The second channel layers504comprise a third material different than the first and second materials. The third channel layer506comprises a mixture of the first, second, and third materials. In some embodiments, the first material comprises gallium oxide (GaO), hafnium oxide (HfO), zirconium oxide (ZrO), titanium oxide (TiO), aluminum oxide (AlO), tantalum oxide (TaO), strontium oxide (SrO), barium oxide (BaO), scandium oxide (ScO), magnesium oxide (MgO), lanthanum oxide (LaO), gadolinium oxide (GdO), or the like. In some embodiments, the second material comprises indium oxide (InO), tin oxide (SnO), arsenic oxide (AsO), zinc oxide (ZnO), or the like. In some embodiments, the third material comprises zinc oxide (ZnO). Thus, for example, in some embodiments, the first material comprises gallium oxide (GaO); the second material comprises indium oxide (InO); and the third material comprises zinc oxide (ZnO), such that the first channel layers502comprise a mixture of gallium oxide (GaO) and indium oxide (InO), the second channel layers504comprise zinc oxide (ZnO), and the third channel layer506is indium gallium zinc oxide (IGZO). In further embodiments, the third channel layer506is amorphous indium gallium zinc oxide (a-IGZO).

In some embodiments, a process for forming the channel structure110comprises depositing the plurality of first channel layers502, the plurality of second channel layers504, and the third channel layer506over the first insulating structure109, the first plurality of spacer structures124, and the first pair of S/D structures120. The plurality of first channel layers502, the plurality of second channel layers504, and the third channel layer506may be deposited by, for example, ALD, CVD, PVD, some other deposition process, or a combination of the foregoing.

In some embodiments, the plurality of first channel layers502, the plurality of second channel layers504, and the third channel layer506are deposited in a processing chamber by using solid precursors. In some embodiments, to form each of the plurality of first channel layers502, a first solid precursor (e.g., an solid indium precursor) and a second solid precursor (e.g., a solid gallium precursor) are activated at the same time (e.g., co-pulsed). An inert gas is used to activate the first and second solid precursors and to generate a first precursor vapor that flows into the processing chamber, thereby forming a first processing layer (e.g., an indium-gallium layer) on the workpiece (e.g., the structure illustrated inFIG.21). Thereafter, an oxygen vapor is introduced into the processing chamber that reacts with the first processing layer, thereby forming one of the first channel layers502(e.g., an indium oxide/gallium oxide layer)

In some embodiments, to form each of the plurality of second channel layers504, a third solid precursor (e.g., a solid zinc precursor) is activated (e.g., pulsed). An inert gas is used to activate the third solid precursor and to generate a second precursor vapor that flows into the processing chamber, thereby forming a second processing layer (e.g., a zinc layer) on the workpiece (e.g., the structure illustrated inFIG.21plus a first one of the first channel layers502). Thereafter, an oxygen vapor is introduced into the processing chamber that reacts with the second processing layer, thereby forming one of the second channel layers504(e.g., a zinc oxide layer).

In some embodiments, to form the third channel layer506, the first solid precursor, the second solid precursor, and the third solid precursor are activated at the same time (e.g., tri-pulsed). An inert gas is used to activate the first, second, and third solid precursors and to generate a third precursor vapor that flows into the processing chamber, thereby forming a third processing layer (e.g., an indium-gallium-zinc layer) on the workpiece (e.g., the structure illustrated inFIG.21plus the first stack508of first and second channel layers). Thereafter, an oxygen vapor is introduced into the processing chamber that reacts with the third processing layer, thereby forming the third channel layer506(e.g., a-IGZO layer). The above steps are repeated in a predefined manner, thereby forming the third channel layer506, the first stack508of first and second channel layers, and the second stack510of first and second channel layers, as shown in the cross-sectional view2200ofFIG.22. It will be appreciated that, in some embodiments, the channel structure110, the selectively-conductive channel122, the plurality of first channel layers502, plurality of second channel layers504, the third channel layer506, the first stack508of first and second channel layers, and the second stack510of first and second channel layers are as described in the aforementioned figures.

As shown in cross-sectional view2300ofFIG.23, a second insulating layer2302is formed over the channel structure110. The second insulating layer2302may be or comprise, for example, hafnium oxide (HfO2), silicon doped hafnium oxide (HSO), hafnium zirconium oxide (HfZrO), silicon oxide (SiO2), aluminum oxide (Al2O3), yttrium oxide (Y2O3), zirconium oxide (ZrO2), magnesium oxide (MgO), or the like. In some embodiments, the second insulating layer2302is formed with a thickness between about 0.1 nm and about 10 nm. In some embodiments, the second insulating layer2302is silicon doped hafnium oxide (HSO) and comprises at least 10% silicon atoms. In some embodiments, the second insulating layer2302is a bi-layer structure comprising a silicon doped hafnium oxide (HSO) layer and a hafnium zirconium oxide (HfZrO) layer. In such embodiments, the hafnium zirconium oxide (HfZrO) layer may have a thickness of about 1 nm. In some embodiments, a process for forming the second insulating layer2302comprises depositing the second insulating layer2302on the channel structure110. The second insulating layer2302may be deposited of grown by, for example, ALD, PVD, CVD, thermal oxidation, some other deposition process, or a combination of the foregoing.

Also shown in the cross-sectional view2300ofFIG.23, a second floating electrode layer2304is formed over the second insulating layer2302. In some embodiments, a process for forming the second floating electrode layer2304comprises depositing the second floating electrode layer2304on the second insulating layer2302. The second floating electrode layer2304may be deposited by, for example, ALD, PVD, CVD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. The second floating electrode layer2304may be or comprise, for example, titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), platinum (Pt), gold (Au), or the like. In some embodiments, the second floating electrode layer2304is formed with a thickness between about 1 nm and about 50 nm.

Also shown in the cross-sectional view2300ofFIG.23, a third seed layer404is formed over the second floating electrode layer2304. In some embodiments, formation of the third seed layer404is omitted. The third seed layer404may be formed in a substantially similar manner as the first seed layer302. It will be appreciated that, in some embodiments, the third seed layer404is as described in the aforementioned figures.

Also shown in the cross-sectional view2300ofFIG.23, a second ferroelectric layer2306is formed over the third seed layer404. In some embodiments, a process for forming the second ferroelectric layer2306comprises depositing the second ferroelectric layer2306on the third seed layer404. The second ferroelectric layer2306may be deposited by, for example, ALD, PVD, CVD, some other deposition process, or a combination of the foregoing. The second ferroelectric layer2306may be or comprise, for example, hafnium zirconium oxide (HfZrO), scandium-doped aluminum nitride (AlScN), some other ferroelectric material, or a combination of the foregoing. In some embodiments, the second ferroelectric layer2306is hafnium zirconium oxide (HfZrO). The second ferroelectric layer2306may be hafnium zirconium oxide (HfZrO) and comprise oxygen vacancies. In some embodiments, the second ferroelectric layer2306is hafnium zirconium oxide (HfZrO) that is doped with aluminum (Al), silicon (Si), lanthanum (La), scandium (Sc), calcium (Ca), barium (Ba), gadolinium (Gd), yttrium (Y), strontium (Sr), or the like. In some embodiments, the second ferroelectric layer2306may be formed with a thickness between about 0.1 nm and about 100 nm.

Also shown in the cross-sectional view2300ofFIG.23, a fourth seed layer406is formed over the second ferroelectric layer2306. In some embodiments, formation of the fourth seed layer406is omitted. The fourth seed layer406may be formed in a substantially similar manner as the first seed layer302. It will be appreciated that, in some embodiments, the fourth seed layer406is as described in the aforementioned figures.

Also shown in the cross-sectional view2300ofFIG.23, a second dielectric layer118is formed over the fourth seed layer406. In some embodiments, a process for forming the second dielectric layer118comprises depositing the second dielectric layer118on the fourth seed layer406. The second dielectric layer118may be deposited by, for example, CVD, PVD, ALD, a spin-on process, some other deposition process, or a combination of the foregoing.

As shown in cross-sectional view2400, a second pair of openings2402are formed in the structure illustrated in the cross-sectional view2300ofFIG.23. For example, a third opening2402aand a fourth opening2402bare formed in the structure illustrated in the cross-sectional view2300ofFIG.23. The second pair of openings2402are formed over the channel structure110. The second pair of openings2402are formed extending vertically through the second insulating layer2302, the second floating electrode layer2304, the second ferroelectric layer2306, the third seed layer404, the fourth seed layer406, and the second dielectric layer118. The third opening2402aexposes a first portion of the channel structure110. The fourth opening2402bexposes a second portion of the channel structure110. By forming the second pair of openings2402, a second insulating structure111is formed over the channel structure110, a second floating electrode structure112is formed over the second insulating structure111, and a second ferroelectric structure114is formed over the second floating electrode structure112. It will be appreciated that, in some embodiments, forming the second pair of openings2402also forms the second plurality of remnant structures (see, e.g.,FIG.8).

In some embodiments, a process for forming the second pair of opening2402comprises forming a patterned masking layer (not shown) (e.g., positive/negative photoresist, a hardmask, etc.) over the second dielectric layer118. The patterned masking layer may be formed by forming a masking layer (not shown) on second dielectric layer118(e.g., via a spin-on process), exposing the masking layer to a pattern (e.g., via a lithography process, such as photolithography, extreme ultraviolet lithography, or the like), and developing the masking layer to form the patterned masking layer. Thereafter, with the patterned masking layer in place, an etching process is performed on the second dielectric layer118, the fourth seed layer406, the second ferroelectric layer2306, the third seed layer404, the second floating electrode layer2304, and the second insulating layer2302(see,FIG.23) according to the patterned masking layer.

The etching process removes unmasked portions of the second insulating layer2302, thereby forming the second insulating structure111between the third opening2402aand the fourth opening2402b. The etching process also removes unmasked portions of the second floating electrode layer2304, thereby forming the second floating electrode structure112between the third opening2402aand the fourth opening2402b. The etching process also removes unmasked portions of the second ferroelectric layer2306, thereby forming the second ferroelectric structure114between the third opening2402aand the fourth opening2402b. The etching process also removes unmasked portions of the third seed layer404, the fourth seed layer406, and the second dielectric layer118. By removing the unmasked portions of the second insulating layer2302, the second floating electrode layer2304, the second ferroelectric layer2306, the third seed layer404, the fourth seed layer406, and the second dielectric layer118, the second pair of openings2402are formed. In some embodiments, the etching process may be or comprise, for example, a wet etching process, a dry etching process, a RIE process, some other etching process, or a combination of the foregoing. Subsequently, the patterned masking layer is stripped away. It will be appreciated that, in some embodiments, the second ferroelectric structure114, the second floating electrode structure112, and the second insulating structure111are as described in the aforementioned figures.

As shown in cross-sectional view2500ofFIG.25, a second plurality of spacer structures704are formed in the second pair of openings2402. For example, a third spacer structure704ais formed in the third opening2402aand over the channel structure110, and a fourth spacer structure704bis formed in the fourth opening2402band over the channel structure110. The second plurality of spacer structures704are formed lining sidewalls of the second pair of openings2402. In some embodiments, a process for forming the second plurality of spacer structure704comprises depositing a spacer layer (not shown) over the second dielectric layer118and in (e.g., along the sidewalls) of the second pair of openings2402. The spacer layer may be deposited by, for example, CVD, PVD, ALD, some other deposition process, or a combination of the foregoing. Thereafter, horizontal portions of the spacer layer are etched away (e.g., via an anisotropic etching process), thereby leaving vertical portions of the spacer layer in place as the second plurality of spacer structures704. In some embodiments, the spacer layer may be or comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiON), some other dielectric material, or a combination of the foregoing. It will be appreciated that, in some embodiments, the second plurality of spacer structures704are as described in the aforementioned figures.

As shown in cross-sectional view2600ofFIG.26, a second pair of S/D structures702are formed in the second pair of openings2402(see,FIG.25) and between inner sidewalls of the second plurality of spacer structures704. For example, a third S/D structure702ais formed in the third opening2402aand between inner sidewalls of the third spacer structure704a, and a fourth S/D structure702bis formed in the fourth opening2402band between inner sidewalls of the fourth spacer structure704b. In some embodiments, the second pair of S/D structures702may be formed with a thickness between about 50 nm and about 1000 nm. For example, the third S/D structure702amay be formed with a thickness between about 50 nm and about 1000 nm.

In some embodiments, a process for forming the second pair of S/D structures702comprises depositing a conductive layer (not shown) over the second dielectric layer118and in the second pair of openings2402(e.g., the remaining portions of the second pair of openings2402not occupied by the second plurality of spacer structures704). The conductive layer may be deposited by, for example, ALD, PVD, CVD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. Thereafter, a planarization process (e.g., a CMP process, an etch back process, etc.) is performed on the conductive layer, thereby forming the second pair of S/D structures702. The conductive layer may be or comprise, for example, titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), platinum (Pt), gold (Au), or the like. It will be appreciated that, in some embodiments, the second pair of S/D structures702are as described in the aforementioned figures.

As shown in cross-sectional view2700ofFIG.27, an upper gate electrode116is formed in the second dielectric layer118and over the second ferroelectric structure114. In some embodiments, a process for forming the upper gate electrode116comprises forming a patterned masking layer (not shown) (e.g., positive/negative photoresist, a hardmask, etc.) over the second dielectric layer118, the second plurality of spacer structures704, and the second pair of S/D structures702. The patterned masking layer may be formed by forming a masking layer (not shown) on second dielectric layer118, the second plurality of spacer structures704, and the second pair of S/D structures702; exposing the masking layer to a pattern (e.g., via a lithography process, such as photolithography, extreme ultraviolet lithography, or the like); and developing the masking layer to form the patterned masking layer. Thereafter, with the patterned masking layer in place, an etching process is performed on the second dielectric layer118, thereby forming an opening in the second dielectric layer118and laterally between the third S/D structure702aand the fourth S/D structure702b.

Thereafter, a conductive layer is deposited in the opening and over the patterned masking layer. The conductive layer may be deposited by, for example, ALD, PVD, CVD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. Thereafter, a planarization process (e.g., a CMP process, an etch back process, etc.) is performed on the conductive layer and the patterned masking layer, thereby forming the upper gate electrode116and removing the patterned masking layer. The conductive layer may be or comprise, for example, platinum (Pt), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), gold (Au), iron (Fe), nickel (Ni), beryllium (Be), chromium (Cr), cobalt (Co), antimony (Sb), iridium (Jr), molybendum (Mo), osmium (Os), thorium (Th), vanadium (V), some other metal or metal nitride, or a combination of the foregoing. It will be appreciated that, in some embodiments, the upper gate electrode116is as described in the aforementioned figures.

As shown in the cross-sectional view2800ofFIG.28, a fifth dielectric layer806is formed over the upper gate electrode116, the second dielectric layer118, the second plurality of spacer structures704, and the second pair of S/D structures702. In some embodiments, a process for forming the fifth dielectric layer806comprises depositing the fifth dielectric layer806on the upper gate electrode116, the second dielectric layer118, the second plurality of spacer structures704, and the second pair of S/D structures702. The fifth dielectric layer806may be deposited by, for example, CVD, PVD, ALD, a spin-on process, some other deposition process, or a combination of the foregoing.

Also shown in the cross-sectional view2800ofFIG.28, a third conductive structure808, a fourth conductive structure810, and a fifth conductive structure812are formed in the fifth dielectric layer806. The third conductive structure808is formed electrically coupled to the third S/D structure702a. The fourth conductive structure810is formed electrically coupled to the fourth S/D structure702b. The fifth conductive structure812is formed electrically coupled to the upper gate electrode116.

In some embodiments, a process for forming the third conductive structure808, the fourth conductive structure810, and the fifth conductive structure812comprises: forming a plurality of openings in the fifth dielectric layer806(e.g., via a photolithography/etching process); depositing a conductive layer in the plurality of openings and over an upper surface of the fifth dielectric layer806; and planarizing the conductive layer to localize the conductive layer to the plurality of openings. Other suitable processes are, however, amenable. The conductive layer may be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. It will be appreciated that, in some embodiments, the fifth dielectric layer806, the third conductive structure808, the fourth conductive structure810, and the fifth conductive structure812are as described in the aforementioned figures. Although not shown, it will also be appreciated that additional conductive structure (e.g., metal wires, metal vias, bond pads, etc.) may be formed over and electrically coupled to the third conductive structure808, the fourth conductive structure810, and the fifth conductive structure812.

FIG.29illustrates a flowchart2900of some embodiments of a method for forming an integrated chip (IC) comprising a double gate metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMIS-FET) structure. While the flowchart2900ofFIG.29is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

At act2902, a lower gate electrode is formed in a first dielectric layer.FIG.12illustrates a cross-sectional view1200of some embodiments corresponding to act2902.

At act2904, a first ferroelectric layer is formed over the lower gate electrode.FIGS.13-15illustrate a series of cross-sectional views1300-1500of some embodiments corresponding to act2904.

At act2906, a first floating electrode layer is formed over the first ferroelectric layer.FIGS.16-17illustrate a series of cross-sectional views1600-1700of some embodiments corresponding to act2906.

At act2908, a first insulating layer is formed over the first floating electrode layer.FIG.18illustrates a cross-sectional view1800of some embodiments corresponding to act2908.

At act2910, a first pair of source/drain (S/D) structures are formed over the first dielectric layer and on opposite sides of the lower gate electrode.FIGS.19-21illustrate a series of cross-sectional views1900-2100of some embodiments corresponding to act2910.

At act2912, a channel structure is formed over the first pair of S/D structures and over the first insulating layer.FIG.22illustrates a cross-sectional view2200of some embodiments corresponding to act2912.

At act2914, a second insulating layer is formed over the channel structure.FIG.23illustrates a cross-sectional view2300of some embodiments corresponding to act2914.

At act2916, a second floating electrode layer is formed over the second insulating layer.FIG.23illustrates a cross-sectional view2300of some embodiments corresponding to act2916.

At act2918, a second ferroelectric layer is formed over the second floating electrode layer.FIG.23illustrates a cross-sectional view2300of some embodiments corresponding to act2918.

At act2920, a second dielectric layer is formed over the second ferroelectric layer.FIG.23illustrates a cross-sectional view2300of some embodiments corresponding to act2920.

At act2922, a second pair of S/D structures are formed over the channel structure.FIGS.24-26illustrate a series of cross-sectional views2400-2600of some embodiments corresponding to act2922.

At act2924, an upper gate electrode is formed over the second ferroelectric layer and laterally between the S/D structures of the second pair of S/D structures.FIG.27illustrates a cross-sectional view2700of some embodiments corresponding to act2924.

At act2926, a third dielectric layer is formed over the second dielectric layer, the upper gate electrode, and the second pair of S/D structures.FIG.28illustrates a cross-sectional view2800of some embodiments corresponding to act2926.

In some embodiments, the present application provides an integrated chip (IC). The IC comprises a lower gate electrode disposed in a dielectric structure. A first ferroelectric structure overlies the lower gate electrode. A first floating electrode structure overlies the first ferroelectric structure. A channel structure overlies the first floating electrode structure. A second floating electrode structure overlies the channel structure. A second ferroelectric structure overlies the second floating electrode structure. An upper gate electrode overlies the second ferroelectric structure.

In some embodiments, the present application provides an integrated chip (IC). The IC comprises a lower gate electrode disposed in a dielectric structure. A first ferroelectric structure overlies the lower gate electrode. A first floating electrode structure overlies the first ferroelectric structure. A first source/drain (S/D) structure is disposed on a first side of the first ferroelectric structure. A second S/D structure is disposed on a second side of the first ferroelectric structure opposite the first side of the first ferroelectric structure. A channel structure overlies the first floating electrode structure, the first S/D structure, and the second S/D structure, wherein the first S/D structure and the second S/D structure are electrically coupled to the channel structure. A second floating electrode structure overlies the channel structure. A second ferroelectric structure overlies the second floating electrode structure. An upper gate electrode overlies the second ferroelectric structure. A third S/D structure overlies the channel structure and is disposed on a first side of the second ferroelectric structure, wherein the third S/D structure is electrically coupled to the channel structure. A fourth S/D structure overlies the channel structure and is disposed on a second side of the second ferroelectric structure opposite the first side of the second ferroelectric structure, wherein the fourth S/D structure is electrically coupled to the channel structure.

In some embodiments, the present application provides a method. The method comprises forming a first ferroelectric layer over a lower gate electrode structure. A first floating electrode layer is formed over the first ferroelectric layer. A channel structure is formed over the first floating electrode layer. A second floating electrode layer is formed over the channel structure. A second ferroelectric layer is formed over the second floating electrode layer. A first opening is formed that extends vertically through both the second ferroelectric layer and the second floating electrode layer, wherein the first opening exposes a first portion of the channel structure. A second opening is formed that extends vertically through both the second ferroelectric layer and the second floating electrode layer, wherein the second opening exposes a second portion of the channel structure that is laterally spaced from the first portion of the channel structure. A first source/drain (S/D) structure is formed in the first opening. A second S/D structure is formed in the second opening. An upper gate electrode is formed over the channel structure and laterally between the first S/D structure and the second S/D structure.