Semiconductor package assembly and method of manufacturing the same

A semiconductor package assembly includes a circuit board, a heat dissipating element and a semiconductor device. The circuit board includes a conductive pattern. The heat dissipating element is located on the circuit board, where the heat dissipating element is connected to the conductive pattern. The semiconductor device is located on the circuit board and next to the heat dissipating element, where the semiconductor device is thermally connected to the heat dissipating element through the conductive pattern.

BACKGROUND

Semiconductor devices and integrated circuits (ICs) are typically manufactured on a single semiconductor wafer. The dies of the wafer may be processed and packaged with other semiconductor devices or dies at the wafer level, and various technologies have been developed for the wafer level packaging. Semiconductor processing for fabrications of the semiconductor devices and ICs continues to evolve towards increasing device-density, higher numbers of active devices (mainly transistors) of ever decreasing device dimensions. As electronic products are continuously miniaturized, heat dissipation of the packaged semiconductor devices and ICs have become an important issue for packaging technology.

DETAILED DESCRIPTION

In addition, terms, such as “first”, “second”, “third”, “fourth” and the like, may be used herein for ease of description to describe similar or different element(s) or feature(s) as illustrated in the figures, and may be used interchangeably depending on the order of the presence or the contexts of the description.

In accordance with some embodiments, a semiconductor package assembly includes a circuit board, a heat dissipating element and a semiconductor device. The heat dissipating element is located on and is connected to a conductive pattern of the circuit board. The semiconductor device is located on the circuit board and next to the heat dissipating element. The semiconductor device is thermally connected to the heat dissipating element through the conductive pattern. Accordingly, device temperature may be controlled with square cooling pattern to improve cooling efficiency.

FIG.1,FIG.3,FIG.5,FIG.7andFIG.9are schematic cross-sectional views showing a method of manufacturing a semiconductor package assembly SA1in accordance with some embodiments of the disclosure.FIG.2,FIG.4,FIG.6,FIG.8andFIG.10are schematic plane views illustrating a relative position of components included in the semiconductor package assembly SA1depicted inFIG.1,FIG.3,FIG.5,FIG.7andFIG.9, respectively.FIG.11throughFIG.14are respectively schematic top views illustrating a relative position of components included in a semiconductor package assembly in accordance with other embodiments of the disclosure.FIG.18is a flow chart illustrating a part of a method of manufacturing a semiconductor package assembly in accordance with some embodiments of the disclosure.FIG.1,FIG.3,FIG.5andFIG.9are the schematic cross-sectional views taken alone a cross-section line A-A′ depicted inFIG.2,FIG.4,FIG.6andFIG.10, whileFIG.7is the schematic cross-sectional view taken alone a cross-section line B-B′ depicted inFIG.8. InFIG.2,FIG.4,FIG.6andFIG.10, certain structural features shown in the respective cross-section views ofFIG.1,FIG.3,FIG.5andFIG.9are omitted for easy illustration. In the disclosure, it should be appreciated that the illustration of components throughout all figures is schematic and is not in scale.

For example, inFIG.1throughFIG.10, one semiconductor package (or device) is shown to represent one or plural semiconductor packages (or devices), and one semiconductor package assembly is shown to represent one or plural semiconductor package assemblies obtained following the manufacturing method; the disclosure is not limited thereto. In other embodiments, multiple semiconductor packages (or devices) are shown to represent plural semiconductor packages (or devices), and multiple semiconductor package assemblies are shown to represent plural semiconductor package assemblies obtained following the manufacturing method. It is to be noted that the process steps described herein cover a portion of the manufacturing processes used to fabricate a semiconductor package assembly. The embodiments are intended to provide further explanations, but are not used to limit the scope of the disclosure.

Referring toFIG.1andFIG.2together, in some embodiments, a circuit board100is provided, where the circuit board100includes a circuit carrier110, a conductive pattern120over the circuit carrier110and a plurality of conductive contacts130over the circuit structure100. The circuit carrier110may have a surface110tand a surface110bopposite to the surface110talong a direction Z. For example, the conductive pattern120and the conductive contacts130are next to each other and disposed on the surface of110tof the circuit carrier100, as shown inFIG.1. In some embodiments, the conductive pattern120is electrically connected to and thermally coupled to the circuit carrier110. On the other hand, the conductive contacts130are separated from one another, where the conductive contacts130are electrically connected to and thermally coupled to the circuit carrier110and are electrically isolated from the conductive pattern120. For the circuit board100, the conductive contacts130are at least thermally coupled to the conductive pattern120through the circuit carrier110, in some embodiments. For example, the conductive pattern120and the conductive contacts130are accessibly revealed from the circuit carrier110for connecting (e.g. at least in a manner of electrical coupling and/or thermal coupling) to a component disposing thereon.

The formation of the circuit board100may be formed by, but not limited to, the following steps: providing the circuit carrier110(in accordance with step S10ofFIG.18), where the circuit carrier110includes a substrate (or referred to as a circuit structure), and the structure includes a plurality of first contact pads (not shown) and a plurality of second contact pads (not shown) located at opposite sides of the substrate and an internal circuitry (not shown) embedded inside the substrate for electrically connecting the first contact pads and the second contact pads; and forming the conductive pattern120over the circuit carrier110(in accordance with step S20ofFIG.18), where the conductive pattern120is electrically connected to and thermally coupled to the circuit carrier110via a direct contact between the conductive pattern120and the first contact pads or between the conductive pattern120and the second contact pads. During forming the conductive pattern120, the conductive contacts130may be formed simultaneously. Alternatively, the conductive contacts130may be formed prior to the formation of the conductive pattern120or after the formation of the conductive pattern120; the disclosure is not limited thereto. The circuit board100may be an organic circuit structure, a printed circuit board (PCB), a system board, or the like.

The substrate may be made of a dielectric material; for example, a polymer such as polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), a nitride such as silicon nitride, an oxide such as silicon oxide, a silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof or the like. The first contact pads may be distributed on a top surface (e.g.,110t) of the substrate, and the second contact pads may be distributed on a bottom surface (e.g.,110b) of the substrate, or vice versa. For example, the top surface is opposite to the bottom surface along the direction Z as shown inFIG.1. In this case, the internal circuitry embedded inside the substrate is electrically connecting the first contact pads and the second contact pads, thereby constituting the circuit carrier110.

In some embodiments, the first contact pads and the second contact pads are respectively distributed over two opposite sides of the substrate and are accessibly exposed for electrically connecting with later-formed elements/features (e.g., the conductive pattern120, the conductive contacts130, a signal source, a power source, the like, or combinations thereof). In some embodiments, the first contact pads and the second contact pads may independently include copper pads, aluminum pads, or the like. The materials of the first contact pads may be the same as the materials of the second contact pads. Alternatively, the materials of the first contact pads may be different from the materials of the second contact pads. Throughout the description, the term “copper” is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing minor amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum or zirconium, etc.

In some embodiments, the internal circuitry includes a plurality of metallization layers and a plurality of vias, where the metallization layers and the vias are alternately arranged along the direction Z and are embedded in the substrate, and two immediately adjacent metallization layers are connected to each other through at least one via interposed therebetween; thereby providing a routing function for the circuit carrier110. That is, the first contact pads are electrically coupled to the second contact pads through the internal circuitry (including the metallization layers and the vias), for example. On the other hand, in some other embodiments, besides above electrical connection between the first contact pads and the second contact pads, one of the first contact pads is electrically coupled to another first contact pad through the internal circuitry, and/or one of the second contact pads is electrically coupled to another second contact pad through the internal circuitry. The materials of the internal circuitry may include conductive materials formed by electroplating or deposition, such as aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof, which may be patterned using a photolithography and etching processes. In some embodiments, the metallization layers included in the internal circuitry are patterned copper layers, and the vias included in the internal circuitry are copper vias. The materials of the metallization layers and the vias may be the same, the disclosure is not limited thereto. Alternatively, the material of the metallization layers may be different from the material of vias.

However, the disclosure is not limited thereto; alternatively, the internal circuitry may include through-insulator vias embedded to the substrate for connecting the first contact pads and the second contact pads. In such case, the through-insulator vias included in the internal circuitry are copper vias.

As illustrated inFIG.1andFIG.2, in some embodiments, the conductive pattern120is formed on the surface110tof the circuit carrier110. In some embodiments, the conductive pattern120is electrically connected to and thermally coupled to the circuit carrier110through a connection between the conductive pattern120and the circuit carrier110(e.g., connecting the conductive pattern120to the first contact pads or the second contact pads). The conductive pattern120may be formed, but not limited to, by, but not limited to, conformally forming a blanket layer of a conductive material over the circuit carrier110and patterning the conductive material layer into a pre-determined pattern on the circuit carrier110to form the conductive pattern120. For example, the conductive pattern120is in a form of cross-shape with an opening OP1located at the center thereof. The opening OP1may correspond to a positioning location of a later-disposed component, such as a socket200(described later inFIG.3andFIG.4) or a semiconductor package400(described later inFIG.7andFIG.8). In some embodiments, the opening OP1is in a quadrilateral form such as a rectangle or a square, as shown inFIG.2. Alternatively, the opening OP1may be in a form of a circular shape or an elliptical shape.

The conductive pattern120may include a plurality of sub-patterns120a,120b,120cand120das shown inFIG.2. For example, the sub-patterns120athrough120dare formed in a same layer, where each of the sub-patterns120athrough120dis in a form of a quadrilateral, and any two adjacent sub-patterns120a,120b,120cand120dare connected to each other via a shared portion122(including122a,122b,122cand122d), as shown inFIG.2. That is, the sub-patterns120aand120bare connected through a shared portion122A, the sub-patterns120band120care connected through a shared portion122B, the sub-patterns120cand120dare connected through a shared portion122C, and the sub-patterns120dand120aare connected through a shared portion122D. The sub-patterns120a,120b,120cand120dmay be different in the plane view projecting in the direction Z, in part or all. For example, as shown inFIG.2, the sizes and shapes of the sub-patterns120aand120care substantially identical (such as square shapes), the sizes and shapes of the sub-patterns120band120dare substantially identical (such as rectangular shapes), and the sizes and shapes of the sub-patterns120aand120care different from the sizes and shapes of the sub-patterns120band120d. Alternatively, the sizes and shapes of the sub-patterns120a,120b,120cand120din the plane view may be the same, such as rectangular shapes inFIG.11.

However, the disclosure is not limited thereto. In other embodiments, the conductive pattern120′ is formed in a frame shape (FIG.12andFIG.13), where the frame shape includes a square annulus or a rectangle annulus having the opening OP1′ therein. For example, the opening OP1′ is in a quadrilateral form such as a rectangle or a square, as shown inFIG.12andFIG.13. Alternatively, the opening OP1′ may be in a form of a circular shape or an elliptical shape. In further alternative embodiments, as shown inFIG.14, a conductive pattern120″ may include a plurality of the sub-patterns120a′,120b′120c′ and120d′, where the sub-patterns120a′,120b′120c′ and120d′ are separated from one another and are arranged in a concentric manner with an opening OP1″ located at the center of and surrounded by the sub-patterns120a′,120b′120c′ and120d′.

The conductive material of the conductive pattern120may include a material that is electrically conductive and thermally conductive. In some embodiments, the conductive material of the conductive pattern120includes a metal or metal alloy, formed by electroplating or deposition. The conductive material may include copper, aluminum, titanium, steel, nickel, tungsten, and/or alloys thereof, which may be patterned using a photolithography and etching process. For example, the conductive pattern120includes a suitable thermally conductive material having a thermal conductivity more than 200 W/(m·K), such as copper or aluminum. Owing to the conductive pattern120, the heat generated from or transmitted to the circuit carrier110can be easily dissipating out from the circuit carrier110via the conductive pattern120. In some embodiments, a thickness T120of the conductive pattern120is approximately ranging from 17.5 μm to 105 μm.

Continued onFIG.1, in some embodiments, the conductive contacts130are formed on the surface110tof the circuit carrier110. In some embodiments, the conductive contacts130are electrically connected to and thermally coupled to the circuit carrier110through a connection between the conductive contacts130and the circuit carrier110(e.g., connecting the conductive contacts130to the first contact pads or the second contact pads). The conductive contacts130are separated apart from each other and from the conductive pattern120, where the conductive contacts130are located inside the opening OP1of the conductive pattern120, as shown inFIG.2, for example. In other words, the conductive contacts130are surrounded by the conductive pattern120, laterally. The conductive contacts130may be arranged in the form of a matrix, such as the N×N array or N×M array (N, M>0, N may or may not be equal to M) along a X-Y plane. The direction X and the direction Y are different form each other and the direction Z, where the direction Z is a stacking direction of the circuit carrier110and the conductive pattern120. For example, the direction X is perpendicular to the direction Y, and the direction X and the direction Y independently perpendicular to the direction Z.

In some embodiments, the conductive contacts130may be made of conductive materials formed by electroplating or deposition, such as aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof, which may be patterned using a photolithography and etching process. In some embodiments, the conductive contacts130may be copper conductive patterns or aluminum conductive patterns. In some embodiments, a thickness T130of the conductive contacts130is approximately ranging from 17.5 μm to 105 μm. The number of the conductive contacts130shown inFIG.1andFIG.2is for illustrative proposes only, and the disclosure is not limited thereto. The number of the conductive contacts130may be selected and designated based on the demand and design layout.

In one embodiment, the material of the conductive pattern120is the same as the materials of the conductive contacts130. In an alternative embodiment, the material of the conductive pattern120is different from the materials of the conductive contacts130. The disclosure is not specifically limited thereto. In some embodiments, the first contact pads or the second contact pads in contact with the conductive pattern120are electrically floating to the first contact pads or the second contact pads in contact with the conductive contacts130.

Referring toFIG.3andFIG.4together, in some embodiments, a socket200is disposed over the circuit carrier110, in accordance with step S30ofFIG.18. As illustrated inFIG.3andFIG.4, for example, the socket200stands on the conductive pattern120, where the socket200is partially overlapped with the conductive pattern120in the vertical projection on the circuit board100along the direction Z. The socket200may be mounted onto the circuit board100through a holding device (not shown) including a plurality of blots and a plurality of fasteners. In some embodiments, the bolts penetrate through the socket200(e.g. the flange portion212) and the circuit board100at corners of the socket200, and the fasteners are respectively threaded onto the bolts and tightened to clamp the socket200and the circuit board100. The fasteners may be, e.g., nuts that thread to the bolts. For example, as shown inFIG.3, the flange portion212of the base210of the socket200directly stands on a surface of the conductive pattern120.

For example, the socket200includes a base210and a plurality of conductive connectors220penetrating therethrough, as shown inFIG.3. In some embodiments, the base210is electrically isolated from the conductive connectors220, and is further electrically isolated from the conductive pattern120and the conductive contacts130. In some embodiments, the base210includes a flange portion212and a central portion214, where the flange portion212is at a periphery of the central portion214. For example, as shown inFIG.3, a cross-section of the base210is in a H-shape. On the other hand, in the top view ofFIG.4, the base210may be in a rectangular shape. Alternatively, in the top view, the base210may be in a square-shape, a circle-shape, an ellipse-shape, or any suitable polygonal shape. In some embodiments, the material of the base210include a dielectric material capable of providing a specific stiffness that ensuring the physical and mechanical strength of the sockets200. The stiffness (which may be quantified by its Yong's modulus) can be in the range of about 10 GPa to about 30 GPa.

The flange portion212and the central portion214may together confine at least two recesses (e.g. R1and R2) inside the socket200. For example, as shown inFIG.3, a recess R1is confined by an inner surface212iof the flange portion212and a surface214tof the central portion214, and a recess R2is confined by the inner surface212iof the flange portion212and a surface214bof the central portion214. For example, the surface214tis opposite to the surface214balong the direction Z, where the surface214tis facing away from the circuit board100while the surface214bis facing towards the circuit board100. In some embodiments, the recess R1is configured to be an accommodating space for the semiconductor package400(described later inFIG.7andFIG.8). In some embodiments, the conductive contacts130are in the recess R2, where the conductive contacts130are enclosed by the socket200, the conductive pattern120and the circuit carrier110. In other words, the recess R2is spatially communicated to the opening OP1, for example.

The central portion214may include a plurality of openings OP2. For example, as shown inFIG.3, the openings OP2penetrate through the central portion214in the direction Z, where the conductive connectors220are respectively inserted into the openings OP2and fixed to the base210. For example, the conductive connectors220includes a plurality of conductive connectors222and a plurality of conductive connectors224. In some embodiments, the conductive connectors222are in contact with the conductive pattern120, where the conductive connectors222are electrically connected to and thermally coupled to the conductive pattern120. In other words, positioning locations of the conductive connectors222are within a positioning location of the conductive pattern120in a vertical projection on the circuit board100along the direction Z. For example, multiple conductive connectors222are connected to (e.g., in contact with) each of sub-patterns120a,120b,120cand120d. The conductive connectors222each may include a body portion222cand two end portions222a,222brespectively connecting to two opposite sides of the body portion222c. For example, as shown inFIG.3, the conductive connectors222are connected to the conductive pattern120through the end portions222b. The conductive pattern120may be electrically connected to and thermally coupled to the semiconductor package400through the end portions222aof the conductive connectors222.

On the other hand, the conductive connectors224are respectively in contact with the conductive contacts130, where the conductive connectors224are electrically connected to and thermally coupled to the conductive contacts130. For example, each conductive connector224is connected to a respective one of the conductive contacts130. In other words, positioning locations of the conductive connectors224are within positioning locations of the conductive contacts130in a vertical projection on the circuit board100along the direction Z. The conductive connectors224each may include a body portion224cand two end portions224a,224brespectively connecting to two opposite sides of the body portion224c. For example, as shown inFIG.3, the conductive connectors224are respectively connected to the conductive contacts130through the end portions224b. The conductive contacts130may be electrically connected to and thermally coupled to the semiconductor package400through the end portions224aof the conductive connectors224.

In some embodiments, the conductive connectors222and the conductive connectors224are pogo pins to establish proper physical contacts between the end portions (e.g.,222a/222b,224a/224b) and an overlying or underlying components (e.g., the semiconductor package400or the circuit board100). Alternatively, the conductive connectors222and/or224may be any suitable conductive connectors which are capable of establishing the proper physical contacts as mentioned. Only two conductive connectors222and eight conductive connectors224are shown inFIG.3for illustrative purposes, the disclosure is not limited thereto. The numbers of the conductive connectors220(including222and224) is selected and designated based on the demand and the design requirement.

Referring toFIG.5andFIG.6together, in some embodiments, a heat dissipating element is mounted over the circuit carrier110, in accordance with step S40ofFIG.18. The heat dissipating element may include one or more than one heat dissipating element300. For example, as shown inFIG.6, the heat dissipating element includes a plurality of heat dissipating elements300, such as a heat dissipating element300a, a heat dissipating element300b, a heat dissipating element300cand a heat dissipating element300d. The heat dissipating elements300are disposed on the circuit board100and surround the socket200, in some embodiments. For example, a thickness T300of the heat dissipating elements300is greater than a thickness T200of the socket200. As shown inFIG.6, only four heat dissipating elements300(e.g.,300athrough300d) are presented for illustrative purposes, however, it should be noted that the number of the heat dissipating elements300may be one or more than one, the disclosure is not limited thereto.

The heat dissipating elements300may be bonded to the conductive pattern120by placing the heat dissipating elements300on the conductive pattern120to establish a proper physical contact therebetween, thereby thermally coupling the heat dissipating elements300and the conductive pattern120. In some embodiments, the heat dissipating elements300are removably installed (or bonded) on the conductive pattern120for thermally coupling the heat dissipating elements300and the conductive pattern120to achieve a thermal bonding therebetween. For example, the heat dissipating element300ais bonded to and thermally coupled to the sub-pattern120a, the heat dissipating element300bis bonded to and thermally coupled to the sub-pattern120b, the heat dissipating element300cis bonded to and thermally coupled to the sub-pattern120c, and the heat dissipating element300dis bonded to and thermally coupled to the sub-pattern120d, as shown inFIG.6. In some embodiments, positioning locations of the heat dissipating elements300are within a positioning location of the conductive pattern120in a vertical projection on the circuit board100along the direction Z. For example, through the conductive pattern120, the heat dissipating elements300and the circuit carrier110are spacing apart and physically separated from one another. In alternative embodiments, the heat dissipating elements300may be further electrically connected to the conductive pattern120.

As shown inFIG.5, for example, the conductive pattern120is located under the socket200and the heat dissipating elements300and further extended from the socket200to the heat dissipating elements300, where a heat dissipating path from the socket200(e.g., the conductive connectors220) to the heat dissipating elements300through the circuit board100(e.g., the conductive pattern120) is established. In the disclosure, the heat dissipating elements300may be referred to as a cooling module or a cooling system. The heat dissipating elements300, for example, each include a metal plate with fins, a metal plate with a conduit therein for conducting a coolant (such as water, oil, or cool air), or the like.

In some embodiments, each of the heat dissipating elements300are distant from the socket200by a gap G, as shown inFIG.5andFIG.6. For example, the gap G is greater than or substantially equal to about 1 mm. The heat dissipating elements300may be different in the plane view projecting in the direction Z, in part or all. For example, as shown inFIG.6, the sizes and shapes of the heat dissipating elements300aand300care substantially identical (e.g., rectangular/square shapes), the sizes and shapes of the heat dissipating elements300band300dare substantially identical (e.g., strip-shapes), and the sizes and shapes of the heat dissipating elements300aand300care different from the sizes and shapes of the heat dissipating elements300band300d. Alternatively, the sizes and shapes of the heat dissipating elements300a,300b,300cand300din the plane view may be substantially the same (rectangular/square shape as depicted inFIG.11and strip-shape as depicted inFIG.12).

However, the disclosure is not limited thereto. In other embodiments, the heat dissipating element includes only one heat dissipating element300′ having a frame shape (FIG.13), where the frame shape includes a square annulus or a rectangle annulus having the opening at the center thereof, and the socket200is disposed inside the opening on the circuit board100and is separated from the heat dissipating element300′ by the gap G. In addition, the opening may be a rectangular shape, a square-shape, a circular shape or an elliptical shape. In addition, there may be one or more than on heat dissipating element300being bonded to one conductive pattern120, depending on the design requirement.

Referring toFIG.7andFIG.8together, in some embodiments, the semiconductor package400is provided, in accordance with step S50ofFIG.18. For example, the semiconductor package400includes a plurality of semiconductor dies410, a plurality of input/output (I/O) interface dies420, an insulating encapsulation430, a redistribution circuit structure440and a plurality of conductive elements450, as shown inFIG.7. In some embodiments, the conductive elements450are the interfaces for external connections to the semiconductor package400. That is, the conductive elements450serve as the conductive terminals of the semiconductor package400to electrical connect with the external devices/apparatus (e.g., the socket200(via the conductive connectors220)) for transmitting (outputting and/or inputting) electric signals, power signals, or ground signals. In alternative embodiments, a semiconductor device (now shown) is optionally bonded to the semiconductor package400in a manner similar to the conductive elements450. The semiconductor device may be an integrated passive element (IPD) or a surface mount device (SMD), the disclosure is not limited thereto.

In some embodiments, if considering a top view on the X-Y plane along the direction Z, the semiconductor package400is in a form of chip-size being greater than or substantially equal to 1000 mm2. Alternatively, the semiconductor package400may be in a wafer or panel form. In other words, the semiconductor package400is processed in the form of a reconstructed wafer/panel. In alternative embodiments, if considering a top view on the X-Y plane along the direction Z, the semiconductor package400is in a form of wafer-size having a diameter of about 4 inches or more. In further alternative embodiments, the semiconductor package400is in a form of wafer-size having a diameter of about 6 inches or more. In yet further alternative embodiments, the semiconductor package400is in a form of wafer-size having a diameter of about 8 inches or more. Or alternatively, the semiconductor package400is in a form of wafer-size having a diameter of about 12 inches or more. In some embodiments, a size of the conductive pattern120is greater than or substantially equal to a size of the semiconductor package400in the vertical projection on the circuit board100along the direction Z (e.g. on the X-Y plane).

The semiconductor dies410and the I/O interface dies420may be arranged aside to each other along the direction X and/or the direction Y. In some embodiments, the semiconductor dies410are arranged in the form of a matrix, such as a N′×N′ array or a N′×M′ array (N′, M′>0, N′ may or may not be equal to M′), while the I/O interface dies420are arranged to surround the semiconductor dies410(arranged into the array/matrix) for providing additional input/output circuitries thereto, and thus more I/O counts are provided to the semiconductor dies410. The matrix of the I/O interface dies420may be a N″×N″ array or a N″×M″ array (N″, M″>0, N″ may or may not be equal to M″). That is, in such embodiments, the I/O interface dies420are arranged into a matrix surrounding the perimeter of the matrix of the semiconductor dies410.

However, the disclosure is not limited thereto, in an alternative embodiment, the semiconductor dies410and the I/O interface dies420are arranged in the form of a matrix, such as the Na×Na array or Na×Ma array (Na, Ma>0, Na may or may not be equal to Ma). With such embodiments, the semiconductor dies410and the I/O interface dies420are arranged into the matrix in an alternation manner. In a further alternative embodiment, the semiconductor dies410are arranged in the form of a first matrix and the I/O interface dies420are arranged in the form of a second matrix, where the first and second matrices are Nb×Nb array or Nb×Mb array (Nb, Mb>0, Nb may or may not be equal to Mb), and the first and second matrices are positioned next to each other along the direction X or the direction Y.

In some embodiments, the semiconductor dies410have a plurality of conductive vias412, where the conductive vias412serve as conductive terminals of the semiconductor dies410for electrical connection to other devices/elements (e.g., the redistribution circuit structure440. The semiconductor dies410each described herein may be referred to as a semiconductor chip or an integrated circuit (IC). For example, the semiconductor dies410, independently, are a logic chip, such as a central processing unit (CPU), graphics processing unit (GPU), system-on-chip (SoC), system-on-integrated-circuit (SoIC), microcontroller, or the like. However, the disclosure is not limited thereto; in alternative embodiments, the semiconductor dies410, independently, are a digital chip, analog chip or mixed signal chip, such as an application-specific integrated circuit (ASIC) chip, a sensor chips, a wireless and radio frequency (RF) chip, a baseband (BB) chip, a memory chip (such as high bandwidth memory (HBM) dies) or a voltage regulator chip. In further alternative embodiments, the semiconductor dies410, independently, are referred to as a chip or an IC of combination-type, such as a WiFi chip simultaneously including both of a RF chip and a digital chip. In some embodiments, a type of a first group of the semiconductor dies410are different from a type of a second group of the semiconductor dies410. In other words, the semiconductor dies410may include semiconductor chips or ICs of different types and/or the same type; the disclosure is not limited thereto. For example, the first group of the semiconductor dies410includes logic dies, while the second group of the semiconductor dies410includes memory dies.

In some embodiments, the I/O interface dies420, independently, have a plurality of conductive vias422, where the conductive vias422serve as conductive terminals of the I/O interface dies420for electrical connection to other devices/elements (e.g., the redistribution circuit structure440. As shown inFIG.7, only two semiconductor dies410and two I/O interface dies420are presented for illustrative purposes, however, it should be noted that the number of the semiconductor dies410and the number of the I/O interface dies420may be one or more than one, the disclosure is not limited thereto.

In some embodiments, the semiconductor dies410and the I/O interface dies420are encapsulated in the insulating encapsulation430. For example, the insulating encapsulation430laterally wraps around the semiconductor dies410and the I/O interface dies420, where the conductive vias412of the semiconductor dies410and the conductive vias422of the I/O interface dies420are accessibly exposed by the insulating encapsulation430. As shown inFIG.7, illustrated bottom surfaces of the conductive vias412and the conductive vias422are substantially leveled with an illustrated bottom surface of the insulating encapsulation430. That is, in some embodiments, the illustrated bottom surfaces of the conductive vias412, the surfaces of the conductive vias422and the bottom surface of the insulating encapsulation430are substantially coplanar to each other for achieving a high degree of coplanarity to facilitate the formation of a later-formed element (e.g., the redistribution circuit structure440). It is appreciated that the illustrated bottom surfaces of the conductive vias412and the conductive vias422depicted inFIG.7are equivalent to active sides of the semiconductor dies410and the I/O interface dies420, respectively.

In some embodiments, a sidewall of each conductive via412of the semiconductor dies410is partially covered (e.g. in physical contact with) by the insulating encapsulation430. In some embodiments, a sidewall of each conductive via422of the I/O interface dies420is partially covered (e.g. in physical contact with) by the insulating encapsulation430. However, the disclosure is not limited thereto; alternatively, the sidewall of each conductive via412and the sidewall of each conductive via422are free from the insulating encapsulation430. In further alternative embodiments, the sidewall of each conductive via412of the semiconductor dies410is partially covered (e.g. in physical contact with) by the insulating encapsulation430, while the sidewall of each conductive via422of the I/O interface dies420is not covered by the insulating encapsulation430. In yet further alternative embodiments, the sidewall of each conductive via412of the semiconductor dies410is not covered by the insulating encapsulation430, while the sidewall of each conductive via422of the I/O interface dies420is partially covered (e.g. in physical contact with) by the insulating encapsulation430.

On the other hand, as shown inFIG.7, illustrated top surfaces (e.g., non-active sides) of the semiconductor dies410and the I/O interface dies420may be substantially leveled with an illustrated top surface of the insulating encapsulation430. For example, the illustrated top surfaces of the semiconductor dies410and the I/O interface dies420are substantially coplanar to the illustrated top surface of the insulating encapsulation430.

The insulating encapsulation430may include an acceptable insulating encapsulation material. The insulating encapsulation430, for example, includes polymers (such as epoxy resins, phenolic resins, silicon-containing resins, or other suitable resins), dielectric materials, or other suitable materials. The insulating encapsulation430may be a molding compound formed by a molding process. The insulating encapsulation430may further include inorganic filler or inorganic compound (e.g. silica, clay, and so on) which can be added therein to optimize coefficient of thermal expansion (CTE) of the insulating encapsulation430. The disclosure is not limited thereto.

In some embodiments, the redistribution circuit structure440is located over the semiconductor dies410, the I/O interface dies420and the insulating encapsulation430. As shown inFIG.7, the redistribution circuit structure440, for example, includes a fine-featured portion440A and a coarse-featured portion440B, and is electrically connected to the semiconductor dies410and the I/O interface dies420through connecting to the conductive vias412of the semiconductor dies410and the conductive vias422of the I/O interface dies420exposed by the insulating encapsulation430. In some embodiments, the fine-featured portion440A is located between the coarse-featured portion440B and the semiconductor dies410and between the coarse-featured portion440B and the I/O interface dies420. In some embodiments, the fine-featured portion440A of the redistribution circuit structure440is formed over and electrically coupled to the semiconductor dies410and the I/O interface dies420, and the coarse-featured portion440B is electrically coupled to the semiconductor dies410and the I/O interface dies420through the fine-featured portion440A. For example, as shown inFIG.7, the fine-featured portion440A is capable of providing local electrical communications between the semiconductor dies410, between the I/O interface dies420and between the semiconductor dies410and the I/O interface dies420, while the coarse-featured portion440B is capable of providing global electrical communications between external devices/apparatus electrically connected to the conductive elements450and the semiconductor dies410and/or the I/O interface dies420.

For example, the fine-featured portion440A includes a dielectric structure442A and a metallization pattern444A located in the dielectric structure442A, and the coarse-featured portion440B includes a dielectric structure442B and a metallization pattern444B located in the dielectric structure442B. The metallization patterns444A and the metallization patterns444B independently may include one or more patterned conductive layers (which being individually referred to as redistribution layers), while the dielectric structures442A and the dielectric structures442B independently may include one or more dielectric layers arranged alternatively with the patterned conductive layers. For example, the one or more patterned conductive layers, which are electrically connected to each other, includes line portions (also referred to as conductive lines or traces) extending on the X-Y plane and via portions (also referred to as conductive vias) extending on the direction Z and electrically connected to the line portions (together referred to as an internal routing circuit) for providing routing functionality. In addition, the one or more patterned conductive layers further include plane portions extending on the X-Y plane and other via portions extending on the direction Z electrically connected to the plane portions (together referred to as a ground plate or ground plane) for being electrically grounded. In such case, the plane portions are electrically isolated from the rest of the metallization pattern444A and the rest of the metallization pattern444B. For example, one line portion and one plane portion located in the same patterned conductive layer in either the fine-featured portion440A or the coarse-featured portion440B are electrically isolated from one another through a slit, where the slit is filled with the dielectric material made for the dielectric structure442A or442B. The number of the dielectric layers included in one dielectric structure442A or442B and the number of the patterned conductive layers included in one metallization pattern444A or444B may not be limited to the drawings of the disclosure, and may be selected and designated based on the demand and design requirements.

The fine-featured portion440A and the coarse-featured portion440B of the redistribution circuit structure440include metallization patterns and dielectric structures of differing sizes, as shown inFIG.7, for example. In certain embodiments, the patterned conductive layers included in the metallization pattern444A are formed from a same conductive material, and are formed to a same thickness (e.g., a first thickness) and a same line width (e.g., a first line width), and the patterned conductive layers included in the metallization pattern444B are formed from a same conductive material, and are formed to a same thickness (e.g., a second thickness) and a same line width (e.g., a second line width). Likewise, in some embodiments, the dielectric layers included in the dielectric structure442A are formed from a same dielectric material and are formed to a same thickness, and the dielectric layers included in the dielectric structure442B are formed from a same dielectric material and are formed to a same thickness. In some embodiments, along the direction Z, the patterned conductive layers included in the metallization pattern444A have the first thickness that is smaller than the second thickness of the patterned conductive layers included in the metallization pattern444B. On the other hand, on the top view (e.g., on the X-Y plane), the patterned conductive layers included in the metallization pattern444A have the first line width that is smaller than the second line width of the patterned conductive layers included in the metallization pattern444B.

The material of the dielectric structures442A,442B may include polyimide, epoxy resin, acrylic resin, phenol resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer-based dielectric material, and may be formed by deposition, lamination or spin-coating. The material of the metallization patterns444A,444B may include aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof, and may be formed by electroplating or deposition. The disclosure is not limited thereto. The dielectric structures442A,442B and the metallization patterns444A,444B independently may also be patterned by a photolithography and etching process.

The material of the dielectric structure442A is, for example, as the same as the material of the dielectric structure442B. For another example, the materials of the dielectric structures442A and442B are different from one another. The material of the metallization pattern444A is, for example, as the same as the material of the metallization pattern444B. For another example, the materials of the metallization patterns444A and444B are different from one another. The disclosure is not limited thereto. In alternative embodiments, the redistribution circuit structure440may include metallization patterns of same size and dielectric structures of same size.

In some embodiments, the conductive elements450are attached to the redistribution circuit structure440for electrically coupling therebetween, as shown inFIG.7. The conductive elements450may include a plurality of conductive elements452and a plurality of conductive elements454surrounded by the conductive elements452. For example, as shown inFIG.7andFIG.8, the semiconductor package400has an illustrated top surface S1and an illustrated bottom surface S2opposite to the illustrated top surface S1in the direction Z, where the illustrated bottom surface S2includes an active region AR and a periphery region PR surrounding the active region AR. As shown inFIG.8, the conductive elements452may be disposed within the periphery region PR of the semiconductor package400, and the conductive elements454may be disposed within the active region AR of the semiconductor package400. In some embodiments, the conductive elements452within the periphery region PR are electrically connected to the ground plate included in the redistribution circuit structure440, and the conductive elements454within the active region AR are electrically connected to the internal routing circuit include in the redistribution circuit structure440. For example, through the redistribution circuit structure440, some of the conductive elements452are electrically connected to the semiconductor dies410, and some of the conductive elements452are electrically connected to the I/O interface dies420. On the other hand, for example, through the redistribution circuit structure440, some of the conductive elements454are electrically connected to the semiconductor dies410, and some of the conductive elements454are electrically connected to the I/O interface dies420. Besides, some of the conductive elements454may be electrically floated or grounded, the disclosure is not limited thereto. The number of the conductive elements450(e.g.452/454) is not limited to the drawings of the disclosure, and may be selected and designed based on the demand. In some embodiments, a ratio of the number of the conductive elements452to the number of the conductive elements454is from about 5:5 to about 3:7.

The conductive elements450may be disposed on the redistribution circuit structure440by ball placement process or reflow process. The conductive elements450are, for example, solder balls or ball grid array (BGA) balls or bumps. Alternatively, the conductive elements450may include micro-bumps, metal pillars, electroless nickel-electroless palladium-immersion gold (ENEPIG) formed bumps, controlled collapse chip connection (C4) bumps, or the like; and may be formed by plating. The conductive elements450may be solder free. In the alternative embodiments of which the semiconductor device(s) is included, the semiconductor device may be disposed on the redistribution circuit structure440by flip-chip bonding technology or surface device mounting technology.

The conductive elements452may be periodically arranged into a first array within the periphery region PR, and the conductive elements454may be periodically arranged in to a second array within the active region AR, where the first array me be different from the second array. For example, the positions of the conductive elements452and454are respectively corresponding to the positions of the conductive connectors222and224, as shown inFIG.8.

In some alternative embodiments (not shown), before disposing/forming the conductive elements450on the redistribution circuit structure440, a plurality of under-ball metallurgy (UBM) patterns are optionally formed on and electrically coupled to the redistribution circuit structure440, where the strength of connection between the conductive elements450and the redistribution circuit structure440is enhanced. The conductive elements450may be placed on the UBM patterns through ball placement process. That is, the conductive elements450may be electrically coupled to the redistribution circuit structure440through the UBM patterns. In some embodiments, the UBM patterns are made of a metal layer including a single layer or a metallization layer including a composite layer with a plurality of sub-layers formed of different materials. In some embodiments, the UBM patterns include copper, nickel, molybdenum, titanium, tungsten, titanium nitride, titanium tungsten, combinations thereof, or the like. For example, the UBM patterns include a titanium layer and a copper layer over the titanium layer. The UBM patterns may be formed using, for example, electroplating, sputtering, physical vapor deposition (PVD), or the like. However, the UBM patterns may be omitted from the redistribution circuit structure440, the disclosure is not limited thereto.

Referring toFIG.9andFIG.10together, in some embodiments, the semiconductor package400is placed onto the socket200to connect the semiconductor package400and the socket200, in accordance with step S60ofFIG.18. In some embodiments, the semiconductor package400is mounted into the recess R1, where the conductive elements450of the semiconductor package400are in contact with (e.g. a removably bonding, such as Ohmic contact) the conductive connector220of the socket200. For example, as shown inFIG.9, the conductive elements452are in physical contact with the end portions222aof the conductive connectors222, and the conductive elements454are in physical contact with the end portions224aof the conductive connectors224, thereby the semiconductor package400is electrically connected to and thermally coupled to the socket200. That is, through the socket200, the semiconductor package400is electrically connected to and thermally coupled to both of the heat dissipating elements300and the circuit board100. Up to here, the semiconductor package assembly SA1is manufactured.

One or more than one semiconductor package assembly SA1may act as a high performance computing (HPC) system. If considering multiple semiconductor package assemblies SA1together acting as the high performance computing (HPC) system, the semiconductor package assemblies SA1may each be used as an electronics card inserting an end having a plurality of electrical connectors (e.g. the first or second contact pads located on the circuit board100and being free from the conductive pattern120and the conductive contacts130) into a slot of a rack, with these electrical connectors contacting the electrical connectors of the rack. In other words, the semiconductor package assemblies SA1are electrically connected and electrically communicated to one another through the rack.

In some embodiments, through the socket200, the ground plate included in the redistribution circuit structure440of the semiconductor package400is thermally coupled to the heat dissipating elements300. Owing to such configuration, the heat generated from the semiconductor package400is dissipated to the heat dissipating elements300through the socket200and the conductive pattern120of the circuit board100, thereby the heat dissipation of the semiconductor package400is greatly enhanced, the reliability of the semiconductor package400is improved. In other words, a better cooling efficiency of the semiconductor package assembly SA1is achieved. On the other hand, in some embodiments, through the socket200, the internal routing circuit included in the redistribution circuit structure440of the semiconductor package400is electrically coupled to the circuit board100. Owing to such configuration, the electric signals, power signals or ground signals are transmitted to the semiconductor package400from the circuit board100or transmitted from the semiconductor package400to the circuit board100through the sockets200and the conductive contacts130of the circuit board100. The performance of the semiconductor package assembly SA1is ensured.

As illustrated inFIG.9, for example, in the semiconductor package assembly SA1, the illustrated top surface S1of the semiconductor package400after mounting to the socket200is substantially coplanar to a top surface210tof the socket200. However, the disclosure is not limited thereto; alternatively, the illustrated top surface S1of the semiconductor package400may be lower or above the top surface210tof the socket200. On the other hand, the illustrated top surface S1of the semiconductor package400is lower than top surfaces300tof the heat dissipating elements300, in some embodiments. That is, for example, as shown inFIG.9, a distance between the illustrated top surface S1of the semiconductor package400and the surface110tof the circuit carrier110is less than a distance between the top surfaces300tof the heat dissipating elements300and the surface110tof the circuit carrier110. Owing to the height-level difference between the heat dissipating elements300and the semiconductor package400, cooling capability is increase, thereby improving the heat dissipating efficiency.

In the disclosure, the semiconductor dies of a semiconductor package may be arranged into a stacking configuration (e.g., an arrangement of multiple tiers each having semiconductor dies) in a semiconductor package assembly of the disclosure. For example, the semiconductor package400may be substituted by a semiconductor package700as depicted inFIG.15.FIG.15is a schematic cross-sectional views showing the semiconductor package assembly SA2in accordance with alternative embodiments of the disclosure. The elements similar to or substantially the same as the elements described above will use the same reference numbers, and certain details or descriptions of the same elements (e.g. the formations and materials) and the relationship thereof (e.g. the relative positioning configuration and connection) will not be repeated herein.

As illustrated inFIG.15, the semiconductor package700is mounted into the recess R1of the socket200to connect the semiconductor package700and the socket200so as to form the semiconductor package assembly SA2. In some embodiments, the semiconductor package700includes a plurality of semiconductor dies710, a plurality of input/output (I/O) interface dies720, an insulating encapsulation730, a redistribution circuit structure740(including a fine-featured portion740A (with742A and744A) and a coarse-featured portion740B (with742B and744B)), a plurality of conductive elements750(including752and754), a plurality of semiconductor dies760and a plurality of conductive pillars770, as shown inFIG.15. The formation and material of each of the semiconductor dies710, the I/O interface dies720, the insulating encapsulation730, the redistribution circuit structure740and the conductive elements750are similar to or substantially identical to the formation and material of each of the semiconductor dies410, the I/O interface dies420, the insulating encapsulation430, the redistribution circuit structure440and the conductive elements450as described inFIG.7andFIG.8, and thus are omitted herein for brevity. In some embodiments, the formation, material and type of each of the semiconductor dies760may be, independently, similar or identical to the semiconductor dies410or the I/O interface dies420as described inFIG.7andFIG.8, and thus are omitted herein.

As shown inFIG.15, the semiconductor dies710and the I/O interface dies720are sandwiched between the semiconductors dies760and the redistribution circuit structure740, where the semiconductor dies710, the I/O interface dies720and the semiconductors dies760are encapsulated in the insulating encapsulation730, for example. In other words, the semiconductors dies760are stacked on the semiconductor dies710and the I/O interface dies720, or vice versa. There are only two tiers of the semiconductor dies as shown inFIG.15, however, the disclosure is not limited thereto. The number of the tiers of the semiconductor dies may be one, two or more than two based on the demand and design layout. As shown inFIG.15, surfaces S760bof the semiconductor dies760are substantially coplanar to and leveled with the surface S730bof the insulating encapsulation730, for example. In other words, the surfaces S760bof the semiconductor dies760are exposed by the insulating encapsulation730.

In some embodiments, the semiconductor package700has an illustrated top surface S3and an illustrated bottom surface S4opposite to the illustrated top surface S3in the direction Z, where the illustrated bottom surface S4includes an active region AR and a periphery region PR surrounding the active region AR. As illustrated inFIG.15, for example, in the semiconductor package assembly SA2, the illustrated top surface S3of the semiconductor package700after mounting to the socket200is substantially coplanar to a top surface210tof the socket200. However, the disclosure is not limited thereto; alternatively, the illustrated top surface S3of the semiconductor package700may be lower or above the top surface210tof the socket200. On the other hand, the illustrated top surface S3of the semiconductor package700is lower than top surfaces300tof the heat dissipating elements300, in some embodiments. That is, for example, as shown inFIG.15, a distance between the illustrated top surface S3of the semiconductor package700and the surface110tof the circuit carrier110is less than a distance between the top surfaces300tof the heat dissipating elements300and the surface110tof the circuit carrier110. Owing to the height-level difference between the heat dissipating elements300and the semiconductor package700, cooling capability is increase, thereby improving the heat dissipating efficiency.

In some embodiments, the redistribution circuit structure740is electrically connected to conductive vias712of the semiconductor dies710and conductive vias722of the I/O interface dies720, and is further electrically connected to conductive vias762of the semiconductor dies760through conductive pillars770. The conductive pillars770may be made of a metal material such as copper, copper alloys, or the like. As shown inFIG.15, the conductive pillars770are located next to the semiconductor dies710and the I/O interface dies720and are encapsulated in the insulating encapsulation730, for example. In some embodiments, the semiconductor dies710, the I/O interface dies720and the semiconductors dies760are electrically connected to and thermally coupled to the redistribution circuit structure740. For example, the conductive elements752of the conductive elements750within the periphery region PR are electrically connected to the ground plate included in the redistribution circuit structure740, and the conductive elements754of the conductive elements750within the active region AR are electrically connected to the internal routing circuit include in the redistribution circuit structure740.

In some embodiments, the conductive elements750of the semiconductor package700are in contact with (e.g. a removably bonding, such as Ohmic contact) the conductive connector220of the socket200. For example, as shown inFIG.15, the conductive elements752are in physical contact with the end portions222aof the conductive connectors222, and the conductive elements754are in physical contact with the end portions224aof the conductive connectors224, thereby the semiconductor package700is electrically connected to and thermally coupled to the socket200. That is, through the socket200, the semiconductor package700is electrically connected to and thermally coupled to both of the heat dissipating elements300and the circuit board100.

In such case, the conductive connectors222of the socket200are electrically connected and thermally coupled to the conductive pattern120underlying thereto and are further electrically connected and thermally coupled to the conductive elements752of the conductive elements750overlying thereto. Owing to such configuration (e.g. due to thermal conduction), a heat dissipating path from the socket200(e.g., the conductive connectors220) to the heat dissipating elements300through the circuit board100(e.g., the conductive pattern120) is established, where the heat generated from the semiconductor package700is dissipated to the heat dissipating elements300through the socket200and the conductive pattern120of the circuit board100, thereby the heat dissipation of the semiconductor package700is greatly enhanced, the reliability of the semiconductor package700is improved. In other words, a better cooling efficiency of the semiconductor package assembly SA2is achieved. On the other hand, the conductive connectors224of the socket200are electrically connected to and thermally coupled to the conductive contacts130underlying thereto and are further electrically connected to and thermally coupled to the conductive elements754of the conductive elements750overlying thereto. Owing to such configuration (e.g. due to electrical conduction), the electric signals, power signals or ground signals are transmitted to the semiconductor package700from the circuit board100or transmitted from the semiconductor package700to the circuit board100through the sockets200and the conductive contacts130of the circuit board100. The performance of the semiconductor package assembly SA2is ensured.

In the disclosure, an additional heat dissipating element may be adopted in a semiconductor package assembly of the disclosure. For example, a heat dissipation lid600is mounted onto the semiconductor package400as illustrated inFIG.16or the semiconductor package700as illustrated inFIG.17.FIG.16is a schematic cross-sectional views showing a semiconductor package assembly SA3in accordance with some embodiments of the disclosure.FIG.17is a schematic cross-sectional views showing a semiconductor package assembly SA4in accordance with alternative embodiments of the disclosure. The elements similar to or substantially the same as the elements described above will use the same reference numbers, and certain details or descriptions of the same elements (e.g. the formations and materials) and the relationship thereof (e.g. the relative positioning configuration and connection) will not be repeated herein.

Referring toFIG.16, in some embodiments, a heat dissipation lid600is provided and bonded to the semiconductor package400to form the semiconductor package assembly SA3. For example, the heat dissipation lid600is attached to the illustrated top surface S1of the semiconductor package400via a thermal interface material500. In some embodiments, the thermal interface material500thermally couples the semiconductor package400and the heat dissipation lid600. The thermal interface material500may comprise any suitable thermally conductive material, for example, a polymer having a good thermal conductivity, which may be between about 1 W/(m·K) to about 50 W/(m·K) or more. The heat dissipation lid600may have a high thermal conductivity, for example, between about 200 W/(m·K) to about 400 W/(m·K) or more, and may be formed in form of a block or a block with fins standing thereon, using a metal, a metal alloy, and the like. In some embodiments, the heat dissipation lid600may provide physical protection to the semiconductor package400in addition to the functionality of dissipating heat. The thermal interface material500is thermally coupled to the semiconductor dies410and the I/O interface dies420, which further helps to dissipate heat from the semiconductor package400to the heat dissipation lid600, and a heat dissipating efficiency of the semiconductor package assembly SA3is further ensured.

In other embodiments, as shown inFIG.17, the heat dissipation lid600is provided and bonded to the semiconductor package700to form the semiconductor package assembly SA4. For example, the heat dissipation lid600is attached to the illustrated top surface S3of the semiconductor package700via the thermal interface material500. In some embodiments, the thermal interface material500thermally couples the semiconductor package700and the heat dissipation lid600. The heat dissipation lid600may provide physical protection to the semiconductor package400in addition to the functionality of dissipating heat. For example, the thermal interface material500is thermally coupled to the semiconductor dies710, the I/O interface dies720and semiconductor dies710, which further helps to dissipate heat from the semiconductor package700to the heat dissipation lid600, and a heat dissipating efficiency of the semiconductor package assembly SA4is further ensured.

Although there is only one semiconductor package400or700being mounted to one socket200in the semiconductor package assembly (e.g., SA1, SA2, SA3, or SA4) in the above embodiments, the number of the semiconductor package400or700mounted to the socket200is not limited thereto. For example, two or more than two semiconductor packages400and/or700may be mounted to a single one socket200, where each of the two or more than two semiconductor packages400and/or700is, through the socket200, at least thermally coupled to the heat dissipating elements300and electrically connected to the circuit board100.

In alternative embodiments, two or more than two sockets200may be installed on a single circuit board100in the semiconductor package assembly (e.g., SA1, SA2, SA3, or SA4), where each socket200may be installed with one or more than one semiconductor package400and/or700and may be thermally coupled to heat dissipating elements300and electrically connected to the circuit board100. For example, each socket200are surrounded by the heat dissipating elements300at a periphery thereof (e.g. four different sides) with a certain distance (e.g., the gap G), where the heat dissipating elements300can be shared by two adjacent sockets200or not shared among the sockets200.

In accordance with some embodiments, a semiconductor package assembly includes a circuit board, a heat dissipating element and a semiconductor device. The circuit board includes a conductive pattern. The heat dissipating element is located on the circuit board, where the heat dissipating element is connected to the conductive pattern. The semiconductor device is located on the circuit board and next to the heat dissipating element, where the semiconductor device is thermally connected to the heat dissipating element through the conductive pattern.

In accordance with some embodiments, a semiconductor package assembly includes a circuit board, a plurality of cooling modules, a socket and a semiconductor package. The circuit board includes a conductive pattern and conductive contacts surrounded by the conductive pattern. The plurality of cooling modules stand on and are thermally coupled to the conductive pattern. The socket is located on the circuit board and connected to the conductive pattern and the conductive contacts, where the socket is surrounded by the plurality of cooling modules. The semiconductor package is located on and connected to the socket, where the semiconductor package is thermally connected to the heat dissipating element through the conductive pattern and the socket and is electrically connected to the circuit board through the conductive contacts and the socket.

In accordance with some embodiments, a method of manufacturing a semiconductor package assembly includes the following steps: providing a circuit board comprising a conductive pattern; mounting a heat dissipating element over the circuit board, the heat dissipating element being connected to the conductive pattern; and mounting a semiconductor device over the circuit board, the semiconductor device being located next to the heat dissipating element in a lateral direction, and the semiconductor device being thermally connected to the heat dissipating element through the conductive pattern.