SYSTEMS, APPARATUSES AND METHODS FOR PRECHARGING DIGIT LINES

Local input/output (LIO) lines may be used for precharging and equalizing the digit lines associated with a sense amplifier. The precharge device and equalization device of the associated sense amplifier may be omitted in some examples. In some examples, an equalization device may short the lines of a LIO line pair together. The LIO line pair may drive one or more pairs of digit lines to a precharge potential. Digit lines may be connected to the LIO line pair and driven to a midpoint potential in some examples.

BACKGROUND

Memory devices are structured to have one or more arrays of memory cells that are arranged, at least logically, in rows and columns. Each memory cell stores data as an electrical charge that is accessed by a digit line associated with the memory cell. A charged memory cell, when the memory cell is accessed, causes a positive change in voltage on the associated digit line, and an accessed memory cell that is not charged causes a negative change in voltage on the associated digit line. The change in voltage on the digit line may be sensed and amplified by a sense amplifier to indicate the value of the data state stored in the memory cell.

Conventional sense amplifiers are typically coupled to a pair of complementary digit lines to which a large number of memory cells are connected. As known in the art, when memory cells are accessed, a row of memory cells are activated and sense amplifiers are used to amplify a data state for the respective column of activated memory cells by coupling each of the digit lines of the selected column to voltage supplies such that the digit lines have complementary logic levels.

When a memory cell is accessed, the voltage of one of the digit lines increases or decreases slightly, depending on whether the memory cell coupled to the digit line is charged or not, resulting in a voltage difference between the digit lines. While the voltage of one digit line increases or decreases slightly, the other digit line does not and serves as a reference for the sensing operation. Respective transistors are enabled due to the voltage difference, thereby coupling the slightly higher voltage digit line to a supply voltage and the other digit line to a reference voltage, such as ground to further drive each of the digit lines to different voltages and amplify the selected digit line signal.

The digit lines are precharged during a precharge period to a precharge voltage, such as one-half of a supply voltage, so that a voltage difference can be accurately sensed and amplified during a subsequent sensing operation. Some sense amplifiers include one or more components that may improve performance of the sense amplifier, such as devices for precharging, equalization, and threshold voltage mismatch compensation.

However, increasing a number of components included in the sense amplifier may increase the size of the sense amplifier and/or reduce flexibility in sense amplifier layouts in devices.

DETAILED DESCRIPTION

FIG.1is a schematic diagram of a sense amplifier that provides threshold voltage compensation. The local data (LIO) lines and devices to selectively connect the LIO lines to the sense amplifier100are omitted fromFIG.1. As used herein, “connect” refers to electrically connecting two components together that may be coupled through another device which may selectively isolate the components. For example, LIO lines may be coupled to digit lines via transistors. The transistors may isolate the LIO lines from the digit lines when in a high resistance and/or off state and may electrically connect the LIO lines and the digit lines when in a low resistance and/or on state.

The sense amplifier100includes a first type of sensing transistors (e.g., P-channel)110and111having drains coupled to sense nodes114and115, respectively. The sense amplifier100further includes second type of sensing transistors (e.g., N-channel)112and113having drains coupled to the nodes114and115through isolation transistors151and152, all respectively. Isolation transistors151,152may selectively isolate transistors112,113based on a state of an isolation signal ISO. Sources of the transistors151and152are coupled to the nodes114and115and drains of the transistors151and152are coupled to the drain of the transistor112and the drain of the transistor113, all respectively. Respective gates of the transistors110and112are coupled to the node115and respective gates of the transistors111and113are coupled to the node114. Sources of the transistors110and111are coupled to a power supply node ACT and sources of the transistors112and113are coupled to a power supply node RNL. A digit line DL is coupled to the node114and a digit line/DL is coupled to the node115.

The sense amplifier100further includes an equalization transistor118having a drain and source coupled to nodes114and115, respectively, and includes a precharge transistor119coupled to the node115. In this embodiment, the transistor119is coupled to the node115; however, in some embodiments, the transistor119may be coupled to the node114additionally or alternatively. In some embodiments, two precharge transistors may be included, one coupled to each node115,114. The transistor119provides a voltage from its source to node115when activated by an active control signal BLEQ (e.g., high logic level). In some embodiments of the disclosure, the voltage VBLP is provided to the node115when the transistor119is active. Also, when activated by the active control signal BLEQ, the transistor118provides a conductive path between the nodes114and115to equalize the respective node voltages. In some embodiments of the disclosure, the voltage VBLP may be about 0.5V.

The sense amplifier100further includes voltage compensation transistors116and117. The transistor116is coupled to the drain of the transistor112and the node115and the transistor117is coupled to the drain of the transistor113and the node114. The transistors116and117are activated by an active compensation control signal BLECP (e.g., active high logic level).

While sense amplifier100is provided as an example, other sense amplifier designs for threshold voltage compensation also exist, some of which include more devices than the sense amplifier100. For example, the sense amplifiers described in U.S. Pat. Nos. 8,598,912, 10,236,036, 10,943,644, and 11,152,055 may provide threshold voltage compensation. While these sense amplifiers may provide improved performance compared to sense amplifiers with fewer components, these sense amplifiers may require additional devices for providing the improved performance as well as the signal lines required for controlling the devices. This may increase the size of the sense amplifiers and/or impose layout restrictions when placing the sense amplifiers in a device. Accordingly, a sense amplifier with a smaller size and/or reduced layout restrictions may be desired in some applications.

According to embodiments of the present disclosure, local input/output (LIO) lines (e.g., local data lines) may be used for precharging and equalizing the digit lines associated with a sense amplifier. The precharge device and equalization device of the associated sense amplifier (e.g., transistors119and118) may be omitted, and the sense amplifier may still provide threshold voltage compensation and/or other performance improvements. In some applications, removing the precharge and equalization devices may reduce the components required in the sense amplifier and/or mitigate the increase in layout requirements.

FIG.2is a block diagram of an apparatus according to at least one embodiment of the disclosure. The apparatus may be a semiconductor device200, and will be referred to as such. The semiconductor device200may include, without limitation, a DRAM device. The semiconductor device200may be integrated into a single semiconductor chip in some embodiments of the disclosure.

The semiconductor device200includes a memory array250. The memory array250is shown as including a plurality of memory banks. In the embodiment ofFIG.2, the memory array250is shown as including sixteen memory banks BANK0-BANK15, however memory array250may have more or fewer memory banks in other examples (e.g., 4, 8, 32). Each memory bank includes a plurality of word lines WL, a plurality of bit lines BL and /BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of digit lines DL and/DL. Selection of the word line WL is performed by a row decoder240and selection of the digit lines DL and/DL is performed by a column decoder245. In the embodiment ofFIG.1, the row decoder240includes a respective row decoder for each memory bank and the column decoder245includes a respective column decoder for each memory bank. The digit lines DL and/DL (e.g., bit lines) are coupled to a respective sense amplifier (SAMP). Read data from the digit line DL or/DL is amplified by the sense amplifier SAMP, and transferred to read/write amplifiers255over complementary local data lines (LIOT/B), transfer gate (TG), and complementary main data lines (MIOT/B). Conversely, write data outputted from the read/write amplifiers255is transferred to the sense amplifier SAMP over the complementary main data lines MIOT/B, the transfer gate TG, and the complementary local data lines LIOT/B, and written in the memory cell MC coupled to the bit line BL or/BL.

In some applications, the number of sense amplifiers for each bank may equal a number of columns in each bank. Although only one sense amplifier SAMP is shown inFIG.2, semiconductor device200may include hundreds or thousands of sense amplifiers. In some examples, each sense amplifier SAMP may be coupled to a corresponding local data line pair LIOT/B. In some examples, sense amplifiers SAMP may be selectively coupled to a local data line pair LIOT/B. In some of these examples, there may be fewer local data line pairs LIOT/B than sense amplifiers SAMP.

According to embodiments of the present disclosure, a local data line pair LIOT/B may be selectively connected to a sense amplifier SAMP by a column select signal CS, which may be provided by column decoder245in some embodiments. For example, local data line LIOT may be connected to digit line DL and local data line LIOB may be connected to digit line/DL associated with sense amplifier SA. The local data line pair LIOT/B may be selectively connected (e.g., shorted) together. That is, a local data line LIOT may be connected to a local data line LIOB. When the local data line pair LIOT/B are connected together, the resulting potential on the local data line pair LIOT/B may be a potential at approximately the midpoint of the potentials of the digit lines DL and/DL, referred to as a midpoint potential. When the digit lines DL and/DL are connected to the local data line pair LIOT/B, the digit lines DL and/DL may be driven to the midpoint potential. Optionally, in some embodiments, a digit precharge voltage circuit (not shown inFIG.1) may provide a midpoint potential to the local data line pair LIOT/B to urge the digit lines to approach the midpoint potential.

The semiconductor device200may employ a plurality of external terminals that include command and address and chip select (CA/CSS) terminals coupled to a command and address bus to receive commands and addresses, and a chip select CSS signal. The external terminals may further include clock terminals to receive clocks CK_t and CK_c, and data clocks WCK_t and WCK_c, and to provide access data clocks RDQS_t and RDQS_c, data terminals DQ, data mask terminal DM, and power supply terminals to receive power supply potentials VDD, VSS, VDDQ, and VSSQ.

The clock terminals are supplied with external clocks CK_t and CK_c that are provided to an input buffer220. The external clocks may be complementary. The input buffer220generates an internal clock ICLK based on the CK_t and CK_c clocks. The ICLK clock is provided to the command decoder215and to an internal clock generator222. The internal clock generator222provides various internal clocks LCLK based on the ICLK clock. The LCLK clocks may be used for timing operation of various internal circuits. Data clocks WCK_t and WCK_c are also provided to the external clock terminals. The WCK_t and WCK_c clocks are provided to a data clock circuit275, which generates internal data clocks based on the WCK_t and WCK_c clocks. The internal data clocks are provided to the input/output circuit260to time operation of circuits included in the input/output circuit260to time the receipt of write data.

The CA/CSS terminals may be supplied with memory addresses. The memory addresses supplied to the CA/CSS terminals are transferred, via a command/address input circuit205, to an address decoder212. The address decoder212receives the address and supplies a decoded row address XADD to the row decoder240and supplies a decoded column address YADD to the column decoder245. The CA/CSS terminals may be supplied with commands. Examples of commands include access commands for accessing the memory, such as read commands for performing read operations and write commands for performing write operations, mode register write and read commands for performing mode register write and read operations, as well as other commands and operations.

The commands may be provided as internal command signals to a command decoder215via the command/address input circuit205. The command decoder215includes circuits to decode the internal command signals to generate various internal signals and commands for performing operations. For example, the command decoder215may provide a row command signal ROWACT to select a word line and a column command signal R/W to select a bit line.

The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to an internal voltage generator circuit270. The internal voltage generator circuit270generates various internal potentials VPP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS supplied to the power supply terminals. The internal potential VPP is mainly used in the row decoder240, the internal potentials VOD and VARY are mainly used in the sense amplifiers SAMP included in the memory array250, and the internal potential VPERI is used in many peripheral circuit blocks.

The power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input/output circuit260. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potentials as the power supply potentials VDD and VSS supplied to the power supply terminals in an embodiment of the disclosure. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals in another embodiment of the disclosure. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used for the input/output circuit260so that power supply noise generated by the input/output circuit260does not propagate to the other circuit blocks.

When an activate command and a row address are received, followed by a read command and a column address, read data is read from memory cells in the memory array250corresponding to the row address and column address. The read command is received by the command decoder215, which provides internal commands so that read data from the memory array250is provided to the read/write amplifiers255. The read data is provided to the input/output circuit260and output to the data terminals DQ. When an activate command and a row address are received, followed by a write command and a column address, write data supplied to the data terminals DQ is written to a memory cells in the memory array250corresponding to the row address and column address. A data mask may be provided to the data mask terminals DM to mask portions of the data when written to memory. The write command is received by the command decoder215, which provides internal commands so that the write data is received by input receivers in the input/output circuit260. The write data is supplied from the data terminals DQ via the input/output circuit260to the read/write amplifiers255, and by the read/write amplifiers255to the memory array250to be written into the memory cell MC. Read and write may be provided to the DQ terminals connection with one or more clock signals, such as data clocks WCK_t and WCK_c, and to provide access data clocks RDQS_t and RDQS_c.

FIG.3is a circuit diagram of a sense amplifier according to at least one embodiment of the disclosure. In some embodiments, the sense amplifier300may be used to implement the sense amplifier SAMP shown inFIG.2. The sense amplifier300may include sensing devices310-313, isolation devices351and352, and voltage compensation devices316,317. Also shown inFIG.3are devices356and357, which selectively connect the digit lines DL and/DL to a LIO pair LIOT and LIOB, which may correspond to LIO pair LIOT/B shown inFIG.2in some embodiments.

Sensing devices310-313may correspond to sensing transistors110-113of sense amplifier100shown inFIG.1in some embodiments, voltage compensation devices316,317may correspond to voltage compensation transistors116,117, respectively. Similarly, in some embodiments, isolation devices351,352may correspond to isolation transistors151,152. In some embodiments, sense amplifier300may be the same as sense amplifier100except that equalization transistor118and precharge transistor119are omitted.

As shown inFIG.3, the digit line DL may be selectively connected to local data line LIOT by device356and digit line/DL may be selectively connected to local data line LIOB by device357. In some embodiments, devices356and357may be N-channel transistors, but other devices or transistor types may be used in other examples. The gates of devices356,357may receive a column select signal CS. When the column select CS signal is in an active high state, the devices356,357may be in an active (e.g., ‘on’) state, and the digit lines may be connected to the LIO lines. When the CS signal is in an inactive low state, the devices356,357may be in an inactive (e.g., ‘off’) state, and the digit lines may be disconnected from the LIO lines.

FIG.4is a circuit diagram of at least a portion of a semiconductor device according to at least one embodiment of the disclosure. Semiconductor device400may be included in semiconductor device200shown inFIG.2. In the portion shown inFIG.4, semiconductor device400may include a sense amplifier block SA402, an equalization device460, a digit precharge voltage circuit (DPVC)462, LIO precharge devices464,466, and read/write circuitry401,405. In some embodiments, the semiconductor device400may use local data LIO lines to precharge and equalize digit lines coupled to the sense amplifiers.

Sense amplifier block SA402may include one or more sense amplifiers, such as sense amplifier300shown inFIG.3. In the example shown inFIG.4, sense amplifier block SA402includes 32 sense amplifiers, but more or fewer sense amplifiers may be included in sense amplifier block402in other examples. Each of the sense amplifiers of sense amplifier block SA402may receive a corresponding column select signal CS<31:0>, an isolation signal ISO, and a compensation control signal BLCP. Each sense amplifier of sense amplifier block SA402may be coupled to a power supply node ACT and a power supply node RNL. Each of the sense amplifiers may be coupled to a corresponding digit line pair DL<31:0>/DL<31:0>. In the example shown inFIG.4, each of the sense amplifiers may be coupled to a LIO line pair LIOT/B (e.g., by turning devices356and357on and off). However, in other examples, each sense amplifier of sense amplifier block SA402may be coupled to a corresponding LIO line pair (e.g., LIOT<31:0>, LIOB<31:0>).

Local data line LIOB may be coupled between the sense amplifier block SA402and read/write circuitry401. Local data line LIOB may be further coupled to LIO precharge device464. LIO precharge device464may be coupled between LIOB and a potential (VDD in the example shown inFIG.4). In some embodiments, such as the one shown inFIG.4, LIO precharge device464may be a P-channel transistor. A gate of the LIO precharge device464may receive a precharge signal LIOPRE. When the precharge signal LIOPRE is active low, LIO precharge device464may be active, and LIOB may be driven to the potential VDD. When the precharge signal LIOPRE is inactive high, LIO precharge device464may be inactive, and LIOB is no longer driven to the potential VDD.

Local data line LIOT may be coupled between the sense amplifier block SA402and read/write circuitry405. Local data line LIOT may be further coupled to LIO precharge device466. LIO precharge device464may be coupled between LIOT and a potential (VDD in the example shown inFIG.4). In some embodiments, such as the one shown inFIG.4, LIO precharge device466may be a P-channel transistor. A gate of the LIO precharge device466may receive a precharge signal LIOPRE. When the precharge signal LIOPRE is active low, LIO precharge device466may be active, and LIOT may be driven to the potential VDD. When the precharge signal LIOPRE is inactive high, LIO precharge device466may be inactive, and LIOT is no longer driven to the potential VDD.

Read/write circuitry401and405may be implemented by known read/write circuitry in some embodiments. In some embodiments, read/write circuitry401and/or405may include one or more circuits such as a transfer gate (e.g., TG inFIG.2), a read/write amplifier such as R/W AMP255, and/or at least a portion of an IO circuit, such as IO circuit260. The read/write circuitry401and405may be controlled, at least in part, by read and write enable signals REN, WEN. Portions of read/write circuitry401,405used for read operations (e.g., when a read command is received by semiconductor device400) may be enabled when an active REN signal is received and disabled when an inactive REN signal is received. Portions of read/write circuitry401,405used for write operations (e.g., when a write command is received by semiconductor device400) may be enabled when an active WEN signal is received and disabled when an inactive WEN signal is received.

The equalization device460may be coupled between LIOT and LIOB of the LIO pair. In some examples, such as the one shown inFIG.4, the equalization device460may be an N-channel transistor. The equalization device460may receive an equalization control signal LIOEQ at a gate. When the equalization control signal LIOEQ is in an active high state, equalization device460may be active and connect (e.g., short) LIOT and LIOB together. When LIOT and LIOB are connected to respective digit lines DL<31:0> and /DL<31:0> and shorted together by equalization device460, the digit lines may be driven to a potential equal to or approximately equal (e.g., within 10%, within 20%) to a midpoint potential such as VDD/2, for example. In some embodiments, the midpoint potential may correspond to a desired precharge potential of the digit lines DL<31:0>, /DL<31:0>.

While ideally, shorting LIOB and LIOT together with equalization device460causes the digit line pairs to equalize to a midpoint potential, in some applications, the LIOB and LIOT may not equalize the digit lines at the desired midpoint (and/or equalize within a desired time) due to variations in potential and/or other properties of the individual digit lines. Optionally, in some examples, such as the one shown inFIG.4, a DPVC462may be included to “urge” LIOB and LIOT, and thus the digit lines, to the desired midpoint potential. The DPVC462may be coupled to LIOT and/or LIOB (coupled to LIOT and coupled to LIOB through equalization device460in the example shown inFIG.4) and a midpoint potential VBLP (which may be equal to VDD/2 in some embodiments). In some examples, such as the one shown inFIG.4, the DPVC462may include an N-channel transistor. The DPVC462may receive the equalization control signal LIOEQ at a gate. When LIOEQ is active high, the DPVC462may connect the midpoint potential VBLP to the shorted LIO line pair.

In some examples, VDD may be 0.9V and VBLP may be 0.45V. Other voltages may be used in other examples. The voltage levels selected may be based, at least in part, on a desired precharge potential of the LIO lines and/or digit lines. The voltage levels selected may be based, at least in part, on a type of device that includes semiconductor device400. For example, higher voltages may be used in electronic devices intended to remain coupled to a power source (e.g., power outlet) whereas lower voltages may be used in battery-powered devices (e.g., mobile phones, tablets).

In operation, when pre-charging of a digit line pair is desired (e.g., after a write operation), the column select CS signal associated with the digit line pair is activated (or remains activated if the digit line pair is associated with a selected sense amplifier) to connect the digit line pair to the corresponding LIO pair and the equalization control signal LIOEQ may be activated (e.g., active high) to cause equalization device460to be in an active state to connect LIO lines LIOB and LIOT to one another. As noted above, this causes LIOB and LIOT to drive (e.g., pull) the digit lines to (or approximately to) a midpoint voltage. In embodiments including the DPVC462, the active LIOEQ signal may cause the DPVC462to be in an active state, which may connect the LIO line pair to a midpoint voltage VBLP. The digit lines are driven to the midpoint potential VBLP, which may correspond to a desired precharge potential of the digit lines.

Optionally, device460, device462, LIOEQ, and/or one or more CS signals may be driven to a higher voltage (e.g., higher than VDD). In some applications, this may decrease the time required to pre-charge the digit lines. In some embodiments, the higher voltage may be 0.5 V higher than the voltage of VDD. For example, if VDD is 0.9V, device460, device462, LIOEQ, and/or one or more CS signals may be driven to 1.4V.

By using the LIO lines to precharge the digit lines, the sense amplifiers of sense amplifier block SA402may not include equalization and precharge devices, such as shown in sense amplifier300ofFIG.3. Thus, the sense amplifiers of sense amplifier block SA402and sense amplifier300may include fewer components compared to other sense amplifiers, such as sense amplifier100shown inFIG.1. This may reduce the layout size of the sense amplifiers and/or reduce layout restrictions of the sense amplifiers (e.g., provide more flexibility in arranging the sense amplifiers of sense amplifier block SA402). The semiconductor device400may have a reduced layout size overall in some embodiments. For example, in embodiments where the LIO pair is shared by multiple sense amplifiers, the equalization device may be shared amongst multiple sense amplifiers, reducing the total number of equalization devices in semiconductor device400. In some embodiments, the precharge devices of the LIO lines may be pre-existing precharge devices used to precharge the LIO lines. Thus, no additional precharge devices may be required by semiconductor device400compared to existing semiconductor devices in these embodiments.

FIG.5is a timing diagram illustrating states of various signals of a semiconductor device according to at least one embodiment of the disclosure. The signals and the states shown in timing diagram500may illustrate the signals and relative states of a semiconductor device, or a portion thereof, such as semiconductor device200, semiconductor device400, and/or sense amplifier300, which may be included in semiconductor device200and/or400in some embodiments. While reference will be made to semiconductor device400and sense amplifier300in describing the timing diagram500, the signals and the states illustrated in timing diagram500may not be limited to the specific examples shown inFIGS.3and4. Furthermore, the operations and/or order of operations in timing diagram500are provided merely as examples, and other operations or order of operations may be performed in other examples.

In the top plot502of timing diagram500, V(CS<0>) and V(CS<1>) illustrate the states of two bits of a multi-bit column address signal CS. In some embodiments, each bit of the CS signal may go to a different sense amplifier of a sense amplifier block, such as sense amplifier300and sense amplifier block SA402. Plot504illustrates the states of LIO lines of a LIO pair, V(LIOT) and V(LIOB), which may be selectively connected to digit lines of one or more sense amplifiers. Plot506includes V(DL<0>) and V(/DL<0>) which illustrate the states of digit lines of a digit line pair coupled to a sense amplifier receiving the CS<0> signal. Plot508includes V(DL<1>) and V(/DL<1>) illustrating the states of digit lines of a digit line pair coupled to a sense amplifier receiving the CS<1> signal. In plot510, V(REN) and V(WEN) indicate the states of read and write enable signals, respectively. The read and write enable signals may be provided to read/write circuitry, such as read/write circuitry401and405. The bottom plot512of timing diagram500, V(LIOEQ) indicates the state of an equalization control signal that activates an equalization device and DPVC, such as equalization device460and DPVC462.

At or before time T0, the signals of timing diagram500may be in states reflecting a prior access operation, for example, a read operation that was initiated prior to time TO. For example, the levels of the digit lines DL<0> and/DL<0> may reflect levels from accessing of an associated row of a memory array. In the example shown inFIG.5, a write operation is performed as indicated by the activation of the WEN signal at or around time TO. Although not shown in timing diagram500, the WEN signal may be activated responsive to a write command received by a semiconductor device, such as semiconductor device200and/or400. The activated WEN signal may enable write components of read/write circuitry, such as read/write circuitry401,405.

The column select signal associated with a sense amplifier may be activated at or around time T1, responsive, at least in part, to the write command. Although in the example inFIG.5shows the column select signal activated at or around time T1, in some embodiments, the column select signal may be activated prior to T1 such as at or around TO. In the example shown in plot504, CS<0> is activated, corresponding to a selected sense amplifier. The column select signal CS<1> may be associated with non-selected sense amplifiers, and remains inactive. Which column select signal is activated may be based, at least in part, on an address (not shown) received with the write command.

Although not shown in timing diagram500, data to be written to a memory cell associated with the selected sense amplifier may be received by the semiconductor device and provided to the associated LIO line pair via read/write circuitry. At or around time T2, the LIO lines LIOT and LIOB are driven to states indicative of the data to be written to the memory cell. In the example shown inFIG.5, LIOT is driven low and LIOB is driven high. Because CS<0> is activated, the digit lines DL<0> and/DL<0> are connected to LIOT and LIOB. Thus, the digit lines DL<0> and/DL<0> are driven to states corresponding to LIOT and LIOB, respectively beginning at or around time T3. Digit lines DL<1> and /DL<1>, which are coupled to a non-selected sense amplifier, remain in their prior states.

After data has been written to the memory cell in accordance with the write operation, the write enable signal WEN may transition to an inactive state at or around time T4. This may disable write components of the read/write circuitry.

At or around time T5, the equalization control signal LIOEQ may be activated responsive, at least in part, to the end of the write operation and/or receipt of a precharge command (not shown inFIG.5). The active LIOEQ signal may activate an equalization device, such as equalization device460. The equalization device460may short the LIO lines of the LIO pair together. The connecting of the LIO lines together may drive the LIO lines LIOT and LIOB to a midpoint potential at or around time T5. Optionally, in some embodiments, the LIOEQ may further activate a digit precharge voltage circuit (DPVC), such as DPVC462, which may connect the LIO pair to the midpoint potential.

Because CS<0> remains active, digit lines DL<0> and/DL<0> remain connected to LIOT and LIOB, respectively. Accordingly, beginning at or around time T5, the digit lines DL<0> and/DL<0> may be driven toward the midpoint potential and reach the midpoint potential (or approximately the midpoint potential) at or around time T6 to be precharged.

In some embodiments, responsive to the end of the write operation and/or receipt of a precharge command, the column select signals CS associated with unselected sense amplifiers may be activated. As shown in the example ofFIG.5, at or around time T5, CS<1> is activated. This may connect digit lines DL<1> and/DL<1> associated with non-selected sense amplifiers to LIOT and LIOB. Thus, digit lines DL<1> and/DL<1> may be driven toward the midpoint potential at or around time T5 and reach the midpoint potential (or approximately the midpoint potential) at or around time T6 to be precharged. Although only one non-selected column select signal and digit line pair are shown in timing diagram500, additional non-selected sense amplifiers with corresponding column select signals and digit line pairs may be present. In some embodiments, some or all of the associated column select signals and digit line pairs of the non-selected sense amplifiers may perform the same or similarly to CS<1>, DL<1> and/DL<1>. Although in the example inFIG.5shows the column select signal activated at or around time T5, in some embodiments, the column select signal may be activated prior to time T5 such as at or around T4.

FIG.6is a flow chart of a method according to at least one embodiment of the disclosure. The method600may be performed in whole or in part by a semiconductor device, such as semiconductor device200and/or400.

At block602“shorting a first line and a second line of a local data line pair together” may be performed. In some embodiments, local data line pair may include local data lines LIOT and LIOB shown inFIGS.2-4. In some embodiments, shorting may be performed by an equalization device, such as equalization device460.

At block604, “connecting the local data line pair to a digit line pair” may be performed. In some embodiments, the connecting may be performed by one or more devices, such as devices356and357. In some embodiments, the digit line pair is connected to the local data line pair responsive to activation of a column select signal CS. In some embodiments, the column select signal is activated, based, at least in part, on an address associated with an access command. Additionally or alternatively, in some embodiments, at block604, “connecting the local data line pair to a plurality of digit line pairs” may be performed. For example, multiple digit line pairs associated with multiple sense amplifiers, such as the sense amplifiers of sense amplifier block SA402. Although block604is shown as following block602, in some embodiments, block604may precede and/or performed concurrently, at least in part, with block602.

In some embodiments, shorting the first line and the second line together drive the first line and the second line to a third potential equal to a midpoint between the first potential and the second potential. In some embodiments, third potential is equal to a digit line precharge potential.

Optionally, in some embodiments, method600may further include “providing to the first line, the second line, or both a midpoint potential” as indicated by block610. In some embodiments, the midpoint potential may be provided by connecting the local data lines to the midpoint potential by activating a digit precharge voltage circuit (DPVC), such as DPVC462. Although shown following block604, in some embodiments, block606may be performed prior to block604and/or block602, or at least partially concurrently with block602and/or604.

FIG.7is a flow chart of a method according to at least one embodiment of the disclosure. The method700may be performed in whole or in part by a semiconductor device, such as semiconductor device200and/or400.

At block702, “connecting at least one local data line pair to a plurality of digit line pairs” may be performed. In some embodiments, local data line pair may include local data lines LIOT and LIOB shown inFIGS.2-4. In some embodiments, the digit line pairs may include digit line pairs DL and/DL and/or DL<31:0>/DL<31:0>. In some embodiments, the connecting may be performed by one or more devices, such as devices356and357. In some embodiments, the digit line pair is connected to the local data line pair responsive to activation of a column select signal CS. In some embodiments, the column select signal is activated, based, at least in part, on an address associated with an access command.

At block704, “providing, via the at least one local data line pair, a precharge voltage to the plurality of digit line pairs during a digit line precharge operation” may be performed. In some embodiments, providing the precharge voltage comprises connecting the at least one local data line pair to the precharge voltage. In some embodiments, the precharge voltage may be a midpoint voltage, such as VDD/2 and/or VBLP. In some embodiments, the precharge voltage may be provided by activating a digit precharge voltage circuit (DPVC), such as DPVC462.

Optionally, in some embodiments, method700may further include “shorting a first line and a second line of the at least one local data line pair together” as indicated by block706. In some embodiments, shorting may be performed by an equalization device, such as equalization device460. Although shown following block704, in some embodiments, block706may be performed prior to block704and/or block7602, or at least partially concurrently with block702and/or704.

The apparatuses, systems, and methods disclosed herein may utilize local data LIO lines for precharging and equalizing digit lines associated with a sense amplifier. This may allow the precharge device and equalization device of the associated sense amplifier to be omitted. In some applications, removing the precharge and equalization devices may reduce the components required in the sense amplifier and/or mitigate increase in layout requirements.

Certain details are set forth herein to provide a sufficient understanding of examples of the disclosure. However, it will be clear to one having skill in the art that examples of the disclosure may be practiced without these particular details. Moreover, the particular examples of the present disclosure described herein should not be construed to limit the scope of the disclosure to these particular examples. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the disclosure. Additionally, terms such as “couples” and “coupled” mean that two components may be directly or indirectly electrically coupled. Indirectly coupled may imply that two components are coupled through one or more intermediate components.