Infrared image sensor component

An infrared image sensor component includes at least one III-V compound layer on the semiconductor substrate, in which the portion of the III-V compound layer(s) uncovered by the patterns is utilized as active pixel region for detecting the incident infrared ray. The infrared image sensor component includes at least one transistor coupled to the active pixel region, and charge generated by the active pixel region is transmitted to the transistor.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation.

In semiconductor technologies, image sensors are used for sensing a volume of exposed light projected towards the semiconductor substrate. Complementary metal-oxide-semiconductor (CMOS) image sensor devices are widely used in various applications such as digital still camera (DSC) applications. These devices utilize an array of active pixels or image sensor cells, including photodiode elements and MOS transistors, to collect photo energy to convert images to streams of digital data.

DETAILED DESCRIPTION

The present disclosure is related to an infrared image senor component. The infrared sensor component includes a substrate, a III-V compound layer disposed on the substrate as an active pixel region, and a plurality of transistors formed on the III-V compound layer. The III-V compound layer is made of III-V groups materials, which have wide infrared wavelength coverage, large absorption coefficient in the infrared region, and high carrier mobility. Therefore, the performance of the infrared image sensor component can be improved accordingly.

FIG. 1AtoFIG. 1Eare local cross-sectional views of different stages of a method of manufacturing an infrared image sensor component, in accordance with some embodiments of the disclosure. Reference is made toFIG. 1A. A III-V compound layer120is formed on a substrate110. The substrate110is a semiconductor substrate. In some embodiments, the semiconductor substrate is made of, for example, silicon; a compound semiconductor, such as silicon carbide, indium arsenide, or indium phosphide; or an alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. The substrate110may optionally include various doped regions, dielectric features, or multilevel interconnects in the semiconductor substrate.

The III-V compound layer120is made from the III-V groups in the periodic table of elements. In some embodiments, the III-V compound layer120is a single layer having a tuned energy gap. In some other embodiments, the III-V compound layer120is a combination of multiple III-V material layers with wide and narrow energy gap. In yet some other embodiments, the III-V compound layer120may have gradient energy gap.

The III-V compound layer120or each of the layers of the III-V compound layer120is made of material selected from a group consisting of InwAlxGayAsz, InwAlxGayPz, InwAlxGaySbz, InwAlxAsyPz, InwAlxPySbz, InwGaxAsyPz, InwGaxPySbz, AlwGaxAsyPz, AlwGaxPySbz, InwAsxPySbz, AlwAsxPySbz, GawAsxPySbz, in which w+x+y+z=1. The III-V compound layer120can be epitaxially grown by a number of processes including, but not limited to, molecular beam epitaxy (MBE), or metal organic chemical vapor deposition (MOCVD), also known as metal organic vapor phase epitaxy (MOVPE), using appropriate precursors. The thickness of the III-V compound layer120is in a ranged from about 0.1 μm to about 10 μm.

Reference is made toFIG. 1B. At least one transistor130is formed on the III-V compound layer120. The transistors130are formed in an array and are arranged corresponding to the pixels of the infrared image senor component100. In some embodiments, the transistor130can be a metal-oxide-semiconductor (MOS) device. Each of the transistors130includes a control gate132formed on the III-V compound layer120, and two doped regions134, and136formed in the III-V compound layer120and disposed at opposite sides of the control gate132. The doped regions134, and136may be doped with impurities. The transistor130further includes a gate isolation138formed between the control gate132and the III-V compound layer120. The transistor130further includes sidewalls135formed at opposite side surfaces of the control gate132.

In some embodiments, the transistor130is a complementary metal-oxide-semiconductor (CMOS) device. An exemplary method of fabricating the transistor130begins at, for instant, forming a photoresist layer on the surface of the III-V compound layer120. In some embodiments, the III-V compound layer120is a P-type layer which includes P-type impurity. The photoresist layer is performed by masking, exposing and developing to define the region for subsequent ion injection, then respectively form a N-type doped regions134, and136in the III-V compound layer120by ion injection. The photoresist layer is removed by, such as stripping, after the N-type doped regions134, and136are formed. The doping impurity of forming the N-type doped regions134, and136can be P, As, Si, Ge, C, O, S, Se, Te, or Sb. The doped regions134, and136are generally formed of a low or high concentration impurity region. In some embodiments, the doped regions134,136are regarded as source/drain regions. In some embodiments, the doped region134is extended longer than the doped region136. The N-type doped region134and the underlying portion of P-type III-V compound layer120may detect incident light.

An isolation layer is further formed on the surfaces of the III-V compound layer120by using a low temperature process, in which the isolation layer may be silicon oxide. A conductive layer is further formed on the isolation layer, in which the conductive layer can be doped polycrystalline silicon, tungsten, titanium nitride, or other suitable materials. One or more etching processes are performed to the isolation layer and the conductive layer thereby forming gate isolation138and the control gate132thereon. Then the sidewalls135are formed at the sides of the control gate132.

The infrared image sensor component100further includes at least one shallow trench isolation structure180. The shallow trench isolation structure180is at least formed in the III-V compound layer120. In some embodiments, the shallow trench isolation structure180is formed in the III-V compound layer120and in the semiconductor substrate110. The shallow trench isolation structure180is formed next to the doped region134to separate the adjacent pixels. The material of the shallow trench isolation structure180can be dielectric, such as oxide.

Reference is made toFIG. 1C. A plurality of patterns140and a plurality of dielectric layers150are sequentially formed on the III-V compound layer120and on the transistors130. The patterns140provide functions including wiring and light shielding. The patterns140are formed by depositing a conductive layer and etching the conductive layer. The material of the conductive layer may be metal, such as W, Cu, or Co. The dielectric layer150is made of insulating material with high transmittance to improve light transmittance. The dielectric layer150can be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, low-dielectric constant dielectric material or a combination thereof. The dielectric layer150can be formed by a deposition process, such as an ALD process, a CVD process, or a PVD process.

The patterns140are formed for shielding a portion of the transistors130and a portion of the III-V compound layer120. Namely, only the doped region134and a portion of the III-V compound layer120are exposed from the patterns140. The doped region134and the exposed portion of the III-V compound layer120are utilized as active pixel region120′ for sensing the light including infrared ray. The active pixel region120′ receives light to generate and accumulate photocharges, and a logic element (not illustrated) may detect electric signals transmitted from the corresponding active pixel region120′.

The energy gap of the active pixel region120′ can be tuned by the composition of the III-V compound layer120and the doped region134. The energy gap of the active pixel region120′ is tuned corresponding to the wavelength of the incident light such as infrared ray. The active pixel region120′ absorbs incident light and accumulates charges corresponding to an amount and/or intensity of the light. The active pixel regions120′ is coupled with the transistors130. The transistor130includes the control gate132, and doped regions134, and136. The doped region134and the under lying III-V compound layer120construct the active pixel region120′ for receiving the charges generated by the active pixel region120′. The charges are transferred to the doped region136through the conducted control gate132. In some embodiments, doped region136generally has parasitic capacitance, so charges may accumulate at the doped region136. The potential of the doped region136can be changed by the accumulated charges, and therefore the amount of charges is detected through the change in electric potential of the doped region136.

In order to prevent light current leakage, the patterns140are formed to shield the portion other than the active pixel region120′. In some embodiments, the patterns140are formed covering the control gate132, and the doped regions136. The active pixel region120′ and the doped region134are exposed from the patterns140to receive the incident light, such as infrared ray.

Reference is made toFIG. 1D. An infrared filter160is disposed on the dielectric layer150. The infrared filter160is an infrared ray pass filter which passes infrared light while blocking other wavelengths. In some embodiments, the infrared filter160is formed of a material capable of blocking out all light except for the spectrum that falls between 800 nanometers and 1000 nanometers.

Reference is made toFIG. 1E, an optical lens170is formed on the infrared filter160. The optical lens170is formed of thermosetting resin and may have a predetermined curvature radius. The curvature radius of the optical lens170can be different depending on the depth of the active pixel region120′, and the wavelength of incident light. The optical lens170changes the path of incident light and collects light onto the active pixel region120′.

Using the III-V compound layer120as the active pixel region120′ may reduce the thickness of the infrared image sensor component100. Comparing with the embodiments of silicon substrate having p-n junction diodes, the III-V compound layer120provides wider infrared response. Namely, the III-V compound material has wider infrared wavelength coverage than the silicon, such that the infrared ray including near infrared ray, and middle infrared ray can be detected by the III-V compound layer120. Also, the III-V compound material has larger absorption coefficient in the infrared region than the silicon, such that the thickness of the III-V compound layer120is thinner than the p-n junction diodes. Furthermore, the III-V compound material provides higher carrier mobility than the silicon, thus the pixel response of the infrared image sensor component100using the III-V compound layer120is faster than that of using the silicon substrate with p-n junction diodes.

Reference is made toFIG. 2, which a local cross-sectional view of an infrared image sensor component of some embodiments of the disclosure. The transistor130may include epitaxy structures131and133instead of the doped regions134and136. In order to form the epitaxy structures131and133, a plurality of openings are formed at opposite sides the control gate132and in the III-V compound layer120, and then an epitaxy is performed to grow the epitaxy structures131and133are formed in the openings. The source/drain stressors form at least parts of the epitaxy structures131and133. In the embodiments in which the transistor130is an nMOS device, the epitaxy structures131and133may include silicon phosphorous (SiP), silicon carbide (SiC), or the like. In the embodiments in which the transistor is a pMOS device, the epitaxy structures131and133may include silicon germanium (SiGe).

The patterns140are formed to shield the control gate132and the epitaxy structure133and to expose the epitaxy structure131and a portion of the III-V compound layer120. The uncovered III-V compound layer120can be utilized as active pixel region120′ to receive the infrared ray and generate photocharges. The epitaxy structure131is coupled to the active pixel region120′, thus the charges are received by the epitaxy structure131and is further transferred to the epitaxy structure133through the conducted control gate132, and a logic element (not illustrated) may detect electric signals transmitted from the corresponding active pixel region120′.

The active pixel regions and the transistors of the infrared image sensor component may have various modifications. For example,FIG. 3AtoFIG. 3Fshow local cross-sectional views of different stages of fabricating an infrared image sensor component, in accordance with some other embodiments of the disclosure. The method begins atFIG. 3A, at least one III-V compound layer is formed on a semiconductor substrate210. In some embodiments, a first III-V compound layer220, and a second III-V compound layer230are formed on a semiconductor substrate210.

In some embodiments, the semiconductor substrate210is made of, for example, silicon; a compound semiconductor, such as silicon carbide, indium arsenide, or indium phosphide; or an alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. The semiconductor substrate210may also include various doped regions, dielectric features, or multilevel interconnects in the semiconductor substrate.

The first III-V compound layer220and the second III-V compound layer230are compounds made from the III-V groups in the periodic table of elements. However, the first III-V compound layer220and the second III-V compound layer230are different from each other in composition. The first III-V compound layer220and the second III-V compound layer230can be respectively epitaxially grown by a number of processes including, but not limited to, metal organic chemical vapor deposition (MOCVD), also known as metal organic vapor phase epitaxy (MOVPE), using appropriate precursors. The first III-V compound layer220and the second III-V compound layer230directly contact each other.

Different composition of III-V compound materials causes the layers to have different energy gaps. An energy gap discontinuity between the first III-V compound layer220and the second III-V compound layer230, along with the piezo-electric effect, creates a very thin layer240of highly mobile conducting electrons in the first III-V compound layer220. The thin layer240contributes to a conductive two dimensional electron gas (2DEG) layer near the junction of the two layers. The thin layer240(also referred to as the 2 DEG layer240) allows charge to flow through the component.

A third III-V compound layer250is further formed on the second III-V compound layer230. In some embodiments, the third III-V compound layer250is a doped III-V compound layer, such a p-type doped GaN layer (also referred to as the doped GaN layer250). The doped GaN layer250can be epitaxially grown by MOCVD using appropriate aluminum, nitrogen and gallium precursors. The aluminum precursor includes trimethylaluminum (TMA), triethylaluminum (TEA), or suitable chemical precursors. Exemplary gallium containing precursors are trimethlgallium (TMG), triethylgallium (TEG) or other suitable chemical precursors. Exemplary nitrogen precursors include, but are not limited to, phenyl hydrazine, dimethylhydrazine, tertiarybutylamine, ammonia, or other suitable chemical precursors. The second III-V compound layer230can also be referred to as a barrier layer.

Reference is made toFIG. 3B. The doped third III-V compound layer250is patterned for defining at least one doped III-V compound region252on the second III-V compound layer230. The 2 DEG layer240under the doped III-V compound region252is removed. In some embodiments, a mask layer, such as a photoresist layer is formed on the doped third III-V compound layer250, and the mask layer is patterned by a lithography process to form a plurality of features and a plurality of openings defined by the features on doped third III-V compound layer250. The pattern of the mask layer is formed according to a predetermined integrated circuit pattern. The lithography process may include photoresist coating, exposing, post-exposure baking, and developing. Then, an etching process is performed to define the doped III-V compound region252.

A shallow trench isolation structure212is formed in the first III-V compound layer220and the second III-V compound layer230to define an active pixel region of a pixel. In some embodiments, the shallow trench isolation structure212is further formed in the semiconductor substrate210. The shallow trench isolation structure212is a dielectric material, such as oxide. The active pixel region is defined between the III-V doped compound region252and the shallow trench isolation structure212.

A dielectric layer260is formed on the doped III-V compound region252and on the second III-V compound layer230. The dielectric layer260can be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, low-dielectric constant dielectric material or a combination thereof. The dielectric layer260can be formed by a deposition process, such as an ALD process, a CVD process, or a PVD process. The dielectric layer260is further patterned to define a plurality of openings262in the dielectric layer260. The dielectric layer260is selectively etched and cleaned to define the openings262. Exemplary etching processes include sputter etching, reactive gas etching, chemical etching and ion milling. The openings262are formed at opposite sides of the doped III-V compound region252. The openings262are led into the second III-V compound layer230. Namely, the thickness of the second III-V compound layer230under the openings262is thinner than other portions of the second III-V compound layer230.

Reference is made toFIG. 3C. A plurality of ohmic metal contacts270,272are formed in the openings262. The ohmic metal contacts270,272can be formed by depositing a ohmic contact layer on the dielectric layer260and in the openings262, and patterning ohmic contact layer. The deposition process can be sputter deposition, evaporation or chemical vapor deposition (CVD). Exemplary ohmic metals include, but are not limited to, Ta, TaN, Pd, W, WSi2, Ti, Al, TiN, AlCu, AlSiCu and Cu. In some embodiments, the ohmic contacts270,272connect to the second III-V compound layer230directly. The ohmic contacts270,272are utilized as a part of drain electrode and a source electrode.

Reference is made toFIG. 3D. The dielectric layer260on the III-V doped compound region252is etched thereby forming another opening therein. A gate metal stack274is further formed in the opening as a gate electrode. The gate metal stack274results in a device yielding an enhancement mode (E-mode) device. In the embodiment depicted inFIG. 2D, the gate metal stack274, the source and drain contacts270,272, and the 2 DEG layer240(as a channel) in the first III-V compound layer220are configured as an E-mode transistor255, which is a normally off device, and when a positive voltage applied to the gate stack for forward bias is great enough, the E-mode transistor is turned on.

Reference is made toFIG. 3E. A plurality of dielectric layers280and a plurality of patterns282are sequentially formed on dielectric layer260and on the transistor255. The patterns282can be conductive patterns and provide functions including wiring and light shielding. The patterns282are formed by depositing a conductive layer and etching the conductive layer. The material of the conductive layer may be metal, such as W, Cu, or Co. The dielectric layers280are made of insulating material with high transmittance to improve light transmittance. The dielectric layers280can be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, low-dielectric constant dielectric material or a combination thereof. The dielectric layers280can be formed by a deposition process, such as an ALD process, a CVD process, or a PVD process.

The patterns280are formed for shielding a portion of the transistors and a portion of the second III-V compound layer230. Namely, only portions of the III-V compound layer230are exposed from the patterns282. The exposed portion of the second III-V compound layer230and the underlying 2 DEG layer240are utilized as active pixel region230′ for sensing the light including infrared ray. The active pixel region230′ receives light to generate and accumulate photocharges, and a logic element (not illustrated) may detect electric signals transmitted from the corresponding active pixel region230.

The energy gap of the active pixel region230′ can be tuned by the composition of the first III-V compound layer220and the second III-V compound layer230. The energy gap of the active pixel region230′ is tuned corresponding to the wavelength of the incident light such as infrared ray. The active pixel region230′ absorbs incident light and accumulates charges corresponding to an amount and/or intensity of the light. The active pixel regions230′ is coupled with the transistors255. The ohmic metal contact270is regarded as source and is connected to the active pixel region230′ for receiving the charges generated by the active pixel region230′. The charges are transferred to the ohmic metal contact272through the conducted control gate252. In some embodiments, charges may accumulate at the ohmic metal contact272, which is regarded as drain. The potential of the ohmic metal contact272can be changed by the accumulated charges, and therefore the amount of charges is detected through the change in electric potential of the ohmic metal contact272.

In order to prevent light current leakage, the patterns282are formed to shield the portion other than the active pixel region230′. In some embodiments, the patterns282are formed covering the doped III-V compound region252and the gate metal stack274(e.g., the gate), and the ohmic metal contact272(e.g., the drain). The active pixel region230′ and the ohmic metal contact270between the active pixel region230′ and the doped III-V compound region252are exposed from the patterns282to receive the incident light, such as infrared ray.

Reference is made toFIG. 3F. An infrared filter290is disposed on the dielectric layer280, and an optical lens292is formed on the infrared filter290. The infrared filter290is an infrared ray pass filter. The curvature radius of the optical lens292can be different depending on the depth of the active pixel region230′, and the wavelength of incident light. The optical lens292changes the path of incident light and collects light onto the active pixel region230′.

The composition of the III-V compound layers can be modified to tune the energy gap of the III-V compound layers. The composition of the III-V compound layers can be modified by changing the materials of the III-V compound layer, changing the thickness of the III-V compound layer, and/or changing the concentration of the III-V compound layer. Different combinations of the III-V compound layers may result in different response wavelength of the active pixel region. Variations of the combination of the III-V compound layers are discussed in following embodiments.

FIG. 4toFIG. 11are local cross-sectional views of an infrared image sensor component, in accordance with different embodiments of the disclosure. Referring toFIG. 4, an infrared image sensor component400including an active pixel region420′ formed on a semiconductor substrate410, and a transistor430coupled to the active pixel region420′ is provided. The active pixel region420′ is the portion of a III-V compound layer stack420uncovered by the patterns. The III-V compound layer stack420includes a plurality of III-V compound layers422,424, and426, which can be grown by performing a plurality of epitaxially growing processes. The semiconductor substrate410can be a silicon substrate. The III-V compound layers422and426are made of III-V compound having wide energy gap, and the III-V compound layer424is made of III-V compound having narrow energy gap. However, the composition of the III-V compound layers422,426may be the same or different. The III-V compound layer426is formed on and in contact with the semiconductor substrate410. The III-V compound layer424with narrow energy gap is sandwiched between the III-V compound layers422,426with wide energy gap. The thickness of the III-V compound layers422,424, and426may be different.

Referring toFIG. 5, an infrared image sensor component500including an active pixel region520′ formed on a semiconductor substrate510, and a transistor530coupled to the active pixel region520′ is provided. The active pixel region520′ is the portion of a III-V compound layer stack520uncovered by the patterns. The III-V compound layer stack520is a multi-layer structure including a plurality of first III-V compound layers522, and a plurality of second III-V compound layers524, which can be grown by performing a plurality of epitaxially growing processes. The semiconductor substrate510can be a silicon substrate. The first III-V compound layers522are made of III-V compound having wide energy gap, and the second III-V compound layers524are made of III-V compound having narrow energy gap. In some embodiments, the transistor530is formed on the first III-V compound layer522. The number of the first III-V compound layers522can be equal to the number of the second III-V compound layers524. The first III-V compound layers522and the second compound layers524are arranged in pair, and the second III-V compound layers522with narrow energy gap are respectively sandwiched between the adjacent two of the first III-V compound layers524with wide energy gap. The thickness of the first III-V compound layers522and thickness of the second III-V compound layers524may be substantially the same (except for the uppermost layer522).

Referring toFIG. 6, an infrared image sensor component600including an active pixel region620′ formed on a semiconductor substrate610, and a transistor630coupled to the active pixel region620′ is provided. The active pixel region620′ is the portion of a III-V compound layer stack620uncovered by the patterns. The III-V compound layer stack620is a multi-layer structure including a plurality of III-V compound layers621,622,623,624,625, and626. The III-V compound layers621,622,623,624,625, and626are sequentially formed on the semiconductor substrate610by performing a plurality of epitaxially growing processes, in which the III-V compound layer626is in contact with the semiconductor substrate610. The energy gap of the III-V compound layers621,622,623,624,625, and626is sequentially increased, from bottom to top. Namely, the III-V compound layer626has the narrowest energy gap among the layers of the III-V compound layer stack620, and III-V compound layer621has the widest energy gap among the layers of the III-V compound layer stack620. The thickness of the III-V compound layers622,623,624,625, and626can be substantially the same and uniform. Therefore, the III-V compound layer stack620can be regarded as having a gradient increasing energy gap, from bottom to top.

Referring toFIG. 7, an infrared image sensor component700including an active pixel region720′ formed on a semiconductor substrate710, and a transistor730coupled to the active pixel region720′ is provided. The active pixel region720′ is the portion of a III-V compound layer stack720uncovered by the patterns. The III-V compound layer stack720is a multi-layer structure including a plurality of III-V compound layers721,722,723,724,725, and726. The III-V compound layers721,722,723,724,725, and726are sequentially formed on the semiconductor substrate710by performing a plurality of epitaxially growing processes, in which the III-V compound layer726is in contact with the semiconductor substrate710. The energy gap of the III-V compound layers721,722,723,724,725, and726is sequentially decreased, from bottom to top. Namely, the III-V compound layer721has the narrowest energy gap among the layers of the III-V compound layer stack720, and III-V compound layer726has the widest energy gap among the layers of the III-V compound layer stack720. The thickness of the III-V compound layers722,723,724,725, and726can be substantially the same and uniform. Therefore, the III-V compound layer stack720can be regarded as having a gradient decreasing energy gap, from bottom to top.

Referring toFIG. 8, an infrared image sensor component800including an active pixel region820′ formed on a semiconductor substrate810, and a transistor830coupled to the active pixel region820′ is provided. The active pixel region820′ is the portion of a III-V compound layer stack820uncovered by the patterns. The III-V compound layer stack820is a multi-layer structure including a plurality of III-V compound layers821,822,823,824,825,826, and827. The III-V compound layers821,822,823,824,825,826, and827are sequentially formed on the semiconductor substrate810by performing a plurality of epitaxially growing processes, in which the III-V compound layer827is in contact with the semiconductor substrate810. The energy gap of the layers of the III-V compound layer stack820is sequentially decreased, from bottom to middle, and energy gap of the layers of the III-V compound layer stack is sequentially increased, from middle to top. Namely, the III-V compound layer824at the middle of the III-V compound layer stack820may have the narrowest energy gap among the layers of the III-V compound layer stack820. The III-V compound layer821, and827at opposite sides of the III-V compound layer stack820may have the widest energy gap among the layers of the III-V compound layer stack820.

Referring toFIG. 9, an infrared image sensor component900including an active pixel region920′ formed on a semiconductor substrate910, and a transistor930coupled to the active pixel region920′ is provided. The active pixel region920′ is the portion of a III-V compound layer stack920uncovered by the patterns. The III-V compound layer stack920is a multi-layer structure including a first III-V compound layer922and a second III-V compound layer924, in which the second III-V compound layer924is disposed between the first III-V compound layer922and the semiconductor substrate910. The energy gap of the first III-V compound layer922is different from that of the second III-V compound layer924thereby forming a 2 DEG layer therebetween. The thickness of the first III-V compound layer922is thinner than that of the second III-V compound layer924. The energy gap of the first III-V compound layer922is substantially consistent since the energy gap of the second III-V compound layer924is in a gradient distribution. In some embodiment, the energy gap of the second III-V compound layer924is gradually increased from top to bottom. Namely, the portion of the second III-V compound layer924close to the first III-V compound layer922has a smaller energy gap since the portion of the second III-V compound layer924close to the semiconductor substrate910has a larger energy gap.

Referring toFIG. 10, an infrared image sensor component1000including an active pixel region1020′ formed on a semiconductor substrate1010, and a transistor1030coupled to the active pixel region1020′ is provided. The active pixel region1020′ is the portion of a III-V compound layer stack1020uncovered by the patterns. The III-V compound layer stack1020is a multi-layer structure including a first III-V compound layer1022and a second III-V compound layer1024, in which the second III-V compound layer1024is disposed between the first III-V compound layer1022and the semiconductor substrate1010. The energy gap of the first III-V compound layer1022is different from that of the second III-V compound layer1024thereby forming a 2 DEG layer therebetween. The thickness of the first III-V compound layer1022is thinner than that of the second III-V compound layer1024. The energy gap of the first III-V compound layer1022is substantially consistent since the energy gap of the second III-V compound layer1024is in a gradient distribution. In some embodiment, the energy gap of the second III-V compound layer1024is gradually decreased from top to bottom. Namely, the portion of the second III-V compound layer1024close to the first III-V compound layer1022has a larger energy gap since the portion of the second III-V compound layer1024close to the semiconductor substrate1010has a smaller energy gap.

Referring toFIG. 11, an infrared image sensor component1100including an active pixel region1120′ formed on a semiconductor substrate1110, and a transistor1130coupled to the active pixel region1120′ is provided. The active pixel region1120′ is the portion of a III-V compound layer stack1120uncovered by the patterns. The III-V compound layer stack1120is a multi-layer structure including a first III-V compound layer1122and a second III-V compound layer1124, in which the second III-V compound layer1124is disposed between the first III-V compound layer1122and the semiconductor substrate1110. The energy gap of the first III-V compound layer1122is different from that of the second III-V compound layer1124thereby forming a 2 DEG layer therebetween. The thickness of the first III-V compound layer1122is thinner than that of the second III-V compound layer1124. The energy gap of the first III-V compound layer1122is substantially consistent since the energy gap of the second III-V compound layer1124is in a gradient distribution. In some embodiment, the energy gap of the second III-V compound layer1124is gradually decreased from top to middle, and is further gradually increased from middle to bottom. Namely, the portions of the second III-V compound layer1124close to the first III-V compound layer1122and close to the semiconductor substrate1110have a larger energy gap since the middle portion of the second III-V compound layer1124has a smaller energy gap.

The infrared image sensor component includes at least one III-V compound layer on the semiconductor substrate, in which the portion of the III-V compound layer(s) uncovered by the patterns is utilized as active pixel region for detecting the incident infrared ray. The infrared image sensor component includes at least one transistor coupled to the active pixel region, and charge generated by the active pixel region is transmitted to the transistor. The III-V compound material has wider infrared wavelength coverage than the silicon, larger absorption coefficient in the infrared region than the silicon, and higher carrier mobility than the silicon, thus performance of the infrared image sensor component is improved accordingly.

According to some embodiments of the disclosure, an infrared image sensor component includes a semiconductor substrate, an active pixel region disposed on the semiconductor substrate for receiving an infrared ray, and a transistor coupled to the active pixel region, in which the active pixel region is made of III-V compound material.

According to some embodiments of the disclosure, an infrared image sensor component includes a semiconductor substrate, at least one III-V compound layer disposed on the semiconductor substrate, a transistor disposed on the III-V compound layer, and a plurality of patterns disposed above the III-V compound layer. The patterns partially shield the III-V compound layer and the transistor, and a portion of the III-V compound layer exposed from the patterns forms an active pixel region for receiving an infrared ray. The transistor is coupled to the active pixel region.

According to some embodiments of the disclosure, a method of manufacturing an infrared image sensor component includes forming at least one III-V compound layer on a semiconductor substrate; forming a transistor on the III-V compound layer; and forming a plurality of patterns partially shielding the transistor and the III-V compound layer. A portion of the III-V compound layer exposed from the patterns forms an active pixel region for receiving an infrared ray, and the transistor is coupled to the active pixel region.