Assigning nets to wiring planes using zero wire load and signal propagation timing for chip design

Nets are assigned to wiring planes for generating a chip design. A computer is caused to execute a zero wire load timing session for a placed but unbufferred chip design. All nets of the chip design are set to a single wide wiring track without wiring plane assignments. A delta time delay is added to each sink of each of the nets to represent an estimated time of flight (TOF) delay. The nets wiring plane or width type for a particular pin is upgraded to a type having improved TOF characteristics. Each of the nets are compared against new predetermined slack and distance targets and new assigned wiring plane or width type determined to consume additional wiring track resources, and based on results, the upgrade is repeated or a design for session timing state for the nets is output to represent the unbufferred chip design.

BACKGROUND

There are a limited number of wiring tracks available to a chip design. Wiring tracks are a valuable and limited resource in chip designs. Most existing solutions for assigning nets to particular wiring planes and/or widths require that the design already have buffers inserted. The existing methods may also assign nets inappropriately based on distance.

SUMMARY

Embodiments of the invention relate to assigning nets to wiring planes that have better signal propagation properties based upon the net's topology and the zero wire load model timing of the timing paths the net is associated with before the design has buffers added in. One embodiment includes a computer program product for assigning nets to wiring planes for generating a chip design, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to: execute, by the computer, a zero wire load timing session for a placed but unbufferred chip design comprising integrated circuits including a plurality of gates and nets, a unit design or both the integrated circuits and the unit design. All nets of the chip design are set by the computer to a single wide wiring track without wiring plane assignments. The computer adds a delta time delay to each sink of each of the nets to represent an estimated time of flight (TOF) delay based upon the nets assigned wiring plane or width type and distance of a particular sink to a source. The TOF delay is equal to determining (TOF pico second (ps)/millimeter (mm) for wiring plane or width type)*(sink to source distance in mm). The computer upgrades the nets wiring plane or width type for a particular pin to a type having improved TOF characteristics to improve timing upon a determination that the particular pin fails a predetermined slack and distance target, and re-determining the TOF delay based on the upgrade. The computer further compares each of the nets against new predetermined slack and distance targets and new assigned wiring plane or width type determined to consume additional wiring track resources. Based on results of the compare, the computer either repeats the upgrading or outputs a design for session timing state for the nets to represent the unbufferred chip design with the nets assigned to wiring plane or width types for use by a buffering tool to assist in the unbuffered chip design's timing closure and to provide to the buffering tool priority for particular nets assigned to wiring plane or width types that are more difficult to close timing on than other particular nets for improved buffer placement.

DETAILED DESCRIPTION

One or more embodiments assign nets to wiring planes that enjoy better signal propagation properties (i.e., better time of flight (TOF) characteristics) based upon the net's topology and the zero wire load (ZWL) model timing of the timing paths the net is associated with before the design has buffers added in. Overuse or inappropriate assignment of nets to more valuable wiring planes might lead to a chip design to suffer excessive wiring congestion, timing closure troubles and noise integrity issues. One or more embodiments use the least amount of the valuable wiring planes' resources as possible that enjoy better TOF characteristics than what may occur if nets are inappropriately assigned based upon the ZWL of the random logic macro (RLMs).

One or more embodiments provide that each net, before buffering, is assigned to a particular wiring plane and type based on its need from a timing closure standpoint and the nets specific topology. Advantages of one or more embodiments may include: using lesser amounts of the valuable wiring planes resources that enjoy better TOF characteristics than what can occur if nets are inappropriately assigned; quicker turn around time (TAT) for a timing analysis than would occur if a chip design were fully buffered and the design's nets planes and types were assigned in a different fashion; and once the unbuffered nets in the design are assigned planes and widths, a buffering tool gives priority to the nets assigned to the more valuable planes. This leads to better placement for the more timing critical nets right from the start of the buffering process.

One or more embodiments provide that a chip or unit designs zero timing is estimated based upon: the design's ZWL timing model to calculate the “silicon” delay; and each sink of each net is given a TOF delay component based upon its distance from the nets source and an estimated TOF per millimeter characteristics for its assigned wiring plane and/or width type.

A peripheral120or series of peripherals120, e.g., facsimile machines, printers, scanners, hard disk drives, networked and/or local storage units or systems, etc., may be coupled to one or more of the networks104,106,108. It should be noted that databases and/or additional components may be utilized with, or integrated into, any type of network element coupled to the networks104,106,108. In the context of the present description, a network element may refer to any component of a network.

According to some approaches, methods and systems described herein may be implemented with and/or on virtual systems and/or systems, which emulate one or more other systems, such as a UNIX system that emulates an IBM z/OS environment, a UNIX system that virtually hosts a MICROSOFT WINDOWS environment, a MICROSOFT WINDOWS system that emulates an IBM z/OS environment, etc. This virtualization and/or emulation may be implemented through the use of VMWARE software in some embodiments.

FIG. 2shows a representative hardware system200environment associated with a user device116and/or server114ofFIG. 1, in accordance with one embodiment. In one example, a hardware configuration includes a workstation having a central processing unit210, such as a microprocessor, and a number of other units interconnected via a system bus212. The workstation shown inFIG. 2may include a Random Access Memory (RAM)214, Read Only Memory (ROM)216, an I/O adapter218for connecting peripheral devices, such as disk storage units220to the bus212, a user interface adapter222for connecting a keyboard224, a mouse226, a speaker228, a microphone232, and/or other user interface devices, such as a touch screen, a digital camera (not shown), etc., to the bus212, communication adapter234for connecting the workstation to a communication network235(e.g., a data processing network) and a display adapter236for connecting the bus212to a display device238.

In one example, the workstation may have resident thereon an operating system, such as the MICROSOFT WINDOWS Operating System (OS), a MAC OS, a UNIX OS, etc. In one embodiment, the system200employs a POSIX® based file system. It will be appreciated that other examples may also be implemented on platforms and operating systems other than those mentioned. Such other examples may include operating systems written using JAVA, XML, C, and/or C++ language, or other programming languages, along with an object oriented programming methodology. Object oriented programming (OOP), which has become increasingly used to develop complex applications, may also be used.

FIG. 3shows an example flow for a process300for assigning nets to wiring planes for generating a chip design, according to an embodiment. On a typical chip design, the majority of nets are assigned to a default wiring plane and width (e.g., a single width wiring track wire code with no planes assignment). A minority of nets involved with more challenging timing paths do require, for timing closure purposes, the better TOF characteristics of wires (usually wider and and/or thicker than default type wires) found with particular wiring planes and/or widths. Typically nets that use wider or thicker types of wiring segments take up more wiring tracks. Care must be taken not to overload a chip design with too many of these types of wires since there are a limited number of wiring tracks available to a chip design. Over use or inappropriate assignment of nets to the more valuable wiring planes might lead to a chip design to suffer excessive wiring congestion, timing closure trouble and noise integrity issues. In one embodiment, process300uses the least amounts of the valuable wiring planes resources possible that enjoy better TOF characteristics than what can occur if nets are inappropriately assigned based upon the ZWL of the RLMs. Process300also identifies timing paths that would be impossible to solve even with an ideal wire/buffer solution.

In one embodiment, process300may be executed using a computing device, such as a processor, workstation, computer, specialized ASIC, etc. (e.g., CPU210of a workstation,FIG. 2, a computing device, e.g., a user device116,FIG. 1, etc.). Process 1 provides that a ZWL timing session is run on a placed but unbufferred chip (e.g., integrated circuits including millions of gates and nets, etc.) and/or unit design. Process 2 provides that all of the of the chip/unit nets are set to single wide wiring track with no wiring plane assignments (i.e., the default wire type), which is the slowest type of wire type with the worst TOF characteristics and uses the least wiring track resources. Therefore, in process 2, the computing device iterates through each pin and each net in the design assigning TOF delay based on layer assignment.

In one embodiment, in process 3, a delta time delay is added to each sink of every net to represent the estimated TOF delay based upon the nets assigned plane/width type and the distance of the particular sink to the source. In one embodiment, TOF delay=(TOF ps/mm for plane/width type)*(sink to source distance in mm). Therefore, in process 3, the computing device iterates through wiring planes and widths with increasingly better TOF characteristics. In process 4, if the particular pin fails a given slack and distance target the nets plane/width is upgraded to a type that has better TOF characteristics to improve its timing. If the net is upgraded to a different plane/width, its TOF delay is recalculated (i.e., repeat process 3 and the computation of TOF delay). Therefore, in process 4 the computing device iterates through each pin and each net in the design. Decision 1 determines whether a pin fits criteria for being an upgrade candidate. Decision 2 determines whether all of the nets have been checked yet. Decision 3 determines if all of the wiring planes and widths upgrades have been checked.

In one embodiment, in process 5, once all the pins of all the nets have been thru process 4, all the nets are checked against new slack and distance targets and new wiring planes/width assignments that consume more wiring track resources. Then the computing device assigns a net to a given layer and width assignment and recalculates pin timing.

In one embodiment, once process300has iterated thru all the processes 1-5 for all the nets design, the sessions timing state then represents an unbufferred design with the nets assigned to wiring planes advantageous to a buffer tool to aid in the designs timing closure. Additionally, by having a buffer tool give priority to nets assigned to the more costly wiring types (i.e., the nets hardest to close timing on) the process300assures that those buffer circuits receive first choice for a more favorable placement in the design. In one embodiment, a quicker TAT on complex paths are shown in the generated design without waiting for buffering solutions to be completed.

Table 1 shows an example table and order of, slack targets, estimated TOF and wiring planes and widths used by one embodiment that is applied during process 5.

Table 2 shows an example metal stack that a chip design that is referenced in Table 1.

FIG. 4illustrates a block diagram for a process400for assigning nets to wiring planes for generating a chip design, according to one embodiment. In one embodiment, the process400may be implemented using a computing process, a computing program, etc. In one embodiment, process400includes a computer program product for assigning nets to wiring planes for generating a chip design. The computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions executable by a computer (e.g., a user device116,FIG. 1, a workstation in system200,FIG. 2, etc.) to cause the computer to perform process400. In one embodiment, block410includes executing, by the computer, a ZWL timing session for a placed but unbufferred chip design that includes integrated circuits with millions of gates and nets design, a unit design or both the integrated circuits and the unit design. In block420all nets of the chip design are set by the computer to a single wide wiring track without wiring plane assignments. In block430the computer adds a delta time delay to each sink of each of the nets to represent an estimated time of flight (TOF) delay based upon the nets assigned wiring plane or width type and distance of a particular sink to a source. The TOF delay is equal to determining (TOF ps/mm for wiring plane or width type)*(sink to source distance in mm). In block440the computer upgrades the nets wiring plane or width type for a particular pin to a type having improved TOF characteristics to improve timing upon a determination that the particular pin fails a predetermined slack and distance target, and re-determining the TOF delay based on the upgrade. In block450the computer further compares each of the nets against new predetermined slack and distance targets and new assigned wiring plane or width type determined to consume additional wiring track resources. In one embodiment, based on results of the compare, the computer either repeats the upgrading or outputs a design for session timing state for the nets to represent the unbufferred chip design with the nets assigned to wiring plane or width types for use by a buffer tool to assist in the unbuffered chip design timing closure and to provide to the buffer tool priority for particular nets assigned to wiring plane or width types harder to close timing on than other particular nets for improved placement.