Replacement channels

The present disclosure relates to a device and method for strain inducing or high mobility channel replacement in a semiconductor device. The semiconductor device is configured to control current from a source to a drain through a channel region by use of a gate. A strain inducing or high mobility layer produced in the channel region between the source and drain can result in better device performance compared to Si, faster devices, faster data transmission, and is fully compatible with the current semiconductor manufacturing infrastructure.

BACKGROUND

The cost and complexity associated with scaling of semiconductor device sizes according to Moore's law has given rise to new methods to improve semiconductor device characteristics. New gate materials such as Hi-K metal gates to decrease device leakage, finFET devices with increased effective gate area as compared to same-size planar devices, and strain inducing channels for increased charge carrier mobility are a few examples of methods to continue Moore's Law scaling for next generation microprocessor designs.

DETAILED DESCRIPTION

The description herein is made with reference to the drawings, wherein like reference numerals are generally utilized to refer to like elements throughout, and wherein the various structures are not necessarily drawn to scale. In the following description, for purposes of explanation, numerous specific details are set forth in order to facilitate understanding. It may be evident, however, to one of ordinary skill in the art, that one or more aspects described herein may be practiced with a lesser degree of these specific details. In other instances, known structures and devices are shown in block diagram form to facilitate understanding.

FIG. 1illustrates semiconductor devices with strain inducing channels formed by conventional methods, comprising an arrangement100aof two planar field-effect transistors (FETs)102aand102b, as well as an arrangement100bof four fin field-effect transistors (finFETs)104a-104d. Each FET102a-102band finFET104a-104dcomprise three terminals: a source106, a drain108, and a gate110, and are formed on a silicon (Si) substrate112and isolated by shallow trench isolation (STI) channels114filled with a dielectric material (e.g., SiO2). Planar FETs102a-102band finFETs104a-104dtypically comprises a metal-oxide-semiconductor FETs (MOSFETs) wherein a Hi-K dielectric resides between the gate110and a channel region116formed between each source106and drain108to reduce power loss due to gate current leakage into the channel region116.

One factor in determining the performance of a FET is the mobility of charge carriers through the channel region116. To increase the mobility of charge carriers in a FET, a strain inducing channel may be produced. However, strain inducing channels formed by conventional methods are formed early in semiconductor processing, and may be subject to a series of thermal processing steps which can degrade their crystal structure and hence reduce their charge carrier mobility.

Accordingly, the present disclosure relates to a device and method for strain inducing or high mobility channel replacement in a semiconductor device. A sacrificial layer is formed early in the semiconductor device processing. After one or more thermal processing steps are carried out with the sacrificial layer in place, the sacrificial layer is removed to form a recess. A strain inducing or high mobility layer then fills the recess to insure a robust crystal structure with minimal defects. Strain inducing or high mobility channel replacement may result in better device performance compared to conventional techniques for strain inducing channel formation, and is fully compatible with the current semiconductor manufacturing infrastructure.

FIG. 2illustrates some embodiments of strained lattices200which are used in semiconductor devices due to their relatively high charge carrier mobility. The strained lattices200comprise a first lattice202composed of species A204, a second lattice206composed of species B208, and a third lattice210composed of species C212. The periodic spacing of a species within a given lattice is defined as its lattice constant. The first lattice202has a lattice constant x214, the second lattice206has a lattice constant y216, and the third lattice210has a lattice constant z218. Near the interface region222of the first lattice202and the second lattice206a mismatch in lattice constants results in a strain of one or more of the first or second crystal lattices,202and206respectively. In this embodiment, the second lattice206is subject to a compressive strain224resulting a mismatch of its lattice constant y with the lattice constant x214(i.e., y>x results in compressive224strain for the second lattice206). Similarly, the third lattice210is subject to a tensile strain226resulting from a mismatch of its lattice constant z with the lattice constant x214near the interface228(i.e., z<x results in tensile strain226for the third lattice210).

Mechanical strain, thermal effects, and chemical effects are some examples of factors that can result in defects within a lattice. A vacancy230results from a particle of species A204being absent from its expected periodic location. An Interstitial232results from a particle of species A204being in a location other than its expected periodic location. A substitution234results from a particle of species C212residing in a location where a particle of species A204is expected (e.g., a contaminant for a single-species lattice). An edge dislocation236is where an extra half plane of particles is introduced. A stacking fault238occurs when one or more planes of atoms interrupts the normal periodic stacking of particle planes. These defects degrade the crystal structure and hence the charge carrier mobility of these strained lattices. Moreover, as defects accumulate the crystal structure may become so distorted that it becomes amorphous.

To improve the strain within a strain inducing layer when thermal processing steps are used in semiconductor device processing a sacrificial layer may be formed early in the semiconductor device processing. After one or more thermal processing steps are carried out with the sacrificial layer in place, the sacrificial layer is removed to form a recess. A strain inducing or high mobility layer then fills the recess to insure a robust crystal structure with minimal defects.

FIG. 3a-FIG. 3cillustrate some embodiments of forming a p-type metal-oxide semiconductor field transistor (p-MOS) transistor with a partial replacement channel.FIG. 3aillustrates p-MOS300comprising a gate306, which overlies a sacrificial layer318. The gate306comprises a hard mask308, Poly-Silicon gate material (Poly-Si)310, a gate dielectric312, and sidewall spacers314to insure electrical isolation of the gate306from the source302and drain304. The p-MOS300is situated on a Si substrate316(i.e., Si lattice) to which the sacrificial layer of Si or SiGe318has been added (i.e., SiGex where x≧0.2). The sacrificial layer of Si or SiGe318includes sacrificial source and drain regions302,304, which are arranged on opposite edges of gate306, and also includes a sacrificial channel region320aligned under the gate306. The mismatch in lattice constants between the Si substrate316and sacrificial layer of Si or SiGe318results in a compressive strain within the sacrificial channel region320of the p-MOS300along the channel width direction, having the effect of increasing the hole charge carrier322mobility by approximately 1.4-1.8times that of bulk devices (i.e., Si).

The hole charge carrier322mobility, however, will be degraded by thermal processing steps that occur after the formation of the sacrificial layer of Si or SiGe318, due to the distortion its lattice structure of the sacrificial layer of Si or SiGe318.FIG. 3billustrates the p-MOS300wherein the sacrificial layer of Si or SiGe318has been etched away from the sacrificial source region302, the sacrificial drain region304, and the sacrificial channel region320(e.g., a wet chemical etch, a dry chemical etch, or a combination thereof) to form a recess324after the thermal processing steps are complete. At the same time (i.e., as a part of the same etch step) a strained source drain (SSD) etch forms larger etch profile regions326within the recess324. Note that a portion of the sacrificial layer of Si or SiGe318approximately 1-50nm thick remains below the gate306, and shields the gate306from any undesired effects from removing the sacrificial layer of Si or SiGe318(e.g., damage and/or contamination to the gate306).

FIG. 3cillustrates the p-MOS300wherein the recess324has been filled with a single strain inducing or high mobility layer330(i.e., single lattice) comprising SiGex (where x≧0.2) or Ge with a gradient concentration, either doped or undoped, with a cap formed from the sacrificial layer of Si or SiGe318that remains below the gate306and above a replacement channel region332. This partial replacement channel region332separates replacement source and drain regions328,334formed within the strain inducing or high mobility layer330. In some embodiments, the replacement channel region332, replacement source region328and replacement drain region334comprise a single crystal. While formation of a partial replacement channel region332has the benefit of protecting the gate306, it results in less overall strain and hence less hole mobility than a full replacement channel region. Nonetheless, because the partial replacement channel332region comprises a strain induced layer formed after thermal processing, it has an increased induced-strain relative to conventional devices.

A strain inducing channel on an n-type metal-oxide semiconductor field transistor (n-MOS) can be achieved by the same means as described in the embodiments of the p-MOS300wherein a composite layer of strained Si on strained SiGe (e.g., Si/SiGe0.2) fills the recess324instead of the strain inducing or high mobility layer330. The mismatch in lattice constants between the composite layer of strained Si on strained SiGe and the substrate314results in a tensile strain of the n-MOS along the channel width direction, having the effect of increasing the electron charge carrier mobility by approximately 1.25-2 times that of bulk devices.

FIG. 4a-FIG. 4cillustrate some embodiments of forming a p-type metal-oxide semiconductor field transistor (p-MOS) transistor with a full replacement channel region. The formation of a full replacement channel region illustrated for a p-MOS400inFIG. 4a-4cis similar to the formation of the partial replacement channel region described in the embodiments ofFIG. 3a-FIG. 3c. However, for the formation of a full replacement channel region, no portion of the sacrificial layer of Si or SiGe318remains such that the recess324abuts the bottom of the gate dielectric312. The recess324is then filled with a single strain inducing or high mobility layer430(i.e., single lattice) comprising SiGex (where x≧0.2) or Ge with a gradient concentration, and is either doped or undoped. Note that no cap is formed since the sacrificial layer of Si or SiGe318has been completely removed. The strain inducing or high mobility layer430forms the replacement source and drain, regions328,334, and a full replacement channel region432, which results in more overall strain than the partial replacement channel region332of the embodiments ofFIGS. 3A-3C, and hence an increased hole mobility relative to the partial replacement channel region332.

FIG. 5aillustrates some embodiments of forming a partial replacement channel on planar FETs500a. Note that the cross-section shown for this embodiment is rotated 90 degrees from the embodiments ofFIG. 3andFIG. 4such that the channel length direction faces out of the page. The planar FETs500acomprise a gate502a, and Si or SiGex channels504awhich are isolated from one another by a shallow trench isolation oxide (STI OX)506a. Each original channel of Si or SiGe is etched away (e.g., a wet chemical etch, a dry chemical etch, or a combination thereof) to form a recess508a, leaving a portion of the Si or SiGe channel510aapproximately 1-50 nm thick below the gate502a. A strain inducing layer or high mobility layer512aof SiGex (where x≧0.2) or Ge is then re-grown within the recess508a(e.g., epitaxial growth). This method results in the formation of a partial replacement channel on the planar FETs500a.

FIG. 5billustrates some embodiments of forming a partial replacement channel on finFETs500b, which is identical to the embodiments of forming a partial replacement channel on planar FETs500awith the distinction that the Si or SiGex channels504bextend into the gate502bto form “fins”507bthat are wrapped in by the gate502bon three sides. Each Si or SiGex channel504bis etched away to form a recess508bwith a portion of the Si or SiGe channel510bapproximately 1-50 nm thick remaining at the top of the original channel504b. A strain inducing layer or high mobility layer512bof SiGex (where x≧0.2) or Ge is then re-grown within the recess508b. This method results in the formation of a partial replacement channel on the finFETs500b.

FIG. 6aillustrates some embodiments of forming a full replacement channel on planar FETs600a, which comprise a gate602a, and Si or SiGex channels604awhich are isolated from one another by a shallow trench isolation oxide (STI OX)606a. Each original channel of Si or SiGe is etched away to form a recess608asuch that no portion of the Si or SiGe channel604aresides between the recess608aand the gate602a(i.e., the recess abuts the bottom of the gate). A strain inducing layer or high mobility layer610aof SiGex (where x≧0.2) or Ge is then re-grown within the recess608a. This method results in the formation of a full replacement channel on the planar FETs600a.

FIG. 6billustrates some embodiments of forming a full replacement channel on finFETs600b. The distinction between the embodiments of600aand600bis similar to the distinction between the embodiments of500aand500b, wherein the only difference is that the Si or SiGex channels604bextend into the gate602bto form “fins”607bthat are wrapped in by the gate602bon three sides. Each Si or SiGe channel is etched away to form a recess608bwhich abuts the bottom of the gate602b. A strain inducing layer or high mobility layer610bof SiGex (where x≧0.2) or Ge is then re-grown within the recess608bto form a full replacement channel on the finFETs600b.

FIG. 7a-FIG. 7eillustrate some detailed embodiments of forming a channel-last replacement channel on a planar FET700in a Hi-K metal gate last (HKL) flow. In the Hi-K metal gate last flow a dummy poly gate and dummy liner (IL) are formed early in the semiconductor device processing and then replaced with a real gate late in the processing. In contrast, a Hi-K metal gate first (HKF) flow forms the real gate early in the processing.

FIG. 7aillustrates a cross-sectional view of a planar FET700comprising a dummy gate702, a dummy liner (IL)704, a Si or SiGex (where x≧0.2) channel706, a spacer708, and a contact etch stop layer710formed between the dummy gate702and spacer708and an interlayer dielectric (ILD)712.FIG. 7billustrates a cross-sectional view of the planar FET700wherein a chemical-mechanical polish (CMP)714has removed the contact etch stop layer710and ILD712to expose the top of the dummy gate702.FIG. 7cillustrates a cross-sectional view of the planar FET700wherein the dummy gate702and a dummy IL704have been etched away to form a first recess716.FIG. 7dillustrates a cross-sectional view of the planar FET700wherein the Si or SiGex channel706has been etched away to form a second recess718.FIG. 7eillustrates a cross-sectional view of the planar FET700wherein a strain inducing layer or high mobility layer720of SiGex (where x≧0.2) or Ge is re-grown within the second recess718to form a channel-last replacement channel.

FIG. 8a-FIG. 8dillustrate some embodiments of forming a channel-last replacement channel on planar FETs800in a Hi-K metal gate last (HKL) flow.FIG. 8aillustrates a cross-sectional view of the planar FETs800, which comprise a dummy gate802, and Si or SiGex channels804which are isolated from one another by a shallow trench isolation oxide (STI OX)806.FIG. 8billustrates a cross-sectional view of the planar FET800wherein the dummy gate802has been etched away.FIG. 8cillustrates a cross-sectional view of the planar FET800wherein each original Si or SiGe channel804is etched away to form a recess808.FIG. 8dillustrates a cross-sectional view of the planar FET800wherein a strain inducing layer or high mobility layer810of SiGex (where x≧0.2) or Ge is then re-grown within the recess808to form a channel-last replacement channel.

FIG. 9a-FIG. 9dillustrate some embodiments of forming a channel-last replacement channel on finFETs900in a Hi-K metal gate last (HKL) flow. The distinction between the embodiments ofFIG. 8a-FIG. 8dandFIG. 9a-FIG. 9dis similar to the distinction between the previous embodiments of600aand600bwherein the only difference is that the Si or SiGex channels904extend into the gate dummy gate902to form “fins”908as illustrated in a cross-sectional view inFIG. 9a.FIG. 9billustrates a cross-sectional view of the finFET900wherein the dummy gate902has been etched away to expose the Si or SiGex “fins”908.FIG. 9cillustrates a cross-sectional view of the planar FET900wherein each original Si or SiGe channel904is etched away to form a recess910.FIG. 9dillustrates a cross-sectional view of the planar FET900wherein a strain inducing layer or high mobility layer912of SiGex (where x≧0.2) or Ge is then re-grown within the recess910to form a channel-last replacement channel.

FIG. 10a-FIG. 10eillustrate cross-sectional views of some embodiments of typical SSD etch profiles.FIG. 10aillustrates a cross-sectional view of some embodiments1000aof a sigma-shape etch profile1002afor a strained source drain (SSD) etch.FIG. 10billustrates a cross-sectional view of some embodiments1000bof a sigma-shape etch profile1002bfor a strained source drain (SSD) etch.FIG. 10cillustrates a cross-sectional view of some embodiments1000cof an anisotropic etch profile1002cfor a strained source drain (SSD) etch.FIG. 10dillustrates a cross-sectional view of some embodiments1000dof an isotropic etch profile1002dfor a strained source drain (SSD) etch.FIG. 10eillustrates a cross-sectional view of some embodiments1000eof a triangular etch profile1002efor a strained source drain (SSD) etch.

FIG. 11illustrates a comparison of some embodiments of a p-MOS1100aformed by conventional strain inducing channel methods vs. a p-MOS1100bformed by a full replacement channel method. The p-MOS1100aformed by a conventional methods comprises a source1102aand drain1104acomprising first and second strained EPI layers of SiGe, respectively. The p-MOS1100afurther comprises gate1106a, and a third strained layer of SiGe1108that forms a channel region1110a. A first boundary1112aseparates the first strained EPI layer of SiGe of the source1102afrom the third strained layer of SiGe1108. A second boundary1114aseparates the second strained EPI layer of SiGe of the drain1104afrom the third strained layer of SiGe1108. The shape of the first and second boundaries1112aand1114ais determined by the type of strained source drain (SSD) etch used to form the source1102aand drain1104a, and may comprise a sigma-shape profile (shown), an anisotropic etch profile, or an isotropic etch profile. The p-MOS1100balso comprises a source1102b, a drain1104b, and a gate1106b. However, the p-MOS1100bcomprises only a single layer of SiGe1108b(i.e., single lattice) that forms the source1102b, drain1104b, as well as a full replacement channel1110b.

FIG. 12illustrates a flow diagram of some embodiments of a conventional method1200for manufacturing a strain inducing or high mobility channel. Note that the method1200is applicable in both the Hi-K metal gate last (HKL) flow as well as the Hi-K metal gate first (HKF) flow. While method1200is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

At step1202a substrate is provided. The substrate may comprise a 300 mm or 450 mm crystalline wafer comprising silicon that has been doped with boron, phosphorus, arsenic, or antimony.

At step1204an active area is formed, which may comprise doping of the substrate.

At step1206a strain or high mobility layer is formed in a channel region within the active area.

At step1208a gate is formed. The gate may comprise a layer of Poly-Silicon above a layer of gate dielectric, and subjects the substrate to thermal processing (Hi T).

At step1210a lightly-doped drain (LDD) is formed to improve charge carrier movement from the source to the drain. Formation of the LDD subjects the substrate to thermal processing (Hi T). The thermal processing may comprise a plurality of high temperature anneals, a plurality of high temperature process steps, or a combination thereof.

At step1212a source and drain epi layer is formed. The source and drain epi layer may comprise a layer of epitaxial SiGe for a p-MOS (e.g., SiGe0.3), or a composite layer of epitaxial Si on layer of epitaxial SiGe for an n-MOS (e.g., Si/SiGe0.2). Formation of the source and drain epi layer subjects the substrate to thermal processing (Hi T). The thermal processing may comprise a plurality of high temperature anneals, a plurality of high temperature process steps, or a combination thereof.

At step1214a source and drain implant and anneal is performed. The source and drain implant may comprise an ion implantation of arsenic to improve threshold voltage, and subjects the substrate to thermal cycling (Hi T). The thermal processing may comprise a plurality of high temperature anneals, a plurality of high temperature process steps, or a combination thereof.

FIG. 13illustrates a flow diagram of some embodiments of a method1300for manufacturing a replacement channel that can be used for both a partial replacement channel and a full replacement channel. Note that the method1300is applicable in both the Hi-K metal gate last (HKL) flow as well as the Hi-K metal gate first (HKF) flow. While method1300is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

At step1302a substrate is provided. The substrate may comprise a 300 mm or 450 mm crystalline wafer comprising silicon that has been doped with boron, phosphorus, arsenic, or antimony.

At step1304an active area is formed, which may comprise doping of the substrate.

At step1306a sacrificial layer is formed in a channel region within the active area. The sacrificial layer may comprise a layer of epitaxial SiGe for a p-MOS (e.g., SiGe0.3), or a composite layer of epitaxial Si on layer of epitaxial SiGe for an n-MOS (e.g., Si/SiGe0.2).

At step1308a gate dielectric is formed, which may comprise SiO2or a Hi-K dielectric to reduce power loss due to gate current leakage into the channel region.

At step1310a gate material is formed. The gate may comprise a layer of Poly-Silicon or metal above the layer of gate dielectric and subjects the substrate to thermal cycling (Hi T).

At step1312a gate spacer is formed, which may comprise a dielectric sidewall spacer to insure electrical isolation of the gate poly.

At step1314a lightly-doped drain (LDD) is formed to improve charge carrier movement within the channel region.

At step1316a LDD anneal is performed to further improve charge carrier movement through the channel region. At the same time a dummy spacer is formed. Both processes subject the substrate to thermal cycling (Hi T).

At step1318the sacrificial layer is removed to form a recess by a wet chemical etch, a dry chemical etch, or a combination thereof, that utilizes an isotropic etch profile.

At step1320a strain inducing layer or high mobility layer is formed in the recess. The strain inducing layer or high mobility layer may comprise a layer of epitaxial SiGe for a p-MOS (e.g., SiGe0.3), a gradient concentration layer (e.g., Ge), a doped layer (e.g., Boron or Phosphorus), a composite layer of epitaxial Si on layer of epitaxial SiGe for an n-MOS (e.g., Si/SiGe0.2), or any combination thereof.

FIG. 14illustrates a flow diagram of some embodiments of a method1400for manufacturing a channel-last replacement channel. Note that the method1400is applicable only in the Hi-K metal gate last (HKL) flow. While method1400is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

At step1402a substrate is provided. The substrate may comprise a 300 mm or 450 mm crystalline wafer comprising silicon that has been doped with boron, phosphorus, arsenic, or antimony.

At step1404an active area is formed, which may comprise doping of the substrate.

At step1406a sacrificial layer is formed in a channel region within the active area. The sacrificial layer may comprise a layer of epitaxial SiGe for a p-MOS (e.g., SiGe0.3), or a composite layer of epitaxial Si on layer of epitaxial SiGe for an n-MOS (e.g., Si/SiGe0.2).

At step1408a dummy gate liner (IL) is formed.

At step1410a dummy gate material is formed. The dummy gate may comprise a layer of dummy oxide beneath a dummy gate material (e.g., Poly-Silicon). The dummy gate is capped by a hard mask. The formation of the dummy gate subjects the substrate to thermal cycling (Hi T).

At step1412a gate spacer is formed, which may comprise a dielectric sidewall spacer to insure electrical isolation of the gate poly.

At step1414a lightly-doped drain (LDD) is formed to improve charge carrier movement within the channel region.

At step1416a LDD anneal is performed to further improve charge carrier movement within the channel region. The LDD anneal subjects the substrate to thermal cycling (Hi T).

At step1418a source and drain epi layer is formed. The source and drain epi layer may comprise a layer of epitaxial SiGe for a p-MOS (e.g., SiGe0.3), or a composite layer of epitaxial Si on layer of epitaxial SiGe for an n-MOS (e.g., Si/SiGe0.2).

At step1420a source and drain implant and anneal is performed. The source and drain implant may comprise an ion implantation of arsenic to improve threshold voltage. The anneal subjects the substrate to thermal cycling (Hi T).

At step1422the hard mask is removed from above the gate, which may comprise a wet chemical etch, a dry chemical etch, or a combination thereof.

At step1424a contact etch stop layer is added above the gate, spacer, source, and drain. An interlayer dielectric (ILD) is added above the etch stop layer.

At step1426the contact etch stop layer and ILD are subjected to a chemical-mechanical polish (CMP) to expose the top of the dummy gate material.

At step1428the dummy gate material is removed, which may comprise a wet chemical etch, a dry chemical etch, or a combination thereof.

At step1430the dummy oxide is removed, which may comprise a wet chemical etch, a dry chemical etch, or a combination thereof.

At step1432the channel region is removed to form a recess. The removal of the channel region may comprise wet chemical etch, a dry chemical etch, or a combination thereof, that utilizes an isotropic etch profile, and anisotropic etch profile, a sigma-shape etch profile, or a triangular etch profile.

At step1434a strain inducing layer or high mobility layer is formed in the recess. The second strain inducing layer or high mobility layer may comprise a layer of epitaxial SiGe for a p-MOS (e.g., SiGe0.3), a gradient concentration layer (e.g., Ge), a doped layer (e.g., Boron or Phosphorus), a composite layer of epitaxial Si on layer of epitaxial SiGe for an n-MOS (e.g., Si/SiGe0.2), or any combination thereof.

FIG. 15a-FIG. 15fillustrate cross-sectional views of some embodiments of channel-last replacement channel profiles.FIG. 15aillustrates a cross-sectional view of some embodiments1500aof a sigma-shape profile1502afor a channel-last replacement channel.FIG. 15billustrates a cross-sectional view of some embodiments1500bof a sigma-shape profile1502bfor a channel-last replacement channel.FIG. 15cillustrates a cross-sectional view of some embodiments1500cof an anisotropic profile1502cfor a channel-last replacement channel.FIG. 15dillustrates a cross-sectional view of some embodiments1500dof an isotropic profile1502dfor a channel-last replacement channel.FIG. 15eillustrates a cross-sectional view of some embodiments1500eof a triangular profile1502efor a channel-last replacement channel.FIG. 15fillustrates a cross-sectional view of some embodiments1500fof a trapezoidal profile1502ffor a channel-last replacement channel.

It will also be appreciated that equivalent alterations and/or modifications may occur to one of ordinary skill in the art based upon a reading and/or understanding of the specification and annexed drawings. The disclosure herein includes all such modifications and alterations and is generally not intended to be limited thereby. In addition, while a particular feature or aspect may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features and/or aspects of other implementations as may be desired. Furthermore, to the extent that the terms “includes”, “having”, “has”, “with”, and/or variants thereof are used herein; such terms are intended to be inclusive in meaning—like “comprising.” Also, “exemplary” is merely meant to mean an example, rather than the best. It is also to be appreciated that features, layers and/or elements depicted herein are illustrated with particular dimensions and/or orientations relative to one another for purposes of simplicity and ease of understanding, and that the actual dimensions and/or orientations may differ substantially from that illustrated herein.

Therefore, the present disclosure relates to a device and method for strain inducing or high mobility channel replacement in a semiconductor device. The semiconductor device is configured to control current from a source to a drain through a channel region by use of a gate. A sacrificial layer is formed early in the semiconductor device processing. After one or more thermal processing steps are carried out with the sacrificial layer in place, the sacrificial layer is removed to form a recess. A strain inducing or high mobility layer then fills the recess to insure a robust crystal structure with minimal defects. Strain inducing or high mobility channel replacement may result in better device performance compared to conventional techniques for strain inducing channel formation, and is fully compatible with the current semiconductor manufacturing infrastructure.

In some embodiments, the strain inducing or high mobility channel replacement comprises a partial replacement channel on a field effect transistor (FET), wherein a sacrificial layer forming a source, drain, and channel region are removed after a series of thermal processing steps to form a recess. The recess is then with a strain inducing or high mobility layer. These embodiments comprise a partially removing the sacrificial layer such that a portion of the sacrificial layer remains immediately below the gate. This results in a partial replacement channel that is a combination of the sacrificial layer and the strain inducing or high mobility layer.

In some embodiments, the strain inducing channel replacement comprises a full replacement channel on a field effect transistor (FET), wherein a sacrificial layer forming a source, drain, and channel region are removed after a series of thermal processing steps to form a recess. The recess is then with a strain inducing or high mobility layer. These embodiments comprise a fully removing the sacrificial layer such that none of the sacrificial layer remains above the source, drain, and channel region. This results in a full replacement channel comprising only the strain inducing or high mobility layer.

In some embodiments the present disclosure relates to a method for strain inducing or high mobility channel replacement comprising partially replacing a channel on a field effect transistor (FET), wherein a sacrificial layer forms a source, drain, and channel region. After a series of thermal processing steps are performed, the sacrificial layer is removed to form a recess. The recess is then filled with a strain inducing or high mobility layer. In the method of these embodiments the sacrificial layer is partially removed such that a portion of the sacrificial layer remains immediately below the gate. The removed portion of the sacrificial layer is then replaced with a strain inducing or high mobility layer such that the replacement channel is a combination of the sacrificial layer and the strain inducing or high mobility layer.

In some embodiments the present disclosure relates to a method for strain inducing channel replacement comprising fully replacing a channel on a field effect transistor (FET), wherein a sacrificial layer forms a source, drain, and channel region. After a series of thermal processing steps are performed, the sacrificial layer is removed to form a recess. The recess is then filled with a strain inducing or high mobility layer. In the method of these embodiments the sacrificial layer is fully removed such that none of the sacrificial layer remains above the source, drain, and channel region. The removed sacrificial layer is then replaced with a strain inducing or high mobility layer such that the replacement channel comprises only the strain inducing or high mobility layer.