Multicore processor system, communication control method, and communication computer product

A multicore processor system is configured to cause among multiple cores, a second core to acquire from a first core that executes a first process, an execution request for a second process and a remaining period from a time of execution of the execution request until an estimated time of completion of the first process; and give notification of a result of the second process from the second core to the first core after an estimated completion time of the first process obtained by adding the remaining period to a start time of the second process.

FIELD

The embodiments discussed herein are related to a multicore processor system, a communication control method, and a computer product that control communication among cores.

BACKGROUND

In one conventional form of parallel processing in a multicore processor, one process is defined as a parent process such that a core executing the parent process causes another core to asynchronously execute a child process. The core executing the child process notifies the core executing the parent process of a result of the child process when completing the process, and the core executing the parent process uses the result to continue the process. Since the communication between parent and child is limited to the timing of activation and termination of the child, such a form of parallel processing is suitable for a multicore processor system having no coherency mechanism for caches between cores and a sparsely-connected multicore processor such as that without a shared memory.

When one core executes only one parent process at a time while the other cores execute only child processes instructed from the parent process, the other cores can be controlled from the parent process. This operation is suitable for implementing the parallel processing in an asymmetric multicore processor that is a multicore processor with processors having different capacities and a multicore processor system not equipped with an OS compatible with multicore processors. Particularly, in the field of embedded devices, since multiple processes executing parallel processing are still rarely activated at the same time and can be implemented with simple hardware, this form of parallel processing requiring no OS compatible with multicore processors is extremely suitable.

A multicore processor can efficiently be operated by predicting an estimated time for completing a process and utilizing the estimated time in a method of controlling the other cores described above. For example, a technique is disclosed that collects predicted times of termination for all the tasks from other cores so as to determine a core to which a process is allocated based on the collected predicted times (see. e.g., Japanese Laid-Open Patent Publication No. H9-160890).

In another technique utilizing an estimated time, for example, a delay of hardware or software is predicted in a system requiring a real-time property and a timer is set in consideration of the predicted delay time. A technique is disclosed that enables packet transmission within a processing request time by transmitting a packet when an interrupt is generated by the timer taking the delay time in consideration (see. e.g., Japanese Laid-Open Patent Publication No. 2001-156842).

However, in the conventional techniques described above, a core completing a child process notifies a core executing a parent process of the completion of the child process or the result of the child process through inter-core communication. The notified core executing the parent process interrupts the parent process to execute a process corresponding to an interrupt, a reception process for the notification, and a process to return to the parent process, etc. Consequently, a problem of an overhead generated by the interruption and restart of processing arises. Since a given process intervenes during another process, the contents of a cache memory are rewritten and changed to contents of given process and the cache hit rate decreases at the time of return to the parent process, resulting in a problem of reduced processing efficiency.

If the number of cores increases and more child processes are executed, the problems described above become more prominent when the frequency of communication increases in proportion to the number of the child processes. As the number of child processes increases, the parent process is frequently blocked by communication from the child processes, resulting in a problem reduced processing efficiency of the core executing the parent process.

SUMMARY

According to an aspect of an embodiment, a multicore processor system is configured to cause among multiple cores, a second core to acquire from a first core that executes a first process, an execution request for a second process and a remaining period from a time of execution of the execution request until an estimated time of completion of the first process; and give notification of a result of the second process from the second core to the first core after an estimated completion time of the first process obtained by adding the remaining period to a start time of the second process.

DESCRIPTION OF EMBODIMENTS

Preferred embodiments of a multicore processor system, a communication control method, and a communication control program will be explained in detail with reference to the accompanying drawings.

FIG. 1is a block diagram of a hardware configuration of a multicore processor system according to a first and a second embodiment. As depicted inFIG. 1, a multicore processor system100includes multiple central processing units (CPUs)101, read-only memory (ROM)102, random access memory (RAM)103, flash ROM104, a flash ROM controller105, and flash ROM106. The multicore process system100includes a display107, an interface (I/F)108, and a keyboard109, as input/output devices for the user and other devices. The components of the multicore system100are respectively connected by a bus110.

The CPUs101govern overall control of the multicore processor system100. The CPUs101refer to CPUs that are single core processors connected in parallel. The CPUs101include CPUs #0to #3respectively having dedicated cache memory. Further, the multicore processor system100is a system of computers that include processors equipped with multiple cores. Provided that multiple cores are provided, implementation may be by a single processor equipped with multiple cores or a group of single-core processors in parallel. In the present embodiments, description will be given taking an example where the CPUs are single-core processors connected in parallel.

The ROM102stores therein programs such as a boot program. The RAM103is used as a work area of the CPUs101. The flash ROM104stores system software such as an operating system (OS), and application software. For example, when the OS is updated, the multicore processor system100receives a new OS via the I/F108and updates the old OS that is stored in the flash ROM104, with the received new OS.

The flash ROM controller105, under the control of the CPUs101, controls the reading and writing of data with respect to the flash ROM106. The flash ROM106stores therein data written under control of the flash ROM controller105. Examples of the data include image data and video data received by the user of the multicore processor system100through the I/F108. A memory card, SD card and the like may be adopted as the flash ROM106.

The display107displays, for example, data such as text, images, functional information, etc., in addition to a cursor, icons, and/or tool boxes. A thin-film-transistor (TFT) liquid crystal display and the like may be employed as the display107.

The I/F108is connected to a network111such as a local area network (LAN), a wide area network (WAN), and the Internet through a communication line and is connected to other apparatuses through the network111. The I/F108administers an internal interface with the network111and controls the input and output of data with respect to external apparatuses. For example, a modem or a LAN adaptor may be employed as the I/F108.

The keyboard109includes, for example, keys for inputting letters, numerals, and various instructions and performs the input of data. Alternatively, a touch-panel-type input pad or numeric keypad, etc. may be adopted.

Function of the multicore processor system100according to the first embodiment will be described.FIG. 2is a functional diagram of the multicore processor system100according to the first embodiment. The multicore processor system100includes a notifying unit202, an acquiring unit203, a calculating unit204, a detecting unit205, a notifying unit206, and an acquiring unit207. The functions (the notifying unit202to the acquiring unit207) acting as a control unit are implemented by the CPUs #0and #1executing programs stored in storage devices. The storage devices are, for example, the ROM102, the RAM103, the flash ROM104, and the flash ROM106depicted inFIG. 1. Alternatively, programs may be executed via the I/F108by another CPU to implement the functions.

InFIG. 2, the notifying unit202and the acquiring unit207are included as functions of the CPU #0and the acquiring unit203to the notifying unit206are included as functions of the CPU #1. The CPU #0is assumed to execute a given process defined as a parent process while the CPU #1executes a child process called from the parent process. Therefore, if the CPU #1executes the parent process and the CPU #0executes the child process, the notifying unit202and the acquiring unit207may be included as functions of the CPU #1and the acquiring unit203to the notifying unit206may be included as functions of the CPU #0.

A process in this embodiment may be a thread itself that is an executable unit of a program, may be one function in a thread, or may be a portion of a function. In the case of a portion of a function, for example, a process may refer to a code portion repeated until a given condition is satisfied.

The multicore processor system100can access a profile table201stored in the RAM103etc. The profile table201stores an estimated time for completing a process acquired by profiling, etc. Details of the profile table201will be described hereinafter with reference toFIG. 6.

The notifying unit202has a function of causing among multiple cores, a first core executing a first process to notify a second core of an execution request for a second process and a remaining period from the time of execution of the execution request to the estimated time of completion of the first process. For example, the first process is a parent process and the second process is a child process. The notifying unit202causes the CPU #0executing the parent process to notify the CPU #1of an execution request for the child process and a remaining period A1from the time of the execution request until the completion of the parent process. The contents of the notification may be stored in a register, a cache memory, etc., of the CPU #0.

The acquiring unit203has a function of causing the second core different from the first core to acquire from the first core, the execution request for the second process and the remaining period from the time of execution of the execution request until the estimated time of completion of the first process. For example, the acquiring unit203causes the CPU #1to acquire from the CPU #0, an execution request for the child process and the remaining period A1from the time of the execution request until the completion of the parent process. The acquired contents are stored in a register, a cache memory, etc., of the CPU #1.

The calculating unit204has a function of calculating a waiting period by subtracting the period consumed for completing the second process from the remaining period, if the second core completes the second process before the estimated time of completion of the first process. For example, if the CPU #1completes the child process before the estimated time of completion of the parent process, the calculating unit204calculates a waiting period (A1−C1) by subtracting a period C1consumed for completing the child process from the remaining period A1. The calculated value is stored in a register, cache memory, etc., of the CPU #1.

The detecting unit205has a function of causing the second core to detect that a waiting period calculated by the calculating unit204has elapsed since the time at the point of calculation by the calculating unit204. For example, the detecting unit205causes the CPU #1to detect that the waiting period (A1−C1) has elapsed since the calculation of the waiting period of the CPU #1. The method of detection may utilize a timer that is a function of the OS or a counter that counts the clock pulses of the CPU #1etc. This embodiment utilizes a timer that is a function of the OS, sets a calculated waiting period in the timer and detects the elapse of the waiting period by the expiration of the timer. Information indicative of the detection is stored in the register, the cache memory, etc., of the CPU #1.

The notifying unit206has a function of giving notification of a result of the second process from the second core to the first core after an estimated completion time of the first process, obtained by adding the remaining period to the start time of the second process obtained by the acquiring unit203. When the detecting unit205detects that the waiting period has elapsed, the notifying unit206may give notification from the second core to the first core. For example, the notifying unit206causes the CPU #1to notify the CPU #0of the result of the child process after the estimated completion time of the first process, obtained by adding the remaining period A1to the time of start of the child process. The contents of the notification may be stored in the register, the cache memory, etc. of the CPU #1.

The acquiring unit207has a function of acquiring a result reported by the notifying unit206. For example, the acquiring unit207causes the CPU #0to acquire a result of the child process, reported by the CPU #1. The acquired contents are stored in a register, cache memory, etc. of the CPU #0.

FIG. 3is an explanatory view of an operation pattern of a process between a parent and child, capable of efficiently utilizing cache memory according to the first embodiment. In the example depicted inFIG. 3, the CPU #0executes a parent process at time t0and the CPUs #1to #3execute child processes1to3in response to execution requests from the parent process. For example, the CPU #1executes the child process1at time t1; the CPU #2executes the child process2at time t2; and the CPU #3executes the child process3at time t3.

InFIG. 3, it is assumed that the CPU #1and the CPU #2complete the processes before time t4when the parent process starts waiting. The CPU #1and the CPU #2wait until time t4when the parent process starts waiting, and notify the CPU #0of the results of the child process1and the child process2at time t4. The notified CPU #0executes interrupt processes with respect to the CPU #1and the CPU #2together from time t4to time t5, executes reception processes from time t5to time t6to receive the results of the child process1and the child process2, and executes a return process from time t6to time t7. Since the point of time t8when the child process3is completed is after time t4, the CPU #3executing the child process3notifies the CPU#0of the result of the child process3without waiting.

As described, if the child process is completed while the CPU #0is executing the parent process between time t0and time t4, the CPU executing the child process waits because the parent process is still under execution, whereby the contents of the cache memory saving the state of the parent process under execution by the CPU #0can be prevented from being rewritten by an interrupt process and the results of a child process. Since the interrupt processes are executed together at the end of the parent process, the number of interrupts can be reduced.

FIG. 4is an explanatory view of processes executed at the time of design and at the time of execution for controlling the timing of inter-core communication according to the first embodiment.FIG. 4depicts processes at the time of design and processes at the time of execution required for implementing the operation depicted inFIG. 3. A process group denoted by reference numeral401represents processes403to406executed at the time of design and execution, and an explanatory view denoted by reference numeral402depicts details of the processes corresponding to the processes403to406. The processes executed at the time of design include the process403and the process404and the processes executed at the time of execution include the process405and the process406.

In the process403, a profiler or a designer determines the pattern of communication operation between the parent and child. For example, if a given process calls a process, the profiler regards the former process as a parent process and the latter process as a child process. In the explanatory view denoted by reference numeral402, a process executed by the CPU #0is regarded as the parent process and a process executed by the CPU #1is regarded as the child process. In the process404, the profiler acquires an estimated period (A) for completing the parent process, based on a result of operation in a simulation, etc.

At the time of execution, in the process405, when the CPU executing the parent process makes an execution request for a child process, the CPU executing the child process is notified of the estimated period (A) for completing the parent process. In the explanatory view denoted by reference numeral402, the CPU #0notifies the CPU #1of the execution request for the child process1and the estimated period (A) for completing the parent process through a notification407. Subsequently, in the process406, the CPU executing the child process selects the timing of the completion of the parent process to notify the CPU executing the parent process of a result of the child process. In the explanatory view denoted by reference numeral402, the CPU #1notifies the CPU #0of a result of the child process1through a notification408.

FIG. 5is an explanatory view of an execution example of a process between the parent and child when the timing of the inter-core communication is controlled according to the first embodiment.FIG. 5depicts an execution example of a process between the parent and child when the timing of the inter-core communication is controlled by executing the processes at the time of design inFIG. 4. At time t0, the CPU #0activates the parent process and at time t1, the CPU #0notifies the CPU #1of an execution request for the child process1and the remaining period A1from time t1until time t6when the parent process is estimated to be completed. Subsequently, at time t2, the CPU #0notifies the CPU #3of an execution request for the child process3to the CPU #3and the remaining period A3from time t2until the time t6when the parent process is estimated to be completed. Subsequently, at time t3, the CPU #0notifies the CPU #2of an execution request for the child process2to the CPU #2and the remaining period A2from time t3until the time t6when the parent process is estimated to be completed.

The CPU #1acquires the notification at time t1and executes the child process1. The CPU #2executes the child process2at time t3and the CPU #3executes the child process3at time t2. At time t4, the CPU #1completes the child process1. Since at time t4, the remaining period A1is greater than a period C1(period consumed for the child process1) and the CPU #0has not yet completed the parent process, the CPU #1calculates the waiting period A1−C1by subtracting C1from A1and sets the waiting period A1−C1in a timer. After the setting, the CPU #1sets a thread executing the child process1in a sleep state until the timer expires.

Similarly, at time t5, the CPU #2completes the child process2. Since at time t5, the remaining period A2is greater than a period C2(period consumed for the child process2) and the CPU #0has not yet completed the parent process, the CPU #2calculates a waiting period A2−C2by subtracting C2from A2and sets the waiting period A2−C2in a timer. After the setting, the CPU #2sets a relevant thread in the sleep state until the timer expires.

When the timers of the CPUs #1and #2expire at time6, the CPUs #1and #2reactivate the threads from the sleep state and notify the CPU #0executing the parent process of a result of the child process1and a result of the child process2, respectively. The CPU #0executes interrupt processes with respect to the CPU #1and the CPU #2together from time t6to time t7, executes reception processes from time t7to time t8to receive the results of the child process1and the child process2, and executes a return process from time t8to time t9. After time t9, the CPU #0executes no particular process and therefore enters a waiting state.

At time t10, the CPU #3completes the child process3. Since at time t10, the remaining period A3is less than or equal to a period C3(period consumed for the child process3) and the CPU #0has completed the parent process, the CPU #3immediately notifies the CPU #0of a result of the child process3. The notified CPU #0executes an interrupt process with respect to the CPU #3from time t10to time t11, executes a reception process from time t11to time t12to receive the result of the child process3, and executes a return process from time t12to time t13. The CPU #0receiving the notifications from the CPUs #1to #3executes from time t13to time t14, a process that uses the results of the child processes1to3.

FIG. 6is an explanatory view of an example of storage contents of the profile table201. The profile table201has four fields including a parent process name, estimated period (A) for completing a parent process, a child process name, and an estimated period (B) for a process that uses a child process result.

The field of parent process name stores a function name of a parent process, or an address storing actual code of the function. The field of estimated period for completing a parent process stores an estimated period for completing a parent process measured by a profiler, etc. The field of child process name stores a child process corresponding to the parent process stored in the field of parent process name. The field of estimated period (B) for a process that uses a child process result stores an estimated period for completing a process that uses a child process result measured by a profiler, etc. The estimated period for a process that uses a child process result is used in the multicore processor system100in the second embodiment described hereinafter.

For example, it is assumed that the parent process is a function “parse_html( )” analyzing Hyper Text Markup Language (HTML) documents as a portion of processes of a web browser that is software executed by the multicore processor system100. The web browser is executed in a simulation to measure the period consumed for “parse_html( )” with a profiler, etc. In the example ofFIG. 6, since 20 [msec] is obtained, a designer, etc. stores 20 [msec] as the estimated period (A) for completing a parent process.

If an image is present in an HTML document, the “parse_html( )” function calls a corresponding function as a child process. For example, if a Joint Photographic Experts Group (JPEG) image is present, the “parse_html( )” function calls a “decode_jpeg( )” function as a child process. If a Portable Network Graphics (PNG) image is present, the “parse_html( )” function calls a “decode_png( )” function as a child process. The functions called from the parent process in this way are registered in the field of child process name.

After completion, the “decode_jpeg( )” function and the “decode_png( )” function defined as the child processes notify the “parse_html( )” function defined as the parent process, of a storage address of the image and a size of the image, for example. The notified “parse_html( )” function executes a process of incorporating the storage address of the image and the size of the image into the analysis result of the HTML document. If this incorporating process consumes 2 [msec] at the time of the simulation, the designer, etc. stores 2 [msec] as the estimated period (B) for a process that uses a child process result.

FIG. 7is a flowchart of a process between a parent and child when the timing of inter-core communication is controlled according to the first embodiment. In the process depicted inFIG. 7, the CPU #0executes a parent process and the CPUs #1to #3execute child processes. For simplicity of description, it is assumed that the CPU #1executes a child process in this description.

The CPU #0executes the parent process (step S701). When a process calling a child process occurs during the execution of the parent process, the CPU #0adds an estimated completion period A of the parent process to the parameters of the child process (step S702). After the addition, the CPU #0notifies the CPU #1of an execution request for the child process (step S703).

The CPU #1acquires the execution request for the child process and executes the child process (step S704). After the completion of the child process, the CPU #1acquires a process period C (period consumed to complete the child process) (step S705). After the acquisition, the CPU #1determines whether the estimated period A added to the parameters is greater than the process period C of the child process (step S706).

If the estimated period A is greater than the process period C of the child process (step S706: YES), the CPU #1sets the timer such that the thread is recovered from the sleep state after (the estimated period A−the process period C of the child process) (step S707) and sets the thread in the sleep state (step S708). After recovery from the sleep state consequent to the process at step S708or if the estimated period A is less than or equal to the process period C of the child process (step S706: NO), the CPU #1notifies the CPU #0of the result of the child process (step S709) and is terminated. The notified CPU #0executes a process that uses the result of the child process (step S710) and completes the process.

As described, according to the multicore processor system, the communication control method, and the communication control program, a second core acquires an estimated period for completing a first process by a first core and an execution request for a second process; and notifies the core of the result of the second process after the estimated period has elapsed. As a result, since the result of the second process is not received while the first core is executing the first process and the contents of the cache memory of the first core are not rewritten and changed to contents of another process, processing efficiency can be improved in the multicore processor system.

If the second core completes the second process before the estimated time of completion of the first process in the multicore processor system, the given core may be notified of the result of the second process when it is detected that the estimated time of completion of the first process has passed. As a result, the contents of the cache memory of the first core are not rewritten and changed to contents of another process and processing efficiency can be improved in the multicore processor system.

If multiple second cores complete the second processes before the estimated period for competing the first process, notification of the results of the second processes are made concurrently after the estimated period for completing the first process has elapsed. Therefore, since the first core can execute together the interrupt processes and the reception processes to receive the results of the second processes, the number of times that the interrupt process is executed is reduced and processing efficiency can be improved.

In the first embodiment, it is not necessary to prepare an estimated period for the second process. Therefore, the accuracy of the estimated period for completing the first process can be improved by allocating a process with a relatively predictable processing period as the first process. A process with a relatively predictable processing period is, for example, a process having a small number of conditional branches.

In the first embodiment, although the parent process is not interrupted by the result of a child process, the process that uses the result of a child process may be interrupted by the result of another child process. The multicore processor system100according to the second embodiment provides a configuration in which the result of another child process does not interrupt the process that uses the result of a child process.

Functions of the multicore processor system100according to the second embodiment will be described.FIG. 8is a functional diagram of the multicore processor system100according to the second embodiment. The multicore processor system100includes a notifying unit801, an acquiring unit802, an acquiring unit803, an acquiring unit804, a notifying unit805, a notifying unit806, an acquiring unit807, an acquiring unit808, a calculating unit809, a detecting unit810, and a notifying unit811. The functions (the notifying unit801to the notifying unit811) acting as a control unit are implemented by the CPUs #0to #3executing programs stored in storage devices. The storage devices are, for example, the ROM102, the RAM103, the flash ROM104, and the flash ROM106depicted inFIG. 1. Alternatively, programs may be executed via the I/F108by another CPU to implement the functions.

InFIG. 8, the notifying unit801and the acquiring unit808are included as functions of the CPU #0; the acquiring unit802and the notifying unit805are included as functions of the CPU #1; and the acquiring unit803and the notifying unit806are included as functions of the CPU #2. The acquiring unit804, the acquiring unit807, and the calculating unit809to the notifying unit811are included as functions of the CPU #3.

This is based on the premise that the CPU #0executes a given process defined as a parent process while the CPU #1, the CPU #2, and the CPU #3execute a child process1, a child process2, and a child process3, respectively, called from the parent process. It is also assumed that at least one among the child processes1and2is completed before the parent process and that the child process3is completed after the parent process.

For example, if the CPU #1executes the parent process and the CPU #0executes a child process, the notifying unit801and the acquiring unit808may be included as functions of the CPU #1and the acquiring unit802and the notifying unit805may be included as functions of the CPU #0. The multicore processor system100according to the second embodiment can access the profile table201. The acquiring unit808has a function equivalent to the acquiring unit207and will not be described.

The notifying unit801has a function of giving notification of an estimated completion period for a process that uses the result of the second process, in addition to the contents of the notification given by the notifying unit202. For example, the notifying unit801causes the CPU #0executing the parent process to notify the CPU #1of an execution request for the child process1, the remaining period A1from the time of the execution request until the completion of the parent process, and an estimated period B1for completing a process that uses the result of the child process1. The contents of the notification may be stored in a register, cache memory, etc. of the CPU #0.

The acquiring units802to804have a function of acquiring the estimated completion period of a process that uses the result of the second process, in addition to the contents acquired by the acquiring unit203. For example, the acquiring unit802causes the CPU #1to acquire from the CPU #0, an execution request for the child process1, the remaining period A1from the time of the execution request until the completion of the parent process, and the estimated period B1for completing the process that uses the result of the child process1. The acquired contents are stored in a register, cache memory, etc. of the CPU #1.

The notifying unit805and the notifying unit806have a function of notifying another core (different from the first core) of the estimated completion period of a process that uses the result of the second process, in addition to the contents notified by the notifying unit206. For example, the notifying unit805causes the CPU #1to notify the CPU #0of the result of the child process1and to notify the CPU #2and the CPU #3of the estimated period B1of the process that uses the result of the child process1. The contents of the notification may be stored in a register, cache memory, etc. of the CPU #1.

The acquiring unit807has a function of causing a third core, which is executing a third process, to acquire an estimated completion period of a fourth process that is executed by the first core and uses the result of the second process, when the second core notifies the first core of the result of the second process. For example, the acquiring unit807causes the CPU #3, which is executing the child process3as the third process, to acquire the estimated period B1of the process that is executed by the CPU #0and uses the result of the child process1.

If multiple second cores exist, when the second cores notify the first core of the results of the second processes, the acquiring unit807may cause the third core to acquire the estimated period of the fourth process, which is present for each of the second cores. For example, when the CPU #1and the CPU #2notify the CPU #0of the result of the child process1and the result of the child process2, respectively, the acquiring unit807causes the CPU #3to acquire the estimated period B1of a process that uses the result of the child process1and an estimated period B2of a process that uses the result of the child process2. The acquired contents are stored in a register, cache memory, etc. of the CPU #3.

The calculating unit809has a function of calculating a waiting period by subtracting from the estimated period of the fourth process, the period that elapses from the point of acquisition of the estimated period of the fourth process by the acquiring unit807until the completion of the third process, if the third core completes the third process before the estimated completion period of the fourth process. For example, if the CPU #3completes the child process3before the estimated completion period of the process that uses the result of the child process1, the calculating unit809calculates a waiting period (B1−D3) by subtracting from the estimated period B1of the process that uses the result of the child process1, the period (period D3) that elapses until the completion of the child process3.

If multiple second cores exist, the calculating unit809may cause the third core to calculate a waiting period by subtracting, from a total of the estimated periods of the fourth processes, the period that elapses from the point of acquisition of the group of the estimated periods of the fourth processes by the acquiring unit until the completion of the third process. For example, the calculating unit809may cause the CPU #3to calculate a waiting period (B1+B2−D3) by subtracting the elapsed period D3from a sum B1+B2of the estimated periods of the processes that use the results of the child process1and child process2. The calculated value is stored in a register, cache memory, etc. of the CPU #3.

The detecting unit810causes the third core to detect that the waiting period calculated by the calculating unit809has elapsed since the time at the point of calculation by the calculating unit809. For example, the detecting unit810causes the CPU #3to detect that the waiting period (B1−D3) has elapsed since the calculation of the waiting period of the CPU #3. Information indicative of the detection is stored in a register, cache memory, etc. of the CPU #3.

The notifying unit811has a function of giving notification of the result of the third process from the third core to the first core after the estimated completion period of the fourth process, obtained by adding the estimated period of the fourth process to the time at the point of acquisition of the estimated period of the fourth process by the acquiring unit807. If the detecting unit810detects that the waiting period has elapsed, the notifying unit811may give notification from the third core to the first core. For example, the notifying unit811gives notification of the result of the child process3from the CPU #3to the CPU #0after the time point obtained by adding the estimated period B1to the time point of acquisition of the estimated period B1of the process that uses the result of the child process1. The contents of the notification may be stored in a register, cache memory, etc. of the CPU #3.

FIG. 9is an explanatory view of an operation pattern of a process between a parent and child, the operation pattern enabling efficient utilization of cache memory according to the second embodiment. In the example depicted inFIG. 9, as is the case withFIG. 3, the CPU #0executes a parent process at time t0and the CPUs #1to #3execute the child processes1to3in response to execution requests from the parent process. For example, the CPU #1executes the child process1at time t1; the CPU #2executes the child process2at time t2; and the CPU #3executes the child process3at time t3.

InFIG. 9, it is assumed that the CPUs #1to #3complete the processes after time t4when the parent process starts waiting and that among the CPUs #1to #3, the CPU #2completes the process first at time t5. Since the parent process has been completed and the CPU #0is in the waiting state at time t5, the CPU #2immediately notifies the CPU #0of the result of the child process2.

The CPU #0executes the interrupt process with respect to the CPU #2from time t5to time t6, executes the reception process from time t6to time t7to receive the result of the child process2, and executes the return process from time t7to time t8. Subsequently, the CPU #0executes from time t8to time t10, a process that uses the result of the child process2.

At time t9, the CPU #1completes the child process1. Since the CPU #0is executing the process that uses the result of the child process2at time t9, the CPU #1waits until time t10when the CPU #0completes the process that uses the result of the child process2, and gives notification of the result of the child process1at time t10. The notified CPU #0executes the interrupt process with respect to the CPU #1from time t10to time t11, executes the reception process from time t11to time t12to receive the result of the child process1, and executes the return process from time t12to time t13. After the return process, the CPU #0executes from time t13to time t14, a process that uses the result of the child process1.

As described, while the CPU #0is executing from time t8to time t10, a process that uses the result of a child process, if another child process is completed, the CPU completing the other process waits because the process that uses the result of the child process is still under execution. Thus, the cache contents saving an incomplete state of the process that uses the result of the child process of the CPU #0can be prevented from being rewritten by the interrupt process and the result of another child process. As is the case withFIG. 3, if the interrupt processes are executed together at the end of the parent process, the number of interrupts can be reduced.

FIG. 10is an explanatory view of processes executed at the time of design and at the time of execution for controlling the timing of the inter-core communication according to the second embodiment.FIG. 10depicts the processes at the time of design and the operation at the time of execution required for implementing the operation depicted inFIG. 9. A process group denoted by reference numeral1001represents processes1003to1006executed at the time of design and execution, and an explanatory view denoted by reference numeral1002represents details of the processes corresponding to the processes1003to1006. The processes executed at the time of design include the process1003and the process1004, and the processes executed at the time of execution include the process1005and the process1006.

In the process1003, a profiler or a designer determines a pattern of communication operation between the parent and child. For example, if a given process calls a process, the profiler regards the former process as a parent process and the latter process as a child process. In the explanatory view denoted by reference numeral1002, the profiler regards a process executed by the CPU #0as the parent process and processes executed by the CPUs #1to #3as the child processes1to3. In the process1004, the profiler acquires an estimated period (A) for completing the parent process and an estimated period (B) for completing a process that uses the result of a child process, based on a result of operation in a simulation, etc.

At the time of execution, in the process1005, when the CPU executing the parent process makes an execution request for a child process, the CPU executing the child process is notified of the estimated period (A) for completing the parent process and the estimated period (B) for completing the process that uses the result of the child process. In the explanatory view denoted by reference numeral1002, the CPU #0notifies the CPU #1of an execution request for the child process1, the estimated period (A) for completing the parent process, and an estimated period (B1) for completing a process that uses the result of the child process1through a notification1007. Similarly, the CPU #0notifies the CPU #2of an execution request for the child process2, the period (A), and a period (B2) through a notification1008, and the CPU #0notifies the CPU #3of an execution request for the child process3, the period (A), and a period (B3) through a notification1009.

Subsequently, in the process1006, a CPU executing a child process selects the timing of the completion of the parent process or of the completion of the process that uses the result of a child process to notify the CPU executing the parent process of a result of the child process. In the explanatory view denoted by reference numeral1002, the CPU #2notifies the CPU #0of the result of the child process2through a notification1008at the timing when the CPU #0completes the parent process. The CPU #1notifies the CPU #0of the result of the child process1through a notification1011at the timing when the CPU #0completes the process that uses the result of the child process2.

FIG. 11is an explanatory view of an execution example 1 of a process between a parent and child when the timing of the inter-core communication is controlled according to the second embodiment.FIG. 11depicts a first execution example of a process between a parent and child when the timing of the inter-core communication is controlled by the processes executed at the time of design, depicted inFIG. 10. At time t0, the CPU #0activates the parent process and at time t1, the CPU #0notifies the CPU #1of an execution request for the child process1to the CPU #1, the remaining period A1from time t1until the estimated time t4when the parent process is completed, and the estimated completion period B1of a process1101that uses the result of the child process1.

Subsequently, at time t2, the CPU #0notifies the CPU #2of an execution request for the child process2to the CPU #2, the remaining period A2from time t2until the estimated time t4when the parent process is completed, and the estimated completion period B2of a process1102that uses the result of the child process2. Subsequently, at time t3, the CPU #0notifies the CPU #3of an execution request for the child process3to the CPU #3, the remaining period A3from time t3until the estimated time t4when the parent process is completed, and an estimated completion period B3of a process1103that uses the result of the child process3.

At time t4, the CPU #0completes the parent process. Since no notification is received from the CPUs #1to #3at the point of time t4, the CPU #0waits until notification is received. At time t5, the CPU #1completes the child process1. Since at time t5, the remaining period A1is less than or equal to the period C1(period consumed for the child process1) and the parent process is completed, the CPU #1immediately notifies the CPU #0of the result of the child process1. The CPU #1notifies the CPUs #2and #3executing the other child processes of the estimated completion period B1of the process that uses the result of the child process1.

The notified CPU #0executes the interrupt process with respect to the CPU #1from time t5to time t6, executes the reception process from time t6to time t7to receive the result of the child process1, and executes the return process from time t7to time t8. The CPU #0receiving the notification from the CPU #1executes from time t8to time t10, the process1101that uses the result of the child process1.

The notified CPUs #2and #3execute the interrupt process with respect to the CPU #1from time t5to time t6, execute the reception process from time t6to time t7to receive the period B1, and execute the return process from time t7to time t8. After the return, the CPU #2continues the child process2and the CPU #3continues the child process3.

At time t9, the CPU #2completes the child process2. At time t9, the estimated completion period B1of the process1101that uses the result of the child process1is greater than a period D2(period consumed from time t5when the period B1is acquired until the completion of the child process2) and the CPU #0has not yet completed the process1101that uses the result of the child process1. Therefore, the CPU #2calculates a waiting period B1−D2by subtracting D2from B1and sets the waiting period B1−D2in the timer. After the setting, the CPU #2sets the thread in the sleep state until the timer expires.

When the timer of the CPU #2expires at time10, the CPU #2recovers the thread from the sleep state and notifies the CPU #0of the result of the child process2. The CPU #2notifies the CPUs #1and #3executing the other child processes of the estimated completion period B2of the process1102that uses the result of the child process2.

The notified CPU #0executes the interrupt process with respect to the CPU #2from time t10to time t11, executes the reception process from time t11to time t12to receive the result of the child process2, and executes the return process from time t12to time t13. After the return, the CPU #0executes from time t13to time t14, the process that uses the result of the child process2.

The notified CPU #3executes the interrupt process with respect to the CPU #2from time t10to time t11, executes the reception process from time t11to time t12to receive the period B2, and executes the return process from time t12to time t13. After the return, the CPU #3continues the child process3. Although the CPU #1also receives the notification, the notification is discarded since the child process1is completed and no process is under execution.

At time t14, the CPU #0completes the process1102that uses the result of the child process2. Since the CPU #0has not yet acquired the result of the child process3at the point of time t14, the CPU #0waits until the result of the child process3is acquired.

At time t15, the CPU #3completes the child process3. At time t15, the estimated period B2of the process1102that uses the result of the child process2is less than or equal to the period D3(period elapsing from time t10when the period B2is acquired until the completion of the child process3) and the CPU #0has completed the process1102that uses the result of the child process2. Therefore, the CPU #3immediately notifies the CPU #0of the result of the child process3. The CPU #3notifies the CPUs #1and #2executing the other child processes of the estimated completion period B3of the process that uses the result of the child process3.

The notified CPU #0executes the interrupt process with respect to the CPU #3from time t15to time t16, executes the reception process from time t16to time t17to receive the result of the child process3, and executes the return process from time t17to time t18. After the return process, the CPU #0executes from time t18to time t19, the process1103that uses the result of the child process3. Although the CPUs #1and #2also receive the notification, the notification is discarded since both the child processes1and2are completed and no process is under execution.

FIG. 12is an explanatory view of an execution example 2 of a process between a parent and child when the timing of the inter-core communication is controlled according to the second embodiment.FIG. 12depicts a second execution example of a process between parent and child when the timing of the inter-core communication is controlled by executing the processes at the time of design inFIG. 10. A difference from the execution example 1 depicted inFIG. 11is in that multiple child processes are completed before the parent process is completed.

At time t0, the CPU #0activates the parent process and at time t1, the CPU #0notifies the CPU #1of an execution request for the child process1to the CPU #1, a remaining period A1from time t1until estimated time t6when the parent process is completed, and an estimated period B1of the process1101that uses the result of the child process1.

Subsequently, at time t2, the CPU #0notifies the CPU #2of an execution request for the child process2to the CPU #2, a remaining period A2from time t2until the estimated time t6when the parent process is completed, and an estimated period B2of the process1102that uses the result of the child process2. Subsequently, at time t3, the CPU #0notifies the CPU #3of an execution request for the child process3to the CPU #3, a remaining period A3from time t3until the estimated time t6when the parent process is completed, and an estimated period B3of the process1103that uses the result of the child process3.

At time t4, the CPU #1completes the child process1. Since at time t4, the remaining period A1is greater than the period C1(period consumed for the child process1) and the parent process is not yet completed, the CPU #1calculates a waiting period A1−C1by subtracting C1from A1and sets the waiting period A1−C1in the timer. After the setting, the CPU #1sets the thread in the sleep state until the timer expires.

At time t5, the CPU #2completes the child process2. Since at time t5, the remaining period A2is greater than the period C2(period consumed for the child process2) and the parent process is not yet completed, the CPU #2calculates the waiting period A2−C2by subtracting C2from A2and sets the waiting period A2−C2in the timer. After the setting, the CPU #2sets the thread in the sleep state until the timer expires.

When the timers of the CPUs #1and #2expire at time6, the CPUs #1and #2recover the threads from the sleep state and notify the CPU #0executing the parent process of a result of the child process1and a result of the child process2, respectively. The CPU #1notifies the CPUs #2and #3executing the other child processes of the estimated period B1of the process1101that uses the result of the child process1. Similarly, the CPU #2notifies the CPUs #1and #3executing the other child processes of the estimated period B2of the process1102that uses the result of the child process2.

The notified CPU #0executes together the interrupt processes with respect to the CPU #1and the CPU #2from time t6to time t7, executes the reception processes from time t7to time t8to receive the results of the child process1and the child process2, and executes the return process from time t8to time t9. After the return process, the CPU #0sequentially executes from time t9to time t11, the process1101that uses the result of the child process1and the process1102that uses the result of the child process2. Although the CPUs #1and #2also receive the notification, the notification is discarded since both the child processes1and2are completed and no process is under execution.

The notified CPU #3executes together the interrupt processes with respect to the CPU #1and the CPU #2from time t6to time t7. Subsequently, the CPU #3executes the reception processes from time t7to time t8to receive the estimated period B1of the process1101that uses the result of the child process1and the estimated period B2of the process1102that uses the result of the child process2, and executes the return process from time t8to time t9. After the return process, the CPU #3continues the child process3from time t9to time t10.

At time t10, the CPU #3completes the child process3. At time t10, the estimated period B1of the process1101that uses the result of the child process1+the estimated period B2of the process1102that uses the result of the child process2is greater than a period D3(period from time t6when the period B1and the period B2are acquired until the completion of the child process3). According to the relationship of this inequality expression, the CPU #0has not yet completed the process1101that uses the result of the child process1nor the process1102that uses the result of the child process2. Therefore, the CPU #3calculates a waiting period B1+B2−D3by subtracting D3from B1+B2and sets the waiting period B1+B2−D3in the timer. After the setting, the CPU #3sets the thread in the sleep state until the timer expires.

When the timer of the CPU #3expires at time11, the CPU #3recovers the thread from the sleep state and notifies the CPU #0of a result of the child process3. The CPU #3notifies the CPUs #1and #2executing the other child processes of the estimated period B3of the process1103that uses the result of the child process3.

The notified CPU #0executes the interrupt process with respect to the CPU #3from time t11to time t12, executes the reception process from time t12to time t13to receive the result of the child process3, and executes the return process from time t13to time t14. After the return process, the CPU #0executes from time t14to time t15, the process that uses the result of the child process3. Although the CPUs #1and #2also receive the notification, the notification is discarded since both the child processes1and2are completed and no process is under execution.

FIG. 13is a flowchart of a process between a parent and child when the timing of inter-core communication is controlled according to the second embodiment. In the process between parent and child depicted inFIG. 13, the CPU #0executes a parent process and the CPUs #1to #3execute child processes. For simplicity of description, it is assumed that the CPU #1executes a child process in this description.

The CPU #0executes the parent process (step S1301). When a process calling a child process occurs during the execution of the parent process, the CPU #0adds an estimated period A of the parent process and an estimated period B of the process that uses the result of the child process to the parameters of the child process (step S1302). After the addition, the CPU #0notifies the CPU #1of an execution request for the child process (step S1303).

The CPU #1acquires the execution request for the child process and executes the child process (step S1304). After the completion of the child process, the CPU #1determines whether during execution of the child process, notification of an estimated period B was received from a CPU executing another child process (step S1305). The CPU executing another child process is the CPU #2or the CPU #3in this embodiment.

If a notification of the estimated period B is not received from a CPU executing another child process (step S1305: NO), the CPU #1acquires a process period C of the child process (step S1306). After the acquisition, the CPU #1determines whether the estimated period A added to the parameters is greater than the process period C of the child process (step S1307). If the estimated period A is greater than the process period C of the child process (step S1307: YES), the CPU #1sets the timer such that the thread is recovered after (the estimated period A−the process period C of the child process) (step S1308) and sets the thread in the sleep state (step S1313).

After the recovery from the sleep state consequent to the process of step S1313or if the estimated period A is less than or equal to the process period C of the child process (step S1307: NO), the CPU #1notifies the CPU #0of a result of the child process (step S1314). After the notification of the result of the child process, the CPU #1notifies the other CPUs except the CPU #0of the estimated period B of the CPU #1(step S1315) and is terminated. The CPU #0notified at step S1314executes a process that uses the result of the child process for the notification is received (step S1316) and completes the process.

If a notification of the estimated period B was received from a CPU executing another child process (step S1305: YES), the CPU #1acquires an elapsed time D after the last notification is received (S1309). After the acquisition, the CPU #1calculates a total of the estimated periods B received at the same time as the last notification (step S1310).

The communications from CPUs completing the child processes may be somewhat shifted from each other and may not exactly be at the same time. However, actually, the CPUs execute the reception process after executing the interrupt process when an interrupt occurs due to the communication and therefore, a shift of communication can be absorbed by interrupt overhead if all the processors are physically located within a short distance such as being housed on one chip. As a result, if the notifications are made in a somewhat shifted manner, each CPU can collectively execute the reception processes.

After calculating the total, the CPU #1determines whether the total of the estimated periods B is greater than the elapsed period D (step S1311). If the total of the estimated periods B is greater than the elapsed period D (step S1311: YES), the CPU #1sets the timer such that the thread is recovered after (the estimated periods B−the elapsed period D) (step S1312) and goes to the process of step S1313. If the total of the estimated periods B is less than or equal to the elapsed period D (step S1311: NO), the CPU #1goes to the process of step S1314.

As described, according to the multicore processor system, the communication control method, and the communication control program, a third core other than first and second cores, and executing a third process acquires an estimated period for completing a fourth process that uses the result of a second process. The third core notifies the first core of the result of the third process after the estimated period for completing the fourth process. As a result, it is not necessary to rewrite cache memory even if the first core is executing a process that uses the result of another process and processing efficiency in the multicore processor system can be improved.

In the multicore processor system, if the third process is completed before the estimated time of completion of the fourth process, the first core may be notified of the result of the third process when it is detected that the estimated time of completion of the fourth process has passed. As a result, even if the first core is executing a process that uses the result of another process, the contents of the cache memory of the first core are not rewritten and changed to contents of another process and processing efficiency in the multicore processor system can be improved. By detecting that the estimated time of completion of the fourth process has passed, an idle period is not generated in the first core and the processing efficiency can be improved.

If multiple second cores complete the second processes before the estimated time of completion of the third process, the first core may be notified of a result of the third process after the estimated completion time of a fourth process group in the multicore processor system. As a result, even if the first core is executing the fourth process group, the contents of the cache memory of the first core are not rewritten and changed to contents of another process and processing efficiency in the multicore processor system can be improved. This is particularly effective when the number of cores increases and the processes that use the results of child processes increase.

In the multicore processor system, if the third process is completed before the estimated time of completion of the fourth process group, the first core may be notified of the result of the third process when it is detected that the estimated time of completion of the fourth process group has passed. As a result, even if the first core is executing the fourth process, the contents of the cache memory of the first core are not rewritten and changed to contents of another process, whereby processing efficiency in the multicore processor system can be improved. By detecting that the estimated time of completion of the fourth process group has passed, an idle period is not generated in the first core and processing efficiency can be improved.

The first embodiment and the second embodiment can be mixed and operated in the multicore processor system. When the first core notifies the second core of an execution request for the second process, the second core can determine whether the acquired process is that of the first embodiment or the second embodiment depending on whether an estimated period of the fourth process that uses the result of the second process is added to parameters.

The communication control method described in the present embodiment may be implemented by executing a prepared program on a computer such as a personal computer and a workstation. The program is stored on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, read out from the computer-readable medium, and executed by the computer. The program may be distributed through a network such as the Internet.

The multicore processor system, the communication control method, and the communication control program prevent the core executing the parent process from being interrupted in the middle of processing, thereby preventing the cache memory from being needlessly rewritten, and enabling improved processing efficiency.