Method and apparatus for adjusting threshold voltage in a replacement metal gate integration

A methodology for enabling a gate stack integration process that provides additional threshold voltage margin without sacrificing gate reliability and the resulting device are disclosed. Embodiments include conformally forming a margin adjusting layer in a gate trench, forming a metal capping layer on the margin adjusting layer, and forming an n-type work function (nWF) metal layer on the metal capping layer.

TECHNICAL FIELD

The present disclosure relates to a replacement metal gate (RMG) process for threshold voltage adjustment. The present disclosure is particularly applicable to n-type and p-type field effect transistors (N/P-FET) for 20 nanometer (nm) technology nodes and beyond.

BACKGROUND

A gate stack integration according to a current RMG process is illustrated inFIGS. 1A through 1D.FIG. 1Aillustrates the formation of an interface layer (IL) and a high-K (HK) dielectric layer in both N-FET and P-FET gate trenches101and103, respectively, on a substrate100. Adverting toFIG. 1B, a p-type work function (pWF) metal layer105(e.g., titanium nitride (TiN)) is deposited. Next, as illustrated inFIG. 1C, the pWF metal layer105is selectively removed from the N-FET devices by a patterning and etch process. Adverting toFIG. 1D, an n-type work function (nWF) metal layer107is deposited on both N-FET and P-FET device gate trenches and a gate metal109(e.g., aluminum (Al)) is deposited.

For 20 nm and beyond technology nodes, the threshold voltage (Vth) is adjusted by Al diffusion to the gate stack from the gate metal (e.g., titanium aluminide (TiAl) or Al). However, Al diffusion may also cause high leakage currents to the gate stack resulting in time dependent dielectric breakdown (TDDB). Such leakage currents especially affect N-FET devices. Thus, the utilization of nWF metals to adjust Vthhas been very selective depending on the subsequent metal layers (e.g., TiN, tantalum nitride (TaN)) in the RMG process and their thickness. Further, RMG processes are made more complicated by the additional metal layers.

A need therefore exists for a methodology enabling reliable threshold voltage adjustment with a simplified post gate (PG) patterning, and the resulting device.

SUMMARY

An aspect of the present disclosure is a method for a simplified RMG process for a gate stack exhibiting additional Vthmargin and reduced susceptibility to TDDB.

Another aspect of the present disclosure is a gate stack exhibiting additional Vthmargin and reduced susceptibility to TDDB.

According to the present disclosure, some technical effects may be achieved in part by a method including: conformally forming a margin adjusting layer in a first gate trench, forming a metal capping layer on the margin adjusting layer, and forming an nWF metal layer on the metal capping layer.

Aspects of the present disclosure include forming the margin adjusting layer by conformal deposition to a thickness of 4 Angstroms (Å) to 6 Å. Additional aspects include forming the metal capping layer of TiN by a conformal deposition process to a thickness of 10 Å to 12 Å. Further aspects include conformally forming a dielectric layer on a bottom surface and sidewalls of the first gate trench and of a second gate trench, forming a pWF metal layer on the dielectric layer in the first and second gate trenches, removing the pWF metal layer from the first gate trench, and forming the margin adjusting layer on the dielectric layer in the first gate trench. Another aspect includes forming the margin adjusting layer on the pWF metal layer in the second gate trench. Further aspects include filling the first and second gate trenches with a silicon (Si) capping layer to a height of 100 Å to 200 Å above the gate trench, annealing the Si capping layer, and subsequently removing the annealed silicon capping layer. Additional aspects include forming the nWF metal layer of an nWF material and forming the margin adjusting layer of lanthanum oxide (La2O3).

Another aspect of the present disclosure is a device including: a margin adjusting layer conformally formed in a first gate trench of an RMG, a metal capping layer formed on the margin adjusting layer, and an nWF metal layer formed on the metal capping layer. Additional aspects include the margin adjusting layer having a thickness of 4 Å to 6 Å. Further aspects include the metal capping layer being formed of TiN and having a thickness of 10 Å to 12 Å. Additional aspects include a HK dielectric layer conformally formed on a bottom surface and sidewalls of the first gate trench and of a second gate trench, wherein the margin adjusting layer is formed on the HK dielectric layer of the first gate trench. Another aspect includes a pWF metal layer formed on the HK dielectric layer in the second gate trench, wherein the margin adjusting layer is formed on the pWF metal layer. Further aspects are the nWF metal layer including an nWF material and the margin adjusting layer including La2O3.

Another aspect includes a method including: forming a HK dielectric layer on the bottom and side surfaces of both N-FET and P-FET gate trenches, forming a pWF metal layer on the HK dielectric layer, removing the pWF metal layer from the N-FET gate trench, conformally forming a margin adjusting layer in the N-FET and P-FET gate trenches, forming a capping layer on the margin adjusting layer, filling the gate trenches with a Si capping layer, annealing the filled N-FET and P-FET gate trenches, subsequently removing the Si capping layer from the N-FET and P-FET gate trenches, and forming an nWF metal layer on the metal capping layer.

Other aspects include forming the margin adjusting layer by conformal deposition to a thickness of 4 Å to 6 Å, forming the metal capping layer of TiN by conformal deposition to a thickness of 10 Å to 12 Å. Further aspects include forming the nWF metal layer of an nWF material, and forming the margin adjusting layer of La2O3.

DETAILED DESCRIPTION

The present disclosure addresses and solves the current problem of TDDB attendant upon nWF metal diffusion in an N-FET gate stack for 20 nm technology nodes and beyond. In accordance with embodiments of the present disclosure, a La-based margin adjusting layer and metal capping layer are formed prior to the nWF metal layer in the N-FET and P-FET gate trenches.

Methodology in accordance with embodiments of the present disclosure includes conformally forming a margin adjusting layer in a first gate trench; forming a metal capping layer on the margin adjusting layer; and forming an n-type work function (nWF) metal layer on the metal capping layer. Additional aspects include conformally forming a HK dielectric layer and a pWF metal layer in first and second gate trenches; selectively removing the pWF metal layer from the first gate trench; and forming the margin adjusting layer on the HK dielectric layer in the first gate trench

FIGS. 2A through 2Fschematically illustrate various process steps for a La-based gate stack integration scheme, in accordance with an exemplary embodiment of the present disclosure.

FIG. 2Aillustrates IL and HK dielectric layers formed within N-FET and P-FET gate trenches201and203, respectively, on a substrate200, similar to current RMG process. In one embodiment, the IL may be formed from a Si-based oxide (SiOx) and has a thickness from 8 Å to 12 Å. The HK dielectric layer may, for example, be formed from hafnium oxide (HfO2) and has a thickness from 13 Å to 15 Å. The IL may be formed by a chemical oxidation process or an in-situ steam generation (ISSG) process, and the HK layer may be formed by an atomic layer deposition (ALD) process.

Adverting toFIG. 2B, a pWF metal layer205is conformally formed on the HK dielectric layer for both the N-FET and P-FET gate trenches. The pWF metal layer205may, for example, include TiN and has a thickness of approximately 50 Å. The pWF metal layer205may be formed by an ALD process.

Adverting toFIG. 2C, the pWF metal layer205is selectively removed from the N-FET gate trench201but is left in place on the P-FET gate trench203. For example, a patterned etch based on a standard clean 1 (SC1) chemistry process may be used to remove the pWF metal layer from the N-FET gate trench201. Next, a margin adjusting layer207, e.g. a La2O3layer, is conformally formed on the (now exposed) HK dielectric layer of the N-FET gate trench201and on the pWF metal layer205of the P-FET gate trench203. The margin adjusting layer207layer may be formed to a thickness ranging from 4 Å to 6 Å.

Adverting toFIG. 2D, a metal capping layer209is conformally formed on the margin adjusting layer207in both the N-FET gate trench201and the P-FET gate trench203. The metal capping layer209may be formed from TiN and may have a thickness ranging from 10 Å to 12 Å. The metal capping layer may be deposited by an ALD process.

Adverting toFIG. 2E, a Si cap211is deposited over both the N-FET gate trench201and the P-FET gate trench203and is subsequently annealed. The Si cap211may, for example, be deposited by a chemical vapor deposition (CVD) process and has a thickness ranging from 100 Å to 200 Å.

Adverting toFIG. 2F, the Si cap211is stripped from both the N-FET gate trench201and the P-FET gate trench203. An ammonium hydroxide (NH4OH) etching process may be used to strip the Si cap211. Next, an nWF metal layer213is conformally formed on the (now exposed) metal capping layer209of the N-FET gate trench201and of the P-FET gate trench203. The nWF metal layer213may include TiAl and may, for example, be formed by a plasma vapor deposition (PVD) process to a thickness of approximately 60 Å. The thickness of the nWF metal layer213in the P-FET device gate trench may be greater near the bottom surface of the trench than at the top without affecting the operation of the resulting P-FET device.

The embodiments of the present disclosure can achieve several technical effects, including additional threshold voltage margin, simplified post gate patterning, and improved gate stack reliability. The present disclosure enjoys industrial applicability in fabricating any of various types of highly integrated semiconductor devices, particularly for 20 nm technology products and beyond.