N/P boundary effect reduction for metal gate transistors

The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of dummy gates over a substrate. The dummy gates extend along a first axis. The method includes forming a masking layer over the dummy gates. The masking layer defines an elongate opening extending along a second axis different from the first axis. The opening exposes first portions of the dummy gates and protects second portions of the dummy gates. A tip portion of the opening has a width greater than a width of a non-tip portion of the opening. The masking layer is formed using an optical proximity correction (OPC) process. The method includes replacing the first portions of the dummy gates with a plurality of first metal gates. The method includes replacing the second portions of the dummy gates with a plurality of second metal gates different from the first metal gates.

BACKGROUND

To enhance the performance of ICs, metal gate transistors have been used in recent years. However, conventional metal gate transistors may suffer from an N/P boundary effect. In more detail, when a P-type metal gate transistor borders an N-type metal gate transistor, contamination may occur through metal diffusion across the boundary between the P-type and N-type metal gate transistors. Such contamination may degrade the threshold voltage (Vt) of the metal gate transistors. Moreover, as device sizes continue to shrink, limitations in current lithography technology may exacerbate the undesirable Vtshifting issue discussed above, thereby further degrading the performance of conventional metal gate transistors.

Therefore, while existing methods of fabricating metal gate transistors have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.

SUMMARY

One of the broader forms of the present disclosure involves a method of fabricating a semiconductor device. The method includes: forming a first dummy gate and a second dummy gate over a substrate; forming a patterned mask over the first and second dummy gates, the patterned mask exposing a first segment of the first dummy gate and a second segment of the second dummy gate, while covering a third segment of the first dummy gate and a fourth segment of the second dummy gate, wherein the forming the mask is carried out in a manner such that the first and second segments have significantly different lengths; replacing the first segment and the second segment with a first metal gate and a second metal gate, respectively, the first and second metal gates containing a first type metal material; and replacing the third segment and the fourth segment with a third metal gate and a fourth metal gate, respectively, the third and fourth metal gates containing a second type metal material different from the first type.

In some embodiments, one of the first and second segments is longer than the other; and a ratio of a longer one of the first and second segments to a shorter one of the first and second segments is greater than 1:1 but less than 1.5:1.

In some embodiments, the forming the patterned mask is carried out using an optical proximity correction (OPC) technique.

In some embodiments, the first and second dummy gates each extend in a first direction; and the patterned mask defines an elongate contour that extends in a second direction different from the first direction.

In some embodiments, the first direction is substantially perpendicular to the second direction; and the first and second segments are confined within the elongate contour.

In some embodiments, an end portion of the contour is wider in the first direction than a rest of the contour; and the end portion of the contour coincides with an edge of one of the first and second segments.

In some embodiments, the first and second dummy gates each contain a polysilicon material.

In some embodiments, the first type metal material includes a P-type metal; and the second type metal material includes an N-type metal.

In some embodiments, the first and second metal gates are formed over an active region; a first N/P boundary is formed by an interface between the first and third segments; a second N/P boundary is formed by an interface between the second and fourth segments; and a first distance from an edge of the active region to the first N/P boundary is less than a second distance from the edge of the active region to the second N/P boundary.

Another of the broader forms of the present disclosure involves a method of fabricating a semiconductor device. The method includes: forming a plurality of dummy gates over a substrate, the dummy gates extending along a first axis; forming a masking layer over the dummy gates, the masking layer defining an elongate opening that extends along a second axis different from the first axis, wherein the opening exposes a plurality of first portions of the dummy gates and protects a plurality of second portions of the dummy gates, wherein a tip portion of the opening has a width greater than a width of a non-tip portion of the opening, and wherein the forming the masking layer includes performing an optical proximity correction (OPC) process; replacing the first portions of the dummy gates with a plurality of first metal gates; and replacing the second portions of the dummy gates with a plurality of second metal gates different from the first metal gates.

In some embodiments, the second axis is approximately orthogonal to the first axis; and the width of the tip portion is measured along the first axis.

In some embodiments, the OPC process includes using a serif assistant feature or a hammerhead assistant feature.

In some embodiments, the first metal gates contain P-type work function metal layers; and the second metal gates contain N-type work function metal layers.

In some embodiments, the first metal gates are formed over an active region for a P-type transistor; a plurality of N/P boundaries are formed by respective pairs of the first and second metal gates; and an outer-most N/P boundary is spaced farther apart from the active region than the rest of the N/P boundaries.

In some embodiments, a ratio between the width of the tip portion of the opening and the width of the non-tip portion of the opening is greater than 1:1 but less than 1.5:1.

In some embodiments, the dummy gates each contain a polysilicon gate electrode.

Yet another of the broader forms of the present disclosure involves a semiconductor device. The semiconductor device includes: a doped active region disposed in a substrate, the doped active region having an elongate shape and extends in a first direction; a plurality of first metal gates disposed over the active region, wherein the first metal gates each extend in a second direction different from the first direction, and wherein an outer-most first metal gate has a greater dimension measured in the second direction than the rest of the first metal gates; and a plurality of second metal gates disposed over the substrate but not over the doped active region, wherein the second metal gates contain different materials than the first metal gates, and wherein the second metal gates each extend in the second direction and form a plurality of respective N/P boundaries with the first metal gates.

In some embodiments, the doped active region includes a source/drain region for a P-type transistor; the first metal gates each include a P-type work function metal; and the second metal gates each include an N-type work function metal.

In some embodiments, a distance between the doped active region and an outer-most N/P boundary exceeds a distance between the doped active region and other N/P boundaries.

In some embodiments, the first direction is approximately perpendicular to the second direction.

DETAILED DESCRIPTION

It is understood that the following disclosure provides many different embodiments, or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the terms “top,” “bottom,” “under,” “over,” and the like are used for convenience and are not meant to limit the scope of embodiments to any particular orientation. Various features may also be arbitrarily drawn in different scales for the sake of simplicity and clarity. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself necessarily dictate a relationship between the various embodiments and/or configurations discussed.

As semiconductor fabrication technologies continue to advance, metal gate transistors have been used instead of polysilicon gate transistors to improve the performance of Integrated Circuit (IC) devices. The metal gate transistors employ a high-k material gate dielectric and a metal gate electrode. For the sake of facilitating the ensuing discussions, a diagrammatic fragmentary cross-sectional side view of a high-k metal gate device35is shown inFIG. 1according to various aspects of the present disclosure.

Referring toFIG. 1, the high-k metal gate device35includes an N-type transistor35A (N-type Metal Oxide Semiconductor Field Effect Transistor, or NMOS) and a P-type transistor35B (P-type Metal Oxide Semiconductor Field Effect Transistor, or PMOS). The NMOS35A and PMOS35B are formed over a substrate40. The substrate40is a silicon substrate doped with a P-type dopant such as boron (for example a P-type substrate). Alternatively, the substrate40could be another suitable semiconductor material. For example, the substrate40may be a silicon substrate that is doped with an N-type dopant such as phosphorous or arsenic (an N-type substrate). The substrate40may alternatively be made of some other suitable elementary semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Further, the substrate40could include an epitaxial layer (epi layer), may be strained for performance enhancement, and may include a silicon-on-insulator (SOI) structure.

Isolation structures50are formed in the substrate40. In some embodiments, the isolation structures50include Shallow Trench Isolation (STI) features. The STI features are formed by etching recesses (or trenches) in the substrate40and filling the recesses with a dielectric material. In some embodiments, the dielectric material of the STI features includes silicon oxide. In alternative embodiments, the dielectric material of the STI features may include silicon nitride, silicon oxy-nitride, fluoride-doped silicate (FSG), and/or a low-k dielectric material known in the art. In yet other embodiments, the isolation structures50may include other types of isolation features such as such as Deep Trench Isolation (DTI) features.

A gate dielectric layer100is then formed over the interfacial layer. The gate dielectric layer100is formed by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. In the illustrated embodiments, the gate dielectric layer100includes a high-k dielectric material. A high-k dielectric material is a material having a dielectric constant that is greater than a dielectric constant of SiO2, which is approximately 4. In an embodiment, the gate dielectric layer100includes hafnium oxide (HfO2), which has a dielectric constant that is in a range from approximately 18 to approximately 40. In alternative embodiments, the gate dielectric layer100may include one of ZrO2, Y2O3, La2O5, Gd2O5, TiO2, Ta2O5, HfErO, HfLaO, HfYO, HfGdO, HfAlO, HfZrO, HfTiO, HfTaO, and SrTiO. It is understood that an interfacial layer may be optionally formed between the substrate40and the gate dielectric layer100. The interfacial layer may be formed by an ALD process and may include a dielectric material such as silicon oxide (SiO2).

A capping layer110is formed over the gate dielectric layer100. The capping layer110may be formed by a deposition process such as CVD, physical vapor deposition (PVD), or ALD. The capping layer110prevents diffusion between the gate dielectric layer100and the metal layers thereabove. In some embodiments, the capping layer110contains titanium nitride.

The NMOS device35A and the PMOS device35B each include a respective metal gate electrode formed over the capping layer110. The NMOS gate electrode includes a work function metal layer120A, a blocking layer130A, and a fill metal layer140A. The PMOS gate electrode includes a work function metal layer120B, a blocking layer130B, and a fill metal layer140B. The work function metal layers120A-120B, the blocking layers130A-130B, and the fill metal layers140A-140B are each formed by one or more deposition processes such as CVD, PVD, ALD, or plating.

The work function metal layers120A-120B are configured to tune a work function of its corresponding transistor to achieve a desired threshold voltage Vt. In some embodiments, the work function metal layer120A contains one of: TiAl, TiAlN, or TaCN, or combinations thereof. In some embodiments, the work function metal layer120B contains one of: TiN, WN, or W, or combinations thereof. In other embodiments, the work function metal layers120A-120B may include other metal materials that are suitable for application or manufacturing considerations.

The blocking layers130A-130B are configured to block or reduce diffusion between the layers therebelow (e.g., the work function metal layers120A-120B) and the layers thereabove (e.g., the fill metal layers140A-140B). In some embodiments, the blocking layer130A and the blocking layer130B each contain one of: TiN, TiON, TaN, TaON, or combinations thereof. The blocking layer130A and the blocking layer130B may have different thicknesses.

The fill metal layers140A-140B are configured to serve as the main conductive portion of the NMOS and PMOS gate electrodes, respectively. In some embodiments, the fill metal layers140A-140B each contain Aluminum (Al). In other embodiments, the fill metal layers140A-140B may include contain other conductive materials such as Tungsten (W), Copper (Cu), or combinations thereof.

The metal gate electrodes of the NMOS device35A and the PMOS device35B may be formed by a gate replacement process. For example, using a gate-last approach, dummy polysilicon gate electrodes are first formed on a high-k gate dielectric layer. A plurality of ion implantation and/or diffusion processes are then performed to form source/drain regions of the transistors, followed by high temperature annealing processes to activate the source/drain regions. Thereafter, the dummy polysilicon gate electrodes are removed and replaced by the metal gate electrodes discussed above. Alternatively, in a high-k last approach (also considered a form of gate-replacement process), a dummy silicon oxide gate dielectric layer may be formed first. The rest of the steps for the high-k last approach are similar to the gate-last approach, except that the dummy silicon oxide gate dielectric layer is removed along with the removal of the dummy polysilicon gate electrodes. A high-k gate dielectric layer is then formed to replace the dummy silicon oxide gate dielectric layer, and then the metal gate electrodes are formed over the high-k gate dielectric layer.

Regardless of the specific approach used to form the high-k metal gate device, in many cases the NMOS and PMOS transistors are bordering each other (such as the NMOS and PMOS metal gate transistors35A and35B ofFIG. 1). In other words, an N/P boundary150exists between these bordering NMOS and PMOS transistors. Since the NMOS and PMOS transistors35A and35B are intended to operate independently, metal diffusion across the boundary150may become a concern. This is because such diffusion may affect the threshold voltage of these transistors.

An example diffusion path160is shown inFIG. 1, which illustrates that the metal material (e.g., Aluminum) from the fill metal layer140A may diffuse across the N/P boundary150and to the PMOS transistor. This diffusion is likely to occur, because the NMOS blocking layer130A is quite narrow/thin, particularly near the corner between the fill metal layer140A and the N/P boundary150. Consequently, the NMOS blocking layer130A may not be able to effectively block or prevent diffusion due to its narrowness. The capping layer110of the PMOS transistor35B will thus be contaminated, which results in a higher threshold voltage Vtfor the PMOS transistor35B compared to PMOS transistors without an N/P boundary (i.e., a PMOS transistor not bordering an NMOS transistor). This may be referred to as a boundary effect.

The boundary effect is exacerbated as semiconductor devices continue to be scaled down. For example, a distance160between the N/P boundary150and an active region (e.g., source/drain region) of the PMOS transistor may shrink as part of the scaling down process. Therefore, the diffusion path160may shrink as well, thereby facilitating the undesirable diffusion across the N/P boundary150and the contamination of the PMOS transistor35B.

It is noted that the diffusion from the PMOS transistor35B to the NMOS transistor35A is not as much of a concern, partially because the blocking layer130B for the PMOS transistor is much thicker (and therefore more capable of preventing diffusion), and also partially because the fill metal layer140B of the PMOS transistor35B is located farther away from the N/P boundary150(and therefore lengthening the diffusion path). Thus, the unintended threshold voltage shift for the PMOS transistor35B is of more concern.

FIG. 2is a graph200that illustrates the relationship between the threshold voltage shift and various other factors such as transistor device size and distance between the N/P boundary and the PMOS active region. Referring toFIG. 2, the graph200includes an X-axis and a Y-axis that is perpendicular to the X-axis. The X-axis represent the distance (e.g., the distance160ofFIG. 1) between an N/P boundary and the PMOS active region, denoted herein as distance “D”. The Y-axis represents the amount of shift in the threshold voltage Vtof the PMOS transistor (e.g., the PMOS transistor35B).

The graph200contains a plurality of curves210-212that represent plots of the threshold voltage Vtversus the distance D. It can be seen that as the distance D increases, the amount of threshold voltage shift is reduced. In other words, a larger distance D is desired, since it corresponds to a minimal amount of threshold voltage shift. On the other hand, a small distance D causes a large amount of threshold voltage shift, which is undesirable.

Meanwhile, the width and length of the PMOS transistor also affects the threshold voltage shift. The dashed line inFIG. 2indicates the direction in which the curves210-212move as the width and/or length of the PMOS transistor decreases. For example, the curve212represents a PMOS transistor having smaller width and/or length than that of the PMOS transistor represented by the curve211, and the curve211represents a PMOS transistor having smaller width and/or length than that of the PMOS transistor represented by the curve210. As such, at any given fixed distance D, the curve212has the greatest amount of threshold voltage shift (undesirable), the curve211has an intermediate amount of threshold voltage shift (less undesirable), and the curve210has the least amount of threshold voltage shift (more desirable).

Thus, based on the relationships indicated inFIG. 2, it can be seen that in order to minimize the amount of threshold voltage shift, the distance D between an N/P boundary and the PMOS active region should be maximized, and the width and length of the PMOS transistor should be maximized as well. However, the trend in modern semiconductor fabrication is the continued scaling down process—continued reductions of semiconductor feature dimensions. Thus, since it is not always feasible to maximize the distance D or the width and length of transistors, it is important to ensure that the various feature sizes do not experience unintentional variations as part of the fabrication process, because these variations may lead to severe degradations in uniformity (for example, threshold voltage uniformity).

Unfortunately, limitations in current lithography technology may cause these undesirable variations. For example, a line-end rounding effect in a lithography process may unintentionally reduce the size of a PMOS metal gate transistor, and/or reduce the distance between the N/P boundary and the PMOS active region. To avoid these problems, a method of fabricating metal gate transistors is discussed below with reference toFIGS. 3-9. In more detail,FIGS. 3-4and6-9are diagrammatic fragmentary top views of a portion of a semiconductor wafer at various stages of fabrication according to some embodiments of the present disclosure, andFIG. 5includes diagrammatic top views of various layout patterns.

Referring toFIG. 3, the wafer includes a substrate. The substrate may be similar to the substrate40ofFIG. 1, and may be doped and may contain a plurality of isolation structures. The wafer also includes a plurality of gates, four of which are illustrated herein as gates220-223. The gates220-223illustrated herein have elongate rectangular shapes, and as such they may also be referred to as gate strips or gate lines220-223. In the illustrated embodiments, the gate lines220-223are dummy gate electrodes and include a polysilicon material. Although not shown in the top view ofFIG. 3, it is understood that each of the gate lines220-223may have a gate dielectric layer formed therebelow. The gate dielectric layer may contain a high-k material.

The wafer includes active regions230. The active regions may include lightly-doped source/drain regions and heavily-doped source/drain regions. These lightly-doped source/drain regions and heavily-doped source/drain regions may each be formed by a plurality of ion implantation processes and diffusion processes. The formation of these regions may be performed using a plurality of patterning processes. The gate lines220-223may be used as patterning masks during these patterning processes.

In the illustrated embodiments, the gate lines220-223have elongate shapes and extend in a direction235. In comparison, the active regions230extend in a direction236, which is different from the direction235. In some embodiments, the directions235and236are substantially perpendicular or orthogonal to each other.

The wafer also includes an interlayer (or interlevel) dielectric (ILD) layer240formed between the gate lines220-223. The ILD layer240contains a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a low-k material. At the stage of fabrication shown inFIG. 3, the ILD layer240has been formed and polished by a polishing process (e.g., a chemical-mechanical-polishing process) to have a planarized surface with the gate lines220-223.

Referring now toFIG. 4, a patterned mask250is formed over the wafer. In some embodiments, the patterned mask250includes a photoresist mask. In other embodiments, the patterned mask250may include a hard mask. The patterned mask250is formed by a lithography process, which may involve one or more masking, exposing, baking, rinsing, and etching processes (not necessarily in that order).

The patterned mask250defines a contour (or an opening)260. The contour260has an elongate shape and extends along the direction236(same direction as the active region230but perpendicular to that of the gate lines220-223). The contour260divides each of the gate lines220-222into two segments or portions: segments220A-222A that are exposed by (or disposed within) the contour260and segments220B-222B that are disposed outside of the contour260(or covered by the mask250). Eventually, the exposed segments220A-222A will each be replaced by one type of metal gate (e.g., a PMOS gate), while the covered segments220B-222B will each be replaced by another type of metal gate (e.g., an NMOS gate). This will be discussed in more detail later.

Still referring toFIG. 4, among the exposed segments, the segment222A may be considered an edge segment or outer-most segment, since it is located closest to an edge or tip270of the contour260. Note that the contour260has another edge or tip opposite the tip270, but sinceFIG. 4is a fragmentary view, the contour260is only partially illustrated herein, and the other edge or tip is not illustrated. Alternatively stated, the contour260may be viewed as having a tip portion280, which includes (but is not limited to) a portion of the contour260located near the tip270of the contour260. The outer-most segment222A is exposed by (and disposed within) the tip portion280of the contour260. The interfaces between the segments222A and222B coincides with the boundaries of the tip portion280.

As illustrated, the tip portion280of the contour260is wider (measured in the direction235) than the rest of the contour260. This is done to ensure that the outer-most segment222A is longer (also measured in the direction235) than the rest of the segments220A-221A. This configuration helps reduce the threshold voltage shift, which will be discussed in more detail below. In some embodiments, the shape of the contour260(i.e., the wider tip portion280) is obtained using an Optical Correction Proximity (OPC) technique. In more detail, refer toFIGS. 5A-5D, where FIGS.5A and5C-5D are diagrammatic top views of layout plans, andFIG. 5Bis a top view of an example semiconductor device corresponding to the top view of the layout plan illustrated inFIG. 5A.

InFIG. 5A, a rectangular layout contour300may delineate the intended boundaries of a mask layer, for example the mask250ofFIG. 4. The shape and geometries of the layout contour may be transferred to a corresponding photomask (not illustrated herein). Ideally, the rectangular shape of the layout contour300will be preserved during a subsequent lithography process, so that the formed mask will also demonstrate the shape of the layout contour300. However, due to current lithography limitations, a line-end rounding effect may occur, which will form a mask having a contour310as shown inFIG. 5B. In more detail, the tip of the formed contour310is rounded or curved, as opposed to being rectangular as intended. If this were to happen to the contour260ofFIG. 4, the segment222A would have been shorter than the rest of the segments220A-221A located away from the tip portion280of the contour260. As discussed above, the segments220A-222A and220B-222B will eventually be replaced by metal gates. For reasons similar to those discussed above with reference toFIGS. 1-2, a shorter metal gate (corresponding to a shortened segment222A) will have detrimental threshold voltage shift effects. Hence, the traditional approach of using a rectangular layout contour to form a desired rectangular contour may not be feasible.

In comparison, according to the various aspects of the present disclosure, an OPC technique is used to overcome the issues discussed above. The OPC technique employs assistant features to “help” the actual contour achieve a desired shape.FIGS. 5C and 5Dillustrate two example assistant features: a serif assistant feature320inFIG. 5Cand a hammerhead assistant feature330inFIG. 5D. These assistant features320-330ofFIGS. 5C-5Dcan effectively minimize the line-end rounding effect of the fabricated mask contour. In the embodiments disclosed herein, assistant features similar to those shown inFIGS. 5C and 5Dmay be used and further configured to ensure that the tip portion280of the contour260does not suffer from the line-end rounding effect. In fact, the assistant features used in the OPC process herein help ensure that the tip portion280has a greater width than the rest of the contour260. In this manner, the length of the segment222A is formed to be at least as long as the rest of the segments220A-221A.

Referring now toFIG. 6, the segments220A-222A are removed, thereby forming openings340-342, respectively. The segments220A-222A may be removed by an etching process, where the patterned mask250is used as an etching mask. Thereafter, the patterned mask250is removed through a suitable process such as an ashing process or a stripping process.

Referring now toFIG. 7, metal gates350-352are formed in the openings340-342, respectively. In the embodiments illustrated, the metal gates350-352are P-type metal gates, similar to the metal gate of the PMOS transistor35B ofFIG. 1. Thus, the metal gates350-352each include a P-type work function metal, similar to the work function layer120B ofFIG. 1. The metal gates350-352may be formed by one or more deposition processes known in the art. Following the deposition processes, a polishing process such as a CMP process may be performed to planarize the surface of the metal gates350-352.

Referring now toFIG. 8, the segments220B-222B of the dummy gates are removed, thereby forming openings360-362. The removal of the segments220B-222B may be carried out using an etching process. Meanwhile, the metal gates350-352still remain after the segments220B-222B are removed.

Referring now toFIG. 9, metal gates370-372are formed in the openings360-362, respectively. In the embodiments illustrated, the metal gates370-372are N-type metal gates, similar to the metal gate of the NMOS transistor35A ofFIG. 1. Thus, the metal gates370-372each include an N-type work function metal, similar to the work function layer120A ofFIG. 1. The metal gates370-372may be formed by one or more deposition processes known in the art. Following the deposition processes, a polishing process such as a CMP process may be performed to planarize the surface of the metal gates370-372. At this stage of fabrication, the dummy polysilicon gates220-222have been replaced by the metal gates350-352and370-372.

N/P boundaries380-382are formed between the metal gates350-352and the metal gates370-372, respectively. Similar to the N/P boundary150, the N/P boundaries380-382represent the boundaries or interfaces between PMOS transistor gates and NMOS transistor gates. Distances390-392separate the N/P boundaries380-382from the edge of the active region230underneath (or intersecting with) the metal gates350-352, respectively. In a cross-sectional view, the distances390-392each correspond to the distance160ofFIG. 1. The active region230underneath the metal gates350-353is a P-type doped active region in the illustrated embodiments.

Metal diffusion across these boundaries380-382is undesirable and therefore should be minimized. In particular, diffusion from the NMOS transistor gates (corresponding to metal gates370-372herein) to the PMOS transistor gates (corresponding to metal gates350-352) is more likely to occur, and therefore is of greater concern. According to the various aspects of the present disclosure, the distances390-392should be optimized. The optimization of the distances involves avoiding having one of the distances390-392being significantly shorter than the rest. Had a traditional patterning process been used to form the metal gates350-352, the line-end rounding effect may occur, which would likely result in the distance392being shorter than the distances390-391. This is undesirable, since as discussed above with reference toFIGS. 1-2, such short distance between the N/P boundary and the active region would increase the amount of threshold voltage variation for the transistor corresponding to the metal gates352and372(i.e., the outer-most transistor).

In comparison, the present disclosure utilizes an OPC technique to form metal gates350-352such that the outer-most metal gate352is longer than the rest of the metal gates350-351. In other words, the distance392is greater than the distances390-391. In some embodiments, a ratio of the distance392to the distances390or391is greater than 1:1 but less than 1.5:1. Having a greater distance392than the distances390-391does not tend to adversely impact the threshold voltage, because asFIG. 2shows, as the distance D increases, the amount of threshold voltage shift decreases (e.g., approaching zero eventually). This is because as the distance between the N/P boundary and the active region increases, it becomes harder and harder for undesirable diffusion across the N/P boundary to occur. Therefore, the present disclosure offers the benefit of reducing the amount of threshold voltage shift.

It is understood that additional processes may be performed to complete the fabrication of the high-k metal gate semiconductor device. For example, these additional processes may include deposition of passivation layers, formation of contacts, and formation of interconnect structures (e.g., lines and vias, metal layers, and interlayer dielectric that provide electrical interconnection to the device including the formed metal gate). For the sake of simplicity, these additional processes are not described herein.

The embodiments discussed above with reference toFIGS. 3-9illustrate a “gate last” approach of a gate replacement fabrication process. It is understood that the various aspects of the present disclosure may also apply to a “high-k last” approach of the gate replacement process. In the high-k last process, a silicon oxide gate dielectric layer is formed first instead of a high-k dielectric gate dielectric. The oxide gate dielectric layer in the high-k last process also serves as a dummy layer and will be removed later along with the dummy polysilicon gate electrodes. A high-k dielectric layer may then be formed to replace the dummy silicon oxide gate dielectric layer. It is understood that the aspects of the present disclosure may apply to both a gate-last approach or a high-k last approach.

In addition, though the embodiments discussed above illustrate a process in which the PMOS metal gates are formed first, it is understood that NMOS metal gates may be formed first in alternative embodiments. For example, whereas the mask layer250may contain a positive photoresist, a negative photoresist mask may be employed, such that the contour260may protect the dummy polysilicon gates therebelow instead of exposing them. The dummy gate segments outside the contour may be removed and replaced with NMOS metal gates, and subsequently the PMOS metal gates may be formed. Once again, the aspects of the present disclosure may apply regardless of whether the PMOS gates are formed first or the NMOS gates are formed first.

FIG. 10is a method400of fabricating a semiconductor device according to various aspects of the present disclosure. Referring toFIG. 1, the method400includes a block410, in which a first dummy gate and a second dummy gate are formed over a substrate. In some embodiments, the first and second dummy gates each include a dummy polysilicon gate electrode. The method400includes a block420, in which a patterned mask is formed over the first and second dummy gates. The patterned mask exposes a first segment of the first dummy gate and a second segment of the second dummy gate, while covering a third segment of the first dummy gate and a fourth segment of the second dummy gate. The mask is formed in a manner such that the first and second segments have significantly different lengths. The method400includes a block430, in which the first segment and the second segment are replaced with a first metal gate and a second metal gate, respectively. The first and second metal gates contain a first type metal material. The method400includes a block440, in which the third segment and the fourth segment are replaced with a third metal gate and a fourth metal gate, respectively. The third and fourth metal gates contain a second type metal material different from the first type.

Based on the above discussions, it can be seen that the present disclosure offers advantages over conventional methods. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiment. One advantage is that the N/P boundary effect can be suppressed. Using an OPC technique, the distance between the N/P boundary and the active region for an outer-most metal gate can be lengthened to be as great as the other distances between the active region and other metal gates. Thus, the threshold voltage shift is significantly reduced. Another advantage is that the process of the present disclosure is fully compatible with existing process flow, and thus no additional fabrication process (or related fabrication equipment) is needed. Therefore, the present disclosure requires no extra fabrication costs. Yet one more advantage is that the customers designing the layout of the ICs need not revise their original layout designs, since the OPC features can be added and implemented by a foundry during fabrication.