Gallium nitride transistor with improved termination structure

A gallium nitride transistor includes one or more P-type hole injection structures that are positioned between the gate and the drain. The P-type hole injection structures are configured to inject holes in the transistor channel to combine with trapped carriers (e.g., electrons) so the electrical conductivity of the channel is less susceptible to previous voltage potentials applied to the transistor.

FIELD

The present invention relates generally to semiconductor devices and in particular to Gallium Nitride (GaN) based devices.

BACKGROUND

In semiconductor technology, GaN is used to form various integrated circuit devices, such as high power field-effect transistors, metal insulator semiconductor field effect transistors (MISFETs), high frequency transistors, high power Schottky rectifiers, and high electron mobility transistors (HEMTs). These devices can be formed by growing epitaxial layers, which can be grown on silicon, silicon carbide, sapphire, gallium nitride, or other substrates. Often, devices are formed using a heteroepitaxial junction of AlGaN and GaN. This structure is known to form a high electron mobility two-dimensional electron gas (2DEG) at the junction. Sometimes additional layers are added to improve or modify the charge density and mobility of electrons in the 2DEG. In some applications it may be desirable to have improved termination structures that improve the reliability and/or performance of GaN devices.

SUMMARY

Some embodiments of the present disclosure relate to gallium-nitride (GaN) based transistors that include one or more hole injection structures to mitigate the effects of trapped carriers that result in current collapse. A GaN transistor includes source, gate and drain connections to the substrate. A channel is formed between the source and the drain and current flow through the channel allowed or blocked depending on a voltage potential applied between the source and the gate. One or more P-type structures are formed on the substrate and positioned in the channel. The P-type structures are configured to inject holes in the channel to combine with and neutralize trapped carriers. The neutralization of the trapped carriers enables the channel to be more conductive and less susceptible to previous voltage potentials applied to the transistor.

In some embodiments a transistor comprises a semiconductor substrate and a source region formed in the substrate and including a source electrode in contact with a portion of the substrate. A drain region is formed in the substrate and is separated from the source region. A gate region is formed in the substrate and includes a gate stack in contact with a portion of the substrate, wherein the gate region is positioned between the source region and the drain region. A hole injection region is formed in the substrate and includes a P-type layer in contact with a portion of the substrate, wherein the hole injection region is positioned between the gate region and the drain region. A dielectric layer is formed over and in contact with a first portion of the P-type layer. A continuous metal layer is (1) formed over and in contact with the drain region of the substrate to form a drain electrode, (2) formed over and in contact with a second portion of the P-type layer to form a hole injection electrode, and (3) formed over and in contact with a portion of the dielectric layer to form a field plate for the hole injection region.

In some embodiments the continuous metal layer extends across the drain region of the substrate, abuts a first side surface of the P-type layer and extends across a first region of a top surface of the P-type layer. In various embodiments the dielectric layer extends across a surface of the substrate, abuts a second side surface of the P-type layer and extends across a second region of the top surface of the P-type layer. In some embodiments the field plate extends across the dielectric layer and terminates before becoming coplanar with the second side surface of the P-type layer.

In some embodiments the continuous metal layer is in ohmic contact with the P-type layer. In various embodiments the transistor further comprises a plurality of individual hole injection regions formed along a length of the drain region. In various embodiments the hole injection region is a first hole injection region and a second hole injection region is formed in the substrate and positioned between the first hole injection region and the gate region.

In some embodiments the second hole injection region includes a P-type layer that is in contact with a portion of the substrate and is not in ohmic contact with the continuous metal layer. In various embodiments the continuous metal layer is formed over approximately one half of a top surface of the P-type layer and the dielectric layer is formed over a remaining portion of the top surface of the P-type layer. In some embodiments the semiconductor substrate comprises gallium nitride.

In some embodiments a transistor comprises a semiconductor substrate and a source region formed in the substrate and including a source electrode in contact with a portion of the substrate. A drain region is formed in the substrate and is separated from the source region. A gate region is formed in the substrate and includes a gate stack in contact with a portion of the substrate, wherein the gate region is positioned between the source region and the drain region. A hole injection region is formed in the substrate and includes a P-type layer in contact with a portion of the substrate, wherein the hole injection region is positioned between the gate region and the drain region. A dielectric layer extends across a first region of a top surface of the P-type layer. A metal layer (1) extends across a drain region of the substrate to form a drain electrode, (2) extends across a second region of the top surface of the P-type layer to form a hole injection electrode, and (3) extends across a portion of the dielectric layer to form a field plate.

In some embodiments the field plate is a hole injection region field plate. In various embodiments the metal layer extends across the drain region of the substrate, abuts a first side surface of the P-type layer and extends across the second region of the top surface of the P-type layer to form the hole injection electrode. In some embodiments the dielectric layer extends across a surface of the substrate, abuts a second side surface of the P-type layer and extends across the first region of the top surface of the P-type layer. In various embodiments the field plate extends across the first region of the dielectric layer and terminates before becoming coplanar with the second side surface of the P-type layer.

In some embodiments the metal layer is in ohmic contact with the P-type layer. In various embodiments the transistor further comprises a plurality of individual hole injection regions formed along a length of the drain region. In some embodiments the hole injection region is a first hole injection region and a second hole injection region is formed in the substrate and is positioned between the first hole injection region and the gate region. In various embodiments the second hole injection region includes a P-type layer that is in contact with a portion of the substrate and is not in ohmic contact with the continuous metal layer.

In some embodiments a transistor comprises a semiconductor substrate and a source region formed in the substrate and including a source electrode in contact with a portion of the substrate. A drain region is formed in the substrate and is separated from the source region. A gate region is formed in the substrate and includes a gate stack in contact with a portion of the substrate, wherein the gate region is positioned between the source region and the drain region. A floating hole injection region is formed in the substrate and includes a P-type layer in contact with a portion of the substrate, wherein the hole injection region is positioned between the gate region and the drain region.

To better understand the nature and advantages of the present disclosure, reference should be made to the following description and the accompanying figures. It is to be understood, however, that each of the figures is provided for the purpose of illustration only and is not intended as a definition of the limits of the scope of the present disclosure. Also, as a general rule, and unless it is evident to the contrary from the description, where elements in different figures use identical reference numbers, the elements are generally either identical or at least similar in function or purpose.

DETAILED DESCRIPTION

Certain embodiments of the present invention relate to GaN-based enhancement-mode field effect transistors having hole injection structures that inject holes in the channel to mitigate “current collapse” in the transistor. Current collapse is an undesirable “memory” effect where the conduction current of the device can be dependent on previously applied voltages, and also on how long these previously applied voltages were present. More specifically, during transistor operation, electrons can get trapped (known as trapped carriers) in epitaxial and/or dielectric layers and repel other electrons flowing through the transistor channel, making it more difficult to conduct current through the 2DEG layer, resulting in an increase in resistance through the channel. In some embodiments the addition of one or more hole injection structures are used to inject holes in the channel so the holes combine with and neutralize the trapped electrons. The reduction of trapped electrons results in a lower electrical resistance in the channel, mitigating the memory effect.

Some embodiments of the present disclosure relate to GaN-based transistors having P-type hole injection structures formed adjacent the drain contact. Hole injection electrodes can be formed on the P-type hole injection structures so the hole injection electrodes are electrically coupled to the drain ohmic metal. In other embodiments the P-type hole injection structures can be electrically insulated from the drain ohmic metal and can be capacitively coupled to the drain ohmic metal.

In order to better appreciate the features and aspects of GaN-based transistors having P-type hole injection structures according to the present disclosure, further context for the disclosure is provided in the following section by discussing several particular implementations of semiconductor devices according to embodiments of the present disclosure. These embodiments are for example only and other embodiments can be employed in other semiconductor devices such as, but not limited to gallium-arsenide, indium-phosphide and other types of semiconductor materials.

FIG. 1illustrates a simplified plan view of a GaN-based semiconductor transistor100. As shown inFIG. 1, transistor100is constructed on a substrate105. Transistor100can have an active region110surrounded by an inactive region115that includes a source terminal120, a gate terminal125and a drain terminal130that are used to form electrical connections to the transistor. Active region110can have one or more transistor “cells” that are repeated across the active region, as discussed in greater detail herein. Transistor100is an illustrative example of a GaN transistor having hole injectors in accordance with embodiments of this disclosure, however, a person of skill in the art will appreciate that in other embodiments, GaN transistor100can have a size, shape and configuration different than the specific examples set forth herein and this disclosure is in no way limited to the examples set forth herein.

FIG. 2illustrates a magnified partial plan view of a drain region220of a GaN-based transistor that may form a portion of active region110of transistor100inFIG. 1.FIG. 3illustrates a partial cross-sectional view across line A-A of drain region220ofFIG. 2and also shows a cross-sectional view of source region210and gate region215of transistor cell205. The following description will simultaneously refer toFIGS. 2 and 3.

In some embodiments a drift region225is disposed between source region210and drain region220in order to withstand high voltage. A channel region is formed in the 2DEG under the gate stack320and is configured to block or conduct current depending on an applied voltage between gate terminal125(seeFIG. 1) and source terminal120. One or more hole injectors230are disposed adjacent drift region225and are configured to inject holes into the channel to combine with trapped electrons, as described in more detail below.

As illustrated inFIG. 3, in some embodiments substrate105can include a first layer305that can include silicon carbide, sapphire, aluminum nitride or other material. A second layer310is disposed on first layer305and can include gallium nitride or other material. A third layer315is disposed on second layer310and can include a composite stack of other III nitrides such as, but not limited to, aluminum nitride, indium nitride and III nitride alloys such as aluminum gallium nitride and indium gallium nitride. In one embodiment third layer315is Al0.20Ga0.80N.

In some embodiments, a two-dimensional electron gas (2DEG) inducing layer is formed within substrate105and can be positioned proximate an interface between second layer310and third layer315. In some embodiments, the 2DEG layer is induced by a combination of piezoelectric effect (stress), bandgap differential, and/or polarization charge. For example, there may be a reduction in the conduction band at the surface, where it drops below the fermi level to create a potential well which fills with electrons. In some embodiments, the 2DEG inducing layer comprises AlGaN in a range, for example, of Al0.25Ga0.75N about 20 nanometers thick. In alternative embodiments, the 2DEG inducing layer can comprise AlN, AlGaInN, or another material. In some embodiments, the 2DEG inducing layer comprises a thin boundary layer with high Al content and a thicker layer with less Al content. In some embodiments the 2DEG inducing layer can have a GaN cap layer while in other embodiments the 2DEG inducing layer does not have a GaN cap layer.

In some embodiments one or more gate stacks320are formed on substrate105to form gate structures. For example, gate stack320can include several layers of compound semiconductors that each can include nitrogen and one or more elements from column three of the periodic table, such as aluminum or gallium or indium or others (e.g., 3N layers). These layers can be doped or undoped. If they are doped they can be doped with either N-type or P-type dopants. In some embodiments, gate stack320can be an insulated gate, Schottky gate, PN gate, recessed gate, or other type of gate.

In some embodiments one or more hole injectors230are formed on substrate105. Hole injectors230can be formed with a P-type structure325disposed on substrate105. In some embodiments P-type structure325can be formed using gallium nitride that is doped with a P-type dopant, that can be as a non-limiting example, magnesium. P-type structure325can act as a hole injector during operation of the semiconductor device to improve performance and/or reliability of transistor100, as described in more detail herein.

An ohmic metal layer323can be deposited and patterned to form ohmic contacts to substrate105including a source ohmic contact327formed between source ohmic pad330and substrate105, and a drain ohmic contact333formed between drain ohmic pad335and substrate105, and other regions as necessary. In some embodiments ohmic metal layer323can include aluminum, titanium, nickel, gold or other metal. After ohmic metal layer323is deposited and patterned, the ohmic metal layer can be annealed to form low resistance electrical connections between the remaining ohmic metal and the 2DEG inducing layer that can be exposed in the ohmic contact regions (e.g., the source and the drain).

Additional sequentially deposited metal layers can include MG layer (gate metal layer)340, M0layer345, M1layer350, M2layer355and so on can be patterned using commercially available processes. To electrically insulate metal layers340,345,350and355from one another and/or from substrate105, one or more intervening dielectric layers can used. In some embodiments dielectric layers can include, but are not limited to, silicon nitride (e.g., Si3N4, Si2N, or SN) or Silicon oxide (e.g. SiO2 or similar) which can be deposited and patterned. In some embodiments, the intervening dielectric layers each comprise only a single layer of insulator material while in other embodiments each layer can comprise a plurality of layers. The insulator layers can be planarized, using, for example, chemo-mechanical polishing, or other techniques.

In some embodiments, MG layer340can be used to form a MG source field plate365, gate electrode370, and hole injection electrode375. In various embodiments, hole injection electrode375can be positioned immediately adjacent to and in electrical contact with drain ohmic pad335so hole injector230has substantially a same voltage as drain ohmic pad335.

In some embodiments, M0layer345can be used to form M0source field plate380and M0drain field plate385. In various embodiments, M1layer350can be used to form M1source field plate390and M1intermediate drain plate395. In some embodiments, M2layer355can be used to form source bus235, gate bus240and drain bus245. Source bus235electrically couples source ohmic pad330of each transistor cell205to source terminal120(seeFIG. 1). Gate bus240electrically couples gate electrode370of each transistor cell205to gate terminal125(seeFIG. 1). Drain bus245electrically couples drain ohmic pad335of each transistor cell205to drain terminal130(seeFIG. 1).

In some embodiments, one or more vias360can be formed through one or more of the intervening insulator layers to electrically connect one or more metal layers340,345,350and355to one another.

In some embodiments transistor100reacts to an applied electrical field under gate stack320to control an electrical conductivity of the 2DEG channel underneath. The electrical conductivity of the channel is a function of a voltage potential applied between gate terminal125(seeFIG. 1) and source terminal120. Gate terminal125can be thought of as controlling the opening and closing of a physical gate. The voltage applied to gate terminal125permits electrons and/or holes to flow between the source terminal120and drain terminal130, or blocks their passage, by creating or eliminating the 2DEG channel under the gate. The electrical conductivity of the channel is influenced by the magnitude of the applied voltage potential between gate terminal125(seeFIG. 1) and source terminal120.

In some embodiments, during operation of transistor100, electrons can get trapped in the epitaxial or dielectric layers (commonly referred to as “trapped carriers”) within substrate105and repel electrons flowing through drift region225, increasing the resistance to current to flowing between source terminal120and drain terminal130. This phenomenon can result in an increase in electrical resistance in drift region225(e.g., an increase in RDSON) and is commonly referred to as “dynamic Rdson” or “current collapse”. Dynamic Rdson is an undesirable “memory” effect where the conduction current of the device can be dependent on previously applied voltages between source terminal120and drain terminal130, and also on how long these previously applied voltages were present.

More specifically, the electrical resistance of drift region225can increase for a certain period of time when the transistor is turned on again after being turned off. To prevent dynamic Rdson increase, in the embodiment illustrated inFIGS. 1 and 2, a plurality of hole injector230islands of P-type GaN are placed immediately adjacent drain ohmic pad335and are electrically coupled to the drain ohmic metal with hole injection electrodes375formed in MG layer340. Each hole injector230inject holes in the drift region225near the drain region220. The holes combine with trapped electrons to neutralize them, preventing, or at least mitigating current collapse.

In one embodiment each hole injector230island can be between 0.5 and 5 microns square, while in other embodiments each island can be between 0.75 and 2 microns square and in one embodiment each island is between 0.9 and 1.1 microns square, however one of skill in the art will appreciate that the invention is not limited to square geometries or the aforementioned dimensions and hole injectors having other geometries and/or dimensions can be used.

As discussed above with regard toFIG. 1, transistor100can be arranged in repeating cells, an example of which is illustrated inFIGS. 2 and 3. Each cell can include a source, a gate, a drain and one or more hole injection structures. An adjacent cell can use the same drain and may have its own gate and source terminations. Similarly, an adjacent cell can use the same source and have its own drain termination. In some embodiments a transistor structure includes a plurality of interdigitated source and drain fingers, with a gate structure disposed between each source and drain finger. Therefore, as shown inFIG. 3, a drift region225can be formed on either side of drain region220.

FIG. 4illustrates a simplified plan view of drain region220of a GaN-based transistor400according to another embodiment of the disclosure. Transistor400is constructed similar to transistor100illustrated inFIGS. 1-3(with like numbers referring to like elements), however transistor400has a plurality of capacitively coupled hole injectors, as described in more detail below.FIG. 5illustrates a partial cross-sectional view across transistor400, with the cross-section made in a similar region of the transistor as the cross-section illustrated inFIG. 3(with like numbers referring to like elements). The following description will simultaneously refer toFIGS. 4 and 5.

Similar to the embodiment illustrated inFIGS. 1-3, transistor400includes one or more hole injectors430formed on substrate105. Hole injectors430can be formed with a P-type structure325disposed on substrate105. In some embodiments P-type structure325can be formed using a combination of aluminum gallium nitride or gallium nitride which are doped with a p-type dopant such as magnesium. P-type structure325can act as a hole injector during operation of the semiconductor device to improve performance and/or reliability of transistor400, as described in more detail herein.

In comparison with transistor100inFIGS. 1-3, transistor400inFIGS. 4 and 5includes hole injectors430, but does not have hole injection electrodes375(seeFIG. 3) and hole injectors430are spaced away from drain ohmic pad335such that hole injectors430are electrically insulated from the drain ohmic pad335. More specifically, hole injectors430of transistor400only include P-type structures325and do not include hole injector electrodes (e.g., there is no metal on top of P-type structure325). Further, hole injectors430of transistor400include a gap450positioned between P-type structures325and drain ohmic pad335, where the gap is filled with a dielectric material resulting in electrically floating hole injectors. As used herein, the term “floating hole injectors” shall mean that the hole injection structures (e.g., P-type GaN regions) are not ohmically coupled to source, gate or drain electrodes but instead use capacitive coupling or a combination of capacitive coupling and leakage current to enable the floating hole injectors to inject holes in drift region225.

FIG. 6illustrates a simplified plan view of drain region220of a GaN-based transistor600according to another embodiment of the disclosure. Transistor600is constructed similar to transistor100illustrated inFIGS. 1-3(with like numbers referring to like elements), however transistor600has a plurality of hole injectors630in the shape of stripes and the drain ohmic metal functions as both a drain ohmic electrode and a hole injector electrode, as described in more detail below.FIG. 7illustrates a partial cross-sectional view across transistor600, with the cross-section made in a similar region of the transistor as the cross-section illustrated inFIG. 3(with like numbers referring to like elements). The following description will simultaneously refer toFIGS. 6 and 7.

Similar to the embodiment illustrated inFIGS. 1-3, transistor600includes one or more hole injectors630formed on substrate105. Hole injectors630can be formed with a P-type structure325disposed on substrate105, however instead of being square islands positioned on either side of drain contact333, the P-type structures are arranged in repetitive stripes that extend across the drain contact and into drift regions225formed on either side of the drain contact.

In comparison with transistor100inFIGS. 1-3, transistor600inFIGS. 6 and 7includes hole injectors630, but does not have separately formed hole injection electrodes375as shown inFIG. 3. More specifically, drain ohmic pad335forms both the drain ohmic contact333and a hole injection electrode. This is illustrated more clearly inFIG. 8which is cross-section B-B of transistor600illustrated inFIG. 7. As shown inFIG. 8, repetitive P-type structures325are formed on substrate105. Drain ohmic pad335contacts both drain contact333as well as P-type structure contact805. Therefore drain ohmic pad335electrically couples P-type structures325to drain contact333.

FIG. 9illustrates a partial cross-sectional view of a GaN-based transistor900according to another embodiment of the disclosure. Transistor900is constructed similar to transistor600illustrated inFIGS. 6-8(with like numbers referring to like elements), however transistor900has a dielectric layer905formed over P-type structures325that are in the shape of stripes and drain ohmic pad335functions as both a drain ohmic electrode and a hole injector electrode, as described in more detail below.FIG. 10illustrates a partial cross-sectional view C-C across transistor900illustrated inFIG. 9. The following description will simultaneously refer toFIGS. 9 and 10.

Similar to the embodiment illustrated inFIGS. 6-8, transistor900includes one or more hole injectors930formed on substrate105. Hole injectors930can be formed with a P-type structure325disposed on substrate105. P-type structures325can be arranged in repetitive stripes that extend across drain contact333and into drift regions225formed on either side of the drain contact.

In comparison with transistor600inFIGS. 6-8, transistor900inFIGS. 9 and 10includes a dielectric layer905formed over P-type structures325and portions of substrate105. Openings910are formed in dielectric layer905and drain ohmic pad335is formed on top of the dielectric layer and within openings910to make electrical contact with P-type structures325. In some embodiments openings910can extend across a spacing between P-type structures325exposing portions of substrate105so drain ohmic pad335can form a drain contact333between each P-type structure. Other embodiments may have a different configuration of openings formed in dielectric layer905so that drain ohmic pad335can form both a hole injector electrode and a drain electrode. Since drain ohmic pad335contacts both drain contact333as well as P-type structure325the drain ohmic metal layer electrically couples P-type structures325to drain contact333.

FIG. 11illustrates a partial cross-sectional view of a GaN-based transistor1100according to another embodiment of the disclosure. Transistor1100is constructed similar to transistor900illustrated inFIGS. 9 and 10(with like numbers referring to like elements), however transistor1100has two separate P-type structures325with a gap in-between for drain contact333, as described in more detail below.

Similar to the embodiment illustrated inFIGS. 9 and 10, transistor1100includes one or more hole injectors1130formed on substrate105. Hole injectors1130can be formed with a P-type structure325disposed on substrate105. P-type structures325can be arranged in repetitive islands that are disposed on either side of drain contact333. Transistor1100includes a dielectric layer1105that covers an entirety of each P-type structure325so it is electrically insulated from drain ohmic pad335. Drain ohmic pad335extends between P-type structures325to contact substrate105forming drain contact333. Drain ohmic pad335also extends over top of P-type structures325, with dielectric layer1105positioned between the drain ohmic metal layer and the P-type structures. Thus, hole injectors1130are electrically insulated from drain ohmic pad335and the hole injectors use capacitive coupling to drain ohmic pad335to enable P-type structures325to inject holes in drift region225.

Continuing to refer toFIG. 11, in some embodiments electrical fields at a drain-edge of source field plates365,380and/or390can be higher than surrounding areas and as a result these regions can result in a higher concentration of trapped carriers in drift region225. Therefore, in some embodiments positioning one or more floating P-type GaN structures1110a. . .1110caligned with the drain-edge of source field plates365,380and/or390can result in efficient and/or effective neutralization of trapped carriers in drift region225.

More specifically, in some embodiments floating P-type GaN structures1110a. . .1110care configured to inject holes in drift region225when in the presence of high electrical fields, as described in further detail herein and inFIGS. 13 and 14. In some embodiments floating P-type GaN structures1110a. . .1110ccan be formed using gallium nitride that is doped with a P-type dopant that can be, for example, magnesium.

FIG. 12illustrates a simplified plan view of a GaN-based transistor1200according to another embodiment of the disclosure. Transistor1200is constructed similar to transistor1100illustrated inFIG. 11(with like numbers referring to like elements), however instead of having a plurality of floating P-type GaN structures under each of three source field plates,365,380,390, transistor1200has a plurality of floating P-type GaN structures1205positioned under and aligned with a drain-edge of only source field plate380. More specifically, in the embodiment illustrated inFIG. 12, plurality of floating P-type GaN structures1205are positioned partially under M0source field plate380and fully under M1source field plate390, in drift region225. In other embodiments floating P-type GaN structures1205can be placed within drift region225in a different position than is shown inFIG. 12. In some embodiments, floating P-type GaN structures1205can perform the same function as P-type GaN structures325(seeFIG. 11) described in more detail above. In some embodiments floating P-type GaN structures1205can be formed using gallium nitride that is doped with a P-type dopant, that can be, for example, magnesium.

FIG. 13illustrates a simplified plan view of a GaN-based transistor1300according to another embodiment of the disclosure. Transistor1300is constructed similar to transistor1100illustrated inFIG. 11(with like numbers referring to like elements), however instead of having a plurality of floating P-type GaN structures under each of three source field plates,365,380,390, transistor1300has a plurality of floating P-type GaN structures1305positioned under and aligned with a drain-edge of only source field plate390. More specifically, in the embodiment illustrated inFIG. 13, plurality of floating P-type GaN structures1305are positioned partially under M1source field plate390, in drift region225. In other embodiments floating P-type GaN structures1305can be placed within drift region225in a different position than is shown inFIG. 13. In some embodiments, floating P-type GaN structures1305can perform the same function as P-type GaN structures325(seeFIG. 11) described in more detail above. In some embodiments floating P-type GaN structures1305can be formed using gallium nitride that is doped with a P-type dopant, that can be, for example, magnesium.

FIG. 14illustrates a simplified plan view of a GaN-based transistor1400according to another embodiment of the disclosure. Transistor1400is constructed similar to transistor100illustrated inFIGS. 1-3(with like numbers referring to like elements), however transistor1400has a plurality of P-type GaN structures1405positioned next to gate electrode370within drift region225, adjacent and under source field plates365,380and390. In the embodiment illustrated inFIG. 14, P-type GaN structures1405are centered on a first edge of MG source field plate365that is closest to gate electrode370, however in other embodiments they can be located at any position adjacent gate electrode370.

In some embodiments, P-type GaN structures1405can assume a potential close to the gate electrode by capacitive coupling or leakage. Trapping of electrons can be caused by high electric fields accelerating hot electrons into dielectrics or substrate regions. The P-type GaN structures1405can prevent the high voltage and high electric field in the drift region from reaching the gate region and reduce the amount of trapping that occurs in that region. This reduced carrier injection can reduce the Dynamic Rdson effect and improve the life of the product. Although transistor1400is similar to transistor100illustrated inFIGS. 1-3, it will be appreciated by one of skill in the art that transistor1400can have a different structure, including that of transistors400,600,900or1100shown in the previous figures, or any other configuration.

FIG. 15illustrates a partial cross-sectional view of a GaN-based transistor1500according to another embodiment of the disclosure. Transistor1500is constructed similar to transistor1100illustrated inFIG. 11(with like numbers referring to like elements) including a P-type structure ohmically coupled to the drain terminal, however transistor1500has a dielectric layer1510that only covers a portion of the P-type structure325and drain ohmic pad335is in ohmic contact with the P-type structure, as described in more detail below. Additionally, transistor1500includes a floating hole injector1545positioned on a source side of drain contact333.

Similar to the embodiment illustrated inFIG. 11, transistor1500includes one or more hole injectors1530formed on substrate105. Each hole injector1530can be formed with a P-type structure325disposed on substrate105. InFIG. 15a line of symmetry1535is used to show only a left-side portion of the drain region and a right-side portion is a mirror image of the right-side portion. P-type structures325can be arranged in repetitive islands that are disposed on both sides (i.e., left and right-sides of drain contact333.

Transistor1500includes a dielectric layer1510that covers a portion of each P-type structure325, with a remaining portion of each P-type structure forming an ohmic contact region1505with drain ohmic pad335. In the embodiment illustrated inFIG. 15, dielectric layer1510covers approximately one half of P-type structure325however in other embodiments it can cover more than half or less than half of the P-type structure.

In some embodiments, drain ohmic pad335can be configured as a continuous metal layer that is (1) formed over and in contact with drain region220of substrate105to form a drain electrode333, (2) formed over and in contact with a second portion of P-type layer325to form a hole injection electrode375, and (3) formed over and in contact with a portion of dielectric layer1510to form a field plate1515for the hole injection region. In other embodiments one or more separate, but electrically coupled metal layers can be used in place of the aforementioned continuous metal layer. In the embodiment illustrated inFIG. 15, field plate1515extends across at least a portion of dielectric layer1510, and in some embodiments extends until it is coplanar with a source-side edge1550of P-type layer325while in other embodiments it extends past the source-side edge of P-type layer325. In one embodiment field plate1515extends past source-side edge1550of P-type layer between 0.125 microns and 2 microns, while in other embodiments it extends past between 0.2 and 0.75 microns.

In some embodiments a plurality of individual hole injectors1530are formed along a length of drain region220forming a series of sequential hole injector islands. Drain ohmic pad335may also extend in-between the individual P-type structures325to contact substrate105forming portions of drain contact333, similar to the structure illustrated inFIG. 10.

In some embodiments a second field plate385can be positioned above field plate1515, and a third field plate395can be positioned above the second field plate. The distal ends of field plates1515,385and395can result in regions of high field strength1540that are identified by dashed circles.

In some embodiments an optional floating hole injector1545can be formed from a portion of P-type layer325. Floating hole injector1545is not ohmically coupled to drain ohmic pad335and may be capacitively coupled to the drain ohmic pad. Floating hole injector1545may be positioned between hole injector1530and the gate region (seeFIG. 11).

FIG. 16illustrates a plan view of a GaN-based transistor1600according to another embodiment of the disclosure. Transistor1600is constructed similar to transistor100illustrated inFIGS. 1-3, however transistor1600includes a gate structure that is formed using P-type GaN islands, as described in more detail below. GaN-based transistor1600is fabricated on substrate1605that can be similar to substrate105inFIG. 1, and can include a source ohmic metal pad1610and a drain ohmic metal pad1620with a gate electrode1615and an active 2DEG region1625there between. Under gate electrode1615one or more P-type GaN islands1630a,1630bwith gaps there-between can be disposed on substrate1605. In various embodiments a single gate electrode1615can be formed across the one or more P-type GaN islands1630a,1630band a contact between the gate electrode and the P-type GaN islands can be formed.

When zero voltage is applied to gate electrode1615with respect to source ohmic metal pad1610, current flows through the 2DEG layer between the P-type GaN islands1630a,1630bin region1635. When a positive gate voltage is applied, a 2DEG is formed under the P-type GaN islands1630a,1630b, and current can flow across the entire width of the active 2DEG region under the gate. If gate electrode1615is biased negative with respect to source ohmic metal pad1610, the gap between the P-type GaN islands1630a,1630bwill form a reverse biased junction around the P-type GaN islands. This reverse-biased condition forms a depletion region around each P-type GaN island1630a,1630band limits the electron flow through region1635. The more negative gate electrode1615is biased relative to source ohmic metal pad1610the more resistive region1635becomes until transistor1600pinches off all current flow. Therefore, P-type GaN islands1630a,1630bform a gate structure that controls current flow through the transistor channel. This also allows the structure to block voltage applied to the drain1620and so limits the electric field on the source side of the gate. This is a similar electric field limiting effect that is accomplished by the P-type GaN structures1205illustrated inFIG. 12.