Generating local oscillator signals in a wireless sensor device

In some aspects, a local oscillator includes a voltage controlled oscillator, a multi-stage frequency divider including first and second stages, and a duty-cycle converter. An output node of the voltage controlled oscillator is coupled to an input node of the first stage. An output node of the first stage is coupled to an input node of the second stage. The first stage is configured to output a first signal from one of a first plurality of signal paths, each configured to provide a signal having a distinct frequency. The second stage is configured to output a second signal from one of a second plurality of signal paths, each configured to provide a signal having a distinct frequency. An output node of the multi-stage frequency divider is coupled to an input node of the duty-cycle converter.

BACKGROUND

The following description relates to generating local oscillator signals in a wireless sensor device.

Many wireless devices detect radio frequency (RF) signals and down-convert them to a lower frequency for signal processing. Many wireless devices can also up-convert baseband signals to a higher frequency for signal transmission. The signals can be up-converted or down-converted by a mixer that uses a reference signal from a local oscillator. The local oscillator may include a voltage controlled oscillator that generates the reference signal.

DETAILED DESCRIPTION

The following description relates generally to local oscillators (LOs). The example local oscillators described here can be used, for example, in a wireless sensor device, or in other contexts. In some cases, the techniques and systems described here are used in integrated circuit RF transmitters, receivers and transceivers for a wide-band, multi-standard radio applications.

In some implementations, a local oscillator includes a voltage controlled oscillator (VCO), and circuitry that is changeable to produce any of multiple different frequency outputs based on the VCO signal. For example, the circuitry can include a frequency divider circuit that can divide the frequency of the VCO signal by an integer (e.g., 2, 4, 8, or another integer) that is controlled by control signals. In some cases, the frequency divider circuit has a single output node that can provide references signals at multiple different frequencies (e.g., fVCO/2, fVCO/4, fVCO/8, etc., where fVCOrepresents the frequency of the VCO signal). For example, the output node may be communicatively coupled to a duty-cycle converter that generates an output of the local oscillator based on the reference signal from the frequency divider circuit. In some cases, the frequency divider circuit has a single input node that receives the VCO signal at the VCO frequency (fVCO). The frequency divider may also include switches that receive the control signals, and circuitry that generates the reference signal from the VCO signal. In some examples, the frequency of the reference signal produced by the frequency divider circuit (e.g., fVCO/2, fVCO/4, fVCO/8, etc.) is a quotient of the VCO frequency and a divisor controlled by the control signals. In some examples, the frequency divider circuit is a multi-stage frequency divider that divides the frequency of the VCO signal in a series of stages.

In some implementations, the subject matter described here provides advantages, such as, for example, reducing hardware requirements (e.g., requiring fewer mixers, fewer duty-cycle converters), allowing for a broader range of hardware (e.g., symmetric NOR logic gates), and others. For instance, in some cases, fewer mixers and fewer duty-cycle converters are used for frequency up-conversion or down-conversion across a broad range of frequencies, which can simplify metal routing, reduce a number of transistors used, and reduce circuit area.

FIG. 1is a block diagram showing an example wireless sensor device100. As shown inFIG. 1, the wireless sensor device100includes an antenna system102, a radio frequency (RF) processor system104, and a power supply103. A wireless sensor device may include additional or different features and components, and the components can be arranged as shown or in another manner.

In operation, the wireless sensor device100can detect and analyze wireless signals. In some implementations, the wireless sensor device100can detect signals exchanged according to a wireless communication standard (e.g., for a cellular network), although the wireless sensor device itself may not be part of the cellular network. In some instances, the wireless sensor device100monitors RF signals by “listening” or “watching” for RF signals over a broad range of frequencies and processing the RF signals that it detects. There may be times when no RF signals are detected, and the wireless sensor device100may process RF signals (e.g., from time to time or continuously) as they are detected in the local environment of the wireless sensor device100.

The example antenna system102is coupled with the RF processor system104, for example, by wires, leads, contacts or another type of coupling that allows the antenna system102and the RF processor system104to exchange RF signals. In some instances, the antenna system102wirelessly receives RF signals from the electromagnetic environment of the wireless sensor device100and transfers the RF signals to the RF processor system104to be processed (e.g., digitized, analyzed, stored, retransmitted, etc.). In some instances, the antenna system102receives RF signals from the RF processor system104and wirelessly transmits the RF signals from the wireless sensor device100.

The example RF processor system104can include circuitry that up-converts a baseband signal to an RF signal, that down-converts an RF signal to a baseband signal, or both. Such circuitry can include mixers that utilize a reference signal provided by a local oscillator, which can include a voltage controlled oscillator (VCO). For instance, in some implementations, the RF processor system104includes the example local oscillator400shown inFIG. 4, the example local oscillator shown inFIGS. 7 and 8, or another type of local oscillator. In some examples, a baseband signal can be input into a mixer that also receives an RF reference signal from a local oscillator. The mixer can up-convert the baseband signal to an RF signal. In some examples, an RF signal can be input into a mixer that also receives an RF reference signal from a local oscillator. The mixer can down-convert the RF signal to a baseband signal. The up-conversion and/or down-conversion can be performed by a zero-intermediate frequency (IF) architecture, a direct conversion architecture, a low-IF architecture, or the like.

The example RF processor system104can include one or more chips, chipsets, or other types of devices that are configured to process RF signals. For example, the RF processor system104may include one or more processor devices that are configured to identify and analyze data encoded in RF signals by demodulating and decoding the RF signals transmitted according to various wireless communication standards. In some cases, the RF processor system104can include one or more digital signal processor (DSP) devices, forward error correction (FEC) devices, and possibly other types of processor devices.

In some implementations, the RF processor system104is configured to monitor and analyze signals that are formatted according to one or more communication standards or protocols, for example, 2G standards such as Global System for Mobile (GSM) and Enhanced Data rates for GSM Evolution (EDGE) or EGPRS; 3G standards such as Code Division Multiple Access (CDMA), Universal Mobile Telecommunications System (UMTS), and Time Division Synchronous Code Division Multiple Access (TD-SCDMA); 4G standards such as Long-Term Evolution (LTE) and LTE-Advanced (LTE-A); wireless local area network (WLAN) or WiFi standards such as IEEE 802.11, Bluetooth, near-field communications (NFC), millimeter communications; or multiple of these or other types of wireless communication standards. In some cases, the RF processor system104is capable of extracting all available characteristics, synchronization information, cells and services identifiers, quality measures of RF, physical layers of wireless communication standards and other information. In some implementations, the RF processor system104is configured to process other types of wireless communication (e.g., non-standardized signals and communication protocols).

In some implementations, the RF processor system104can perform various types of analyses in the frequency domain, the time domain, or both. In some cases, the RF processor system104is configured to determine bandwidth, power spectral density, or other frequency attributes of detected signals. In some cases, the RF processor system104is configured to perform demodulation and other operations to extract content from the wireless signals in the time domain such as, for example, signaling information included in the wireless signals (e.g., preambles, synchronization information, channel condition indicator, SSID/MAC address of a WiFi network). The RF processor system104and the antenna system102can operate based on electrical power provided by the power supply103. For instance, the power supply103can include a battery or another type of component that provides an AC or DC electrical voltage to the RF processor system104.

In some cases, the wireless sensor device100is implemented as a compact, portable device that can be used to sense wireless signals and analyze wireless spectrum usage. In some implementations, the wireless sensor device100is designed to operate with low power consumption (e.g., around 0.1 to 0.2 Watts or less on average). In some implementations, the wireless sensor device100can be smaller than a typical personal computer or laptop computer and can operate in a variety of environments. In some instances, the wireless sensor device100can operate in a wireless sensor network or another type of distributed system that analyzes and aggregates wireless spectrum usage over a geographic area. For example, in some implementations, the wireless sensor device100can be used as described in U.S. Pat. No. 9,143,168, entitled, “Wireless Spectrum Monitoring and Analysis,” or the wireless sensor device100can be used in another type of environment or operate in another manner.

FIG. 2is a diagram of an example wireless receiver200. The receiver200can implement a zero-IF architecture, a direct conversion architecture, a low-IF architecture, or the like. The receiver200includes an antenna201(e.g., antenna system102inFIG. 1) and RF-stage circuitry202coupled to the antenna201. Generally, when items are described as being coupled to one another, they may be communicatively coupled (e.g., directly or indirectly connected for signal communication between them), operatively coupled (e.g., directly or indirectly connected to enable operation of one or both of them) or otherwise. The antenna201is configured to receive a wireless signal (e.g., electromagnetic signal) and to then transform the wireless signal to an electronic signal. The electronic signal is transmitted from the antenna201to the RF-stage circuitry202. The RF-stage circuitry202can include circuitry, such as, for example, bandpass filter circuitry, amplifier circuitry (e.g., a low noise amplifier (LNA)), etc., that is configured to perform actions on the electronic signal, such as filtering out signals at unwanted frequencies, amplifying the electronic signal, etc. The RF-stage circuitry202is configured to output an RF signal.

The receiver200further includes a mixer203and a local oscillator204. In some cases, the local oscillator204can be implemented according to the example local oscillator400shown inFIG. 4or the example local oscillator shown inFIGS. 7 and 8, or the local oscillator204can be implemented in another manner. The local oscillator204is coupled to and provides to the mixer203an in-phase RF reference signal and a quadrature RF reference signal. The RF-stage circuitry202is coupled to the mixer203and transmits to the mixer203the RF signal. The RF signal output from the RF-stage circuitry202is down-converted to an in-phase (I) baseband/low-IF (BB/lIF) signal by the mixer203using the in-phase RF reference signal from the local oscillator204, and further, the RF signal output from the RF-stage circuitry202is down-converted to a quadrature (Q) BB/lIF signal by the mixer203using the quadrature RF reference signal from the local oscillator204.

The receiver200also includes BB/lIF-stage circuitry205and a DSP device207. The BB/lIF-stage circuitry205is coupled to the mixer203and receives the in-phase and quadrature BB/lIF signals from the mixer203. The BB/lIF-stage circuitry205can include circuitry, such as, for example, filter circuitry, analog-to-digital converter (ADC) circuitry, etc., that is configured to perform actions on the BB/lIF-stage signals, such as filtering out signals at unwanted frequencies, converting the analog signals to digital signals, etc. The in-phase and quadrature BB/lIF signals are input into the DSP device207for further processing as discussed above.

FIG. 3is a diagram of an example wireless transmitter300. The transmitter300can implement a zero-IF architecture, a direct conversion architecture, a low-IF architecture, or the like. The transmitter300includes a DSP device301that outputs an in-phase (I) BB/lIF signal and a quadrature (Q) BB/lIF signal. The transmitter300also includes BB/lIF-stage circuitry302coupled to the DSP device301and that receives the in-phase and quadrature BB/lIF signals from the DSP device301. The BB/lIF-stage circuitry302can include circuitry, such as, for example, digital-to-analog converter (DAC) circuitry, filter circuitry, etc., that is configured to perform actions on the BB/lIF signals, such as, for example, converting the digital signals to analog signals, filtering out signals at unwanted frequencies, etc. The BB/lIF-stage circuitry302is configured to output in-phase and quadrature BB/lIF signals.

The transmitter300further includes a mixer303and a local oscillator304. In some cases, the local oscillator304can be implemented according to the example local oscillator400shown inFIG. 4or the example local oscillator shown inFIGS. 7 and 8, or the local oscillator304can be implemented in another manner. The local oscillator304is coupled to and provides to the mixer303an in-phase RF reference signal and a quadrature RF reference signal. The BB/lIF-stage circuitry302is coupled to the mixer303and transmits to the mixer303the in-phase and quadrature BB/lIF signals. The in-phase BB/lIF signal output from the BB/lIF-stage circuitry302is up-converted to an in-phase (I) RF signal by the mixer303using the in-phase RF reference signal from the local oscillator304, and further, the quadrature BB/lIF signal output from the BB/lIF-stage circuitry302is up-converted to a quadrature (Q) RF signal by the mixer303using the quadrature RF reference signal from the local oscillator304.

The in-phase and quadrature RF signals output by the mixer303are combined at305to form a combined RF signal, and the combined RF signal is input into RF-stage circuitry306of the transmitter300. The RF-stage circuitry306can include circuitry, such as, for example, bandpass filter circuitry, amplifier circuitry (e.g., a power amplifier), etc., that is configured to perform actions on the electronic signal, such as filtering out signals at unwanted frequencies, amplifying the RF signal, etc. The RF-stage circuitry306transmits the RF signal to an antenna307. The antenna307is configured to receive the RF signal and to then transform the electronic RF signal to a wireless signal (e.g., electromagnetic signal). The wireless signal is transmitted from the antenna307.

FIG. 4is a diagram of an example local oscillator400. In some cases, the local oscillator400can be used in a wireless sensor device (e.g., the wireless sensor device100shown inFIG. 1) or another type of wireless system. For example, the local oscillator can be used in a wireless transmitter, a wireless receiver or a wireless transceiver. In some cases, the example local oscillator400shown inFIG. 4can be used to implement the local oscillators204and304shown inFIGS. 2 and 3, for example.

The example local oscillator400shown inFIG. 4includes a voltage-controlled oscillator (VCO)401, a multi-stage frequency divider having a first stage410and a second stage411, and a duty-cycle converter409. A local oscillator may include additional or different features, and the components of a local oscillator can be arranged in the manner shown or in another manner.

In the example local oscillator400shown inFIG. 4, the multi-stage frequency divider includes multiple stages of circuitry that process signals in series; each stage of circuitry can, in some instances, divide the frequency of a signal and propagate the frequency-divided signal to a subsequent stage or to another device. The frequency division applied at each stage can be specified by a control signal delivered to the stage, and in some instances, one or more of the stages propagates the input signal to a subsequent stage (or to another device) without dividing the frequency of the signal. In some cases, one or more of the stages is configured to perform additional of different types of processing.

In the example shown inFIG. 4, the first stage410of the multi-stage frequency divider includes a first signal path having a first switch402, and a second signal path having a first frequency divider403and a second switch404. The signal paths in the first stage are configured to produce signals with distinct frequencies. For instance, the second signal path includes the first frequency divider403that divides frequencies by two, and the first signal path does not have a frequency divider, so the second signal path produces an output signal with half the frequency of the output signal produced by the first signal path. The second stage411of the multi-stage frequency divider includes a third signal path having a second frequency divider405and a third switch407, and a fourth signal path having a third frequency divider406and a fourth switch408. The signal paths in the second stage are configured to produce signals with distinct frequencies. For instance, the third signal path includes the second frequency divider405that divides frequencies by two, and the fourth signal path includes the third frequency divider406that divides frequencies by four, so the fourth signal path produces an output signal with half the frequency of the output signal produced by the third signal path. The respective stages of a multi-stage frequency divider may include additional or different features, and may be configured as shown or in another manner.

In the example shown inFIG. 4, the first stage410is configured to receive (from the VCO401) a first reference signal having a first radio frequency, and the switches in the first stage410are configured to receive control signals. The circuitry in the first stage410is configured to generate a second reference signal from the first reference signal, such that the second reference signal has a second radio frequency that is the quotient of the first radio frequency and a first divisor; the first divisor is controlled by the control signals that are received by the switches in the first stage410. Similarly, the second stage411is configured to receive the second reference signal from the first stage, and the switches in the second stage411are configured to receive control signals. The circuitry in the second stage411is configured to generate a third reference signal from the second reference signal, such that the third reference signal has a third frequency that is the quotient of the second frequency and a second divisor; the second divisor is controlled by the control signals that are received by the switches in the second stage411. Examples of the first and second divisors are shown in TABLE 1 below.

The example VCO401can be, for example, a ring-type oscillator, an LC oscillator, or another type of voltage controlled oscillator. Each of the first switch402, the second switch404, the third switch407, and the fourth switch408can be a switch, such as, for example, a single transistor or another type of switch. For instance, a switch may be implemented using a p-type or n-type Field Effect Transistor (FET), such as a p-type or n-type Metal Oxide Semiconductor (MOS) FET, a parallel combination of a p-type or n-type FET as in a transmission gate, or the like. Each of the first frequency divider403, the second frequency divider405, and the third frequency divider406can be implemented as circuitry that divides the frequency of an input signal by a number, e.g., integer or fractional number, and produces an output signal having the divided frequency. In the example shown, the first frequency divider403, the second frequency divider405, and the third frequency divider406divide the frequencies of their respective input signals by two, two, and four, respectively. A frequency divider may divide the frequency of a signal by another value in some cases. The duty-cycle converter409can convert the duty-cycle of an input signal by a designated amount. In the example shown, the duty-cycle is converted to a twenty-five percent duty-cycle.

In the example shown inFIG. 4, an output node of the VCO401is coupled to an input node of the first stage410(e.g., to respective input nodes of the first switch402and the first frequency divider403). An output node of the first frequency divider403is coupled to an input node of the second switch404. The first switch402is controlled by a first control signal EN_DIV to selectively open or close the first switch402, and the second switch404is controlled by a complementary first control signal EN_DIV to selectively open or close the second switch404. Accordingly, in this example, the first and second switches402,404are configured such that one switch is open when the other switch is closed (e.g., the first switch402is open when the second switch404is closed, and the second switch404is open when the first switch402is closed). Output nodes of the first switch402and the second switch404are coupled together to form an output node of the first stage410.

As shown inFIG. 4, the output node of the first stage410is coupled to an input node of the second stage411(e.g., to input nodes of the second frequency divider405and the third frequency divider406). An output node of the second frequency divider405is coupled to an input node of the third switch407, and an output node of the third frequency divider406is coupled to an input node of the fourth switch408. Output nodes of the third switch407and the fourth switch408are coupled together to form an output node of the second stage411. The output node of the second stage411is coupled to an input node of the duty-cycle converter409.

In the example shown inFIG. 4, the third switch407is controlled by a second control signal EN_DIV2to selectively open or close the third switch407, and the fourth switch408is controlled by a third control signal EN_DIV4to selectively open or close the fourth switch408. In some examples, the third control signal EN_DIV4is complementary to the second control signal EN_DIV2. Accordingly, the third and fourth switches407,408can be configured such that one switch is open when the other switch is closed (e.g., the third switch407is open when the fourth switch408is closed, and the fourth switch408is open when the third switch407is closed). In some examples, the third switch407and the fourth switch408are configured to be operated independently, such that either switch can be open or closed independent of the state of the other switch.

In some aspects of operation, the VCO401generates an original reference signal having an original frequency. The VCO401outputs the original reference signal to the input node of the first stage410(e.g., to the input nodes of the first switch402and the first frequency divider403). The first frequency divider403then divides the original frequency of the original reference signal and outputs to the input node of the second switch404a first-stage-divided reference signal with a first-stage-divided frequency that is the original frequency divided by a number (divided by two, in the example shown). In the example shown, the first control signal EN_DIV and the complementary first control signal EN_DIV selectively close either the first switch402or the second switch404while the other switch is open. When the first switch402is closed and the second switch404is open, the original reference signal having the original frequency is output from the first stage410as the first stage output signal that is input to the second stage411(e.g., to the second frequency divider405and the third frequency divider406). In such an instance, the first stage output signal output from the first stage410has the original frequency. When the second switch404is closed and the first switch402is open, the first-stage-divided signal having the first-stage-divided frequency (in this example, the original frequency divided by two) is output from the first stage410as the first stage output signal that is input to the second stage411(e.g., to the second frequency divider405and the third frequency divider406).

From the input node of the second stage411, the second frequency divider405then divides the frequency of the first stage output signal (e.g., the original frequency of the original reference signal or the first-stage-divided frequency of the first-stage-divide signal) and outputs to the input node of the third switch407a first second-stage-divided reference signal with a first second-stage-divided frequency that is the frequency of the first stage output signal divided by a number (divided by two, in the example shown). Also from the input node of the second stage411, the third frequency divider406then divides the frequency of the first stage output signal (e.g., the original frequency of the original reference signal or the first-stage-divided frequency of the first-stage-divide signal) and outputs to the input node of the fourth switch408a second second-stage-divided reference signal with a second second-stage-divided frequency that is the frequency of the first stage output signal divided by a number that is different from the divisor applied by the second frequency divider405. The second control signal EN_DIV2and the third control signal EN_DIV4will can selectively close either the third switch407or the fourth switch408while the other switch is open. When the third switch407is closed and the fourth switch408is open, the first second-stage-divided signal having the first second-stage-divided frequency is output from the second stage411as the second stage output signal that is input to the duty-cycle converter409. When the fourth switch408is closed and the third switch407is open, the second second-stage-divided signal having the second second-stage-divided frequency is output from the second stage411as the second stage output signal that is input to the duty-cycle converter409.

TABLE 1 below shows the frequency ffof the second stage output signal produced by the second stage411and received at the duty-cycle converter409under the given conditions. The original reference signal produced by the VCO401and input to the first stage410has the original frequency fo. The first frequency divider403divides the frequency of an input signal by a first divisor D1(e.g., 2 as illustrated); the second frequency divider405divides the frequency of an input signal by a second divisor D2(e.g., 2 as illustrated); and the third frequency divider406divides the frequency of an input signal by a third divisor D3(e.g., 4 as illustrated).

In the example shown inFIG. 4, the duty-cycle converter409then converts the duty-cycle of the second stage output signal (e.g., the first second-stage-divided signal or the second second-stage-divided signal) to produce a corresponding local oscillator reference signal with a duty-cycle and having a frequency of the second stage output signal. The local oscillator reference signal is output to a mixer.

FIG. 5is a diagram showing a portion of an example receiver circuit that can use the local oscillator400ofFIG. 4. The example receiver circuit shown inFIG. 5includes a mixer500. The mixer500can include circuitry that down-converts an RF signal to an IF signal (e.g., low IF signal), such as an IF signal having an in-phase (I) signal and a quadrature (Q) signal. An output node of the duty-cycle converter409is coupled to an input of the mixer500. The mixer500has an RF input node RF, an IF in-phase output node IF_I, and an IF quadrature output node IF_Q. In some aspects of operation, the local oscillator reference signal is output from the duty-cycle converter409and input into the mixer500. The mixer500receives an RF signal (e.g., from an antenna through RF-stage circuitry) on the RF input node RF. The mixer500then uses the local oscillator reference signal to down-convert the RF signal to an IF in-phase signal and an IF quadrature signal that are output on the IF in-phase output node IF_I and the IF quadrature output node IF_Q, respectively (e.g., to BB/lIF-stage circuitry). In some instances, a baseband (BB) signal can be processed in a similar manner as the IF signal discussed above.

FIG. 6is a diagram showing a portion of an example transmitter circuit that can use the local oscillator400ofFIG. 4. The example transmitter circuit shown inFIG. 6includes a mixer600. The mixer600can include circuitry that up-converts an IF signal to an RF signal. An output node of the duty-cycle converter409(seeFIG. 4) is coupled to an input of the mixer600. The mixer600has an IF input node IF and an RF output node RF. In some aspects of operation, the local oscillator reference signal is output from the duty-cycle converter409and input into the mixer600. The mixer600receives an IF signal (e.g., from BB/lIF-stage circuitry) on the IF input node IF. The mixer600then uses the local oscillator reference signal to up-convert the IF signal to an RF signal that is output on the RF output node RF (e.g., to an antenna through RF-stage circuitry). In some instances, a baseband (BB) signal can be processed in a similar manner as the IF signal discussed above.

FIGS. 7 and 8show aspects of another example local oscillator. In some cases, the local oscillator shown inFIGS. 7 and 8can be used in a wireless sensor device (e.g., the wireless sensor device100shown inFIG. 1) or another type of wireless system. For example, the local oscillator can be used in a wireless transmitter, a wireless receiver or a wireless transceiver. In some cases, the example local oscillator shown inFIGS. 7 and 8can be used to implement the local oscillators204and304shown inFIGS. 2 and 3, for example. In some aspects, the local oscillator shown inFIGS. 7 and 8can be considered an example implementation of the local oscillator400shown inFIG. 4. A local oscillator may include additional or different features, and the components of a local oscillator can be arranged in the manner shown inFIGS. 7 and 8or in another manner.

The example local oscillator shown inFIGS. 7 and 8includes a multi-stage frequency divider, which includes multiple stages of circuitry that process signals in series. In particular, a first stage707is shown inFIG. 7and a second stage850is shown inFIG. 8. Additional or different stages may be used. Each stage of the multi-stage frequency divider can, in some instances, divide the frequency of a signal and propagate the frequency-divided signal to a subsequent stage or another device. The frequency division applied at each stage can be specified by a control signal delivered to the stage, and in some instances, one or more of the stages propagates the input signal to a subsequent stage or another device without dividing the frequency of the signal. A multi-stage frequency divider may be configured as shown inFIGS. 7 and 8or in another manner.

In the example shown inFIGS. 7 and 8, the first stage707of the multi-stage frequency divider includes a first signal path having first and second switches702,704, and a second signal path having a first frequency divider703and third and fourth switches705,706. The second stage850of the multi-stage frequency divider includes a third signal path having a second frequency divider816and multiple switches (808,810,826,827,828,829), and a fourth signal path having a third frequency divider817and multiple switches (809,811,830,831,832,833). The respective stages of a multi-stage frequency divider may include additional or different features, and may be configured as shown or in another manner.

In the example shown inFIGS. 7 and 8, the first stage707is configured to receive (from the VCO701) a differential first reference signal having a first radio frequency, and the switches in the first stage707are configured to receive control signals. The circuitry in the first stage707is configured to generate a differential second reference signal from the differential first reference signal, such that the differential second reference signal has a second radio frequency that is the quotient of the first radio frequency and a first divisor; the first divisor is controlled by the control signals that are received by the switches in the first stage707. Similarly, the second stage850is configured to receive the differential second reference signal from the first stage707, and the switches in the second stage850are configured to receive control signals. The circuitry in the second stage850is configured to generate a differential third reference signal from the differential second reference signal, such that the differential third reference signal has a third frequency that is the quotient of the second frequency and a second divisor; the second divisor is controlled by the control signals that are received by the switches in the second stage850.

FIG. 7is a diagram showing an example circuit implementation of a voltage controlled oscillator (VCO)701and first stage of a multi-stage frequency divider of a local oscillator. The example circuit700shown inFIG. 7utilizes differential signals and appropriate connections to transmit differential signals. The differential signal includes two signals that are 180° out of phase with each other, or are complementary of each other. Here, a positive signal component (with a 0° phase shift) of a differential signal (and nodes on which the positive signal is carried) is designated with a “P,” and a negative signal component (with a 180° phase shift) of a differential signal (and nodes on which the negative signal is carried) is designated with a “N.”

The example VCO701has a first output node OR_P and a second output node OR_N. The first output node OR_P of the VCO701is coupled to a first input node of the first stage707(e.g., to respective input nodes of a first switch702and the first frequency divider703). The second output node OR_N of the VCO701is coupled to a second input node of the first stage707(e.g., to respective input nodes of a second switch704and the first frequency divider703). A first output node of the first frequency divider703is coupled to an input node of the third switch705. A second output node of the first frequency divider703is coupled to an input node of the fourth switch706. Output nodes of the first switch702and the third switch705are coupled together and form a first output node S1_P of the first stage707. Output nodes of the second switch704and the fourth switch706are coupled together and form a second output node S1_N of the first stage707. The first switch702and the second switch are controlled by a first control signal EN_DIV to selectively open and close the first switch702and the second switch704; the third switch705and the fourth switch706are controlled by a complementary first control signalEN_DIVto selectively open and close the third switch705and the fourth switch706. Accordingly, the first switch702and the second switch704are open when the third switch705and the fourth switch706are closed, and vice versa.

FIG. 8is a diagram showing an example circuit implementation of a second stage850of the multi-stage frequency divider inFIG. 7and duty-cycle converters838,839,840, and841of the local oscillator. The example circuit800utilizes differential signals, and hence, appropriate connections to transmit differential signals.

As shown inFIG. 8, the first output node S1_P of the first stage707(shown inFIG. 7) is coupled a first input node801of the second stage850, and the second output node S1_N of the first stage707(shown inFIG. 7) is coupled to a second input node802of the second stage850. The first input node801of the second stage850is coupled to an input node804of a first switch808and an input node805of a second switch809. The second input node802of the second stage850is coupled to an input node806of a third switch810and an input node807of a fourth switch811. An output node of the first switch808is coupled to a first input node812of a second frequency divider816, and an output node of the third switch810is coupled to a second input node814of the second frequency divider816. An output node of the second switch809is coupled to a first input node813of a third frequency divider817, and an output node of the fourth switch811is coupled to a second input node815of the third frequency divider817.

As shown inFIG. 8, each of the second frequency divider816and the third frequency divider817include four output nodes. The four output nodes include an in-phase output node having an in-phase signal designated by “0°”, and three output nodes having respective signals with phase differences from the in-phase output node as designated by “90°,” “180°,” and “270°.” A first output node818of the second frequency divider816(e.g., that outputs an in-phase signal) is coupled to an input node of a fifth switch826. A second output node819of the second frequency divider816(e.g., that outputs a signal 180° out of phase from the in-phase signal) is coupled to an input node of a sixth switch827. A third output node820of the second frequency divider816(e.g., that outputs a signal 90° out of phase from the in-phase signal) is coupled to an input node of a seventh switch828. A fourth output node821of the second frequency divider816(e.g., that outputs a signal 270° out of phase from the in-phase signal) is coupled to an input node of an eighth switch829.

As shown inFIG. 8, a first output node825of the third frequency divider817(e.g., that outputs an in-phase signal) is coupled to an input node of a ninth switch833. A second output node824of the third frequency divider817(e.g., that outputs a signal 180° out of phase from the in-phase signal) is coupled to an input node of a tenth switch832. A third output node823of the third frequency divider817(e.g., that outputs a signal 90° out of phase from the in-phase signal) is coupled to an input node of an eleventh switch831. A fourth output node822of the third frequency divider817(e.g., that outputs a signal 270° out of phase from the in-phase signal) is coupled to an input node of a twelfth switch830.

As shown inFIG. 8, output nodes of the fifth switch826, sixth switch827, seventh switch828, eighth switch829, ninth switch833, tenth switch832, eleventh switch831, and twelfth switch830are coupled to a respective one of a first bus line834, second bus line835, third bus line836, or fourth bus line837of a bus. The output nodes of the fifth switch826and the ninth switch833are coupled to the first bus line834(e.g., that carries an in-phase signal). The output nodes of the sixth switch827and the tenth switch832are coupled to the third bus line836(e.g., that carries a signal 180° out of phase from the in-phase signal). The output nodes of the seventh switch828and the eleventh switch831are coupled to the second bus line835(e.g., that carries a signal 90° out of phase from the in-phase signal). The output nodes of the eighth switch829and the twelfth switch830are coupled to the fourth bus line837(e.g., that carries a signal 270° out of phase from the in-phase signal).

In the example shown inFIG. 8, the second switch809, fourth switch811, ninth switch833, tenth switch832, eleventh switch831, and twelfth switch830are controlled by a second control signal EN_DIV2to selectively open and close the second switch809, fourth switch811, ninth switch833, tenth switch832, eleventh switch831, and twelfth switch830. The first switch808, third switch810, fifth switch826, sixth switch827, seventh switch828, and eighth switch829are controlled by a third control signal EN_DIV4to selectively open and close the first switch808, third switch810, fifth switch826, sixth switch827, seventh switch828, and eighth switch829. The third control signal EN_DIV4may be complementary to the second control signal EN_DIV2, and accordingly, the second switch809, fourth switch811, ninth switch833, tenth switch832, eleventh switch831, and twelfth switch830may be open when the first switch808, third switch810, fifth switch826, sixth switch827, seventh switch828, and eighth switch829are closed, and vice versa. In some instances, the first switch808, second switch809, third switch810, fourth switch811, fifth switch826, sixth switch827, seventh switch828, eighth switch829, ninth switch833, tenth switch832, eleventh switch831, and twelfth switch830may be open simultaneously.

As shown inFIG. 8, duty-cycle converters are coupled to the bus. Each of a first duty-cycle converter838, a second duty-cycle converter839, a third duty-cycle converter840, and a fourth duty-cycle converter841includes a first inverter INV1and a second inverter INV2. A first input node of the first duty-cycle converter838(e.g., an input node of the first inverter INV1) is coupled to the first bus line834, and a second input node of the first duty-cycle converter838(e.g., an input node of the second inverter INV2) is coupled to the second bus line835. Output nodes of the first inverter INV1and the second inverter INV2of the first duty-cycle converter838are coupled together to form a positive quadrature local oscillator reference signal output node (LO_QP)842of the first duty-cycle converter838. A first input node of the second duty-cycle converter839(e.g., an input node of the first inverter INV1) is coupled to the third bus line836, and a second input node of the second duty-cycle converter839(e.g., an input node of the second inverter INV2) is coupled to the fourth bus line837. Output nodes of the first inverter INV1and the second inverter INV2of the second duty-cycle converter839are coupled together to form a negative quadrature local oscillator reference signal output node (LO_QN)843of the second duty-cycle converter839. A first input node of the third duty-cycle converter840(e.g., an input node of the first inverter INV1) is coupled to the second bus line835, and a second input node of the third duty-cycle converter840(e.g., an input node of the second inverter INV2) is coupled to the third bus line836. Output nodes of the first inverter INV1and the second inverter INV2of the third duty-cycle converter840are coupled together to form a negative in-phase local oscillator reference signal output node (LO_IN)844of the third duty-cycle converter840. A first input node of the fourth duty-cycle converter841(e.g., an input node of the first inverter INV1) is coupled to the first bus line834, and a second input node of the fourth duty-cycle converter841(e.g., an input node of the second inverter INV2) is coupled to the fourth bus line837. Output nodes of the first inverter INV1and the second inverter INV2of the fourth duty-cycle converter841are coupled together to form a positive in-phase local oscillator reference signal output node (LO_IP)845of the fourth duty-cycle converter841.

The example VCO701can be, for example, a ring-type oscillator, an LC oscillator, or another type of voltage controlled oscillator. Each of the switches inFIGS. 7 and 8(702,704,705,706,808,809,810,811,826,827,828,829,830,831,832and833) can be a switch, such as, for example, a single transistor or another type of switch. Each of the first frequency divider703, the second frequency divider816, and the third frequency divider817can be implemented as circuitry that divides the frequency of an input signal by a number, e.g., integer or fractional number, and produces an output signal having the divided frequency. In the example shown, the first frequency divider703, the second frequency divider816, and the third frequency divider817divide the frequencies of their respective input signals by two, four, and two, respectively. A frequency divider may divide the frequency of a signal by another value in some cases. Each of the example duty-cycle converters (838,839,840,841) can convert the duty-cycle of an input signal by a designated amount. In the example shown, the duty-cycle is converted to a twenty-five percent duty-cycle.

In the example circuits shown inFIGS. 7 and 8, various lines (e.g., metal lines) in the example circuits700and800may be matched and have low resistances and capacitances. Low resistance and capacitance may lead to lower RC time constants. Lines that are matched may be symmetric, may have a same length, may have same metal layers, and may observe similar environments (e.g., adjacent surroundings, metal, p+ diffusion, n+ diffusion, poly-silicon fills, and parasitic capacitances). As examples, the following lines may be matched: lines between the output nodes S1_P and S1_N of the first stage707and the input nodes804,805,806,807of the first through fourth switches808,809,810,811; lines between output nodes of switches809,810and input nodes813,814of the third frequency divider817and the second frequency divider816; lines between output nodes of switches808,809and input nodes812,813of the second frequency divider816and the third frequency divider817; lines between output nodes of switches810,811and input nodes814,815of the second frequency divider816and the third frequency divider817; lines between output nodes818,819,820,821of the second frequency divider816and input nodes of the switches826,827,828,829; lines between output nodes822,823,824,825of the third frequency divider817and input nodes of the switches830,831,832,833; and the bus lines834,835,836,837. In some cases, the arrangement of bus lines834,835,836,837may allow an amount of parasitic capacitance seen by each signal on each bus line to be balanced, which may help avoid DC offsets being observed after an up-conversion or down-conversion by a mixer.

In some aspects of the operation, the VCO701generates a differential original reference signal having an original frequency. The VCO701outputs the differential original reference signal on its first output node OR_P and second output node OR_N and to the input nodes of the first stage707(e.g., to the input nodes of the first switch702, the second switch704, and the first frequency divider703). The first frequency divider703then divides the original frequency of the differential original reference signal and outputs to the input nodes of the third switch705and the fourth switch706a differential first-stage-divided reference signal with a first-stage-divided frequency that is the original frequency divided by a number. The first control signal EN_DIV and the complementary first control signalEN_DIVcan selectively close either the first switch702and the second switch704or the third switch705and the fourth switch706while the other group of switches are open. When the first switch702and the second switch704are closed and the third switch705and the fourth switch706are open, the differential original reference signal having the original frequency is output from the first stage707as a differential first stage output signal on the first and second output nodes S1_P and S1_N and input to the second stage850(e.g., to the first input node801and the second input node802of the second stage850). In such an instance, the first stage output signal output from the first stage707has the original frequency. When the third switch705and the fourth switch706are closed and the first switch702and the second switch704are open, the differential first-stage-divided signal having the first-stage-divided frequency is output from the first stage707as the differential first stage output signal on the first and second output nodes S1_P and S1_N and input to the second stage850(e.g., to the first input node801and the second input node802of the second stage850).

In some aspects of the operation, at the second stage850, the differential first stage output signal is input to the first input node801and the second input node802of the second stage850from the first output node S1_P and the second output node S1_N, respectively, of the first stage707. The positive portion of the differential first stage output signal is input along the first input node801and into the input nodes804and805of the first switch808and the second switch809. The negative portion of the differential first stage output signal is input along the second input node802and into the input nodes806and807of the third switch810and the fourth switch811. Switches are selectively open or closed to direct the differential first stage output signal to the second frequency divider816or the third frequency divider817and to output a second stage output signal to the bus.

In a first scenario, the third control signal EN_DIV4is in a state (e.g., low or high) such that the first switch808, third switch810, fifth switch826, sixth switch827, seventh switch828, and eighth switch829are closed while the second control signal EN_DIV2is in a state (e.g., low or high) such that the second switch809, fourth switch811, ninth switch833, tenth switch832, eleventh switch831, and twelfth switch830are open. Since the second switch809and the fourth switch811are open, the differential first stage output signal does not propagate beyond the second switch809and the fourth switch811. Since the first switch808and the third switch810are closed, the differential first stage output signal is input to the first input node812and the second input node814of the second frequency divider816.

The second frequency divider816divides the frequency of the differential first stage output signal and outputs to the bus, as a second stage output signal, a first second-stage-divided reference signal with a first second-stage-divided frequency that is the frequency of the differential first stage output signal divided by a number. The second frequency divider816outputs an in-phase (e.g., 0° phase difference) first second-stage-divided reference signal on the first output node818of the second frequency divider816, a quadrature (e.g., 90° phase difference from the in-phase signal) first second-stage-divided reference signal on the third output node820of the second frequency divider816, a complementary in-phase (e.g., 180° phase difference) first second-stage-divided reference signal on the second output node819of the second frequency divider816, and a complementary quadrature (e.g., 270° phase difference) first second-stage-divided reference signal on the fourth output node821of the second frequency divider816. Since the fifth switch826, sixth switch827, seventh switch828, and eighth switch829are closed, the in-phase first second-stage-divided reference signal from the second frequency divider816is output to the first bus line834; the quadrature first second-stage-divided reference signal from the second frequency divider816is output to the second bus line835; the complementary in-phase first second-stage-divided reference signal from the second frequency divider816is output to the third bus line836; and the complementary quadrature first second-stage-divided reference signal from the second frequency divider816is output to the fourth bus line837.

In a second scenario, the second control signal EN_DIV2is in a state (e.g., low or high) such that the second switch809, fourth switch811, ninth switch833, tenth switch832, eleventh switch831, and twelfth switch830are closed while the third control signal EN_DIV4is in a state (e.g., low or high) such that the first switch808, third switch810, fifth switch826, sixth switch827, seventh switch828, and eighth switch829are open. Since the first switch808and the third switch810are open, the differential first stage output signal does not propagate beyond the first switch808and the third switch810. Since the second switch809and the fourth switch811are closed, the differential first stage output signal is input to the first input node813and the second input node815of the third frequency divider817.

The third frequency divider817divides the frequency of the differential first stage output signal and outputs to the bus, as a second stage output signal, a second second-stage-divided reference signal with a second second-stage-divided frequency that is the frequency of the differential first stage output signal divided by a number. The third frequency divider817outputs an in-phase (e.g., 0° phase difference) second second-stage-divided reference signal on the first output node825of the third frequency divider817, a quadrature (e.g., 90° phase difference from the in-phase signal) second second-stage-divided reference signal on the third output node823of the third frequency divider817, a complementary in-phase (e.g., 180° phase difference) second second-stage-divided reference signal on the second output node824of the third frequency divider817, and a complementary quadrature (e.g., 270° phase difference) second second-stage-divided reference signal on the fourth output node822of the third frequency divider817. Since the ninth switch833, tenth switch832, eleventh switch831, and twelfth switch830are closed, the in-phase second second-stage-divided reference signal from the third frequency divider817is output to the first bus line834; the quadrature second second-stage-divided reference signal from the third frequency divider817is output to the second bus line835; the complementary in-phase second second-stage-divided reference signal from the third frequency divider817is output to the third bus line836; and the complementary quadrature second second-stage-divided reference signal from the third frequency divider817is output to the fourth bus line837.

In the first scenario and the second scenario described above, the second stage output signal from either the second frequency divider816or the third frequency divider817is an example of a differential divided reference signal that can be produced by the multi-stage frequency divider. The example duty-cycle converters shown inFIG. 8are configured to receive the differential divided reference signal and output a differential duty-cycle converted signal, for instance, as described below.

In some aspects of operation, the in-phase second stage output signal (e.g., the first or second second-stage-divided reference signal) and the complementary quadrature second stage output signal are input to the input node of the first inverter INV1and the input node of the second inverter INV2, respectively, of the fourth duty-cycle converter841. The fourth duty-cycle converter841outputs a positive in-phase local oscillator reference signal on the positive in-phase local oscillator reference signal output node (LO_IP)845of the fourth duty-cycle converter841. The quadrature second stage output signal and the complementary in-phase second stage output signal are input to the input node of the first inverter INV1and the input node of the second inverter INV2, respectively, of the third duty-cycle converter840. The third duty-cycle converter840outputs a negative in-phase local oscillator reference signal on the negative in-phase local oscillator reference signal output node (LO_IN)844of the third duty-cycle converter840. The in-phase second stage output signal and the quadrature second stage output signal are input to the input node of the first inverter INV1and the input node of the second inverter INV2, respectively, of the first duty-cycle converter838. The first duty-cycle converter838outputs a positive quadrature local oscillator reference signal on the positive quadrature local oscillator reference signal output node (LO_QP)842of the first duty-cycle converter838. The complementary in-phase second stage output signal and the complementary quadrature second stage output signal are input to the input node of the first inverter INV1and the input node of the second inverter INV2, respectively, of the second duty-cycle converter839. The second duty-cycle converter839outputs a negative quadrature local oscillator reference signal on the negative quadrature local oscillator reference signal output node (LO_QN)843of the second duty-cycle converter839. The conversion of the respective duty-cycles by the first duty-cycle converter838, second duty-cycle converter839, third duty-cycle converter840, and fourth duty-cycle converter841can be performed, for example, as described with respect toFIGS. 12 and 13or in another manner. In some examples, the positive in-phase, negative in-phase, positive quadrature, and negative quadrature local oscillator reference signals are output to mixers.

FIG. 9is a diagram showing a portion of an example receiver circuit that uses the local oscillator shown inFIGS. 7 and 8. In the example shown inFIG. 9, a first mixer900has a positive RF input node RF_P and a negative RF input node RF_N (e.g., that may be coupled through RF-stage circuitry to an antenna) and has a positive IF quadrature output node IF_QP and a negative IF quadrature output node IF_QN (e.g., that may be coupled to BB/lIF-stage circuitry). The first mixer900further has a first reference signal input node that is coupled to the positive quadrature local oscillator reference signal output node (LO_QP)842and a second reference signal input node that is coupled to the negative quadrature local oscillator reference signal output node (LO_QN)843. A second mixer902has a positive RF input node RF_P and a negative RF input node RF_N (e.g., that may be coupled through RF-stage circuitry to an antenna) and has a positive IF in-phase output node IF_IP and a negative IF in-phase output node IF_IN (e.g., that may be coupled to IF-stage circuitry). The second mixer902further has a first reference signal input node that is coupled to the positive in-phase local oscillator reference signal output node (LO_IP)845and a second reference signal input node that is coupled to the negative in-phase local oscillator reference signal output node (LO_IN)844.

As further examples, the following lines may be matched: lines between the output nodes842,843of the first duty-cycle converter838and the second duty-cycle converter839and the input nodes of the first mixer900; lines between the output nodes844,845of the third duty-cycle converter840and the fourth duty-cycle converter841and the input nodes of the second mixer902; lines to input nodes RF_P and RF_N of the first mixer900and the second mixer902; and lines from the output nodes IF_IP, IF_IN, IF_QP, and IF_QN of the first mixer900and the second mixer902.

In some aspects of operation, the differential quadrature local oscillator reference signal is output from the first duty-cycle converter838and the second duty-cycle converter839on the positive quadrature local oscillator reference signal output node (LO_QP)842and the negative quadrature local oscillator reference signal output node (LO_QN)843, respectively, and input into the first mixer900. The first mixer900receives a differential RF signal on the positive RF input node RF_P and the negative RF input node RF_N. The first mixer900then uses the differential quadrature local oscillator reference signal to down-convert the differential RF signal to a differential IF quadrature signal that is output on the positive IF quadrature output node IF_QP and the negative IF quadrature output node IF_QN. In some aspects of operation, the differential in-phase local oscillator reference signal is output from the fourth duty-cycle converter841and the third duty-cycle converter840on the positive in-phase local oscillator reference signal output node (LO_IP)845and the negative in-phase local oscillator reference signal output node (LO_IN)844, respectively, and input into the second mixer902. The second mixer902receives a differential RF signal on the positive RF input node RF_P and the negative RF input node RF_N. The second mixer902then uses the differential in-phase local oscillator reference signal to down-convert the differential RF signal to a differential IF in-phase signal that is output on the positive IF in-phase output node IF_IP and the negative IF in-phase output node IF_IN. In some instances, a baseband (BB) signal can be processed in a similar manner as the IF signal discussed above.

FIG. 10is diagram showing a portion of an example transmitter circuit that uses the local oscillator shown inFIGS. 7 and 8. In the example shown inFIG. 10, a first mixer1000has a positive IF quadrature input node IF_QP and a negative IF quadrature input node IF_QN (e.g., that may be coupled to BB/lIF-stage circuitry). The first mixer1000further has a first reference signal input node that is coupled to the positive quadrature local oscillator reference signal output node (LO_QP)842and a second reference signal input node that is coupled to the negative quadrature local oscillator reference signal output node (LO_QN)843. A second mixer1002has a positive IF in-phase input node IF_IP and a negative IF in-phase input node IF_IN (e.g., that may be coupled to IF-stage circuitry). The second mixer1002has a first reference signal input node that is coupled to the positive in-phase local oscillator reference signal output node (LO_IP)845and a second reference signal input node that is coupled to the negative in-phase local oscillator reference signal output node (LO_IN)844. First outputs of the first mixer1000and the second mixer1002are coupled together to form a positive RF output node (RF_P)1003(e.g., that may be coupled through RF-stage circuitry to an antenna). Second outputs of the first mixer1000and the second mixer1002are coupled together to form a negative RF output node (RF_N)1004(e.g., that may be coupled through RF-stage circuitry to an antenna).

As further examples, the following lines may be matched: lines between the output nodes842,843of the first duty-cycle converter838and the second duty-cycle converter839and the input nodes of the first mixer1000; lines between the output nodes844,845of the third duty-cycle converter840and the fourth duty-cycle converter841and the input nodes of the second mixer1002; lines to input nodes IF_IP, IF_IN, IF_QP, and IF_QN of the first mixer1000and the second mixer1002; and lines from the output nodes RF_P and RF_N of the first mixer1000and the second mixer1002.

In some aspects of operation, the differential quadrature local oscillator reference signal is output from the first duty-cycle converter838and the second duty-cycle converter839on the positive quadrature local oscillator reference signal output node (LO_QP)842and the negative quadrature local oscillator reference signal output node (LO_QN)843, respectively, and input into the first mixer1000. The first mixer1000receives a differential IF quadrature signal on the positive IF quadrature input node IF_QP and the negative IF quadrature input node IF_QN. The first mixer1000then uses the differential quadrature local oscillator reference signal to up-convert the differential IF quadrature signal to a differential RF signal that is output on the positive RF output node (RF_P)1003and the negative RF output node (RF_N)1004. In some aspects of operation, the differential in-phase local oscillator reference signal is output from the fourth duty-cycle converter841and the third duty-cycle converter840on the positive in-phase local oscillator reference signal output node (LO_IP)845and the negative in-phase local oscillator reference signal output node (LO_IN)844, respectively, and input into the second mixer1002. The second mixer1002receives a differential IF in-phase signal on the positive IF in-phase input node IF_IP and the negative IF in-phase input node IF_IN. The second mixer1002then uses the differential in-phase local oscillator reference signal to up-convert the differential IF in-phase signal to a differential RF signal that is output on the positive RF output node (RF_P)1003and the negative RF output node (RF_N)1004.

FIG. 11is a diagram showing an example circuit implementation1100of a duty-cycle converter. In some implementations, the duty-cycle converters838,839,840, and841shown inFIGS. 8, 9 and 10can be implemented according to the example shown inFIG. 11, or the duty-cycle converters838,839,840, and841shown inFIGS. 8, 9 and 10can be implemented in another manner.

The example circuit implementation1100shown inFIG. 11includes symmetric NOR logic circuitry. As shown inFIG. 11, the example circuit implementation1100includes a first p-type transistor (e.g., a p-type MOSFET) Mp1, a second p-type transistor (e.g., a p-type MOSFET) Mp2, a first n-type transistor (e.g., an n-type MOSFET) Mn1, and a second n-type transistor (e.g., an n-type MOSFET) Mn2. The gates of the first p-type transistor Mp1and the first n-type transistor Mn1are connected together and form a first input node IN1of the duty cycle converter. A source of the first p-type transistor Mp1is coupled to a positive power supply node VDD, and a source of the first n-type transistor Mn1is coupled to a negative power supply node VSS. The gates of the second p-type transistor Mp2and the second n-type transistor Mn2are connected together and form a second input node IN2of the duty cycle converter. A source of the second p-type transistor Mp2is coupled to the positive power supply node VDD, and a source of the second n-type transistor Mn2is coupled to a negative power supply node VSS. The drains of the first p-type transistor Mp1, the first n-type transistor Mn1, the second p-type transistor Mp2, and the second n-type transistor Mn2are connected together and form an output node OUT of the duty cycle converter.

In the example shown inFIG. 11, the first p-type transistor Mp1and the first n-type transistor Mn1form the first inverter INV1of the duty-cycle converters838,839,840, and841, and the second p-type transistor Mp2and the second n-type transistor Mn2form the second inverter INV2of the duty-cycle converters838,839,840, and841. In operation, the example circuit implementation1100acts as a NOR gate. The relatively small number of transistors in this example circuit implementation1100may, in some instances, allow the circuit to have a fast response time for high frequency applications. Further, the example circuit implementation1100may, in some instances, allow for a wider output swing capability in high frequency applications, which can also allow for an improved phase-noise specification.

FIG. 12is a plot showing example signals on the bus ofFIG. 8.FIG. 12shows an in-phase signal I(0°) that is carried on the first bus line834; a quadrature signal Q(90°) that is 90° out of phase from the in-phase signal I(0°) and is carried on the second bus line835; a complementary in-phase signal Ī(180°) that is 180° out of phase from the in-phase signal) I(0°) and is carried on the third bus line836; and a complementary quadrature signal)Q(270°) that is 270° out of phase from the in-phase signal I(0°) and that is carried on the fourth bus line837. These signals can be output from the second frequency divider816or the third frequency divider817through respective switches to the first bus line834, second bus line835, third bus line836, and fourth bus line837as discussed above. The example signals shown inFIG. 11have fifty percent (50%) duty-cycles.

FIG. 13is a plot showing example signals output from the duty-cycle converters ofFIG. 8. The example signals shown inFIG. 13have twenty-five percent (25%) duty-cycles.FIG. 13shows a converted in-phase signal I(0°) that is output by the fourth duty-cycle converter841by NORing (applying the NOR Boolean logic operation) the in-phase signal I(0°) that is carried on the first bus line834and the complementary quadrature signalQ(270°) that is carried on the fourth bus line837; a converted quadrature signal Q(90°) that is output by the first duty-cycle converter838by NORing the quadrature signal Q(90°) that is carried on the second bus line835and the in-phase signal I(0°) that is carried on the first bus line834; a converted complementary in-phase signal Ī(180°) that is output by the third duty-cycle converter840by NORing the complementary in-phase signal) Ī(180°) that is carried on the third bus line836and the quadrature signal Q(90°) that is carried on the second bus line835; and a converted complementary quadrature signalQ(270°) that is output by the second duty-cycle converter839by NORing the complementary quadrature signalQ(270°) that is carried on the fourth bus line837and the complementary in-phase signal Ī(180°) that is carried on the third bus line836.

In a general aspect, local oscillators have been described. In some examples, the local oscillators includes features or components that provide one or more advantages, as described above.

In a first example, a wireless sensor device includes an antenna, a mixer, and a local oscillator. The antenna is configured to wirelessly communicate a wireless signal. The mixer is communicatively coupled to the antenna. The local oscillator includes a voltage controlled oscillator, a multi-stage frequency divider, and a duty-cycle converter. An output node of the voltage controlled oscillator is communicatively coupled to an input node of a first stage of the multi-stage frequency divider. An output node of the first stage of the multi-stage frequency divider is communicatively coupled to an input node of a second stage of the multi-stage frequency divider. The first stage of the multi-stage frequency divider is configured to selectively output to the output node of the first stage of the multi-stage frequency divider a first signal from at least one of a first plurality of signal paths, where each of the first plurality of signal paths is configured to provide a signal having a distinct frequency (different from the frequencies of signals provided the other signal paths). The second stage of the multi-stage frequency divider is configured to output to an output node of the second stage of the multi-stage frequency divider a second signal from at least one of a second plurality of signal paths, where each of the second plurality of signal paths is configured to provide a signal having a distinct frequency (different from the frequencies of signals provided the other signal paths). An output node of the multi-stage frequency divider is communicatively coupled to an input node of the duty-cycle converter. An output node of the duty-cycle converter is communicatively coupled to an input node of the mixer.

Implementations of the first example may, in some cases, include one or more of the following features. The antenna may be configured to receive the wireless signal and send a radio-frequency signal to the mixer through a radio-frequency node, and the mixer may be configured to down-convert the radio-frequency signal. The antenna may be configured to transmit the wireless signal and receive a radio-frequency signal from the mixer through a radio-frequency node, and the mixer may be configured to up-convert a signal to the radio-frequency signal.

Implementations of the first example may, in some cases, include one or more of the following features. The duty-cycle converter may be configured to output a reference signal having a twenty-five percent duty-cycle. The duty-cycle converter may comprise a first inverter having a first input node and a second inverter having a second input node, and a first output node of the first inverter may be communicatively coupled to a second output node of the second inverter to form the output node of the duty-cycle converter. The voltage controlled oscillator may be configured to output a differential original reference signal; the multi-stage frequency divider may be configured to output a differential divided reference signal; and the duty-cycle converter may be configured to output a differential duty-cycle converted signal.

Implementations of the first example may, in some cases, include one or more of the following features. The first stage of the multi-stage frequency divider may comprise a first signal path and a second signal path of the first plurality of signal paths, and the second stage of the multi-stage frequency divider may comprise a third signal path and a fourth signal path of the second plurality of signal paths. The first signal path of the first plurality of signal paths has a first switch and is configured to output a signal. The second signal path of the first plurality of signal paths has a second switch. The second signal path is configured to divide the frequency of the input signal input on the input node of the first stage by a second divisor that is greater than one to form a second divided signal. The first switch and the second switch are configured such that one is open when the other is closed to selectively output the signal from the first signal path or the second divided signal as the first signal. The third signal path of the second plurality of signal paths has a third switch. The third signal path is configured to divide a frequency of an input signal input on the input node of the second stage by a third divisor that is greater than one to form a third divided signal. The fourth signal path of the second plurality of signal paths has a fourth switch. The fourth signal path is configured to divide the frequency of the input signal input on the input node of the second stage by a fourth divisor that is greater than one to form a fourth divided signal. The third divisor is different from the fourth divisor. The third switch and the fourth switch are configured such that one is open when the other is closed to selectively output the third divided signal or the fourth divided signal as the second signal.

In a second example, a local oscillator includes a voltage controlled oscillator, a multi-stage frequency divider, and a duty-cycle converter. The multi-stage frequency divider comprises a first stage and a second stage. The first stage comprises a first input node configured to receive a first reference signal from the voltage controlled oscillator, one or more first switches configured to receive a first control signal, and first stage circuitry configured to generate a second reference signal from the first reference signal. The first reference signal has a first radio frequency, and the second reference signal has a second radio frequency that is a quotient of the first radio frequency and a first divisor controlled by the first control signal. The second stage comprises a second input node configured to receive the second reference signal from the first stage, one or more second switches configured to receive a second control signal, and second stage circuitry configured to generate a third reference signal from the second reference signal. The third reference signal has a third radio frequency that is a quotient of the second radio frequency and a second divisor controlled by the second control signal. The duty-cycle converter is configured to receive an output of the multi-stage frequency divider.

Implementations of the second example may, in some cases, include one or more of the following features. The duty-cycle converter may be configured to receive a differential output of the multi-stage frequency divider, and the duty-cycle converter may comprise a first inverter having a third input node configured to receive a positive signal of the differential output, and may comprise a second inverter having a fourth input node configured to receive a negative signal of the differential output. A first output node of the first inverter is communicatively coupled to a second output node of the second inverter to form an output node of the duty-cycle converter. The first inverter may comprise a first p-type transistor and a first n-type transistor, and the second inverter may comprise a second p-type transistor and a second n-type transistor. The first p-type transistor has a source operatively coupled to a first power supply node, and the first n-type transistor has a source operatively coupled to a second power supply node. A gate of the first p-type transistor and a gate of the first n-type transistor are operatively coupled together as the third input node of the first inverter. The second p-type transistor has a source operatively coupled to the first power supply node, and the second n-type transistor has a source operatively coupled to the second power supply node. A gate of the second p-type transistor and a second of the second n-type transistor are operatively coupled together as the fourth input node of the second inverter. Respective drains of the first p-type transistor, the first n-type transistor, the second p-type transistor, and the second n-type transistor are operatively coupled together as the output node of the duty-cycle converter.

Implementations of the second example may, in some cases, include one or more of the following features. The duty-cycle converter may be configured to output a reference signal having a twenty-five percent duty-cycle. The first reference signal may be a differential first reference signal; the second reference signal may be a differential second reference signal; and the third reference signal may be a differential third reference signal.

Implementations of the second example may, in some cases, include one or more of the following features. The first stage of the multi-stage frequency divider may comprise a first signal path and a second signal path, and the second stage of the multi-stage frequency divider may comprise a third signal path and a fourth signal path. The first signal path is communicatively coupled to the first input node and comprises a first switch of the one or more first switches. The first switch is controllable by the first control signal. The second signal path is communicatively coupled to the first input node and comprises a first frequency divider and a second switch of the one or more first switches. The first frequency divider is configured to divide the first radio frequency of the first reference signal by a third divisor that is greater than one. The second switch is controllable by a complementary signal of the first control signal. A first path signal from the first signal path or a second path signal from the second signal path is the second reference signal based on controlling the first switch and the second switch. The third signal path is communicatively coupled to the second input node and comprises a second frequency divider and a third switch of the one or more second switches. The second frequency divider is configured to divide the second radio frequency of the second reference signal by a fourth divisor that is greater than one. The third switch is controllable by the second control signal. The fourth signal path is communicatively coupled to the second input node and comprises a third frequency divider and a fourth switch of the one or more second switches. The third frequency divider is configured to divide the second radio frequency of the second reference signal by a fifth divisor that is greater than one and different from the fourth divisor. The fourth switch being controllable by a third control signal. A third path signal from the third signal path or a fourth path signal from the fourth signal path is the third reference signal based on controlling the third switch and the fourth switch.

In a third example, an original reference signal is output from a voltage controlled oscillator to an input node of a first stage of a multi-stage frequency divider; outputting a first stage reference signal from the first stage of the multi-stage frequency divider to an input node of a second stage of the multi-stage frequency divider, and outputting a second stage reference signal from the second stage of the multi-stage frequency divider. The first stage reference signal is selected from first signal paths in the first stage of the multi-stage frequency divider, and the first signal paths are configured to produce signals with distinct frequencies. The second stage reference signal is selected from second signal paths in the second stage of the multi-stage frequency divider, and the second signal paths are configured to produce signals with distinct frequencies.

Implementations of the third example may, in some cases, include one or more of the following features. The second stage reference signal is input to an input node of a duty-cycle converter; and outputting a duty-cycle converted second stage reference signal from an output node of the duty-cycle converter. A low frequency signal is up-converted to a radio frequency signal using the duty-cycle converted second stage reference signal. A radio frequency signal is down-converted to a low frequency signal using the duty-cycle converted second stage reference signal. The second stage reference signal may have a duty-cycle of approximately 50%, and the duty-cycle converted second stage reference signal may have a duty-cycle of approximately 25%. The duty-cycle converter may comprise a first inverter and a second inverter, and an output of the first inverter and an output of the second inverter may be communicatively coupled together as the output node of the duty-cycle converter. Each of the first inverter and the second inverter may comprise a p-type transistor and an n-type transistor. The p-type transistor has a source operatively coupled to a first power supply node. The n-type transistor has a source operatively coupled to a second power supply node. A gate of the p-type transistor and a gate of the n-type transistor are operatively coupled together, and a drain of the p-type transistor and a drain of the n-type transistor are operatively coupled together.

In a fourth example, a wireless sensor device includes an antenna, a mixer and a local oscillator. The antenna is configured to wirelessly communicate a wireless signal, and the mixer is communicatively coupled to the antenna. The local oscillator includes a voltage controlled oscillator (VCO), a frequency divider circuit and a duty-cycle converter communicatively coupled between the mixer and the frequency divider circuit. The frequency divider circuit is communicatively coupled between the VCO and the duty-cycle converter. The frequency divider circuit includes an input node configured to receive a VCO signal from the VCO; switches configured to receive respective control signals; and circuitry configured to generate a reference signal from the VCO signal. The VCO signal has a VCO frequency, and the reference signal has a reference signal frequency that is a quotient of the VCO frequency and a divisor controlled by the control signals.

Implementations of the fourth example may, in some cases, include one or more of the following features. The frequency divider circuit is implemented as a multi-stage frequency divider. The multi-stage frequency divider includes a first stage configured to selectively output a first signal from at least one of a first plurality of signal paths, each of the first plurality of signal paths being configured to provide a signal having a distinct frequency. The multi-stage frequency divider includes a second stage configured to selectively output a second signal from at least one of a second plurality of signal paths, each of the second plurality of signal paths being configured to provide a signal having a distinct frequency.

A number of examples have been described. Nevertheless, it will be understood that various modifications can be made. Accordingly, other implementations are within the scope of the following claims.