ISOLATED SWITCHING CONVERTER WITH SOFT SWITCHING AND CONTROL METHOD THEREOF

A controller used in an isolated switching converter with a transformer, a primary switch and a secondary switch, the controller has a maximum sense circuit for providing a first voltage signal representative of a maximum value of a first voltage across the secondary switch, and a timer for starting timing when the first voltage increases to a second voltage signal less than the first voltage signal and stop timing when the first voltage increases to the first voltage signal, and the timing duration of the timer is a first time interval. The secondary switch is turned on for a second ON-time after a current flowing through the secondary switch decreases to zero. The second ON-time of the secondary switch is adjusted so that the first time interval of the next switching cycle is close to a first time threshold.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of CN application 202210891437.3, filed on Jul. 27, 2022, and incorporated herein by reference.

TECHNICAL FIELD OF THE INVENTION

The present invention generally relates to electronic circuits, and more particularly but not exclusively, to isolated switching converters with soft switching and associated control methods.

BACKGROUND OF THE INVENTION

The Universal Serial Bus (USB) Power Delivery (PD) standard has started gaining popularity among smart devices and notebook computer manufacturers. The USB PD standard allows for a higher power level (up to 100 W) and adaptive output voltages (e.g., 5V to 28V), this trend requires higher power, faster and smaller isolated switching power supplies.

However, as silicon-based devices approach their theoretical performance limits, further performance improvements of the existing isolated power supplies have become more difficult to meet the higher power delivery requirements of PD standards while maintaining high efficiency and low cost.

SUMMARY OF THE INVENTION

An embodiment of the present invention discloses a controller used in an isolated switching converter, the switching converter has a transformer having a primary winding and a secondary winding, a primary switch coupled to the primary winding and a secondary switch coupled to the secondary winding. The controller comprises a maximum sense circuit, a voltage divider, a timer, and an ON-time control circuit. The maximum sense circuit is coupled to the secondary switch to sense a first voltage across the secondary switch and configured to provide a first voltage signal representative of a maximum value of the first voltage. The voltage divider is configured to receive the first voltage signal and provide a second voltage signal less than the first voltage signal. The timer is configured to start timing in response to the first voltage increasing to the second voltage signal and stop timing in response to the first voltage increasing to the first voltage signal, and the timing duration of the timer is a first time interval. The ON-time control circuit is configured to provide an ON-time control signal to control a second ON-time of the secondary switch. The secondary switch is turned on for the second ON-time after a current flowing through the secondary switch decreases to zero. The ON-time control circuit is configured to adjust the second ON-time of the secondary switch so that the first time interval of the next switching cycle is close to a first time threshold.

Another embodiment of the present invention discloses an isolated switching converter. The switching converter comprises a transformer having a primary winding and a secondary winding, a primary switch coupled to the primary winding, a secondary switch coupled to the secondary winding, and a controller. The controller comprises a maximum sense circuit, a voltage divider, a timer, and an ON-time control circuit. The maximum sense circuit is coupled to the secondary switch to sense a first voltage across the secondary switch and configured to provide a first voltage signal representative of a maximum value of the first voltage. The voltage divider is configured to receive the first voltage signal and provide a second voltage signal less than the first voltage signal. The timer is configured to start timing in response to the first voltage increasing to the second voltage signal and stop timing in response to the first voltage increasing to the first voltage signal, and the timing duration of the timer is a first time interval. The ON-time control circuit is configured to provide an ON-time control signal to control a second ON-time of the secondary switch. The secondary switch is turned on for the second ON-time after a current flowing through the secondary switch decreases to zero. The ON-time control circuit is configured to adjust the second ON-time of the secondary switch so that the first time interval of the next switching cycle is close to a first time threshold.

Yet another embodiment of the present invention discloses a control method used in an isolated switching converter. The switching converter has a transformer having a primary winding and a secondary winding, a primary switch coupled to the primary winding and a secondary switch coupled to the secondary winding. The control method comprises: providing a first voltage signal by sampling and holding a maximum value of a first voltage across the secondary switch, providing a second voltage signal less than the first voltage signal, starting a timer set to a first time interval in response to the first voltage increasing to the secondary voltage signal and resetting the timer to the first time interval in response to the first voltage increasing to the first voltage signal, turning on the secondary switch for a second ON-time after a current flowing through the secondary switch decreases to zero; and providing an ON-time control signal to control the second ON-time so that the first time interval of the next switching cycle is close to a first time threshold.

DETAILED DESCRIPTION OF THE INVENTION

Reference to “one embodiment”, “an embodiment”, “an example” or “examples” means: certain features, structures, or characteristics are contained in at least one embodiment of the present invention. These “one embodiment”, “an embodiment”, “an example” and “examples” are not necessarily directed to the same embodiment or example. Furthermore, the features, structures, or characteristics may be combined in one or more embodiments or examples. In addition, it should be noted that the drawings are provided for illustration, and are not necessarily to scale. And when an element is described as “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or there could exist one or more intermediate elements. In contrast, when an element is referred to as “directly connected” or “directly coupled” to another element, there is no intermediate element.

The present invention can be used in any isolated switching converter with soft switching. In the following detailed description, for the sake of brevity, only a flyback converter is taken as an example to explain and describe the working principle of the present invention.

FIG.1shows a block diagram of an isolated switching converter100in accordance with an embodiment of the present invention. As shown inFIG.1, the isolated switching converter100comprises a transformer T, a primary switch10, a secondary switch20and a controller30. The transformer T for providing isolation between a primary side and a secondary side, and has a primary winding, a secondary winding and an auxiliary winding. The primary winding and the secondary winding both have a first terminal and a second terminal. The first terminal of the primary winding receives an input voltage Vin, the first terminal of the secondary winding provides a DC output voltage Vo, and the second terminal of the secondary winding is coupled to a secondary reference Ground (SGND). The primary switch10is coupled between the second terminal of the primary winding and a primary reference ground (PGND). The secondary switch20is coupled between the second terminal of the secondary winding and a load. However, those skilled in the art should know that the secondary switch20may also be coupled between the first terminal of the secondary winding and the load.

The primary switch10is coupled to the primary winding, and controls the energy stored in the primary winding to be transferred to the secondary winding. The secondary switch20is coupled to the secondary winding, and serves as a synchronous rectifier to replace a traditional rectifier diode, to reduce loss and improve the efficiency of the isolated switching converter100. In addition, the switching loss may be further reduced by using the parasitic elements of the circuit (e.g., an output capacitance of the primary switch10and an excitation inductance of the transformer T) to turn on the primary switch10at zero voltage.

In the embodiment shown inFIG.1, the switching converter100operates in a discontinuous conduction mode (DCM), and the primary switch10is turned on with zero voltage turning-on technique. Before the primary switch10will be turned on at zero voltage, the secondary switch20is turned on twice. In detail, after the primary switch10is turned off, the secondary switch20is turned on. After a current flowing through the secondary switch20crosses zero, the secondary switch20is turned off. Subsequently, the secondary switch20will be turned on again for a second ON-time, to generate a negative current flowing through the magnetized inductance of the transformer T. This negative current is used to discharge the output capacitance of the primary switch10. After the secondary switch20is turned off again, the primary switch10is turned on and the next switching cycle starts. In the embodiment of the present invention, the second ON-time of the secondary switch20is adjusted in real time based on a comparison between a first time interval tDand a first time threshold tD_refin each switching cycle, so as to completely discharge the output capacitance of the primary switch10, and the first time interval tDin the subsequent switching cycle is close to the first time threshold tD_ref, to achieve full zero-voltage switching (Full ZVS) of the primary switch10.

In the example shown inFIG.1, the controller30comprises a maximum sense circuit301, a voltage divider302, a timer303, a threshold generator304, an ON-time control circuit305, a secondary logic circuit306, and a twice off detection circuit307, an isolation circuit308, a zero cross detection circuit309and a primary logic circuit310. In one embodiment, the controller30is an integrated circuit chip having a plurality of pins.

As shown inFIG.1, the maximum sense circuit301is coupled to a drain terminal of the secondary switch20via a SRD pin to detect a first voltage VSec_SRacross the secondary switch20, and has an output terminal to provide a first voltage signal VSRDrepresentative of a maximum of the first voltage VSec_SR. The voltage divider302is coupled to the output terminal of the maximum sense circuit301to receive the first voltage signal VSRD, and provides a second voltage signal k*VSRDat its output terminal. Wherein k is a ratio greater than 0 and less than 1. In one embodiment, the voltage divider302divides the first voltage signal VSRDto provide the second voltage signal k*VSRD. The voltage divider302may comprise a resistive voltage divider or a capacitive voltage divider. In another embodiment, the voltage divider302subtracts a bias voltage signal (1−k)*VSRDfrom the first voltage signal VSRDto provide the second voltage signal k*VSRDat the output terminal.

In the embodiment shown inFIG.1, the timer303has a first input terminal, a second input terminal, a third input terminal and an output terminal, wherein the first input terminal is coupled to the drain terminal of the secondary switch20through the SRD pin for receiving the first voltage VSec_SRacross the secondary switch20, the second input terminal is coupled to the output terminal of the maximum sense circuit301to receive the first voltage signal VSRD, the third input terminal is coupled to the output terminal of the voltage divider302to receive the second voltage signal k*VSRD. The timer303starts timing when the first voltage VSec_SRacross the secondary switch increases to the second voltage signal k*VSRD, and then stop timing when the first voltage VSec_SRacross the secondary switch20increases to the first voltage signal VSRD. The timing duration of the timer303is the first time interval tD. In one embodiment, the timer303may include a combination of multiple comparators and gate circuits.

In the example shown inFIG.1, the threshold generator304is configured to generate a second control signal TDREF. In one embodiment, the second control signal TDREF has an effective width equal to the first time threshold tD_ref. In one embodiment, the threshold generator304is coupled to a reference resistor RTDlocated outside of the controller30via a ZVS pin. In one embodiment, the user may select the reference resistor RTD to set the first time threshold tD_ref.

In the example shown inFIG.1, the ON-time control circuit305has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to receive a first control signal TD, the second input terminal is coupled to receive the second control signal TDREF. Based on the first control signal TD and the second control signal TDREF, the ON-time control circuit305compares the first time interval tDwith the first time threshold tD_refand provides an ON-time control signal ZOFF at the output terminal to control the second ON-time of the secondary switch20. The secondary switch is turned on for the second ON-time after a current flowing through the secondary switch decreases to zero. The second ON-time of the secondary switch20is generated and adjusted based on the comparison result between the first time interval tDand the first time threshold tD_ref, so that in the next switching cycle, the first time interval tDis closer to the first time threshold tD_ref. In one embodiment, when the first time interval tDis less than the first time threshold tD_ref, the second ON-time of the secondary switch20is extended. When the first time interval tDis longer than the first time threshold tD_ref, the second on-time of the secondary switch20is shorten. Finally, in the subsequent switching cycle, the first time interval tDis closer to the first time threshold tD_ref.

Referring still toFIG.1, the secondary logic circuit306is coupled to the ON-time control circuit305to receive the ON-time control signal ZOFF, and is configured to generate a secondary control signal CTRLS, which is coupled to a control terminal of the secondary switch20through a SDrv pin, to control the turning-on and turning-off of the secondary switch20.

The twice off detection circuit307is configured to provide a primary on enable signal PRON when the secondary switch20is turned off after the second ON-time of the secondary switch20.

The isolation circuit308has an input terminal configured to receive the primary on enable signal PRON and an output terminal for outputting a synchronous signal SYNC electrically isolated from the primary on enable signal PRON, so as to achieve electrical isolation between the primary side and the secondary side. The isolation circuit308may comprise opto-coupler, transformer, capacitor or any other suitable electrical isolation device. In other embodiments, the isolation circuit308may be located outside of the controller30.

The zero cross detection circuit309is configured to detect if a voltage VPri_DSacross the primary switch10crosses zero, and provide a voltage zero-crossing detection signal PON. In one embodiment, the zero cross detection circuit309is coupled to the auxiliary winding of the transformer T, and receives a voltage detection signal VZCD representative of the voltage VPri_DSacross the primary switch10through a ZCD pin of the controller30, and compares the voltage detection signal VZCD with a zero-crossing threshold VZCD_THand provides the voltage zero-crossing detection signal PON at the output terminal based on the comparison. In one embodiment, the zero-crossing threshold VZCD_THis 20 mV.

The primary logic circuit310is coupled to the output terminal of the isolation circuit308to receive the synchronous signal SYNC, and is further coupled to the zero cross detection circuit309to receive the voltage zero-crossing detection signal PON, and generates a primary control signal CTRLP. The primary control signal CTRLP is provided to a control terminal of the primary switch10via a PDrv pin of the controller to control the primary switch10. In some embodiments, when the synchronous signal SYNC comes while the voltage VPri_DSacross the primary switch10crossing zero, the primary switch10is turned on after a time delay tDelay.

Generally, silicon-based devices (such as MOSFETs) require a large amount of energy to fully discharge their output capacitance to achieve zero-voltage switching due to their large output capacitance. However, in practical applications, the output capacitance of silicon-based device is often not fully discharged in consideration of both the cost and the loss. Therefore, when the zero-voltage switching technology is applied, a partial zero voltage switching is used, rather than a full zero voltage switching in the silicon-based devices. The voltage across the silicon-based device is often not 0V but 15-25V when the silicon-based device is turned on, the controller30achieves ZVS for only a part of its operating range. Such partial zero-voltage turning-on will not only increase the conduction loss, but also the secondary switch20will bear high spike voltage, resulting in worse electromagnetic interference.

In one embodiment, the primary switch10may include an emerging wide bandgap device, such as a gallium nitride (GaN) or silicon carbide (SiC), instead of a traditional silicon-based device. Wide bandgap devices may operate at higher switching frequencies without deterioration in efficiency and have output capacitances much lower than silicon-based devices, such devices will further reduce the size of isolated switching converters while achieving high efficiency.

Furthermore, the ON-time control circuit305shown inFIG.1may dynamically adjust the second ON-time of the secondary switch20by the comparison of the first time interval tDand the first time threshold tD_ref, so as to adaptively and fully discharge the output capacitance of the primary switch10according to the actual operation, to achieve the best performance. In one embodiment, the zero-crossing threshold VZCD_THis tens of millivolts, which is much smaller than the voltage when the silicon-based device is turned on with zero voltage switching technique.

FIG.2shows a flow diagram of a control method200for the isolated switching converter100in accordance with an embodiment of the present invention. The control method200comprises steps201˜208.

At step201, a first voltage signal VSRDis provided by sampling and holding a maximum value of a first voltage across the secondary switch20.

At step202, a second voltage signal k*VSRDis provided based on the first voltage signal VSRD. The second voltage signal k*VSRDis less than the first voltage signal VSRD. In one embodiment, k is a ratio greater than 0 and less than 1. In one embodiment, the second voltage signal k*VSRDis provided by dividing the first voltage signal VSRD. In another embodiment, a bias voltage signal (1−k)*VSRDis subtracted from the first voltage signal VSRDto provide the second voltage signal k*VSRD.

At step203, start the timer303set to the first time interval tDin response to the first voltage VSec_SRincreasing to the secondary voltage signal k*VSRD, and reset the timer303to the first time interval tDin response to the first voltage VSec_SRincreasing to the first voltage signal VSRD.

At step204, after a current flowing through the secondary switch20decreases to zero, the secondary switch20is turned on for a second ON-time TON.

At step205, the ON-time control signal ZOFF is provided to control the second ON-time TON so that the first time interval tDin the next switching cycle is close to the first time threshold tD_ref.

At step206, when the secondary switch20is turned off after the second ON-time TON, the primary on enable signal PRON is provided the isolation circuit308.

At step207, the synchronous signal SYNC electrically isolated from the primary on enable signal PRON is received through the isolation circuit308.

At step208, provide the primary control signal CTRLS for controlling the primary switch10based on the synchronous signal SYNC and the voltage zero-crossing detection signal PON indicating whether the voltage VPri_DSacross the primary switch crosses zero. In one embodiment, the primary switch10is turned on after a delay time, in response to the voltage VPri_DSacross the primary switch10crossing zero.

FIG.3shows a schematic diagram of a control principle for the second ON-time of the secondary switch in accordance with an embodiment of the present invention.

As shown inFIG.3, curve1shows the waveform of the voltage VSec_SRacross the secondary switch20when the second ON-time of the secondary switch20is 0. In other words, in curve1, when the secondary switch20is turned off after the current flowing through the secondary switch20decreases to zero, the secondary switch20is not turned on again. And wherein Tsshown inFIG.3is an oscillation period of the sinusoidal oscillation of the voltage VSec_SRacross the secondary switch20with an output voltage Vo as a center value after the current flowing through the secondary switch20decreases to zero.

Look up from curve1to curve5, the second ON-time of the secondary switch is increased gradually, and the voltage VSec_SRacross the secondary switch20when the primary switch10is turned on is also increased accordingly. When the primary switch10achieves full zero voltage switching, the voltage VSec_SRacross the secondary switch20is increased to the curve5as shown inFIG.3. The first time threshold tD_refis set using the following relationship:

where k is a ratio of the second voltage signal K*VSRDand the first voltage signal VSRD. In one embodiment, the ratio k=0.75.

Referring still to the curve3shown inFIG.3, after the second-ON time of the secondary switch20, the negative current is not enough to increase the voltage VSec_SRacross the secondary switch20up to the second voltage signal k*VSRDwhen the primary switch10is turned on.

In this case, the timing duration when the voltage VSec_SRacross the secondary switch20increases from the second voltage signal k*VSRDrise to the first voltage signal VSRDis 0, that is, the first time interval tDis timed be 0. Obviously, the first time threshold tD_refis greater than the first time interval tD. In response to a first time difference between the first time threshold tDref and the first time interval tD, the second ON-time of the secondary switch20is increased, to further increase the voltage VSec_SRacross the secondary switch20when the primary switch10is turned on in the next switching cycle, so that the first time interval tDof the next switching cycle is close to the first time threshold tDref. Compared to the curve3, as shown the curve4ofFIG.3, the voltage VSec_SRacross the secondary switch20when the primary switch10is turned on is increased in curve4, so that the first time interval tDis closer to the first time threshold tD_Ref. Until the voltage VSec_SRfollows the curve5, the first time interval tDis equal to the first time threshold tD_Ref, and the full zero-voltage switching is achieved.

It can be seen that, in order to achieve the full zero-voltage turning-on of the primary switch10, the second ON-time of the secondary switch20can be increased. A longer second ON-time may lead to a higher magnitude of negative current flowing through the secondary switch2. And subsequently when the primary switch10is turned on in the next switching cycle, a lower voltage VPri_DSacross the primary switch will be obtained, and thus the partial zero-voltage turning-on is improved to the full zero-voltage turning-on.

However, if the second ON-time of the secondary switch20is too long, it will cause the first time interval tDexceeds the first time threshold tD_Ref, causing unnecessary energy waste. In this case, in response to a second time difference ref/between the first time interval tDand the first time threshold tDthe ON-time control circuit305will reduce the second ON-time of the secondary switch20, so that the first time interval tDof the next switching cycle decreases and be close to the first time threshold tD_ref, to provide a minimum energy that enables the primary switch10to achieve the zero voltage switching. Therefore, the zero voltage switching of this embodiment may save the conduction loss of the primary switch10.

Taking k=0.75 as an example, according to the curve5, the time interval from 0.75*VSRDto VSRDis set to be the first time threshold tD_Ref. In one embodiment, the first time threshold tD_Refis determined by the external reference resistor RTD. Theoretically, regardless of the first voltage signal VSRDand the output voltage Vo, the first time threshold tD_Reffor the zero-voltage turning-on is a fixed value. Therefore, by selecting the appropriate resistor RTD, the full zero-voltage switching under different input and output voltages can be obtained.

Accordingly, according to the embodiments shown in this disclosure, the isolated switching converter100A may meet the high power density, high switching frequency, high efficiency, and electromagnetic interference standards required by USB PD applications, while maintaining the low cost.

FIG.4shows a schematic diagram of a controller30for an isolated switching converter in accordance with an embodiment of the present invention.

The controller30A shown inFIG.4is similar with the controller30shown inFIG.1, the difference is that the controller30A further comprises a primary off detection circuit311, a current zero cross detection circuit312and a quasi-resonant control circuit313located at the secondary side, and a current comparison circuit314located at the primary side.

In the example shown inFIG.4, the primary off detection circuit311is configured to detect if the primary switch10is off and provide a primary off detection signal PROFF. The primary off detection circuit311may detect whether the primary switch10is off based on the voltage VSec_SRacross the secondary switch20, the current flowing though the secondary switch20or a voltage across the secondary winding and so on. The primary off detection circuit311may also receive signals indicating whether the primary switch10is off from the primary side.

The current zero-crossing detection circuit312is configured to detect whether the current flowing through the secondary switch20crosses zero and generate a zero-crossing detection signal ZCD1. The quasi-resonant control circuit313is coupled to the secondary switch20and is configured to sense the voltage VSec_SRacross the secondary switch20when the secondary switch20is off, and provide an on control signal ZON corresponding to a target locked valley number for turning ON the secondary switch20. It will be understood by those of ordinary skill that the quasi-resonant control is only an example, and the isolated switching converter under discontinuous conduction mode controlled by other control methods also satisfies the spirit and protection scope of the present invention.

As mentioned above, the ON-time control circuit305adjusts the second ON-time of the secondary switch20, and generates the ON-time control signal ZOFF when the ON-time of the secondary switch20reaches the second ON-time TON.

The secondary logic circuit306A has a first input terminal, a second input terminal, a third input terminal, a fourth input terminal and an output terminal, wherein the first input terminal is coupled to the primary off detection circuit311to receive the primary off detection signal PROFF, the second input terminal is coupled to the output terminal of the current zero cross detection circuit312to receive the zero-crossing detection signal ZCD1, the third input terminal is coupled to the quasi-resonant control circuit313to receive the on control signal ZON, the fourth input terminal is coupled to the ON-time control circuit305A to receive the ON-time control signal ZOFF. The secondary logic circuit306A generates the secondary control signal CTRLS based on the primary off detection signal PROFF and the zero-crossing detection signal ZCD1to control the first switching of the secondary switch20. In addition, the secondary logic circuit306A also provides the secondary control signal CTRLS based on the on control signal ZON and the ON-time control signal ZOFF to control the second switching of the secondary switch20. When the twice off detection circuit307detects that the secondary switch20is turned off after the second ON-time, it provides the primary on enable signal PRON to the isolation circuit308.

In addition, the switching converter100A further comprises a current comparison circuit314. The current comparison circuit314has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives a primary current sensing signal ISENP representing the current flowing through the primary switch10, and the second input terminal receives a first threshold voltage VTH1. The current comparison circuit314compares the primary current sensing signal ISENP with the first threshold voltage VTH1, and generates a current comparison signal POFF at the output terminal. The primary logic circuit310is coupled to the output terminal of the current comparison circuit314to receive the current comparison signal POFF, and based on the current comparison signal POFF, the voltage zero-crossing detection signal PON and the synchronous signal SYNC, to generate the primary control signal CTRLP to control the primary switch10. When the current ISENP flowing through the primary switch10reaches the first threshold voltage VTH1, the primary switch10is turned off. The first threshold voltage VTH1may be a constant value, or may dependent on the synchronous signal SYNC.

FIG.5shows a working waveform diagram of the isolated switching converter in accordance with an embodiment of the present invention. As shown inFIG.5, in a switching cycle, for example, at time t1, the primary control signal CTRLP is changed from high level to low level, the primary switch10is turned off. After the primary switch10is turned off, the voltage VSec_SRacross the secondary switch20is changed from positive to negative, and thus the secondary control signal CTRLS changes from low level to high level, the secondary switch20is turned on for a first time.

After that, at time t2, when the current ISENS flowing through the secondary switch20decreases to cross zero, the secondary control signal CTRLS changes from high level to low level, the secondary switch20is turned off accordingly. The first conduction of the secondary switch20finishes.

Subsequently, when the currents flowing through the primary side and the secondary side are both zero, the energy storage element and the parasitic capacitance of the switch begin to resonate to generate a resonant voltage whose waveform is detected by the quasi-resonant circuit313located on the secondary side. At time t3, due to the quasi-resonant control, the voltage VSec_SRacross the secondary switch20is detected when the resonant voltage reaches the target locked valley number (e.g., a third valley) in the current switching cycle, the on control signal ZON changes from low level to high level, and the secondary control signal CTRLS also becomes high, and the secondary switch20is turned on again.

At time t4, when the rising edge of the ON-time control signal ZOFF comes, the secondary control signal CTRLS changes from high level to low level, the secondary switch20is turned off again. The second conduction of the secondary switch20finishes. As shown inFIG.5, the second ON-time of the secondary switch20is labeled as TON1.

In addition, the twice off detection circuit307detects the second turning-off of the secondary switch20after the second ON-time, and provides a primary on enable signal PRON. When a rising edge of the primary on enable signal PRON comes, almost at the same time, the synchronous signal SYNC outputted by the isolation circuit308also changes from low level to high level. Then when the zero cross detection circuit309detects if the voltage VZCDacross the auxiliary winding crosses zero, the primary switch10is turned on after a delay time tDelayin response to the voltage VZCDcrossing zero.

As shown inFIG.5, when the primary switch10is turned on at point A, the voltage VPri_DSacross the primary switch10is still relatively high, The timer303starts timing when the voltage VSec_SRacross the secondary switch20is quickly pulled up to the second voltage signal k*VSRD. The timer303stops timing when the voltage VSec_SRacross the secondary switch20increases to the first voltage signal VSRD, and the timing duration is the first time interval tD1. As shown inFIG.5, the first time interval tD1of the current switching cycle is very short and is much smaller than the first time threshold tD_ref.

According to an embodiment of the present invention, in order to achieve full zero voltage turning-on, the ON-time control circuit305is configured to adjust (increase or reduce) the second ON-time of the secondary switch20, based on the comparison between the first time interval tD1of the current switching cycle and the first time threshold tD_refprovided by the threshold generator304, so that the first time interval (labeled as tD2) of the subsequent switching cycle is more closer to the first time threshold tD_ref.

As shown inFIG.5, the second ON-time of the secondary switch20increases from TON1to TON2, and when the primary switch10is turned on at point B, the voltage VPri_DSacross the primary switch10is much smaller than the voltage level at point A. Then the timer303starts timing when the voltage VSec_SRacross the secondary switch20increases to the second voltage signal k*VSRDand stops timing when the voltage VSec_SRincreases to the first voltage signal VSRD. The timing duration of the timer303in this switching cycle is labeled as a time interval tD2. Since the time interval tD2is still less than the first time threshold tD_ref, the ON-time control circuit305continues to increase the second-ON time of the secondary switch20, from TON2to TON3. Subsequently, when the primary switch10is turned on at point C, the voltage VPri_DSacross the primary switch10is further reduced, and is further less than the voltage level at point B. At point C, the primary switch10is turned on at zero voltage. In the next switching cycle, the time interval tD3is closer to the first time threshold tD_ref.

It can be seen that, according to the embodiments of the present invention, the ON-time control circuit305dynamically adjust the second ON-time of the secondary switch20based on the comparison of the first time interval in the current switching cycle and the first time threshold tD_ref,and continuously adjust the second ON-time of the secondary switch, so that the first time interval of the next switching cycle is close to the first time threshold tD_ref. After one or more switching cycles, the primary switch10can achieve full zero voltage turning-on.

FIG.6shows a schematic diagram of a timer303A and a threshold generator304A in accordance with an embodiment of the present invention.

As shown inFIG.6, the timer303A comprises a first comparison circuit3031, a second comparison circuit3032and a logic circuit3033. The first comparison circuit3031compares the voltage VSec_SRacross the secondary switch20with the first voltage signal VSRD, and provides a first comparison signal CP1at the output terminal. In one embodiment, when the voltage VSec_SRacross the secondary switch20is increased to the first voltage signal VSRD, the first comparison signal CP1becomes a high level. In an example shown inFIG.6, the first comparison circuit3031compares a comparator CMP1. The inverting input terminal of the comparator CMP1is coupled to the output terminal of the maximum sense circuit301to receive the first voltage signal VSRD, the non-inverting input terminal is coupled to the SRD pin of the controller30A to receive the voltage VSec_SRacross the secondary switch20, the output terminal is configured to provide the first comparison signal CP1.

The second comparison circuit3032compares the voltage VSec_SRacross the secondary switch20with the second voltage signal k*VSRD, and provides a second comparison signal CP2at the output terminal. In one embodiment, when the voltage VSec_SRacross the secondary switch20is increase to the second voltage signal k*VSRD, the second comparison signal CP2becomes high level. In the example shown inFIG.6, the second comparison circuit3032compares a comparator CMP2. The inverting input terminal of the comparator CMP2is coupled to the output terminal of the voltage divider302to receive the second voltage signal k*VSRD, the non-inverting input terminal is coupled to the SRD pin of the controller30A to receive the voltage VSec_SR, the output terminal is configured to provide the second comparison signal CP2.

The logic circuit3033is configured to provide the first control signal TD based on the first comparison signal CP1and the second comparison signal CP2. In one embodiment, the high-level width of the first control signal TD is corresponding to the first time interval tp. In the example shown inFIG.6, the logic circuit3033comprises a RS flip-flop FF1. The RS flip-flop FF1has a set terminal, a reset terminal and an output terminal, wherein the set terminal receives the second comparison signal CP2, the reset terminal receives the first comparison signal CP1, and the output terminal is configured to provide the first control signal TD. In one embodiment, the high-level width of the first control signal TD is the first time interval tD.

The threshold generator304A is configured to provide the second control signal TDREF which has a high-level width corresponding to the first time threshold tD_ref. In the example shown inFIG.6, the threshold generator304A comprises a current mirror3041, a reference capacitor Cs, a switch control circuit3042and a third comparison circuit3043. The current mirror3041has a current setting terminal and a current output terminal, wherein the current setting terminal is coupled to the reference resistor RTDthrough the ZVS pin of the controller30A for setting a control current Is. The reference capacitor Cs has a first terminal and a second terminal, wherein the first terminal is coupled to the current output terminal of the current mirror3041, and the second terminal is coupled to the secondary reference ground (SGND pin).

The switch control unit3042is coupled to the output terminal of the second comparison circuit3032to receive the second comparison signal CP2, and in response to the second comparison signal CP2, charges the reference capacitor Cs with the control current Is. As shown inFIG.6, the switch control unit3042comprises a RS flip-flop FF2, a normally-on switch01and a normally-off switch Q2. The RS flip-flop FF2has a set terminal, a reset terminal and an output terminal, wherein the set terminal is coupled to the output terminal of the second comparison circuit3032to receive the second comparison signal CP2, and the reset terminal is coupled to receive the second control signal TDREF, the output terminal is coupled to the control terminal of the normally-on switch Q1. The normally-on switch Q1is coupled between a power supply VP and the first terminal of the reference capacitor Cs. The normally-off switch Q2is coupled in parallel with the reference capacitor Cs, and its control terminal is coupled to receive the second control signal TDREF.

The third comparison circuit3043compares the voltage VCs across the reference capacitor Cs with a reference voltage Vref, and generates the second control signal TDREF based on the comparison result. In the example shown inFIG.6, the third comparison circuit3043comprises a comparator CMP3. The inverting input terminal of the comparator CMP3is coupled to the first terminal of the reference capacitor Cs to receive the voltage VCs, the non-inverting input terminal receives the reference voltage Vref, and the output terminal is configured to provide the second control signal TDREF.

In one embodiment, the threshold generator304A further comprises a one-shot circuit3044, which is coupled between the output terminal of the third comparison circuit3043and the control terminal of the normally-on switch Q2, is configured to reset the voltage VCs to zero when the voltage VCs reaches the reference voltage Vref.

Referring still toFIG.6, the ON-time control circuit305has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to receive the first control signal TD, and the second input terminal is coupled to receive the second control signal TDREF, based on the first control signal TD and the second control signal TDREF, the ON-time control circuit305is configured to provide the ON-time control signal ZOFF, for controlling the second ON-time of the secondary switch20.

FIG.7shows a schematic diagram of an ON-time control circuit305A in accordance with an embodiment of the present invention. In the example shown inFIG.7, the ON-time control circuit305A comprises a duration comparison circuit3051, a charging control unit3052, a discharging control unit3053, a first capacitor C1, and a second capacitor C2and a fourth comparison circuit3054.

The duration comparison circuit3051has a first input terminal, a second input terminal, a first output terminal and a second output terminal, wherein the first input terminal is coupled to the output terminal of the timer303A to receive the first control signal TD, the second input terminal is coupled to the output terminal of the threshold generation circuit304A to receive the second control signal TDREF. Based on the first control signal TD and the second control signal TDREF, the duration comparison circuit3051is configured to provide a first enable signal T1at the first output terminal, and provides a second enable signal T2at the second output terminal. The first enable signal T1represents the first time difference between the first time threshold tD_refand the first time interval tD. The second enable signal T1represents the second time difference between the first time interval tD and the first time threshold tD_ref.

In the example shown inFIG.7, the duration comparison circuit3051comprises a first AND gate circuit AND1and a second AND gate circuit AND2. The first AND gate circuit AND1has a first input terminal, a second inverting input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the timer304A to receive the second control signal TDREF, the second reverse input terminal receives the first control signal TD, and the first AND gate circuit AND1provides the first enable signal T1at the output terminal. The first enable signal T1indicates that the first time interval tD is less than the first time threshold tD_ref. The second AND gate circuit AND2has a first input terminal, a second inverting input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the timer303A to receive the first control signal TD, the second reverse input terminal receives the second control signal TDREF, the second AND gate circuit AND2provides the second enable signal T2at the output terminal. The second enable signal T2indicates that the first time interval tDis greater than the first time threshold tD_ref.

The charging control unit3052receives the first enable signal T1, and controls a first charging current source I1to charge a first capacitor C1based on the first enable signal T1. As shown inFIG.7, the charging control unit3052is coupled between the output terminal of the first charging current source I1and the first terminal of the first capacitor C1, a power supply terminal of the first current source I1is coupled to a power supply, and the second terminal of the first capacitor C1is coupled to the secondary reference ground. The charging duration of the first current source I1to the capacitor C1is determined by the first time difference. In the example shown inFIG.7, the charging control unit3052comprises a switch S1coupled between an output terminal of the first charging current source I1and the first terminal of the first capacitor C1. In other embodiments, the first charging current source I1has an enable control terminal to charge the first capacitor C1only when the first enable signal T1is active.

The discharging control unit3053receives the second enable signal T2, and controls the first discharge current source I2to discharge the first capacitor C1based on the second enable signal T2. As shown inFIG.7, the discharging control unit3053is coupled between the first terminal of the first capacitor C1and the input terminal of the discharge current source I2, and the output terminal of the first discharging current source I2is coupled to the secondary reference ground. The discharging duration of the first discharge current source I2to the first capacitor C1is determined by the second time difference. In the embodiment shown inFIG.7, the discharging control unit3053comprises a switch S2coupled between the input terminal of the first discharge current source I2and the first terminal of the first capacitor C1. In other embodiments, the first discharge current source I2has an enable control terminal, and discharges the first capacitor C1only when the second enable signal T2is active.

The second capacitor C2has a first terminal and a second terminal, wherein the first terminal is coupled to the output terminal of the first charging current source11through a switch S3, and the second terminal is connected to the secondary reference ground. The switch S3is controlled by the on control signal ZON. When the secondary switch20is turned on after the current flowing through the secondary switch20decreases to zero, the first charging current source I1begins to charge the second capacitor C2, and the voltage VC2across the second capacitor C2starts to increase from zero. The fourth comparison circuit3054compares the voltage VCI across the first capacitor C1with the voltage VC2across the second capacitor C2, and generates the ON-time control signal ZOFF for control the second ON-time of the secondary switch20. In one embodiment, when the voltage VC2across the second capacitor C2increases to the voltage VC1across the first capacitor C1, the ON-time control signal ZOFF becomes high level, and the secondary switch20is turned off. In the example shown inFIG.7, the fourth comparison circuit3054comprises a comparator CMP4. The non-inverting input terminal of the comparator CMP4is coupled to the first terminal of the second capacitor C2to receive the voltage VC2across the second capacitor C2, and the inverting input terminal is coupled to the second terminal of the first capacitor C1to receive the voltage VC1across the first capacitor C1. The voltage VC1provides the ON-time control signal ZOFF at its output.

In the embodiment shown inFIG.7, when the secondary switch20is turned on again after the current flowing through the secondary switch20decreases to cross zero, that is, when the on control signal ZON changes from low level to high level, the voltage VC2across the second capacitor C2starts to increase from zero. When the voltage VC2across the second capacitor C2increases to reach the voltage VC1across the first capacitor C1, the output of the fourth comparison circuit3054is reversed, the ON-time control signal ZOFF at the output terminal changes from low level to high level, and the secondary switch20is turned off again. Subsequently, the voltage VC2across the second capacitor C2is reset to zero by an output of a one-shot circuit3055.

FIG.8illustrates a flow diagram of a method204for generating an ON-time control signal ZOFF in accordance with an embodiment of the present invention. The control method204comprises steps2041and2045.

At step2041, the first time interval of the current switching cycle is less than the first time threshold. In response to a first time difference between the first time threshold and the first time interval, a first charging current source is coupled to a first capacitor for charging the first capacitor.

At step2042, the first interval of the current switching cycle is less than the first time threshold. In response to a second time difference between the first time interval and the first time threshold, a first discharging current source is coupled to the first capacitor for discharging the first capacitor.

At step2043, in response to the second turning-on of the secondary switch after the current flowing through the secondary switch decreases to cross zero, the first charging current source is coupled to a second capacitor for charging the second capacitor, the voltage across the second capacitor starts to increase from zero.

At step2044, the voltage across the first capacitor is compared with the voltage across the second capacitor.

At step2045, when the voltage across the second capacitor is increased to the voltage across the first capacitor, the ON-time control signal is generated for control the second ON-time of the secondary switch.

In a further embodiment, the method204further comprises a step2046. At step2046, the voltage across the second capacitor is reset to zero.

Obviously, many modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described. It should be understood, of course, the foregoing disclosure relates only to a preferred embodiment (or embodiments) of the invention and that numerous modifications may be made therein without departing from the spirit and the scope of the invention as set forth in the appended claims. Various modifications are contemplated and they obviously will be resorted to by those skilled in the art without departing from the spirit and the scope of the invention as hereinafter defined by the appended claims as only a preferred embodiment(s) thereof has been disclosed.