Liquid crystal display panel, common inversion driving method, liquid crystal display device, and liquid crystal display driver

A driving method for driving an LCD panel having a counter electrode and a source line. In a first period, the counter electrode is driven to a potential VCOMH. In a second period, the counter electrode and the source line are short-circuited to a power supply interconnection having a power supply potential VCI. In a third period, the counter electrode is connected to a ground interconnection while the source line is kept to be short-circuited to the power supply interconnection. In a fourth period, the counter electrode is pulled down to a potential VCOML lower than a ground potential In a fifth period, the source line is driven to a potential corresponding to an image data while the counter electrode is kept to the potential VCOML. The electric power consumed in pulling down the counter electrode from a positive potential to a negative potential can be effectively reduced.

INCORPORATION BY REFERENCE

This patent application is based on Japanese Patent Application No. 2007-283116. The disclosure of the Japanese Patent Application is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display device and, more specifically, to a driving technique for a liquid crystal panel of a liquid crystal display device that employs common inversion driving.

2. Description of Related Art

In driving of the liquid crystal display, in order to avoid so-called ghosting, the inversion drive is performed. In the inversion drive, the polarity of a driving voltage applied to each pixel (that is, potential polarity of a pixel electrode for a counter electrode) at an appropriate time interval. As an example of inversion drive, in a frame inversion drive, a driving voltage of each pixel is inverted for every one frame period.

However, in a simple frame inversion drive, flickers tend to become apparent. Therefore, when performing the frame inversion drive, a polarity of the driving voltage applied to each pixel is inverted at adequate spatial interval for suppressing the flickers. For example, one of widely-employed inversion drive techniques is the dot inversion drive which drives pixels in such a manner that the polarities of the driving voltages for neighboring pixels become opposite from each other both in a vertical direction and a horizontal direction. Another one of those widely-employed inversion drive techniques is the horizontal line inversion drive which inverts a polarity of the driving voltage for each pixel by every prescribed number of horizontal line(s). The inversion cycle of the horizontal lines for inverting the driving voltage can be determined variously. For example, the horizontal line inversion drive which inverts a polarity of the driving voltage for every horizontal line is referred to as the 1H inversion drive. The horizontal line inversion drive which inverts the polarity of the driving voltage by a unit of two horizontal lines may be referred to as the 2H inversion drive.

The inversion drive can be classified from another viewpoint based on a method for driving the counter electrode. That is, the inversion drive can be largely classified into the common constant drive and the common inversion drive. The common constant drive is a driving method which keeps potential of the counter electrode constant. The common inversion drive is a driving method which inverts the potential of the counter electrode in accordance with a cycle at which a polarity of the driving voltage of the pixel is inverted. The common inversion drive is preferable than the common constant drive if it can be employed, since it is capable of reducing an operating voltage of a driving circuit which generates the driving voltage of the pixel. When the dot inversion drive is employed, the common inversion drive cannot be employed. Thus, the common constant drive is employed for such case. However, in a case where the horizontal line inversion drive is to be performed, the common inversion drive is normally employed.

One of the problems for employing the common inversion drive is that it requires large power for driving the counter electrode, since parasitic capacitance of the counter electrode is generally large. This is not preferable, because it increases the power consumption of the liquid crystal display device.

One of the methods for reducing the power consumption of the liquid crystal display device in a case that the common inversion drive is employed is to short-circuit source lines (also referred to as data lines or signal lines in general) of the liquid crystal display panel and the common electrodes before driving the common electrodes. This makes it possible to utilize electric charges accumulated in the source lines and the counter electrode effectively and to reduce the power required for driving the source lines and the counter electrode effectively. Such technique is disclosed in Japanese Laid-Open Patent Application JP-P2007-101570A (referred to as Patent Document 1 in the following), for example.

FIG. 1is a block diagram showing a structure of a liquid crystal display device disclosed in the Patent Document 1. A driving device600for driving a liquid crystal display panel512includes a source line driving circuit520for driving source lines S1to Sn and a power supply circuit542. The power supply circuit542includes a counter electrode voltage supply circuit560which generates a counter electrode voltage to be supplied to a counter electrode VCOM, and supplies the counter electrode voltage to the counter electrode VCOM. The source line driving circuit520includes short-circuiting circuits SHT1to SHTN for short-circuiting the counter electrode VCOM and the source lines S1to Sn. The short-circuiting circuits SHT1to SHTN operate in response to a polarity signal POL and a control signal BSC generated in accordance with an electric charge reuse period designating signal. The power supply circuit542includes the counter electrode voltage supply circuit560which generates the driving voltage of the counter electrode VCOM in accordance with the polarity of the driving voltage of the pixel, and a voltage setting circuit562which supplies either the voltage supplied from the counter electrode voltage supply circuit560or a set voltage VSET to the counter electrode VCOM. The set voltage VSET is a potential close to a ground potential VSS. The voltage setting circuit562operates in response to the control signal VSC that is generated in accordance with the polarity signal POL and the electric charge reuse period designating signal.

FIG. 2is a timing chart showing an operation of the liquid crystal display device shown inFIG. 1. InFIG. 2, a curve with reference code S1shows variation of a potential of a given source line Sj, and a curve with reference code VCOM shows variation of a potential of the counter electrode VCOM. Note thatFIG. 2shows an operations of the liquid crystal display device when the liquid crystal display panel512is “normally-white”.

In the liquid crystal display device shown inFIG. 1, driving procedures for the source lines S1to Sn and the counter electrode VCOM are different for a case where the polarity of the driving voltage of the pixel is changed from positive to negative and for a case where the polarity is changed from negative to positive. In other words, the driving procedures are different for a case where the counter electrode VCOM is pulled up to a potential VCOMH and for a case where it is pulled down to a potential VCOML. Note here that the potential VCOMH is a predetermined positive potential that is to be set for the counter electrode VCOM when the polarity of the driving voltage of the pixel is negative, and the potential VCOML is a predetermined negative potential that is to be set for the counter electrode VCOM when the polarity of the driving voltage of the pixel is positive.

When the polarity of the driving voltage of the pixel is changed from positive to negative, first, the counter electrode VCOM is driven to the setting potential VSET. Specifically, the voltage setting period signal is asserted, the setting potential VSET is selected by the voltage setting circuit562, and the counter electrode VCOM is driven to the setting potential VSET. Subsequently, the electric charge reuse period designating signal is asserted. Thereby, the counter electrode VCOM and the source lines S1to Sn are short-circuited through the short-circuiting circuits STH1to STHn. With this, the counter electrode VCOM and the source lines S1to Sn come to have a mean potential of the source lines S1to S2and the counter electrode VCOM without electric power consumption. In this procedure, the counter electrode VCOM is driven to the setting potential in advance.

This is done to prevent the source lines S1to S2from having a negative potential, when the counter electrode VCOM and the source lines S1to Sn are short-circuited. After the counter electrode VCOM and the source lines S1to Sn are short-circuited, each pixel connected to the source lines S1to Sn is driven to a predetermined driving voltage.

In the meantime, when the polarity of the driving voltage of the pixel is changed from negative to positive, the counter electrode VCOM and the source lines S1to Sn are short-circuited (without driving the counter electrode VCOM to the setting potential VSET). After the counter electrode VCOM and the source lines S1to Sn are short-circuited, each pixel connected to the source lines S1to Sn is driven to a predetermined driving voltage.

In any cases, by short-circuiting the counter electrode VCOM and the source lines S1to Sn, the electric charges accumulated in the counter electrode VCOM or the source lines S1to Sn are reutilized effectively. As a result, the power required for driving the counter electrode VCOM and the source lines S1to Sn can be reduced.

SUMMARY

However, the inventor of the present invention has found that a process for changing the driving voltage of each pixel from negative to positive (that is, process for pulling down the counter electrode VCOM to the potential VCOML from the potential VCOMH) is not optimum in a reference technique described above, and that it is possible to reduce the power consumption further. This is related to a fact that the driving method of the above mentioned reference technique does not sufficiently consider that the source lines S1to Sn are electrically coupled to the counter electrode VCOM by parasitic capacitance. As described above, with the driving method of the reference technique, the procedure for pulling down the counter electrode VCOM to the potential VCOML includes two steps. That is, the source lines S1to Sn and the counter electrode VCOM are short-circuited in an electric charge reuse period and, thereafter, the source lines S1to Sn are driven to a predetermined potential and the counter electrode VCOM is driven to the potential VCOML in a driving period. It is true that the power is not consumed in the electric charge reuse period, since the source lines S1to Sn and the counter electrode VCOM are simply short-circuited in that period. However, unnecessarily large amount of power is consumed in the driving period, due to a fact that the source lines S1to Sn are electrically coupled to the counter electrode VCOM by parasitic capacitance.

More specifically, with the driving method of the reference technique, the counter electrode VCOM is pulled down to the potential VCOML while driving the source lines S1to Sn to a predetermined potential. When the counter electrode VCOM is pulled down, a potential of the source lines S1to Sn also follows to go down because the source lines S1to Sn are electrically coupled to the counter electrode VCOM by the parasitic capacitance. To drive the source lines S1to Sn to the predetermined potential by canceling such action, the power for canceling such action that works to lower the potential of the source lines S1to Sn is required in addition to the power required for driving the source lines S1to Sn to the predetermined potential. That is, provided that the potential of the source lines S1to Sn and the counter electrode VCOM after being short-circuited is VSH™, and the predetermined potential of the source line Sj is Vj, it is necessary to have the power that can cancel the action working to pull down the source line Sj by an amount of voltage (VSHT−VCOML) and then to pull up the source line Sj by an amount of voltage (Vj−VSHT) in order to drive the source line Sj to the potential Vj.

Similarly, with the reference technique, the source lines S1to Sn are pulled up, when pulling down the counter electrode VCOM to the potential VCOML. Since the source lines S1to Sn are electrically coupled to the counter electrode VCOM by the parasitic capacitance, the potential of the counter electrode VCOM also follows to go up when the source lines S1to Sn are pulled up. To drive the counter electrode VCOM to the predetermined potential VCOML by canceling such action, the power for canceling such action that works to boost up the potential of the counter electrode VCOM is required in addition to the power that is required for driving the counter electrode VCOM to the potential VCOML.

Such conditions bring particularly serious results when the source lines S1to Sn are driven by a power supply voltage generated by a boost-up power supply. When driving the liquid crystal panel, normally, the source lines S1to Sn are driven by a power supply voltage generated by a double boost-up power supply. For example, when the source lines S1to Sn are pulled up by supplying an electric charge to the source lines S1to Sn by the power supply voltage generated by the double boost-up power supply, the electric charge of twice as much is consumed compared to a case where the double boost-up power supply is not used. Therefore, the increase in the power required for driving the source lines S1to Sn becomes more serious when using the boost-up power supply.

In the followings, electric changes required for driving the counter electrode VCOM and the source lines S1to Sn when executing the operations ofFIG. 2will be calculated. In this calculation, it is assumed that the pixels of the liquid crystal display panels512are in a structure shown inFIG. 3. That is, a gate line G1is connected to a gate of a TFT, and a source line Sj is connected to a source of the TFT. A drain of the TFT is connected to the pixel electrode and a storage capacitance Cst. Electrically, a liquid crystal capacitance CI and the storage capacitance Cst are connected between the drain of the TFT and the counter electrode VCOM. A parasitic capacitance Csv is formed between the counter electrode VCOM and the source lines S1to Sn, and a parasitic capacitance Cgv is formed between the counter electrode VCOM and the gate lines G1to Gm.

When calculating the electric charges required for driving the counter electrode VCOM and the source lines S1to Sn, only the parasitic capacitance Csv between the counter electrode VCOM and the source lines S1to Sn is taken into consideration, and the liquid crystal pixel capacitance CI, the storage capacitance Cst, and the parasitic capacitance Cgv are neglected. Regarding the liquid crystal pixel capacitance CI and the storage capacitance Cst, the electric charges are transferred only between the liquid crystal capacitance CI and the storage capacitance Cst of each pixel of a selected line, and the capacitance per pixel is also insignificant. Thus, the electric current generated in the liquid crystal capacitance CI and the storage capacitance Cst is small, so that it is neglected in the explanations below. Regarding the parasitic capacitance of the gate line Gj, the capacitance of the gate of the TFT is more dominant than the parasitic capacitance Cgv between the counter electrode VCOM and the gate lines G1to Gm. Further, the number of gate lines provided in the structure of the typical liquid crystal panel is smaller than that of the source lines, so that the parasitic capacitance Cgv is not so significant. Thus, it is neglected in the explanations below. The most influential factor for the current consumption when driving the counter electrode VCOM and the source lines S1to Sn is the parasitic capacitance Csv between the counter electrode VCOM and the source lines S1to Sn.

The electric charges are calculated under the following conditions.

It is assumed that the potential VCOML is −1 V, and the potential VCOMH is +4 V. The possible range of the source line potential is assumed to be +0.5 to 4.5 V. It is also assumed that a source line driving circuit and a circuit for generating the potential VCOMH are driven by a power supply voltage that is generated by the double boost-up power supply which operates by receiving the power supply voltage VCI (−2.8 V). In the meantime, it is assumed that the circuit for generating the potential VCOML is driven by the power supply voltage that is generated by a negative voltage power supply which operates by receiving the power supply voltage VCI (=2.8 V). Further, a factor that is most influential to the electric charge consumption when driving the counter electrode VCOM and the source lines S1to Sn is the parasitic capacitance Csv between the counter electrode VCOM and the source lines S1to Sn. Thus, the other parasitic capacitance Cgv, the liquid crystal pixel capacitance CI, and the storage capacitance Cst are neglected. The parasitic capacitance Csv between the source lines S1to Sn and the counter electrode VCOM is assumed to be C[F]. Further, the liquid crystal panel is assumed to be a normally-white panel. That is, the source lines are driven to a potential that is close to the potential of the counter electrode VCOM for white display (by which a pixel is displayed in white color), and the source lines are driven to a potential that is deviated from the potential of the counter electrode VCOM for black display. The source lines are driven to an intermediate potential for gray display.

FIG. 4is a table showing the electric charge consumed when pulling up the counter electrode VCOM to the potential VCOMH from the potential VCOML.FIG. 5is a table showing the electric charge consumed when pulling down the counter electrode VCOM from the potential VCOML to the potential VCOMH.

(1) A Case where Counter Electrode VCOM is Pulled Up from Potential VCOML to Potential VCOMH

Hereinafter, at first, the calculation of the electric charge consumed when the LCD panel2provides black display is described.

A period T1is considered as a period where the liquid crystal display device1is in an initial state. In the period T1, the counter electrode VCOM is kept to the potential VCOML (=−1 [V]. Further, the source lines S1to Sn are driven to 4.5 V. In the period T1, there is no transfer of the electric charge, so that no electric charge is consumed.

In a period T2, the voltage setting period designating signal is asserted, and the counter electrode VCOM is driven to the setting potential VSET from the potential VCOML. In the Patent Document 1 mentioned above, it is so depicted that the setting potential VSET is the ground potential VSS or a potential slightly higher than the ground potential VSS. However, it is assumed herein that the setting potential VSET is the ground potential VSS. The source lines S1to Sn are kept at 4.5 V. The counter electrode VCOM is pulled up from the potential VCOML to the ground potential VSS by discharging the electric charge of “1 [V]×C” to the ground line. Further, because of the variation in the counter electrode VCOM, the source lines S1to Sn are to boost up by 1 [V]. However, the potential of the source lines S1to Sn is kept at +4.5 [V] by discharging the electric charge of “1 [V]×C” to the ground line. As a result, no electric charge is consumed also in the period T2.

In a period T3, the electric charge reuse period designating signal is asserted, and the source lines S1to Sn and the counter electrode VCOM are short-circuited. With this, the potential of the source lines31to Sn and the counter electrode VCOM becomes +2.25 [V]. When the source lines S1to Sn and the counter electrode VCOM are short-circuited, the electric charges are only cancelled but not supplied additionally. Thus, no electric charge is consumed in the period T3, and there is no consumption of the power.

In a period T4, the source lines S1to Sn are driven from +2.25 [V] to +0.5 V, and the counter electrode VCOM is driven from +2.25 [V] to the potential VCOMH (=+4.0 [V]). At this time, the potential of the source lines S1to Sn also follows to boost up because the counter electrode VCOM is pulled up. However, the electric charges are only released from the source lines S1to Sn to the ground line, so that no electric charge is consumed in the source lines S1to Sn. Thus, there is no consumption of the power.

In the meantime, the power is consumed in driving of the counter electrode VCOM. It should be noted that a larger amount of electric charge than that of a potential difference to be driven originally is consumed when driving the counter electrode VCOM, since the potential of the source lines S1to Sn is lowered. The counter electrode VCOM is pulled up by a potential difference of +1.75 [V]. However, the potential of the source lines S1to Sn is pulled down by 1.75 V, so that it is necessary to supply electric charges of “3.5 [V]×C” to the counter electrode VCOM as a result. The circuit for generating the potential VCOMH is driven by the double boost-up power supply, so that the electric charge of “7.0 [V]×C” is required for driving the counter electrode VCOM, when converting it on the basis of the power supply voltage VCI.

As a result of the above, the total amount of electric charge consumed in the periods T1to T4for providing black display is “7.0 [V]×C”. For displays of other colors, the electric charge consumption can be calculated similarly.FIG. 4shows the results thereof.

(2) A Case where Counter Electrode VCOM is Pulled Down from Potential VCOMH to Potential VCOML

First, calculations of the electric charge consumption for providing black display will be described.

The period T1is considered as a period where the liquid crystal display device is in the initial state. In the period T1, the counter electrode VCOM is kept to the potential VCOMH (=4.0 [V]). Further, the source lines S1to Sn are driven to 0.5 V. In the period T1, there is no transfer of the electric charges, so that no electric charge is consumed.

In the period T2, the electric charge reuse period designating signal is asserted, and the source lines S1to Sn and the counter electrode VCOM are short-circuited. With this, the potential of the source lines S1to Sn and the counter electrode VCOM becomes +2.25 [V]. When the source lines S1to Sn and the counter electrode VCOM are short-circuited, the electric charges are only cancelled but not supplied additionally. Thus, no power is consumed in the period T2.

In the period T3, the source lines S1to Sn are driven from +2.25 [V] to +4.5 [V], and the counter electrode VCOM is driven from +2.25 [V] to the potential VCOML (=−1.0 [V]). The source lines S1to Sn originally need to be pulled up by 2.25 V. However, the counter electrode VCOM is pulled down by 3.25V, so that it is necessary to supply the electric charge of “5.5 [V]×C” to the source lines S1to Sn as a result. In addition, the source lines S1to Sn are driven by a double boost-up power supply. Thus, the electric charge of “11.0 [V]×C” is required for driving the source lines S1to Sn, when converting it on the basis of the power supply voltage VCI.

Furthermore, the counter electrode VCOM originally needs to be pulled down by 3.25 V when driving the counter electrode VCOM. However, the electric charge of more than that is required for driving the counter electrode VCOM. That is, it is necessary to supply the electric charge of “5.5 [V]×C” to the counter electrode VCOM for driving the counter electrode VCOM to the target potential VCOML (=−1.0 [V]), since the source lines S1to Sn are pulled up by 2.25 V.

Therefore, the total amount of electric charge consumed in the periods T1to T3is “16.5 [V]×C”. For displays of other colors, the electric charge consumption can be calculated similarly.FIG. 5shows the results thereof.

In the above-described procedure executed for pulling down the counter electrode VCOM from the potential VCOMH to the potential VCOML, the power is consumed uneconomically. As will be described in detail hereinafter, it is possible to reduce the power consumption by pulling down the counter electrode VCOM to the potential VCOML by employing an optimum procedure.

According to an aspect of the present invention, a driving method of a liquid crystal display panel having a source line and a counter electrode includes:

(a) driving the counter electrode to a first potential being a high level of an amplitude of a potential of the counter electrode;

(b) setting the counter electrode and the source line to a second potential by short-circuiting the counter electrode and the source line to a power supply interconnection having the second potential lower than the first potential after the driving;

(c) connecting the counter electrode to a ground interconnection having a ground potential while the source line is kept to be short-circuited to the power supply interconnection after the setting;

(d) driving the counter electrode to a third potential being a low level of an amplitude of a potential of the counter electrode after the connecting; and

(e) driving the source line to a potential corresponding to an image data after the connecting.

The (d) driving and the (e) driving may be executed at a same time. Or, the (e) driving is executed after the (d) driving.

In this aspect of the present invention, the following phenomena are effectively used: (1) electric power is not consumed even when a counter electrode and a source line are short-circuited; (2) electric charge is not newly consumed when a counter electrode output is connected to ground terminal and the charge existing in the counter electrode is supplied to the ground terminal. As a result, it is possible to pull down the counter electrode from a first potential which is the high level potential of the amplitude of the counter electrode to a third potential which is the low level potential of the amplitude of the counter electrode by consuming less electric power.

The liquid display panel driving method of this aspect of the present invention is especially effective when the driving of the source line driven to a potential corresponding to the image data is performed by a driving circuit which is driven by a boost-up power source voltage generated by boosting-up a first power source voltage supplied by the first power source or a second power source voltage which is generated by regulator circuit from the boost-up power source voltage.

According to another aspect of the present invention, a liquid crystal display device includes:

a liquid crystal display panel having a source line and a counter electrode; and

an LCD driver which comprises a source driver circuit having a source output connected to the source line, VCOM circuit having a VCOM output connected to the counter electrode and a power supply interconnection having a predetermined potential. The source driver circuit includes: a driving section configured to drive the source line; and a first switch connected between the source output and the power supply interconnection. The VCOM circuit includes: a first driving section configured to drive the counter electrode to a first potential being a high level of an amplitude of a potential of the counter electrode; a second switch connected between the counter electrode and the power supply interconnection; a third switch connected between the counter electrode and a ground interconnection; and a second driving section configured to drive the counter electrode to a third potential being a low level of an amplitude of a potential of the counter electrode. The predetermined potential of the power supply interconnection is lower than the first potential and higher than the ground interconnection.

A liquid crystal display apparatus having such a configuration is preferable for performing the aforementioned driving method of a liquid crystal display panel. Here, by such a representation “a component C connected between a component A and component B” includes a case in which another component exists between the component C and components A or B.

According to a preferable embodiment, the source driver circuit further includes: a common interconnection connected to the source output via the first switch; and a fourth switch connected between the common interconnection and the power supply interconnection. The second switch is connected between the VCOM output of the VCOM circuit and the common interconnection.

In this case, it is also preferable that the source driver circuit further includes: a fifth switch connected to the VCOM output in parallel with the second switch and connected between the VCOM output and the power supply interconnection.

According to an embodiment of the present invention, it is possible to effectively reducing the power required for pulling down the counter electrode from the positive potential to the negative potential.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a semiconductor storage device and a memory cell test method according to embodiments of the present invention will be described with reference to the attached drawings.

First Embodiment

[Structure of Liquid Crystal Display Device]

FIG. 6Ais a block diagram showing a structure of a liquid crystal display device1according to a first embodiment of the present invention. The liquid crystal display device of a first embodiment includes an LCD panel2and an LCD driver3. The LCD driver3includes a power supply circuit11, a source driver circuit12, a gate driver circuit13, a VCOM circuit14, and a timing control circuit15.

The power supply circuit11generates supply voltages with voltage levels corresponding to each circuit from a power supply voltage VCI that is supplied form a VCI power supply interconnection30. The VCI power supply interconnection30is an interconnection for supplying the power supply voltage VCI to the power supply circuit11from a VCI power supply (not shown). The VCI power supply may be integrated to the LCD driver or may be provided externally.

More specifically, the power supply circuit11supplies a power supply voltage VS to the source driver circuit12, and supplies power supply voltages VGH, VGL to the gate driver circuit13. Note here that the power supply voltage VGH is a power supply voltage used for pulling up gate lines Gj and the power supply voltage VGL is a power supply voltage used for pulling down the gate lines Gj. Further, the power supply circuit11supplies power supply voltages VCOMH, VCOML to the VCOM circuit14, and supplies a double boost-up power supply VDD2to the timing control circuit15. The power supply voltage VCOMH is a power supply voltage used for pulling up a counter voltage VCOM, and the power supply voltage VCOML is a power supply voltage used for pulling down the counter voltage VCOM. The double boost-up power supply VDD2is a power supply voltage obtained by performing double boost-up of the power supply voltage VCI.

FIG. 6Bis a block diagram showing a structure of a part of the power supply circuit11, which generates the power supply voltage VS, the power supply voltages VCOMH, VCOML, and the double boost-up power supply VDD2. The power supply circuit11includes a double boost-up circuit31, a VS regulator circuit32, a VCOMH regulator circuit33, a negative voltage generation circuit34, and a VCOML regulator circuit35. The double boost-up circuit31performs double boost-up of the power supply voltage VCI that is supplied from the VCI power supply interconnection30so as to generate the double boost-up power supply VDD2. Upon receiving a supply of the double boost-up power supply VDD2, the VS regulator32generates the power supply voltage VS that is slightly lower than the double boost-up power supply VDD2, and supplies the generated power supply voltage VS to the source driver circuit12. Upon receiving a supply of the double boost-up power supply VDD2, the VCOMH regulator33generates the power supply voltage VCOMH that is slightly lower than the double boost-up power supply VDD2, and supplies the generated power supply voltage VCOMH to the VCOM circuit14. The negative voltage generation circuit34generates a negative voltage—VCI from the power supply voltage VCI, and supplies the power supply voltage −VCI to the VCOML regulator circuit35. The VCOML regulator circuit35generates the power supply voltage VCOML in a range of the power supply voltage VCI to the negative voltage −VCI, and supplies the generated power supply voltage VCOML to the VCOM circuit14. Typically, the power supply voltage VCI is 2.8 V (that is, the double boost-up power supply voltage VDD2is 5.6 V), the power supply voltage VS is 5.0 V, the power supply voltage VCOMH is 4.0 V, and the power supply voltage VCOML is −1.0 V. It is possible for the double boost-up power supply VDD2to be supplied to the source driver circuit12instead of the power supply voltage VS so as to operate the source driver12by the double boost-up power supply VDD2.

When the electric charges are consumed in circuits to which the power supply voltage VS and the power supply voltage VCOMH are supplied, it is to be noted that the electric charges of twice as much are consumed in the VCI power supply interconnection30. This means that it is highly effective to reduce the electric charges consumed in the circuits to which the power supply voltage VS and the power supply voltage VCOMH are supplied, in order to reduce power consumption.

The source driver circuit12has source lines S1to Sn of the LCD panel2connected to its output, and drives the source lines S1to Sn. An output of the source driver circuit12may be referred to as a “source output” hereinafter.FIG. 6Cis a block diagram showing an example of a structure of the source driver circuit12. The source driver circuit12includes latch circuits21-1to21-n, latch circuits22-1to22-n, decoder circuits23-1to23-n, gray-scale selection circuits24-1to24-n, output amplifiers25-1to25-n, output control circuits26-1to26-n, and a VCI power supply interconnection27.

Each of the latch circuits21-1to21-nsuccessively latches N-bit image data transmitted successively to the source driver circuit12, in response to strobe signals STRB1-1to STRB1-n. More specifically, the strobe signals STRB1-1to STRB1-nare asserted by synchronizing with the image data transferred successively to the source driver circuit12. Each latch circuit21-jlatches the image data, when a corresponding strobe signal STRB1-jis asserted. The latch circuits21-1to21-nlatch the image data for pixels of one horizontal line all together. More specifically, the latch circuits21-1to21-nlatch the image data of the pixels corresponding to the gate lines Gj+1 that are selected in a next horizontal scanning period.

Each of the latch circuits22-1to22-nlatches the image data latched by the latch circuits21-1to21-nsimultaneously or by shifting the timing slightly for dispersing peak currents, in response to a common strobe signal SRTB2. The latch circuits22-1to22-nlatch the image data of the pixels corresponding to the gate lines Gj selected in a current horizontal scanning period.

The decoder circuits23-1to23-ndecode the image data received from the latch circuits22-1to22-n, and outputs2″-numbers of selection signals. Further, depending on a circuit structure, a level shifter circuit may be inserted between the decoder circuits23-1to23-nand the latch circuits22-1to22-n.

The gray-scale selection circuits24-1to24-nselects one gray-scale voltage VG from gray-scale voltages VG1to VGp, in response to the selection signals received from the decoder circuits23-1to23-n.

Output amplifiers25-1to25-noutput a driving voltage corresponding to the gray-scale voltage VG selected by the gray-scale selection circuits24-1to24-n. The source lines S1to Sn are driven to a predetermined voltage level by the output amplifiers25-1to25-n.

The output control circuits26-1to26-nare circuits for switching connecting relations of the output terminals (that is, the source lines S1to Sn) of the source driver circuit12, the output amplifiers25-1to25-n, and the VCI power supply interconnection27. Note here that the VCI power supply interconnection27is an interconnection through which the power supply voltage VCI is supplied from the VCI power supply (not shown), and it is electrically connected to the VCI power supply interconnection30that is connected to the power supply circuit11. The potential of the VCI power supply interconnection27is kept to the potential VCI by the VCI power supply.

Each of the output control circuits26-1to26-nincludes a switch SW1and a switch SW2. The switches SW1are connected between the source outputs of the source driver circuit12and the VCI power supply interconnection27. The switches SW2are connected between the source outputs and the output amplifiers25-1to25-n. The switches SW1are turned on/off in response to a control signal S-SW1supplied from the timing control circuit15, and the switches SW2are turned on/off in response to a control signal S-SW2. When the switches SW1are turned on, the source lines S1to Sn are electrically connected to the VCI power supply interconnection27, and the source lines S1to Sn are driven to the potential VCI. In the meantime, when the switches SW2are turned on, the source lines S1to Sn are electrically connected to the output amplifiers25-1to25-n, and the source lines S1to Sn are driven thereby to a potential corresponding to the image data.

Note here that the decoder circuits23-1to23-n, the gray-scale selection circuits24-1to24-n, the output amplifiers25-1to25-n, and the output control circuits26-1to26-nare operated by receiving the supply of the power supply voltage VS generated from the double boost-up power supply voltage VDD2. When the electric charges are consumed in those circuits, electric charges of twice as much are consumed in the VCI power supply interconnection30.

Further, note here that the configuration of the source driver circuit12can be modified variously. For example, the output amplifiers25-1to25-nmay be omitted from the source driver circuit12.

Referring back toFIG. 6A, the gate driver circuit13is a circuit for driving the gate lines G1to Gm by receiving the supply of power supply voltages VGH and VGL. The gate driver circuit13scans and drives the gate lines G1to Gm successively.

The VCOM circuit14has the counter electrode VCOM connected to its output, and functions to drive the counter electrode VCOM. The output of the VCOM circuit14may be referred to as a VCOM output hereinafter. The VCOM circuit14includes a VCOMH output amplifier41, a VCOML output amplifier42, a VCI power supply interconnection43, a ground interconnection44, and switches SW6to SW9. The power supply voltage VCOMH is supplied to the VCOMH output amplifier41, and it is used for pulling up the counter electrode VCOM to the potential VCOMH. In the meantime, the power supply voltage VCOML is supplied to the VCOML output amplifier42, and it is used for pulling down the counter electrode VCOM to the potential VCOML. The VCI power supply interconnection43is an interconnection connected to the VCI power supply, and a potential of the VCI power supply interconnection43is kept to the potential VCI. The VIC power supply interconnection43is electrically connected to the VCI power supply interconnections27and30described above. The ground interconnection44is an interconnection kept to the ground potential VSS. The switch SW6is connected between the VCOM output of the VCOM circuit14and the VCOMH output amplifier41, and it is turned on/off in response to a control signal S-SW6that is supplied from the timing control circuit15. The switch SW7is connected between the VCOM output and the VCOML output amplifier42, and it is turned on/off in response to a control signal S-SW7that is supplied from the timing control circuit15. The switch SW8is connected between the VCOM output and the VCI power supply interconnection43, and it is turned on/off in response to a control signal S-SW8that is supplied from the timing control circuit15. The switch SW9is connected between the VCOM output and the ground potential VSS44, and it is turned on/off in response to a control signal S-SW9that is supplied from the timing control circuit15.

The VCOMH output amplifier41operates by receiving the power supply voltage VCOMH generated from the double boost-up power supply voltage VDD2, and it is noted that when the electric charges are consumed in the VCOM output amplifier41, the electric charges of twice as much are consumed in the VCI power supply interconnection30.

The timing control circuit15controls timings of the LCD driver3. More specifically, the timing control circuit15supplies the control signals S-SW1, S-SW2to the source driver circuit12, and supplies the control signals S-SW6to S-SW9to the VCOM circuit14.

A most distinctive point in the operations of the liquid crystal display device1according to a present embodiment is the procedure for changing the polarity of the driving voltage from negative to positive, i.e., the procedure for pulling down the counter electrode VCOM from the potential VCOMH to the negative potential VCOML. In a present embodiment, the procedure for pulling down the counter electrode VCOM to the negative potential VCOML is optimized so as to achieve reduction of the power consumption.

More specifically, as shown inFIG. 7A, in a present embodiment, the source lines S1to Sn and the counter electrode VCOM are short-circuited to the VCI power supply to be the potential VCI and, thereafter, the counter electrode VCOM is connected to a ground interconnection to pull it down to the ground potential while keeping the source lines S1to Sn to the potential VCI. Further, the source lines S1to Sn are driven to a predetermined potential. The operation for short-circuiting the source lines S1to Sn and the counter electrode VCOM to the VCI power supply can be executed without consuming the electric charge. Further, for an operation executed to connect the counter electrode VCOM to the ground interconnection, the electric charge is consumed in the source lines S1to Sn but not consumed in the counter electrode VCOM. After those operations, the counter electrode VCOM is pulled down to the negative potential VCOML. With this, the counter electrode VCOM can be pulled down from the potential VCOMH to the negative potential VCOML, while reducing the power consumption.

With a reference technique shown inFIG. 2, the counter electrode VCOM and the source lines S1to Sn are driven simultaneously. Thus, the power is consumed uneconomically in both the counter electrode VCOM and the source lines S1to Sn. That is, there is required an extra power for canceling the influence that is generated because the source lines S1to Sn are pulled up when driving the counter electrode VCOM, and there is required an extra power for canceling the influence that is generated because the counter electrode VCOM is pulled down when driving the source lines S1to Sn. With the operation of a present embodiment, however, when driving the source lines S1to Sn, there is required only a half the power since the influence by the pull-down of the counter electrode VCOM is cancelled while being short-circuited to the VCI power supply, without using the double boost-up power supply. Further, for driving the source lines S1to Sn to the target potential thereafter, the power for driving the source lines S1to Sn can be reduced since the change in the potential is small. The source lines S1to Sn are driven by using the power supply voltage VS generated from the double boost-up power supply voltage VDD2, so that reduction of the electric charges required for driving the source lines S1to Sn is effective for reducing the power consumption.

In a strict sense, there is such a disadvantage in the operations of this embodiment that it requires an additional power to keep the source lines S1to Sn to the potential VCI, when pulling down the counter electrode VCOM to the ground potential VSS. However, this power is smaller compared to the increase in the power required for simultaneously driving the counter electrode VCOM and the source lines S1to Sn.

Hereinafter, the operations of this embodiment will be described in details.

(1) A Case where Counter Electrode VCOM is Pulled Down from Potential VCOMH to Potential VCOML

FIG. 7Ais a timing chart for describing an operation of the liquid crystal display device1when the polarity of the driving voltage is changed from negative to positive, i.e., when the counter electrode VCOM is pulled down from the potential VCOMH to the potential VCOML.FIG. 8Ais a flowchart showing an operation of the liquid crystal display device1in each period. Explanations hereinafter will be provided assuming that the liquid crystal display device1is in an initial state in the period T1.

In the period T1, the counter electrode VCOM is pulled up to the potential VCOMH, and the source lines S1to Sn are driven to the potential corresponding to the image data. For achieving black display, the source lines S1to Sn are driven to a positive potential that is lower than the VCOMH and deviated from the potential VCOMH. In the meantime, for achieving white display, the source lines S1to Sn are driven to a potential slightly higher than the potential VCOMH. In addition, the switches SW1, SW7to SW9are turned off, while the switches SW2and SW6are turned on. That is, the control signals S-SW1, S-SW7to S-SW9are negated, while the control signals S-SW2and S-SW6are asserted.

From the period T2, the operations for changing the polarity of the driving voltage from negative to positive are started. In the period T2, the source lines S1to Sn and the counter electrode VCOM are short-circuited to the VCI power supply. More specifically, the control signals S-SW1, S-SW8are asserted and the switches SW1, SW8are turned on, while the switches SW2, SW6, SW7, and SW9are turned off. With this, the source lines S1to Sn are connected to the VCI power supply interconnection27, and the counter electrode VCOM is connected to the VCI power supply interconnection43. Thereby, the source lines S1to Sn and the counter electrode VCOM are driven to the potential VCI. Note that the VCI power supply interconnection27and the VCI power supply interconnection43are both connected to the VCI power supply interconnection30electrically. With this operation, the electric charges of the source lines S1to Sn and the counter electrode VCOM are simply redistributed through the VCI power supply interconnections27and43, so that no power is consumed.

In the period T3following the period T2, the counter electrode VCOM is pulled down to the ground potential VSS, while the source lines S1to Sn are being connected to the VCI power supply. More specifically, the control signals S-SW1, S-SW9are asserted, and the switches SW1, SW9are turned on. The switches SW2, SW6, SW7, and SW8are turned off. With this operation, the counter electrode VCOM is short-circuited to the ground interconnection44, while the source lines S1to Sn are being connected to the VCI power supply interconnection27. This operation requires no electric charge for pulling down the counter electrode VCOM to the ground potential VSS, even though electric charge is consumed for keeping the source lines S1to Sn to the potential VCI.

In the period T4following the period T3, the counter electrode VCOM is pulled down to the potential VCOML, while the source lines S1to Sn are kept to a high-impedance state. More specifically, the control signal S-SW7is asserted and the switch SW7is turned on, while the switches SW1, SW2, SW6, SW8, and SW9are turned off. With this, the counter electrode VCOM is connected to the output of the VCOML output amplifier42, and the counter electrode VCOM is pulled down to the potential VCOML. The potential of the source lines S1to Sn is lowered because of the pull-down of the counter electrode VCOM. However, the change in the potential of the counter electrode VCOM is small, so that an amount of the change in the potential of the source lines S1to Sn is also small. Thus, no electric charge is consumed in the period T4.

In the period T5following the period T4, the source lines S1to Sn are driven to the potential in accordance with the image data (different from that of the period T1), while the counter electrode VCOM is kept to the potential VCOML. More specifically, the control signals S-SW2, S-SW7are asserted and the switches SW2, SW7are turned on, while the switches SW1, SW6, SW8, and SW9are turned off. With this, the source lines S1to Sn are connected to the output amplifiers25-1to25-n, and driven to the potential corresponding to the image data.

FIGS. 9 to 13are illustrations for respectively showing examples of the state of the electric charges in the periods T1to T5in details. In the explanations usingFIGS. 9 to 13, it is assumed that the potential VCOML is −1.0 (VI, the potential VCOMH is +4.0 [V], and the potential VCT is 2.8 [V]. A possible range of the source line potential is assumed to be +0.5−4.5 [V]. Further, the factor that is most influential to the electric charges consumed when driving the counter electrode VCOM and the source lines S1to Sn is the parasitic capacitance Csv between the counter electrode VCOM and the source lines S1to Sn. Thus, the parasitic capacitance Cgv between the common electrode VCOM and the gate lines G1to Gm, the liquid crystal pixel capacitance CI, and the storage capacitance Cst are neglected, since influences of those are insignificant. The parasitic capacitance Csv between each source line Sj and the counter electrode VCOM is assumed to be C [F]. Further, the LCD panel2is assumed to be a normally-white panel, and it is assumed that black display is performed on the LCD panel2. That is, it is assumed that the source line Sj is driven to 0.5 V when the counter electrode VCOM is pulled up to the potential VCOMH (−4.0 [V]), and that the source line Sj is driven to 4.5 V when the counter electrode VCOM is pulled down to the potential VCOML (=−1.0 [V]).

In the period T1being the initial state, as shown inFIG. 9, the counter electrode VCOM is in the potential VCOMH (+4.0 [V]), and the potential of the source line Sj is 0.5 V. As a result, the electric charge of “3.5 [V]×C” is to be accumulated to the parasitic capacitance between the source line Sj and the counter electrode VCOM.

As shown inFIG. 10, in the period T2, the counter electrode VCOM and the source lines S1to Sn are short-circuited to the VCI power supply. In this operation, the electric charges accumulated to the parasitic capacitance are simply transferred from the common electrode VCOM to the source lines S1to Sn, so that no power is consumed in the VCI power supply. In the period T2, there is no electric charge accumulated in the parasitic capacitance between the source lines S1to Sn and the counter electrode VCOM.

As shown inFIG. 11, in the period T3, the counter electrode VCOM is pulled down to the ground potential VSS, while the source lines S1to Sn are connected to the VCI power supply. At this time, the VCI power supply supplies the electric charge corresponding to the change in the potential of the counter electrode (that is, electric charges of “2.8 [V]×C”) to the source lines S1to Sn in order to keep the source lines S1to Sn to the potential VCI. That is, the electric charge consumed in the VCI power supply is “2.8 [V]×C”. In the meantime, the counter electrode VCOM can be pulled down to the ground potential VSS by simply having the electric charge flown out to the ground interconnection44, so that no electric charge is consumed in the VCI power supply. In the period T3, the electric charge accumulated in the parasitic capacitance between the source lines S1to Sn and the counter electrode VCOM is “2.8 [V]×C”. Thus, the electric charge of “2.8 [V]×C” is to be consumed in the period T3.

As shown inFIG. 12, in the period T4, the source lines S1to Sn are driven to a high-impedance state. Further, the counter electrode VCOM is pulled down to the potential VCOML (=−1.0 [V]). In accordance with the pull-down of the counter electrode VCOM, the source lines S1to Sn come to exhibit a same potential change as that of the counter electrode VCOM. Thereby, the source lines S1to Sn are pulled down to 1.8 [V]. The electric charges accumulated in the parasitic capacitance between the source lines S1to Sn and the counter electrode VCOM are not transferred when pulling down the counter electrode VCOM to the potential VCOML. Thus, no electric charge is consumed in the VCI power supply.

As shown inFIG. 13, in the period T5, the source lines S1to Sn are pulled up to 4.5 V, while the counter electrode VCOM is kept to the potential VCOML (=−1.0 [V]). At this time, the electric charge of “2.7 [V]×C” is supplied from the VCI power supply to the source lines S1to Sn in order to pull up the source lines S1to Sn to 4.5 V. The source lines S1to Sn are driven by the power supply voltage VS generated from the double boost-up power supply VDD2, so that the electric charge consumed in the VCI power supply is the electric charge of “5.4 [V]×C” that is twice as much. In addition, an electric charge corresponding to the change in the potential of the source lines S1to Sn (that is, electric charge of “2.7 [V]×C”) is consumed in the VCOML output amplifier42in order to cancel the influence generated by the pull-up of the source lines S1to Sn and to keep the counter electrode VCOM to −1.0 [V]. As a result, the electric charge consumed in the VCI power supply in the period T5is “8.1 [V]×C”.

Through the whole periods T1to T5, the electric charge of “10.9 [V]×C” in total is consumed in the VCI power supply for providing black display. For displays of other colors, the electric charge consumption can also be calculated similarly.

FIG. 14is a table showing the electric charges consumed for each display color when executing the driving method shown inFIGS. 7A and 8A. As described above, the electric charge of “10.9 [V]×C” in total is consumed in the VCI power supply for providing black display. Further, the electric charge of “4.1 [V]×C” in total is consumed in the VCI power supply for providing white display, and the electric charge of “4.9 [V]×C” in total is consumed in the VCI power supply for providing gray display. The advantages of the driving method shown inFIGS. 7A and 8Acan be understood by comparingFIG. 14withFIG. 5which shows the electric charges consumed in a driving method according to the aforementioned reference technique. For performing black display in particular, it is possible with the driving method of this embodiment to reduce the electric charge consumption to “10.9 [V]×C”, while the electric charge of “16.5 [V]×C” is consumed with the reference technique. The electric charge consumption can be reduced for other display colors as well.FIG. 38shows a comparison table regarding the electric charge consumption and a consumption current. The consumption current is calculated assuming that capacitance C between the source lines S1to Sn and the counter electrode VCOM is 100 pF, the number of gate lines G1to Gm is 160, and the frame frequency is 60 Hz. For example, when the electric charge consumption is “10 [V]×C”, it can be calculated as follows.
I=10000 pf×10V×160×60=0.96 mA

As shown inFIG. 38, the driving method of this embodiment can reduce the electric charge consumption by about 34% for a case of providing black display, and about 9% for the case of providing white display.

In a first embodiment, pull-down of the counter electrode VCOM from the ground potential VSS to the potential VCOML and drive of the source lines S1to Sn to the potential in response to the image data may be performed simultaneously.FIG. 7Bis a timing chart for describing the operations of the liquid crystal display device1executed for such case, andFIG. 5Bis a flowchart showing the operation of the liquid crystal display device1in each period ofFIG. 7B.

The operations of the periods T1to T3shown inFIGS. 7B and 8Bare the same as the operations shown inFIGS. 7A and 8A.

That is, in the period T1where the liquid crystal display device1is in the initial state, the counter electrode VCOM is pulled up to the potential VCOMH, while the source lines S1to Sn are driven to the potential corresponding to the image data. In addition, the switches SW1, SW7to SW9are turned off, while the switches SW2and SW6are turned on. That is, the control signals S-SW1, S-SW7to S-SW9are negated, and the control signals S-SW2, S-SW6are asserted. The state of the electric charges in the period T1of the operations shown inFIGS. 7B and 8Bis the same as the state of the electric charges in the period T1of the operations ofFIGS. 7A and 8Ashown inFIG. 9.

From the period T2, the operations for changing the polarity of the driving voltage from negative to positive are started. In the period T2, the source lines S1to Sn and the counter electrode VCOM are short-circuited to the VCI power supply. More specifically, the control signals S-SW1, S-SW8are asserted and the switches SW1, SW8are turned on, while the switches SW2, SW6, SW7, and SW9are turned off. With this, the source lines S1to Sn are connected to the VCI power supply interconnection27, and the counter electrode VCOM is connected to the VCI power supply interconnection43. Thereby, the source lines S1to Sn and the counter electrode VCOM are driven to the potential VCI. Note that the VCI power supply interconnection27and the VCI power supply interconnection43are electrically connected to each other. With this operation, the electric charges of the source lines S1to Sn and the counter electrode VCOM are simply redistributed through the VCI power supply interconnections27and43, so that no power is consumed. The state of the electric charges in the period T2of the operations shown inFIGS. 7B and 8Bis the same as the state of the electric charges in the period T2of the operations ofFIGS. 7A and 8Ashown inFIG. 10.

In the period T3following the period T2, the counter electrode VCOM is pulled down to the ground potential VSS, while the source lines S1to Sn are being connected to the VCI power supply. More specifically, the control signals S-SW1, S-SW9are asserted and the switches SW1, SW9are turned on, while the switches SW2, SW6, SW7, and SW8are turned off. With this operation, the counter electrode VCOM is, short-circuited to the ground interconnection44, while the source lines S1to Sn are being connected to the VCI power supply interconnection27. This operation requires no electric charge for pulling down the counter electrode VCOM to the ground potential VSS, even though electric charge is consumed for keeping the source lines S1to Sn to the potential VCI. The state of the electric charges in the period T3of the operations shown inFIGS. 7B and 8Bis the same as the state of the electric charges in the period T3of the operations ofFIGS. 7A and 8Ashown inFIG. 11. When performing black display under the same conditions shown inFIGS. 9 to 13(the potential VCI is 2.8 V, the potential to which the source lines S1to Sn are to be driven is 4.5 V, and the potential VCOML is −1.0 V), the electric charge of “2.8 [V]×C” is consumed in the period T3for keeping the source lines S1to Sn to the potential VCI.

In the period T4following the period T3, the source lines S1to Sn are driven to the potential corresponding to the image data, and the counter electrode VCOM is pulled down from the ground potential VSS to the potential VCOML. More specifically, the control signals S-SW2, S-SW7are asserted and the switches SW2, SW7are turned on, while the switches SW1, SW6, SW8, and SW9are turned off. With this, the source lines S1to Sn are connected to the output amplifiers25-1to25-n, while the counter electrode VCOM is connected to the output of the VCOML output amplifier42. At this time, in order to drive the source lines S1to Sn to the potential corresponding to the image data, it is necessary to supply, to the source lines, the electric charges required for canceling the influence generated by the pull-down of the counter electrode VCOM from the ground potential VSS to the potential VCOML and driving the source lines S1to Sn from the ground potential VCI to the potential corresponding to the image data. Thus, the electric charge of “12.7 [V]×C” is consumed for driving the source lines S1to Sn, when performing black display under the same conditions as those shown inFIG. 9toFIG. 13. More specifically, the electric charge of “1.0 V×C” is consumed for canceling the influence generated when pulling down the counter electrode VCOM from the ground potential VSS to the potential VCOML, and the electric charge of “1.7 [V]×C” is consumed for pulling up the source lines S1to Sn from 2.8 V to 4.5 V. The source lines S1to Sn are driven by the power supply voltage VS generated from the double boost-up power supply VDD2, so that the electric charge consumed in the VCI power supply is the electric charge of “5.4 [V]×C” that is twice as much. In the meantime, the electric charge corresponding to the sum of the change in the potential of the source lines S1to Sn and the change in the potential of the counter electrode VCOM (that is, electric charge of “2.7 [V]×C”) is consumed in the VCOML output amplifier42in order to cancel the influence generated by the pull-up of the source lines S1to Sn and to drive the counter electrode VCOM to −1.0 [V]. As a result, the electric charge consumed in the VCI power supply in the period T4is “8.1 [V]×C”.

As a result, the electric charge of “10.9 [V]×C” in total is consumed in the VCI power supply when performing black display by the operations ofFIGS. 7B and 8B, similarly to the operations ofFIGS. 7A and 8A.

For such operations, when driving the source lines S1to Sn, there is required only a half the power since the influence generated by the pull-down of the counter electrode VCOM is cancelled while being short-circuited to the VCI power supply, without using the double boost-up power supply. Further, for driving the source lines S1to Sn to the target potential thereafter, the power required for driving the source lines S1to Sn can be reduced since the change in the potential is small.

(2) Case where Counter Electrode VCOM is Pulled Up from Potential VCOML to Potential VCOMH

FIG. 15is a timing chart for describing the operation of the liquid crystal display device1when changing the polarity of the driving voltage from positive to negative, i.e., when pulling up the counter electrode VCOM from the potential VCOML to the potential VCOMH.FIG. 16is a flowchart showing the operation of the liquid crystal display device1in each period ofFIG. 15. As will be described hereinafter, the counter electrode VCOM is pulled up from the potential VCONL to the potential VCOMH in the liquid crystal display device1of a present embodiment by a driving method different from that of a liquid crystal device of the aforementioned reference technique, because of the difference between the structures of those devices. However, with the driving method explained below, there is no increase generated in the power consumption at least. Explanations hereinafter will be provided assuming that the liquid crystal display device1is in the initial state in the period T1.

In the period T1, the counter electrode VCOM is pulled down to the potential VCOML, and the source lines S1to Sn are driven to the potential corresponding to the image data. For achieving black display, the source lines S1to Sn are driven to a positive potential that is higher than the VCOML and deviated from the potential VCOML. In the meantime, for achieving white display, the source lines S1to Sn are driven to a potential slightly higher than the potential VCOML. In addition, the switches SW1, SW6, SW8, and SW9are turned off, while the switches SW2and SW7are turned on. That is, the control signals S-SW1, S-SW6, S-SW8, and S-SW9are negated, while the control signals S-SW2and S-SW7are asserted.

From the period T2, the operations for changing the polarity of the driving voltage from positive to negative are started. In the period T2, the source lines S1to Sn and the counter electrode VCOM are short-circuited to the VCI power supply. More specifically, the control signals S-SW1, S-SW8are asserted and the switches SW1, SW8are turned on, while the switches SW2, SW6, SW7, and SW9are turned off. With this, the source lines S1to Sn are connected to the VCI power supply interconnection27, and the counter electrode VCOM is connected to the VCI power supply interconnection43. Thereby, the source lines S1to Sn and the counter electrode VCOM are driven to the potential VCI. Note that the VCI power supply interconnection27and the VCI power supply interconnection43are electrically connected to each other. With this operation, the electric charges of the source lines S1to Sn and the counter electrode VCOM are simply redistributed through the VCI power supply interconnections27and43, so that no power is consumed.

In the period T3following the period T2, the counter electrode VCOM is pulled up to the potential VCOMH, while the source lines S1to Sn are in the high-impedance state. More specifically, the control signal S-SW6is asserted and the switch SW6is turned on, while the switches SW1, SW2, and SW7to SW9are turned off. With this, the counter electrode VCOM is connected to the output of the VCOMH output amplifier41, and the counter electrode VCOM is pulled up to the potential VCOMH. The potential of the source lines S1to Sn is boosted up because of the pull-up of the counter electrode VCOM. However, the change in the potential of the counter electrode VCOM is small, so that an amount of change in the potential of the source lines S1to Sn is also small. Thus, no electric charge is consumed.

In the period T4following the period T3, the source line S1to Sn are driven to the potential corresponding to the image data, while the counter electrode VCOM is kept to the potential VCOMH. More specifically, the control signals S-SW2, S-SW6are asserted and the switches SW2, SW6are turned on, while the switches SW1, and SW7to SW9are turned off. With this, the source lines S1to Sn are connected to the output amplifiers25-1to25-n, and driven to a potential corresponding to the image data.

FIGS. 17 to 20are illustrations for respectively showing examples of a state of the electric charges in the periods T1to T4in details. In the explanations usingFIGS. 17 to 20, the same conditional assumptions as those of the explanations provided withFIGS. 9 to 13are employed. That is, it is assumed that the potential VCI is −1.0 [V], the potential VCOMH is +4.0 [V], and the potential VCI is 2.8 [V]. Further, the possible range of the source line potential is assumed to be +0.5−4.5 [V]. Furthermore, the LCD panel2is assumed to be a normally-white panel, and it is assumed that black display is performed on the LCD panel2.

As shown inFIG. 17, the potential of the counter electrode VCOM is the potential VCOML (−1.0 [V]) and the potential of the source lines S1to Sn is 4.5 V in the period T1that is in the initial state. As a result, the electric charge of “5.5 [V]×C” is accumulated to the parasitic capacitance between the source lines S1to Sn and the counter electrode VCOM.

As shown inFIG. 18, the counter electrode VCOM and the source lines S1to Sn are short-circuited to the VCI power supply in the period T2. In this operation, no power is consumed in the VCI power supply since the electric charges are canceled by short-circuiting both ends of the parasitic capacitance. In the period T2, there is no electric charge accumulated in the parasitic capacitance between the source lines S1to Sn and the counter electrode VCOM.

As shown inFIG. 19, in the period T3, the source lines S1to Sn are driven to the high-impedance state. Further, the counter electrode VCOM is pulled up to the potential VCOMH (=+4.0 [V]). The electric charges accumulated in the parasitic capacitance between the source lines S1to Sn and the counter electrode VCOM are not transferred when pulling up the counter electrode VCOM to the potential VCOMH. Thus, no electric charge is consumed in the VCI power supply.

As shown inFIG. 20, in the period T4, the source lines S1to Sn are pulled down to 0.5 V, while the counter electrode VCOM is kept to the potential VCOMH (=+4 [V]). At this time, the source lines S1to Sn are pulled down by having the electric charges discharged from the source lines S1to Sn to the ground potential via the output amplifier25. Thus, no power is consumed for pulling down the source lines S1to Sn. In the meantime, the VCOMH output amplifier41supplies the electric charge corresponding to the change in the potential of the source lines S1to Sn (that is, the electric charge of “3.5 [V]×C”) to the counter electrode VCOM in order to cancel the influence of the pull-down of the source lines S1to Sn and to keep the counter electrode VCOM to +4.0 [V]. The VCOMH output amplifier41is driven by the power supply voltage VCOMH that is generated from the double boost-up power supply voltage VDD2, so that the electric charge consumed in the VCI power supply is “7.0 [V]×C” that is twice as much. As a result, the electric charge consumed in the VCI power supply in the period T3is “7.0 [V]×C”.

Through the whole periods T1to T4, the electric charge of “7.0 [V]×C” in total is consumed in the VCI power supply for providing black display. For displays of other colors, the electric charge consumption can be calculated similarly.

FIG. 21is a table showing the electric charges consumed for each display color when executing the driving method shown inFIGS. 15 and 16. As described above, the electric charge of “7.0 [V]×C” in total is consumed in the VCI power supply for providing black display. Further, the electric charge of “1.0 V×C” in total is consumed in the VCI power supply for providing white display, and the electric charge of “3.0 [V]×C” in total is consumed in the VCI power supply for providing gray display. It can be understood by comparingFIG. 21withFIG. 14that it is possible with the driving method ofFIGS. 15 and 16to pull up the counter electrode VCOM from the potential VCOML to the potential VCOMH without increasing the power consumption at least.

For the operation to change the polarity of the driving voltage from positive to negative, it is also possible to employ other procedures.FIG. 22is a timing chart for describing another example of the operations executed by the liquid crystal display device1when changing the polarity of the driving voltage from positive to negative (that is, when pulling up the counter electrode VCOM from the potential VCOML to the potential VCOMH), andFIG. 23is a flowchart for describing the operation of the liquid crystal display device1executed in each period. A difference between the operations ofFIGS. 22 and 23and the operations ofFIGS. 15 and 16is that the counter electrode VCOM and the source lines S1to Sn are driven simultaneously in the operations ofFIGS. 22 and 23. Detailed explanations will be provided hereinafter.

The operations in the periods T1and T2ofFIGS. 22 and 23are the same as those shown inFIGS. 15 and 16. That is, in the period T1where the liquid crystal display device1is in the initial state, the counter electrode VCOM is pulled down to the potential VCOML, while the source lines S1to Sn are driven to the potential corresponding to the image data. In addition, the switches SW1, SW6, SW8, and SW9are turned off, while the switches SW2and SW7are turned on. That is, the control signals S-SW1, S-SW6, S-SW8, S-SW9are negated, and the control signals S-SW2, S-SW7are asserted. The state of the electric charges in the period T1of the operations shown inFIGS. 22 and 23is the same as the state of the electric charges in the period T1of the operations ofFIGS. 15and16shown inFIG. 18.

From the period T2, the operations for changing the polarity of the driving voltage from positive to negative are started. In the period T2, the source lines S1to Sn and the counter electrode VCOM are short-circuited to the VCI power supply. More specifically, the control signals S-SW1, S-SW8are asserted and the switches SW1, SW8are turned on, while the switches SW2, SW6, SW7, and SW9are turned off. With this, the source lines S1to Sn are connected to the VCI power supply interconnection27, and the counter electrode VCOM is connected to the VCI power supply interconnection43. Thereby, the source lines S1to Sn and the counter electrode VCOM are driven to the potential VCI. Note that the VCI power supply interconnection27and the VCI power supply interconnection43are electrically connected to each other. With this operation, the electric charges of the source lines S1to Sn and the counter electrode VCOM are simply redistributed through the VCI power supply interconnections27and43, so that no additional electric charge is consumed. The state of the electric charges in the period T2of the operations shown inFIGS. 22 and 23is the same as the state of the electric charges in the period T2of the operations ofFIGS. 15 and 16shown inFIG. 18.

In the period T3following the period T2, the source lines S1to Sn are driven to the potential corresponding to the image data, and the counter electrode VCOM is pulled up to the potential VCOMH at the same time. More specifically, the control signals S-SW2, S-SW6are asserted and the switches SW2, SW6are turned on, while the switches SW1, SW7to SW9are turned off. With this, the source lines S1to Sn are connected to the output amplifiers25-1to25-n, while the counter electrode VCOM is connected to the output of the VCOMH output amplifier41. When it is assumed that the potential VCOML is −1.0 [V], the potential VCOMH is +4.0 [V], the potential VCI is 2.8 [V], and the possible range of the source line potential is +0.5−4.5[V], the state of the electric charges in the period T3of the operations shown inFIGS. 22 and 23is the same as the state of the electric charges in the period T4of the operations ofFIGS. 15 and 16shown inFIG. 20. In the period T3, the source lines S1to Sn are driven to 0.5 V by having the electric charges flown out from the source lines S1to Sn to the ground potential via the output amplifier25.

Thus, no electric charge is consumed for driving the source lines S1to Sn. In the meantime, the VCOMH output amplifier41supplies the electric charge of “3.5 [V]×C” to the counter electrode VCOM for pulling up the counter electrode VCOM from +2.8 [V] to +4.0 [V]. It is supposed that the counter electrode VCOM can be driven by simply supplying the electric charge required for pulling up the counter electrode by 1.2 [V] (that is, the electric charge of “1.2 [V]×C”), if there is no influence generated by the pull-down of the source lines S1to Sn. However, in order to cancel the influence generated by pulling down the source lines S1to Sn from 2.8 [V] to 0.5 [V], it is necessary to additionally supply the electric charge of “2.3 [V]×C” that corresponds to the change in the potential of the source lines S1to Sn. The VCOMH output amplifier41is driven by the power supply voltage VCOMH that is generated from the double boost-up power supply voltage VDD2, so that the electric charge consumed in the VCI power supply is “7.0 [V]×C” that is twice as much. As a result, the electric charge consumed in the VCI power supply in the period T3is “7.0 [V]×C”.

As a result, as shown inFIG. 24, the power consumed with the driving method ofFIGS. 22 and 23is the same as the power consumed with the driving method executed by the operations ofFIGS. 15 and 16, i.e., same as the power consumed with a driving method of the reference technique. At least, there is no increase in the power consumption caused by employing the driving method ofFIGS. 22 and 23.

Second Embodiment

FIG. 25is a timing chart for describing operations of the liquid crystal display device1according to a second embodiment when changing the polarity of the driving voltage from negative to positive, i.e., when pulling down the counter electrode VCOM from the potential VCOMH to the potential VCOML.FIG. 26is a flowchart showing the operation of the liquid crystal display device1in each period. In a second embodiment, the counter electrode VCOM is pulled down to the potential VCOML by a procedure different from that of a first embodiment.

More specifically, the operations regarding the periods T1to T3of a second embodiment shown inFIGS. 25 and 26are the same as the operations of a first embodiment shown inFIGS. 7A and 8A. In the period T1under the initial state, the counter electrode VCOM is pulled up to the potential VCOMH, while the source lines S1to Sn are driven to the potential corresponding to the image data. In the period T2following the period T1, the source lines S1to Sn and the counter electrode VCOM are short-circuited to the VCI power supply. As described in a first embodiment, no electric charge is consumed in the periods T1and T2. In the period T3following the period T2, the counter electrode VCOM is pulled down to the ground potential VSS, while the source lines S1to Sn are being connected to the VCI power supply. Under the same conditions shown inFIG. 9toFIG. 13, the electric charge of “2.8 [V]×C” is consumed in the period T3for keeping the source lines S1to Sn to the potential VCI.

In the meantime, the operations of the period T4and thereafter according to a second embodiment are different from those of a first embodiment. More specifically, in the period T4, the counter electrode VCOM is pulled down from the ground potential VSS to the potential VCOML, while the source lines S1to Sn are being connected to the VCI power supply. More specifically, the control signals S-SW1, S-SW7are asserted and the switches SW1, SW7are turned on, while the switches SW2, SW6, SW8, and SW9are turned off. With this, the counter electrode VCOM is connected to the output of the VCOML output amplifier42and pulled down to the potential VCOML, while the source lines S1to Sn are being connected to the VCI power supply interconnection27.

FIG. 27is a conceptual illustration showing a state of electric charges accumulated in the period T4. InFIG. 27, it is assumed that the potential VCOML is −1.0 [V], the potential VCOMH is +4.0 [V], the potential VCI is 2.8 [V], and the possible range of the source line potential is +0.5 to 4.5 [V].

In the period T4, the electric charge of “1.0 [V]×C” is consumed in the VCOML output amplifier42because the counter electrode VCOM is pulled down from the ground potential VSS to the potential VCOML. Further, due to the influence caused by the pull-down of the counter electrode VCOM from the ground potential VSS to the potential VCOML, the electric charge corresponding to the change in the potential of the counter electrode VCOM (that is, the electric charge of “1.0 [V]×C”) is supplied to the source lines S1to Sn and consumed therein, in order to keep the source lines S1to Sn to the potential VCI. Therefore, the electric charge of “2.0 V×C” in total is to be consumed in the period T4.

In the period T5following the period T4, the source line S1to Sn are driven to the potential corresponding to the image data, while the counter electrode VCOM is kept to the potential VCOML. More specifically, the control signals S-SW2, S-SW7are asserted and the switches SW2, SW7are turned on, while the switches SW1, SW6, SW8, and SW9are turned off. With this, the source lines S1to Sn are connected to the output amplifiers25-1to25-n, and driven to the potential according to the image data.

A state of the electric charges in the period T5is the same as that of the period T5of a first embodiment shown inFIG. 13. In the period T5, the electric charge of “1.7 [V]×C” is supplied from the VCI power supply to the source lines S1to Sn in order to pull up the source lines S1to Sn from 2.8 V to 4.5 V. The source lines S1to Sn are driven by the power supply voltage VS generated from the double boost-up power supply VDD2, so that the electric charge consumed in the VCI power supply is “3.4 [V]×C” that is twice as much. In addition, the electric charge corresponding to the change in the potential of the source lines S1to Sn (that is, electric charge of “1.7 [V]×C”) is consumed in the VCOML output amplifier42in order to cancel the influence caused by the pull-up of the source lines S1to Sn and to keep the counter electrode VCOM to −1.0 [V]. As a result, the electric charge consumed in the VCI power supply in the period T5is “5.1 [V]×C”.

Through the whole periods T1to T5, the electric charge of “9.9 [V]×C” in total is consumed in the VCI power supply for providing black display. For displays of other colors, the electric charge consumption can also be calculated similarly.

FIG. 28is a table showing the electric charges consumed for each display color when executing the driving method shown inFIGS. 25 and 26. As described above, the electric charge of “9.9 [V]×C” in total is consumed in the VCI power supply for providing black display. Further, the electric charge of “7.1 [V]×C” in total is consumed in the VCI power supply for providing white display, and the electric charge of “5.1 [V]×C” in total is consumed in the VCI power supply for providing gray display. Advantages of the driving method shown inFIGS. 25 and 26can be understood by comparingFIG. 28withFIG. 5which shows the electric charges consumed with a driving method according to the reference technique. For performing black display, it is possible with the driving method of a second embodiment to reduce the electric charge consumption to “9.9 [V]×C”, while the electric charge of “16.5 [V]×C” is consumed with the reference technique.FIG. 38shows a comparison table regarding the electric charge consumption.

Third Embodiment

By comparing the electric charges consumed in the operations of a first embodiment for changing the polarity of the driving voltage from negative to positive, i.e., the electric charges consumed in the operations for pulling down the counter electrode VCOM to the potential VCOML (seeFIG. 14), with the electric charges consumed by the same operations of a second embodiment (seeFIG. 28), it can be understood that: for performing white display, the electric charge consumption is smaller in a first embodiment; and for performing black display, it is smaller in a second embodiment. Therefore, it is possible to reduce the electric charge consumption by changing, in accordance with the values of image data, the operation of the period T4where the counter electrode VCOM is pulled down from the ground potential VSS to the potential VCOML.

More specifically, as shown inFIGS. 7A and 8Aof a first embodiment, the source line Sj providing white display (that is, the source line Sj that is driven to a potential relatively close to the potential VCOML) is set to be in the high-impedance state in the period T4where the counter electrode VCOM is pulled down from the ground potential VSS to the potential VCOML. In the meantime, as shown inFIGS. 25 and 26of a second embodiment, the source line Sj providing black display (that is, the source line Sj that is driven to a potential relatively deviated from the potential VCOML) is continuously connected to the VCI power supply in the period T4.

FIG. 29is a block diagram showing an example of a structure of the source driver circuit12that makes it possible to achieve such operations.FIG. 29shows the circuit structure of a part of the source driver circuit12, which corresponds to a single source line Sj. As can be understood by comparing it with the structure of the source driver circuit12of a first embodiment shown inFIG. 6C, a data judging circuit28-jfor controlling the switch SW1in accordance with the value of the image data is provided in a third embodiment. More specifically, the polarity signal POL for designating the polarity of the driving voltage and the control signal S-SW1are supplied to the data judging circuit28-jfrom the timing control circuit15, and the highest order bit of the image data, “MSBDATA”, is supplied to the data judging circuit28-jfrom the latch circuit22-j. Note that the control signal S-SW1is asserted in the period T4, as in the case of a second embodiment. The data judging circuit28-jgenerates a control signal SW1_SEL for controlling the switch SW1of the output control circuit26-j, from the polarity signal POL, the control signal S-SW1, and a highest order bit MSBDATA.

FIG. 30is a true-value table showing an operation of the data judging circuit28-j. The true-value table ofFIG. 30shows logic behaviors of a case where black-based display is performed on a normally-white panel, when the gray-scale selection circuit24-jselects a potential deviated from the counter electrode VCOM (that is, black display is performed on the source line Sj), provided that the polarity signal POL for designating the polarity of the driving voltage to be positive is “0” and the value of the image data is large (that is, the highest order bit MSBDATA is “1”). Inversely, a logic operation when the highest order bit of the image data, “MSBDATA”, is “0” is executed when performing white-based display.

When the polarity of the driving voltage is changed from negative to positive (that is, when the polarity signal POL is set as “0”, and the counter electrode VCOM is pulled down from the potential VCOMH to the potential VCOML), the control signal SW1_SEL is controlled in accordance with the highest order bit MSBBATA in the period T4. More specifically, in the period T4, when the highest order bit MSBDATA is “0” (that is, white display is performed on the source line Sj), the data judging circuit28-jsets the control signal SW1_SEL as “0” to turn off the switch SW1, even though the control signal SW1is “1” (that is, “High” level). In the period T4, the switch SW2is also turned off. As a result, the source line Sj is set to be in the high-impedance state. In the meantime, when the highest order bit MSBDATA is “1” (that is, black display is performed on the source line Sj), the control signal SW1_SEL is set as “1” to turn on the switch SW1. By turning on the switch SW1, the source line Sj is connected to the VCI power supply interconnection27and short-circuited to the VCI power supply.

In the meantime, when the polarity of the driving voltage is changed from positive to negative (that is, when the polarity signal POL is set as “1”, and the counter electrode VCOM is pulled up from the potential VCOML to the potential VCOMH), the data judging circuit28-jsets the value of the control signal SW1to be consistent with the value of the control signal SW1_SEL regardless of the highest order bit MSBDATA.

In the operations ofFIG. 30, the control signal SW1_SEL is generated by responding only to the highest order bit of the image data, so that the operation for driving the source line Sj to an intermediate potential may not be optimum. It becomes possible to execute the operation with more reduced power consumption, through generating the control signal SW1_SEL by responding to a plurality of bits of the image data. However, the structure of generating the control signal SW1_SEL by responding only to the highest order bit is effective for reducing the circuit scale of the data judging circuit28-j.

As described, in the liquid crystal display device1of a third embodiment, each source line is short-circuited to the VCI power supply or set to be in the high-impedance sate in accordance with the image data. With this, the power consumption can be reduced further.

Fourth Embodiment

FIG. 31Ais a block diagram showing a structure of a liquid crystal display device1A according to a fourth embodiment. The liquid crystal display device1of a fourth embodiment has almost a same structure as that of the liquid crystal display device of a first embodiment shown inFIG. 6A, except for following aspects.

First, a common interconnection16having a low impedance (that is, the interconnection width thereof is large), switches SW3and SW4, and a ground interconnection29are added to a source driver circuit12A of an LCD driver3A. The switch SW1is provided between the common interconnection16and the output of the source driver circuit12, the switch SW3is provided between the common interconnection16and the VCI power supply interconnection27, and the switch SW4is provided between the common interconnection16and the ground interconnection29. For controlling the switches SW3and SW4, control signals S-SW3and S-SW4are supplied to the source driver circuit12A from the timing control circuit15.

Secondly, a switch SW5is provided to a VCOM circuit14A. The switch SW5is connected between the output of the VCOM circuit14A and the common interconnection16of the source driver circuit12A. For controlling the switch SW5, a control signal S-SW5is supplied to the VCOM circuit14A from the timing control circuit15.

The Switch SW5provided to the VCOM circuit14A functions to provide a path for directly short-circuiting the source lines S1to Sn to the counter electrode VCOM. In a first embodiment, the source lines S1to Sn and the counter electrode VCOM are all connected to the VCI power supply to be electrically short-circuited. With such structure, however, the impedance of the path through which the electric charges transfer becomes increased, so that time for the source lines S1to Sn and the counter electrode VCOM to be stabilized to the potential VCI may become extended. With the structure of this embodiment, the source lines S1to Sn and the counter electrode VCOM can be connected via a short path by turning on the switch SW5. Therefore, the time for stabilizing the source lines S1to Sn and the counter electrode VCOM to the potential VCI can be shortened.

The switches SW3and SW4are capable of setting the source lines S1to Sn not only to the potential VCI but also to the ground potential VSS. The source lines S1to Sn can be set to the potential VCI by turning on the switches SW1and SW3while turning off the switch SW4. Further, the source lines S1to Sn can be set to the ground potential VSS by turning on the switches SW1and SW4while turning off the switch SW3. To set the source lines S1to Sn to the ground potential VSS is effective when stopping a display operation of the liquid crystal display device1A without having a residual image. It is preferable to release the electric charges remained in the pixels of the LCD panel2to the ground in order to stop the display operation of the liquid crystal display device1A without having a residual image. It becomes possible to release the electric charges remained in the pixels of the LCD panel2to the ground and stop the display operation of the liquid crystal display device1A without having a residual image, through scanning the gate lines G1to Gm by turning on the switches SW1and SW4.

The structure having the VCI power supply interconnection27and the ground interconnection29connected to the common interconnection16via the switches SW3and SW4is preferable, since it is possible to connect the output terminals (that is, the source lines S1to Sn) of the source driver circuit12A to the VCI power supply interconnection27and the ground interconnection29electrically without increasing the circuit scale of the source driver circuit12. It is true that a structure having individual switches for connecting the VCI power supply interconnection27and the ground interconnection29to each of the output terminals of the source driver circuit12A can also be employed. However, with such structure, the number of switches is increased, and a plurality of thick interconnections are required for distributing the potential VCI and the ground potential with a low impedance. Therefore, the area of the source driver circuit12A becomes enlarged. The structure of an embodiment can set the source lines to the potential VCI and the ground potential VSS by using a single thick interconnection with a low impedance (specifically, the common interconnection16), so that the enlargement of the area can be suppressed.

Basically, the operations of the liquid crystal display device1A of a fourth embodiment are almost the same as those of the liquid crystal display device1of a first embodiment. The main difference is that the switch SW5is turned on in a fourth embodiment when short-circuiting the source lines S1to Sn and the counter electrode VCOM to the VCI power supply. Hereinafter, the operations of the liquid crystal display device1A of a fourth embodiment will be described in details.

FIG. 32is a timing chart for describing the operation of the liquid crystal display device1A when changing the polarity of the driving voltage from negative to positive (i.e., when pulling down the counter electrode VCOM from the potential VCOMH to the potential VCOML).FIG. 33is a flowchart showing the operation of the liquid crystal display device1A in each period. Explanations hereinafter will be provided assuming that the liquid crystal display device1is in the initial state in the period T1.

In the period T1, the counter electrode VCOM is pulled up to the potential VCOMH, and the source lines S1to Sn are driven to the potential corresponding to the image data. In addition, the switches SW1, SW3to SW5, SW7to SW9are turned off, while the switches SW2and SW6are turned on. That is, the control signals S-SW1, S-SW3to SW-5, S-SW7to SW9are negated, while the control signals S-SW2and S-SW6are asserted.

From the period T2, an operation for changing the polarity of the driving voltage from negative to positive are started. In the period T2, the source lines S1to Sn and the counter electrode VCOM are short-circuited to the VCI power supply. Note that, in a present embodiment, the switch SW5is turned on, and the source lines S1to Sn and the counter electrode VCOM are short-circuited via the switch SW5for short-circuiting the source lines S1to Sn and the counter electrode VCOM to the VCI power supply. As described above, to have the switch SW5turned on is effective for connecting the source lines S1to Sn and the counter electrode VCOM via a short path and for shortening a time for stabilizing the source lines S1to Sn and the counter electrode VCOM to the potential VCI.

More specifically, the control signals S-SW1, S-SW3, S-SW5, S-SW8are asserted and the switches SW1, SW3, SW5, SW8are turned on, while the switches SW2, SW4, SW6, SW7, SW9are turned off. With this, the source lines S1to Sn are connected to the VCI power supply interconnection27, and the counter electrode VCOM is connected to the VCI power supply interconnection43. In addition, the common interconnection16and an output of a VCOM circuit143are short-circuited, and the source lines S1to Sn and the counter electrode VCOM are driven to the potential VCI. With this operation, the electric charges of the source lines S1to Sn and the counter electrode VCOM are simply redistributed through the VCI power supply interconnections27and43and the switch SW5, so that no power is consumed.

In the period T3following the period T2, the counter electrode VCOM is pulled down to the ground potential VSS, while the source lines S1to Sn are being connected to the VCI power supply. More specifically, the control signals S-SW1, S-SW3, S-SW9are asserted and the switches SW1, SW3, SW9are turned on, while the switches SW2, SW4, SW5, SW6, SW7, and SW8are turned off. With this operation, the counter electrode VCOM is short-circuited to the ground interconnection44, while the source lines S1to Sn are being connected to the VCI power supply interconnection27. This operations requires no electric charge for pulling down the counter electrode VCOM to the ground potential VSS, even though electric charges are consumed for keeping the source lines S1to Sn to the potential VCI.

In the period T4following the period T3, the counter electrode VCOM is pulled down to the potential VCOML, while the source lines S1to Sn are in the high-impedance state. More specifically, the control signal S-SW7is asserted and the switch SW7is turned on, while the switches SW1to SW6, SW8, and SW9are turned off. With this, the counter electrode VCOM is connected to the output of the VCOML output amplifier42, and the counter electrode VCOM is pulled down to the potential VCOML.

In the period T5following the period T4, the source lines S1to Sn are driven to the potential corresponding to the image data, while the counter electrode VCOM is kept to the potential VCOML. More specifically, the control signals S-SW2, S-SW7are asserted and the switches SW2, SW7are turned on, while the switches SW1, SW3to SW6, SW8, and SW9are turned off. With this, the source lines S1to Sn are connected to the output amplifiers25-1to25-n, and driven to a potential corresponding to the image data.

The electric charge consumed by the operations for pulling down the counter electrode VCOM to the potential VCOML through the above-described procedure is the same as the electric charge consumed by the operation of a first embodiment. With the liquid crystal display device1A of a fourth embodiment, it is also possible to reduce the power consumption when pulling down the counter electrode VCOM from the potential VCOMH to the potential VCOML.

With the liquid crystal display device1A of a fourth embodiment, the counter electrode VCOM may also be pulled down to the potential VCOML in the period T4while having the source lines S1to Sn short-circuited to the VCI power supply (as in the case of a second embodiment).FIG. 34is a timing chart for describing the operations of the liquid crystal display device1A of a fourth embodiment, when short-circuiting the source lines S1to Sn to the VCI power supply in the period T4.FIG. 35is a flowchart showing the operations of the liquid crystal display device1A in each period.

In the period T4of the operations shown inFIGS. 34 and 35, the control signals S-SW1, S-SW3, S-SW7are asserted and the switch SW7are turned on, while the switches SW2, SW4-SW6, SW8, and SW9are turned off. With this, the counter electrode VCOM is connected to the output of the VCOML output amplifier42and pulled down to the potential VCOML, while the source lines S1to Sn are being connected to the potential VCI. As described in a second embodiment, these operations make it possible to reduce the power consumption when providing black display.

In addition, as in the case of a third embodiment, whether to set each source line Sj to the high-impedance state or to have it short-circuited to the VCI power supply in the period T4may also be determined in accordance with the image data in a fourth embodiment.

FIG. 36is a timing chart for describing the operation of the liquid crystal display device1A when changing the polarity of the driving voltage from positive to negative (i.e., when pulling up the counter electrode VCOM from the potential VCOML to the potential VCOMH).FIG. 37is a flowchart showing the operations of the liquid crystal display device1A in each period.

In the period T1, the counter electrode VCOM is pulled down to the potential VCOML, and the source lines S1to Sn are driven to the potential corresponding to the image data. In addition, the switches SW1, SW3to SW6, SW8, and SW9are turned off, while the switches SW2and SW7are turned on. That is, the control signals S-SW1, S-SW3to S-SW6, S-SW8, and S-SW9are negated, while the control signals S-SW2and S-SW7are asserted.

From the period T2, the operation for changing the polarity of the driving voltage from positive to negative is started. In the period T2, the source lines S1to Sn and the counter electrode VCOM are short-circuited to the VCI power supply. Note that when the source lines S1to Sn and the counter electrode VCOM are short-circuited to the VCI power supply in a present embodiment, the switch SW5is turned on so that the source lines S1to Sn and the counter electrode VCOM are short-circuited via the switch SW5.

More specifically, the control signals S-SW1, S-SW3, S-SW5, S-SW8are asserted and the switches SW1, SW3, SW5, SW8are turned on, while the switches SW2, SW4, SW6, SW7, and SW9are turned off. With this, the source lines S1to Sn are connected to the VCI power supply interconnection27, and the counter electrode VCOM is connected to the VCI power supply interconnection43. In addition, the common interconnection16is short-circuited to the output of the VCOM circuit14B. Thereby, the source lines S1to Sn and the counter electrode VCOM are driven to the potential VCI. With this operation, the electric charges of the source lines S1to Sn and the counter electrode VCOM are simply redistributed through the VCI power supply interconnections27,43, and the switch SW5, so that no power is consumed.

In the period T3following the period T2, the counter electrode VCOM is pulled up to the potential VCOMH, while the source lines S1to Sn are in the high-impedance state. More specifically, the control signal S-SW6is asserted and the switch SW6is turned on, while the switches SW1to SW5and SW7to SW9are turned off. With this, the counter electrode VCOM is connected to the output of the VCOMH output amplifier41, and the counter electrode VCOM is pulled up to the potential VCOMH. The potential of the source lines S1to Sn is boosted up because of the pull-up of the counter electrode VCOM. However, the change in the potential of the counter electrode VCOM is small, so that the amount of the change in the potential of the source lines S1to Sn is also small. Thus, no electric charge is consumed in the period T3.

In the period T4following the period T3, the source lines S1to Sn are driven to the potential corresponding to the image data, while the counter electrode VCOM is kept to the potential VCOMH. More specifically, the control signals S-SW2, S-SW6are asserted and the switches SW2, SW6are turned on, while the switches SW1, SW3to SW5, and SW7to SW9are turned off. With this, the source lines S1to Sn are connected to the output amplifiers25-1to25-n, and driven to the potential corresponding to the image data.

With such driving method, the counter electrode VCOM can be pulled up from the potential VCOML to the potential VCOMH without having an increase in the power consumption at least.

With a present embodiment, it is also possible to employ a structure where the VCI power supply interconnection43and the switch SW8are omitted from the VCOM circuit14B of the LCD driver3A, as shown inFIG. 31B. In the operations described above, the switches SW3and SW5are turned on in the period T2where the source lines S1to Sn and the counter electrode VCOM are connected to the VCI power supply. Thus, in the period T2, the counter electrode VCOM is connected to the VCI power supply interconnection27via the switches SW5and SW3. The VCI power supply interconnection43and the switch SW8are connected between the counter electrode VCOM and the VCI power supply in parallel to the switches SW3and SW5. Therefore, the counter electrode VCOM can be connected to the VCI power supply without having the VCI power supply interconnection43and the switch SW8.

Although the present invention has been described above in connection with several embodiments thereof, it would be apparent to those skilled in the art that those embodiments are provided solely for illustrating the present invention, and should not be relied upon to construe the appended claims in a limiting sense.