Test apparatus and manufacturing method

Provided is a test apparatus that tests a device under test, comprising a test signal generating section that generates a test signal to be applied to the device under test; a first driver that is electrically connected to a terminal of the device under test and that supplies the test signal to the terminal of the device under test; a correction signal generating section that generates a correction signal for correcting attenuation of the test signal occurring until the test signal reaches the terminal of the device under test; and a second driver that is electrically connected to the terminal of the device under test and that supplies the correction signal to the terminal of the device under test.

BACKGROUND

1. Technical Field

The present invention relates to a test apparatus. In particular, the present invention relates to a test apparatus provided with a correction signal generating section that generates a correction signal for compensating loss of a test signal applied to a device under test, and to a method for manufacturing a device that uses the test apparatus.

2. Related Art

When conventionally testing a device under test such as a semiconductor circuit, the acceptability of the device under test is judged by applying a prescribed test signal to the device under test and measuring a response signal output by the device under test. For example, a test is performed to determine whether the device under test is operating normally by judging whether a logic pattern of the response signal output by the device under test supplied with the test signal having a prescribed test pattern matches an expected value pattern.

When performing such a test, the test apparatus applies the prescribed signal to the device under test. If the signal is attenuated in the transmission path from the test apparatus to the device under test, however, the logic pattern of the test signal to be applied to the device under test is sometimes different from the actual logic pattern of the test signal applied to the device under test.

To solve this problem, a test apparatus is known that corrects the waveform of the test signal in advance according to the attenuation of the test signal in the transmission path. Japanese Patent Application Publication No. 2002-40112, for example, discloses a test apparatus that can generate the test signal to have emphasized edge portions by generating a plurality of pulse signals having different pulse widths, with the edge timing of the test signal as a reference, and adding the waveforms of these pulse signals to the waveform of the test signal.

This test apparatus, however, is provided with a register storing the pulse width and amplitude of the correction signal for correcting in advance the waveform of the test signal, and with a calculating apparatus that obtains the pulse width and amplitude of the correction signal for correcting the waveform of the test signal based on digital data of the waveform of the signal resulting from the test signal applied to the device under test being reflected at the end of the transmission line. Not only does this result in a complicated circuit configuration, but also necessitates changing the settings of the register and the calculating apparatus when a test signal with a different waveform is applied to the device under test.

SUMMARY

Therefore, it is an object of an aspect of the innovations herein to provide a test apparatus and a method for manufacturing a device using the test apparatus, which are capable of overcoming the above drawbacks accompanying the related art. The above and other objects can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the innovations herein.

According to a first aspect related to the innovations herein, one exemplary test apparatus may include a test apparatus that tests a device under test, comprising a test signal generating section that generates a test signal to be applied to the device under test; a first driver that is electrically connected to a terminal of the device under test and that supplies the test signal to the terminal of the device under test; a correction signal generating section that generates a correction signal for correcting attenuation of the test signal occurring until the test signal reaches the terminal of the device under test; and a second driver that is electrically connected to the terminal of the device under test and that supplies the correction signal to the terminal of the device under test.

According to a second aspect related to the innovations herein, one exemplary test apparatus may include a test apparatus that tests a device under test, comprising a comparator that is electrically connected to a terminal of the device under test, and that detects a logic value of a response signal from the device under test; a correction signal generating section that generates a correction signal for correcting attenuation of the response signal occurring while the response signal travels from the terminal of the device under test to the comparator; and a driver that supplies the generated correction signal to the comparator.

According to a third aspect related to the innovations herein, one exemplary manufacturing method may include a method for manufacturing a device, comprising manufacturing the device; and selecting the device by testing the device using a test apparatus. The test apparatus includes a test signal generating section that generates a test signal to be applied to the device under test; a first driver that is electrically connected to a terminal of the device under test and that supplies the test signal to the terminal of the device under test; a correction signal generating section that generates a correction signal for correcting attenuation of the test signal occurring until the test signal reaches the terminal of the device under test; and a second driver that is electrically connected to the terminal of the device under test and that supplies the correction signal to the terminal of the device under test.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 1shows an exemplary configuration of a test apparatus1010according to an embodiment of the present invention.FIG. 2is a timing chart showing an exemplary operation of the test apparatus1010. The test apparatus1010tests a device under test1600such as an IC or an LSI, and is provided with a test head1050and a device interface section1060. The test head1050includes a timing generator1020, a pattern generator1030, a pattern delay control circuit1040, a test signal generating section1100, a correction signal generating section1200, a first driver1301, and a second driver1302. The device interface section1060provides an electrical connection between the first driver1301and a terminal of the device under test1600using a signal line that includes a coaxial cable1501, and provides an electrical connection between the second driver1302and the same terminal of the device under test1600using a signal line that includes a coaxial cable1502. The device interface section1060may instead provide the electrical connection between the first driver1301and the terminal of the device under test1600and between the second driver1302and the terminal of the device under test1600using a signal line such as a microstrip line, which does not include the coaxial cables1501and1502.

The test apparatus1010may judge the acceptability of the device under test1600by (i) applying, to the device under test1600, a test signal706S obtained by combining a test signal704S generated based on a prescribed test pattern702D and a correction signal705S generated based on a correction pattern703D generated from the test pattern702D and (ii) comparing a logic pattern of a response signal from the device under test1600to an expected value pattern corresponding to the test pattern702D. In the test apparatus1010shown inFIG. 1, the configuration of the section that judges the acceptability of the device under test1600based on the response signal from the device under test1600is not shown.

The timing generator1020is a circuit that generates a cyclical signal701S for generating the test pattern702D. The cyclical signal701S has a specific repeating cycle, as shown inFIG. 2. Upon receiving the cyclical signal701S generated by the timing generator1020, the pattern generator1030generates the test pattern702D based on the cyclical signal701, and sends the test pattern702D to the pattern delay control circuit1040. The test pattern702D is a logic pattern with a prescribed arrangement of logic H and logic L, and includes pattern data that is to be contained in the test signal704S that is supplied to the device under test1600to test the device under test1600. The pattern delay control circuit1040sends the test pattern702D sent from the pattern generator1030to the waveform shaper1120of the test signal generating section1100, described below, without altering the signal. The pattern delay control circuit1040also generates the correction pattern703D, which is a logic pattern obtained by delaying the test pattern702D by one bit and inverting the delayed test pattern702D, and sends the correction pattern703D to the waveform shaper1220of the correction signal generating section1200, described below.

The test signal generating section1100includes the waveform shaper1120and a variable delay circuit1140, and generates the test signal704S applied to the device under test1600. The waveform shaper1120generates the test signal704S based on the test pattern702D sent from the pattern delay control circuit1040. The variable delay circuit1140delays the test signal704S generated by the waveform shaper1120by an amount set in advance according to the test pattern702D. The test signal generating section1100sends the generated test signal704S to the first driver1301. The first driver1301supplies the test signal704S received from the test signal generating section1100to the terminal of the device under test1600via the signal line that includes the coaxial cable1501of the device interface section1060. Here, the test signal704S is a pulse signal having a voltage level that corresponds to the logic value of each bit of the test pattern702D. For example, for each prescribed period, e.g. each unit cycle, the test signal704S takes a voltage value that corresponds to each logic H and logic L of the test pattern702D centered on a reference voltage value of zero, as shown inFIG. 2.

The correction signal generating section1200includes a waveform shaper1220and a variable delay circuit1240. The correction signal generating section1200generates the correction signal705S that compensates for the attenuation of the test signal704S that occurs until the test signal704S reaches the terminal of the device under test1600. The waveform shaper1220generates the correction signal705S based on the correction pattern703D sent by the pattern delay control circuit1040. The variable delay circuit1240delays the correction signal705S generated by the waveform shaper1220by an amount set in advance according to the correction pattern703D. The correction signal generating section1200sends the generated correction signal705S to the second driver1302. The second driver1302supplies the correction signal705S received from the correction signal generating section1200to the same terminal of the device under test1600that received the test signal704S from the first driver1301, via the signal line that includes the coaxial cable1502of the device interface section1060. In the test apparatus1010of the present embodiment, instead of being generated by the test head1050and supplied to the terminal of the device under test1600along with the test signal704S, the correction signal705S may be generated in advance based on the test pattern702D and supplied directly to the terminal of the device under test1600.

The correction signal705S is a pulse signal generated based on the correction pattern703D, which is generated from the test pattern702D by the pattern delay control circuit1040, as described above. The correction signal705S has a voltage level that corresponds to the logic value of each bit of the correction pattern703D. For example, for each unit cycle that is the same as that of the test signal704S, the correction signal705S takes a voltage value that corresponds to each logic H and logic L of the correction pattern703D centered on a reference voltage value of zero, as shown inFIG. 2. Here, the amplitude of the correction signal705S relative to the reference voltage is smaller than the amplitude of the test signal704S relative to the reference voltage. From the above, it is understood that the correction signal705S is a pulse signal obtained by delaying the test signal704S by one cycle and then inverting the delayed test signal704S, and therefore the correction signal705S has an amplitude, i.e. a voltage level centered on the reference voltage, that is smaller than that of the test signal704S.

The test signal704S and the correction signal705S are combined at the terminal of the device under test1600, and the resulting test signal706S is supplied from the terminal to the device under test1600. In comparison to the test signal704S, the test signal706S has a waveform in which each rising edge and falling edge is emphasized by the correction signal705S.

In this way, even when the change in the voltage level between each pulse in the test signal704S becomes very small due to attenuation, particularly at the rising edges and falling edges, that occurs while the test signal704S travels from the first driver1301to the terminal of the device under test1600, the test apparatus1010of the present embodiment can use the correction signal705S to emphasize the rising and falling edges of the pulses. Accordingly, bit errors are less likely to occur at the device under test1600side, thereby enabling accurate testing of the device under test1600.

Since the amplitude of each pulse in the correction signal705S is smaller than the amplitude of each pulse in the test signal704S, as described above, when combining the test signal704S and the correction signal705S, even if a portion corresponding to logic H in the correction signal705S is superimposed on a portion corresponding to logic L in the test signal704S or a portion corresponding to logic L in the correction signal705S is superimposed on a portion corresponding to logic H in the test signal704S, bit errors at the device under test1600side can be prevented.

FIG. 3shows an exemplary configuration of a test apparatus1011according to a modification of the present embodiment. The components of the test apparatus1011shown inFIG. 3are given the same reference numerals as identical components in the test apparatus1010, and further description is omitted. The test apparatus1011is provided with a test head1051and a device interface section1061. In the test apparatus1011, the transmission paths on the output side of the first driver1301and the output side of the second driver1302are connected to a single signal line extending from the device interface section1061to the test head1051. The device interface section1061includes the signal line having the coaxial cable1511, and this signal line provides an electrical connection between (i) the first driver1301and the second driver1302and (ii) the terminal of the device under test1600. The device interface section1061may instead use a signal line that does not include the coaxial cable1511, such as a microstrip line, to provide the electrical connection between (i) the first driver1301and the second driver1302and (ii) the terminal of the device under test1600.

A cable serial resistor1403is provided in series with the coaxial cable1511at the end of the coaxial cable1511on the side of the drivers. A first driver serial resistor1401is provided between the first driver1301and the driver-side end of the cable serial resistor1403. A second driver serial resistor1402is provided between the second driver1302and the driver-side end of the cable serial resistor1403. Here, the resistance value for each of the first driver serial resistor1401, the second driver serial resistor1402, and the cable serial resistor1403is desirably set such that (i) the impedance of the coaxial cable1511as seen from the device under test1600is equal to (ii) the combined impedance of the first driver serial resistor1401, the second driver serial resistor1402, and the cable serial resistor1403. If the connection between (i) the first driver1301and the second driver1302and (ii) the terminal of the device under test1600is provided by a signal line that does not include the coaxial cable1511, the impedance of the signal line between the cable serial resistor1403and the terminal of the device under test1600is desirably set to be equal to the combined impedance of the first driver serial resistor1401, the second driver serial resistor1402, and the cable serial resistor1403.

Here, since the correction signal705S has an amplitude relative to the reference voltage less than that of the test signal704S, as described above, the signal line noise or the like might be attenuated to the same level in the test apparatus1010while being transmitted on the coaxial cable1502. In this case, it becomes difficult to detect the pulse of the correction signal705S, such that it is difficult to combine the correction signal705S with the test signal704S. To solve this problem, the correction signal705S output from the second driver1302in the test apparatus1011is combined with the test signal704S before being transmitted on the coaxial cable1511. Accordingly, the test apparatus1011can generate a more suitable test signal706S in which the rising and falling edges of the test signal704S are emphasized by correcting the attenuation of the test signal704S with the correction signal705S.

FIG. 4shows an exemplary configuration of a test apparatus1012according to another modification of the present embodiment.FIG. 5is a timing chart showing an exemplary operation of the test apparatus1012. In the timing chart and the configuration of the test apparatus1012shown inFIGS. 4 and 5, components that are the same as those of the test apparatus1010are given the same reference numeral, and further description is omitted. The test apparatus1012is provided with a test head1052and a device interface section1062. In addition to the configuration of the test head1050described above, the test head1052further includes a correction signal generating section1212and a third driver1312. In addition to the configuration of the device interface section1060in the test apparatus1010described above, the device interface section1062further includes a signal line containing a coaxial cable1512. This signal line provides an electrical connection between the third driver1312and the terminal of the device under test1600. The device interface section1062may instead use a signal line that does not include the coaxial cable1512, such as a microstrip line, to provide the electrical connection between the third driver1312and the terminal of the device under test1600.

The correction signal generating section1212includes a differentiating circuit1260that generates a signal by differentiating the pulse waveform of the supplied signal. The differentiating circuit1260generates the correction signal707S by differentiating the test signal704S output by the waveform shaper1120, and sends the generated correction signal707S to the third driver1312. The third driver1312supplies the correction signal707S received from the differentiating circuit1260to the same terminal of the device under test1600that the first driver1301and the second driver1302are connected to, via the signal line of the device interface section1062including the coaxial cable1512.

Accordingly, the correction signal707S generated by the differentiating circuit1260of the correction signal generating section1212is combined with the test signal704S and the correction signal705S at the terminal of the device under test1600. By combining the test signal704S with the correction signal705S and the correction signal707S, the device under test1600can be supplied with a test signal708S in which the rising edges and falling edges of the pulses are further emphasized.

In this way, even when the change in the voltage level between each pulse in the test signal704S becomes very small due to attenuation, particularly at the rising edges and falling edges, that occurs while the test signal704S travels from the first driver1301to the terminal of the device under test1600, the test apparatus1012of the present modification can use the correction signal705S and the correction signal707S to emphasize the rising and falling edges of the pulses. Accordingly, bit errors are less likely to occur at the device under test1600side, thereby enabling accurate testing of the device under test1600.

Furthermore, whether the amplitude of each pulse in the correction signal707S is a pulse with a high voltage level relative to the reference voltage or a pulse with a low voltage level relative to the reference voltage depends on whether the pulse in the same cycle of the test signal704S has a rising edge or a falling edge. Accordingly, when combining the test signal704S and the correction signal707S, the test apparatus1012prevents (i) a portion of the correction signal707S with a voltage level higher than the reference voltage from being superimposed on a portion of the test signal704S with a voltage level lower than the reference voltage such that the voltage level of this portion of the test signal704S becomes higher than the reference voltage and (ii) a portion of the correction signal707S with a voltage level lower than the reference voltage from being superimposed on a portion of the test signal704S with a voltage level higher than the reference voltage such that the voltage level of this portion of the test signal704S becomes lower than the reference voltage.

FIG. 6shows an exemplary configuration of a test apparatus1013according to another modification of the present embodiment.FIG. 7is a timing chart showing an exemplary operation of the test apparatus1013. As shown inFIG. 6, the test apparatus1013includes a test head1053, a device interface section1063, and a judging section1073. The test head1053includes a timing generator1023, an expected value pattern generator1033, a pattern delay control circuit1043, a correction signal generating section1213, a driver1313, a comparator1323, a variable delay circuit1443, and a latch circuit1453. The device interface section1063provides an electrical connection between the driver1313and the terminal of the device under test1600using a signal line that includes a coaxial cable1513, and provides an electrical connection between the comparator1323and the terminal of the device under test1600using a signal line that includes a coaxial cable1523. The device interface section1063may instead provide the electrical connection between the driver1313and the terminal of the device under test1600and between the comparator1323and the terminal of the device under test1600using a signal line such as a microstrip line, which does not include the coaxial cables1513and1523.

The test apparatus1013may apply, to the device under test1600, the test signal generated based on a prescribed test pattern. The test apparatus1013generates a response signal757S by combining (i) a response signal756S output by the device under test1600in response to the test signal and (ii) a correction signal755S generated based on a correction pattern753D, which is generated from an expected value pattern752D corresponding to the test pattern. The test apparatus1013may then judge the acceptability of the device under test1600by comparing the logic pattern of the response signal757S to the expected value pattern752D. In the test apparatus1013shown inFIG. 6, the configuration relating to the section for applying the test signal to the device under test1600is not described.

The timing generator1023is a circuit that generates a cyclical signal751S for generating the expected value pattern752D. The cyclical signal751S has a prescribed repeating cycle, as shown inFIG. 7. Upon receiving the cyclical signal751S generated by the timing generator1023, the expected value pattern generator1033generates the expected value pattern752D based on the cyclical signal751S and sends the expected value pattern752D to the pattern delay control circuit1043. The expected value pattern752D corresponds to the above test pattern, and is a logic pattern in which logic H and logic L are in the same arrangement as in the test pattern. The pattern delay control circuit1043sends the expected value pattern752D unaltered to the judging section1073, and also delays the expected value pattern752D by one bit to generate the correction pattern753, which is the inverted logic pattern, and sends the correction pattern753D to a waveform shaper1223of the correction signal generating section1213, described below.

The correction signal generating section1213includes the waveform shaper1223and a variable delay circuit1243. The correction signal generating section1213generates the correction signal755S that compensates for the waveform attenuation of the response signal756S occurring when the response signal756S travels from the terminal of the device under test1600to the comparator1323. The waveform shaper1223generates the correction signal755S based on the correction pattern753D received from the pattern delay control circuit1043. The variable delay circuit1243delays the correction signal755S generated by the waveform shaper1223by a preset amount corresponding to the correction pattern753D. The correction signal generating section1213sends the generated correction signal755S to the driver1313. The driver1313supplies the correction signal755S received from the correction signal generating section1213to the transmission path between the comparator1323and the terminal of the device under test1600that output the response signal756S, via the signal line including the coaxial cable1513in the device interface section1063. For example, the driver1313supplies the correction signal755S to a terminal-side end of the signal line that includes the coaxial cable1523providing the connection between the comparator1323and the terminal of the device under test1600that output the response signal756S. The driver1313may instead supply the correction signal755S to the comparator-side end of the signal line including the coaxial cable1523.

The correction signal755S is a pulse signal generated based on the correction pattern753D, which is generated from the expected value pattern752D by the pattern delay control circuit1043, as described above. The correction signal755S has a voltage level corresponding to each logic value of the correction pattern753D. As shown inFIG. 7, while centered on a reference voltage value of zero, the correction signal755S may take a voltage value that is greater than the reference voltage by a certain amount when the correction pattern753D is logic H, and may take a voltage value that is less than the reference voltage by a certain amount when the correction pattern753D is logic L. The amplitude of the correction signal755S relative to the reference voltage is smaller than the amplitude of the response signal756S relative to the reference voltage. From the above, it is understood that the correction signal755S is a pulse signal obtained by delaying the response signal756S by one cycle and then inverting the delayed response signal756S, and therefore the correction signal755S has an amplitude, i.e. a voltage level centered on the reference voltage, that is smaller than that of the response signal756S.

The response signal756S and the correction signal755S are combined near the terminal of the device under test1600, for example, to form the response signal757S having a waveform such as that shown inFIG. 2. The response signal757S is supplied to the comparator1323via the signal line including the coaxial cable1523in the device interface section1063. Upon receiving the response signal757S, the comparator1323detects the logic value of the response signal757S. The latch circuit1453acquires the logic value of the response signal757S detected by the comparator1323, at the edge timings of the cyclical signal751S supplied thereto, and sends the acquired logic values to the judging section1073as the response signal pattern758D. Here, the cyclical signal751S supplied to the latch circuit1453is delayed by the variable delay circuit1443by a preset amount. The judging section1073determines whether the logic values of the response signal757S match the logic values of the expected value pattern752D, based on the expected value pattern752D received from the expected value pattern generator1033and the response signal patterns758received from the latch circuit1453.

In the test apparatus1013described above, the response signal756S and the correction signal755S are combined near the terminal of the device under test1600, and the resulting response signal757S having the waveform shown inFIG. 7is supplied to the comparator1323. Accordingly, the correction signal755S corrects the voltage level attenuation of the response signal756S occurring when the response signal756S travels from the terminal of the device under test1600to the comparator1323. In this way, even when the change in the voltage level between each pulse in the test signal becomes very small due to attenuation that occurs while the response signal756S travels from the terminal of the device under test1600to the comparator1323, the test apparatus1013of the present modification can use the correction signal755S to emphasize the rising and falling edges. Therefore, the test apparatus1013can accurately detect the logic values of the response signal757S using the comparator1323.

Since the amplitude of each pulse in the correction signal755S is smaller than the amplitude of each pulse in the response signal756S, as described above, when combining the response signal756S and the correction signal755S, even if a portion corresponding to logic H in the correction signal755S is superimposed on a portion corresponding to logic L in the response signal756S and a portion corresponding to logic L in the correction signal755S is superimposed on a portion corresponding to logic H in the response signal756S, the comparator1323correctly detect the logic value of the response signal757S corresponding to the response signal756S.

In the same manner as in the test apparatus1012, the test head1053in the test apparatus1013may include the third driver1312and the correction signal generating section1212containing the differentiating circuit1260, and the device interface section1063may further include the signal line containing the coaxial cable1512. In this case, the differentiating circuit1260generates the correction signal by differentiating the correction signal755S output by the waveform shaper1223and sends the correction signal to the third driver1312. The third driver1312supplies the correction signal received from the differentiating circuit1260to the terminal of the device under test1600that outputs the response signal756S, via the signal line including the coaxial cable1512of the device interface section1063.

Accordingly, the correction signal generated by the differentiating circuit1260of the correction signal generating section1212is combined with the response signal756S and the correction signal755S near the terminal of the device under test1600. Therefore, the response signal756S from the device under test1600has a waveform in which the rising and falling edges of the pulses are emphasized by the combination with the correction signal755S and again by the combination with the correction signal obtained by differentiating the correction signal755S. As a result, the comparator1323can more accurately detect the response signal757S.

FIG. 8shows an exemplary configuration of a test apparatus1014according to another modification of the present embodiment. In the configuration of the test apparatus1014shown inFIG. 8, components that are the same as those of the test apparatus1013are given the same reference numeral, and further description is omitted. The test apparatus1014is provided with a test head1054and a device interface section1064. In the test apparatus1014, the output side of the driver1313and the input side of the comparator1323are connected to each other by a single signal line in the test head1054. The device interface section1064provides an electrical connection between this signal line and the terminal of the device under test1600using a signal line including a coaxial cable1514. The device interface section1064may instead provide the electrical connection between (i) the driver1313and the comparator1323and (ii) the terminal of the device under test1600using a signal line such as a microstrip line, which does not include the coaxial cable1514.

A cable serial resistor1413is provided serially with the coaxial cable1514at a driver-side end of the coaxial cable1514. A first driver serial resistor1411is provided between the driver1313and the driver-side end of the cable serial resistor1403. A second driver serial resistor1412is provided between the comparator1323and the driver-side end of the cable serial resistor1403. Here, the resistance value for each of the first driver serial resistor1411, the second driver serial resistor1412, and the cable serial resistor1403is desirably set such that (i) the impedance of the coaxial cable1514as seen from the device under test1600is equal to (ii) the combined impedance of the first driver serial resistor1411, the second driver serial resistor1412, and the cable serial resistor1413. If the connection between (i) the driver1313and the comparator1323and (ii) the terminal of the device under test1600is provided by a signal line that does not include the coaxial cable1514, the impedance of the signal line between the cable serial resistor1413and the terminal of the device under test1600is desirably set to be equal to the combined impedance of the first driver serial resistor1411, the second driver serial resistor1412, and the cable serial resistor1413.

Here, since the correction signal755S has an amplitude relative to the reference voltage less than that of the response signal756S, as described above, the signal line noise or the like might be attenuated to the same level in the test apparatus1013while being transmitted on the coaxial cable1514. In this case, it becomes difficult to detect the pulse of the correction signal755S, such that it is difficult to combine the correction signal755S with the test signal704S. To solve this problem, the correction signal755S output from the driver1313in the test apparatus1014is combined with the response signal756S by the test head1054without being transmitted on the signal line including the coaxial cable. Accordingly, the test apparatus1014can generate a more suitable response signal757S in which the rising and falling edges of the response signal756S are emphasized by correcting the attenuation of the response signal756S with the correction signal755S.

In the same manner as in the test apparatus1012, the test head1054in the test apparatus1014may include the third driver1312and the correction signal generating section1212containing the differentiating circuit1260. In this case, the differentiating circuit1260generates the correction signal by differentiating the correction signal755S output by the waveform shaper1223and sends the correction signal to the third driver1312. The third driver1312combines the correction signal received from the differentiating circuit1260with the correction signal755S and the response signal756S in the test head1054. By providing the correction signal generating section1212and the third driver1312in this way, the test apparatus1014can combine the response signal756S from the device under test1600with the correction signal755S and again with the correction signal obtained by differentiating the correction signal755S. Therefore, the comparator1323can detect the response signal757S in which the rising and falling edges of the pulses are emphasized, thereby increasing the detection accuracy.

FIG. 9shows an exemplary configuration of a test apparatus200according to another modification of the present embodiment. The test apparatus200tests a device under test300such as a semiconductor circuit. For example, the test apparatus200judges the acceptability of the device under test300by inputting a signal having a prescribed test pattern to the device under test300and comparing a test pattern of a signal output by the device under test300to an expected value pattern. The test apparatus200of the present modification is provided with a signal generating apparatus100, a pattern generating section110, a judging section120, and a transmission path140.

The pattern generating section110generates a test pattern for testing the device under test300. For example, the pattern generating section110generates a test pattern that includes a logic pattern, i.e. pattern data, to be included in the test signal input to the device under test300.

The signal generating apparatus100generates the test signal input to the device under test300based on the test pattern generated by the pattern generating section110. For example, the signal generating apparatus100generates a test signal that indicates a level corresponding to pattern data included in the test pattern. The signal generating apparatus100corrects, in advance, the waveform of the test signal. The operation and configuration of the signal generating apparatus100is described in detail further below.

The transmission path140sends the test signal output by the amplifier130to the input end of the device under test300. The transmission path140may be a wire such as a cable. The transmission path140may cause a prescribed attenuation in the test signal or may cause the test signal to become a prescribed reflected wave.

The judging section120judges the acceptability of the device under test300based on the output signal from the device under test300. For example, the judging section120judges the acceptability of the device under test300by comparing the logic pattern of the output signal to the expected value pattern supplied from the pattern generating section110. The pattern generating section110generates the expected value pattern, which is based on the generated test pattern.

The signal generating apparatus100includes a timing generating section10, a shift register section20, a register section40, and a waveform generating section. The waveform generating section of the present modification includes a first calculating section50, a second calculating section60, an output section70, and an amplifier130.

The timing generating section10includes a plurality of timing generators12-1to12-n (referred to hereinafter collectively as the “timing generators12”) that generate a plurality of cyclical signals, which each have a different phase with respect to a reference clock, based on the reference clock supplied thereto. In other words, the plurality of timing generators12each have substantially the same cycle, and each generate a cyclical signal with a phase different from that of the other cyclical signals. Each timing generator12may be a PLL circuit. Instead, a single reference timing generator12may be a PLL circuit and the rest of the timing generators12may be delay circuits. In this case, the reference timing generator12generates a first cyclical signal, the first cyclical signal is branched and received by each of the other timing generators12, and each of the other timing generators12delays the first cyclical signal by a different amount.

The shift register section20includes a plurality of flip-flops22-1to22-m (referred to hereinafter collectively as the “flip-flops22”) in a cascade connection. The shift register section20sequentially propagates each piece of data in the pattern data output by the pattern generating section110. Each flip-flop22receives the first cyclical signal output by the first timing generator12-1, as the operation clock, and sequentially propagates each piece of data in the pattern data to a downstream flip-flop22, according to the first cyclical signal.

The second calculating section60includes a plurality of sign-control circuits62-1to62-m (referred to hereinafter collectively as the “sign control circuits62”) and a plurality of calculating circuits64-1to64-m (referred to hereinafter collectively as the “calculating circuits64”), both pluralities disposed to correspond one-to-one with the plurality of flip-flops22. Each sign control circuit62determines the sign of the data value output by the corresponding flip-flop22. In other words, each sign control circuit62selects whether the sign of the data value output by the corresponding flip-flop22is positive or negative, and outputs the data value with the selected sign. The sign selected by each sign control circuit62may be set in advance by a user. The sign selected by each sign control circuit62may be fixed during operation of the signal generating apparatus100, or may be changeable during operation of the signal generating apparatus100.

Each calculating circuit64receives the data value output by the corresponding flip-flop22via the corresponding sign control circuit62. Each calculating circuit64outputs a signal having a level according to a result obtained by multiplying the received data value by a preset coefficient. Each calculating circuit64may be an amplifier circuit with an amplification rate corresponding to the above coefficient. The coefficient of each calculating circuit64may be fixed during operation of the signal generating apparatus100, or may be changeable during operation of the signal generating apparatus100.

The output section70adds together the waveforms of the signals output by the calculating circuits64, and outputs the result. The amplifier130amplifies the test signal generated by the output section70by a prescribed amplification rate, and outputs the result. The amplifier130may output the test signal with a predetermined signal level as a reference level. For example, the amplifier130may amplify the test signal by a predetermined amplification rate, add the test signal to a predetermined offset voltage, and output the result. With this configuration, a correction can be made for the waveform of the output signal with the edges of the first cyclical signal as a reference, based on the pattern data.

The register section40includes a plurality of registers42-1to42-m (referred to hereinafter collectively as the “registers42”) that are provided to correspond one-to-one with the plurality of timing generators12-2to12-n, but not with the first timing generator12-1. The registers42are in a cascade connection. In other words, the output data from each register42is input to the register42at the subsequent stage. Each register42acquires the input data according to the cyclical signal output by the corresponding timing generator12, and outputs the acquired data. In the present modification, the first-stage register42receives data output by a single pre-selected flip-flop and sequentially propagates the data according to the cyclical signal output by the corresponding timing generator12.

The first calculating section50includes a plurality of sign-control circuits52-1to52-m (referred to hereinafter collectively as the “sign control circuits52”) and a plurality of calculating circuits54-1to54-m (referred to hereinafter collectively as the “calculating circuits54”), both pluralities disposed to correspond one-to-one with the plurality of registers42. Each sign control circuit52determines the sign of the data value output by the corresponding register42. In other words, each sign control circuit52selects whether the sign of the data value output by the corresponding register42is positive or negative, and outputs the data value with the selected sign. The sign selected by each sign control circuit52may be set in advance by a user. The sign selected by each sign control circuit52may be fixed during operation of the signal generating apparatus100, or may be changeable during operation of the signal generating apparatus100.

Each calculating circuit54receives the data value output by the corresponding register42via the corresponding sign control circuit52. Each calculating circuit54outputs a signal having a level according to a result obtained by multiplying the received data value by a preset coefficient. Each calculating circuit54may be an amplifier circuit with an amplification rate corresponding to the above coefficient. The coefficient of each calculating circuit54may be fixed during operation of the signal generating apparatus100, or may be changeable during operation of the signal generating apparatus100.

The output section70adds together the waveforms of the signals output by the calculating circuits54, and outputs the result. In other words, the output section70outputs a signal obtained by adding together the waveforms of the plurality of signals output by the calculating circuits54and the calculating circuits64. With this configuration, a correction can be made for the waveform of the output signal with a timing different from the edges of the first cyclical signal as a reference, based on the pattern data.

The phases of the cyclical signals output by the timing generators12relative to the first cyclical signal may be set as desired by a user. In this way, the correction can be made for the waveform of the output signal with a desired timing as a reference. For example, when correcting a signal edge of the output signal, i.e. an edge timing of the first cyclical signal, a waveform can be generated corresponding to this signal edge at a different phase, i.e. the edge timing of a different cyclical signal. Therefore, even if a reflected wave occurs in the transmission path140, a waveform that cancels out this reflected wave is already generated in the output signal. As a result, the desired signal can be accurately input to the device under test300.

The tap control section30selects a data value output by a certain flip-flop22from among the plurality of flip-flops22, and inputs the data value to the first-stage register42. In this way, it is possible to select which flip-flop22outputs the data value to be used as the reference when correcting the waveform. The user can set in advance which flip-flop22the tap control section30selects.

The tap control section30inputs to each sign control circuit62the data value output by the corresponding flip-flop22. A user may set in advance which flip-flop22corresponds to which sign control circuit62. The setting of the tap control section30may be fixed during operation of the signal generating apparatus100.

FIG. 10is a timing chart showing an exemplary operation of the signal generating apparatus100.FIG. 10mainly describes waveform correction by the first calculating section50, and describes a case where five timing generators are provided. In this example, the tap control section30selects the data output by the flip-flop22-1to be input to the first-stage register42-2.

The flip-flop22-1sequentially propagates the data values output by the pattern generating section110, according to the first cyclical signal. As shown inFIG. 10, when the flip-flop22-1outputs a data value of 1, the register42-2acquires the data value of 1 according to a second cyclical signal output by the corresponding timing generator12-2, and outputs the acquired data value. In the same way, each register42at a later stage acquires the data output by the register42at an earlier stage according to the cyclical signal output by the corresponding timing generator12, and outputs the acquired data.

Each calculating circuit54outputs a signal according to the data value output by the corresponding register42, as shown inFIG. 10. As described above, each calculating circuit54outputs a signal having a level obtained by multiplying (i) the data value output by the corresponding register42by (ii) a preset coefficient. Each sign control circuit52determines the sign of the signal output by the corresponding calculating circuit54.

The output section70adds together the waveforms output by the calculating circuits54to correct the waveform of the output signal. At this time, the output section70may further add the waveform at unit interval (UI) units generated by the second calculating section60. The generation of the waveform at UI units is a conventional technique, and therefore no description is provided. The unit interval may refer to a period of time that a single bit lasts in the test signal.

InFIG. 10, the dotted lines indicate regions corrected by the first calculating section50and the second calculating section60. Being able to correct the waveform of the output signal based on a plurality of cyclical signals having different phases, as shown inFIG. 10, enables correction with a high degree of freedom.

As described above, the signal generating apparatus100of the present embodiment can perform waveform correction with single UI units of the output signal as references, based on the pattern data of the output signal, and can also perform waveform correction of the output signal at any desired timing. In this way, the signal generating apparatus100can accurately correct the waveform of the output signal to enable accurate testing of the device under test300.

FIG. 11shows another example of edge timings of the plurality of cyclical signals. The timing generating section10may output the cyclical signals such that the distribution of edge timings of the cyclical signals output by the plurality of timing generators12other than the first timing generator12-1becomes denser when these edge timings are closer to the edge timings of the first cyclical signal output by the first timing generator12-1, as shown inFIG. 11A. In this case, finer correction can be performed near the signal edges of the output signal.

The timing generating section10may set the phase difference between the first cyclical signal and the cyclical signal output by a certain timing generator12to be greater than 1 UI (unit interval of the first cyclical signal), as shown inFIG. 11B. In this case, a waveform can be generated in advance that cancels out the reflected wave occurring at a phase separated from the pulse of the output signal by more than 1 UI. The cycle of each cyclical signal may be substantially equal to the cycle of the test signal, i.e. 1 UI.

FIG. 12shows another exemplary configuration of the signal generating apparatus100. The signal generating apparatus100of the present example has the same configuration as the signal generating apparatus100shown inFIG. 9, except that instead of a register section40, the signal generating apparatus100of the present example has a set-reset latch section80. Other components are the same as those of the signal generating apparatus100shown inFIG. 9, and therefore further description is omitted.

The set-reset latch section80includes a plurality of set-reset latches82-2to82-(n−1) (referred to hereinafter collectively as the “set-reset latches82”) provided to correspond one-to-one with the timing generators12-2to12-(n−1), but not with the first timing generator12-1and the final-stage timing generator12-n. Each set-reset latch82receives a cyclical signal from both the corresponding timing generator12and the timing generator12at the next stage after the corresponding timing generator12. The timing generator12at the next stage may refer to the timing generator12that (i) outputs a cyclical signal having a phase delayed by the cyclical signal output by the corresponding timing generator12and (ii) outputs a cyclical signal having a phase that is nearest the phase of the cyclical signal output by the corresponding timing generator12.

Each set-reset latch82outputs a signal that indicates a logic value of 1 during a period between (i) the edge of the cyclical signal received from the corresponding timing generator12and (ii) the edge of the cyclical signal received from the timing generator12at the next stage. The tap control section30inputs to the sign control circuits52the data value output by the selected flip-flop22. Each sign control circuit52determines the sign of the received data value when the corresponding set-reset latch82outputs a logic value of 1, and outputs the determined sign.

The signal generating apparatus100of the present example can correct the waveform of the output signal at a desired timing corresponding to the edges of the cyclical signals, and can correct the waveform of the output signal at a desired pulse width corresponding to the phase difference of each cyclical signal. For example, the signal generating apparatus100can perform an extremely fine waveform correction by significantly decreasing the phase difference between the cyclical signals output by two timing generators12.

FIG. 13shows another exemplary configuration of the signal generating apparatus100. The signal generating apparatus100of the present example generates a continuous waveform by emphasizing a prescribed frequency component in a discrete waveform obtained by combining rectangular waveforms, such as the waveforms shown inFIG. 10. For example, the signal generating apparatus100may emphasize the waveform in UI units, as shown inFIG. 10, or may emphasize a prescribed frequency component of the output signal. In the latter case, the signal generating apparatus100shown inFIG. 9orFIG. 12may be further provided with an analog circuit500that is located downstream from the amplifier130and that emphasizes the prescribed frequency component of the waveform output by the amplifier130. The analog circuit500may be an analog peaking circuit that emphasizes a prescribed high-frequency component. The analog circuit500may emphasize the high-frequency component by superimposing a differential waveform of the input waveform or the like onto the input waveform. The analog circuit500may smooth the input waveform. With this configuration, the signal generating apparatus100can convert the discrete waveform of the output signal shown inFIG. 10into a continuous waveform in which the prescribed frequency component is emphasized.

FIG. 13describes an exemplary configuration of the signal generating apparatus100when emphasizing the waveform in UI units shown inFIG. 10. The signal generating apparatus100of the present example has the same basic configuration as the signal generating apparatus100shown inFIG. 9, but the register section40and the first calculating section50are removed and the analog circuit500is included. The timing generating section10of the present example also differs from the timing generating section10ofFIG. 9in that this timing generating section10has only one timing generator12-1. Other components are the same as those of the signal generating apparatus100shown inFIG. 9, and therefore further description is omitted.

The shift register section20sequentially propagates each piece of data in the pattern data to the plurality of flip-flops22, according to the cyclical signal generated by the timing generator12-1. For example, the timing generator12-1may generate the cyclical signal to have a cycle substantially equal to the cycle of the test signal to be generated, i.e. 1 UI. The tap control section30of the present example may have the same function and configuration as the tap control section30described inFIG. 9orFIG. 12.

The waveform generating section of the present example includes the second calculating section60, the output section70, and the amplifier130. The waveform generating section generates an output signal having a value that changes at each cycle of the cyclical signal generated by the timing generator12-1, based on the data values output by the flip-flops22in the shift register section20. Since the signal generating apparatus100of the present example does not include the register section40and the first calculating section50, the waveform of the output signal from the amplifier130corresponds to the waveform in UI units shown inFIG. 10, for example.

The analog circuit500emphasizes the prescribed frequency component in the waveform of the output signal generated by the amplifier130of the waveform generating section, and inputs the resulting waveform to the device under test300via the transmission path140. For example, the analog circuit500may be an analog peaking circuit that emphasizes a predetermined high-frequency component to emphasize the edge portions of the output signal. The analog circuit500may be provided in parallel with an RC high-pass filter in the transmission path, as described below inFIG. 18, and may generate a waveform in which the predetermined high-frequency component is emphasized by combining the signals of the RC high-pass filter and the transmission path. The time constant of the analog circuit500may be determined according to the time constant of the transmission path140, which can be measured in advance.

FIG. 14shows exemplary analog waveforms output by the analog circuit500. As described above, the analog circuit500is supplied with a discrete waveform in UI units, and generates an analog waveform in which the high-frequency component is emphasized. The signal generating apparatus100of the present example uses the simple configuration shown inFIG. 13to generate a test signal having a value that changes in units smaller than 1 UI, as shown inFIG. 14.

FIG. 15shows another exemplary configuration of the signal generating apparatus100. The signal generating apparatus100of the present example has the same configuration as the signal generating apparatus100shown inFIG. 9, but is further provided with the analog circuit500. Furthermore, the timing generating section10includes the first timing generator12-1and the second timing generator12-2, and register section40includes a single register42-2, and the first calculating section50includes a single sign control circuit52-2and a single calculating circuit54-2. Other components are the same as those of the signal generating apparatus100shown inFIG. 9, and therefore further description is omitted.

The second timing generator12-2may generate a second cyclical signal having a phase that differs from that of the first cyclical signal generated by the first timing generator12-1. The second cyclical signal and the first cyclical signal may have substantially the same cycle. The register42-2sequentially acquires the data output by the single flip-flop22selected in advance by the tap control section30, according to the second cyclical signal received from the second timing generator12-2.

The waveform generating section of the present example includes the first calculating section50, the second calculating section60, the output section70, and the amplifier130. The waveform generating section generates an output signal having a value that changes according to a phase of the first cyclical signal and a phase of the second cyclical signal, based on the data values output by the flip-flops22and the registers24.

More specifically, the sign control circuit52-2and the calculating circuit54-2in the first calculating section50generate a waveform having a value that changes according to the phase of the second cyclical signal, based on the data values output by the register24. The second calculating section60generates a waveform having a value that changes according to the phase of the first cyclical signal output by the data values output by the flip-flops22. The output section70combines the waveforms output by the first calculating section50and the second calculating section60to generate the output signal having a value that changes according to a phase of the first cyclical signal and a phase of the second cyclical signal.

The amplifier130and the analog circuit500may have the same function and configuration as the amplifier130and the analog circuit500shown inFIG. 13. This configuration enables more accurate correction of the waveform of the test signal. For example, the signal generating apparatus100can generate a waveform in which a reflected wave or the like occurring at a certain timing differing from the edges of the first cyclical signal is compensated for.

In this case, the tap control section30may select the flip-flop22to be connected to the register42-2according to which unit interval includes the reflection of a square wave in a certain unit interval. By selecting a flip-flop22, the tap control section30can select a unit interval for generating the waveform to compensate for the reflected wave. The phase in the selected unit interval at which the waveform compensating for the reflected wave is generated can be adjusted by the phase of the second cyclical signal generated by the second timing generator12-2. The second timing generator12-2may generate the second cyclical signal to have a phase difference, relative to the first cyclical signal, that corresponds to the phase at which the waveform compensating for the reflected wave is to be generated.

FIG. 16shows another exemplary configuration of the signal generating apparatus100. The signal generating apparatus100of the present example has the same configuration as the signal generating apparatus100at shown inFIG. 15, except that the signal generating apparatus100of the present invention is provided with the set-reset latch section80instead of the register section40. The set-reset latch section80includes a single set-reset latch82, as described inFIG. 12. The timing generating section10further includes a third timing generator12-3. Other components are the same as those of the signal generating apparatus100shown inFIG. 15, and therefore further description is omitted.

The third timing generator12-3generates a third cyclical signal. The third cyclical signal may have a phase different from that of the second cyclical signal. The set-reset latch82receives the second cyclical signal and the third cyclical signal, and outputs a pulse having a pulse width corresponding to the phase difference between the second cyclical signal and the third cyclical signal, as described inFIG. 12.

As described inFIG. 12, the sign control circuit52-2determines the sign of the logic value supplied from the tap control section30, and outputs the sign while the signal received from the set-reset latch82is logic H. The processes performed by the calculating circuit54and onward may be the same as the processes of the signal generating apparatus100described inFIG. 15.

With this configuration, the signal generating apparatus100can generate a waveform in which the reflected wave or the like is compensated for with a pulse width that differs from the cycle of each cyclical signal. In other words, the signal generating apparatus100can generate a waveform in which a reflected wave or the like with any pulse width is compensated for by adjusting the phase difference between the second cyclical signal and the third cyclical signal.

FIG. 17shows an exemplary operation of the signal generating apparatus100described inFIG. 16. InFIG. 17, T1represents the phase of the first cyclical signal and T2represents the phase of the second cyclical signal, for example. As described above, the signal generating apparatus100can generate a waveform in which a pulse with a certain pulse width is set at a certain position by adjusting the phase difference between the first cyclical signal and the second cyclical signal. In this way, the signal generating apparatus100can compensate for a reflected wave or the like with any pulse width occurring at any location.

FIG. 18shows an exemplary configuration of the analog circuit500. The analog circuit500includes a plurality of resistors502,512,522, and532, a plurality of capacitors514,524, and534, and a plurality of switches526and528. The resistors502,512,522, and532are provided in parallel. The capacitors514,524, and534are provided to correspond one-to-one with the resistors512,522, and532in the transmission path, and are each connected serially to the corresponding resistor. The switch526switches whether the resistors and capacitors from the second stage onward are connected in parallel with the resistor502in the signal path.

For example, when the switch526is off, the analog circuit500generates a waveform by superimposing a signal passed through a one-stage CR high-pass FIR filter onto the original signal. When all of the switches are on, the analog circuit500generates a waveform by superimposing a signal passed through a three-stage CR high-pass FIR filter onto the original signal. The constants for the resistors and capacitors may be adjusted according to the time constant to be set. With this configuration, a waveform can be generated in which a prescribed high-frequency component of the input signal is emphasized. The configuration of the analog circuit500is not limited to the configuration shown inFIG. 18. Any known high-frequency component emphasizing circuit can be used as the analog circuit500.

FIG. 19shows another exemplary configuration of the test apparatus200. The test apparatus200of the present example has the same configuration as the test apparatuses200described inFIGS. 9 to 18, but is further provided with a calibration section180. Other components are the same as those of the test apparatuses200shown inFIGS. 9 to 18, and therefore further description is omitted.

The calibration section180calibrates the signal generating apparatus100before testing of the device under test300. The calibration section180includes a reference generating section150, a reference measuring section170, and a control section160.

The reference generating section150outputs a reference signal having a prescribed waveform to the signal generating apparatus100. The reference generating section150of the present example causes the pattern generating section110to output prescribed pattern data.

The reference measuring section170measures the waveform of the reference signal transmitted to the input terminal of the device under test300. The control section160sets the first calculating section50and the second calculating section60based on the waveform of the reference signal measured by the reference measuring section170. For example, the control section160sets the signs for the sign control circuit52and the sign control circuit62, and sets the weighting coefficients for the calculating circuit54and the calculating circuit64. The control section160may also set the phase of the cyclical signals output by the timing generators12.

FIG. 20shows an exemplary operation of the calibration section180. As described above, the reference generating section150causes the signal generating apparatus100to output the prescribed reference signal. The reference measuring section170measures the waveform of the signal transmitted to the input terminal of the device under test300. The control section160discretizes the waveform measured by the reference measuring section170, as shown inFIG. 20. The control section160detects the attenuation or the like of the reference signal in the transmission path140based on the discretized measured waveform, and calibrates the signal generating apparatus100based on the detection result.

For example, the control section160approximates the measured waveform using a plurality of pulses. The control section160may then control the phases of the cyclical signals output by the timing generators12, based on the pulse width and phase of each pulse. The control section160may control the weighting coefficients in the calculating circuit54and the calculating circuit64based on the levels of the rectangular waves. The control section160may compare the waveform of the reference signal to the discretized measured waveform to determine whether to superimpose the rectangular wave components of the measured waveform onto the reference signal or to subtract the rectangular wave components of the measured waveform from the reference signal. The control section160may control the signs for the sign control circuit52and the sign control circuit62based on the determination result.

InFIGS. 9 to 20, the waveform of the output signal was corrected to compensate in advance for attenuation, reflection, or the like in the transmission path140, but the function of the signal generating apparatus100is not limited to this. For example, the signal generating apparatus100may deteriorate the waveform of the output signal and input the deteriorated waveform to the device under test300. In this way, it is possible to test the degree of waveform degradation that is acceptable for the device under test300to still operate correctly.

FIG. 21shows an exemplary configuration of a circuit device400according to an embodiment of the present invention. The circuit device400may include a semiconductor circuit or the like. The circuit device400is provided with a substrate410, the pattern generating section110, the signal generating apparatus100, and the control section160. The substrate410is a semiconductor substrate or the like. The pattern generating section110, the signal generating apparatus100, and the control section160may be circuits formed on the substrate410.

Components of the pattern generating section110, the signal generating apparatus100, and the control section160that are the same as those described inFIGS. 9 to 20are given the same reference numerals, and further description is omitted. The control section160of the present embodiment may receive in advance information concerning the phases of the cyclical signals, the weighting coefficients, and the signs to be set in the signal generating apparatus100. The control section160may set the signal generating apparatus100based on setting data received from the outside. With this configuration, the circuit device400can output a signal having a desired waveform.