Storage devices and methods of operating storage devices

Example embodiments provide for a storage device that includes a storage controller including a plurality of analog circuits and at least one nonvolatile memory device including a first region and a second region. The at least one nonvolatile memory device stores user data in the second region and stores trimming control codes in the first region as a compensation data set. The trimming control codes are configured to compensate for offsets of the plurality of analog circuits and are obtained through a wafer-level test on the storage controller. The storage controller, during a power-up sequence, reads the compensation data set from the first region of the at least one nonvolatile memory device, stores the read compensation data set therein, and adjusts the offsets of the plurality of analog circuits based on the stored compensation data set.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims benefit of priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0127717, filed on Sep. 28, 2021 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

1. Technical Field

The present disclosure generally relates to data processing devices, and more particularly, to storage devices and methods of operating storage devices.

2. Discussion of the Related Art

A computing device may include a desktop computer, a notebook computer, a smart phone, a smart tablet, etc. A hard disk drive has traditionally been used as a storage device. However, a mobile device, such as a smart phone, a smart tablet, etc., may use a nonvolatile memory device, such as a NAND flash memory, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc., as a storage device. A frequency of using a nonvolatile memory device as a storage device even in a notebook computer and a desktop computer is on the increase.

Offset compensation information of analog circuits in a storage controller to control a nonvolatile memory device may be stored in an electrical fuse (E-fuse) of the storage controller, which may increase a size of the storage controller.

SUMMARY

Some example embodiments may provide a storage device capable of reducing a size of a storage controller to control a nonvolatile memory device.

Some example embodiments may provide a method of operating a storage device, capable of reducing a size of a storage controller to control a nonvolatile memory device.

According to some example embodiments, a storage device includes a storage controller including a plurality of analog circuits, and at least one nonvolatile memory device including a first region and a second region. The at least one nonvolatile memory device stores user data in the second region, and stores trimming control codes in the first region as a compensation data set. The trimming control codes are configured to compensate for offsets of the plurality of analog circuits, and are obtained through a wafer-level test on the storage controller. The storage controller, during a power-up sequence, is configured to read the compensation data set from the first region of the at least one nonvolatile memory device, store the read compensation data set therein, and adjust the offsets of the plurality of analog circuits based on the stored compensation data set.

According to some example embodiments, there is provided a method of operating a storage device, which includes at least one nonvolatile memory device including a first region and a second region, and a storage controller to control the at least one nonvolatile memory device. The method includes operating, by the storage controller, at a first speed to read trimming control codes in the first region as a compensation data set. The trimming control codes compensate for offsets of a plurality of analog circuits, and are obtained through a wafer-level test on the storage controller. The method further includes storing the read compensation data set in a static random access memory (SRAM) in the storage controller. The method further includes operating, by the storage controller, at a second speed faster than the first speed to adjust the offsets of the plurality of analog circuits based on the compensation data set stored in the SRAM.

According to some example embodiments, a storage device includes a storage controller including a plurality of analog circuits, and at least one nonvolatile memory device including a first region and a second region. The plurality of analog circuits are configured to provide outputs varying based on respective one of a plurality of control codes. The at least one nonvolatile memory device is configured to store user data in the second region. The at least one nonvolatile memory device is further configured to store trimming control codes in the first region as a compensation data set. The trimming control codes are configured to compensate for offsets of the plurality of analog circuits, and are obtained through a wafer-level test on the storage controller. The storage controller, during a power-up sequence, is configured to read the compensation data set from the first region of the at least one nonvolatile memory device, store the read compensation data set therein, and adjust the offsets of the plurality of analog circuits based on the compensation data set stored therein. Each of the trimming control codes corresponds to a control code when each of the plurality of analog circuits provides a corresponding output having a target level during the wafer-level test. The first region corresponds to a single level cell block including a plurality of single level cells, each one of the plurality of single level cells being configured to store a single bit data.

Accordingly, automatic test equipment (ATE) stores trimming control codes that compensate for offsets of the plurality of analog circuits, and are obtained through a wafer-level test on the storage controller, in a single level cell (SLC) block in a nonvolatile memory device instead of an electrical fuse (E-fuse) block in the storage controller, and the storage controller reads the trimming control codes from the SLC block and adjusts the offsets of the analog circuits based on the trimming control codes during a power-up sequence. Therefore, the storage device may reduce a size of the storage controller and may store much information on the analog circuits in the SLC block.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown.

FIG.1is a schematic diagram of a wafer on which a plurality of storage controllers are formed according to example embodiments, andFIG.2is an enlarged diagram of a die in a storage controller inFIG.1, according to example embodiments.

Referring toFIGS.1and2, a plurality of dies180may be formed on a wafer170through a fabrication (FAB) process, and after the plurality of dies180are singulated along a scribe line175, the plurality of dies180may be fabricated into individual unit chips or packages through an assembly process.

Between the FAB process and the assembly process, a wafer-level test process or an electric die sorting (EDS) process, in which electrical characteristics of a storage controller (e.g., storage controller300inFIG.2) formed in each of the plurality of dies180are tested, may be performed. The wafer-level testing process may be a process in which test operation signals are applied to a die180formed on the wafer170, and the process may determine whether the die180has a defect by a test result signal output by the die180in response to the test operation signals.

An automatic test equipment (ATE)40may provide the test operation signals, transfer the test operation signals to the die180via a probe card, and may determine whether the die180is defective by receiving the test result signal in response to the test operation signals from the die180via the probe card.

Each of the dies180may include test pads (e.g., test pads191-196inFIG.2) thereon, which support the wafer-level test. When the probe card physically and electrically contacts the test pads191-196, the die180may perform the test mode in response to the test operation signals. In this case, an electrostatic discharge (ESD) or noise may be induced via the test pads191-196.

Referring toFIG.2, the die180may include at least one or more test pads191-196and the storage controller300.

The test pad191may receive a test enable signal and the test pads192-196may receive test operation signals the test operation signals may be applied to the storage controller300. The test operation signals may include a test clock signal, a test command signal, a test pattern signal, etc. for controlling operations of the storage controller300. The die180may be connected to the ATE40having a probe through the test pads191-196for performing the wafer-level test.

The storage controller300may include a plurality of analog circuits, a processor310, a power-on reset circuit (PORC)595, and a temperature sensor (TSEN)580. The plurality of analog circuits may include a low voltage detector (LVD)590, a plurality of low drop-out (LDO) regulators (LDORs)510a,510b,510c, and510d, an oscillator (OSC)610, and a reference voltage generator (RVG)570.

The low voltage detector590may receive a first operating voltage VOP1from the ATE40, may generate a reset flag RFG in response to a voltage level of the first operating voltage VOP1being smaller (e.g., lower) than a reference level, and may provide the reset flag RFG to the power-on reset circuit595. The low voltage detector590may adjust the reference level in response to a first control code CCD1.

The power-on reset circuit595may reset the low voltage detector (LVD)590, the LDO regulators510a,510b,510c, and510d, the oscillator610, and the reference voltage generator570in response to the reset flag RFG.

The LDO regulators510a,510b,510c, and510dmay regulate the first operating voltage VOP1based on at least one reference voltage VREF to generate a plurality of output voltages VOUT1, VOUT2, VOUT3, and VOUT4. Each of the LDO regulators510a,510b,510c, and510dmay adjust a level of a respective one of the output voltages VOUT1, VOUT2, VOUT3, and VOUT4based on respective one of sub control codes CCD21, CCD22, CCD23, and CCD24, included in a second control code CCD2.

The oscillator610may generate a reference clock signal RCLK associated with an operating frequency of the processor310based on one VOUT1of the plurality of output voltages VOUT1, VOUT2, VOUT3, and VOUT4. The oscillator610may adjust a frequency of the reference clock signal RCLK based on a third control code CCD3.

The reference voltage generator570may generate the at least one reference voltage VREF, and may provide the at least one reference voltage VREF to the LDO regulators510a,510b,510c, and510d. The reference voltage generator570may adjust a level of the at least one reference voltage VREF based on a fourth control code CCD4.

During an ESD test on the die180, the ATE40inFIG.1may obtain the first through fourth control codes CCD1, CCD2, CCD3, and CCD4as trimming control codes for compensating for offsets of the low voltage detector590, the LDO regulators510a,510b,510c, and510d, the oscillator610, and the reference voltage generator570in response to each of the low voltage detector590, the LDO regulators510a,510b,510c, and510d, the oscillator610, and the reference voltage generator570providing a corresponding output having a target level in response to varying respective one of the first through fourth control codes CCD1, CCD2, CCD3, and CCD4by sweeping the first through fourth control codes CCD1, CCD2, CCD3, and CCD4. The trimming control codes may be stored as a compensation data set in a single level cell (SLC) region in a nonvolatile memory device that is assembled with the storage controller300.

When the storage controller300passes a wafer-level test, and after the storage controller300is assembled with the nonvolatile memory device, the storage controller300, or the processor310, during a power-up sequence, may read the compensation data set from the SLC region, may store the read compensation data set therein (e.g., stored inside of the storage controller300), and may adjust the offsets of the low voltage detector590, the LDO regulators510a,510b,510c, and510d, the oscillator610, and the reference voltage generator570to output a voltage having a target level or a clock signal having a target frequency.

FIG.3is a flow chart illustrating fabrication process of a storage device according to example embodiments.

Referring toFIGS.1through3, a plurality of first dies180are provided on a first wafer170(operation S110). The ATE40performs an ESD test on each of the storage controllers300provided in the first dies180to generate trimming control codes for compensating for offsets of analog circuits in each of the storage controllers300(operation S130).

The ATE40determines whether each of the first dies180based on a result of the ESD test (operation S150).

In parallel with the operations S110, S130, and S150, a plurality of second dies are provided on a second wafer (operation S210). An ATE performs an ESD test on each of a plurality of nonvolatile memory devices provided in the second dies (operation S230). The ATE determines whether each of the second dies based on a result of the ESD test (operation S250).

When a first die does not pass the ESD test (NO in operation S150), the corresponding first die is processed as a failed die (operation S160). When the first die passes the ESD test (YES in operation S150), the trimming control codes is stored as a compensation data set in a first region corresponding to an SLC region of an associated nonvolatile memory device which will be assembled with a storage controller in the first corresponding die (operation S170).

When a second die does not pass the ESD test (NO in operation S250), the corresponding second die is processed as a failed die (operation S260). When the second die passes the ESD test (YES in operation S250), the corresponding nonvolatile memory device and the associated storage controller are assembled into a storage device (operation S310). The storage device may be shipped as a product (operation S330).

Each of the first dies180may have a different characteristic based on a relative location in the first wafer170, and thus, each of the storage controller300may have a different process variance based on a location of an associated die in the first wafer170.

During the ESD test on each of the storage controller300, the ATE40may determine the trimming control codes associated with control codes to render the analog circuit to output voltages and a frequency having target levels, and the ATE40may store the trimming control codes in the SLC region of the nonvolatile memory device as the compensation data set. During a real operation, when the storage controller300operates the analog circuits based on the compensation data set, the analog circuits in each of the storage controllers300provided in the first dies180may output voltages and a frequency having the same target levels without regard to the relative location of the first die180in the wafer170.

In addition, because the trimming control codes are stored in the SLC region of the nonvolatile memory device, more information may be stored in the SLC region than a case when the trimming control codes are stored in the E-fuse block in the storage controller and the trimming control codes may be easily updated. In addition, when codes, stored in a read-only memory (ROM) in the storage controller300are to be changed, the code values to be changed may be stored in the SLC region, and thus performance of the storage device may be enhanced.

FIG.4is a block diagram illustrating a clock generation circuit including an oscillator included in the storage controller inFIG.2according to example embodiments.

Referring toFIG.4, a clock generation circuit600may include an oscillator OSC610and a temperature compensation circuit TCC650.

The temperature compensation circuit650may receive an operating temperature code TCS corresponding to an operating temperature to generate the third control code CCD3varying according to the operating temperature based on a reference temperature code and the operating temperature code TCS. The reference temperature code may be determined through a test operation of the storage controller in which the clock generation circuit600is integrated. The operating temperature code TCS may be provided from the temperature sensor580inFIG.2.

The oscillator610may generate the reference clock signal RCLK having an operating frequency based on the third control code CCD3such that the operating frequency is uniform regardless of the operating temperature.

In general, the oscillator610may have a particular temperature characteristic, for example, a proportional to absolute temperature (PTAT) characteristic or a complementary to absolute temperature (CTAT) characteristic. The temperature compensation circuit650may generate the third control code CCD3that is varied in the direction to counterbalance the temperature characteristic of the oscillator610.

The clock generation circuit600may efficiently reduce the effect of change of the reference clock signal RCLK by generating the third control code CCD3reflecting the temperature characteristic of the oscillator610using the output value of the temperature sensor580and controlling the oscillator610using the third control code CCD3.

FIG.5is a circuit diagram illustrating an example of the oscillator included in a clock generation circuit according to example embodiments.

Referring toFIG.5, the oscillator610may include a reference current generator615, a charging current generator620, a comparison voltage generator630, a comparing unit640, and a latch circuit645.

The reference voltage generator615may include a reference p-channel metal-oxide semiconductor (PMOS) transistor MP0and a reference resistor Rref. The reference PMOS transistor MP0may be connected between a first power node NP1to which a regulator voltage VREG is applied and a first node N11. The reference resistor Rref may be connected between the first node N11and a second power node NP2to which a ground voltage VSS is applied.

The gate electrode and the drain electrode of the reference PMOS transistor MP0may be connected electrically. The reference current generator615may generate a reference current Iref through the first node N11and the voltage on the first node N11may be provided as a reference voltage Vref.

The charging current generator620may be connected between the first power node NP1and a second node N12. The charging current generator620may be biased with the reference voltage VREF. The reference PMOS transistor MP0and the charging current generator620may form a current mirror. The charging current generator620may generate a charging current Ichg based on the third control code CCD3.

The comparison voltage generator630may be connected between the second node N12and the second power node NP2.

The comparison voltage generator630may include a first inverting unit631and a second inverting unit632. The first inverting unit631may receive a clock signal CLK and generate a first comparison voltage VA. The second inverting unit632may receive an inverted clock signal CLKB and may generate a second comparison voltage VB. The first comparison voltage VA and the second comparison voltage VB may transition in a manner complementarily to each other.

The first inverting unit631may include a first PMOS transistor MP1and a first n-channel metal-oxide-semiconductor (NMOS) transistor MN1that are serially connected and operate as inverters. The first inverting unit631may also include a first capacitor C1for delaying a change in voltage level of the first comparison voltage VA.

As illustrated inFIG.5, the first capacitor C1is charged by the charging current Ichg. Therefore, the time taken by the first comparison voltage VA to transition from the low level to the high level may be determined by the charging current Ichg and the first capacitor C1.

The structure and operation of the second inverting unit632may be similar to the first inverting unit631. The second inverting unit632may include a second PMOS transistor MP2and a second NMOS transistor MN2that are serially connected and operate as inverters. The second inverting unit632may also include a second capacitor C2for delaying a change in voltage level of the second comparison voltage VB. As illustrated inFIG.5, the second capacitor C2is charged by the charging current Ichg. Therefore, the time taken by the second comparison voltage VA to transition from the low level to the high level may be determined by the charging current Ichg and the second capacitor C2.

In some example embodiments, sizes of the second PMOS transistor MP2and the second NMOS transistor MN2may be the same as sizes of the first PMOS transistor MP1and the first NMOS transistor MN1, respectively. In addition, the capacitance of the second capacitor C2may be the same as that of the first capacitor C1.

The comparing unit640may include a first comparator (COM1)641and a second comparator (COM2)643. The first comparator641may output first output voltage Vcmp1which corresponds to the result of a comparison between the reference voltage VREF and the first comparison voltage VA. When the first comparison voltage VA is lower than the reference voltage VREF, the first comparator641outputs the first output voltage Vcmp1at a low level. When the first comparison voltage VA is greater than or equal to the reference voltage VREF, the first comparator641may output the first output voltage Vcmp1at a high level.

The second comparator643may output a second output voltage Vcmp2which corresponds to the result of a comparison between the reference voltage VREF and the second comparison voltage VB. When the second comparison voltage VB is lower than the reference voltage VREF, the second comparator643outputs the second output voltage Vcmp2at a low level. When the second comparison voltage VB is greater than or equal to the reference voltage VREF, the second comparator643may output the second output voltage Vcmp2at a high level.

The latch circuit645latches the first output voltage Vcmp1and the second output voltage Vcmp2, and may output the reference clock signal RCLK and an inverted reference clock signal RCLKB. In an example embodiment, the latch circuit645may be implemented by an set/reset (SR) latch circuit as illustrated inFIG.5. In this case, the first output voltage Vcmp1is applied to a first input node S of the latch circuit645, and the second output voltage Vcmp2may be applied to a second input node R of the latch circuit645.

When the voltage levels of the first output voltage Vcmp1and the second output voltage Vcmp2are different (e.g., when the first output voltage Vcmp1is at a high level and the second output voltage Vcmp2is at a low level), the latch circuit645outputs the reference clock signal RCLK at the same level as the first output voltage Vcmp1through a first output node Q, and may output the inverted reference clock signal RCLKB at the same level as the second output voltage Vcmp2through a second output node QB.

When the first output voltage Vcmp1and the second output voltage Vcmp2are at a low level, the latch circuit645may output the reference clock signal RCLK and the inverted reference clock signal RCLKB in the same state as a previous state through the first output node Q and the second output terminal QB, respectively.

FIG.6is a circuit diagram illustrating an example of a charging current generator included in the oscillator ofFIG.5.

Referring toFIG.6, a charging current generator620included in the oscillator610ofFIG.5may include variable current cells CCV1-CCVp, one or more fixed current cells CCF1-CCFq and a thermometer decoder625. In some example embodiments, the thermometer decoder625may be disposed outside the oscillator610, and in this case, the oscillator610may receive a thermometer code TMC instead of the third control code CCD3.

The variable current cells CCV1-CCVp and the fixed current cells CCF1-CCFq may be connected in parallel between the first power node NP1and the second node N12.

The variable current cells CCV1-CCVp may include PMOS transistors PM and switches SW1-SWp, respectively.

The switches SW1-SWp may be turned based on bits TMC1-TMCs of the thermometer code TMC, respectively. Each of the variable current cells CCV1-CCVp may provide a unit current to the second node N12when the corresponding switch is turned on.

The fixed current cells CCF1-CCFq may include the PMOS transistors PM, respectively, and each of the fixed current cells CCF1-CCFq may provide the unit current to the second node N12regardless of the thermometer code TMC.

As such, the charging current Ichg flowing through the second node N12may be determined based on the unit current, the number of the fixed currents cells and the variable current cells that are turned on. If the sizes of the PMOS transistors PM inFIG.6are the same, in other words, if each of the variable current cells CCV1-CCVp and the fixed current cells CCF1-CCFq generates the same unit current, the charging current may be represented by Eq. 1.
Ichg=(p′+q)×Iu[Eq. 1]

In Eq. 1, p′ indicates the number of the variable current cells that are turned on, q indicates the number of the fixed current cells, and Iu indicates the unit current.

The thermometer decoder625may convert the third control code CCD3corresponding to a binary code of M bits to the thermometer code TMC of 2M−1 bits. In other words, s is equal to 2M−1. In some example embodiments, the third control code CCD3may be determined based on the difference between the measured frequency and the target frequency of the reference clock signal RCLK.

FIG.7is a block diagram illustrating one of the LDO regulators inFIG.2according to example embodiments.

FIG.7illustrates a configuration of the LDO regulator510aand each configuration of the LDO regulators510b,510cand510dmay be substantially the same as the configuration of the LDO regulator510a.

Referring toFIG.7, the LDO regulator510amay include an error amplifier (EA)520, a buffer (BUF)535, a pass element530including a power transistor531and a feedback circuit (FC)550.

InFIG.7, a load540and a load capacitor CL which are connected between an output node NO and the ground voltage VSS are also illustrated. The load capacitor CL is connected between the output node NO and the ground voltage VSS in parallel with respect to the load capacitor CL. The load540may include a load resistor RL.

The error amplifier520may be connected between the first operating voltage VOP1and the ground voltage VSS, may receive a reference voltage VREF and a feedback voltage VFB, may compare the reference voltage VREF and the feedback voltage VFB, may amplify a difference between the reference voltage VREF and the feedback voltage VFB based on the comparison to generate a first error voltage EV1corresponding to the difference, and may output the first error voltage EV1to the buffer535.

The first error voltage EV1may correspond to the difference between the reference voltage VREF and the feedback voltage VFB. The error amplifier520has a positive (+) input terminal to receive the reference voltage VREF and a negative (−) input terminal to receive the feedback voltage VFB.

The buffer535may buffer the first error voltage EV1and may output a second error voltage EV2to a gate of the power transistor531. The buffer535may have a gain of −1.

The power transistor531may have a gate receiving the second error voltage EV2, and may regulate the first operating voltage VOP1based on the second error voltage EV2to provide the first output voltage VOUT1to the output node NO. A load current IL corresponding to the first output voltage VOUT1is provided to the load540from the output node NO.

The power transistor531has a source coupled to the first operating voltage VOP1, a gate to receive the second error voltage EV2, and a drain coupled to the output node NO. When the load current IL increases, a level of the first output voltage VOUT1decreases and a level of the first error voltage EV1increases. A level of the second error voltage EV2decreases in response to the level of the first error voltage EV1increasing. When the level of the second error voltage EV2decreases, the level of the first output voltage VOUT1increases.

When the load current IL decreases, the level of the first output voltage VOUT1increases and the level of the first error voltage EV1decreases. The level of the second error voltage EV2increases in response to the level of the first error voltage EV1decreasing. When the level of the second error voltage EV2increases, the level of the first output voltage VOUT1decreases.

Therefore, when the load current IL increases, the level of the second error voltage EV2decreases and when the load current IL decreases, the level of the second error voltage EV2increases.

The feedback circuit550may be connected between the output node NO and the ground voltage VSS, may generate a feedback voltage VFB by dividing the first output voltage VOUT1and may provide the feedback voltage VFB to the error amplifier520.

The feedback circuit550may include a first resistor R1and a variable resistor VR connected in series between the output node NO and the ground voltage VSS. The first resistor R1and the variable resistor VR are connected to each other at a feedback node FN, and the feedback circuit550provides the feedback voltage VFB at the feedback node FN.

The variable resistor VR may provide a resistance value varying based on the sub control code CCD21. When the resistance value of the variable resistor VR is varied based on the sub control code CCD21, a voltage level of the first output voltage VOUT1may be varied. Therefore, the LDO regulator510amay adjust the voltage level of the first output voltage VOUT1based on the sub control code CCD21.

FIG.8is a block diagram illustrating a storage system according to example embodiments.

Referring toFIG.8, a storage system50may include a host100and a storage device200. The host100may include a storage interface140.

The storage device200may be any kind of storage device.

The storage device200may include a storage controller300, a plurality of nonvolatile memory devices400a-400k(where k is an integer greater than two), a power management integrated circuit (PMIC)500, and a host interface240. The host interface240may include a signal connector241and a power connector243. The storage device200may further include a volatile memory device250.

The plurality of nonvolatile memory devices400a-400kmay be used as a storage medium of the storage device200. In some example embodiments, each of the plurality of nonvolatile memory devices400a-400kmay include a flash memory or a vertical NAND memory device. The storage controller300may be coupled to the plurality of nonvolatile memory devices400a-400kthrough a plurality of channels CHG1-CHGk, respectively.

The storage controller300may be configured to receive a request REQ from the host100and communicate data DTA with the host100through the signal connector241. The storage controller300may write the data DTA to the plurality of nonvolatile memory devices400a-400kor read the data DTA from plurality of nonvolatile memory devices400a-400kbased on the request REQ.

The storage controller300may communicate the data DTA with the host100using the volatile memory device250as an input/output buffer. In some example embodiments, the volatile memory device250may include a dynamic random access memory (DRAM).

The PMIC500may be configured to receive a plurality of power supply voltages (i.e., external supply voltages) VES1-VESt from the host100through the power connector243. For example, the power connector243may include a plurality of power lines P1-Pt, and the adaptive power supply circuit500may be configured to receive the plurality of power supply voltages VES1-VESt from the host100through the plurality of power lines P-Pt, respectively. Here, t represents a positive integer greater than one.

The PMIC500may generate at least one first operation voltage VOP1used by the storage controller, at least one second operation voltage VOP2used by the plurality of nonvolatile memory devices400a-400k, and at least one third operation voltage VOP3used by the volatile memory device250based on the plurality of power supply voltages VES1-VESt.

For example, when the PMIC500receives all of the plurality of power supply voltages VES1-VESt from the host100, the PMIC500may generate the at least one first operation voltage VOP1, the at least one second operation voltage VOP2, and the at least one third operation voltage VOP3using all of the plurality of power supply voltages VES1-VESt. Alternatively or additionally, when the PMIC500receives less than all of the plurality of power supply voltages VES1-VESt from the host100, the PMIC500may generate the at least one first operation voltage VOP1, the at least one second operation voltage VOP2, and the at least one third operation voltage VOP3using all of the part (e.g., a portion) of the plurality of power supply voltages VES1-VESt that is received from the host100.

FIG.9is a block diagram illustrating the host inFIG.8according to example embodiments.

Referring toFIG.9, the host100may include a central processing unit (CPU)110, a read-only memory (ROM)120, a main memory130, a storage interface (I/F)140, a user interface (I/F)150and a bus160.

The bus160may refer to a transmission channel via which data is transmitted between the CPU110, the ROM120, the main memory130, the storage interface140and the user interface150of the host100. The ROM120may store various application programs. For example, application programs supporting storage protocols such as Advanced Technology Attachment (ATA), Small Computer System Interface (SCSI), embedded Multi Media Card (eMMC), and/or Unix File System (UFS) protocols are stored.

The main memory130may temporarily store data or programs. The user interface150may be a physical and/or virtual medium for exchanging information between a user and the host device100, a computer program, etc., and includes physical hardware and/or logical software. For example, the user interface150may include an input device for allowing the user to manipulate the host100, and an output device for outputting a result of processing an input of the user.

The CPU110may control overall operations of the host100. The CPU110may generate a command for storing data in the storage device200or a request (or a command) for reading data from the storage device200using an application stored in the ROM120, and transmit the request to the storage device200via the storage interface140.

FIG.10is a block diagram illustrating an example of the storage controller inFIG.8according to example embodiments.

Referring toFIG.10, the storage controller300may include a processor310, an error correction code (ECC) engine320, a static random access memory (SRAM)330, a randomizer335, a ROM340, a host interface (I/F)350, a power controller360, and a nonvolatile memory (NVM) interface (I/F)345, which are connected via a bus305.

The storage controller300may further include a plurality of analog circuits such as a low voltage detector590, a plurality of LDO regulators (LDORs)510a,510b,510c, and510d, an oscillator610, and a reference voltage generator (RVG)570. The storage controller300may further include a power-on reset circuit595and a temperature sensor580.

The processor310controls an overall operation of the storage controller300. The processor310may include a plurality of cores.

The plurality of cores of the processor310may perform control operations associated with the nonvolatile memory devices400a-400k. At least one of the plurality of cores may process a command provided from the host100, at least one of the plurality of cores may perform address mapping and garbage collection using a flash translation layer (FTL), and at least one of the plurality of cores may control the nonvolatile memory devices400a-400kthrough the nonvolatile controller345.

Memory cells of the nonvolatile memory devices400a-400kmay have the physical characteristic that a threshold voltage distribution varies due to causes, such as a program elapsed time, a temperature, program disturbance, read disturbance and etc. For example, data stored at the nonvolatile memory devices400a-400kmay become erroneous due to at least one of the above causes.

The storage controller300utilizes a variety of error correction techniques to correct such errors. For example, the storage controller300may include the ECC engine320. The ECC engine320may correct errors which occur in the data stored in the nonvolatile memory devices400a-400k.

The ROM340stores a variety of information, needed for the storage controller300to operate, in firmware, etc. The SRAM330may store data provided from the nonvolatile memory devices400a-400k.

The randomizer335randomizes data to be stored in the nonvolatile memory devices400a-400k. For example, the randomizer335may randomize data to be stored in the nonvolatile memory devices400a-400kin a unit of a word-line.

Data randomizing may refer to processing data such that program states of memory cells connected to a word-line have the same ratio.

For example, if memory cells connected to one word-line are multi-level cells (MLC) each storing 2-bit data, each of the memory cells has one of an erase state and first through third program states.

In this case, the randomizer335randomizes data such that in memory cells connected to one word-line, the number of memory cells having the erase state, the number of memory cells having the first program state, the number of memory cells having the second program state, and the number of memory cells having the third program state are substantially the same as one another. For example, memory cells in which randomized data is stored may have program states of which the number is equal to one another.

The randomizer335de-randomizes data read from the nonvolatile memory devices400a-400k.

The host interface350may perform interfacing between the host100and the nonvolatile memory devices400a-400k.

The power controller360may select one of a plurality of initializing modes based on information of the host100, and may perform a power throttling to adjust power level consumed in the initializing operation associated with the selected initializing mode.

The nonvolatile memory interface345may control the nonvolatile memory devices400a-400kbased on the request REQ.

The low voltage detector590may receive the first operating voltage VOP1from the PMIC500, may generate a reset flag RFG in response to a voltage level of the first operating voltage VOP1being smaller than a reference level and may provide the reset flag RFG to the power-on reset circuit595. The low voltage detector590may adjust the reference level in response to the first control code CCD1.

The power-on reset circuit595may reset the low voltage detector (LVD)590, the LDO regulators510a,510b,510c, and510d, the oscillator610, and the reference voltage generator570, in response to the reset flag RFG.

The LDO regulators510a,510b,510c, and510dmay regulate the first operating voltage VOP1based on at least one reference voltage VREF to generate the plurality of output voltages VOUT1, VOUT2, VOUT3, and VOUT4. Each of the LDO regulators510a,510b,510c, and510dmay adjust a level of a respective one of the output voltages VOUT1, VOUT2, VOUT3, and VOUT4based on respective one of sub control codes CCD21, CCD22, CCD23, and CCD24included in a second control code CCD2.

The oscillator610may generate the reference clock signal RCLK associated with an operating frequency of the processor310based on one VOUT1of the plurality of output voltages VOUT1, VOUT2, VOUT3, and VOUT4. The oscillator610may adjust a frequency of the reference clock signal RCLK based on a third control code CCD3.

The reference voltage generator570may generate the at least one reference voltage VREF and may provide the at least one reference voltage VREF to the LDO regulators510a,510b,510c, and510d. The reference voltage generator570may adjust a level of the at least one reference voltage VREF based on a fourth control code CCD4. The reference voltage generator570may have a configuration similar with the feedback circuit550inFIG.7.

FIG.11illustrates an example of the power controller in the storage controller ofFIG.10according to example embodiments.

Referring toFIG.11, the power controller360may include a control logic361, a power throttling look-up table (LUT)370, a clock generator380, and a selection circuit390.

The clock generator380may include phase-locked loop (PLL) circuits381and383, and the selection circuit390may include multiplexers391,392,393, and394.

InFIG.11, the processor310including a plurality of cores311,312, and313and the nonvolatile memory interface345are also illustrated for convenience of explanation.

The core311may process a request provided from the host100, the core312may perform address mapping and garbage collection using FTL, and the core313may control the nonvolatile memory devices400a-400kthrough the nonvolatile memory interface345.

The control logic361may access the power throttling LUT370based on host connection information HCI indicating that the storage controller300is connected to the host100, and may generate selection signals SS1, SS2, SS3, and SS4by referring to a corresponding power target in the power throttling LUT370.

The power throttling LUT370may store information on power targets associated with a plurality of initializing modes. In example embodiments, the power throttling LUT370may store information on frequencies of clock signals provided to the cores311,312, and313, the system bus305, and the nonvolatile controller345in each of the plurality of initializing modes.

The PLL circuit381may generate a base clock signal CLK1having a first frequency and divided clock signals CLKD11and CLKD12by dividing the base clock signal CLK1based on the reference clock signal RCLK.

The PLL circuit383may generate a base clock signal CLK2having a second frequency and divided clock signals CLKD21and CLKD22by dividing the base clock signal CLK2based on the reference clock signal RCLK.

The multiplexer391selects one of the base clock signal CLK1and the divided clock signals CLKD11and CLKD12as a first selected clock signal SCLK1in response to a first selection signal SS1and provides the first selected clock signal SCLK1to the cores311and313.

The multiplexer392selects one of the base clock signal CLK1and the divided clock signals CLKD11and CLKD12as a second selected clock signal SCLK2in response to a second selection signal SS2and provides the second selected clock signal SCLK2to the system bus305.

The multiplexer393selects one of the base clock signal CLK2and the divided clock signals CLKD21and CLKD22as a third selected clock signal SCLK3in response to a third selection signal SS3and provides the third selected clock signal SCLK3to the core312.

The multiplexer394selects one of the base clock signal CLK2and the divided clock signals CLKD21and CLKD22as a fourth selected clock signal SCLK4in response to a fourth selection signal SS4and provides the fourth selected clock signal SCLK4to the nonvolatile controller345.

FIG.12illustrates an example of a power-up sequence of the storage device ofFIG.8according to example embodiments.

Referring toFIG.12, during a power-up sequence in which power is initially applied to the storage device200or the power is applied again to the storage device200, the storage controller300operates at a first speed to read a compensation data set CDS stored in a first region421of the nonvolatile memory device400aand stores the compensation data set CDS in the SRAM330in the storage controller300as reference numeral671indicates. The SRAM330may belong to a power-on domain PON_D to which power is provided in a power saving state and in a hibernate state of the storage controller300.

The storage controller300operates at a second speed faster than the first speed to compensate for offsets of outputs of the plurality of analog circuits such as the low voltage detector590, the plurality of LDO regulators510a,510b,510c, and510d, the oscillator610, and the reference voltage generator570, based on the compensation data set CDS stored in the SRAM330.

The first region421of the nonvolatile memory device400amay include a main region422to store the compensation data set CDS and a replica block423to store a copied version CDS_C of the compensation data set CDS. The first region421may correspond to a single-level cell (SLC) block including a plurality of SLCs.

FIG.13illustrates an example of a power-up sequence of the storage device ofFIG.8according to example embodiments.

Referring toFIG.13, during a power-up sequence in which power is initially applied to the storage device200or the power is applied again to the storage device200, the storage controller300operates at a first speed to read a compensation data set CDS stored in a first region421of the nonvolatile memory device400aand provides the compensation data set CDS to the ECC engine320in the storage controller300as reference numeral681indicates.

The ECC engine320performs an ECC decoding on the compensation data set CDS, detects at least one error in the compensation data set CDS, corrects correctable error in the compensation data set CDS, and provides the compensation data set CDS to the SRAM as reference numeral683indicates.

In response to the engine320detecting uncorrectable errors in the compensation data set CDS, the storage controller300operates at the first speed to read a copied version CDS_C of the compensation data set in the replica block423and provides the copied version CDS_C of the compensation data set to the ECC engine320as reference numeral685indicates.

The ECC engine320performs an ECC decoding on the copied version CDS_C of the compensation data set, detects at least one error in the copied version CDS_C of the compensation data set, corrects correctable error in the copied version CDS_C of the compensation data set, and provides the copied version CDS_C of the compensation data set to the SRAM as reference numeral687indicates.

The SRAM330and the ECC engine320may belong to a power-on domain PON_D to which power is provided in a power saving state and in a hibernate state of the storage controller300.

The storage controller300operates at a second speed faster than the first speed to compensate for offsets of outputs of the plurality of analog circuits such as the low voltage detector590, the plurality of LDO regulators510a,510b,510c, and510d, the oscillator610, and the reference voltage generator570based on the compensation data set CDS or the copied version CDS_C of the compensation data set stored in the SRAM330.

FIG.14is a block diagram illustrating a connection relationship between the storage controller and one nonvolatile memory device in the storage device ofFIG.8.

Referring toFIG.14, the nonvolatile memory device400amay perform an erase operation, a program operation, and/or a write operation under control of the storage controller300. The nonvolatile memory device400amay receive a command CMD, an address ADDR, and (user) data DTA through input/output lines from the storage controller300for performing such operations.

In addition, the nonvolatile memory device411may receive a control signal CTRL through a control line and receive power PWR through a power line from the storage controller300. In addition, the nonvolatile memory device411may provide a status signal RnB to the storage controller300through the control line.

FIG.15is a block diagram illustrating the nonvolatile memory device inFIG.14according to some example embodiments.

Referring toFIG.15, the nonvolatile memory device400aincludes a memory cell array420, an address decoder450, a page buffer circuit430, a data input/output circuit440, a control circuit460, and a voltage generator470.

The memory cell array420may be coupled to the address decoder450through a string selection line SSL, a plurality of word-lines WLs, and a ground selection line GSL. In addition, the memory cell array420may be coupled to the page buffer circuit430through a plurality of bit-lines BLs.

The memory cell array420may include a plurality of memory cells coupled to the plurality of word-lines WLs and the plurality of bit-lines BLs.

In some example embodiments, the memory cell array420may be or may include a three-dimensional memory cell array, which is formed on a substrate in a three-dimensional structure (e.g., a vertical structure). In such a case, the memory cell array420may include vertical cell strings that are vertically oriented such that at least one memory cell is located over another memory cell.

FIG.16is a block diagram illustrating the memory cell array in the nonvolatile memory device ofFIG.15.

Referring toFIG.16, the memory cell array420may include a plurality of memory blocks BLK1to BLKz. The memory blocks BLK1to BLKz extend along a first horizontal direction EED1, a second horizontal direction HD2and a vertical direction VD. In some example embodiments, the memory blocks BLK1to BLKz are selected by the address decoder450inFIG.15. For example, the address decoder450may select a memory block BLK corresponding to a block address among the memory blocks BLK1to BLKz.

FIG.17is a circuit diagram illustrating one of the memory blocks ofFIG.16.

The memory block BLKi ofFIG.17may be formed on a substrate SUB in a three-dimensional structure (or a vertical structure). For example, a plurality of memory cell strings included in the memory block BLKi may be formed in a direction VD perpendicular to the substrate SUB.

Referring toFIG.17, the memory block BLKi may include memory cell strings NS11to NS33coupled between bit-lines BL1, BL2and BL3and a common source line CSL. Each of the memory cell strings NS11to NS33may include a string selection transistor SST, a plurality of memory cells MC1to MC8, and a ground selection transistor GST. InFIG.17, each of the memory cell strings NS11to NS33is illustrated to include eight memory cells MC1to MC8. However, inventive concepts are not limited thereto. In some example embodiments, each of the memory cell strings NS11to NS33may include any number of memory cells.

The string selection transistor SST may be connected to corresponding string selection lines SSL1to SSL3. The plurality of memory cells MC1to MC8may be connected to corresponding word-lines WL1to WL8, respectively. The ground selection transistor GST may be connected to corresponding ground selection lines GSL1to GSL3. The string selection transistor SST may be connected to corresponding bit-lines BL1, BL2and BL3, and the ground selection transistor GST may be connected to the common source line CSL.

Word-lines (e.g., WL1-WL8) having the same height may be commonly connected, and the ground selection lines GSL1to GSL3and the string selection lines SSL1to SSL3may be separated. InFIG.17, the memory block BLKi is illustrated to be coupled to eight word-lines WL1to WL8and three bit-lines BL1to BL3. However, inventive concepts are not limited thereto. In some example embodiments, the memory cell array420may be coupled to any number of word-lines and bit-lines.

FIG.18illustrates an example of a structure of a cell string (CS) in the memory block ofFIG.17.

Referring toFIGS.17and18, a pillar PL is provided on the substrate SUB such that the pillar PL extends in a direction perpendicular to the substrate SUB to make contact with the substrate SUB. Each of the ground selection line GSL, the word lines WL1to WL8, and the string selection lines SSL illustrated inFIG.18may be formed of a conductive material parallel with the substrate SUB, for example, a metallic material. The pillar PL may be in contact with the substrate SUB through the conductive materials forming the string selection lines SSL, the word lines WL1to WL8, and the ground selection line GSL.

A sectional view taken along a line A-A′ is also illustrated inFIG.18. In some example embodiments, a sectional view of a first memory cell MC1corresponding to a first word line WL1is illustrated. The pillar PL may include a cylindrical body BD. An air gap AG may be defined in the interior of the body BD.

The body BD may include P-type silicon and may be an area where a channel will be formed. The pillar PL may further include a cylindrical tunnel insulating layer TI surrounding the body BD and a cylindrical charge trap layer CT surrounding the tunnel insulating layer TI. A blocking insulating layer BI may be provided between the first word line WL and the pillar PL. The body BD, the tunnel insulating layer TI, the charge trap layer CT, the blocking insulating layer BI, and the first word line WL may constitute or be included in a charge trap type transistor that is formed in a direction perpendicular to the substrate SUB or to an upper surface of the substrate SUB. A string selection transistor SST, a ground selection transistor GST, and other memory cells may have the same structure as the first memory cell MC1.

Referring back toFIG.15, the control circuit460may receive the command (signal) CMD and the address (signal) ADDR from the storage controller300, and may control an erase loop, a program loop and/or a read operation of the nonvolatile memory device411based on the command signal CMD and the address signal ADDR. The program loop may include a program operation and a program verification operation. The erase loop may include an erase operation and an erase verification operation.

For example, the control circuit460may generate control signals CTLs, which are used for controlling the voltage generator470, based on the command signal CMD, and generate a row address R_ADDR and a column address C_ADDR based on the address signal ADDR. The control circuit460may provide the row address R_ADDR to the address decoder450and provide the column address C_ADDR to the data input/output circuit440.

The address decoder450may be coupled to the memory cell array420through the string selection line SSL, the plurality of word-lines WLs, and the ground selection line GSL. During the program operation or the read operation, the address decoder450may determine one of the plurality of word-lines WLs as a first word-line (e.g., a selected word-line) and determine the rest of the plurality of word-lines WLs except for the first word-line as unselected word-lines based on the row address R_ADDR.

The voltage generator470may generate word-line voltages VWLs, which are required for the operation of the nonvolatile memory device411, based on the control signals CTLs. The voltage generator470may receive a power PWR from the storage controller300. The word-line voltages VWLs may be applied to the plurality of word-lines WLs through the address decoder450.

For example, during the erase operation, the voltage generator470may apply an erase voltage to a well of the memory block and may apply a ground voltage to entire word-lines of the memory block. During the erase verification operation, the voltage generator470may apply an erase verification voltage to the entire word-lines of the memory block or sequentially apply the erase verification voltage to word-lines in a word-line basis.

For example, during the program operation, the voltage generator470may apply a program voltage to the first word-line and may apply a program pass voltage to the unselected word-lines. In addition, during the program verification operation, the voltage generator470may apply a program verification voltage to the first word-line and may apply a verification pass voltage to the unselected word-lines.

Furthermore, during the read operation, the voltage generator470may apply a read voltage to the first word-line and may apply a read pass voltage to the unselected word-lines.

The page buffer circuit430may be coupled to the memory cell array420through the plurality of bit-lines BLs. The page buffer circuit430may include a plurality of page buffers. In some example embodiments, one page buffer may be connected to one bit-line. In some example embodiments, one page buffer may be connected to two or more bit-lines.

The page buffer circuit430may temporarily store data to be programmed in a selected page or data read out from the selected page.

The data input/output circuit440may be coupled to the page buffer circuit430through data lines DLs. During the program operation, the data input/output circuit440may receive the data DTA from the storage controller300or the compensation data set CDS and provide the data DTA and the compensation data set CDS to the page buffer circuit430based on the column address C_ADDR received from the control circuit460.

During the read operation, the data input/output circuit440may provide the data DTA or the compensation data set CDS, which are stored in the page buffer circuit430, to the storage controller300based on the column address C_ADDR received from the control circuit460.

In addition, the page buffer circuit430and the data input/output circuit440read data from a first area of the memory cell array420and write the read data to a second area of the memory cell array420. For example, the page buffer circuit430and the data input/output circuit440may perform a copy-back operation. The control circuit460may control the page buffer circuit430and data I/O circuit440.

The control circuit460may include a status signal generator465and the status signal generator465may generate the status signal RnB indicating whether each of the program operation, the erase operation and the read operation is completed or and/or is in progress.

The storage controller300may determine idle state or busy state of each of the nonvolatile memory devices400a-400kbased on the status signal RnB.

FIG.19is a block diagram illustrating an example of the memory cell array in the nonvolatile memory device ofFIG.15according to example embodiments.

Referring toFIG.19, the memory cell array420may include a first region421and a second region425. The first region421may correspond to a SLC block including a plurality of SLCs and the second region425may correspond to a triple-level cell (TLC) block including a plurality of TLCs or a quadruple-level cell (QLC) block including a plurality of QLCs.

The first region421may include a main region422to store the compensation data set CDS and a replica block to store a copied version CDS_C of the compensation data set CDS. The compensation data set CDS may include trimming control codes TCCD1, TCCD2, TCCD3and TCCD4associated with control codes to render the low voltage detector590, the LDO regulators510a,510b,510c, and510d, the oscillator610, and the reference voltage generator570to provide corresponding outputs having target levels, respectively.

The main region may further include specific information ECID of the storage controller300, associated with fabricating the storage controller300, and the replica block may further include a copied version ECID_C of the specific information ECID. The specific information ECID may include information associated with generation of the storage controller300and location information indicating a location of a die in the wafer, in which the storage controller300is fabricated. The storage controller300may adjust the offsets of the analog circuits further based on the specific information ECID.

The control circuit460inFIG.15may program the compensation data set CDS and the specific information ECID in the first region421by unit of a page in a fabrication process of the nonvolatile memory device400a.

FIG.20illustrates signals exchanged between a storage interface of the host and a host interface in the storage device inFIG.8.

InFIG.20, a storage interface140aof the host100and a host interface240ain the storage device200may be referred to as a first interface circuit and a second interface circuit, respectively, and may include a physical layer M-PHY and a UniPro corresponding to interface protocols suggested by Mobile Industry Processor Interface (MIPI) Alliance. The physical layer M-PHY of the first interface circuit140amay include a pair of lines for transferring a differential input signal pair DIN_t and DIN_c, a pair of lines for transferring a differential output signal pair DOUT_t and DOUT_c and a line for transferring a reference clock signal REF_CLK.

The physical layer M-PHY of the first interface circuit140amay transfer signals to the second interface circuit240athrough the output terminals DOUT_t and DOUT_c. The output terminals DOUT_t and DOUT_c may constitute a transmit channel M-TX of the first interface circuit140a. For example, the signals that are transferred through the output terminals DOUT_t and DOUT_c may be a pair of differential signals. That is, a signal that is transferred through the output terminal DOUT_c may be complementary to a signal that is transferred through the output terminal DOUT_t.

The physical layer M-PHY of the first interface circuit140amay receive signals from the second interface circuit240athrough the input terminals DIN_t and DIN_c. The input terminals DIN_t and DIN_c may constitute a receive channel M-RX of the first interface circuit140a. For example, the signals that are received through the input terminals DIN_t and DIN_c may be a pair of differential signals. That is, a signal that is received through the input terminal DIN_c may be complementary to a signal that is received through the input terminal DIN_t.

The output terminals DOUT_t and DOUT_c and the input terminals DIN_t and DIN_c may be controlled to one of various states in compliance with a given protocol. For example, each of the output terminals DOUT_t and DOUT_c and the input terminals DIN_t and DIN_c may be controlled to a positive state DIF-P, a negative state DIF-N, a ground state DIF-Z, or a floating state DIF-Q.

When a level (e.g., a voltage level) of an output signal of the first output terminal DOUT_t is higher than a level of an output signal of the second output terminal DOUT_c, the output terminals DOUT_t and DOUT_c may be at the positive state DIF-P. When the level of the output signal of the first output terminal DOUT_t is lower than the level of the output signal of the second output terminal DOUT_c, the output terminals DOUT_t and DOUT_c may be at the negative state DIF-N. When the first output terminal DOUT_t and the second output terminal DOUT_c are floated, the output terminals DOUT_t and DOUT_c may be at the floating state DIF-Q. When the levels of the first output terminal DOUT_t and the second output terminal DOUT_c are equal, the output terminals DOUT_t and DOUT_c may be at the ground state DIF-Z.

When a level of an input signal of the first input terminal DIN_t is higher than a level of an input signal of the second input terminal DIN_c, the input terminals DIN_t and DIN_c may be at the positive state DIF-P. When the level of the input signal of the first input terminal DIN_t is lower than the level of the input signal of the second input terminal DIN_c, the input terminals DIN_t and DIN_c may be at the negative state DIF-N. When the first input terminal DIN_t and the second input terminal DIN_c are connected with terminals of a ground state, the input terminals DIN_t and DIN_c may be at the ground state DIF-Z. When the first input terminal DIN_t and the second input terminal DIN_c are floated, the input terminals DIN_t and DIN_c may be at the floating state DIF-Q.

The second interface circuit240amay include input terminals DIN_t and DIN_c, output terminals DOUT_t and DOUT_c, and a clock terminal REF_CLK.

The output terminals DOUT_t and DOUT_c of the second interface circuit240amay correspond to the input terminals DIN_t and DIN_c of the first interface circuit140a, and the input terminals DIN_t and DIN_c of the second interface circuit240amay correspond to the output terminals DOUT_t and DOUT_c of the first interface circuit140a.

A physical layer M-PHY of the second interface circuit240amay receive signals through the input terminals DIN_t and DIN_c and may transfer signals through the output terminals DOUT_t and DOUT_c. As in the above description given with reference to the first interface circuit140a, the output terminals DOUT_t and DOUT_c and the input terminals DIN_t and DIN_c of the second interface circuit240amay be controlled to the positive state DIF-P, the negative state DIF-N, the ground state DIF-Z, or the floating state DIF-Q.

Meanwhile, according to the MIPI M-PHY specification, the physical layer M-PHY of the second interface circuit240amay a reference clock detector245. The reference clock detector245may detect a change between the idle mode and the active mode of the storage device200.

When the storage device200does not execute any operation, the storage device200may be in a first idle mode or a second idle mode. When storage device200is in the first idle mode or the second idle mode, the first interface circuit140amay not transfer the reference clock REF_CLK to the second interface circuit240a. When the storage device200switches from the first idle mode and/or the second idle mode to the active mode, the input terminals DIN_t and DIN_c of the second interface circuit240amay switch from the floating state DIF-Q to the negative state DIF-N. When the storage device200switches from the first idle mode and/or the second idle mode to the active mode, the first interface circuit140amay resume a transfer of the reference clock REF_CLK to the second interface circuit240a.

In an example embodiment, when the storage device200is in the second idle mode, the reference clock detector245may generate the trigger signal allowing the storage device200to enter the active mode, based on toggling of the reference clock REF_CLK.

FIGS.21A and21Billustrate state machines of the first interface circuit and the second interface circuit inFIG.20.

In detail,FIG.21Aillustrates a state machine of the output terminal M-TX of the first interface circuit140a, andFIG.21Billustrates a state machine of the input terminal M-RX of the second interface circuit240a. For example, the state machines ofFIGS.21A and21Bmay be associated with a Type-I module defined in the M-PHY protocol.

Referring toFIGS.20,21A, and21B, the M-PHY protocol defines a high speed mode HS-MODE and a low speed mode LS-MODE of the second interface circuit240a. Each of the high speed mode HS-MODE and the low speed mode LS-MODE may include a burst data transmission mode and a power saving state. In addition, the M-PHY protocol defines a hibernate state HIBERN8 being an ultra-low power state. The power saving state of the high speed mode HS-MODE may be the stall state STALL, and the power saving state of the low speed mode LS-MODE may be the sleep state SLEEP.

For example, the sleep state SLEEP and the stall state STALL ofFIGS.21A and21Bmay correspond to the active mode described with reference toFIG.20, and the hibernate state HIBERN8 may correspond to the idle mode described with reference toFIG.20.

The storage device200may perform a mode switch even between the sleep state SLEEP or the stall state STALL being the power saving state and the hibernate state HIBERN8 being the ultra-low power state. For example, in the hibernate state HIBERN8, a power supply voltage may not be supplied to at least some components of the second interface circuit240a. However, in the hibernate state HIBERN8, a power supply voltage may be supplied to some components of the second interface circuit240a. That is, the hibernate state HIBERN8 may be a state in which the Unipro link startup sequence for a physical connection between the first interface circuit140aand the second interface circuit240ais not required.

As illustrated, in the case where the second interface circuit240ais in the hibernate state HIBERN8, the host100may not provide the reference clock REF_CLK to the storage device200. In the case where the second interface circuit240ais in the sleep state SLEEP or the stall state STALL, the host100may provide the reference clock REF_CLK to the storage device200.

In the case where the second interface circuit240ais in the hibernate state HIBERN8, the reference clock detector245may detect toggling of the reference clock REF_CLK received from the first interface circuit140aand may generate a trigger signal for allowing the storage device200to enter the active mode based on a result of the detection.

Even when the second interface circuit240ais in the power saving state or in the hibernate state, the PMIC500provides the first operating voltage VOP1to the SRAM330inFIG.12orFIG.13, the storage controller300may adjust the offsets of the analog circuits based on the compensation data set CDS stored in the SRAM330.

FIG.22is a flow chart illustrating a method of operating a storage device according to example embodiments.

Referring toFIGS.2,8,12,13and22, there is provided a method of operating a storage device200which includes at least one nonvolatile memory device400aincluding a first region and a second region and a storage controller200to control the at least one nonvolatile memory device400a.

According to the method, the storage controller200operates at a first speed to read trimming control codes that compensate for offsets of analog circuits as compensation data set CDS from a first region421of the at least one nonvolatile memory device400aduring a power-up sequence of the storage device200(operation S410). The trimming control codes are obtained by the ATE40during a wafer-level test on the storage controller300and are stored in the first region421.

The storage controller300stores the read compensation data set CDS in an SRAM330included in the storage controller300(operation S430). The storage controller300operates at a second speed faster than the first speed to adjust offsets of the analog circuits based on the compensation data set CDS stored in the SRAM330(operation S450).

FIG.23is a cross-sectional view of a nonvolatile memory device according to example embodiments.

Referring toFIG.23, a nonvolatile memory device2000(the nonvolatile memory device2000may be also referred to as a memory device) may have a chip-to-chip (C2C) structure. The C2C structure may refer to a structure formed by manufacturing an upper chip including a memory cell region or a cell region CELL on a first wafer, manufacturing a lower chip including a peripheral circuit region PERI on a second wafer, separate from the first wafer, and then bonding the upper chip and the lower chip to each other. Here, the bonding process may include a method of electrically connecting a bonding metal formed on an uppermost metal layer of the upper chip and a bonding metal formed on an uppermost metal layer of the lower chip. For example, when the bonding metals may include copper (Cu) using a Cu-to-Cu bonding. The example embodiment, however, may not be limited thereto. For example, the bonding metals may also be formed of aluminum (Al) or tungsten (W).

Each of the peripheral circuit region PERI and the cell region CELL of the memory device2000may include an external pad bonding area PA, a word-line bonding area WLBA, and a bit-line bonding area BLBA.

The peripheral circuit region PERI may include a first substrate2210, an interlayer insulating layer2215, a plurality of circuit elements2220a,2220b, and2220cformed on the first substrate2210, first metal layers2230a,2230b, and2230crespectively connected to the plurality of circuit elements2220a,2220b, and2220c, and second metal layers2240a,2240b, and2240cformed on the first metal layers2230a,2230b, and2230c. In an example embodiment, the first metal layers2230a,2230b, and2230cmay be formed of tungsten having relatively high electrical resistivity, and the second metal layers2240a,2240b, and2240cmay be formed of copper having relatively low electrical resistivity.

In an example embodiment illustrated inFIG.23, although only the first metal layers2230a,2230b, and2230cand the second metal layers2240a,2240b, and2240care shown and described, the example embodiment is not limited thereto, and one or more additional metal layers may be further formed on the second metal layers2240a,2240b, and2240c. At least a portion of the one or more additional metal layers formed on the second metal layers2240a,2240b, and2240cmay be formed of aluminum or the like having a lower electrical resistivity than those of copper forming the second metal layers2240a,2240b, and2240c.

The interlayer insulating layer2215may be disposed on the first substrate2210and cover the plurality of circuit elements2220a,2220b, and2220c, the first metal layers2230a,2230b, and2230c, and the second metal layers2240a,2240b, and2240c. The interlayer insulating layer2215may include an insulating material such as silicon oxide, silicon nitride, or the like.

Lower bonding metals2271band2272bmay be formed on the second metal layer2240bin the word-line bonding area WLBA. In the word-line bonding area WLBA, the lower bonding metals2271band2272bin the peripheral circuit region PERI may be electrically bonded to upper bonding metals2371band2372bof the cell region CELL. The lower bonding metals2271band2272band the upper bonding metals2371band2372bmay be formed of aluminum, copper, tungsten, or the like. Further, the upper bonding metals2371band2372bin the cell region CELL may be referred as first metal pads and the lower bonding metals2271band2272bin the peripheral circuit region PERI may be referred as second metal pads.

The cell region CELL may include at least one memory block. The least one memory block may include a first region and a second region. The first region may store compensation data set and may correspond to SLC block. The cell region CELL may include a second substrate2310and a common source line2320. On the second substrate2310, a plurality of word-lines2331,2332,2333,2334,2335,2336,2337, and2338(e.g.,2330) may be stacked in a vertical direction VD (e.g., a Z-axis direction), perpendicular to an upper surface of the second substrate2310. At least one string selection line and at least one ground selection line may be arranged on and below the plurality of word-lines2330, respectively, and the plurality of word-lines2330may be disposed between the at least one string selection line and the at least one ground selection line.

In the bit-line bonding area BLBA, a channel structure CH may extend in the vertical direction VD, perpendicular to the upper surface of the second substrate2310, and pass through the plurality of word-lines2330, the at least one string selection line, and the at least one ground selection line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, and the like, and the channel layer may be electrically connected to a first metal layer2350cand a second metal layer2360c. For example, the first metal layer2350cmay be a bit-line contact, and the second metal layer2360cmay be a bit-line. In an example embodiment, the bit-line2360cmay extend in a second horizontal direction HD2(e.g., a Y-axis direction), parallel to the upper surface of the second substrate2310.

In an example embodiment illustrated inFIG.23, an area in which the channel structure CH, the bit-line2360c, and the like are disposed may be defined as the bit-line bonding area BLBA. In the bit-line bonding area BLBA, the bit-line2360cmay be electrically connected to the circuit elements2220cproviding a page buffer2393in the peripheral circuit region PERI. The bit-line2360cmay be connected to upper bonding metals2371cand2372cin the cell region CELL, and the upper bonding metals2371cand2372cmay be connected to lower bonding metals2271cand2272cconnected to the circuit elements2220cof the page buffer2393.

In the word-line bonding area WLBA, the plurality of word-lines2330may extend in a first horizontal direction HD1(e.g., an X-axis direction), parallel to the upper surface of the second substrate2310and perpendicular to the second horizontal direction HD2, and may be connected to a plurality of cell contact plugs2341,2342,2343,2344,2345,2346, and2347(i.e.,2340). The plurality of word-lines2330and the plurality of cell contact plugs2340may be connected to each other in pads provided by at least a portion of the plurality of word-lines2330extending in different lengths in the first horizontal direction HD1. A first metal layer2350band a second metal layer2360bmay be connected to an upper portion of the plurality of cell contact plugs2340connected to the plurality of word-lines2330, sequentially. The plurality of cell contact plugs2340may be connected to the peripheral circuit region PERI by the upper bonding metals2371band2372bof the cell region CELL and the lower bonding metals2271band2272bof the peripheral circuit region PERI in the word-line bonding area WLBA.

The plurality of cell contact plugs2340may be electrically connected to the circuit elements2220bforming an address decoder2394in the peripheral circuit region PERI. In an example embodiment, operating voltages of the circuit elements2220bforming the address decoder2394may be different than operating voltages of the circuit elements2220cforming the page buffer circuit2393. For example, operating voltages of the circuit elements2220cforming the page buffer circuit2393may be greater than operating voltages of the circuit elements2220bforming the row decoder2394.

A common source line contact plug2380may be disposed in the external pad bonding area PA. The common source line contact plug2380may be formed of a conductive material such as a metal, a metal compound, polysilicon, or the like, and may be electrically connected to the common source line2320. A first metal layer2350aand a second metal layer2360amay be stacked on an upper portion of the common source line contact plug2380, sequentially. For example, an area in which the common source line contact plug2380, the first metal layer2350a, and the second metal layer2360aare disposed may be defined as the external pad bonding area PA.

Input/output pads2205and2305may be disposed in the external pad bonding area PA. A lower insulating film2201covering a lower surface of the first substrate2210may be formed below the first substrate2210, and a first input/output pad2205may be formed on the lower insulating film2201. The first input/output pad2205may be connected to at least one of the plurality of circuit elements2220a,2220b, and2220cdisposed in the peripheral circuit region PERI through a first input/output contact plug2203, and may be separated from the first substrate2210by the lower insulating film2201. In addition, a side insulating film may be disposed between the first input/output contact plug2203and the first substrate2210to electrically separate the first input/output contact plug2203and the first substrate2210.

An upper insulating film2301covering the upper surface of the second substrate2310may be formed on the second substrate2310and a second input/output pad2305may be disposed on the upper insulating layer2301. The second input/output pad2305may be connected to at least one of the plurality of circuit elements2220a,2220b, and2220cdisposed in the peripheral circuit region PERI through a second input/output contact plug2303. In the example embodiment, the second input/output pad2305is electrically connected to a circuit element2220a.

According to embodiments, the second substrate2310and the common source line2320may not be disposed in an area in which the second input/output contact plug2303is disposed. Also, the second input/output pad2305may not overlap the word-lines2330in the vertical direction HD. The second input/output contact plug2303may be separated from the second substrate2310in the direction, parallel to the upper surface of the second substrate310, and may pass through the interlayer insulating layer2315of the cell region CELL to be connected to the second input/output pad2305.

According to embodiments, the first input/output pad2205and the second input/output pad2305may be selectively formed. For example, the memory device2000may include only the first input/output pad2205disposed on the first substrate2210or the second input/output pad2305disposed on the second substrate2310. Alternatively, the memory device200may include both the first input/output pad2205and the second input/output pad2305.

A metal pattern provided on an uppermost metal layer may be provided as a dummy pattern or the uppermost metal layer may be absent, in each of the external pad bonding area PA and the bit-line bonding area BLBA, respectively included in the cell region CELL and the peripheral circuit region PERI.

In the external pad bonding area PA, the memory device2000may include a lower metal pattern2273a, corresponding to an upper metal pattern2372aformed in an uppermost metal layer of the cell region CELL, and having the same cross-sectional shape as the upper metal pattern2372aof the cell region CELL so as to be connected to each other, in an uppermost metal layer of the peripheral circuit region PERI. In the external pad bonding area PA, the memory device2000may include lower bonding metals2271aand2271bconnected to the lower metal pattern2273a. In the peripheral circuit region PERI, the lower metal pattern2273aformed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact. Similarly, in the external pad bonding area PA, an upper metal pattern2372a, corresponding to the lower metal pattern2273aformed in an uppermost metal layer of the peripheral circuit region PERI, and having the same shape as a lower metal pattern2273aof the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL. Similarly, in the external pad bonding area PA, an upper bonding metal2371amay be formed and may be electrically connected to the upper metal pattern2372a.

The lower bonding metals2271band2272bmay be formed on the second metal layer2240bin the word-line bonding area WLBA. In the word-line bonding area WLBA, the lower bonding metals2271band2272bof the peripheral circuit region PERI may be electrically connected to the upper bonding metals2371band2372bof the cell region CELL by a Cu-to-Cu bonding.

Further, in the bit-line bonding area BLBA, an upper metal pattern2392, corresponding to a lower metal pattern2252formed in the uppermost metal layer of the peripheral circuit region PERI, and having the same cross-sectional shape as the lower metal pattern2252of the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL. A contact may not be formed on the upper metal pattern2392formed in the uppermost metal layer of the cell region CELL.

In an example embodiment, corresponding to a metal pattern formed in an uppermost metal layer in one of the cell region CELL and the peripheral circuit region PERI, a reinforcement metal pattern having the same cross-sectional shape as the metal pattern may be formed in an uppermost metal layer in the other one of the cell region CELL and the peripheral circuit region PERI. A contact may not be formed on the reinforcement metal pattern.

The word-line voltages may be applied to at least one memory block in the cell region CELL through the lower bonding metals2271band2272bin the peripheral circuit region PERI and upper bonding metals2371band2372bof the cell region CELL.

FIG.24is a block diagram illustrating an electronic system including a semiconductor device according to example embodiments.

Referring toFIG.24, an electronic system3000may include a semiconductor device3100and a controller3200electrically connected to the semiconductor device3100. The electronic system3000may be a storage device including one or a plurality of semiconductor devices3100or an electronic device including a storage device. For example, the electronic system3000may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device that may include one or a plurality of semiconductor devices3100.

The semiconductor device3100may be a non-volatile memory device, for example, a NAND flash memory device that will be illustrated with reference toFIGS.6to21. The semiconductor device3100may include a first structure3100F and a second structure3100S on the first structure3100F. The first structure3100F may be a peripheral circuit structure including a decoder circuit3110, a page buffer circuit3120, and a logic circuit3130. The second structure3100S may be a memory cell structure including a bit-line BL, a common source line CSL, word-lines WL, first and second upper gate lines UL1and UL2, first and second lower gate lines LL1and LL2, and memory cell strings CSTR between the bit line BL and the common source line CSL.

In the second structure3100S, each of the memory cell strings CSTR may include lower transistors LT1and LT2adjacent to the common source line CSL, upper transistors UT1and UT2adjacent to the bit-line BL, and a plurality of memory cell transistors MCT between the lower transistors LT1and LT2and the upper transistors UT1and UT2. The number of the lower transistors LT1and LT2and the number of the upper transistors UT1and UT2may be varied in accordance with example embodiments.

In example embodiments, the upper transistors UT1and UT2may include string selection transistors, and the lower transistors LT1and LT2may include ground selection transistors. The lower gate lines LL1and LL2may be gate electrodes of the lower transistors LT1and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, respectively, and the upper gate lines UL1and UL2may be gate electrodes of the upper transistors UT1and UT2, respectively.

In example embodiments, the lower transistors LT1and LT2may include a lower erase control transistor LT1and a ground selection transistor LT2that may be connected with each other in serial. The upper transistors UT1and UT2may include a string selection transistor UT1and an upper erase control transistor UT2. At least one of the lower erase control transistor LT1and the upper erase control transistor UT2may be used in an erase operation for erasing data stored in the memory cell transistors MCT through gate induced drain leakage (GIDL) phenomenon.

The common source line CSL, the first and second lower gate lines LL1and LL2, the word lines WL, and the first and second upper gate lines UL1and UL2may be electrically connected to the decoder circuit3110through first connection wirings1115extending to the second structure3110S in the first structure3100F. The bit-lines BL may be electrically connected to the page buffer circuit3120through second connection wirings3125extending to the second structure3100S in the first structure3100F.

In the first structure3100F, the decoder circuit3110and the page buffer circuit3120may perform a control operation for at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit3110and the page buffer circuit3120may be controlled by the logic circuit3130. The semiconductor device3100may communicate with the controller3200through an input/output pad3101electrically connected to the logic circuit3130. The input/output pad3101may be electrically connected to the logic circuit3130through an input/output connection wiring3135extending to the second structure3100S in the first structure3100F.

The controller3200may include a processor3210, a NAND controller3220, and a host interface3230. The electronic system3000may include a plurality of semiconductor devices3100, and in this case, the controller3200may control the plurality of semiconductor devices3100.

The processor3210may control operations of the electronic system3000including the controller3200. The processor3210may be operated by firmware, and may control the NAND controller3220to access the semiconductor device3100. The NAND controller3220may include a NAND interface3221for communicating with the semiconductor device3100. Through the NAND interface3221, a control command for controlling the semiconductor device3100, data to be written in the memory cell transistors MCT of the semiconductor device3100, data to be read from the memory cell transistors MCT of the semiconductor device3100, etc., may be transferred. The host interface3230may provide communication between the electronic system3000and an outside host. When control command is received from the outside host through the host interface3230, the processor3210may control the semiconductor device3100in response to the control command.

A nonvolatile memory device or a storage device according to example embodiments may be packaged using various package types or package configurations.

The present disclosures may be applied to various electronic devices including a nonvolatile memory device. For example, the present disclosures may be applied to systems such as be a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a camcorder, personal computer (PC), a server computer, a workstation, a laptop computer, a digital TV, a set-top box, a portable game console, a navigation system, etc.