Semiconductor device and method of forming openings in thermally-conductive frame of FO-WLCSP to dissipate heat and reduce package height

A semiconductor device has a thermally-conductive frame and interconnect structure formed over the frame. The interconnect structure has an electrical conduction path and thermal conduction path. A first semiconductor die is mounted to the electrical conduction path and thermal conduction path of the interconnect structure. A portion of a back surface of the first die is removed by grinding. An EMI shielding layer can be formed over the first die. The first die can be mounted in a recess of the thermally-conductive frame. An opening is formed in the thermally-conductive frame extending to the electrical conduction path of the interconnect structure. A second semiconductor die is mounted over the thermally-conductive frame opposite the first die. The second die is electrically connected to the interconnect structure using a bump disposed in the opening of the thermally-conductive frame.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming openings in a thermally-conductive frame of a FO-WLCSP to dissipate heat and reduce package height.

BACKGROUND OF THE INVENTION

Semiconductor devices perform a wide range of functions such as high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.

Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.

One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size may be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.

In fan-out wafer level chip scale packages (FO-WLCSP), semiconductor die are stacked and vertically interconnected within the package. The FO-WLCSP generates considerable thermal energy which must be adequately dissipated. In high frequency applications, the FO-WLCSP can emit or be susceptible to radiation, electromagnetic interference (EMI), radio frequency interference (RFI), harmonic effects, and other inter-device interference, which reduces the electrical performance of the device.

SUMMARY OF THE INVENTION

A need exists to dissipate thermal energy and shield against inter-device interference in a FO-WLCSP in a low profile package. Accordingly, in one embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a thermally-conductive frame, and forming an interconnect structure over the thermally-conductive frame. The interconnect structure includes an electrical conduction path and thermal conduction path. The method further includes the steps of mounting a first semiconductor die to the electrical conduction path and thermal conduction path of the interconnect structure over a first surface of the thermally-conductive frame, removing a portion of a back surface of the first semiconductor die, forming an opening in the thermally-conductive frame extending to the electrical conduction path of the interconnect structure, and mounting a second semiconductor die over a second surface of the thermally-conductive frame, opposite the first surface of the thermally-conductive frame. The second semiconductor die is electrically connected to the interconnect structure using a bump disposed in the opening of the thermally-conductive frame.

In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a thermally-conductive frame, forming an opening through the thermally-conductive frame, depositing sacrificial material in the opening of the thermally-conductive frame, and forming an interconnect structure over the thermally-conductive frame. The interconnect structure includes an electrical conduction path and thermal conduction path. The method further includes the steps of mounting a first semiconductor die to the electrical conduction path and thermal conduction path of the interconnect structure, removing the sacrificial material from the opening of the thermally-conductive frame, and mounting a second semiconductor die over a surface of the thermally-conductive frame opposite the first semiconductor die. The second semiconductor die is electrically connected to the interconnect structure conductive layer using a bump disposed in the opening of the thermally-conductive frame.

In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a thermally-conductive frame, and forming an interconnect structure over the thermally-conductive frame. The interconnect structure includes an electrical conduction path and thermal conduction path. The method further includes the steps of mounting a first semiconductor die to the electrical conduction path and thermal conduction path of the interconnect structure, and forming an opening in the thermally-conductive frame.

In another embodiment, the present invention is a semiconductor device comprising a thermally-conductive frame and interconnect structure formed over the thermally-conductive frame. The interconnect structure includes an electrical conduction path and thermal conduction path. A first semiconductor die is mounted to the electrical conduction path and thermal conduction path of the interconnect structure. An opening is formed in the thermally-conductive frame. A second semiconductor die is mounted over a surface of the thermally-conductive frame opposite the first semiconductor die. The second semiconductor die is electrically connected to the electrical conduction path of the interconnect structure using a bump disposed in the opening of the thermally-conductive frame.

DETAILED DESCRIPTION OF THE DRAWINGS

The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. The portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.

FIG. 1illustrates electronic device50having a chip carrier substrate or printed circuit board (PCB)52with a plurality of semiconductor packages mounted on its surface. Electronic device50may have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown inFIG. 1for purposes of illustration.

Electronic device50may be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device50may be a subcomponent of a larger system. For example, electronic device50may be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components.

For the purpose of illustration, several types of first level packaging, including wire bond package56and flip chip58, are shown on PCB52. Additionally, several types of second level packaging, including ball grid array (BGA)60, bump chip carrier (BCC)62, dual in-line package (DIP)64, land grid array (LGA)66, multi-chip module (MCM)68, quad flat non-leaded package (QFN)70, and quad flat package72, are shown mounted on PCB52. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB52. In some embodiments, electronic device50includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using cheaper components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

FIGS. 2a-2cshow exemplary semiconductor packages.FIG. 2aillustrates further detail of DIP64mounted on PCB52. Semiconductor die74includes an active region containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and are electrically interconnected according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active region of semiconductor die74. Contact pads76are one or more layers of conductive material, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and are electrically connected to the circuit elements formed within semiconductor die74. During assembly of DIP64, semiconductor die74is mounted to an intermediate carrier78using a gold-silicon eutectic layer or adhesive material such as thermal epoxy or epoxy resin. The package body includes an insulative packaging material such as polymer or ceramic. Conductor leads80and wire bonds82provide electrical interconnect between semiconductor die74and PCB52. Encapsulant84is deposited over the package for environmental protection by preventing moisture and particles from entering the package and contaminating die74or wire bonds82.

FIG. 2billustrates further detail of BCC62mounted on PCB52. Semiconductor die88is mounted over carrier90using an underfill or epoxy-resin adhesive material92. Wire bonds94provide first level packing interconnect between contact pads96and98. Molding compound or encapsulant100is deposited over semiconductor die88and wire bonds94to provide physical support and electrical isolation for the device. Contact pads102are formed over a surface of PCB52using a suitable metal deposition process such as electrolytic plating or electroless plating to prevent oxidation. Contact pads102are electrically connected to one or more conductive signal traces54in PCB52. Bumps104are formed between contact pads98of BCC62and contact pads102of PCB52.

InFIG. 2c, semiconductor die58is mounted face down to intermediate carrier106with a flip chip style first level packaging. Active region108of semiconductor die58contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements within active region108. Semiconductor die58is electrically and mechanically connected to carrier106through bumps110.

BGA60is electrically and mechanically connected to PCB52with a BGA style second level packaging using bumps112. Semiconductor die58is electrically connected to conductive signal traces54in PCB52through bumps110, signal lines114, and bumps112. A molding compound or encapsulant116is deposited over semiconductor die58and carrier106to provide physical support and electrical isolation for the device. The flip chip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die58to conduction tracks on PCB52in order to reduce signal propagation distance, lower capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die58can be mechanically and electrically connected directly to PCB52using flip chip style first level packaging without intermediate carrier106.

FIGS. 3a-3gillustrate, in relation toFIGS. 1 and 2a-2c, a process of forming openings in a thermally-conductive frame of FO-WLCSP to dissipate heat and reduce package height. InFIG. 3a, wafer-form frame or heat spreader120can be Al, Cu, or another material with high thermal conductivity to provide heat dissipation and structural support. InFIG. 3b, an insulating or dielectric layer122is formed over thermally-conductive frame120using PVD, CVD, printing, spin coating, spray coating, or thermal oxidation. The insulating layer122can be one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), polyimide, benzocyclobutene (BCB), polybenzoxazoles (PBO), or other dielectric material having similar insulating and structural properties.

An electrically conductive layer124is formed over insulating layer122using patterning with PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer124can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Some portions of conductive layer124extend through insulating layer122to frame120. The portions of conductive layers124can be electrically common or electrically isolated depending on the design and function of the semiconductor device.

A plurality of vias is formed through insulating layer122to frame120using laser drilling or etching process. The vias are filled with Al, Cu, or other suitable thermally conductive material using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process to form thermally-conductive through hole vias (THV)126. The insulating layer122, conductive layer124, and THVs126constitute an interconnect structure128formed over the thermally-conductive frame with an electrical conduction path as conductive layer124and thermal conduction path as THV126.

InFIG. 3c, semiconductor die130are mounted over a first surface of frame120to conductive layer124and THVs126using bumps132. Each semiconductor die130include an active surface134containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface134to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, memory, or other signal processing circuit. Semiconductor die130may also contain IPDS, such as inductors, capacitors, and resistors, for RF signal processing. In one embodiment, semiconductor die130is a flipchip type device. Bumps132aprovide electrical connection between circuits within semiconductor die130and conductive layer124. Bumps132bprovide thermal conduction between semiconductor die130and frame120. An underfill material138, such as epoxy resin, is deposited under semiconductor die130.

InFIG. 3d, grinder140removes excess bulk material from a backside of semiconductor wafer130, opposite active surface134, to reduce thickness of the die prior to singulation.

InFIG. 3e, an electrically conductive bump material is deposited over conductive layer124using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer124using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps142. In some applications, bumps142are reflowed a second time to improve electrical contact to conductive layer124. The bumps can also be compression bonded to conductive layer124. Bumps142represent one type of interconnect structure that can be formed over conductive layer124. The interconnect structure can also use bond wires, stud bump, micro bump, or other electrical interconnect.

The wafer-form frame120is singulated along line144with saw blade or laser cutting tool148into individual FO-WLCSP150.

Post-singulation FO-WLCSP150is inverted inFIG. 3fand a portion of frame120is removed using a laser drilling or etching process to form hollowed openings or through holes152and expose a backside of conductive layer124which extended through insulating layer122to frame120, as described inFIG. 3b. Openings152can also be formed prior to singulation.

InFIG. 3g, semiconductor die154is mounted over a second surface of frame120opposite semiconductor die130to conductive layer124using bumps156. Semiconductor die154includes an active surface158containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface158to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuit. Semiconductor die154may also contain IPDS, such as inductors, capacitors, and resistors, for RF signal processing. In one embodiment, semiconductor die154is a flipchip type device. Alternatively, a discrete semiconductor device is mounted over thermally-conductive frame120to conductive layer124with bumps disposed within openings152.

Semiconductor die130in FO-WLCSP150dissipates heat through bumps132band thermally-conductive frame120. Semiconductor die154is electrically connected through bumps156and132aand conductive layer124to semiconductor die130, and further through bumps142to external devices. Bumps156are disposed within openings152of frame120to reduce the height of FO-WLCSP150and simplify semiconductor package stacking. Openings152are sufficiently large to contain bumps156without electrical shorting to frame120.

FIGS. 4a-4gillustrate, in relation toFIGS. 1 and 2a-2c, another process of forming openings in a thermally-conductive frame of FO-WLCSP to dissipate heat and reduce package height. InFIG. 4a, wafer-form frame or heat spreader160can be Al, Cu, or another material with high thermal conductivity to provide heat dissipation and structural support. A plurality of openings or through holes is formed in frame160using laser drilling or etching process. The openings are filled with sacrificial material162, such as a B-stage polymer or heat-releasable materials. The sacrificial material162is releasable with ultra-violet (UV) light or heat.

An electrically conductive layer166is formed over insulating layer164using patterning with PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer166can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Some portions of conductive layer166extend through insulating layer164to sacrificial material162. The portions of conductive layers166can be electrically common or electrically isolated depending on the design and function of the semiconductor device.

A plurality of vias is formed through insulating layer164to frame160using laser drilling or etching process. The vias are filled with Al, Cu, or other suitable thermally conductive material using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process to form thermally-conductive THV168. The insulating layer164, conductive layer166, and THVs168constitute an interconnect structure formed over the thermally-conductive frame with an electrical conduction path as conductive layer166and thermal conduction path as THV168.

InFIG. 4c, semiconductor die170are mounted over a first surface of frame160to conductive layer166and THVs168using bumps172. Each semiconductor die170include an active surface174containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface174to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuit. Semiconductor die170may also contain IPDS, such as inductors, capacitors, and resistors, for RF signal processing. In one embodiment, semiconductor die170is a flipchip type device. Bumps172aprovide electrical connection between circuits within semiconductor die170and conductive layer166. Bumps172bprovide thermal conduction between semiconductor die170and frame160. An underfill material178, such as epoxy resin, is deposited under semiconductor die170.

InFIG. 4d, grinder180removes excess bulk material from a backside of semiconductor wafer170, opposite active surface174, to reduce thickness of the die prior to singulation.

InFIG. 4e, an electrically conductive bump material is deposited over conductive layer166using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer166using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps182. In some applications, bumps182are reflowed a second time to improve electrical contact to conductive layer166. The bumps can also be compression bonded to conductive layer166. Bumps182represent one type of interconnect structure that can be formed over conductive layer166. The interconnect structure can also use bond wires, stud bump, micro bump, or other electrical interconnect.

The wafer-form frame160is singulated along line184with saw blade or laser cutting tool188into individual FO-WLCSP190.

Post-singulation FO-WLCSP190is inverted inFIG. 4fand sacrificial material162is removed using UV or heat leaving hollowed openings or through holes192. Openings192expose a backside of conductive layer166which extended through insulating layer164to sacrificial material162, as described inFIG. 4b. Sacrificial material162can also be removed prior to singulation.

InFIG. 4g, semiconductor die194is mounted over a second surface of frame160opposite semiconductor die170to conductive layer166using bumps196. Semiconductor die194includes an active surface198containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface198to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuit. Semiconductor die194may also contain IPDS, such as inductors, capacitors, and resistors, for RF signal processing. In one embodiment, semiconductor die194is a flipchip type device. Alternatively, a discrete semiconductor device is mounted over frame160to conductive layer166with bumps disposed within openings192.

Semiconductor die170in FO-WLCSP190dissipates heat through bumps172band thermally-conductive frame160. Semiconductor die194is electrically connected through bumps196and172aand conductive layer166to semiconductor die170, and further through bumps182to external devices. Bumps196are disposed within openings192of frame160to reduce the height of FO-WLCSP190and simplify semiconductor package stacking. Openings192are sufficiently large to contain bumps196without electrical shorting to frame160.

FIG. 5shows an embodiment continuing fromFIG. 3fwith an encapsulant200deposited over semiconductor die130using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant200can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant200is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.

FIG. 6shows an embodiment without underfill material138inFIG. 3c. Instead, an encapsulant202is deposited over and around semiconductor die130using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant202can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant202is removed during the grinding process ofFIG. 3dto expose a backside of semiconductor die130opposite active surface134.

FIG. 7shows an embodiment, continuing fromFIG. 3b, with semiconductor die210mounted to thermally-conductive frame120with thermal interface material (TIM)212. TIM212can be aluminum oxide, zinc oxide, boron nitride, or pulverized silver. Semiconductor die210contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within its active surface to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuit. Semiconductor die210may also contain IPDS, such as inductors, capacitors, and resistors, for RF signal processing. The circuits on semiconductor die210are electrically connected to conductive layer124with bond wires214.

An encapsulant216is deposited over semiconductor die210using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant216can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant216is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.

An electrically conductive bump material is deposited over conductive layer124using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer124using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps218. In some applications, bumps218are reflowed a second time to improve electrical contact to conductive layer124. The bumps can also be compression bonded to conductive layer124. Bumps218represent one type of interconnect structure that can be formed over conductive layer124. The interconnect structure can also use bond wires, stud bump, micro bump, or other electrical interconnect.

FIG. 8shows an embodiment, continuing fromFIG. 7, with a shielding layer220formed over or mounted to encapsulant216surrounding semiconductor die210. Shielding layer220can be Cu, Al, ferrite or carbonyl iron, stainless steel, nickel silver, low-carbon steel, silicon-iron steel, foil, epoxy, conductive resin, and other metals and composites capable of blocking or absorbing EMI, RFI, and other inter-device interference. Shielding layer220can also be a non-metal material such as carbon-black or aluminum flake to reduce the effects of EMI and RFI. Shielding layer220is grounded through conductive layer124and bumps218. An EMI shielding layer can also be mounted over a flipchip type semiconductor die, such as shown inFIG. 5.

FIG. 9shows an embodiment, continuing fromFIG. 3f, with an insulating or dielectric layer222, such as SiO2 or Al2O3, formed around the sidewalls of openings152to prevent electrical shorting between bumps156and frame120.

FIG. 10shows an embodiment, continuing fromFIG. 3f, with a recess or cavity224formed in frame120to accommodate another semiconductor die while maintaining a low vertical profile for the FO-WLCSP.

FIG. 11shows an embodiment, continuing fromFIG. 3f, with an insulating or dielectric layer226, such as SiO2 or Al2O3, formed over frame120and into openings152. The insulating layer226follows the contour of frame120and openings152. An electrically conductive layer228is formed over insulating layer226using patterning with PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer228can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer228operates as a redistribution layer to extend electrical interconnect to external devices.

FIG. 12shows an embodiment, similar toFIG. 3f, with a recess or cavity230formed in a surface of frame120prior to mounting semiconductor die130. The insulating layer122and conductive layer124follow the contour of recess230in frame120. Recess230reduces the thickness of the FO-WLCSP while providing heat dissipation for semiconductor die130through THVs126and thermally-conductive frame120.

In another an embodiment, continuing fromFIG. 3f, FO-WLCSP150is inverted and an encapsulant232is deposited over semiconductor die130and bumps142using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant232can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant232is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.