METHODS AND APPARATUS TO DETERMINE EXECUTION COST

Methods, apparatus, systems, and articles of manufacture to determine execution cost are disclosed. An example apparatus includes memory; instructions included in the apparatus; and processor circuitry to execute the instruction to: cause a plurality of instructions corresponding to a mnemonic to be executed; determine an average execution cost of the plurality of instructions; determine a standard deviation of execution costs of the plurality of instructions; and generate a mapping table including an entry, the entry including the mnemonic in association with the average and the standard deviation.

FIELD OF THE DISCLOSURE

This disclosure relates generally to computing systems and, more particularly, to methods and apparatus to determine execution cost.

BACKGROUND

Processor resources are needed to execute instructions to perform one or more tasks. The amount of processor resources needed to execute the instructions corresponds to an execution cost of the instructions. The execution cost may correspond to a total number of cycles and/or seconds to execute the program. Because different computer architectures are structured differently, a program designed for one type of computer architecture may have a different execution cost for another computer architecture. A computing system may use execution cost of code to attempt to optimize instruction, improve instructions, and/or otherwise lower the execution cost of the instructions. For example, machine programming may rely on execution cost when attempting to replace low-performance instructions with high-performance instructions based on the execution cost of both sets of instructions.

DETAILED DESCRIPTION

The figures are not to scale. Instead, the thickness of the layers or regions may be enlarged in the drawings. As used herein, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference and/or relative movement between those elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and/or in fixed relation to each other. As used herein, stating that any part is in “contact” with another part is defined to mean that there is no intermediate part between the two parts.

Unless specifically stated otherwise, descriptors such as “first,” “second,” “third,” etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly that might, for example, otherwise share a same name. As used herein, “approximately” and “about” refer to dimensions that may not be exact due to manufacturing tolerances and/or other real world imperfections. As used herein “substantially real time” refers to occurrence in a near instantaneous manner recognizing there may be real world delays for computing time, transmission, etc. Thus, unless otherwise specified, “substantially real time” refers to real time +/−1 second. As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events.

Accurate and efficient determination of a program's cost (e.g., total number of clock cycles and/or seconds to complete a program) is desirable in many different applications (e.g., code optimization, design of hardware (e.g., compilers), design of software (e.g., binary translators), code recommendation systems, schedulers on cloud or clusters, etc.). For example, compiler backends may select instructions by relying on an estimation of execution cost. To determine execution cost of instructions, some techniques simply execute them on the actual hardware. However, such techniques are expensive and time consuming. Other techniques have been used to estimate execution cost using models and/or other tools. However, such techniques may be inaccurate and/or require large maintenance overhead. Some techniques use artificial intelligence (AI) to predict the execution cost of a set of instructions. Although such techniques are accurate, such techniques are computationally-intensive and, moreover, AI-based techniques do not provide an explanation for a result. Accordingly, the reason for why the AI-based techniques determined that the code corresponds to an execution cost is unknown.

Examples disclosed herein develop an approach that is accurate, explainable, and executes using less processor resources than the above-mentioned techniques. Examples disclosed herein include a server that develops architecture-specific mapping tables that map converted instructions (e.g., abstractions of instructions based on the leading mnemonic and/or function of an instruction line) to an average execution cost and standard deviation cost. Using examples disclosed herein, the server can obtain programs and/or basic blocks of code from storage (e.g., open-source repositories, crowd-sourced repositories, closed-source repositories, local storage, external stored, local databases, external databases, etc.), execute lines of the code to identify execution costs corresponding to the function and/or mnemonic of the line of code and map the mnemonic to the average execution cost and the standard deviation of the execution cost. For example, examples disclosed herein may identify 10 instances of instructions that begin with the mnemonic “add,” execute the 10 instances on a CPU corresponding to a particular architecture and determine that the average cycles needed to execute the instruction was 3 with standard deviation of 1. In this manner, examples disclosed herein map the mnemonic “add” to a “3” average and a “1” standard deviation. As used herein, a basic block is a sequence of instructions or program, where the control flows sequentially through the sequence.

After a threshold number of programs and/or blocks of code have been mapped, examples disclosed herein can deploy the mapping table to computing devices within a network that may or may not correspond to the particular computer architecture. In this manner, the computing system can use the mapping to estimate the execution cost of a program corresponding to a basic block by identifying mnemonic for each line of the program and determining the corresponding average and/or standard deviation of the execution cost using the mapping table, thereby requiring far less resources and time than the above-mentioned techniques. In some examples, the architecture of the computing device during deployment could be different than the architecture of the mapping table. Additionally, the mapping provides the reasoning and/or explainability for the cost of a program line-by-line.

FIG. 1is a block diagram of an example environment100described in conjunction with examples disclosed herein. The example environment100includes an example server102, example execution cost mapping table determination circuitry104, example architecture-specific CPU(s)105, an example network106, an example computing device108, an example mapping table storage112, an example CPU114, and an example basic block execution cost determination circuitry116.

The example server(s)102ofFIG. 1may be server(s) and/or any other computing device(s) that generates mapping tables. The example server103may access blocks of code stored locally or externally (e.g., a code repository/storage/database stored locally or externally). After blocks of code have been obtained, the example execution cost mapping table determination circuitry104processes the blocks of code to generate a mapping table that links average and standard deviation of execution cost to a mnemonic and/or function of a line of instruction. As further described below, the execution cost mapping table determination circuitry104processes the lines of the blocks of code and generates the mnemonic by abstracting out specific numerical and/or register values. In this manner, instructions corresponding to the same mnemonic are executed by one or more of the architecture-specific CPU(s)105and the execution cost is identified. In some examples, the architecture of the server102and the computing device108are different. For example, the computing device108may be a client device that has CPU for a first architecture but is optimizing a program written for a second architecture using the mapping table for the second architecture. This may occur because compilers may support a cross compilation mode, where a compiler running on the second architecture can generate or optimize a program written for the first architecture. The execution cost for each instruction corresponding to the same mnemonic are averaged and a standard deviation is calculated. The mnemonic is stored in a mapping table in conjunction with the corresponding average and standard deviation. In this manner, the computing device108can use the entry in the mapping table to estimate execution cost based on a program that includes a line of code that corresponds to the mnemonic.

Because execution cost for the same instruction may be different for different architectures, the example server102ofFIG. 1includes the different architecture-specific CPU(s)105to execute code according to different specific architectures. The architecture-specific CPU(s)105executes code and outputs execution cost corresponding to the executed code. For example, the architecture-specific CPU(s)105acts as a driver program with necessary boilerplate code around concrete assembly instructions to execute individual instructions in a loop to reach a steady state (e.g., 100 iterations) and measure execution cost based on the iterations. In this manner, the execution cost mapping table determination circuitry104can develop architecture-specific mapping tables that can be deployed to computing devices. The example execution cost mapping table determination circuitry104is further described below in conjunction withFIG. 2.

The example network106ofFIG. 1is a system of interconnected systems exchanging data. The example network106may be implemented using any type of public or private network such as, but not limited to, the Internet, a telephone network, a local area network (LAN), a cable network, and/or a wireless network. To enable communication via the network106, the example server(s)102and/or the computing device108includes a communication interface that enables a connection to an Ethernet, a digital subscriber line (DSL), a telephone line, a coaxial cable, or any wireless connection, etc. In some examples, the server(s)102and the example computing device108are connected via the example network106.

The example computing device108ofFIG. 1obtains determined mapping tables from the server102(e.g., via the network106) and uses the mapping table to estimate the execution costs of programs. The example computing device108may be a server, an edge-based device, a cloud-based device, an internet of thing (IoT) device, a computer, a mobile device, a tablet, and/or any other type of computing device. The example computing device108includes the example network interface110to obtain the determined mapping table corresponding to the architecture of the computing device108from the server102via the network106. An obtained mapping table is stored in the mapping table storage112of the example computing device108. Additionally, the network interface110may obtain mapping table updates and/or replacements. In such examples, the updates and/or replacements are used to update the mapping table stored in the example mapping table storage112.

The example CPU114ofFIG. 1executes instructions (e.g., a program and/or code) to perform one or more tasks. In some examples, the CPU114may instruct the basic block execution cost determination circuitry116to determine the cost of program, block of code, and/or instruction. The basic block execution cost determination circuitry116ofFIG. 1determines the cost by traversing through the code line-by-line and determining a range of the execution cost of each line of code based on the execution cost and standard deviation corresponding to the mnemonic of the line using the mapping table stored in the example mapping table storage112. For example, when the basic block execution cost determination circuitry116processes a line of code, the cost determination circuitry determines the mnemonic and/or function part of the line of code (e.g., “add,” “div,” “store,” etc.). After the mnemonic is obtained, the basic block execution cost determination circuitry116accesses the mapping table in the mapping table storage112to identify an average and standard deviation for the determined mnemonic. The example basic block execution cost determination circuitry116determines an execution cost maximum and minimum based on the average and standard deviation. After the maximum and minimum execution costs of each line is determined, the example basic block execution cost determination circuitry116determines the average execution cost and standard deviation cost for the code based on the maximum and minimum execution costs. If the basic block execution cost determination circuitry116is unable to match the determined mnemonic with a mnemonic in the mapping table, the basic block execution cost determination circuitry116may determine the average and standard deviation of the line of code based on present values (e.g., the mean, median, or mode of the average execution cost and/or the mean, median, or mode of the standard deviation execution cost across the mnemonics of the mapping table). The example basic block execution cost determination circuitry116is further described below in conjunction withFIG. 2.

FIG. 2is a block diagram of an example implementation of the example execution cost mapping table determination circuitry104and the example basic block execution cost determination circuitry116ofFIG. 1. The example execution cost mapping table determination circuitry104includes an example network interface200, example architecture-specific compiler(s)202, example instruction converter circuitry204, example pair storage206, example cost determination circuitry208, and an example component interface210. The example basic block execution cost determination circuitry116includes an example component interface212, example instruction conversion circuitry214, example cost estimation circuitry216, and example calculation circuitry218.

The example network interface200ofFIG. 2transmits mapping tables to computing device(s) (e.g., the computing device108) via the network106. In some examples, the network interface200obtains instructions, code, programs, and/or basic blocks from one or more external repositories, storage, and/or databases.

The example architecture-specific compiler(s)202compiles high level code into assembly code corresponding to a target architecture. The example architecture-specific compiler(s)202may be a single compiler to compile high level code into multiple architectures or may be multiple compilers (e.g., a first compiler for a first architecture, a second compiler for a second architecture, etc.). The example architecture-specific compiler(s)202may be GNU compiler collection (GCC), Intel® C++ Compiler (ICC), low level virtual machine (LLVM), etc. that compile(s) input programs using different permutations of compiler options (e.g., −O2, −march=T, etc.). Additionally, the example architecture-specific compiler(s)202may convert commands in makefiles (e.g., if available).

The example instruction converter circuitry204ofFIG. 2converts lines of assembly code into mnemonic and operands. For example, the instruction converter circuitry204may convert “add $2, % rax” into “add” and “$2, % rax.” After converting in the mnemonic and operands, the example instruction convert circuitry204abstracts the command by removing the values and/or variables that correspond to numbers and/or registers and replaces them with tokens corresponding to the value type. For example, operands that include numerical constants will be replaced with tokens corresponding to numerical type (e.g., integer, real number, Boolean, etc.) and operands that correspond to register will be replaced with a token corresponding to register. Additionally, the example instruction converter circuitry204pairs the assembly instruction with the corresponding abstraction and stores the pair in the example pair storage206. In some examples, before storing the paid storage206, the example instruction converter circuitry204determines if the pair and/or the abstraction and token is already stored in the pair storage206, the instruction converter circuitry204may discard the pair (e.g., because a duplicate instruction may not add diversity to the stored pairs when determining execution cost information). The example instruction converter circuitry204may continue to process additional input programs until a threshold number of pairs are stored in the example pair storage206. The threshold may be based on user and/or manufacturer preferences.

The example cost determination circuitry208ofFIG. 2accesses the example pair storage206to access one or more stored pairs. The example cost determination circuitry208may identify the pairs that correspond to the same mnemonic (e.g., with different operands) based on the abstraction. The cost determination circuitry208transmits (e.g., via the component interface210) the pairs of corresponding to the same mnemonic to the architecture-specific CPU105(e.g., corresponding a specific architecture that corresponds to the architecture of the architecture-specific compiler202) and obtains (e.g., via the component interface210) the execution cost for each of the instructions. The example cost determination circuitry208determines the average and standard deviation of the execution costs of the plurality of instructions corresponding to the same mnemonic. After the average and standard deviation corresponding to the mnemonic are determined, the cost determination circuitry208generates an entry for a mapping table to include the mnemonic and corresponding average and standard deviation cost.

The example component interface210ofFIG. 2transmits instructions to be executed to the example architecture-specific CPU(s)105. Additionally, the example component interface210obtains execution cost of executing the instructions from the architecture-specific CPU(s)105. In some examples, the component interface210may obtain high level instructions, code, and/or basic blocks from internal storage of the server102(e.g., when the server102includes storage, one or more databases, and/or one or more repositories including code).

The example component interface212ofFIG. 2of the example basic block execution cost determination circuitry116accesses mapping tables from the example mapping table storage112. As described above, the network interface110of the computing device108obtains the mapping table from the server102and stores the mapping table into the example mapping table storage112. Additionally, the example component interface212may obtain instructions to determine the execution cost of a program from the example CPU114. The example component interface212obtains a basic block, program, and/or code in assembly language to determine the execution cost. After the execution cost is determined, the example component interface212transmits the execution cost to the example CPU114or another device.

The example instruction conversion circuitry214ofFIG. 2converts obtained and/or determined assembly language code into individual lines. In some examples, the CPU114includes a compiler to convert high level language into the assembly language. After the code is broken up into individual instructions, the example instruction conversion circuitry214identifies the mnemonic (e.g., function) of the individual instructions. For example, the instruction conversion circuitry214may identify the mnemonic “div” from the instructions “div $2.”

The example cost estimation circuitry216processes the mnemonics of the basic block, code, and/or program to determine an execution cost for the basic block, code, and/or program and/or a standard deviation for the basic block, code, and/or program. For example, for an instruction that corresponds to a “mov” mnemonic, the cost estimation circuitry216accesses the mapping table to identify an entry for the mnemonic “mov.” After the corresponding entry is identified, the cost estimation circuitry216determines corresponding execution cost average (e.g., also referred to as range average, Ravg) and execution cost standard deviation (e.g., also referred to as range standard deviation, Rstdev) of the mnemonic from the mapping table. If the mnemonic of the instruction is not included in the mapping table, the example cost estimation circuitry216may use a preset value for the execution cost average and the execution standard deviation. In some examples, the cost estimation circuitry216selects the preset value based on the average execution cost and average standard deviation across the mnemonics from the mapping table.

The example calculation circuitry218ofFIG. 2calculates the execution cost of the program (e.g., also referred to as a range summation) and a standard deviation for the execution cost of the program using the average execution cost and standard deviation of the execution cost of the instructions of the program, code, and/or basic block. For example, the calculation circuitry218may determine a minimum execution cost and/or cost range for a particular instruction using the below Equation 1, a maximum execution cost and/or cost range for the particular instruction using the below Equation 2, and the execution cost for the program (e.g., range summation) using the below Equation 3 (e.g., the sum of the average costs for the instructions of the program, code, and/or basic block).

In the above Equations 1-3, Ravg is the average execution cost for an instruction and Rstdev is the standard deviation for the execution cost. Because standard deviation may provide valuable information that is not included in the range summation, the example calculation circuitry218also calculates the standard deviation of the minimum execution costs and maximum execution costs of the instructions of the program, code, and/or basic block, as shown in the below Equation 4.

The example calculation circuitry218transmits the execution cost and standard deviation of the program, code, and/or basic block to the CPU114and/or other component/device using the example component interface212.

In some examples, the computational cost mapping table determination circuitry104includes means for identifying, means for generating, and means for converting. For example, the means for identify may be implemented by the instruction converter circuitry204, the means for generating may be implemented by the cost determination circuitry208, and the means for converting may be implemented by the instruction converter circuitry204or the architecture-specific compiler(s)202. In some examples, the architecture-specific compiler(s)202, the instruction converter circuitry204, and/or the cost determination circuitry208may be instantiated by processor circuitry such as the example processor circuitry512ofFIG. 5. For instance, the architecture-specific compiler(s)202, the instruction converter circuitry204, and/or the cost determination circuitry208may be instantiated by the example general purpose processor circuitry600ofFIG. 6executing machine executable instructions such as that implemented by at least blocks ofFIGS. 3A and 3B. In some examples, the architecture-specific compiler(s)202, the instruction converter circuitry204, and/or the cost determination circuitry208may be instantiated by hardware logic circuitry, which may be implemented by an ASIC or the FPGA circuitry700ofFIG. 7structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the architecture-specific compiler(s)202, the instruction converter circuitry204, and/or the cost determination circuitry208may be instantiated by any other combination of hardware, software, and/or firmware. For example, the architecture-specific compiler(s)202, the instruction converter circuitry204, and/or the cost determination circuitry208may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

In some examples, the basic block execution cost determination circuitry116includes means for identifying, means for finding, and means for selecting, means for determining, and/or means for reporting. For example, the means for identifying may be implemented by the instruction conversion circuitry214, the means for finding may be implemented by the cost estimation circuitry216, and the means for selecting, the means for determining, and/or the means for reporting may be implemented by the calculation circuitry218. In some examples, the instruction conversion circuitry214, the cost estimation circuitry216, and/or the calculation circuitry218may be instantiated by processor circuitry such as the example processor circuitry512ofFIG. 5. For instance, the instruction conversion circuitry214, the cost estimation circuitry216, and/or the calculation circuitry218may be instantiated by the example general purpose processor circuitry600ofFIG. 6executing machine executable instructions such as that implemented by at least blocks ofFIG. 4. In some examples, the instruction conversion circuitry214, the cost estimation circuitry216, and/or the calculation circuitry218may be instantiated by hardware logic circuitry, which may be implemented by an ASIC or the FPGA circuitry700ofFIG. 7structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the instruction conversion circuitry214, the cost estimation circuitry216, and/or the calculation circuitry218may be instantiated by any other combination of hardware, software, and/or firmware. For example, the instruction conversion circuitry214, the cost estimation circuitry216, and/or the calculation circuitry218may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

While an example manner of implementing the execution cost mapping table determination circuitry104and/or the basic block execution cost determination circuitry116ofFIG. 1is illustrated inFIG. 2, one or more of the elements, processes, and/or devices illustrated inFIG. 2may be combined, divided, re-arranged, omitted, eliminated, and/or implemented in any other way. Further, the example network interface200, the example architecture-specific compiler(s)202, the example instruction converter circuitry204, the example cost determination circuitry208, the example component interface210,212, the example instruction conversion circuitry214, the example cost estimation circuitry216, the example calculation circuitry218, and/or, more generally, the execution cost mapping table determination circuitry104and/or the basic block execution cost determination circuitry116ofFIGS. 1-2, may be implemented by hardware, software, firmware, and/or any combination of hardware, software, and/or firmware. Thus, for example, any of the example network interface200, the example architecture-specific compiler(s)202, the example instruction converter circuitry204, the example cost determination circuitry208, the example component interface210,212, the example instruction conversion circuitry214, the example cost estimation circuitry216, the example calculation circuitry218, and/or, more generally, the execution cost mapping table determination circuitry104and/or the basic block execution cost determination circuitry116ofFIGS. 1-2, could be implemented by processor circuitry, analog circuit(s), digital circuit(s), logic circuit(s), programmable processor(s), programmable microcontroller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)), and/or field programmable logic device(s) (FPLD(s)) such as Field Programmable Gate Arrays (FPGAs). When reading any of the apparatus or system claims of this patent to cover a purely software and/or firmware implementation, the execution cost mapping table determination circuitry104and/or basic block execution cost determination circuitry116ofFIGS. 1-2is/are hereby expressly defined to include a non-transitory computer readable storage device or storage disk such as a memory, a digital versatile disk (DVD), a compact disk (CD), a Blu-ray disk, etc., including the software and/or firmware. Further still, the execution cost mapping table determination circuitry104and/or basic block execution cost determination circuitry116ofFIGS. 1-2may include one or more elements, processes, and/or devices in addition to, or instead of, those illustrated inFIG. 1-2, and/or may include more than one of any or all of the illustrated elements, processes, and devices.

FIGS. 3A and 3Billustrate a flowchart representative of example machine readable instructions and/or example operations300that may be executed and/or instantiated by processor circuitry (e.g., the example execution cost mapping table determination circuitry104ofFIG. 2) to determine develop an architecture-specific mapping table to provide to a computing device corresponding to the specific architecture. The instructions begin at block302when the architecture-specific compiler(s)202determine(s) if a program, code, and/or basic block has been obtained (e.g., via the network interface200for external data and/or via the component interface210for internal data).

At block304, the example architecture-specific compiler(s)202converts the program, code, and/or basic block into assembly language. At block306, the example instruction converter circuitry204selects a first instruction (e.g., a first line of the assembly instructions) from the assembly language of the program, code, and/or basic block. At block308, the example instruction converter circuitry204converts the instruction of the assembly language into a mnemonic and an operand.

At block310, the example instruction converter circuitry204determines if the operand corresponds to numeric constant(s). For example, does the operate include a numeric value or a value that corresponds to a number constant. If the example instruction converter circuitry204determines that the operand does not correspond to a numeric constant (block310: NO), control continues to block314. If the example instruction converter circuitry204determines that the operand corresponds to a numeric constant (block310: YES), the instruction converter circuitry204generates a converted instruction (e.g., an abstraction of the instruction) by replacing the number or variable corresponding to the numeric constant with a token corresponding to the constant type (e.g., integer, Boolean, short, long, float, etc.) (block312). In this manner, the specific numeric number is abstracted to a general number type.

At block314, the example instruction converter circuitry204determines if the operand corresponds to a register operation (e.g., where a value will be accessed, stored, etc.). If the example instruction converter circuitry204determines that the operand does not correspond to a register (block314: NO), instructions continue to block318. If the example instruction converter circuitry204determines that the operand corresponds to a register (block314: YES), the example instruction converter circuitry204generates a converted instruction (e.g., an abstraction of the instruction) by replacing the value corresponding to the register with a token corresponding to register (block316). In this manner, the specific register number is abstracted to a general register token.

At block318, the example instruction converter circuitry204pairs the instruction with the converted (e.g., abstract) instruction. At block320, the example instruction converter circuitry204determines if the pair is already stored in the example pair storage206(e.g., to prevent duplicate pairs being stored). In some examples, the instruction converter circuitry204determines if abstraction of the instruction is already stored in the example pair storage206as opposed to the complete pair. If the example instruction converter circuitry204determines that a pair is already included in the pair storage206(block320: YES), the pair is discarded and control continue to block322. If the example instruction converter circuitry204determines that a pair is not already included in the pair storage206(block320: YES), the example instruction converter circuitry204stores the pair in the example pair storage206(block322).

At block324, the example instruction converter circuitry204determines if the pair storage206includes a threshold number of pairs (e.g., entries). The less pairs stored in the example pair storage206, the less robust the mapping table will be (e.g., less entries and possibly less accurate execution cost information), and the more pairs, the more resources, time, and input data needed. Accordingly, a user and/or manufacturer can define the threshold of entries to balance robustness with time, resources, and/or input data. If the example pair storage206does not include the threshold number of pairs (e.g., does not satisfy the threshold) (block324: NO), control returns to block302to process additional programs, code and/or basic blocks. If the example pair storage206includes the threshold number of pairs (e.g., satisfies the threshold) (block324: YES), the example cost determination circuitry208accesses the instruction(s) corresponding to a first mnemonic (block326ofFIG. 3B).

At block328, the example cost determination circuitry208selects a first instruction of the accessed instruction(s). At block330, the example cost determination circuitry208instructs the CPU105to execute the selected instruction. For example, the cost determination circuitry208may transmit the instruction to the example CPU105via the component interface210. As described above, the example CPU105may execute the instruction one or more times to determine the execution cost of the instruction. After the instruction is executed one or more times, the CPU105provides the execution cost of the instruction to the cost determination circuitry208via the component interface210. At block332, the example cost mapping circuitry obtains the execution cost of the instruction from the CPU105via the component interface210.

At block334, the example cost determination circuitry208determines if there is an additional instruction corresponding to the converted instruction. If the cost determination circuitry208determines that there is an additional instruction (block334: YES), the example cost determination circuitry208selects the subsequent instruction (block336) and control returns to block330to determine the execution cost of the additional instruction corresponding to the selected mnemonic. If the cost determination circuitry208determines that there is no additional instruction (block334: NO), the example cost determination circuitry208determines the execution cost average based on an average of the execution costs of the instructions corresponding to the selected mnemonic (block338).

At block340, the example cost determination circuitry208determines the execution cost standard deviation based on the obtained execution costs of instructions corresponding to the mnemonic. At block342, the example cost determination circuitry208adds an entry for a mapping of the mnemonic to the execution cost average and standard deviation in the mapping table. For the first entry, the example cost determination circuitry208generate the mapping table with the single entry. For subsequent entries, the example cost mapping circuitry adds entries to the previously generate mapping table. At block344, the example cost determination circuitry208determines if there is an additional mnemonic in the pair storage206to be processed. If the example cost determination circuitry208determines that there is an additional mnemonic in the pair storage206(block344YES), the cost determination circuitry208accesses the instruction(s) corresponding to the subsequent mnemonic (block346) and control returns to block328. If the example cost determination circuitry208determines that there is not an additional mnemonic in the pair storage206(block344NO), the cost determination circuitry208deploys the mapping table to devices that correspond to the architecture via the network interface200(block348).

FIG. 4is a flowchart representative of example machine readable instructions and/or example operations that may be executed and/or instantiated by processor circuitry (e.g., the basic block execution cost determination circuitry116ofFIG. 2) to determine execution cost of a program, code, and/or basic block using a mapping table. The instructions begin at block402when the example instruction conversion circuitry214determines if a program, code, and/or a basic block has been obtained (e.g., via the component interface212). It is assumed that the obtained program, code, and/or basic block is and/or has been converted to assembly language. If the obtained program, code, and/or basic block is not in assembly language, the example instruction conversion circuitry214converts the program, code, and/or basic block into assembly language.

If the example instruction conversion circuitry214determines that a program, code, and/or basic block has not been obtained (block402: NO), control returns to block402. If the example instruction conversion circuitry214determines that a program, code, and/or basic block has been obtained (block402: YES), the example instruction conversion circuitry214selects a first instruction of the program, code, and/or basic block (block404). At block406, the example instruction conversion circuitry identifies the mnemonic and/or function of the selected instruction. At block408, the example cost estimation circuitry216accesses (e.g., via the component interface212) the mapping table in the mapping table storage112to attempt to find the mnemonic from the mapping table. If the example cost estimation circuitry216does not find the mnemonic and/or function in the mapping table (block410: NO), the example calculation circuitry218determines a minimum and/or maximum execution cost of the instruction based on a corresponding preset average and/or standard deviation for the instruction (block412). For example, the calculation circuitry218selects a preset average and standard deviation for the instruction and determines the minimum and/or maximum execution cost using the above Equations 1-2.

If the example cost estimation circuitry216finds the mnemonic and/or function in the mapping table (block410: YES), the example calculation circuitry218determines a minimum and/or maximum execution cost of the instruction based on an average and/or standard deviation of the mnemonic based on the mapping table (block414). For example, the calculation circuitry218determines the average and standard deviation for the instruction based on the average and standard deviation linked to (e.g., stored in association with) the mnemonic in an entry of the mapping data and determines the minimum and/or maximum execution cost using the above Equations 1-2. At block416, the example instruction conversion circuitry214determines if there is an additional instruction in the obtained program, code, and/or basic block to be processed.

If the example instruction conversion circuitry214determines that there is an additional instruction in the obtained program, code, and/or basic block (block416: YES), the example instruction conversion circuitry214selects the subsequent instruction (block418) and control returns to block406. If the example instruction conversion circuitry214determines that there is not an additional instruction in the obtained program, code, and/or basic block (block416: NO), the example calculation circuitry218determines the average and standard deviation of the executed program based on the execution cost averages and/or the minimum and maximum execution costs of the instructions of the program, code, and/or basic block (block420). For example, the calculation circuitry218determines the average and standard deviation of the execution cost for the program, code, and/or basic block using the above Equations 3-4. At block422, the example calculation circuitry218reports the execution cost to the CPU114and/or another device (e.g., via the component interface212) based on the average and standard deviation of the execution cost of the program, code, and/or basic block.

FIG. 5is a block diagram of an example processor platform500structured to execute and/or instantiate the machine readable instructions and/or operations ofFIGS. 3A, 3B and/or 4to implement the execution cost mapping table determination circuitry104and/or the basic block execution cost determination circuitry116ofFIG. 2. The processor platform500can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smart phone, a tablet such as an iPad), a personal digital assistant (PDA), an Internet appliance, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a gaming console, a personal video recorder, a set top box, a headset (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.) or other wearable device, or any other type of computing device.

The processor platform500of the illustrated example includes processor circuitry512. The processor circuitry512of the illustrated example is hardware. For example, the processor circuitry512can be implemented by one or more integrated circuits, logic circuits, FPGAs microprocessors, CPUs, GPUs, DSPs, and/or microcontrollers from any desired family or manufacturer. The processor circuitry512may be implemented by one or more semiconductor based (e.g., silicon based) devices. When the processor platform500is implemented in the example server102, the processor circuitry512implements the architecture-specific compiler(s)202, the instruction converter circuitry204, the cost determination circuitry208, and/or the component interface210. When the processor platform500is implemented in the example computing device108, the processor circuitry512implements the component interface212, the instruction conversion circuitry214, the cost estimation circuitry216, and the calculation circuitry218.

The processor circuitry512of the illustrated example includes a local memory513(e.g., a cache, registers, etc.). The processor circuitry512of the illustrated example is in communication with a main memory including a volatile memory514and a non-volatile memory516by a bus518. The volatile memory514may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and/or any other type of RAM device. The non-volatile memory516may be implemented by flash memory and/or any other desired type of memory device. Access to the main memory514,516of the illustrated example is controlled by a memory controller517. Any one of the example memory513,514,516may implement the example mapping table storage112and/or the example pair storage206ofFIG. 1 and/or 2.

The processor platform500of the illustrated example also includes interface circuitry520. The interface circuitry520may be implemented by hardware in accordance with any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, a Bluetooth® interface, a near field communication (NFC) interface, a PCI interface, and/or a PCIe interface. InFIG. 2, the example interface520implements the example network interface110ofFIG. 1and/or the example network interface200ofFIG. 2.

In the illustrated example, one or more input devices522are connected to the interface circuitry520. The input device(s)522permit(s) a user to enter data and/or commands into the processor circuitry512. The input device(s)522can be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a track-pad, a trackball, an isopoint device, and/or a voice recognition system.

The processor platform500of the illustrated example also includes one or more mass storage devices528to store software and/or data. Examples of such mass storage devices528include magnetic storage devices, optical storage devices, floppy disk drives, HDDs, CDs, Blu-ray disk drives, redundant array of independent disks (RAID) systems, solid state storage devices such as flash memory devices, and DVD drives.

The machine executable instructions532, which may be implemented by the machine readable instructions ofFIGS. 3A, 3B and/or 4, may be stored in the mass storage device528, in the volatile memory514, in the non-volatile memory516, and/or on a removable non-transitory computer readable storage medium such as a CD or DVD.

FIG. 6is a block diagram of an example implementation of the processor circuitry512ofFIG. 5. In this example, the processor circuitry512ofFIG. 5is implemented by a microprocessor600. For example, the microprocessor600may implement multi-core hardware circuitry such as a CPU, a DSP, a GPU, an XPU, etc. Although it may include any number of example cores602(e.g., 1 core), the microprocessor600of this example is a multi-core semiconductor device including N cores. The cores602of the microprocessor600may operate independently or may cooperate to execute machine readable instructions. For example, machine code corresponding to a firmware program, an embedded software program, or a software program may be executed by one of the cores602or may be executed by multiple ones of the cores602at the same or different times. In some examples, the machine code corresponding to the firmware program, the embedded software program, or the software program is split into threads and executed in parallel by two or more of the cores602. The software program may correspond to a portion or all of the machine readable instructions and/or operations represented by the flowcharts ofFIGS. 3A, 3B, and/or4

The cores602may communicate by an example bus604. In some examples, the bus604may implement a communication bus to effectuate communication associated with one(s) of the cores602. For example, the bus604may implement at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the bus604may implement any other type of computing or electrical bus. The cores602may obtain data, instructions, and/or signals from one or more external devices by example interface circuitry606. The cores602may output data, instructions, and/or signals to the one or more external devices by the interface circuitry606. Although the cores602of this example include example local memory620(e.g., Level 1 (L1) cache that may be split into an L1 data cache and an L1 instruction cache), the microprocessor600also includes example shared memory610that may be shared by the cores (e.g., Level 2 (L2_cache)) for high-speed access to data and/or instructions. Data and/or instructions may be transferred (e.g., shared) by writing to and/or reading from the shared memory610. The local memory620of each of the cores602and the shared memory610may be part of a hierarchy of storage devices including multiple levels of cache memory and the main memory (e.g., the main memory514,516ofFIG. 5). Typically, higher levels of memory in the hierarchy exhibit lower access time and have smaller storage capacity than lower levels of memory. Changes in the various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherency policy.

Each core602may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuitry. Each core602includes control unit circuitry614, arithmetic, and logic (AL) circuitry (sometimes referred to as an ALU)616, a plurality of registers618, the L1 cache620, and an example bus622. Other structures may be present. For example, each core602may include vector unit circuitry, single instruction multiple data (SIMD) unit circuitry, load/store unit (LSU) circuitry, branch/jump unit circuitry, floating-point unit (FPU) circuitry, etc. The control unit circuitry614includes semiconductor-based circuits structured to control (e.g., coordinate) data movement within the corresponding core602. The AL circuitry616includes semiconductor-based circuits structured to perform one or more mathematic and/or logic operations on the data within the corresponding core602. The AL circuitry616of some examples performs integer based operations. In other examples, the AL circuitry616also performs floating point operations. In yet other examples, the AL circuitry616may include first AL circuitry that performs integer based operations and second AL circuitry that performs floating point operations. In some examples, the AL circuitry616may be referred to as an Arithmetic Logic Unit (ALU). The registers618are semiconductor-based structures to store data and/or instructions such as results of one or more of the operations performed by the AL circuitry616of the corresponding core602. For example, the registers618may include vector register(s), SIMD register(s), general purpose register(s), flag register(s), segment register(s), machine specific register(s), instruction pointer register(s), control register(s), debug register(s), memory management register(s), machine check register(s), etc. The registers618may be arranged in a bank as shown inFIG. 6. Alternatively, the registers618may be organized in any other arrangement, format, or structure including distributed throughout the core602to shorten access time. The bus620may implement at least one of an I2C bus, a SPI bus, a PCI bus, or a PCIe bus

FIG. 7is a block diagram of another example implementation of the processor circuitry512ofFIG. 5. In this example, the processor circuitry512is implemented by FPGA circuitry700. The FPGA circuitry700can be used, for example, to perform operations that could otherwise be performed by the example microprocessor600ofFIG. 6executing corresponding machine readable instructions. However, once configured, the FPGA circuitry700instantiates the machine readable instructions in hardware and, thus, can often execute the operations faster than they could be performed by a general purpose microprocessor executing the corresponding software.

In the example ofFIG. 7, the FPGA circuitry700is structured to be programmed (and/or reprogrammed one or more times) by an end user by a hardware description language (HDL) such as Verilog. The FPGA circuitry700ofFIG. 7, includes example input/output (I/O) circuitry702to obtain and/or output data to/from example configuration circuitry704and/or external hardware (e.g., external hardware circuitry)706. For example, the configuration circuitry704may implement interface circuitry that may obtain machine readable instructions to configure the FPGA circuitry700, or portion(s) thereof. In some such examples, the configuration circuitry704may obtain the machine readable instructions from a user, a machine (e.g., hardware circuitry (e.g., programmed, or dedicated circuitry) that may implement an Artificial Intelligence/Machine Learning (AI/ML) model to generate the instructions), etc. In some examples, the external hardware706may implement the microprocessor600ofFIG. 6. The FPGA circuitry700also includes an array of example logic gate circuitry708, a plurality of example configurable interconnections710, and example storage circuitry712. The logic gate circuitry708and interconnections710are configurable to instantiate one or more operations that may correspond to at least some of the machine readable instructions ofFIG. 4-5and/or other desired operations. The logic gate circuitry708shown inFIG. 7is fabricated in groups or blocks. Each block includes semiconductor-based electrical structures that may be configured into logic circuits. In some examples, the electrical structures include logic gates (e.g., And gates, Or gates, Nor gates, etc.) that provide basic building blocks for logic circuits. Electrically controllable switches (e.g., transistors) are present within each of the logic gate circuitry708to enable configuration of the electrical structures and/or the logic gates to form circuits to perform desired operations. The logic gate circuitry708may include other electrical structures such as look-up tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.

The storage circuitry712of the illustrated example is structured to store result(s) of the one or more of the operations performed by corresponding logic gates. The storage circuitry712may be implemented by registers or the like. In the illustrated example, the storage circuitry712is distributed amongst the logic gate circuitry708to facilitate access and increase execution speed.

The example FPGA circuitry700ofFIG. 7also includes example Dedicated Operations Circuitry714. In this example, the Dedicated Operations Circuitry714includes special purpose circuitry716that may be invoked to implement commonly used functions to avoid the need to program those functions in the field. Examples of such special purpose circuitry716include memory (e.g., DRAM) controller circuitry, PCIe controller circuitry, clock circuitry, transceiver circuitry, memory, and multiplier-accumulator circuitry. Other types of special purpose circuitry may be present. In some examples, the FPGA circuitry700may also include example general purpose programmable circuitry718such as an example CPU720and/or an example DSP722. Other general purpose programmable circuitry718may additionally or alternatively be present such as a GPU, an XPU, etc., that can be programmed to perform other operations.

AlthoughFIGS. 6 and 7illustrate two example implementations of the processor circuitry512ofFIG. 5, many other approaches are contemplated. For example, as mentioned above, modern FPGA circuitry may include an on-board CPU, such as one or more of the example CPU720ofFIG. 7. Therefore, the processor circuitry512ofFIG. 5may additionally be implemented by combining the example microprocessor600ofFIG. 6and the example FPGA circuitry700ofFIG. 7. In some such hybrid examples, a first portion of the machine readable instructions represented by the flowcharts ofFIGS. 3A, 3B, and/or4may be executed by one or more of the cores602ofFIG. 6and a second portion of the machine readable instructions represented by the flowcharts ofFIGS. 3A, 3B, and/or4may be executed by the FPGA circuitry700ofFIG. 7.

In some examples, the processor circuitry512ofFIG. 5may be in one or more packages. For example, the processor circuitry600ofFIG. 6and/or the FPGA circuitry700ofFIG. 7may be in one or more packages. In some examples, an XPU may be implemented by the processor circuitry512ofFIG. 5, which may be in one or more packages. For example, the XPU may include a CPU in one package, a DSP in another package, a GPU in yet another package, and an FPGA in still yet another package.

A block diagram illustrating an example software distribution platform805to distribute software such as the example machine readable instructions532ofFIG. 5to hardware devices owned and/or operated by third parties is illustrated inFIG. 8. The example software distribution platform805may be implemented by any computer server, data facility, cloud service, etc., capable of storing and transmitting software to other computing devices. The third parties may be customers of the entity owning and/or operating the software distribution platform805. For example, the entity that owns and/or operates the software distribution platform805may be a developer, a seller, and/or a licensor of software such as the example machine readable instructions532ofFIG. 5. The third parties may be consumers, users, retailers, OEMs, etc., who purchase and/or license the software for use and/or re-sale and/or sub-licensing. In the illustrated example, the software distribution platform805includes one or more servers and one or more storage devices. The storage devices store the machine readable instructions532, which may correspond to the example machine readable instructions300,400ofFIGS. 3A, 3B and/or 4, as described above. The one or more servers of the example software distribution platform805are in communication with a network810, which may correspond to any one or more of the Internet and/or any example network. In some examples, the one or more servers are responsive to requests to transmit the software to a requesting party as part of a commercial transaction. Payment for the delivery, sale, and/or license of the software may be handled by the one or more servers of the software distribution platform and/or by a third party payment entity. The servers enable purchasers and/or licensors to download the machine readable instructions532from the software distribution platform805. For example, the software, which may correspond to the example machine readable instructions300,400ofFIGS. 3A, 3B and/or 4, may be downloaded to the example processor platform500, which is to execute the machine readable instructions532to implement the execution cost mapping table determination circuitry104. In some example, one or more servers of the software distribution platform805periodically offer, transmit, and/or force updates to the software (e.g., the example machine readable instructions532ofFIG. 5) to ensure improvements, patches, updates, etc., are distributed and applied to the software at the end user devices.

Example methods, apparatus, systems, and articles of manufacture to improve data quality for artificial intelligence are disclosed herein. Further examples and combinations thereof include the following: Example 1 includes an apparatus to generate a mapping table based on execution cost, the apparatus comprising memory, instructions included in the apparatus, and processor circuitry to execute the instructions to cause a plurality of instructions corresponding to a mnemonic to be executed, determine an average execution cost of the plurality of instructions, determine a standard deviation of execution costs of the plurality of instructions, and generate a mapping table including an entry, the entry including the mnemonic in association with the average and the standard deviation.

Example 2 includes the apparatus of example 1, wherein the processor circuitry is to cause the plurality of instructions to be executed on a processor unit specific to an architecture, the architecture corresponding to a computing device that obtains the mapping table to estimate execution cost.

Example 3 includes the apparatus of example 1, wherein the plurality of instructions is a first plurality of instructions, the processor circuitry is to convert a second plurality of instructions into mnemonics and operands, generate a converted instructions by replacing the operands with a token corresponding to the operands, and generate pairs by combining the instructions with the converted instructions.

Example 4 includes the apparatus of example 3, wherein the processor circuitry is to store the pairs in the memory, and access the first plurality of instruction corresponding to the mnemonic from the memory.

Example 5 includes the apparatus of example 3, wherein the processor circuitry is to determine whether a pair including at least one of a same mnemonic or a same operand is included in storage, and when the pair is already included in the storage, discard the pair.

Example 6 includes the apparatus of example 3, wherein the token corresponds to at least one of a constant type when the operand corresponds to a numeric constant or a register when the operand corresponds to a register operation.

Example 7 includes the apparatus of example 1, wherein the processor circuitry is to obtain the instructions from a repository, and convert the instructions into assembly language.

Example 8 includes a non-transitory computer readable medium comprising instructions which, when executed, cause one or more processors to at least cause a plurality of instructions corresponding to a mnemonic to be executed, determine an average execution cost of the plurality of instructions, determine a standard deviation of execution costs of the plurality of instructions, and generate a mapping table including an entry, the entry including the mnemonic in association with the average and the standard deviation.

Example 9 includes the computer readable storage medium of example 8, wherein the instructions cause the one or more processors to cause the plurality of instructions to be executed on a processor unit specific to an architecture, the architecture corresponding to a computing device that obtains the mapping table to estimate execution cost.

Example 10 includes the computer readable storage medium of example 8, wherein the plurality of instructions is a first plurality of instructions, the instructions to cause the one or more processors to convert a second plurality of instructions into mnemonics and operands, generate a converted instructions by replacing the operands with a token corresponding to the operands, and generate pairs by combining the instructions with the converted instructions.

Example 11 includes the computer readable storage medium of example 10, wherein the instructions cause the one or more processors to store the pairs in storage, and access the first plurality of instruction corresponding to the mnemonic from the storage.

Example 12 includes the computer readable storage medium of example 10, wherein the instructions cause the one or more processors to determine whether a pair including at least one of a same mnemonic or a same operand is included in storage, and when the pair is already included in the storage, discard the pair.

Example 13 includes the computer readable storage medium of example 10, wherein the token corresponds to at least one of a constant type when the operand corresponds to a numeric constant or a register when the operand corresponds to a register operation.

Example 14 includes the computer readable storage medium of example 8, wherein the instructions cause the one or more processors to obtain the instructions from a repository, and convert the instructions into assembly language.

Example 15 includes an apparatus to generate a mapping table based on execution cost, the apparatus comprising interface circuitry, and processor circuitry including one or more of at least one of a central processing unit, a graphic processing unit or a digital signal processor, the at least one of the central processing unit, the graphic processing unit or the digital signal processor having control circuitry, one or more registers, and arithmetic and logic circuitry to perform one or more first operations corresponding to instructions in the apparatus, and, a Field Programmable Gate Array (FPGA), the FPGA including logic gate circuitry, a plurality of configurable interconnections, and storage circuitry, the logic gate circuitry and interconnections to perform one or more second operations, or Application Specific Integrate Circuitry (ASIC) including logic gate circuitry to perform one or more third operations, the processor circuitry to perform at least one of the first operations, the second operations or the third operations to instantiate cost mapping circuitry to cause a plurality of instructions corresponding to a mnemonic to be executed, determine an average execution cost of the plurality of instructions, determine a standard deviation of execution costs of the plurality of instructions, and generate a mapping table including an entry, the entry including the mnemonic in association with the average and the standard deviation.

Example 16 includes the apparatus of example 15, wherein the cost mapping circuitry is to cause the plurality of instructions to be executed on a processor unit specific to an architecture, the architecture corresponding to a computing device that obtains the mapping table to estimate execution cost.

Example 17 includes the apparatus of example 15, wherein the plurality of instructions is a first plurality of instructions, further including instruction converter circuitry is to convert a second plurality of instructions into mnemonics and operands, generate a converted instructions by replacing the operands with a token corresponding to the operands, and generate pairs by combining the instructions with the converted instructions.

Example 18 includes the apparatus of example 17, wherein the instruction converter circuitry is to store the pairs in the storage, and the cost mapping circuitry is to access the first plurality of instruction corresponding to the mnemonic from the storage.

Example 19 includes the apparatus of example 17, wherein the cost mapping circuitry is to determine whether a pair including at least one of a same mnemonic or a same operand is included in storage, and when the pair is already included in the storage, discard the pair.

Example 20 includes the apparatus of example 17, wherein the token corresponds to at least one of a constant type when the operand corresponds to a numeric constant or a register when the operand corresponds to a register operation.

Example 21 includes the apparatus of example 15, further including an architecture-specific compiler to obtain the instructions from a repository, and convert the instructions into assembly language.

Example 22 includes an apparatus to generate a mapping table based on execution cost, the apparatus comprising means for identify a mnemonic of a plurality of instructions, means for generating a mapping table, the means for generating to cause the plurality of instructions corresponding to the mnemonic to be executed, determine an average execution cost of the plurality of instructions, determine standard deviation of execution costs of the plurality of instructions, and generate a mapping table including an entry, the entry including the mnemonic in association with the average and the standard deviation.

Example 23 includes the apparatus of example 22, wherein the means for generating is to cause the plurality of instructions to be executed on a processor unit specific to an architecture, the architecture corresponding to a computing device that obtains the mapping table to estimate execution cost.

Example 24 includes the apparatus of example 22, wherein the plurality of instructions is a first plurality of instructions, further including means for converting, the means for converting to convert a second plurality of instructions into mnemonics and operands, generate a converted instructions by replacing the operands with a token corresponding to the operands, and generate pairs by combining the instructions with the converted instructions.

Example 25 includes the apparatus of example 24, wherein the means for converting is to store the pairs in storage, and access the first plurality of instruction corresponding to the mnemonic from the storage.

Example 26 includes the apparatus of example 24, wherein the means for generating is to determine whether a pair including at least one of a same mnemonic or a same operand is included in storage, and when the pair is already included in the storage, discard the pair.

Example 27 includes the apparatus of example 24, wherein the token corresponds to at least one of a constant type when the operand corresponds to a numeric constant or a register when the operand corresponds to a register operation.

Example 28 includes the apparatus of example 22, further including means for converting, the means for converting to obtain the instructions from a repository, and convert the instructions into assembly language.

Example 29 includes a method to generate a mapping table based on execution cost, the method comprising causing a plurality of instructions corresponding to a mnemonic to be executed, determining, by executing an instruction with one or more processors, an average execution cost of the plurality of instructions, determining, by executing an instruction with the one or more processors, a standard deviation of execution costs of the plurality of instructions, and generating, by executing an instruction with the one or more processors, a mapping table including an entry, the entry including the mnemonic in association with the average and the standard deviation.

Example 30 includes the method of example 29, further including causing the plurality of instructions to be executed on a processor unit specific to an architecture, the architecture corresponding to a computing device that obtains the mapping table to estimate execution cost.

Example 31 includes the method of example 29, wherein the plurality of instructions is a first plurality of instructions, further including converting a second plurality of instructions into mnemonics and operands, generating a converted instructions by replacing the operands with a token corresponding to the operands, and generating pairs by combining the instructions with the converted instructions.

Example 32 includes the method of example 31, further including storing the pairs in the storage, and accessing the first plurality of instruction corresponding to the mnemonic from the storage.

Example 33 includes the method of example 31, further including determining whether a pair including at least one of a same mnemonic or a same operand is included in storage, and when the pair is already included in the storage, discarding the pair.

Example 34 includes the method of example 31, wherein the token corresponds to at least one of a constant type when the operand corresponds to a numeric constant or a register when the operand corresponds to a register operation.

Example 35 includes the method of example 29, further including obtaining the instructions from a repository, and converting the instructions into assembly language.

From the foregoing, it will be appreciated that example systems, methods, apparatus, and articles of manufacture have been disclosed that determine execution cost. To determine the execution cost of instructions, some techniques run the instructions prior to executing the instructions to identify the code execution. However, such techniques are expensive and time consuming. Other techniques have been used to estimate execution cost using models and/or other tools. However, such techniques may be inaccurate and/or require large maintenance overhead. Some techniques use artificial intelligence (AI) to predict the execution cost of a set of instructions. Although such techniques are accurate, such techniques are computationally intensive and AI-based techniques do not provide an explanation for a result.

Examples disclosed herein include a server that develops architecture-specific mapping tables that maps converted instructions (e.g., abstractions of instructions based on the leading mnemonic and/or function of an instruction line) to an average execution cost and standard deviation cost. Using examples disclosed herein, the server can obtain programs and/or basic blocks of code from storage (e.g., open-source repositories, crowd-sourced repositories, closed-source repositories, local storage, external stored, local databases, external databases, etc.), execute lines of the code to identify execution costs corresponding to the function and/or mnemonic of the line of code and map the mnemonic to the average execution cost and the standard deviation of the execution cost. Examples disclosed herein develops an approach that is accurate, explainable, and executes using less processor resources that the above-mentioned techniques. Thus, the disclosed systems, methods, apparatus, and articles of manufacture are accordingly directed to one or more improvement(s) in the operation of a machine such as a computer or other electronic and/or mechanical device.