Generic debug external connection (GDXC) for high integration integrated circuits

A high integration integrated circuit may comprise a plurality of processing cores, a graphics processing unit, and an uncore area coupled to an interface structure such as a ring structure. A generic debug external connection (GDXC) logic may be provisioned proximate to the end point of the ring structure. The GDXC logic may receive internal signals occurring in the uncore area, within the ring structure and on the interfaces provisioned between the plurality of cores and the ring structure. The GDXC logic may comprise a qualifier to selectively control the entry of the packets comprising information of the internal signals into the queue. The GDXC logic may then transfer the packets stored in the queues to a port provisioned on the surface of the integrated circuit packaging to provide an external interface to the analysis tools.

BACKGROUND

Advancements in integrated circuit process technology have enabled packing more circuitry or logic into the die space resulting in a highly integrated ICs (integrated circuits). An example of such highly integrated IC is one in which the memory controller, graphics processor, and multiple processing cores may be integrated in the same die. However, it is a highly challenging task to debug and validate a high integration integrated circuit due to low observability of internal signals at the external pins of the die or due to unavailability of internal signals, for example, front side bus, which is used as an interface between the integrated circuit and the peripherals. Such buses provided important hints about the internal signals, which enabled performing of root-cause analysis of many failures in the platform and the integrated circuit. The internal signals may provide an insight into the flow of the processor threads and operation of the functional units within the high integration integrated circuit. For example, the internal signals may provide failure data of the functional units such as the core area or uncore area of the high integrated ICs. Availability of such internal signals is critical for performing debug and validation of the high integrated ICs.

DETAILED DESCRIPTION

The following description describes embodiments of a technique to perform debugging and validation of a high integration integrated circuit. In the following description, numerous specific details such as logic implementations, resource partitioning, sharing, duplication implementations, types and interrelationships of system components, and logic partitioning or integration choices are set forth in order to provide a more thorough understanding of the present invention. It will be appreciated, however, by one skilled in the art that the invention may be practiced without such specific details. In other instances, control structures, gate level circuits, and full software instruction sequences have not been shown in detail in order not to obscure the invention. Those of ordinary skill in the art, with the included descriptions, will be able to implement appropriate functionality without undue experimentation.

Embodiments of the invention may be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the invention may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device).

For example, a machine-readable medium may include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other similar signals. Further, firmware, software, routines, and instructions may be described herein as performing certain actions. However, it should be appreciated that such descriptions are merely for convenience and that such actions in fact result from computing devices, processors, controllers, and other devices executing the firmware, software, routines, and instructions.

An embodiment of the processor100, which may support observability of internal signals to enable debug and validation of the highly integrated processor100is illustrated inFIG. 1. In one embodiment, the processor100may comprise a core area120, a graphics unit115, an uncore area180, and a signal support structure based on a distributed protocol such as, for example, a ring structure152. The description below is provided with reference to a processor100comprising a ring structure152provisioned to support communication between the core area120and the uncore area180. However, GDXC techniques described below may be used in other embodiments that comprise non-ring structures and GDXC techniques support debugging and validation of such high integration integrated processor as well.

In one embodiment, the core area120may comprise core110-A to110-K, which may be coupled to the uncore area180using interfaces126-A to126-K, respectively. In one embodiment, the core area120may comprise interface agents140-A to140-K. In one embodiment, the interface agent140-A may observe the internal signals transferred on the interface126-A and may send the signals in the form of data units or packets to the uncore area180. In one embodiment, the interface agents140-B to140-K may observe the signals transferred on the interfaces126-B to126-K, respectively, and send the data units to the uncore area180. In one embodiment, the graphics unit115may be coupled to the uncore area180using an interface116. In one embodiment, the interface agent140-M coupled to the interface116may observe the signals transferred on the interface116. In one embodiment, the interface agent140-M may capture the internal signals on the interface116and may generate data units or packets before sending the data units to the uncore area180.

In one embodiment, the uncore area180may couple the core area120to external system such as I/O system. In one embodiment, the uncore area180may supply data and code to the cores, handle system events such as interrupts, testability, and handle clock and power management. In one embodiment, the uncore area180may support integrated memory controller, integrated graphics controller, and interfaces to interconnects such as the peripheral component interconnect (PCI) express.

In one embodiment, the core interface151-A may support interface between the core110-A and the core interface151-A may support protocols to handle requests, responses, and data transfer between the core110-A and the uncore area180. In one embodiment, the cache interface152-A may handle requests for accessing the last level cache slice that are received from the core110-A or other external requestors. In one embodiment, the cache interface152-A may maintain cache coherency and may serve as a caching agent as well. In one embodiment, the ring interface153-A may provide an interface to the ring152(comprising paths155and156). In one embodiment, the ring interface153-A may couple the interface end block150-A to the system agent SA168. In one embodiment, the ring interface153-A may be shared by the core interface151-A and the cache interface152-A.

In one embodiment, the uncore area180may comprise one or more interface end blocks150-A to150-M, a system agent160, and a DV port interface190. In one embodiment, the interface end blocks150-A to150-M may be coupled to each other, for example, by a ring152comprising paths155and156. In one embodiment, the interface end block150-A may comprise a core interface151-A, a cache interface152-A, and a ring interface153-A. In one embodiment, the interface end blocks150-B to !50-M may each comprise (core interface151-B, cache interface152-B, ring interface153-B), (core interface151-K, cache interface152-K, ring interface153-K), and (core interface151-M, cache interface !152-M, ring interface153-M).

In one embodiment, the core110-A may send an access request to access last level cache (LLC) slice associated with the interface end block150-A. In one embodiment, the core interface151-A and152-A, in response to receiving the access request, may establish a connection, directly, with the cache interface152-A. In one embodiment, the core interface151-A and the cache interface152-A may generate data units or packets that may comprise information of the transactions that occur between the core interface151-A and the cache interface152-A. In one embodiment, the interface end block150-A may send such data units to the system agent160.

In one embodiment, the core110-A may send a read request to the interface end block150-A to read data from the last level cache slice associated with the interface end block150-K. In one embodiment, the core interface151-A of the interface end block150-A may request the ring interface153-A to send the read request to the interface end block150-K over the path156of an address and control portion of the ring152. In one embodiment, the address and control ring portion of the ring152may support both coherent and non-coherent transactions. In one embodiment, the ring interface153-K may communicate with the cache interface152-K to access the LLC slice associated with the interface end block150-K to retrieve the data requested for. In one embodiment, the cache interface !52-K may transfer the data to the ring interface153-K and the ring interface153-K may send the data (response) to the ring interface153-A on the data ring portion of the ring152. In one embodiment, the ring interface153-A may communicate with the core interface151-A to provide the data requested by the core110-A. In one embodiment, the data portion of the ring may support data transfers and non-coherent transactions. In one embodiment, the interface end block150-A and150-K may exchange acknowledgements or other hand-shake signals on the acknowledgement and global observation portion of the ring152.

In one embodiment, the interface end blocks150-A to150-M may send data units or packets that comprise information of the events or transactions that occur while transferring cache requests, I/O writes, acknowledgements, interrupts, power management transactions, log of architectural events such as a write to status registers and branch trace messages to the system agent160. Also, in one embodiment, the data units may comprise information of power management transactions and states, message channel transfers, and such other information.

In one embodiment, the system agent160may comprise a ring stop interface163, a memory control and peripheral control hub (MCPC) hub165, a power management block166, a msg-Ch block167, and a GDXC logic168. In one embodiment, the system agent160may comprise clock domains such as the uncore clock (UCLK), FCLK, and LCLK. In one embodiment, the system agent160may be provisioned at the end of the ring such that the GDXC logic168is enabled to observe internal signals of the processor100. In one embodiment, the GDXC logic168may observe internal signals, which may comprise transactions, or events, or signals transferred between the core area120, graphics unit115and the uncore area180over the interfaces116and126, transactions within the interface end blocks150, transactions on the paths155and156of the ring152, power management transactions and states generated by the PM block166, time stamped signals, and access signals to the registers in the uncore area180generated by the Msg-Ch block167.

In one embodiment, the MCPC hub165may comprise a memory controller and a non-coherent traffic control unit, which may be provided with a FCLK. In one embodiment, the MCPC hub165may comprise peripheral and I/O devices controller, which may be provided with LCLK. In one embodiment, the ring stop interface163and the GDXC logic168may be provided with UCLK.

In one embodiment, the ring stop interface163may couple the system agent180to the ring152. In one embodiment, the ring stop interface163may transfer the data units received from the interfaces116and126, interface agents140-A to140-M, paths155and156, the interface end points150-A to150-M, and such other sub-functional units with the graphics unit115, the core area120, and the uncore area180to the GDXC logic168.

In one embodiment, the GDXC logic168may collect the data units received from the ring stop interface163and may filter the data units before storing the filtered in data units in memory spaces such as queues. In one embodiment, the GDXC logic168may collect the data units in a non-intrusive manner. In one embodiment, the GDXC logic168may collect the data units in an intrusive manner as well. In one embodiment, the GDXC logic168may collect the data in a condensed manner using packets. In one embodiment, the generic debug external connection logic may pack N internal signals into a packet before sending the packet to an external analysis tool. In one embodiment, the packet may comprise a collection of signals or transactions in a specific format. In one embodiment, the GDXC logic168, the GDXC port interface190, and an external logic analyzer tool may use the same packet format. In one embodiment, the GDXC logic168may provide the data units to the GDXC port interface190. In one embodiment, the GDXC logic168provisioned at the end of the ring152may enable observability of the internal signals. In one embodiment, observing the internal signals and transferring the internal signals to the analysis tools and devices through an external debug port may facilitate debug and validation of the high integration integrated circuits such as the processor100. In one embodiment, the GDXC logic168may be programmed using a programming port.

In one embodiment, the GDXC logic168may provide observability of ring structure comprising150-A,150-B,150-K and150-M and the paths155and156. In one embodiment, the GDXC logic168may provide observability on one or more sub-rings of the paths155and156. In one embodiment, the GDXC168may provide observability of Address and Control (AD) sub-ring used to support transfer of address and control information and coherent transactions, a BL sub-ring sub-ring used support transfer of data units and non-coherent transactions, an AK sub-ring used to support transfer of acknowledgements and global observation transactions, and a IV sub-ring used to support transfer of interrupts and lock transactions.

In one embodiment, the GDXC logic168may provide observability of in-die interface (IDI) paths such as the paths116,126-A to126-K. In one embodiment, the amount of traffic on IDI paths116and126-A to126-K may be heavy and the heavy traffic may be filtered by the agents140to generate a subset of the heavy traffic. In one embodiment, the subset of the heavy traffic may be sent over a bus such as MCI bus and received by the GDXC logic168. In one embodiment, the transfer of subset over the MCI bus may not interfere with the ring transactions providing non-intrusive observability.

In one embodiment, the GDXC logic168may provide observability of power management transactions and states. In one embodiment, the GDXC logic168may provide visibility of the power management components such as PCode (power control unit PCU firmware), power management (PM) link such as PM upstream and PM downstream, and serial VID (SVID) commands. In one embodiment, the GDXC logic168may provide observability of message channel transfers by capturing transactions or transfers on the message channel. In one embodiment, observability of the message channel transfers may provide observability of UNCORe configuration register accesses and backbone operations on the buses of the system agent160.

In one embodiment, the GDXC logic168may provide observability of failure scenario by providing observability of signals that occurred prior to the failure, during the failure, and after the failure. In one embodiment, the GDXC packet format with a time-stamp technique may allow alignment of events based on time and may enable debugging of the failure scenario. In one embodiment, the GDXC logic168may enable debugging of external interfaces to the processor100. In one embodiment, the architecture of the debug logic168and the position at which the debug logic168is provisioned may allow observability of transactions on the interfaces116,126-A to126-K, ring152, message channels, power management sequences and such other internal signals. Such internal signals may provide an insight into the operation of the functional units within the processor100and may provide information such as coreID, threadID, cache attributes, memory ordering, special cycles, code flow, power management, live lock, dead lock, true misses to the cache, uncacheable traffic, I/O traffic, snoop activity, non-coherent traffic, interrupts and such other information. Also, in one embodiment, the position of the debug logic168enables the debug logic168to watch the ring152for protocol correctness.

An embodiment of a high integration integrated circuit package200, which may support debugging and validation of high integration integrated circuit is illustrated inFIG. 2. In one embodiment, a high integration high integrated circuit may comprise a memory controller, a graphics processing unit, and a multiple processing cores integrated on the same die. As a result of such high integration, accessing internal signals for debugging and validation of the processor becomes a challenge. In one embodiment, the package200may comprise an external packing210, a processor230, a topside debug and validation (DV) port250, a debug and validation (DV) cable260, a debug and validation (DV) connector265, a program cable270, a programming port275, and a logic analyzer280.

In one embodiment, the processor230may support a GDXC logic, which may observe, collect, and process the internal signals from the functional or sub-functional areas within the processor230. In one embodiment, the program cable270and programming port275may be used to program the GDXC logic of the processor230.

In one embodiment, the external packing210may support the DV port250and the processor230may use the DV port250to provide the internal signals to the external analysis tools such as the logic analyzer280. In one embodiment, the DV port250may be provisioned on the topside of the external packing210, which may allow the DV port250to be accessed with ease. However, in other embodiments, the DV port250may be provisioned on other surfaces of the external packing210as well. In one embodiment, the DV port250may share PCIe lanes or DDR channels, for example.

An embodiment of the operation of the GDXC logic168to enable debugging and validation of high integration integrated circuits such as the processor100is illustrated in a flow-chart ofFIG. 3.

In block310, the GDXC logic168may receive the data units comprising information of the internal signals from the functional units of the high integration integrated circuit. In one embodiment, the GDXC logic168may receive data units from the interface agents140-A to140-M, interface end blocks150-A to150-M, ring portions such as the address and control (AD) sub-ring, BL sub-ring, acknowledgment (AK) sub-ring, and interrupt (IV) sub-ring In one embodiment, the GDXC logic168may receive data units comprising information of the traffic on IDI interfaces116and126-A to126-K, message channel transfers, power management transactions and states such as PCU firmware, PM link, and SVID commands, failure scenarios, and such other sources.

In block330, the GDXC logic168may route the data units to one of the filters/qualifiers based on the source that generated the data units. In one embodiment, the data units that are generated by the interface agents140-A to140-M may be routed to a one filter and the data units generated by a portion of the ring152may be routed to a second filter/qualifier.

In block350, the GDXC logic168may filter-in the data units that are essential for debugging and validating the functional units. In one embodiment, the GDXC logic168may look into the contents of the data units before determining whether to store the data units or to filter out the data units. In one embodiment, the GDXC logic168may determine whether the contents of the data units may be used for debugging and validating the processor100.

In block360, the GDXC logic168may store the filtered-in data units in a queue associated with the filter/qualifier. In one embodiment, the GDXC logic168may comprise a qualifier-queue combination for each type of data units. In one embodiment, the qualifiers may be used to select the data units such that the queues have memory space to store the data units without causing overflow. In one embodiment, the number of data units selected by the qualifier may depend on the bandwidth of the queues and the ports used to store and transfer data units. In one embodiment, if the qualifiers may avoid overflow of data units and thus avoid missing of failure information.

In block380, the GDXC logic168may provide the data units stored in the queues to the DV interface190. In block390, the data units provided to the external tools may be used to perform debugging and validation of the high integration integrated circuit.

An embodiment of the GDXC logic168, which may observe, capture and transfer internal signals to facilitate debugging and validation of high integration integrated circuit is illustrated inFIG. 4. In one embodiment, the GDXC logic168may comprise a uncore interface410, address ring observer415, data ring observer425, acknowledgement ring observer435, interrupt ring observer445, in-die-interface (IDI) observer455, power management (PM) and message channel (MC) PMMC observer465, multiplexers MUX485to489, a control unit492, and a port control unit495. In one embodiment, the GDXC logic168may operate on uncore clock (UCLK) provided by the clock domain of the uncore area180.

In one embodiment, the uncore interface410may receive the data units or packets from different functional units of the processor100and route the data units to one of the observer blocks415,425,435,445,455, or465. In one embodiment, the uncore interface410may receive data units from the interface agents140-A to140-M, interface end blocks150-A to150-M, portions of the ring152, power management block and message channels and forward the data units to one of the observer blocks415-465. In one embodiment, the uncore interface410may receive data units generated by the AD, BL, AK, and IV sub-rings of the ring152and may forward the data units to the observers415to445, respectively. In one embodiment, the uncore interface410may receive data units transferred on IDI interfaces116and126-A to126-K and forward the data units to the In-die interface (IDI) observer455. In one embodiment, the uncore interface410may receive data units comprising information of a power management sequence and message channeling and may forward the data units to the PMMC observer465.

In one embodiment, the address ring observer415may comprise a qualifier416and a queue418. In one embodiment, the qualifier416may control the entry of data units into the queue418based on the contents of the data unit and the usefulness of contents of the data unit for debugging and validation of the high integration integrated circuit such as the processor100. In one embodiment, the qualifier416may affix a time stamp to the data units that are allowed to enter the queue418. Similarly, the data units received from BL, AK, IV sub-rings, IDI interfaces, power management and message channel may be selected by the qualifiers426to466, respectively. In one embodiment, the qualifiers426to466may add timestamp to the data units before storing the selected data units in the queues418to468, respectively. In one embodiment, affixing time stamps to data units stored in the queues418to468may enable the processor100to be immune to latency. In one embodiment, the size of the data unit that may be stored in the queues418to468may equal 32 bits, 64 bits, 96 bits, or 128 bits. In one embodiment, the data units stored in the queues418to468may be sent over X16 PCIe lanes.

In one embodiment, the MUX485-489may allow selection of data units from the queues418to468. In one embodiment, the output of the MUX489may be provided as an input to a memory496of the port control unit495. In one embodiment, the MUX485to489may be used to control the transfer of the data units from the queues418to468to a bubble generator first-in first-out (FIFO) BGF494.

In one embodiment, the control unit492may control the selection and time stamping operations of the qualifiers416to466. In one embodiment, the control unit492may support post-processing software, which may layout the data units in a chronological order based on the time stamp associated with the data units. In one embodiment, the control unit CU492may generate the select inputs to the MUX485to489based on arbitration logic that may control the manner and the order of the data units that may be evicted from the queues418to468. In one embodiment, the control unit492may control outflow of the data units from the queues418to468by using techniques such as arbitration and multiplexing. In one embodiment, the control unit492may use arbitration logic such as a weighted round robin technique for slow protocols (e.g., power management) and in-order arbitration technique for fast protocols (e.g., ring). In one embodiment, the data units stored in the BGF494may be transferred to the GDXC port interface190a port495.

An embodiment of an interface technique to convert the GDXC internal packet format to a known interface format to allow seamless interface to the logic analyzer is illustrated inFIG. 5. In one embodiment, the data units stored in the BGF494may be transferred to logic analyzer280through the port495. However, the internal GDXC packet format may be converted into a known interface format, which may be processed by the logic analyzer280. In one embodiment, the packet format may be based on a robust protocol. For example, a packet format based on the robust protocol may comprise a start field and an end field. In one embodiment, the start field may comprise bits such as a start bit, packet size, and time stamp, for example.

In one embodiment, the BGF494and the port495may use credit based protocol to transfer data units from the BGF494to the port495. In one embodiment, the packets stored in the BGF494may be transferred on, for example, PCIe transmit lanes. In one embodiment, the port495may communicate with the GDXC physical layer using a credit based handshake protocol. In one embodiment, each time a 128 bit data unit or 4 chunks of 32 bit data is sent out on an interconnect such as a PCIe transmit lanes595-A to595-N from the BGF494, a space for storing an entry in the BGF494is available. In one embodiment, the BGF494may cause a credit pulse510to be sent to the control unit492indicating that an entry from the queues418to468may be delivered to the BGF494. In one embodiment, the credit pulse on path510may initiate a transfer of n×4 chunks to the top of the BGF494. In one embodiment, if the size of the data unit or a packet exceeds 128-bit or the 4thchunk, the port control570may automatically wrap around the data unit to the next symbol clock.

In one embodiment, in order to increase the robustness of a communication channel between the GDXC port495to the logic analyzer280, a cyclic redundancy check (CRC) packet is 128-bit aligned. In one embodiment, to avoid wrap around, the CRC packet may start at lane0of the PCI-e transmit lanes and the size of the packet is 128 bits. In one embodiment, the fixed location of the start of the CRC packet at lane0allows the logic analyzer280to be identified with ease. In one embodiment, the port control570may generate a ‘Request Unbroken’ signal520, which may be sent to the control unit492. In one embodiment, the port control570may send the ‘Request Unbroken’ signal520each time the CRC packet is inserted. In one embodiment, the ‘Request Unbroken’ signal520is generated by the port control570to avoid a CRC packet breaking a 128-bit data unit. In one embodiment, the port control570may receive an ‘Unbroken’ signal540and may insert a CRC packet in response to receiving the ‘Unbroken’ signal540. In one embodiment, the port control570may arrange the chunks in an order before delivering the ordered chunks on the interconnect PCIe lanes595. In one embodiment, the port control570may cause the data units or chunks to be delivered to the GDXC port interface190. In one embodiment, the PCIe lanes595may operate at rates of a Gen2(5 gigahertz) or Gen1(2.5 gighertz).

In one embodiment, in response to receiving the ‘Request Unbroken’ signal520, the control unit494may cause the 4 chunks or 128-bit packet from the BGF494to be delivered and may then send a ‘Valid’ signal550. In one embodiment, the control unit492may send an ‘Unbroken’ signal on540while the data unit is 128-bit aligned. In one embodiment, the port control570may insert a periodic time synchronization packet such as COM/Skip/Skip/Skip in PCI-e standard. In one embodiment, the CRC and COM/SKP/SKP/SKP may be optionally handshaked between the port495and the control unit492to ensure higher reliability of communication between the GDXC logic168and the logic analyzer280.

Certain features of the invention have been described with reference to example embodiments. However, the description is not intended to be construed in a limiting sense. Various modifications of the example embodiments, as well as other embodiments of the invention, which are apparent to persons skilled in the art to which the invention pertains are deemed to lie within the spirit and scope of the invention.