MEMORY, METHOD FOR MANUFACTURING MEMORY, AND ELECTRONIC DEVICE

Disclosed is a memory, a method for manufacturing the memory. The memory includes: one or more layers of memory cell arrays stacked in a direction perpendicular to a substrate; a plurality of wordlines that penetrate through one or more layers of the memory cell arrays; and a plurality of bitlines, wherein each memory cell includes a semiconductor layer that surrounds a sidewall of the wordline and extends along the sidewall and each bitline is connected to the semiconductor layers of a column of memory cells in one layer of the memory cell array, wherein the bitline is composed of different branch lines, and the semiconductor layer of each memory cell is connected to two adjacent first branch lines but is not connected to at least a part of the region of the second branch line between the two adjacent first branch lines.

TECHNICAL FIELD

The embodiments of the present disclosure relate to the field of semiconductor technologies, and in particular, to a memory, and a method for manufacturing the memory.

BACKGROUND

With the development of integrated circuit technology, the critical dimensions of devices continue to shrink, and the variety and number of devices on a single chip are increased, which poses ever-greater challenges to device performance.

SUMMARY

Embodiments of the present disclosure provide a memory, and a method for manufacturing the memory.

According to some embodiments, a memory is provided. The memory includes one or more layers of memory cell arrays stacked in a direction perpendicular to a substrate, wherein each layer of the memory cell array includes a plurality of memory cells; a plurality of wordlines that penetrate through one or more layers of the memory cell arrays; and a plurality of bitlines, wherein each memory cell includes a semiconductor layer that surrounds a sidewall of the wordline and extends along the sidewall and each bitline connected to the semiconductor layers of a column of memory cells in one layer of the memory cell array, wherein the bitline includes a plurality of first branch lines and a plurality of second branch lines, with one second branch line connected between every two adjacent first branch lines; the semiconductor layer of each memory cell is connected to two adjacent first branch lines but is not connected to at least a part of a region of the second branch line between the two adjacent first branch lines.

In some embodiments, a region of the semiconductor layer between two adjacent first branch lines is disposed opposite to the second branch line between the two adjacent first branch lines.

In some embodiments, the second branch line includes all or part of a region of the bitline directly facing the semiconductor layer, and insulation material is filled between the region of the second branch line directly facing the semiconductor layer and the semiconductor layer; the insulation material is filled between the region of the semiconductor layer between the two adjacent first branch lines and the oppositely positioned second branch line.

In some embodiments, the wordline is disposed opposite to the second branch line, and there is an overlapping area between projections of the wordline surrounded by the semiconductor layer and the oppositely positioned second branch line on a plane perpendicular to the substrate, wherein the plane perpendicular to the substrate extends along a column direction of one column of memory cells.

In some embodiments, there is no overlapping area between projections of the wordline and the first branch line on the plane perpendicular to the substrate.

In some embodiments, each first branch line includes side surfaces and end surfaces, and the semiconductor layer is connected to at least one of the end surfaces and the side surfaces of two adjacent first branch lines, respectively.

In some embodiments, the second branch line is provided with a via hole penetrating through an upper surface and a lower surface or a hole on the upper surface, wherein a dielectric layer is filled within the via hole or the hole.

In some embodiments, each first branch line extends along the direction perpendicular to the substrate and exhibits a polygonal structure from a cross-sectional view along a plane parallel to the substrate, both ends of each second branch line are respectively connected to bending points of two adjacent first branch lines, and the semiconductor layer of each memory cell is connected to one end of two adjacent first branch lines, respectively.

In some embodiments, each memory cell further includes two first conductive layers connected respectively to the semiconductor layer and a second conductive layer connected to two first conductive layers, wherein a region of the semiconductor layer of each memory cell surrounded by two first conductive layers is disposed opposite to the second conductive layer, and an insulation material is filled between the region of the semiconductor layer of each memory cell surrounded by two adjacent first conductive layers and the second conductive layer.

In some embodiments, the second conductive layer extends in the direction perpendicular to the substrate and exhibits a U-shaped structure from a cross-sectional view along a plane parallel to the substrate, and both the first conductive layer and the second conductive layer include side surfaces and end surfaces, wherein the end surfaces of two first conductive layers of each memory cell are connected respectively to the two end surfaces of the second conductive layer.

In some embodiments, each memory cell further includes a third conductive layer connected to inner walls on both sides of the second conductive layer near the end surface.

In some embodiments, inner and outer walls of the U-shaped structure of the second conductive layer are respectively connected to a fourth conductive layer.

In some embodiments, each layer of the memory cell array includes a first column of memory cells and a second column of memory cells, and a plurality of bitlines include a first bitline and a second bitline, wherein the semiconductor layers in the first column of memory cells are connected to the first bitline, and the semiconductor layers in the second column of memory cells are connected to the second bitline; the first bitline and the second bitline are disposed between the first column of memory cells and the second column of memory cells, and the first bitline and the second bitline share one second branch line.

According to some embodiments, a memory is provided. The memory includes: one or more layers of transistor arrays stacked in a direction perpendicular to a substrate, wherein each layer of the transistor array includes a plurality of transistors; a plurality of wordlines that penetrate through one or more layers of the transistor arrays; and a plurality of bitlines, wherein each transistors includes a channel surrounding the wordline and a drain connected to the channel, and each bitline is connected to the drains of a column of transistors in one layer of the transistor array; wherein an insulation material is filled between a first channel region of the channel of each transistor and a first bitline region of the bitline, wherein the first channel region refers to a region of the channel directly facing the bitline, and the first bitline region refers to a region of the bitline directly facing the channel. It can be interpreted as that the second branch line includes all or part of a region of the bitline directly facing the semiconductor layer, and an insulation material is filled between the region of the second branch line directly facing the semiconductor layer and the semiconductor layer.

In some embodiments, the memory further includes a plurality of capacitors, and each transistor further includes a source connected to the channel, wherein the source of each transistor is connected to a first electrode of one capacitor, and insulation material is filled between a second channel region of the channel of each transistor and a first electrode region of the first electrode, wherein the second channel region refers to a region of the channel directly facing the first electrode, and the first electrode region refers to a region of the first electrode directly facing the channel.

In some embodiments, the first electrode is of a U-shaped structure, and an open end of the first electrode is connected to the source.

In some embodiments, the memory further includes a plurality of third conductive layers, wherein each third conductive layer is connected to inner walls on both sides of the first electrode near the open end.

In some embodiments, each bitline includes a plurality of first bitline segments and a plurality of second bitline segments, with one second bitline segment connected between every two adjacent first bitline segments; the first channel region of each transistor directly faces one second bitline segment.

According to some embodiments, a method for manufacturing a memory is provided, wherein the memory is the memory provided according to any one of the above embodiments, and the method includes: providing the substrate; forming, on the substrate, a plurality of conductor layers and a plurality of isolation layers alternately stacked in the direction perpendicular to the substrate as well as a plurality of dummy wordlines that penetrate through a plurality of the conductor layers and a plurality of the isolation layers; metallizing each conductor layer to form a plurality of the first branch lines in each conductor layer, with every two adjacent first branch lines connected to one dummy wordline; filling an insulation material in semi-enclosed regions surrounded by each dummy wordline and two adjacent first branch lines; connecting a plurality of the first branch lines in each conductor layer to form second branch lines disposed between every two adjacent first branch lines; and etching away each dummy wordline and forming a plurality of the wordlines and the semiconductor layers surrounding each wordline.

In some embodiments, the conductor layer is made of silicon; prior to metallizing the each conductor layer, the method further includes: etching a plurality of the conductor layers and a plurality of the isolation layers to form passages that penetrate through a plurality of the conductor layers and a plurality of the isolation layers and are disposed on both sides of each dummy wordline, with parts of each dummy wordline in the conductor layer exposed to the passages; and metallizing the each conductor layer to form the plurality of the first branch lines in the each conductor layer, with the every two adjacent first branch lines connected to the one dummy wordline, includes: depositing a metal film on an inner wall of the passage; and annealing the metal film to metallize the silicon on a surface of the conductor layer, resulting in a plurality of the first branch lines in each conductor layer.

In some embodiments, upon metallizing each conductor layer, two first conductive layers connected to each dummy wordline as well as a second conductive layer connected to two first conductive layers are further formed in each conductor layer, wherein the second conductive layer extends in the direction perpendicular to the substrate and exhibits a U-shaped structure from a cross-sectional view, and end faces of two first conductive layers connected to each dummy wordline are connected respectively to two end surfaces of one second conductive layer; connecting the plurality of the first branch lines in the each conductor layer to form the second branch lines disposed between the every two adjacent first branch lines, includes: etching a plurality of the conductor layers and a plurality of the isolation layers to form a plurality of first through holes that penetrate through a plurality of the conductor layers and a plurality of the isolation layers and are disposed between every two adjacent first branch lines, with an inner wall of the second conductive layer exposed; depositing a first metal layer on an inner wall of each first through hole and an inner wall of each second conductive layer near the first conductive layer; and etching the first metal layer disposed on each isolation layer and retaining the first metal layer disposed on each conductor layer to obtain a plurality of second branch lines and a plurality of third conductive layers disposed on each conductor layer.

In some embodiments, filling the insulation material in the semi-enclosed regions surrounded by the each dummy wordline and the two adjacent first branch lines, includes: etching a plurality of the conductor layers and a plurality of the isolation layers to form a plurality of second through holes that penetrate through a plurality of the conductor layers and a plurality of the isolation layers and are disposed in the semi-enclosed regions surrounded by each dummy wordline and two adjacent first branch lines, with both inner and outer walls of the second conductive layer exposed; etching away the silicon of each conductor layer in a plurality of the conductor layers; and depositing an insulation material in gaps between a plurality of the conductor layers and a plurality of the isolation layers after being etched, such that the insulation material is filled between the semi-enclosed regions surrounded by each dummy wordline and two adjacent first branch lines in each conductor layer as well as regions between each dummy wordline and two first conductive layers.

In some embodiments, etching away each dummy wordline and forming the plurality of the wordlines and the semiconductor layers surrounding each wordline, includes: etching away a plurality of the dummy wordlines to form a plurality of third through holes that penetrate through a plurality of the conductor layers and a plurality of the isolation layers; sequentially depositing a channel layer, a second dielectric layer, and a second metal layer on an inner wall of each third through hole to form a semiconductor layer, a gate insulating layer, and a plurality of the wordlines for each memory cell; and etching the channel layer disposed on each isolation layer to expose the second dielectric layer disposed on each isolation layer.

According to some embodiments, an electronic device is provided. The electronic device includes the memory provided according to any one of the above aspects.

In some embodiments, the electronic device includes a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device, or a smart mobile terminal.

REFERENCE NUMERALS

DETAILED DESCRIPTION

For clearer descriptions of the objects, technical solutions, and advantages of the present disclosure, embodiments of the present disclosure are further described in detail below with reference to the accompanying drawings.

Before interpreting and explaining the embodiments of the present disclosure, the application scenario of the embodiments of the present disclosure needs to be clarified first. The embodiments disclosed herein can be used in the field of semiconductor technologies, specifically in the field of memories. Any product in the memory field that includes transistors with the following characteristics falls within the protection scope of the present disclosure. The characteristics of the transistor at least include: the channel is arranged horizontally, with wordlines or gates extending vertically and surrounded by a semiconductor layer; the bitline is connected to the semiconductor layer, and the extension directions of the wordlines and bitlines are perpendicular to each other; the bitline is connected to the semiconductor layer through two branches; and the insulating layer is arranged between the bitline and the semiconductor layer and is surrounded by the bitline and branches, which reduces the contact area between semiconductor layer and the bitline, thereby reducing the parasitic capacitance.

Take memory as an example, in dynamic random access memory (DRAM) including one or more layers of memory arrays, and each layer of memory array includes a plurality of memory cells. Regardless of whether the memory array is two-dimensional or 3D, or whether the memory cell is 1T or 2T, DRAM always exhibits a certain degree of parasitic capacitance, especially between bitlines and wordlines, or between the capacitor electrode and wordlines. For example, in a 1T1C memory cell of DRAM, the memory cell includes a transistor and a capacitor. As shown inFIG.1, a wordline (WL) extends in a direction perpendicular to the substrate. The channel of the transistor surrounds the periphery of the WL. One side of the channel is connected to a first conductive pillar, which serves simultaneously as the source of the transistor and the first electrode of the capacitor. The other side of the channel is connected to a second conductive pillar, which serves simultaneously as the drain of the transistor and the bitline (BL). However, the parasitic capacitance between the WL and the BL in the structure shown inFIG.1can be further improved.

The embodiments disclosed herein are primarily illustrated using 3D DRAM as an example. As technology evolves, the miniaturization of DRAM has approached its limit. To achieve higher-density DRAM, 3D stacking is an important direction for development. 3D DRAM refers to stacking memory cells on a substrate to effectively reduce the cost of DRAM. 3D DRAM includes multiple layers of stacked memory cell arrays. Each layer of memory cell array includes a plurality of memory cells. These memory cells can be of various types, such as 1T1C, 1T0C, 2T1C, or 2T0C, which is not limited in the embodiments disclosed herein. A 2T0C memory cell includes two transistors, and data storage and read/write operation control are respectively accomplished through the gates of the two transistors. A 2T1C memory cell can be seen as a 2T0C memory cell with an added capacitor. However, the capacitor is not for storing data as 1 or 0 but for improving the degradation of the gate threshold voltage of the two transistors. Therefore, the 2T1C memory cell can also be seen as a different embodiment of the 2T0C memory cell. The capacitor in the memory provided according to the subsequent embodiments disclosed herein is the capacitor for storing data as 1 or 0. In addition, 1T1C-3D DRAM based on a horizontal channel surround structure greatly enhances the design flexibility of 3D DRAM due to the compatibility of channel material deposition technology with other processes. However, in such a type of memory, the parasitic capacitance between wordlines and bitlines, as well as between wordlines and the capacitor electrodes, needs to be further reduced. This reduction leads to a decrease in noise and signal interference caused by parasitic capacitance. Therefore, it is necessary to optimize the structure and fabrication process to ensure the stability and reliability of 3D DRAM during operation.

FIG.1is a schematic cross-sectional diagram of a memory cell in a 3D DRAM. As shown inFIG.1, the channel directly facing the BL is entirely in direct contact with the BL, allowing for further improvement in the parasitic capacitance between the WL and the BL. In addition, the channel directly facing the first electrode of the capacitor is also entirely in direct contact with the first electrode, also allowing for further improvement in the parasitic capacitance between the WL and the first electrode of the capacitor. Based on this, the embodiments disclosed herein provide a memory, a method for manufacturing the memory, and an electronic device that aims at improving the parasitic capacitance of DRAM.

FIGS.2to8show a type of memory that reduces the parasitic capacitance of DRAM according to some embodiments of the present disclosure.FIG.2is a structural schematic diagram of a memory according to some embodiments of the present disclosure. InFIG.2, the lower diagram is a cross-sectional view of the memory cut along a plane parallel to the substrate0, and the upper diagram is a three-dimensional view of the two memory cells in the first horizontal row depicted in the lower diagram. As shown inFIG.2, in some embodiments, the memory includes one or more layers of memory cell arrays stacked in a direction perpendicular to the substrate0, withFIG.2showing one layer of the memory cell array and each layer of the memory cell array including a plurality of memory cells1; a plurality of wordlines2that penetrate through one or more layers of the memory cell arrays; each memory cell1including a semiconductor layer41that surrounds the sidewall of the wordline2and extends along the sidewall; and a plurality of bitlines3, with each bitline3connected to the semiconductor layers41of a column of memory cells in one layer of the memory cell array. The bitline3includes a plurality of first branch lines31and a plurality of second branch lines32, with one second branch line32connected between every two adjacent first branch lines31. The semiconductor layer41of each memory cell1is connected to two adjacent first branch lines31but is not connected to at least a part of the region, between the two adjacent first branch lines31, of the second branch line32.

In the embodiments disclosed herein, the bitline includes a plurality of first branch lines and a plurality of second branch lines, with one second branch line connected between every two adjacent first branch lines. That is, the bitline is composed of different branch lines. Additionally, the semiconductor layer of each memory cell is connected to two adjacent first branch lines but is not connected to at least a part of the region, between the two adjacent first branch lines, of the second branch line. Compared to the channel of the memory cell inFIG.1, which is directly connected to the conductive pillar serving as a bitline, the memory provided according to the embodiments disclosed herein reduces the contact area between the semiconductor layer of the memory cell and the bitline, thereby reducing the parasitic capacitance between the wordline and the bitline.

In addition, the composition of the bitline from different branch lines can be understood in multiple ways. One interpretation is that the first and second branch lines are made from different materials. Another interpretation is that the first and second branch lines are formed separately from the same or different materials and then connected together. Such a configuration would reveal, upon analysis of the internal structure of the bitline in a cross-section parallel to the substrate, a discontinuity in stress on either side of the contact surface between the first and second branch lines. A further interpretation is that the bitline is made from the same material in an integrated manner, but the first and second branch lines have different orientations. For example, a bitline similar to what is shown inFIG.3is produced through an integrated process. In such a scenario, the vertical and horizontal branch lines close to the memory cell1in the bitline3are referred to as the first branch lines, and the vertical branch lines away from the memory cell1are referred to as the second branch lines.

Further, in some embodiments, as shown inFIG.2or3, the region of the semiconductor layer41between two adjacent first branch lines31is disposed opposite to the second branch line32between the two adjacent first branch lines31. In other words, the region of the semiconductor layer41of each memory cell1surrounded by two adjacent first branch lines31is disposed opposite to the second branch line32between the two adjacent first branch lines31.

To further reduce the parasitic capacitance between the bitlines and wordlines, an insulation material is filled between the region of the semiconductor layer41between the two adjacent first branch lines31and the oppositely positioned second branch line32. In other words, an insulation material is filled between the region of the semiconductor layer41of each memory cell1surrounded by two adjacent first branch lines31and the oppositely positioned second branch line32.

In some embodiments, the second branch line includes all or part of the region the bitline directly facing the semiconductor layer, and the insulation material is filled between the region of the second branch line directly facing the semiconductor layer and the semiconductor layer. The method of filling with insulation material allows the semiconductor layer41of each memory cell1to be not entirely connected to the second branch line32between two adjacent first branch lines31, which reduces the contact area between the semiconductor41and the bitline, thereby reducing the parasitic capacitance.

To facilitate understanding of the connections between various parts, the insulation material is not shown inFIGS.2and3.FIG.4is a structural schematic diagram of another memory according to some embodiments of the present disclosure, where the black areas represent the filled insulation material. As shown inFIG.4, the extension direction of each wordline2is referred to as the first direction, and the extension direction of each bitline3is referred to as the second direction. InFIG.4, the left diagram is a cross-sectional view of one of the wordlines2along the first direction. As shown in the left diagram inFIG.4, the wordline2extends along the first direction and is surrounded by a plurality of memory cells to form multiple layers of memory cell arrays stacked along the first direction perpendicular to the substrate. The right diagram inFIG.4is a cross-sectional view of one layer of memory cell array from the multiple layers of memory cell arrays. As shown in the right diagram inFIG.4, a layer of memory cell array includes a plurality of memory cells1, which is illustrated with2memory cells1as an example in the right diagram inFIG.4. The plurality of memory cells1are arranged in a column along the second direction, and the semiconductor layers41of the plurality of memory cells1are connected to the same bitline3. As shown inFIG.4, an insulation material is filled between the region of the semiconductor layer41of each memory cell1surrounded by two adjacent first branch lines31and the oppositely positioned second branch line32.

In some embodiments, the region of the semiconductor layer41of each memory cell1surrounded by two adjacent first branch lines31is disposed opposite to the second branch line32disposed between the two adjacent first branch lines31. This can be interpreted as that the wordline2is disposed opposite to the second branch line32, and there is an overlapping area between the projections of the wordline surrounded by the semiconductor layer41of each memory cell1and the oppositely positioned second branch line32on a plane perpendicular to the substrate0. The plane perpendicular to the substrate0extends along the column direction of a column of memory cells. Exemplarily, as shown inFIGS.2to4, the projection of the wordline surrounded by the semiconductor layer41of each memory cell1completely is overlapped with the projection of the oppositely positioned second branch line32on the plane perpendicular to the substrate0. In this case, there is no overlapping area between the projections of the wordline2and the first branch line31on the plane perpendicular to the substrate0.

In some embodiments, the projection of the wordline surrounded by the semiconductor layer41of each memory cell1is partially overlapped with the projection of the oppositely positioned second branch line32on the plane perpendicular to the substrate0. Further examples are not detailed here.

In addition, in the embodiments disclosed herein, the first and second branch lines are named after the shape of the bitline3as shown in the cross-sectional views inFIGS.2and3. In the memory according to the embodiments disclosed herein, the first and second branch lines are a conductive layer extending in a direction perpendicular to the substrate0, that is, the first and second branch lines have a certain thickness in the direction perpendicular to the substrate0to ensure electrical connections with other parts. As shown in the left diagram inFIG.4, the second branch line32extends a certain thickness along the first direction perpendicular to the substrate0.

In some embodiments, as shown inFIG.2, each first branch line31includes side surfaces and end surfaces, and the semiconductor layer41of each memory cell1is connected to the end surfaces of two adjacent first branch lines31, respectively. For linear structures, the end surfaces typically refer to the surfaces at the two ends of the linear structure, and the side surfaces typically refer to the surfaces of the linear structure excluding the surfaces of the two ends. The area of the end surfaces is much smaller than that of the side surfaces. For example, for a cylinder of a linear structure, the end surfaces refer to the surfaces at the two ends of the cylinder, and the side surface refers to the surface of the cylindrical sidewall. As shown inFIG.2, since the semiconductor layer41of memory cell1is connected to the end surfaces of the first branch lines31, the part of the bitline that can form parasitic capacitance with the wordline2is only the end surface of the first branch line, which typically has a small area. As a result, the memory shown inFIG.2significantly reduces the parasitic capacitance between the wordline2and the bitline3.

In some embodiments, as shown inFIG.4, each first branch line31includes side surfaces and end surfaces, and the semiconductor layer41of each memory cell1is connected to the side surfaces of two adjacent first branch lines31near the end surfaces, respectively. In this case, the semiconductor layer41of the memory cell1is connected only to a small part of the side surface of the first branch line31, which reduces the parasitic capacitance between the wordline2and the bitline3as well. In some embodiments, the semiconductor layer41of each memory cell1is connected to the end surfaces and the side surfaces near the end surfaces of two adjacent first branch lines31.

In addition, in some embodiments, as shown inFIGS.2and4, each first branch line31extends along the plane perpendicular to the substrate and exhibits a polygonal structure from a cross-sectional view along the plane parallel to the substrate, both ends of each second branch line32are respectively connected to the bending points of two adjacent first branch lines31, and the semiconductor layer41of each memory cell1is connected to one end of two adjacent first branch lines31, respectively. The semiconductor layer41of each memory cell1is connected to one end of two adjacent first branch lines31respectively, connected to the end faces of two adjacent first branch lines31, or connected to the side surfaces of two adjacent first branch lines31near the end surfaces.

In some embodiments, each first branch line31is of other types of structures, such as arc-shaped, etc. Further examples are not detailed here.

In the memory shown inFIGS.2to4, the semiconductor layer41surrounding the wordline2serves as the channel of the transistor in the memory cell, and the part of the first branch line connected to the semiconductor layer simultaneously serves as the drain of the transistor in the memory cell.

In addition, as shown inFIGS.2and4, the semiconductor layer41of each memory cell1is connected to two adjacent first branch lines31. In some embodiments, the semiconductor layer41of each memory cell1is further connected to a greater number of first branch lines31, which is not limited in the embodiments disclosed herein.

For the memory shown inFIGS.2and4, the bitline3is not fabricated in an integrated manner but is composed of alternating first branch lines31and second branch lines32. This facilitates the process of filling insulation material between the region of the semiconductor layer41of each memory cell1surrounded by two adjacent first branch lines31and the oppositely positioned second branch line32.

In addition, in the memory shown inFIGS.2and4, in some embodiments, the first branch line31is made of metal silicide. This allows a plurality of first branch lines31to be fabricated in an integrated manner through a silicon metallization process during the manufacture of the memory. The spaced first branch lines31are then connected by the second branch lines32to form a complete bitline3. Specific implementation can refer to subsequent manufacturing method embodiments, which will not be elaborated here.

In some embodiments, each second branch line is a straight line, and they are connected to form a continuous line. The continuous line is a conductive wire of a one-piece structure, which is a solid line. The conductive wire of a one-piece structure is connected to the first branch lines on the side. In some embodiments, the second branch lines32are independent of each other and are connected separately to the first branch lines31on the memory cells. In some embodiments, the first branch line31includes a branch extending laterally and a branch extending longitudinally (in the same direction as the bitline extends), with both branches being a one-piece structure and having a bending region formed by extending in different directions.

In some embodiments, one bitline is connected to at least one column of memory cells. In some embodiments, one bitline is connected simultaneously to two columns of memory cells. The second branch line32is of a hollow ring shape, with one second branch line32connected between every two adjacent first branch lines31. A semiconductor layer corresponding to one memory cell is connected to two different first branch lines31, and the first branch lines for two adjacent memory cells in a column are of a one-piece structure. The ring-shaped second branch line32is connected to the bending regions of two first branch lines corresponding to two columns of memory cells.

The first and second branch lines are of a one-piece structure made of the same material. Alternatively, the first and second branch lines are independent and interconnected structures made of different materials.

In some embodiments, as shown inFIG.2, the conductive wire or conductive film layer corresponding to the second branch line32includes an upper surface and a lower surface parallel to the substrate. The second branch line32includes a via hole penetrating through the upper surface and the lower surface or a hole on the upper surface. A dielectric layer is filled within the via hole or the hole. This design facilitates the process of fabricating the second branch line32through the etching of via holes or holes. Specific implementation can refer to subsequent manufacturing method embodiments, which will not be elaborated here.

In some embodiments, for the memory with 1T1C memory cells, the structure shown inFIGS.5to7can also be referenced to reduce the parasitic capacitance between the wordline and the capacitor.

FIG.5is a structural schematic diagram of another memory improved based on the memory shown inFIG.4according to some embodiments of the present disclosure. As shown inFIG.5, based on the memory shown inFIG.4, each memory cell1further includes two first conductive layers43connected respectively to the semiconductor layer41and a second conductive layer51connected to the two first conductive layers43. As shown inFIG.5, the region of the semiconductor layer41of each memory cell1surrounded by the two first conductive layers43is disposed opposite to the second conductive layer51. Additionally, an insulation material is filled between the region of the semiconductor layer41of each memory cell1surrounded by two adjacent first conductive layers43and the second conductive layer51. As the insulation material is filled between the region of the semiconductor layer41of each memory cell1surrounded by two adjacent first conductive layers43and the second conductive layer51, the parasitic capacitance between the WL and the capacitor is reduced.

In some embodiments, as shown inFIG.5, the first conductive layer43includes side surfaces and end surfaces, and the second conductive layer51is connected to the end surface of the first conductive layer43. The first conductive layer43serves as the source of the transistor in the memory cell. The second conductive layer51serves as the first electrode of the capacitor in the memory cell. For a film layer structure, the end surface typically refers to the surface of the film layer structure with a smaller area, and the side surface typically refers to the surface of the film layer structure with a larger area, such as the main surface. As shown in the right diagram inFIG.5, since the end surface of the first conductive layer43of the memory cell1is connected to the second conductive layer51, the part of the first electrode that can form parasitic capacitance with the wordline2is only the part of the first electrode that contacts the end surface of the first conductive layer43. As the area of the end surface is usually small, the memory shown inFIG.5can significantly reduce the parasitic capacitance between the wordline2and the capacitor.

Exemplarily, as shown inFIG.5, each memory cell1includes two first conductive layers43, with the end surfaces of the two first conductive layers43connected respectively to the second conductive layer51. In this case, the two first conductive layers43together serve as the source of a transistor. In some embodiments, each memory cell1further includes fewer or more first conductive layers43, the number of which is not limited in the embodiments disclosed herein.

In addition, in the memory shown inFIG.5, in some embodiments, both the first conductive layer43and the second conductive layer51are made of metal silicide. This allows the first conductive layer43and the second conductive layer51to be fabricated in an integrated manner through a silicon metallization process during the manufacture of the memory. Specific implementation can refer to subsequent manufacturing method embodiments, which will not be elaborated here.

In the memory shown inFIG.5, there is no specific structure defined for the second conductive layer51, i.e., the first electrode of the capacitor. In the memory shown inFIG.5, the second conductive layer51, i.e., the first electrode of the capacitor5can be of any structure, which is not limited in the embodiments disclosed herein.

In some embodiments, as shown inFIG.6, based on the memory shown inFIG.5, the second conductive layer51extends in a direction perpendicular to the substrate and exhibits a U-shaped structure from a cross-sectional view along the plane parallel to the substrate. The second conductive layer51includes side surfaces and end surfaces. The end surfaces of the two first conductive layers43of each memory cell1are connected respectively to the two end surfaces of the second conductive layer51. With the U-shaped second conductive layer51, the surface area of the first electrode of the capacitor5is increased, thereby enhancing the charge storage capacity of the memory cell.

Further, in some embodiments, the structure of the memory shown inFIG.6is modified to further increase the area of the first electrode of the capacitor5. As shown inFIG.6, each memory cell1further includes a third conductive layer6connected to the inner walls on both sides of the second conductive layer51near the end surface. The third conductive layer6also serves as the first electrode of the capacitor5. In this case, the U-shaped second conductive layer51and the third conductive layer6form a ring-shaped electrode, which serves as the first electrode of the capacitor5. In the memory shown inFIG.6, there is no specific structure defined for the second electrode of the capacitor. In the memory shown inFIG.6, the second electrode of the capacitor can be of any structure, which is not limited in the embodiments disclosed herein.

In some embodiments, as shown inFIG.7, based on the memory shown inFIG.6, the inner and outer walls of the U-shaped structure of the second conductive layer51are respectively connected to a fourth conductive layer52. The two parts of the fourth conductive layer52, which are connected respectively to the inner and outer walls of the U-shaped structure of the second conductive layer51, serve as the second electrode of the capacitor5. In this case, the first electrode of the capacitor is of a ring-shaped structure, and the second electrode of the capacitor is not just one part but includes two parts, which are disposed respectively on the inner side and outer side of the ring-shaped first electrode.

In addition, as shown in the left diagram inFIG.7, the same material as the fourth conductive layer52is also filled in the region between the memory arrays of different layers and between the upper and lower surfaces of the capacitor5. This allows the two parts of the fourth conductive layer52on the inner and outer walls of the second conductive layer51shown in the right diagram inFIG.7to be connected together. In addition, in the right cross-sectional diagram inFIG.7, a first dielectric layer is distributed between the first electrode (i.e., second conductive layer51) and the second electrode (i.e., fourth conductive layer52) of the capacitor5, serving as the dielectric layer of the capacitor5. The first dielectric layer is disposed on both sides of the inner and outer walls of the first electrode.

FIGS.4to7illustrate an example where each layer of the memory cell array includes a column of memory cells. In some embodiments, as shown inFIG.2, each layer of the memory cell array includes more columns of memory cells. Exemplarily, as shown inFIG.2, each layer of the memory cell array includes a first column of memory cells and a second column of memory cells, and the plurality of bitlines3include a first bitline and a second bitline. The semiconductor layers41of the first column of memory cells are connected to the first bitline, and the semiconductor layers41of the second column of memory cells are connected to the second bitline. Moreover, the first bitline and the second bitline are disposed between the first column of transistors and the second column of transistors. That is, the first column of memory cells and the second column of memory cells are arranged in a mirrored layout. In this case, the first bitline and the second bitline can also be connected to allow the first column of memory cells and the second column of memory cells to share the same bitline, facilitating subsequent control of the first bitline and the second bitline.

In some embodiments, as shown inFIG.2, each second branch line32in the first bitline is connected to a second branch line32in the second bitline. Further, the first bitline and the second bitline share the second branch line, facilitating the process of fabricating the second branch line32. Specific implementation can refer to subsequent manufacturing method embodiments, which will not be elaborated here.FIG.2illustrates an example where each layer of the memory cell array includes two columns of memory cells. In some embodiments, each layer of the memory cell array includes more columns of memory cells. Further examples are not detailed here.

When the layer of memory cell array shown inFIG.2is stacked in a multi-layer manner, a type of 3D DRAM according to the embodiments disclosed herein can be obtained.FIG.8is a three-dimensional view of the memory cell array shown inFIG.2after being stacked in a multi-layer manner. As shown inFIG.8, a plurality of wordlines2are arranged in an array along the second direction and the third direction on the substrate0. Multiple layers of memory cell arrays are stacked along the first direction on the substrate0. Each layer of memory cell array includes two columns of memory cells arranged in a mirrored layout, each column of memory cells including a plurality of memory cells1arranged along the second direction (reference numeral1is not shown inFIG.8). The semiconductor layer41of each memory cell1in every column of memory cells is connected to the first branch line31of the bitline3, with the specific connection method referring to the relevant content shown inFIG.2. The semiconductor layer41serves as the channel of the transistor, with the part of the first branch line31near the semiconductor layer41simultaneously serving as the drain of the transistor. The end surface of the first conductive layer43of each memory cell1in every column of memory cells is connected to a U-shaped second conductive layer51, with the first conductive layer43serving as the source of the transistor in the memory cell, and the second conductive layer serving as the first electrode of the capacitor in the memory cell.

FIGS.9to12illustrate another type of memory according to some embodiments of the present disclosure to reduce the parasitic capacitance of DRAM. A detailed explanation is provided below.FIG.9is a structural schematic diagram of another memory according to some embodiments of the present disclosure that reduces parasitic capacitance. As shown inFIG.9, in some embodiments, the memory includes one or more layers of transistor arrays stacked in a direction perpendicular to the substrate0, with each layer of the transistor array including a plurality of transistors4; a plurality of wordlines2that penetrate through one or more layers of the transistor arrays; each transistor4including a channel41′ surrounding the wordline2and a drain42connected to the channel41′; and a plurality of bitlines3, with each bitline3connected to the drains42of a column of transistors in one layer of the transistor array. Specifically, as shown inFIG.9, a plurality of wordlines2are arranged in the second direction, and a plurality of bitlines3are arranged in the first direction; multiple layers of the transistor array are stacked in the first direction on the substrate0, each layer of the transistor array including a column of transistors4arranged in the second direction. The channels41of multiple transistors4arranged along the first direction in different layers of the transistor arrays surround the same wordline2, and the drains42of a column of transistors4in the same layer of the transistor array are connected to the same bitline3.

In the embodiments disclosed herein, as shown inFIG.9, an insulation material is filled between the first channel region of the channel41′ of the transistor4and the first bitline region of the bitline3. The first channel region refers to the region of the channel41′ directly facing the bitline3, and the first bitline region refers to the region of the bitline3directly facing the channel41′. This arrangement reduces the parasitic capacitance between the wordline and the bitline.

The first channel region refers to the region of the channel41′ directly facing the bitline3, which can be interpreted as that all or part of the sidewall area of the channel41′ that can be seen from the bitline3along the third direction is referred to as the first channel region. Alternatively, it can be interpreted as that all or part of the sidewall area of the channel41′ onto which the bitline3can be projected along the third direction is referred to as the first channel region. The first bitline region refers to the region of the bitline3directly facing the channel41′, which can be interpreted as that all or part of the bitline area that can be seen from the channel41′ along the third direction is referred to as the first bitline region. Alternatively, it can be interpreted as that all or part of the side surface area of the bitline3onto which the channel41′ can be projected along the third direction is referred to as the first bitline region. As shown inFIG.9, since the insulation material is filled between the first channel region of the channel41′ of the transistor4and the first bitline region of the bitline3, not all of the first channel region and the first bitline region are directly electrically connected. This reduces the contact area between the channel41′ and the bitline3, thereby avoiding a large parasitic capacitance between the wordline and the bitline that would result from a direct and complete electrical connection between the first channel region and the first bitline region.

In addition, in the memory shown inFIG.9, the drain42of each transistor4is composed of two semiconductor layers. In this case, the filling of the insulation material between the first channel region of the channel41′ of the transistor4and the first bitline region of the bitline3can also be interpreted as the insulation material being filled within the semi-enclosed area surrounded by the drain42and channel41′ of the transistor4.

In addition, in some embodiments, as shown inFIG.9, the bitline3includes a plurality of first branch lines31and a plurality of second branch lines32, with one second branch line32connected between every two first branch lines31. The first channel region directly faces a second branch line32. With the above arrangement, each branch line can be fabricated in segments, and then these branch lines are connected to form a complete bitline. This facilitates the initial fabrication of the drain and the first branch lines, followed by filling the insulation material at the corresponding positions, and finally connecting all the first branch lines together to form a complete bitline.

In this case, exemplarily, both the drain42and the first branch line31are made of metal silicide. This allows the drain42and the first branch line31to be fabricated in an integrated manner through a silicon metallization process during the manufacture of the memory. Specific implementation can refer to subsequent manufacturing method embodiments, which will not be elaborated here.

In some embodiments, for the memory with 1T1C memory cells, the structure shown inFIG.9can also be referenced to reduce the parasitic capacitance between the wordline and the capacitor.

FIG.10is a structural schematic diagram of another memory improved based on the memory shown inFIG.9according to some embodiments of the present disclosure. As shown inFIG.10, based on the memory shown inFIG.9, the memory further includes a plurality of capacitors5. Each transistor4further includes a source43′ connected to the channel41′. The source43′ of each transistor4is connected to the first electrode51′ of the capacitor5, and an insulation material is filled between the second channel region of the channel41′ and the first electrode region of the first electrode51′. The second channel region refers to the region of the channel41′ directly facing the first electrode51′, and the first electrode region refers to the region of the first electrode51′ directly facing the channel41′.

The second channel region refers to the region of the channel41′ directly facing the first electrode51′, which can be interpreted as that all or part of the sidewall area of the channel41′ that can be seen from the first electrode51′ along the third direction is referred to as the second channel region. Alternatively, it can be interpreted as that all or part of the sidewall area of the channel41′ onto which the first electrode51′ can be projected along the third direction is referred to as the second channel region. The first electrode region refers to the region of the first electrode51′ directly facing the channel41′, which can be interpreted as that all or part of the first electrode51′ area that can be seen from the channel41′ along the third direction is referred to as the first electrode region. Alternatively, it can be interpreted as that all or part of the side surface area of the first electrode51′ onto which the channel41′ can be projected along the third direction is referred to as the first electrode region.

As shown inFIG.10, since the insulation material is filled between the second channel region of the channel41′ of the transistor4and the first electrode region of the first electrode51′, not all of the second channel region and the first electrode region are directly electrically connected. This reduces the contact area between the channel41′ and the first electrode51′, thereby avoiding a large parasitic capacitance between the wordline and the bitline that would result from a direct and complete electrical connection between the second channel region and the first electrode region.

In addition, in the memory shown inFIG.10, the source43′ of each transistor4is composed of two semiconductor layers. In this case, the filling of the insulation material between the second channel region of the channel41′ of the transistor4and the first electrode region of the first electrode51′ can also be interpreted as the insulation material being filled within the semi-enclosed area surrounded by the source43′ and channel41′ of the transistor4.

In addition, in the memory shown inFIG.10, in some embodiments, both the source43′ and the first electrode51′ are made of metal silicide. This allows the source43′ and the first electrode51′ to be fabricated in an integrated manner through a silicon metallization process during the manufacture of the memory. Specific implementation can refer to subsequent manufacturing method embodiments, which will not be elaborated here.

In the memory shown inFIG.10, there is no specific structure defined for the second conductive layer, i.e., the first electrode51′ of the capacitor5. In the memory shown inFIG.10, the first electrode51′ of the capacitor5can be of any structure, which is not limited in the embodiments disclosed herein.

In some embodiments, as shown inFIG.11, based on the memory shown inFIG.10, the first electrode51′ is of a U-shaped structure, and the open end of the first electrode51′ is connected to the source43′. With the U-shaped first electrode51′, the surface area of the first electrode51′ of the capacitor is increased, thereby enhancing the charge storage capacity of the memory cell composed of the transistor and the capacitor. The aforementioned first electrode51′ is also referred to as the first electrode of the capacitor.

Further, in some embodiments, the structure of the memory shown inFIG.11is modified to further increase the area of the first electrode of the capacitor. As shown inFIG.11, the memory further includes a plurality of third conductive layers6; each third conductive layer6is connected to the inner walls on both sides of a first electrode51′ near the open end. The third conductive layer6also serves as the first electrode of the capacitor. In this case, the U-shaped first electrode51′ and the third conductive layer6form a ring-shaped electrode, which serves as the first electrode of the capacitor.

In some embodiments, the specific structure of the first electrode of the capacitor is not defined, and the first electrode of the capacitor can be of any structure.

In addition, the relevant content for the second electrode of the capacitor can refer to the content related toFIG.7, which will not be reiterated here.

FIGS.9to11illustrate an example where each layer of the memory cell array includes a column of memory cells. In some embodiments, each layer of the memory cell array includes more columns of memory cells.FIG.12is a structural schematic diagram of another memory improved based on the memory shown inFIG.11according to some embodiments of the present disclosure. As shown inFIG.12, each layer of the transistor array includes a first column of transistors and a second column of transistors, and the plurality of bitlines3include a first bitline and a second bitline. The drains42of the first column of transistors are connected to the first bitline, and the drains42of the second column of transistors are connected to the second bitline. The first bitline and the second bitline are disposed between the first column of transistors and the second column of transistors. That is, the first column of transistors and the second column of transistors are arranged in a mirrored layout. In this case, the first bitline and the second bitline can also be connected to allow the first column of transistors and the second column of transistors to share the same bitline, facilitating subsequent control of the first bitline and the second bitline.

In some embodiments, as shown inFIG.12, where each bitline3includes both first branch lines31and second branch lines32, a second branch line32in the first bitline and a second branch line32in the second bitline are the same second branch line, facilitating the process of fabricating the second branch line32. Specific implementation can refer to subsequent manufacturing method embodiments, which will not be elaborated here.

Regarding the three-dimensional view of the memory shown inFIG.12in the context of 3D DRAM, reference can also be made toFIG.8, which will not be reiterated here.

Next, the method for manufacturing the memory according to the embodiments disclosed herein will be explained in detail.FIG.13is a flowchart of a method for manufacturing the memory according to some embodiments of the present disclosure. As shown inFIG.13, the method includes the following steps.

Step1301: providing a substrate0.

In some embodiments, the substrate0is made of silicon. Exemplarily, the substrate is made of monocrystalline silicon.

Step1302: forming, on the substrate0, a plurality of conductor layers100and a plurality of isolation layers200alternately stacked in a direction perpendicular to the substrate0as well as a plurality of dummy wordlines300that penetrate through the plurality of conductor layers100and the plurality of isolation layers200.

In some embodiments, the method for implementing Step1302is as follows: depositing a plurality of isolation layers200and a plurality of conductor layers100alternately on the substrate0along the first direction to obtain the structure shown inFIG.14; etching the plurality of isolation layers200and the plurality of conductor layers100to form fourth through holes that penetrate through the plurality of isolation layers200and the plurality of conductor layers100and extend along the first direction; and depositing an insulation material in each fourth through hole to obtain a plurality of dummy wordlines300, resulting in the structure shown inFIG.15.

The first direction is perpendicular to the substrate0. The dummy wordline300is also labeled as dummy WL. The c1, c2, and c3inFIGS.14and15represent cross-sectional views obtained along the three directions shown inFIG.14. Reference may be made to this explanation for c1, c2, and c3in subsequent figures.

It should be noted that dummy wordlines refer to structures that will be sacrificed later to form the actual wordlines, hence dummy wordlines are also referred to as sacrificial wordlines.

Exemplarily, as shown inFIGS.14and15, the isolation layer200is made of oxide, which is an insulation material. The conductor layer100is made of polycrystalline silicon (poly). The dummy wordline300is made of SiN, which is also an insulation material. The dummy wordline300is made of SiN to facilitate subsequent operations. In some embodiments, the dummy wordline300is also made of other materials.

In addition, after the plurality of isolation layers200and the plurality of conductor layers100are alternately stacked inFIG.14, a layer of mask (hard mask) is further deposited on the topmost isolation layer200to facilitate subsequent etching operations. The mask is made of SiN or other mask materials.

In addition, for ease of subsequent explanations, the plurality of isolation layers200and the plurality of conductor layers100alternately deposited are simply referred to as the stacked layers.

Step1303: metallizing each conductor layer100to form a plurality of first branch lines31in each conductor layer100, with every two adjacent first branch lines31connected to one dummy wordline300.

In some embodiments, the conductor layer100is made of silicon. In this case, prior to metallizing each conductor layer100, as shown inFIGS.16and17, the plurality of conductor layers100and the plurality of isolation layers200are first etched to form passages101that penetrate through the plurality of conductor layers100and the plurality of isolation layers200and are disposed on both sides of each dummy wordline300, with the parts of each dummy wordline300in the conductor layer100exposed to the passages101.

The specific process for forming the structure shown inFIG.16is as follows: first etching the mask, then etching the stacked layers through the etched mask to form the initial passages on both sides of each dummy wordline300as shown inFIG.16. It should be noted that at this point, the sidewalls of the dummy wordlines in the conductor layer100are not yet exposed. Then, the conductor layer is etched through the isotropic etching method to form the structure shown inFIG.17, where the parts of each dummy wordline300in the conductor layer100are exposed to the passages101.

Based on this, the method for implementing Step1303is as follows: depositing a metal film on the inner wall of the passage101; and annealing the metal film to metallize the silicon on the surface of the conductor layer100, as shown inFIG.18, resulting in a plurality of first branch lines31of a bitline3in each conductor layer100.

Exemplarily, the method for depositing the metal film on the inner wall of the passage101is as follows: using the atomic layer deposition (ALD) technology to deposit metal Pt on the inner wall of the passage101.

Upon depositing the metal film on the inner wall of the passage101, the metal film is deposited on the sidewalls of both the conductor layer100and the isolation layer200in the passage101. However, during annealing, only the silicon in the conductor layer100reacts with the metal film to generate a metal silicide (SILICIDE), while the oxide in the isolation layer200does not react with the metal film. Therefore, after the annealing and stripping away the metal film, a plurality of first branch lines31of a bitline3in each conductor layer100are then formed.

In addition, upon stripping away the metal film, annealing treatment is continued to further improve the stability of the metal silicide.

In some embodiments, as shown inFIG.18, upon metallizing each conductor layer100, the first conductive layers43for a column of memory cells1are also formed in each conductor layer100.

In some embodiments, as shown inFIG.18, upon metallizing each conductor layer100, the first conductive layers43and the second conductive layer51for a column of memory cells1are also formed in each conductor layer100.

The part of the first branch line31near the semiconductor layer41serves as the drain42of the transistor, the first conductive layer43serves as the source43′ of the transistor, and the second conductive layer51serves as the first electrode51′ of the capacitor. In this case, the drain42of the transistor, the source43′ of the transistor, the first electrode51′ of the capacitor, and part of the bitline3in each memory cell are all fabricated in an integrated manner through a silicon metallization process, enhancing the manufacturing efficiency of the memory.

After obtaining the structure shown inFIG.18, connecting each first branch line together forms a complete bitline. As shown inFIG.18, the dummy wordline300is connected to the first branch line31by means of an end surface connection. This limits the contact area between the channel of the transistor formed later in the dummy wordline300and the bitline to only the area of the end surface, thus reducing the contact area between the channel of the transistor and the bitline, and consequently reducing the parasitic capacitance between the wordline and the bitline. Moreover, as shown inFIG.18, the source43′ of the transistor is also connected to the first electrode51′ by means of an end surface connection. This also limits the contact area between the channel of the transistor and the first electrode51′ to only the area of the end surface, thus reducing the contact area between the channel of the transistor and the first electrode51′, and consequently lowering the parasitic capacitance between the wordline and the capacitor.

Step1304: filling an insulation material in the semi-enclosed areas surrounded by each dummy wordline300and two adjacent first branch lines31.

The filling of the insulation material in the semi-enclosed areas surrounded by each dummy wordline300and two adjacent first branch lines31enables the filling of the insulation material in the area directly facing the channel formed later in the dummy wordline300and the bitline. This reduces the contact area between the channel and the bitline, thereby reducing the parasitic capacitance between the wordline and the bitline.

In some embodiments, the silicon in the semi-enclosed area surrounded by the dummy wordline300and the first conductive layer43can also be replaced with an insulation material to further reduce the parasitic capacitance between the wordline and the capacitor.

In some embodiments, as shown inFIGS.19to21, the method for replacing the silicon in the semi-enclosed area surrounded by the dummy wordline300and the first branch line31and the semi-enclosed area surrounded by the dummy wordline300and the first conductive layer43with the insulation material is as follows: etching the plurality of conductor layers100and the plurality of isolation layers200to form a plurality of second through holes102that penetrate through the plurality of conductor layers100and the plurality of isolation layers200and are disposed in the semi-enclosed areas surrounded by each dummy wordline and two adjacent first branch lines31, with both the inner and outer walls of the second conductive layer51exposed; etching away the silicon of each conductor layer100among the plurality of conductor layers100; depositing the insulation material in the gaps between the plurality of conductor layers100and the plurality of isolation layers200after being etched, such that the semi-enclosed area surrounded by the dummy wordline300and the first branch line31and the semi-enclosed area surrounded by the dummy wordline300and the first conductive layer43are filled with the insulation material.

Specifically, after obtaining the structure shown inFIG.18, to facilitate the subsequent filling of the insulation material, SiN, an insulation material, is first deposited on the sidewalls of the structure shown inFIG.18. This ensures that the grooves surrounding the sidewalls of the dummy wordlines300in the cross-sectional view of c2inFIG.18are filled with the insulation material of SiN, resulting in the structure shown inFIG.19.

After obtaining the structure shown inFIG.19, to replace the silicon in the semi-enclosed area surrounded by the dummy wordline300and the first branch line31and the semi-enclosed area surrounded by the dummy wordline300and the first conductive layer43with the insulation material, thereby reducing the parasitic capacitance between the wordline and the bitline as well as between the wordline and the capacitor, oxide is filled in all the gaps in the structure shown inFIG.19, and then the stacked layers are etched through the mask to form a plurality of second through holes102that penetrate through the plurality of conductor layers100and the plurality of isolation layers200and are disposed in the semi-enclosed areas surrounded by each dummy wordline and two adjacent first branch lines31, with the inner wall of the second conductive layer51exposed, resulting in the structure shown inFIG.20.

Then, the silicon around the second through holes102in each conductor layer and the silicon near the second conductive layer51are etched away in an isotropic manner to remove the silicon in the semi-enclosed area surrounded by the dummy wordline300and the first branch line31and the semi-enclosed area surrounded by the dummy wordline300and the first conductive layer43in the conductor layer100. Then, the insulation material is deposited in all the gaps of the etched structure, resulting in the structure shown inFIG.21. As shown inFIG.21, the semi-enclosed area surrounded by the dummy wordline300and the first branch line31and the semi-enclosed area surrounded by the dummy wordline300and the first conductive layer43in the conductor layer100have been filled with the insulation material.

The above is illustrated with the example of simultaneously filling the insulation material in the semi-enclosed area surrounded by the dummy wordline300and the first branch line31and in the semi-enclosed area surrounded by the dummy wordline300and the first conductive layer43. In some embodiments, the operation of filling the insulation material in the semi-enclosed area surrounded by the dummy wordline300and the first branch line31and the operation of filling the insulation material in the semi-enclosed area surrounded by the dummy wordline300and the first conductive layer43can be performed separately, which is not limited in the embodiments disclosed herein.

Exemplarily, upon obtaining the first branch line31as shown inFIG.18, the insulation material is filled in the first semi-enclosed area surrounded by the dummy wordline300and the first branch line31.

Exemplarily, upon obtaining the source43′ of the transistor as shown inFIG.18, the insulation material is filled in the second semi-enclosed area surrounded by the dummy wordline300and the first conductive layer43.

Step1305: connecting the plurality of first branch lines31in each conductor layer100to form second branch lines32disposed between every two adjacent first branch lines31.

In some embodiments, after obtaining the structure shown inFIG.21through Step1304, as shown inFIGS.22and23, the method for implementing Step1305is as follows: etching the plurality of conductor layers100and the plurality of isolation layers200to form a plurality of first through holes104that penetrate through the plurality of conductor layers100and the plurality of isolation layers200and are disposed between every two adjacent first branch lines31, with the inner wall of the second conductive layer51exposed; depositing the first metal layer103on the inner wall of each first through hole104and the inner wall of each second conductive layer51near the first conductive layer43; etching the first metal layer103disposed on each isolation layer200and retaining the first metal layer103disposed on each conductor layer100to obtain a plurality of second branch lines32and a plurality of third conductive layers6disposed on each conductor layer100. The bitline3disposed in each conductor layer100includes a plurality of first branch lines31and the second branch lines32disposed between every two adjacent first branch lines31.

Specifically, for the structure shown inFIG.21, the stacked layers shown inFIG.21are anisotropically etched firstly to form the first through holes104, with both sides of the second conductive layer51exposed. Then, the SiN is isotropically etched to obtain the structure shown inFIG.22. This process causes the inner wall of the first through hole as well as the two sidewalls as shown in the cross-sectional view of cl in the conductor layer100to slightly indent, while the sidewalls in the isolation layer200to slightly protrude, facilitating the implementation in subsequent processes.

After obtaining the structure shown inFIG.22, a tungsten W layer is deposited on the inner wall of the first through hole104and the inner walls on both sides of the second conductive layer51near the end surface in the structure shown inFIG.22, resulting in the first metal layer103. Since inFIG.22, the inner wall of the first through hole as well as the two sidewalls as shown in the cross-sectional view of cl in the conductor layer100are slightly indented, while the sidewalls in the isolation layer200slightly protrude, the tungsten W layer deposited on the inner wall of the first through hole and the tungsten W layer deposited on the two sidewalls as shown in the cross-sectional view of c1in the conductor layer100are slightly indented, while the tungsten W layer deposited on the sidewalls in the isolation layer200slightly protrudes. Then, after isotropically etching the tungsten W layer, the tungsten W layer at the protruding parts in the isolation layer is etched away, thereby retaining the tungsten W layer in the conductor layer100, resulting in the structure shown inFIG.23.

The above is illustrated with the example of obtaining the second branch line32and the third conductive layer6simultaneously through a single process. In some embodiments, the two structures are formed separately.

Exemplarily, the method for separately forming the second branch line32is as follows: etching the plurality of conductor layers100and the plurality of isolation layers200to form a plurality of first through holes104that penetrate through the plurality of conductor layers100and the plurality of isolation layers200and are disposed between every two adjacent first branch lines31in each conductor layer100; depositing the first metal layer103on the inner walls of the first through holes104; etching the first metal layer103disposed on the isolation layer200and retaining the first metal layer103disposed on the conductor layer100to obtain the second branch line32disposed on the conductor layer100. The bitline3includes two first branch lines31and the second branch line32.

Exemplarily, the method for separately forming the third conductive layer6is as follows: etching the plurality of conductor layers100and the plurality of isolation layers200to expose the inner wall of the second conductive layer51in each conductor layer; depositing the first metal layer103on the inner side of the second conductive layer51near the first conductive layer43; etching the first metal layer103disposed on the isolation layer200and retaining the first metal layer103disposed on the conductor layer100to obtain the third conductive layer6disposed on the conductive layer100.

The second conductive layer51obtained through the above process serves as the first electrode51′ of the capacitor in the memory cell. After obtaining the first electrode51′ of the capacitor5in each memory cell through the above process, the second electrode of the capacitor is further manufactured.

In some embodiments, as shown inFIGS.24to25, the method for manufacturing the second electrode of the capacitor is as follows: sequentially depositing the first dielectric layer105and the silicon layer106on both sides of the plurality of second conductive layers51in each conductor layer100. The silicon layer106serves as the second electrode of the capacitor.

Specifically, after obtaining the structure shown inFIG.23, the oxide is deposited firstly in the gaps of the structure shown inFIG.23to facilitate subsequent operations on the stacked layers. Then, the oxide on both sides of the first electrode51′ is etched away through the mask to expose both sides of the first electrode51′, resulting in the structure shown inFIG.24.

After obtaining the structure shown inFIG.24, a layer of high dielectric (HK) material is deposited on both sides of the first electrode51′ to obtain a first dielectric layer105. Then, polycrystalline silicon (poly) is deposited on the outer walls of the first dielectric layer105disposed on both sides of the first electrode51′ to obtain the silicon layer106, thereby resulting in the structure shown inFIG.25.

As shown in the cross-sectional view of c3inFIG.25, silicon is also filled in the area between the upper and lower surfaces of the capacitor in each layer of the memory cell array, allowing the two parts of the silicon layer on both sides of the first electrode51′ in the cross-sectional view of c1to be connected to serve as the second electrode of the capacitor.

Step1306: etching away each dummy wordline300and forming a plurality of wordlines2and semiconductor layers41surrounding each wordline2.

In some embodiments, the method for implementing Step1306is as follows: etching away the plurality of dummy wordlines300to form a plurality of third through holes that penetrate through the plurality of conductor layers100and the plurality of isolation layers200; sequentially depositing a channel layer301, a second dielectric layer302, and a second metal layer303on the inner wall of each third through hole to form the semiconductor layer41, gate insulating layer, and a plurality of wordlines2for each memory cell, resulting in the structure shown inFIG.26; etching the channel layer301disposed on each isolation layer200to expose the second dielectric layer302disposed on each isolation layer200, resulting in the structure shown inFIG.27.

Exemplarily, as shown inFIG.26, the channel layer301is made of metal oxide, polycrystalline silicon, or monocrystalline silicon, among other materials.

The metal oxide material is indium gallium zinc oxide (IGZO). In the case that the metal oxide material is IGZO, the leakage current of the transistor11is small (less than or equal to 10 to 15A), ensuring a low refresh rate for the dynamic memory. It should be noted that the metal oxide material may also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx, etc. The specific material needs to ensure that the leakage current of the transistor meets the requirements, and then the material can be adjusted according to the actual situation.

The second dielectric layer302is made of a high dielectric (HK) material, and the second metal layer303is made of tungsten W.

In addition, a layer of TiN (not shown inFIG.26) is also deposited between the second dielectric layer302and the second metal layer303. TiN serves two purposes: one is to serve as an adhesive to prevent the second metal layer303from peeling off, and the other is to prevent the second metal layer303from diffusing into the channel.

In addition, etching the channel layer301disposed on each isolation layer200to expose the second dielectric layer302disposed on each isolation layer200reduces the parasitic MOS (metal-oxide-semiconductor) field-effect transistors in the memory.

In addition, as inFIG.25, the blank spaces inFIGS.26and27are filled with oxide, which is not shown inFIGS.26and27.FIG.28shows a complete view of the memory corresponding toFIG.27. As shown inFIG.28, the blank spaces in the structure shown inFIG.27are all filled with oxide. Further descriptions of the structure shown inFIG.28can refer to the aforementioned embodiments, which will not be reiterated here.

All the optional technical solutions mentioned above can be combined in any form to constitute optional embodiments of the present disclosure, which will not be reiterated in the embodiments disclosed herein.

It should be noted that the process flow shown inFIG.13is exemplary, and the embodiments disclosed herein do not limit the method for manufacturing the memory shown inFIGS.2to12.

In summary, in the embodiments disclosed herein, the bitline includes a plurality of first branch lines and a plurality of second branch lines, with one second branch line connected between every two adjacent first branch lines. That is, the bitline is composed of different branch lines. Additionally, the semiconductor layer of each memory cell is connected to two adjacent first branch lines but is not connected to at least a part of the region, between the two adjacent first branch lines, of the second branch line. Compared to the channel of the memory cell inFIG.1, which is directly connected to the conductive pillar serving as a bitline, the memory provided according to the embodiments disclosed herein reduces the contact area between the semiconductor layer of the memory cell and the bitline, thereby reducing the parasitic capacitance between the wordline and the bitline.

Further, in the case that the memory provided according to the embodiments disclosed herein is a 1T1C memory cell, the embodiments disclosed herein further provide a process optimization flow that reduces the parasitic capacitance between the wordline and bitline, as well as between the wordline and the capacitor in the 1T1C memory cell. In the optimized process flow, firstly, a stacked structure is manufactured using oxide/polycrystalline silicon, and the basic framework is etched out, followed by the making of dummy wordlines. Next, the disconnected bitlines are obtained through the silicon metallization process. After that, the insulation material SiN is filled between the bitlines and the dummy wordlines. Then, the disconnected bitlines are connected. Finally, the dummy wordlines are replaced with actual wordlines, and the parasitic MOS is removed.

The optimized process flow reduces parasitic capacitance without compromising device performance and at the same time alters the shape of the capacitor within the memory cell. This allows the capacitor in the memory cell to occupy a smaller area and is compatible with the process of removing parasitic MOS.

In addition, the embodiments disclosed herein further provide an electronic device that includes at least one semiconductor device as described in the aforementioned embodiments. The electronic device includes, but is not limited to, smart phones, computers, tablets, artificial intelligence devices, wearable devices, or smart mobile terminals.

Unless otherwise defined, the technical or scientific terms used in the embodiments disclosed herein should be understood in the general sense by those of ordinary skill in the art to which the present disclosure belongs.

The embodiments disclosed herein are not necessarily limited to the dimensions indicated, and the shapes and sizes of various components in the accompanying drawings do not reflect the actual proportions. Furthermore, the accompanying drawings schematically show desirable examples, and the embodiments disclosed herein are not limited to the shapes or numerical values shown in the accompanying drawings.

Ordinal numbers such as “first”, “second”, and “third” in the embodiments disclosed herein are used to avoid confusion about constituent elements and do not indicate any order, quantity, or importance.

In the embodiments disclosed herein, for convenience, terms indicating orientations or positional relationships such as “middle”, “upper”, “lower”, “front”, “back”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, and “outer” are used to refer to the positional relationships of the constituent elements in the accompanying drawings. The terms are merely used to facilitate the description of the specification and simplify the description and do not indicate or imply that the referred apparatuses or elements must possess a specific orientation, be constructed and operated in a particular orientation, and thus should not be considered as limiting the scope of the embodiments disclosed herein. The positional relationships of the constituent elements are appropriately changed according to the direction in which the constituent elements are described. Therefore, the terms used in the disclosure are not limiting and can be appropriately replaced according to the context.

In the embodiments disclosed herein, unless explicitly defined and limited, terms like “install”, “connect”, and “link” should be understood broadly. For example, the terms can imply a fixed connection, a detachable connection, or an integral connection, imply mechanical or electrical connections, and imply a direct connection, or an indirect connection through an intermediate medium, or an internal communication within two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments disclosed herein are interpreted according to specific conditions.

In the embodiments disclosed herein, in the case that the transistors having opposite polarities are used, or in the case that a current direction during circuit operation changes, the functions of the “source” and the “drain” may sometimes be interchanged. Therefore, in the embodiments disclosed herein, “source” and “drain” may be interchanged with each other.

In the embodiments disclosed herein, “electrical connection” includes the scenario where constituent elements are connected via elements that have some electrical function. There are no particular restrictions on the “elements that have some electrical function” as long as these elements can facilitate the transmission and reception of electrical signals between connected constituent elements. Examples of the “elements that have some electrical function” include not only electrodes and wiring but also switching elements like transistors, resistors, inductors, capacitors, and other elements with various functions.

In the embodiments disclosed herein, “parallel” refers to approximately parallel or nearly parallel, for example, in the case where two straight lines form an angle between −10° and 10°, which therefore also includes the cases where the angle is between —5° and 5°. In addition, “perpendicular” refers to approximately perpendicular, for example, in the case where two straight lines form an angle between 80° and 100°, which therefore also includes the cases where the angle is between 85° and 95°.

The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalents, improvements, and the like made within the spirit and principle of the present disclosure should fall within the protection scope of the present disclosure.