Methods of forming thin film resistor structures utilizing interconnect liner materials

Methods/structures of forming thin film resistors using interconnect liner materials are described. Those methods/structures may include forming a first liner in a first trench, wherein the first trench is disposed in a dielectric layer that is disposed on a substrate. Forming a second liner in a second trench, wherein the second trench is adjacent the first trench, forming an interconnect material on the first liner in the first trench, adjusting a resistance value of the second liner, forming a first contact structure on a top surface of the interconnect material, and forming a second contact structure on the second liner.

CLAIM OF PRIORITY

This Application is a National Stage Entry of, and claims priority to, PCT Application No. PCT/US16/69153, filed on Dec. 29, 2016, and titled “METHODS OF FORMING THIN FILM RESISTOR STRUCTURES UTILIZING INTERCONNECT LINER MATERIALS”, which is incorporated by reference in its entirety for all purposes.

BACKGROUND

Thin film resistors may be used utilized in the fabrication of microelectronic devices, such as in the fabrication of integrated chips/devices. These resistor structures often require removal process steps, such as polishing process, in order to fabricate the resistor structures. In some cases, such removal processes may negatively impact the density of underlying interconnect structures, which may comprise routable conductive traces within a device, for example.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the methods and structures may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the embodiments. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the embodiments.

The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the embodiments is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals may refer to the same or similar functionality throughout the several views. The terms “over”, “to”, “between” and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “over” or “on” another layer or bonded “to” another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers. Layers and/or structures “adjacent” to one another may or may not have intervening structures/layers between them. A layer(s)/structure(s) that is/are directly on/directly in contact with another layer(s)/structure(s) may have no intervening layer(s)/structure(s) between them. Embodiments of methods of forming device structures, such as methods of forming thin film resistors using interconnect liner materials, are described. Those methods/structures may include forming a first liner in a first trench, wherein the first trench is disposed in a dielectric layer that is disposed on a substrate. Forming a second liner in a second trench, wherein the second trench is adjacent the first trench, forming an interconnect material on the first liner in the first trench, adjusting a resistance value of the second liner, forming a first contact structure on a top surface of the interconnect material, and forming a second contact structure on the second liner. The embodiments herein enable the formation of thin film resistor structures which are patterned within the same layer of as an interconnect structure.

The various Figures herein illustrate embodiments of fabricating thin film resistor structures comprising interconnect structure liner material, such as titanium and or tantalum containing liner materials, for example. InFIG. 1a(cross-sectional view), a portion of a device/die100, such as a microelectronic die, is shown. The portion of the device100may comprise a substrate101, such as a silicon substrate, for example. The substrate101may be a monocrystalline silicon substrate, in an embodiment. The substrate101may also be other types of substrates, such as silicon-on-insulator (“SOI”), germanium, gallium arsenide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, and the like, any of which may be combined with silicon.

A dielectric material/layer102may be disposed on the substrate100. The dielectric layer may comprise an interlayer dielectric material (ILD) in an embodiment, and may comprise one or more of an oxide, such as silicon dioxide (SiO2), silicon oxide (SiO), carbon-doped SiO2, for example, a nitride, such as silicon nitride (Si3N4), a polymer, such as perfluorocyclobutane (C4F8) and/or polytetrafluoroethylene (PTFE), a phosphosilicate glass (PSG), a fluorosilicate glass (FSG), an organosilicate glass (OSG), such as silsesquioxane, siloxane, and/or a combination of any of the aforementioned. In an embodiment, the dielectric layer102may comprise low-κ dielectric material having a dielectric constant that is less than the dielectric constant of silicon dioxide (SiO2). In some embodiments, the dielectric layer102may be substantially non-porous, whereas in some other embodiments, the dielectric layer102may be provided with any degree of porosity, as desired for a given application.

A plurality of trenches/interconnect structures107may be disposed adjacent to each other within the dielectric layer102. In an embodiment, the individual ones of the plurality of trenches107may comprise a liner104, and an interconnect material106within each of the individual ones of the plurality of trenches107. In an embodiment, each of the individual trenches107may comprise sidewall portions ones132and may comprise a bottom portion134. In some embodiments, the liner104may be at least partially conductive and may be disposed between the dielectric layer102and the interconnect material106. The liner104may be disposed on at least a portion of the sidewalls132and on at least a portion of the bottom portion134of the trench structures107. The trench structures107are depicted as rectangular in the figure, however other shapes are possible, such as wherein the bottom portion134of the trench107is rounded, and wherein the sidewalls132possess a slanted profile, for example.

In an embodiment, the liner104may comprise an interconnect barrier layer/liner104. By way of illustration and not limitation, the liner104may be formed using techniques such as physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), low pressure CVD or other such methods as applicable to the particular design requirements. In an embodiment, the liner104can include any one of the following materials: tantalum, tungsten, titanium, ruthenium, molybdenum, and their alloys with nitrogen, silicon and carbon. In another embodiment, the liner104may comprise such materials as silicon nitride (Si3N4), silicon dioxide (SiO2), silicon oxynitride (SiOxNy), titanium nitride (TiN), and silicon carbon nitride (SiCN).

Although a few examples of materials that may be used to form liner104are described here, the liner104may be made from other materials that serve to prevent the diffusion of a metal across the liner104, in an embodiment. The liner104can range from about 1 nm to about 10 nm in thickness, in an embodiment, however in other embodiments the liner104may be formed from a variety of materials, thicknesses or multiple layers of material.

The interconnect material106may comprise various conductive materials, such as copper exclusively, or its alloys with tin, indium, cadmium, aluminum, magnesium, or its alloys with noble metals such as silver, palladium, platinum, rhodium, ruthenium, gold, iridium and osmium, for example. The interconnect material106may serve to form interconnect traces/routing traces, which may comprise multiple levels of interconnection structures107that are used to connect/route circuit elements (such as to planar and/or trigate transistor structures and to passive elements such as resistors for example) within the device100, to each other. The interconnect material106may be formed by electroless and/or electroplating techniques, in an embodiment.

In an embodiment, the array of interconnect structures107may be disposed in a region105, which may comprise a level/layer of metallization within the device100. The array of trenches/interconnect structures107may be disposed/formed in the same layer105during fabrication, such that top surfaces136of the interconnect material106are disposed directly on an etch stop material108. In an embodiment, the etch stop material108may comprise such materials as silicon carbide, silicon nitride, silicon carbon nitride, however it may be formed from a variety of materials, thicknesses or multiple layers of material, in other embodiments.

The etch stop material/layer108may be formed from materials which serve to stop the etching of the interconnect material106during fabrication, such as during lithographic, etching and cleaning processing steps, for example, and may be formed by techniques such as PVD, ALD, conventional CVD, low pressure CVD. The etch stop layer108can range from about 100 angstroms to about 1000 angstroms, in some embodiments. In an embodiment, the trenches/interconnect structures107may be formed utilizing a dual damascene process, in which vias and trenches (not shown) are etched into a dielectric layer, such as the dielectric layer102. Metal layers, which may comprise interconnect material106, are then formed over the vias and trenches. This process can be repeated to achieve interconnection, through the trenches and vias, of multiple layers of metallization within the device100.

InFIG. 1b, a patterning stack, which may comprise a hard mask material110disposed on the etch stop108, an anti-reflective coating (ARC)112disposed on the hard mask110, and a photoresist material114disposed on the ARC material112, may be employed to pattern the etch stop108and underlying interconnect material106′ of a trench structure107′, in an embodiment. An opening111may be formed in the patterning stack above a trench structure107′, and then a portion of the etch stop108may be removed by utilizing an etch stop removal process113, such as a dry and/or wet etch process, for example (FIG. 1c). The interconnect material106′ may then be removed from the trench structure107′, the utilizing any suitable removal process, such as removal process115, in an embodiment, wherein the liner104′ remains in the trench107′ (FIG. 1d). In an embodiment, the removal process115may comprise a selective etch process, wherein an etchant may comprise a high etch rate for the interconnect material106′, but may comprise a low to negligible etch rate for the liner material104′. In an embodiment, the liner104′ may comprise a titanium liner, and the interconnect material106′ may comprise copper, wherein the etchant may be selectively remove copper and not titanium. In another embodiment, the interconnect material106′ may comprise tungsten, and the liner104′ may comprise titanium nitride, wherein the etchant may selectively remove tungsten, and not remove titanium nitride.

In an embodiment, a treatment117may be performed to modulate/adjust a resistance value of the liner104′, to form a resistance adjusted liner105, which may comprise a thin film resistor105(FIG. 1e). For example, a plasma treatment117may be performed, wherein a resistance of the liner104′ may be modulated by the application of any suitable plasma process to produce a resistance adjusted liner105, which may comprise a thin film resistor105.

In another embodiment, the treatment117may comprise a process which may provide a dopant species to incorporate into the thin film resistor105, wherein the dopant species may comprise any suitable dopant species, for example, such as phosphorus or boron, which may be impregnated into the liner material104′ to produce a thin film resistor105. In another embodiment, the liner104′ may be removed from the trench107′ (FIG. 10by a removal process119, and a second liner105may be formed on the sidewalls132and bottom portion134of the trench107′ (FIG. 1g). In an embodiment, the second liner105may comprise a thin film resistor105, wherein the material selection/composition of the thin film resistor105may be tailored depending upon the requirements of the particular resistor design/value.

In an embodiment, a dielectric material124may be formed in the trench107′ and on the resistor105(FIG. 1h). The dielectric material124may comprise an ILD, in an embodiment, but may comprise any suitable dielectric material, according to the application. The dielectric material124may be disposed directly on the thin film resistor/second liner105, and may be disposed within the trench107′. In an embodiment, a portion of the dielectric material124may be removed from the trench (FIG. 1i). A first opening127, which may comprise a via and trench in an embodiment, may be formed/patterned in a second dielectric layer126, wherein the first opening127may comprise a damascene trench and via structure, and may be formed adjacent the trench107′, and the dielectric material124, in an embodiment.

In an embodiment, a second opening129may be formed in the second dielectric layer126, adjacent a trench107, wherein the trench107comprises the interconnect material106. In an embodiment, the trench107comprises a first trench107with the interconnect material106disposed within the trench107and disposed on a first liner104, wherein the first liner104comprises a barrier layer104, and does not comprise a thin film resistor. In an embodiment, the first liner104may comprise different materials than the second liner105, since the first liner104comprises a barrier layer, in an embodiment, and the second liner105comprises a thin film resistor. Additionally, the first and second liners104,105may comprise different resistance values from each other, with the thin film resistor105being much less conductive than the first liner104. In an embodiment, the resistance values of the thin film resistor may comprise between about 2 micro Ohm-cm to greater than about 20000 micro Ohm-cm.

In an embodiment, the trench107′ may comprise a second trench107′, wherein the second trench107′ does not comprise the interconnect material106, and wherein the second liner105comprises a thin film resistor105. In an embodiment, a first contact structure130may be disposed on a top surface of the interconnect material106disposed in the first trench107, and may be electrically coupled with the interconnect material106(FIG. 1j). In an embodiment, a second contact structure132may be disposed on a top surface of the dielectric material124that is disposed within the second trench107′. In an embodiment, the dielectric material124may be disposed in a first portion136of the second trench107′ and a portion of the second contact structure132may be disposed in a second portion138of the trench107′.

In an embodiment, the second contact structure132may extend a distance of about ⅓ to about ½ into the depth of the second trench107′, but may extend other distances into the second contact132in other embodiments. The first contact130may not extend any appreciable distance into the first trench107, since it makes contact to the surface of the interconnect material106and not to a thin film resistor. In an embodiment, the contact material of the first and second contact structures130,132may comprise copper, and/or tungsten and alloys thereof.

In an embodiment, a portion of the second contact structure132may be physically disposed on the second liner/thin film resistor105in the second trench107′, and may be electrically coupled with the thin film resitor105. In an embodiment, the first liner104and the second liner105may comprise different materials, since the second liner105is treated to adjust the resistance value of the resistor material. Additionally, there may be structural differences (grain boundaries, intermetallics, etc) that may be present in the thin film resistor105due to the treatment/adjustment performed inFIG. 1e, for example.

In an embodiment, the thin film resistor105may comprise different concentrations/chemical composition of materials than the first liner104of the first trench107, such as different percentages of elements within the resistor film105as compared with the first liner104. In an embodiment, the thin film resistor105may comprise such materials as tantalum, titanium, nitrogen, tantalum, titanium, copper, titanium nitride, tantalum oxide, tungsten, cobalt, ruthenium, nickel, silver, aluminum, and their alloys, for example, but other materials may be utilized according to the required resistance values for a particular application, which may comprise about 100 Ohm to about 10 MOhm, in an embodiment. In an embodiment, the thin film resistor105may comprise similar materials as the first liner, but in different percentages, due to the resistor adjustment process. In an embodiment, the resistor105may be formed in any number of trench structures107, according to the embodiments herein, within an array of trench structures107, depending upon the particular design requirements of the device100.

In another embodiment, a plurality of trenches/interconnect structures207may be disposed adjacent to each other within a dielectric layer202of a device200(FIG. 2a, showing a cross-sectional view, perpendicular to the interconnect material206). In an embodiment, the individual ones of the plurality of trenches207may comprise a liner204, and an interconnect material206within each of the individual ones of the plurality of trenches207. The liner204and interconnect material206may comprise any of the liner materials and interconnect materials, respectively, previously described herein. In an embodiment, each of the individual trenches207may comprise sidewall portions232and a bottom portion234. In some embodiments, the liner204may be at least partially conductive and may be disposed between the dielectric layer202and the interconnect material206.

The liner204may be disposed on at least a portion of the sidewalls232and on at least a portion of the bottom portion234of the trench structures207. An etch stop material208may be disposed on top surfaces of the interconnect material206.FIG. 2a′ depicts a cross-sectional view parallel to the interconnect material206, wherein trench structures207are disposed in the dielectric material202, and the etch stop material208is on the top surface of the trench structures207.FIGS. 2b′,2c′ and the like described subsequently herein, similarly refer to cross sectional views parallel to the interconnect material206.

FIGS. 2b-2cdepict patterning and formation of an opening perpendicular to the interconnect material206, andFIGS. 2b′-2c′ depict the fabrication of the opening parallel to the interconnect material206, wherein a mask material227is employed. Trench opening209and then via opening210(which may comprise a damascene structure210) are formed, wherein the interconnect material206and the liner204are removed from the trench207′. A thin film resistor material/structure205, which may comprise any of the thin film resistor materials/fabrication techniques previously described herein, may be formed in the opening210, wherein a resistor deposition process212may be employed (FIGS. 2d, 2d′). The resistor material205may comprise any suitable thickness, and may comprise a thickness of between about 1 nm to about 10 nm, in an embodiment. The resistance value of the thin film resistor205may comprise any suitable value, depending upon the particular design requirements. The thin film resistor205may line the sidewalls and bottom portion of the trench207′.

A dielectric material224may be formed in the trench207′ and on the thin film resistor structure205(FIGS. 2e, 2e′), and then the hard mask227may be removed (FIG. 2f, 2f). A portion of the dielectric material224may be removed/trimmed from a sidewall portion of the thin film resistor205(FIGS. 2g, 2g′) using any suitable removal process, such as an etch process, for example. The thin film resistor205may optionally be trimmed using a laser trim process, for example, wherein the sidewall portions of the resistor205may be removed, and the bottom portion of the resistor205remains under the dielectric material224(FIGS. 2h, 2h′). The trimming of the resistor205may be performed to adjust the resistance value of the resistor205to a desired value for a particular application.

After the dielectric material224and resistor205have been trimmed, a second dielectric material may be formed to fill in the space between the dielectric224and the sidewall of the trench207′ (FIG. 2i, 2i′). The dielectric material224may then be polished/planarized by utilizing a chemical mechanical polishing (CMP) process, for example, to substantially achieve planarity with the etch stop layer208, in an embodiment. In an embodiment, a contact structure230may be disposed on a top surface of the trimmed resistor205(subsequent to the removal of the dielectric material224from the trench207′) that is disposed within and on the bottom portion of the trench207′ (FIGS. 2j, 2j′). In an embodiment, the contact material of the contact structure230may comprise copper, and/or tungsten and alloys thereof, and may be physically and electrically coupled with the trimmed resistor205.

The trim process serves to reduce a width or a length of the resistor205in order to increase resistance, if necessary for design requirements. Additionally, since the thin film resistor205is formed around the topography of the originally patterned trench (for example,FIG. 2kdepicts an undulating resistor structure205around the patterned dielectric), the sheet resistance of the thin film resistor205may be increased by about 3 to about 50 times that of a non-undulating resistor205. In an embodiment, the resistor205may be formed around multiple plug structures211disposed beneath the etch stop material208. In an embodiment, the amount of resistance increase can be controlled by changing the conformality of the resistor deposition, wherein a less conformal desposition increases the resistance of the resistor205, more than a deposition comprising greater conformality.

FIG. 3depicts a method300according to embodiments herein. At step302, a first liner may be formed in a first trench, wherein the first trench is disposed in a dielectric layer that is disposed on a substrate. At step304, a second liner may be formed in a second trench, wherein the second trench is adjacent the first trench. The first and second trenches may be a portion of an array of trenches, which may be disposed in the same metal layer within a device. In an embodiment, the first and second trenches may be substantially parallel with one another, and the liner material may comprise an interconnect barrier layer.

At step306, an interconnect material may be formed on the first liner in the first trench. The interconnect material may comprise copper and/or copper alloys, in an embodiment. At step308, a resistance value of the second liner may be adjusted. The resistance value may be adjusted by various methods, such as by removing the second liner and replacing it with a thin film resistor comprising a desired resistor value. In another embodiment, the resistance value of the second liner may be adjusted by applying a plasma treatment and/or by doping the second liner with a dopant species in order to achieve a desired resistance value.

At step310, a first contact structure may be formed on a top surface of the interconnect material. At step312, a second contact structure may be formed on the second liner. In an embodiment, a dielectric material may be disposed on a top portion of the second liner, and the second contact may be physically and electrically coupled with a sidewall portion of the second liner. In another embodiment, the second contact structure may be physically and electrically coupled with a trimmed thin film resistor/second liner that is disposed on a bottom portion of the second trench.

The embodiments herein enable the fabrication of thin film resistors using interconnect liner materials. Thin film resistors of the embodiments herein are patterned in the same layer as the interconnect structures, which avoids added topography and requires zero metal density in surrounding layers, which in turn minimizes capacitance and shorting risks. Patterning the thin film resistor in the same layer as the interconnect structure reduces topography in the interconnect region, improves interconnect density near the thin film resistor region, and allows for the use of non-dry etch-able materials as thin film resistors. Dual damascene patterning may be employed wherein an additional mask may be used to remove the bulk interconnect material selectively to expose the interconnect liner in desired regions where a resistor may be formed. The contact via above the thin film resistor may land on the liner material/resistor, with no additional changes required from a typical process flow.

The microelectronic device structures of the embodiments herein may be coupled with any suitable type of structures capable of providing electrical communications between a microelectronic device, such as a die, disposed in package structures, and a next-level component to which the package structures may be coupled (e.g., a circuit board). The device/package structures, and the components thereof, of the embodiments herein may comprise circuitry elements such as logic circuitry for use in a processor die, for example. Metallization layers and insulating material may be included in the structures herein, as well as conductive contacts/bumps that may couple metal layers/interconnects to external devices/layers. In some embodiments the structures may further comprise a plurality of dies, which may be stacked upon one another, depending upon the particular embodiment. In an embodiment, the die(s) may be partially or fully embedded in a package structure.

The various embodiments of the device/die structures included herein may be used for system on a chip (SOC) products, and may find application in such devices as smart phones, notebooks, tablets, wearable devices and other electronic mobile devices. In various implementations, the package structures may be included in a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder, and wearable devices. In further implementations, the package devices herein may be included in any other electronic devices that process data.

The embodiments herein may include portions of die/device structures, which may comprise any type of integrated circuit die/device. In one embodiment, the die may include a processing system (either single core or multi-core). For example, an integrated circuit (IC) die may comprise a microprocessor, a graphics processor, a signal processor, a network processor, a chipset, etc. In one embodiment, the IC die120comprises a system-on-chip (SoC) having multiple functional units (e.g., one or more processing units, one or more graphics units, one or more communications units, one or more signal processing units, one or more security units, etc.). However, it should be understood that the disclosed embodiments are not limited to any particular type or class of IC devices/die.

Conductive interconnect structures may be disposed on a side(s) of a die/device, and may comprise any type of structure and materials capable of providing electrical communication between a die/device and a substrate, or another die/device, for example. In an embodiment, conductive interconnect structures may comprise an electrically conductive terminal on a die (e.g., a pad, bump, stud bump, column, pillar, or other suitable structure or combination of structures) and a corresponding electrically conductive terminal on a substrate (e.g., a pad, bump, stud bump, column, pillar, or other suitable structure or combination of structures). Solder (e.g., in the form of balls or bumps) may be disposed on the terminals of the substrate and/or die/device, and these terminals may then be joined using a solder reflow process. Of course, it should be understood that many other types of interconnects and materials are possible (e.g., wirebonds extending between a die and a substrate).

The terminals on a die may comprise any suitable material or any suitable combination of materials, whether disposed in multiple layers or combined to form one or more alloys and/or one or more intermetallic compounds. For example, the terminals on die may include copper, aluminum, gold, silver, nickel, titanium, tungsten, as well as any combination of these and/or other metals. In other embodiments, a terminal may comprise one or more non-metallic materials (e.g., a conductive polymer). The terminals on a substrate may also comprise any suitable material or any suitable combination of materials, whether disposed in multiple layers or combined to form one or more alloys and/or one or more intermetallic compounds.

For example, the terminals on substrate may include copper, aluminum, gold, silver, nickel, titanium, tungsten, as well as any combination of these and/or other metals. Any suitable solder material may be used to join the mating terminals of the die and substrate, respectively. For example, the solder material may comprise any one or more of tin, copper, silver, gold, lead, nickel, indium, as well as any combination of these and/or other metals. The solder may also include one or more additives and/or filler materials to alter a characteristic of the solder (e.g., to alter the reflow temperature).

Various die/devices of the embodiments herein may be coupled with a substrate, such as a package substrate. A package substrate may comprise any suitable type of substrate capable of providing electrical communications between a die, such as an integrated circuit (IC) die, and a next-level component to which an IC package may be coupled (e.g., a circuit board). In another embodiment, the substrate may comprise any suitable type of substrate capable of providing electrical communication between an IC die and an upper IC package coupled with a lower IC/die package, and in a further embodiment a substrate may comprise any suitable type of substrate capable of providing electrical communication between an upper IC package and a next-level component to which an IC package is coupled.

Turning now toFIG. 4, illustrated is an embodiment of a computing system400. The system400includes a mainboard410, such as a motherboard or other circuit board. Mainboard410includes a first side401and an opposing second side403, and various components may be disposed on either one or both of the first and second sides401,403. In the illustrated embodiment, the computing system400includes a die402, such as any of the die/device structures of the embodiments herein, disposed on a substrate404. The substrate404may comprise an interposer404, for example. The substrate404may comprise various levels of conductive layers414,408, for example, which may be electrically and physically connected to each other by via structures410. The substrate404may further comprise through substrate vias412. Dielectric material405may separate/isolate conductive layers from each other within the substrate404. Joint structures406, may electrically and physically couple the substrate404to the board410. The computing system400may comprise any of the embodiments described herein.

System400may comprise any type of computing system, such as, for example, a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile interne device, a music player, a tablet computer, a laptop computer, a nettop computer, etc.). However, the disclosed embodiments are not limited to hand-held and other mobile computing devices and these embodiments may find application in other types of computing systems, such as desk-top computers and servers.

Mainboard410may comprise any suitable type of circuit board or other substrate capable of providing electrical communication between one or more of the various components disposed on the board. In one embodiment, for example, the mainboard410comprises a printed circuit board (PCB) comprising multiple metal layers separated from one another by a layer of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route—perhaps in conjunction with other metal layers—electrical signals between the components coupled with the board410. However, it should be understood that the disclosed embodiments are not limited to the above-described PCB and, further, that mainboard1010may comprise any other suitable substrate.

FIG. 5is a schematic of a computing device500that may be implemented incorporating embodiments of the package structures described herein. For example, any suitable ones of the components of the computing device500may include, or be included in, device/die structures of the various embodiments disclosed herein. In an embodiment, the computing device500houses a board502, such as a motherboard502for example. The board502may include a number of components, including but not limited to a processor504, an on-die memory506, and at least one communication chip508. The processor504may be physically and electrically coupled to the board502. In some implementations the at least one communication chip1108may be physically and electrically coupled to the board502. In further implementations, the communication chip508is part of the processor504.

Depending on its applications, computing device500may include other components that may or may not be physically and electrically coupled to the board502, and may or may not be communicatively coupled to each other. These other components include, but are not limited to, volatile memory (e.g., DRAM)509, non-volatile memory (e.g., ROM)510, flash memory (not shown), a graphics processor unit (GPU)512, a chipset514, an antenna516, a display518such as a touchscreen display, a touchscreen controller520, a battery522, an audio codec (not shown), a video codec (not shown), a global positioning system (GPS) device526, an integrated sensor528, a speaker530, a camera532, compact disk (CD) (not shown), digital versatile disk (DVD) (not shown), and so forth). These components may be connected to the system board502, mounted to the system board, or combined with any of the other components.

The computing device500may include a plurality of communication chips508. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

Embodiments of the package structures described herein may be implemented as a part of one or more memory chips, controllers, CPUs (Central Processing Unit), microchips or integrated circuits interconnected using a motherboard, an application specific integrated circuit (ASIC), and/or a field programmable gate array (FPGA).

EXAMPLES

Example 1 is a microelectronic device structure comprising: a first trench disposed in a dielectric layer, wherein the dielectric layer comprises a portion of a substrate, and wherein the first trench comprises a first liner disposed on at least a portion of a sidewall of the first trench, and wherein an interconnect material is disposed within the first trench adjacent the first liner; a second trench disposed adjacent the first trench, wherein the second trench comprises a second liner disposed on at least a portion of a sidewall within the second trench; a dielectric material disposed on the second liner within the second trench; and a contact structure physically and electrically coupled to the second liner material in the second trench.

Example 2 includes the microelectronic device structure of example 1, wherein the second liner material comprises a thin film resistor.

Example 3 includes the microelectronic device structure of example 2 wherein the thin film resistor comprises a material selected from the group consisting of tantalum, titanium, tantalum, titanium, copper, titanium nitride, tantalum oxide, tungsten, cobalt, ruthenium, nickel, silver, aluminum, and alloys thereof.

Example 4 includes the microelectronic device structure of example 1 wherein the first liner material comprises an interconnect barrier layer.

Example 5 includes the microelectronic device structure of example 1 wherein the second liner material comprises a dopant species.

Example 6 includes the microelectronic device structure of example 1 wherein the first liner comprises a different material than the material of the second liner.

Example 7 includes the microelectronic device structure of example 1 wherein the second liner comprises an undulating structure.

Example 8 includes the microelectronic device structure of example 1 wherein the second trench does not comprise the interconnect material.

Example 9 is a microelectronic device structure comprising: a substrate; a dielectric layer on the substrate; an array of trenches disposed in the dielectric layer, wherein a first trench and a second trench are adjacent each other, and wherein an interconnect material is disposed within the first trench and is disposed on a first liner disposed within the first trench, and wherein the second trench comprises a second liner that is disposed within the second trench, and wherein the second trench does not comprise the interconnect material; a first contact structure disposed on a top surface of the interconnect material; and a second contact structure disposed on the second liner within the second trench.

Example 10 includes the microelectronic device structure of example 9 wherein a dielectric material is disposed on the second liner within the second trench.

Example includes the microelectronic device structure of example 10 wherein the second contact structure is disposed on the dielectric material.

Example 12 includes the microelectronic device structure of example 9 wherein the first liner and the second liner comprise different materials from each other.

Example 13 includes the microelectronic device structure of example 9 wherein the interconnect material comprises at least one of copper titanium nitride, tantalum oxide, tungsten, cobalt, ruthenium, nickel, silver, or aluminum, or combinations thereof.

Example 14 includes the microelectronic device structure of example 9 wherein the second liner comprises an undulating structure around the dielectric topography.

Example 15 includes the microelectronic device structure of example 9 wherein the second liner is disposed on a bottom portion of the trench, and not on a sidewall portion of the trench.

Example 16 includes the device structure of example 9, wherein the second liner is disposed on a sidewall of the second trench.

Example 17 is a method of forming a microelectronic device, comprising: forming a first liner in a first trench, wherein the first trench is disposed in a dielectric layer that is disposed on a substrate; forming a second liner in a second trench, wherein the second trench is adjacent the first trench; forming an interconnect material on the first liner in the first trench; adjusting a resistance value of the second liner; forming a first contact structure on a top surface of the interconnect material; and forming a second contact structure on the second liner.

Example 18 includes the method of example 17 wherein adjusting the resistance value comprises removing the second liner and forming a thin film resistor in the second trench, wherein the thin film resistor comprises a targeted resistance value.

Example 19 includes the method of example 17 wherein adjusting the resistance value comprises implanting a dopant species within the second liner to adjust the resistance value.

Example 20 includes the method of example 17 wherein adjusting the resistance value comprises applying a plasma treatment to the second liner to adjust the resistance value.

Example 21 includes the method of example 17 wherein the first liner comprises a material selected from the group consisting of tantalum, tungsten, titanium, ruthenium, molybdenum, and their alloys with nitrogen, silicon and carbon.

Example 22 includes the method of example 17 further comprising wherein the second liner comprises a thickness of between about 1 nm to about 10 nm.

Example 23 includes the method of example 17 further comprising wherein the second trench does not comprise the interconnect material.

Example 24 includes the method of example 17 further comprising wherein the interconnect material comprises copper.

Example 25 includes the method of example 17 wherein the second liner is not disposed on a sidewall of the second trench.

Example 26 includes the method of example 17 wherein the second liner is disposed in an undulating structure around a portion of the dielectric layer.

Example 27 includes the method of example 17 wherein the thin film resistor comprises a material selected from the group consisting of tantalum, titanium and copper.

Example 28 includes the method of example 17 wherein a dielectric material is disposed on the second liner within the second trench.

Although the foregoing description has specified certain steps and materials that may be used in the methods of the embodiments, those skilled in the art will appreciate that many modifications and substitutions may be made. Accordingly, it is intended that all such modifications, alterations, substitutions and additions be considered to fall within the spirit and scope of the embodiments as defined by the appended claims. In addition, the Figures provided herein illustrate only portions of exemplary microelectronic devices and associated package structures that pertain to the practice of the embodiments. Thus the embodiments are not limited to the structures described herein.