Frequency divider

A frequency divider circuit comprises a first divider chain including at least one first divider cell and a second divider chain coupled to the first divider chain to form an extendable divider chain. The second divider chain includes at least one second divider cell with a respective reset control. An effective length of the extendable divider chain may be altered, dynamically, via the respective reset control. Altering the effective length, dynamically, enables a division ratio of the frequency divider circuit to be changed, dynamically. The frequency divider circuit may be advantageously employed by applications that rely upon a dynamic division ratio, such as a fractional-N (frac-N) phase-locked loop (PLL).

BACKGROUND

A phase-locked loop (PLL), also referred to interchangeably herein as a frequency synthesizer, is a negative feedback system that locks a phase and frequency of a higher frequency device, usually a voltage controlled oscillator (VCO), whose phase and frequency are not very stable over temperature and time, to a more stable and lower frequency device, usually a temperature compensated or oven controlled crystal oscillator. A PLL is typically employed when there is a need for a high frequency local oscillator (LO) source. Example applications of PLLs are numerous and include wireless communications, medical devices, and instrumentation.

SUMMARY

According to an example embodiment, a frequency divider circuit may comprise a first divider chain including at least one first divider cell and a second divider chain coupled to the first divider chain to form an extendable divider chain. The second divider chain may include at least one second divider cell with a respective reset control. An effective length of the extendable divider chain may be altered, dynamically, via the respective reset control.

The frequency divider circuit may be configured to receive an input frequency signal with an input frequency and generate a divided output frequency signal with a divided output frequency that is a function of the input frequency and a division ratio. The effective length of the extendable divider chain may be a total number of divider cells in the extendable divider chain that influence the division ratio.

The frequency divider circuit may be configured to receive an input frequency signal and generate a divided output frequency signal. The frequency divider circuit may further comprise an output frequency generator circuit. The output frequency generator circuit may be configured to perform a logical NOR of each output modulus signal generated by the first divider chain to generate the divided output frequency signal.

The frequency divider circuit may be further configured to receive a set of division ratio control signals. Each of the at least one first and second divider cells may be configured to receive a respective programming input signal for controlling a respective division mode of the at least one first and second divider cells. The frequency divider circuit may further comprise a division ratio update circuit. The division ratio update circuit may be configured to update each respective programming input signal to a respective division ratio control signal of the set of division ratio control signals in response to a rising edge of the divided output frequency signal.

The frequency divider circuit may further comprise a length altering circuit. The length altering circuit may be configured to alter, dynamically, the effective length of the extendable divider in response to a rising edge of the divided output frequency signal.

The frequency divider circuit may further comprise a reset generator circuit configured to generate a respective reset control signal for controlling the respective reset control of each at least one second divider cell. The reset generator circuit may be further configured to update a respective state of the respective reset control signal in response to a falling edge of the divided output frequency signal.

The respective reset control signal may be configured to be a function of at least one respective programming input signal received for controlling the respective division mode of the at least one second divider cell.

Each at least one second divider cell may be configured to generate a respective modulus output signal and to set the respective modulus output signal to an active level in an event the respective reset control is asserted.

The frequency divider circuit may be employed by a fractional-N phase-locked loop (frac-N PLL). The frac-N PLL may be configured to be in a non-reset state throughout a dynamic change to the effective length of the extendable divider chain.

Each first divider cell of the at least one first divider cell may be a 2/3 divider cell and each second divider cell of the at least one second divider cell may be a resettable 2/3 divider cell.

According to another example embodiment, a method for performing frequency division by a frequency divider circuit may comprise employing a first divider chain including at least one first divider cell. The method may comprise coupling the first divider chain to a second divider chain to form an extendable divider chain. The second divider chain may include at least one second divider cell with a respective reset control. The method may comprise altering an effective length of the extendable divider chain, dynamically, via the respective reset control, enabling the frequency divider circuit to alter, dynamically, the frequency division performed.

The method may comprise receiving an input frequency signal with an input frequency and generating a divided output frequency signal with a divided output frequency that is a function of the input frequency and a division ratio. The effective length of the extendable divider chain may be a total number of divider cells in the extendable divider chain that influence the division ratio.

The method may comprise receiving an input frequency signal with an input frequency, generating a divided output frequency signal with a divided output frequency, and performing a logical NOR of each output modulus signal generated by the first divider chain to generate the divided output frequency signal.

The method may comprise receiving a set of division ratio control signals, receiving a respective programming input signal for controlling a respective division mode of the at least one first and second divider cells, and updating each respective programming input signal to a respective division ratio control signal of the set of division ratio control signals in response to a rising edge of the divided output frequency signal.

Altering the effective length may be performed in response to a rising edge of the divided output frequency signal.

The method may comprise generating a respective reset control signal for controlling a respective reset control of each at least one second divider cell and updating a respective state of the respective reset control in response to a falling edge of the divided output frequency signal.

The respective reset control signal may be a function of at least one respective programming input signal received for controlling the respective division mode of the at least one second divider cell.

The method may comprise generating, by each at least one second divider cell, a respective modulus output signal and setting the respective modulus output signal to an active level in an event the respective reset control is asserted.

The method may comprise employing the frequency divider circuit by a fractional-N phase-locked loop (frac-N PLL) and maintaining the frac-N PLL in a non-reset state throughout a dynamic change to the effective length of the extendable divider chain.

It should be understood that example embodiments disclosed herein can be implemented in the form of a method, apparatus, or system.

DETAILED DESCRIPTION

A basic building block of a phase-locked loop (PLL) is a feedback divider (N-divider) circuit, also referred to interchangeably herein as a frequency divider. When the feedback divider assumes integer values for N, the PLL is called an integer-N PLL, and when non-integer values are assumed, the PLL is called a fractional-N (frac-N) PLL. The frac-N PLL may lock faster when compared to a similar integer-N PLL because a lower value of N accommodated by the frac-N PLL allows a wider loop filter bandwidth which, in turn, may allow a faster lock time.

FIG. 1is a block diagram100of an example frac-N PLL120optionally within an embodiment disclosed herein. The frac-N PLL120includes a phase detector101, loop filter103, and voltage controlled oscillator (VCO)105. The VCO105generates an output frequency signal123which has a frequency proportional to a voltage at an input to the VCO105. The phase detector101may measure a phase difference between an input frequency signal121and a divided down version of the output frequency signal124. The loop filter103may be employed to prevent unwanted spurious noise that may be generated by the phase detector101from being superimposed on a control voltage to the VCO105. According to an example embodiment, the non-integer value of N may be changed, dynamically, during a locked state of the frac-N PLL120.

According to an example embodiment, the frac-N PLL120may employ a multi-modulus dividing circuit with a dynamically updating division ratio102to divide down the output frequency signal123. Example embodiments of the multi-modulus dividing circuit with the dynamically updating division ratio102are disclosed further below with reference toFIG. 2andFIG. 6. The frac-N PLL120may be implemented in any suitable manner, such as an integrated circuit (IC).

FIG. 2is a block diagram200of an example embodiment of a frequency divider circuit202. The frequency divider circuit202may be a multi-modulus divider circuit configured to receive an input frequency signal242and to generate a divided output frequency signal244. The frequency divider circuit202may comprise a first divider chain204including at least one first divider cell206and a second divider chain208that may be coupled to the first divider chain204to form an extendable divider chain with a dynamic division ratio210. The first divider chain204and the second divider chain208may be coupled.

For example, the first divider chain204and the second divider chain208may be coupled via a first divider chain output frequency signal245that may be output from an endmost first divider cell (not shown) of the first divider chain204that may be input to a starting second divider cell (not shown) of the second divider chain208. The first divider chain204and the second divider chain208may be further coupled via a second divider chain modulus signal246that may be output from the starting second divider of the second divider chain208cell and input to the endmost first divider cell of the first divider chain204.

The second divider chain208may include at least one second divider cell212with a respective reset control214. An effective length216of the extendable divider chain210may be altered, dynamically, via the respective reset control214. The effective length216of the extendable divider chain may be a total number of divider cells in the extendable divider chain that influence the division ratio. The effective length216may be a sum of a minimum length217and an extended length219. The minimum length217may be a first total number of first divider cells that compose the first divider chain204as each at least one first divider cell206may influence the division ration. The extended length219may be a second total number of second divider cells of the second divider chain208that actively influence the division ratio based on a respective state of the respective reset control214.

According to an example embodiment, each first divider cell of the at least one first divider cell206may be a 2/3 divider cell, such as the 2/3 divider cell ofFIG. 4, disclosed further below. Each second divider cell of the at least one second divider cell212may be a resettable 2/3 divider cell, such as the resettable 2/3 divider cell ofFIG. 12, disclosed further below.

The frequency divider circuit202may be employed by a frac-N PLL (not shown), such as the frac-N PLL120ofFIG. 1, disclosed above. For example, the input frequency signal242may be the output frequency signal123that is output from the VCO105ofFIG. 1and the divided output frequency signal244may be input to the phase detector101for comparison with an input frequency signal, such as the input frequency signal121ofFIG. 1, disclosed above.

The frac-N PLL120may be configured to be in a non-reset state throughout a dynamic change to the effective length216of the extendable divider chain210. For example, the frac-N PLL120may be able to maintain a locked state even though the dynamic change to the effective length216is made. As such, the frequency divider circuit202may be employed by applications, such as a frac-N PLL application, that may require dynamic changes to the division ratio with no adverse effect, such as no loss of lock of the frac-N PLL. Thus, the frequency divider circuit202provides an advantage over other frequency divider circuits that may have a limited range or a range that, while programmable, may be a statically programmable range, such as the prior art frequency divider circuits ofFIG. 3andFIG. 5, disclosed below.

FIG. 3is a circuit diagram300of a prior art frequency divider circuit, that is, the programmable prescaler301. The programmable prescaler301includes a chain of 2/3 divider cells303a-e. Each 2/3 divider cell of the 2/3 divider cells303a-edivides by either2or3, as disclosed with reference toFIG. 4, disclosed below.

FIG. 4is a circuit diagram400of a prior art 2/3 divider cell403. The 2/3 divider cell403divides a frequency of an input frequency signal407, that is, Fin, either by 2 or by 3, and outputs the divided clock signal411, that is, Fo, to a next cell (not shown) in a chain (not shown). A momentaneous division ratio of the 2/3 divider cell403may be based on a state of a modulus input signal405, also referred to interchangeably herein as a “mod_in” signal405, and a programming input signal409, also referred to interchangeably herein as the “p” input signal409. The mod_in signal405becomes active once in a division cycle. At that moment, a state of the p input signal409is checked.

If p==1, the 2/3 divider cell403is forced to swallow one extra period of the input frequency signal407. In other words, the 2/3 divider cell403divides by 3. If, however, p==0, the 2/3 divider cell403stays in division by 2 mode. Regardless of the state of the p input signal409, the mod_in signal405is re-clocked and the re-clocked version is output as the modulus output signal413, also referred to interchangeably herein as the mod_out signal413, that may be output to a preceding cell (not shown) in the chain (not shown).

Turning back toFIG. 3, the programmable prescaler301operates as follows. Once in a division period, a last cell on the chain (also referred to interchangeably herein as an endmost cell), that is, the 2/3 divider cell303eof the chain of 2/3 divider cells303a-e, generates the modulus input signal305, that is, modn-1. The modulus input signal305then propagates “up” the chain, being re-clocked by each cell along the way. An active modulus input signal enables a cell to divide by 3 (once in a division cycle), provided that its programming input signal p is set to 1, as disclosed above with reference toFIG. 4. Division by 3 adds one extra period of each cell's input signal to a period of the divided clock signal311, that is, Fo, to control the division ratio applied to the input frequency signal307(i.e., Fin).

InFIG. 3, the programming input signals309a-e(i.e., p0, . . . , pn-1) are the binary programming values of the cells1to n, respectively. As such, integer division ratios ranging from 2n(if all pn=0) to 2n+1−1 (if all pn=1) may be realized. A division range of the programmable prescaler301may be considered rather limited as the division range amounts to roughly a factor of two between maximum and minimum division ratios. Such a division range may be expanded to achieve a smaller division number, such as disclosed below with reference toFIG. 5.

FIG. 5is a circuit diagram500of a prior art programmable prescaler515with extended range. The divider implementation ofFIG. 5extends the division range of the prescaler ofFIG. 3, disclosed above. The operation of the programmable prescaler515with extended range may be based on a direct relationship between a performed division ratio and a bus programmed division word pn, pn−1, . . . , p1, p0. An effective length n′ of the chain may be a total number of divider cells that are effectively influencing the division cycle.

For example, by deliberately setting a modulus input signal, that is, a mod input of a particular 2/3 cell, to an active level overrules an influence of all cells to the right of that particular cell. As such, the divider chain behaves as if it has been shortened. The effective length n′ may correspond to an index of a most significant (and active) bit of the programmed division word pn, pn−1, . . . , p1, p0. In the programmable prescaler515, the OR gates517a-dare employed to adapt n′ to the programmed division word.

By employing the additional logic, that is, the OR gates517a-d, and signals pn, Gn−1, Gn−2, etc. for controlling modulus input control signals, the division range becomes:minimum division ratio: 2′minmaximum division ratio: 2n′+1−1.
The minimum and maximum division ratios may be set, independently, by choice of n′min319and n, respectively, where n corresponds to a total number of 2/3 cells in the chain and n′min319corresponds to a minimum number of 2/3 cells that always influence the division ratio for producing the divided clock signal511(i.e., Fo) from the input signal507(i.e., Fin).

The programmable prescaler515with extended range may be employed for applications in which a statically programmed division ratio is acceptable; however, such a design does not enable the division ratio to be changed, dynamically, as may be needed by applications, such as the frac-N PLL120ofFIG. 1, disclosed above.

Although the programmable prescaler515with extended range appears to cover from 2n′minto 2′n′+1−1, dynamic changes to the effective length n′ may result in errors, such as the errors1376ofFIG. 13, disclosed further below. An example embodiment disclosed herein enables such a dynamic change to the effective length n′ while the frac-N PLL maintains lock because no errors are introduced as a result of the dynamic change, as shown inFIG. 14, disclosed further below.

FIG. 6is a circuit diagram600of an example embodiment of a frequency divider circuit602that may be an example embodiment of a multi-modulus divider circuit, such as the frequency divider circuit202ofFIG. 2, disclosed above.

The frequency divider circuit602comprises a first divider chain604that includes at least one first divider cell, for example, nmin619first divider cells including the first divider cells633a-c, in the example embodiment. The nmin619first divider cells that include the first divider cells633a-cmay be any suitable number nmin619of first divider cells that always influence the division ratio.

The frequency divider circuit602comprises a second divider chain608that may be coupled to the first divider chain604to form an extendable divider chain610. For example, the first divider chain604and the second divider chain608may be coupled via the divided frequency output signal645(i.e., FOn-2) that may be output from the endmost first divider cell633cof the first divider chain604and input to the starting second divider cell622aof the second divider chain608. The first divider chain604and the second divider chain608may be further coupled via the second divider chain modulus signal646that may be gated via the OR gate647aof the OR gates647a-dand input to the endmost first divider cell633c. It should be understood that the number of the first and second divider cells ofFIG. 6are shown for illustrative purposes and that the first and second divider chains may be composed of an suitable number of first and second divider cells.

The second divider chain608may include at least one second divider cell with a respective reset control, such as the second divider cells620aand620bwith reset control622aand622b, respectively. An effective length n′ of the extendable divider chain610may be altered, dynamically, via the respective reset control, that is622aand622b, in the example embodiment.

For example, the second divider cells620aand620bmay be 2/3 cells with resettable latches, as disclosed with reference toFIG. 12, further below. By forcing an output modulus signal of a given second divider cell to an active state via the respective reset control, any second divider cell to the right of the given second divider cell may not influence the division ratio, effectively shortening the chain. Further, a length altering circuit may be employed in addition to the respective reset control to override the output modulus signal of the given second divider cell such that an inactive state is overridden such that an active state is propagated to a preceding cell instead, effectively shortening the chain.

For example, the frequency divider circuit602may further comprise a length altering circuit. The length altering circuit may be composed of the OR gates647a-dand the latches (i.e., flip-flops)649aand649b. The length altering circuit may be configured to alter, dynamically, the effective length of the extendable divider chain610in response to a rising edge of the divided output frequency signal644. For example, each of the latches649aand649bmay be configured to update a respective gating signal651aor651bin response to the rising edge of the divided output frequency signal644.

Each gating signal may be a function of one or more programming input signals and a latched version of each gating signal may be inverted and input to a respective OR gate of the OR gates647aor647bfor setting a modulus signal653aor653bto an active state to shorten the effective length. Updating the effective length with the rising edge of the divided output frequency signal644introduces an extra delay between a division number update and a divider length change, enabling such a dynamic change to be made without error, as shown inFIG. 14, disclosed further below. The divided output frequency signal644may be generated via an output frequency generator circuit, such as the output frequency generator circuit752ofFIG. 7, disclosed further below.

Turning back toFIG. 6, the frequency divider circuit602may be configured to receive an input frequency signal642with an input frequency and to generate a divided output frequency signal644with a divided output frequency that is a function of the input frequency and a division ratio. The effective length of the extendable divider chain may be a total number of divider cells in the extendable divider chain that influence the division ratio. The frequency divider circuit602may be an asynchronous divider circuit that achieves reliable operation with a dynamically updating division ratio.

Each of the at least one first and second divider cells, such as the first divider cells633a-cand second divider cells620aand620b, may be configured to receive a respective programming input signal, such as the programming input signals635a-efor controlling a respective division mode of the at least one first and second divider cells. Gating signals, such as the gating signal651a(i.e., Gn−1) and the gating signal651c(i.e., Gn−2), may be generated from a subset of the programming input signals635a-e, such as the subset pn, pn−1, and pn−2, and employed to control states of modulus input control signals propagating along the chain.

FIG. 7is a circuit diagram750of an example embodiment of an output frequency generator circuit752for generating a divided output frequency signal744, such as the divided output frequency signal644ofFIG. 6, disclosed above. The frequency divider circuit602may further comprise the output frequency generator circuit752. The output frequency generator circuit752may be configured to perform a logical NOR of each output modulus signal generated by the first divider chain604to generate the divided output frequency signal744(i.e., Fout).

For example, the output frequency generator circuit752may include a NOR gate734that may be configured to perform a logical NOR of the modulus signals766a-dthat may each be generated by a first divider chain, such as the modulus signals666a-d(i.e., mod0, mod1, mod2, . . . , modn−3) ofFIG. 6, disclosed above.

By performing a NOR operation of all the modulus signals from the nmin619cells of the first divider chain604, none of which are not affected by the divider chain shortening method, and employing a result from such a NOR operation both as the divided output (i.e., Fout) and as a clock for synchronizing the dynamic change of the division ratio, the divided output frequency signal644that is generated has negligible jitter. Since the modulus signal666aof a starting first divider cell633aof the first divider chain604(i.e., mod0) is used, the divided output frequency signal644(i.e., Fout) is gated directly by the input frequency signal642and, thus, has negligible jitter. Also, a combined pulse width of the divided output frequency signal644(i.e., Fout) is much wider relative to a pulse width of the modulus signal666a(i.e., mod0), alone, as shown with reference toFIG. 8, disclosed below.

FIG. 8is a graph800of an example embodiment of voltage862over time864for modulus signals866a-dgenerated by a first divider chain, such as the modulus signals666a-dofFIG. 6generated by the first divider chain604, and a divided output frequency signal Fout844generated according to the example embodiment ofFIG. 7, disclosed above. As shown in the graph800, a pulse width of the modulus signals866a-dmay become narrower as a modulus number, such as 3, 2, 1, and 0, in the example embodiment, becomes smaller. However, an overlap between any two adjacent modulus signals, such as an overlap between the modulus signal866a(i.e., mod0) and the modulus signal866b(i.e., mod1), or an overlap between the modulus signal866b(i.e., mod1) and the modulus signal866c(i.e., mod2), etc., is present.

Thus, there is no glitch in the divided output frequency signal Fout844that may be generated by combining multiple modulus signals using a logical NOR gate, such as the logical NOR gate734ofFIG. 7, disclosed above. Further, as shown in the graph800, at a falling edge of the modulus signal866a(i.e., mod0), it is safe to update the division numbers p0-pnwithout disrupting a normal propagation of the modulus signals when each of the modulus signals are zero.

FIG. 9is a graph900of an example embodiment of a divided output frequency signal. The graph900shows that a divided output frequency signal944that may be generated based on an example embodiment disclosed herein yields an expected division ratio according to controlling division inputs934and936.

Turning back toFIG. 6, the frequency divider circuit602may be further configured to receive a set of division ratio control signals (not shown), such as the set of division ratio control signals1081ofFIG. 10, disclosed below. The frequency divider circuit602may further comprise a division ratio update circuit (not shown), such as the division ratio update circuit1080ofFIG. 10.

FIG. 10is a circuit diagram1000of an example embodiment of the division ratio update circuit1080. As disclosed inFIG. 6, above, each of the at least one first and second divider cells, that is, each of the at least one first divider cells633a-cand the at least one second divider cells620aand620b, may be configured to receive a respective programming input signal for controlling a respective division mode of the at least one first and second divider cells, such as the programming input signals635a-e. The division ratio update circuit1080may be configured to update each respective programming input signal of the at least one and second divider cells, such as the respective programming input signals635a-e, to a respective division ratio control signal of the set of division ratio control signals1081. The respective programming input signals635a-emay be updated to a respective division ratio control signal of the set of division ratio control signals1081in response to a rising edge of the divided output frequency signal644that may be generated according to the example embodiment ofFIG. 7, disclosed above.

Turning back toFIG. 6, the frequency divider circuit602may further comprise a reset generator circuit configured to generate a respective reset control signal for controlling the respective reset control of each at least one second divider cell. The reset generator circuit may be further configured to update a respective state of the respective reset control signal in response to a falling edge of the divided output frequency signal as disclosed with reference toFIG. 11, below.

FIG. 11is a circuit diagram1100of an example embodiment of a reset generator circuit1190. The reset generator circuit1190may be configured to update reset signals for the dynamic cells, that is, each second divider cell of the at least one second divider cell of the second divider chain608, with a falling edge of Fout1144, that may be generated according to the example embodiment ofFIG. 7, disclosed above.

The respective reset control signal, such as the reset control622aand622bofFIG. 6, disclosed above, may be configured to be a function of at least one respective programming input signal received for controlling the respective division mode of the at least one second divider cell. Each at least one second divider cell, such as the second divider cells620aand620bmay be configured to generate a respective modulus output signal and to set the respective modulus output signal to an active level in an event the respective reset control is asserted. Each of the second divider cells620aand620bmay be resettable 2/3 divider cells, as disclosed with reference toFIG. 12below. The reset generator circuit1190may include a plurality of latches1191each receiving an inverted form of a respective programming input signal and each clocked via the falling edge of Fout1144to generate a respective reset control. It should be understood that receiving an inverted form of a respective programming input signal may include inverting the respective programming input signal via an inverter at a respective input to the latch or via employing the latch's inverted output (i.e., /Q) as the respective reset control.

FIG. 12is a circuit diagram1200of an example embodiment of a resettable 2/3 divider cell1220. The resettable 2/3 divider cell1220may be employed as a second divider cell of the second divider chain208ofFIG. 2or the second divider chain608, ofFIG. 2andFIG. 6, respectively, disclosed above. The resettable 2/3 divider cell1220may be composed of a first resettable latch1228awith an output Q11237that may be coupled to an input D2of a second resettable latch1228b. The 2/3 resettable divider cell1220may be further composed of a set/reset latch1229, a settable latch1230, a first AND gate1231a, a second AND gate1231b, and a third AND gate1231c.

An input frequency signal1245, that may be output from a preceding 2/3 cell, may be employed as an input clock to the first resettable latch1228aand the settable latch1230while the input frequency signal1245in an inverted form may be employed as the input clock to the second resettable latch1228band the set/reset latch1229.

A first inverse output /Q21252from the second resettable latch1228bmay be input to the first AND gate1231aand combined via a logical AND operation with a second inverse output /Q31243from the set/reset latch1229to generate a first input D11254to the first resettable latch1228a. The first inverse output /Q21252may be employed as the output frequency signal to a next 2/3 resettable divider cell (not shown). A modulus signal1253from the next 2/3 resettable divider cell may be combined via a logical AND operation with an output Q21241of the second resettable latch1228bby the second AND gate1231band the result may be input as D4to the settable latch1230.

The output Q41246from the settable latch1230may be employed as a modulus signal output that is input to a preceding 2/3 divider cell (not shown) that may be a resettable or non-resettable 2/3 divider cell. The output Q41246may be combined via an AND operation with a programming input signal p1235by the AND gate1231cand the output D4from the AND gate1231cmay be input to the set/reset latch1229.

According to the example embodiment ofFIG. 12, when the reset control signal1222input to the resettable 2/3 divider cell1220is active, the output Q11237from the first resettable latch1228aand the output Q2from the second resettable latch1228bare both zero, the output Q41246, which is the modulus output signal (i.e., mod_out) from the 2/3 resettable latch1220is one. Further, the set/reset latch1229includes a control C input1238. In an event the reset control signal1222is inactive, the control C input1238is ignored. However, in an event the reset control signal1222is active, configuring the control C input1238to a high level, that is, one, causes the set/reset latch1229to be set, that is, the Q3output1227is set to one and the /Q3output1243is zero. If however, the reset control signal1222is active and the control C input1238is configured to be a low level, that is zero, the Q3output1227is set to zero and the /Q3output1243is one. Thus, in an event the reset control signal1222is active, the Q3output1227is the programming input signal p1235and the /Q3output1243is an inverse of the programming input signal p1235, where a high value of the programming input signal p1235sets the set/reset latch1229and a low value the programming input signal p1235resets the set/reset latch1229.

As disclosed above, the 2/3 resettable latch1220may be composed of two latches of a same type, that is, the first resettable latch1228aand the second resettable latch1228bthat both reset to zero, the settable latch1230that resets to one, and the set/reset latch1229that may be reset to either one or zero depending upon the programming input signal p1235input to the control C input1238. As such, the resettable 2/3 divider cell1220may operate in a same manner as a non-resettable 2/3 cell, such as disclosed with reference toFIG. 4, above, when the reset control signal1222is in an inactive state. However, when the reset control signal1222is active, the resettable 2/3 divider cell1220may generate a modulus output signal, that is, the output Q41246, that is active, such that the modulus output signal would prevent further divider cells in the chain from influencing the length of the chain and, thus, the division ratio. Further, the resettable 2/3/ divider1220advantageously preserves the internal states of all latches, such as the first resettable latch1228a, the second resettable latch1228b, the settable latch1230, and the set/reset latch1229, to keep division ratio correct when the divider chain length is increasing.

Embodiments disclosed herein enable a frequency divider circuit with a dynamically updating division ratio. To enable such a dynamic update, an example performs a nor operation of all the modulus signals from the first divider chain, that is, each of the left “nmin” first divider cells ofFIG. 6, which are not affected by the divider chain shortening method, and employ a result of such a NOR operation (i.e., Fout) both as the divided output signal and as a clock for synchronizing the dynamic change to the length. Since mod0 is employed in the NOR operation, Foutmay be gated directly by the input clock (i.e., Fin) and, thus, has the smaller jitter. Also, a combined pulse width of Foutis much wider than mod0 alone.

To enable the dynamic update, an example embodiment disclosed above updates the division ratio with the rising edge of Fout. To enable the dynamic update, an example embodiment updates the dynamic length shortening with a rising edge of Fout, introducing an extra delay between the division number update and the divider length change, ensuring proper division. To enable the dynamic update, an example embodiment disclosed above updates reset signals for the dynamic cells, that is, the second divider cells that may be 2/3 resettable divider cells, with the falling edge of Foutto ensure proper reset timing.

Further to enable the dynamic update, an example embodiment of second divider cell may be a resettable 2/3 divider cell with four latches that operate such that when the reset control is active, Q1and Q2are 0, Q4is 1, and Q3is equal to the p input programming signal, as disclosed above.

FIG. 13is a graph1300showing a correlation between an intended division ratio1372and an actual division ratio1374achieved via a prior art frequency divider circuit in real time.

FIG. 14is a graph1400showing a correlation between an intended division ratio1472and an actual division ratio1474achieved via an example embodiment of a frequency divider circuit in real time. The graphs1300and1400show that the prior art frequency divider circuit generates a division ratio with errors1376that include substantive errors, whereas the frequency divider circuit according to the example embodiment yields correct division with no errors1476.

FIG. 15is flow diagram1500of an example embodiment of a method for performing frequency division by a frequency divider circuit. The method begins (1502) and employs a first divider chain including at least one first divider cell (1504). The method may couple the first divider chain to a second divider chain to form an extendable divider chain (1506). The second divider chain may include at least one second divider cell with a respective reset control. The method may alter an effective length of the extendable divider chain, dynamically, via the respective reset control, enabling the frequency divider circuit to alter, dynamically, the frequency division performed (1508), and the method thereafter ends in the example embodiment (1510).