Single crystal source-drain merged by polycrystalline material

A method of forming a semiconductor structure includes forming a first fin and a second fin on a substrate. A gate structure is formed over a first portion of the first fin and the second fin without covering a second portion of the first fin and the second fin. Single-crystal epitaxial layers are deposited surrounding the second portion of the first fin and the second fin such that the single-crystal epitaxial layer on the first fin does not contact the single-crystal epitaxial layer on the second fin. A polycrystalline layer is then deposited surrounding the single-crystal epitaxial layers, so that the polycrystalline layer contacts the single-crystal epitaxial layer on the first fin and the single-crystal epitaxial layer on the second fin. The single-crystal epitaxial layers and the polycrystalline layer form a merged source-drain region.

BACKGROUND

The present invention generally relates to semiconductor devices and more particularly to fin field effect transistor devices (FinFET) having single-crystal source-drain regions merged by a polycrystalline material.

Complementary Metal-oxide-semiconductor (CMOS) technology is commonly used for fabricating field effect transistors (FET) as part of advanced integrated circuits (IC), such as CPUs, memory, storage devices, and the like. Most common among these may be metal-oxide-semiconductor field effect transistors (MOSFET), in which a gate structure may be energized to create an electric field in an underlying channel region of a substrate, by which charge carriers are allowed to travel through the channel region between a source region and a drain region of the substrate. As ICs continue to scale downward in size, fin field effect transistors (FinFETs), sometimes referred to as tri-gate structures, may be potential candidates for 32 nm node technology and beyond primarily because FinFETs may offer better performance than planar FETs at the same power budget. FinFETs are three dimensional (3D), fully depleted MOSFET devices having a fin structure formed from the substrate material. The gate structure may wrap a portion of the fin acting as the channel region. The portion of the fin not covered by the gate structure may define the source-drain region of the semiconductor device.

SUMMARY

The ability to manufacture FinFET devices including a polycrystalline material merging single-crystal source-drain regions may facilitate advancing the capabilities of current CMOS technology.

According to one embodiment of the present disclosure, a method of forming a semiconductor structure may include forming a first fin and a second fin on a substrate. A gate structure may be formed over a first portion of the first fin and the second fin without covering a second portion of the first fin and the second fin. Single-crystal epitaxial layers may be deposited surrounding the second portion of the first fin and the second fin such that the single-crystal epitaxial layer on the first fin does not contact the single-crystal epitaxial layer on the second fin. A polycrystalline layer may be deposited surrounding the single-crystal epitaxial layers, so that the polycrystalline layer contacts the single-crystal epitaxial layer on the first fin and the single-crystal epitaxial layer on the second fin thereby forming a merged source-drain region.

According to another embodiment, a semiconductor structure may include a first fin and a second fin on a substrate, a gate structure over a first portion of the first fin and the second fin, a second portion of the first fin and the second fin not covered by the gate structure, single-crystal epitaxial layers surrounding the second portion of the first fin and the second fin, the single-crystal epitaxial layer on the first fin does not contact the single-crystal epitaxial layer on the second fin, a polycrystalline layer surrounding the single-crystal epitaxial layers, so that the polycrystalline layer contacts the single-crystal epitaxial layer on the first fin and the single-crystal epitaxial layer on the second fin to form a merged source-drain region.

DETAILED DESCRIPTION

FinFET devices may present an alternative to planar FET devices to allow increased scaling of semiconductor devices. However, FinFETs size and topography may pose numerous challenges to current CMOS manufacturing technology. Among those challenges may be the reduction of source-drain resistance without sacrificing device performance and process complexity. Source-drain resistance may be reduced by forming an epitaxial layer off the fin surface until the fin structures are merged. However, such a technique may present several limitations to the formation of merged source-drain regions including extended deposition time and selectivity loss during the epitaxial deposition process which may ultimately lead to reduced device performance and reliability. By forming a polycrystalline material surrounding single-crystal unmerged source-drain regions, embodiments of the present disclosure may, among other potential benefits, reduce deposition time, prevent selectivity loss during the deposition process and limit dopant diffusion to certain regions of the substrate.

Referring now toFIG. 1, a semiconductor structure100may be formed or provided. At this step of the manufacturing process, a plurality of fin structures14(hereinafter “fins”) may be formed from a substrate102of the semiconductor structure100. The substrate102may be, for example, a semiconductor-on-insulator (SOI) substrate, where a buried insulator layer (not shown) separates a base substrate (not shown) from a top semiconductor layer (not shown). The components of the semiconductor structure100, including the fins14, may then be formed in or adjacent to the top semiconductor layer. In other embodiments, the substrate102may be a bulk substrate which may be made from any of several known semiconductor materials such as, for example, silicon, germanium, silicon-germanium alloy, carbon-doped silicon, carbon-doped silicon-germanium alloy, and compound (e.g. III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide.

The fins14may be formed by any method known in the art. In an exemplary embodiment, the fins14may be formed by a sidewall image transfer (SIT) technique. It should be noted that, while the embodiment depicted inFIG. 1includes four fins14, any number of fins may be formed from the substrate102. In embodiments in which the fins14may be formed from a bulk semiconductor substrate, the fins14may be isolated from one another by regions of a dielectric material (not shown). In one exemplary embodiment, the fins14may have a height h ranging from approximately 5 nm to approximately 200 nm, a width w ranging from approximately 5 nm to approximately 50 nm and may be separated by a pitch p ranging from approximately 20 nm to 100 nm.

Referring now toFIG. 2, a gate structure22may be formed over a portion of the fins14covering a channel region (not shown) of the semiconductor structure100. It should be noted that the FinFET device may be fabricated using either a replacement metal gate (RMG) or gate last process flow, or a gate first process flow. For illustration purposes only, without intent of limitation, the embodiment described below uses a gate first process flow.

At this point of the manufacturing process, the gate structure22may include a gate dielectric24, a gate electrode26and a gate cap28. The gate dielectric24may include an insulating material including, but not limited to: oxide, nitride, oxynitride or silicate including metal silicates and nitrided metal silicates. In one embodiment, the gate dielectric24may include an oxide such as, for example, SiO2, HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, and mixtures thereof. The gate dielectric24may be formed by any suitable deposition technique known in the art, such as, for example, chemical vapor deposition (CVD), plasma-assisted CVD, atomic layer deposition (ALD), evaporation, reactive sputtering, chemical solution deposition or other like deposition processes. The physical thickness of the gate dielectric24may vary, but typically may have a thickness ranging from about 0.5 nm to about 10 nm. More preferably the gate dielectric24may have a thickness ranging from about 0.5 nm to about 3 nm.

The gate electrode26may be formed on top of the gate dielectric24. The gate electrode26may include, for example, Zr, W, Ta, Hf, Ti, Al, Ru, Pa, metal oxide, metal carbide, metal nitride, transition metal aluminides (e.g. Ti3Al, ZrAl), TaC, TiC, TaMgC), and any combination of those materials. In one embodiment, the gate electrode26may include tungsten (W). The gate electrode26may be deposited by any suitable technique known in the art, for example by ALD, CVD, physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), or liquid source misted chemical deposition (LSMCD). Furthermore, the gate cap28may be formed on top of the gate electrode26using any suitable deposition technique known in the art. The gate cap28may include but is not limited to, for example, silicon oxide, silicon nitride, silicon oxynitride, boron nitride, or any suitable combination of those materials.

Referring now toFIG. 3, gate spacers32may be formed on opposite sidewalls of the gate structure22. The gate spacers32may be made from an insulator material such as an oxide, nitride, oxynitride, silicon carbon oxynitride, silicon boron oxynitride, low-k dielectric, or any combination thereof. In one embodiment, the gate spacers32may be made from a nitride and may be formed by conventional deposition and etching techniques. Further, in various embodiments, the gate spacers32may include one or more layers. While the gate spacers32are herein described in the plural, the gate spacers32may consist of a single spacer surrounding the gate structure22.

Referring now toFIG. 4, epitaxial layers40may be formed on exposed portions of the fins14. The exposed portions of the fins14may consist of regions of the fins14not covered by the gate structure22(FIG. 3). The epitaxial layers40may include a single-crystal or monocrystalline material epitaxially grown on the fins14. Growth of the epitaxial layers40may include forming the epitaxial layers40on the exposed portions of the fins14such that the epitaxial layers40surrounding one of the fins14does not contact the epitaxial layers40surrounding an adjacent fin14thereby forming single-crystal unmerged source-drain regions42(hereinafter “unmerged source-drain regions”) as part of the semiconductor structure100. In the depicted embodiment, the diamond shape observed in the unmerged source-drain regions42may be a consequence of the different growth rates during the epitaxial deposition process inherent to each crystallographic orientation plane of the single-crystal material forming the epitaxial layers40. In other embodiments, the unmerged source-drain regions42may have a shape other than the diamond shape depicted inFIG. 4.

The terms “epitaxial growth and/or deposition” and “epitaxially formed and/or grown” mean the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown may have the same crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the deposition surface of the substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxial semiconductor material may have the same crystalline characteristics as the deposition surface on which it may be formed. For example, an epitaxial semiconductor material deposited on a {100} crystal surface may take on a {100} orientation. In some embodiments, epitaxial growth and/or deposition processes may be selective to forming on semiconductor surfaces, and may not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.

The epitaxial layers40may include any suitable single-crystal semiconductor material doped in-situ according to the characteristic of the semiconductor structure100.

For example, in one embodiment where the semiconductor structure100is an n-type field effect transistor (n-FET) device, the epitaxial layers40may include a single-crystal carbon-doped silicon (Si:C) material, where the atomic concentration of carbon (C) may range from about 0.2-3.0%. The epitaxial layers40may be doped by any known n-type dopant use in the fabrication of an n-FET device, such as, for instance, phosphorus or arsenic. In one embodiment, the dopant concentration in the epitaxial layers40may range from approximately 4×1020cm−3to approximately 9×1020cm−3

For example, in another embodiment where the semiconductor structure100is a p-type field effect transistor (p-FET) device, the epitaxial layers40may include a single-crystal silicon-germanium (SiGe) material, where the atomic concentration of germanium (Ge) may range from approximately 10% to approximately 80%. In another embodiment, the concentration of germanium (Ge) may range from approximately 25% to approximately 50%. The epitaxial layers40may be doped by any known p-type dopant use in the fabrication of a p-FET device, such as, for instance, boron. In one embodiment, the dopant concentration in the epitaxial layers40may range from approximately 4×1020cm−3to approximately 9×1020cm−3.

Examples of various epitaxial growth process apparatuses that may be suitable for use in forming the epitaxial layers40may include, for example, rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD) and molecular beam epitaxy (MBE).

Referring now toFIG. 5, a polycrystalline layer50may be formed on the epitaxial layers40. Formation of the polycrystalline layer50may include depositing a multi-grain polycrystalline material surrounding the epitaxial layers40until the polycrystalline layer50may combine the unmerged source-drain regions42(FIG. 4) forming a merged structure52(hereinafter “merged source-drain region”) as part of the semiconductor structure100. The deposition of the polycrystalline layer50may occur until the polycrystalline layer50surrounding one unmerged source-drain region42amay contact the polycrystalline layer50surrounding an adjacent unmerged source-drain region42b. The polycrystalline material forming the polycrystalline layer50may exhibit various crystal planes that may allow for growth in different directions during the deposition process thereby forming a merged source-drain region52with a substantially even surface. The ability to form a merged source-drain region52with a substantially even surface may provide a smooth landing region to a subsequently formed contact metal80(FIG. 8).

Owing to the different crystallographic directions in which the deposition process of the polycrystalline layer50may take place, formation of the merged source-drain region52may occur in a substantially faster rate than growing a single-crystal epitaxial layer off the fins14until the epitaxial layer has merged the fins14.

The polycrystalline layer50may include any suitable polycrystalline semiconductor material doped in-situ according to the characteristic of the semiconductor structure100.

For example, in one embodiment where the semiconductor structure100is an n-FET device, the polycrystalline layer50may include a polycrystalline silicon material. The polycrystalline layer50may be doped by any known n-type dopant use in the fabrication of an n-FET device, such as, for instance, phosphorus or arsenic. In one embodiment, the dopant concentration may range from approximately 5×1020cm−3to approximately 2×1021cm−3.

For example, in another embodiment where the semiconductor structure100is a p-FET device, the polycrystalline layer50may include a polycrystalline silicon-germanium (SiGe) material, where the atomic concentration of germanium (Ge) may range from about 10% to about 80%. In another embodiment, the concentration of germanium (Ge) may range from about 25% to about 50%. The polycrystalline layer50may be doped by any known p-type dopant use in the fabrication of a p-FET device, such as, for example, boron. In one embodiment, the dopant concentration may range from approximately 5×1020cm−3to approximately 2×1021cm−3. In other embodiments the polycrystalline layer50may also include a boron doped polycrystalline silicon material.

In an exemplary embodiment, the polycrystalline layer50may have a higher dopant concentration than the epitaxial layers40which may provide a lower dopant concentration near the fins14and a higher dopant concentration in close proximity to a subsequently formed contact metal (FIG. 8). The lower doping level in the epitaxial layers40may decrease dopant diffusion to an extension region (not shown) of the channel region (not shown) enfolded by the gate structure22, more specifically, dopant diffusion may be reduced in an area of the substrate located under the gate spacers32thereby preventing a potential electrical short in the semiconductor structure100.

The polycrystalline layer50may be formed by any suitable deposition technique known in the art, including atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), or liquid source misted chemical deposition (LSMCD).

Referring now toFIG. 6, an interlayer dielectric (ILD) layer60may be formed above the substrate102. The ILD layer60may cover the gate structure22and the merged source-drain region52. Further, the ILD layer60may fill gaps between other existing devices within the semiconductor structure100. While the ILD is shown to not fully cover the merged source-drain region52or the substrate102inFIG. 6, the end of the merged source-drain region52may be exposed only for illustrative clarity. The ILD layer60may include any suitable dielectric material, for example, silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, silicon based low-k dielectrics, flowable oxides, porous dielectrics, or organic dielectrics including porous organic dielectrics and may be formed by any suitable deposition method known in the art, for example, by chemical vapor deposition (CVD) of a dielectric material.

Referring now toFIG. 7, a contact hole72may be formed in the ILD layer60to expose the merged source-drain region52. The contact hole72may be formed by any photolithographic patterning process including, for example an anisotropic etching process such as reactive ion etching (RIE) or plasma etching.

Referring now toFIG. 8, a contact metal80may be deposited within the contact hole72(FIG. 7). The contact metal80may include any suitable metal or conductive metal compound. The contact metal80may be formed by several metal layers (not shown) of different materials. In one exemplary embodiment the contact metal80may include multiple layers including a titanium (Ti) liner, a titanium nitride (TiN) liner and a tungsten (W) layer. The contact metal80may be formed by any deposition method, including but not limited to ALD, CVD and plating. The polycrystalline layer50forming the merged source-drain region52may provide an even landing surface with a high dopant concentration to the contact metal80.

Therefore, forming a polycrystalline layer50including a multi-grain polycrystalline material that combines single-crystal unmerged epitaxial layers40may decrease deposition times during formation of the merged source-drain region52, which may prevent non-selective nodule formation. Further, the epitaxial layers40and the polycrystalline layer50may allow tunable dopant concentration, which may help constrain dopant diffusion under the gate spacers32(FIG. 5) to avoid possible electric shorts in the device thus enhancing device performance and increasing product yield and reliability, and the polycrystalline material forming the polycrystalline layer50may allow multi-directional growth which may result in a substantially even surface for contact landing.