Field-effect transistor and method of making the same

A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.

TECHNOLOGY FIELD

The disclosure relates to a semiconductor device and, more particularly, to a semiconductor field-effect transistor and a method of making the same.

BACKGROUND

With the development of technologies in the semiconductor integrated circuit industry, more and more semiconductor devices can be integrated in one semiconductor integrated circuit (IC), and the size of individual semiconductor devices becomes smaller and smaller. A field-effect transistor (FET) is a typical semiconductor device that constitutes a basic unit of a semiconductor IC. An FET includes a gate structure formed over a semiconductor substrate, as well as a source and a drain formed in the semiconductor substrate and close to the gate structure. Conventionally, the source and drain are formed by doping the semiconductor substrate. With the increasing of the integration level of IC's and the scaling down of the FETs in the IC's, different processes have been developed for forming the source and drain.

One of these processes involves using an epitaxial technique to form the source and drain. According to this process, the semiconductor substrate is etched to form recesses, also referred to as “S/D recesses,” and then a semiconductor material is deposited in the recesses to form the source and drain. In some FETs, the semiconductor material is also deposited above the S/D recesses, and the resulting sources or drains are also referred to as raised sources or raised drains having an elevated portion above the surface of the substrate. The recesses can be hexagonal-shaped recesses, also referred to as sigma-shaped recesses. The process of forming the hexagonal-shaped recesses can include a dry etching to form U-shaped recesses and then a wet etching to form the hexagonal-shaped recesses.

The semiconductor material deposited in the recesses can be different for different types of FETs. For example, for a P-channel FET formed in a silicon (Si) substrate, silicon-germanium (SiGe) can be deposited in the recesses to form the source and drain. Since SiGe has a larger lattice constant than Si, an SiGe source/drain introduces a compressive stress in the channel of the FET, which increases the hole mobility in the channel. Further, for an N-channel FET formed in an Si substrate, phosphorous-doped Si (Si:P) can be deposited in the recesses to form the source and drain.

FIG. 1schematically shows a conventional semiconductor device100including a substrate102, two gate structures104formed over the substrate102, a hexagonal-shaped S/D recess106formed in the substrate102and between the gate structures104according to conventional technology, and a raised source/drain108formed in and over the S/D recess106and between the gate structures104. Each of the gate structures104includes a gate dielectric layer104-2formed over the substrate102, a gate electrode104-4formed over the gate dielectric layer104-2, a cap layer104-6formed over the gate electrode104-4, and a spacer104-8formed on the side surface of the gate structure, i.e., the side surfaces of the gate dielectric layer104-2, the gate electrode104-4, and the cap layer104-6.

The source/drain108includes a buried portion108-2formed in the S/D recess106and an elevated portion108-4formed over the S/D recess106, i.e., above the top surface of the substrate102. In the semiconductor device100, the distance between the elevated portion108-4and the gate electrode104-4, also referred to herein as an “S2G distance,” is determined by the thickness of the spacer104-8.

The inventors have observed that the conventional semiconductor device100has structural and operational deficiencies.

SUMMARY

In accordance with the disclosure, there is provided a semiconductor device including a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The epitaxial structure serves as one of a source or drain region corresponding to the gate structure. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.

Also in accordance with the disclosure, there is provided a method for forming a semiconductor device. The method includes forming a gate structure over a semiconductor substrate, forming a capping layer over the semiconductor substrate and the gate structure, implanting arsenic into the semiconductor substrate through the capping layer and using the gate structure as a mask to form an implanted region in the semiconductor substrate, removing the capping layer, forming an etching spacer on a side surface of the gate structure, and etching the implanted region using the gate structure and the etching spacer as a mask to form a recess in the semiconductor substrate. The recess includes an undercut region directly beneath the etching spacer.

Also in accordance with the disclosure, there is provided an epitaxial structure formed partially within a semiconductor substrate. The epitaxial structure includes a vertically extending portion extending vertically above a top surface of the semiconductor substrate and a laterally extending portion extending laterally at an area below the top surface of the semiconductor substrate and beyond an area where the vertically extending portion extends vertically. The vertically extending portion joins the laterally extending portion at a rounded corner.

Features and advantages consistent with the disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the disclosure. Such features and advantages will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.

DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments consistent with the disclosure will be described with reference to the drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

Embodiments consistent with the disclosure include a semiconductor field-effect transistor having an undercut source/drain and a method of making the same.

The inventors have observed that the conventional semiconductor device100shown inFIG. 1has structural and operational deficiencies, and have discovered new ways to construct an FET without such deficiencies.

As shown inFIG. 1, the hexagonal-shaped S/D recess106includes recess tips106-2, which overlap with tips of the buried portion108-2of the source/drain108. The horizontal distance from the recess tip106-2to a vertical plane on which the side surface of the gate electrode104-4is disposed is referred to herein as a “T2G distance.” In this disclosure, the terms “horizontal/horizontally” and “vertical/vertically,” when used to describe directional relations associated with a device, are relative to the orientation of the device as shown in one of the accompanying drawings. These terms are used to facilitate description and not a required orientation of the illustrated devices. The T2G distance can be positive or negative. A positive T2G distance means the recess tip106-2has not reached the vertical plane on which the side surface of the gate electrode104-4is disposed, i.e., the recess tip106-2is not beneath the gate electrode104-4, as shown inFIG. 1. On the other hand, a negative T2G distance means the recess tip106-2is beyond the vertical plane on which the side surface of the gate electrode104-4is disposed, i.e., the recess tip106-2is beneath the gate electrode104-4. The vertical distance from the recess tip106-2to the surface of the substrate102is referred to herein as a “sigma depth” or “SMD.” Further, the vertical distance from the bottom of the S/D recess106to the surface of the substrate102is referred to herein as a “recess depth” or “RCD.”

In the semiconductor device100shown inFIG. 1, the T2G distance, the sigma depth, and the recess depth can be controlled by controlling etching conditions for forming the S/D recess106. Usually, with a longer etching time, the T2G distance decreases and the sigma depth increases. The T2G distance also depends on the S2G distance and increases when the S2G distance increases. The S2G distance, the T2G distance, and the sigma depth need to be controlled to optimize the performance of the semiconductor device100.

The elevated portion108-4of the source/drain108, the gate electrode104-4, and the spacer104-8sandwiched between the elevated portion108-4of the source/drain108and the gate electrode104-4form a parasitic capacitor. The capacitance, Cov, of the parasitic capacitor can be affected by the S2G distance. Generally, a smaller S2G distance results in a larger Cov, which in turn increases the RC delay of the semiconductor device100and thus reduces the operating speed of the semiconductor device100. Therefore, to reduce the negative impact on the operating speed of the semiconductor device100, the S2G distance should be made larger. However, as discussed above, a larger S2G distance can cause a larger T2G distance, i.e., the recess tip106-2is farther away from the channel below the gate electrode104-4. As a result, in the case that the substrate102is Si and the source/drain108is SiGe, the stress introduced by the source/drain108in the channel becomes smaller and thus the hole mobility in the channel becomes smaller. A smaller hole mobility will result in a slower operating speed of the semiconductor device100. Although increasing the etching time when forming the recess106can reduce the T2G distance, the sigma depth is increased and the recess tip106-2moves vertically away from the channel. That is, increasing the etching time generally does not help to increase the hole mobility. Moreover, both the sigma depth and the recess depth should be kept within a certain range, which prevents further increasing the etching time.

FIGS. 2A and 2Bare transmission electron microscopy (TEM) images respectively showing an SiGe source/drain of a P-channel FET and an Si:P source/drain of an N-channel FET, each of which has a sigma-shaped recess similar to the S/D recess106of the semiconductor device100. As shown inFIGS. 2A and 2B, with such a recess, stacking faults in the SiGe source/drain of the P-channel FET and cat ears in the Si:P source/drain of the N-channel FET can occur.

FIG. 3Aschematically shows an exemplary semiconductor device300A consistent with the present disclosure. The semiconductor device300A includes a substrate302, two gate structures304formed over the substrate302, a source/drain (S/D) recess306formed in the substrate302and between the gate structures304, a raised source/drain308formed in and over the S/D recess306and between the gate structures304, an interlayer dielectric layer310formed over the substrate302, the gate structures304, and the source/drain308, and an S/D contact312formed through the interlayer dielectric layer310and in contact with the source/drain308. Portions of the substrate302below the gate structures304serve as channel regions314. Since a semiconductor device consistent with the present disclosure has a symmetric structure, hereinafter, the description will be made with respect to components at one side of the semiconductor device, unless both sides are mentioned.

The substrate302includes a semiconductor substrate, such as an N-type silicon (Si) substrate. The two gate structures304share one source/drain308and each corresponds to one field-effect transistor (FET). In this example, each FET is a P-channel FET. The gate structure304includes a gate dielectric layer304-2formed over the substrate302, a gate electrode304-4formed over the gate dielectric layer304-2, and a spacer304-6formed on the side surfaces of the gate dielectric layer304-2and the gate electrode304-4. The gate dielectric layer304-2can be formed of, e.g., silicon oxide (SiO2) or a high-k material such as hafnium silicate (HfO4Si). The gate electrode304-4can be formed of, e.g., polycrystalline Si. The spacer304-6can be a single spacer made of, e.g., silicon nitride (Si3N4) or silicon oxynitride (SiOxNy), or a composite spacer including a combination of, e.g., a Si3N4layer and a SiOxNylayer. In some embodiments, the gate structure304further includes a cap layer (not shown) formed over the gate electrode304-4. The cap layer can be formed of, e.g., Si3N4. In such embodiments, the spacer304-6can be formed on the side surfaces of the gate dielectric layer304-2, the gate electrode304-4, and the cap layer.

The source/drain308is formed near the gate structures304and can function as either the source or the drain of each FET of the semiconductor device300A. The source/drain308includes an epitaxial structure containing a material that is capable of exerting a stress on the channel region314, such as silicon-germanium (SiGe). The SiGe can be doped with a P-type dopant, such as boron (B). In some embodiments, the source/drain308can include a composite epitaxial structure. For example,FIG. 3Bschematically shows another exemplary semiconductor device300B consistent with the present disclosure. In the semiconductor device300B, the source/drain308includes a buffer SiGe layer308A, a bulk SiGe layer308B formed over the buffer SiGe layer308A, and an Si cap layer308C formed over the bulk SiGe layer308B. At least a portion of the Si cap layer308C can be silicided to reduce a contact resistance between the source/drain308and the contact312. In the example shown inFIG. 3B, an entire top surface of the Si cap layer308C is silicided to form a silicided layer308C-1. In some embodiments, only the portion of the top surface of the Si cap layer308C at which the contact312lands is silicided.

In some embodiments, as shown inFIG. 3B, the interlayer dielectric layer310includes a contact etch stop layer310-1, which is formed at the bottom of the interlayer dielectric layer310. The contact etch stop layer310-1helps to improve etching uniformity when the interlayer dielectric layer310is etched to form an opening for the contact312.

Referring again toFIG. 3A, the source/drain308includes a buried portion308-2formed in the S/D recess306and an elevated portion308-4formed over the S/D recess306. That is, the buried portion308-2is formed below the top surface of the substrate302while the elevated portion308-4extends vertically (as viewed inFIG. 3A) above the top surface of the substrate302. As shown inFIG. 3A, the buried portion308-2extends laterally, i.e., horizontally (as viewed inFIG. 3A), toward the channel region314and beyond the elevated portion308-4, i.e., the lateral end, i.e., the tip in this example, as labeled inFIG. 3A, of the buried portion308-2is laterally closer to the gate structure304than the lateral end, i.e., the side surface, of the elevated portion308-4.

The interlayer dielectric layer310can be made of, e.g., SiO2. As shown inFIG. 3A, a portion of the interlayer dielectric layer310is formed between the side surface of the elevated portion308-4and the side surface of the spacer304-6, i.e., the side surface of the gate structure304. Further, a top surface of the part of the buried portion308-2that extends laterally beyond the elevated portion308-4directly contacts the interlayer dielectric layer310. In the exemplary semiconductor device300A shown inFIG. 3A, the top surface of the part of the buried portion308-2that extends laterally beyond the elevated portion308-4does not directly contact the spacer304-6.FIG. 3Cschematically shows another exemplary semiconductor device300C consistent with the present disclosure. The semiconductor device300C is similar to the semiconductor device300A, except that in the semiconductor device300C, the top surface of the part of the buried portion308-2that extends laterally beyond the elevated portion308-4also directly contacts the spacer304-6. Further,FIG. 3Dshows another exemplary semiconductor device300D consistent with the present disclosure. The semiconductor device300D is also similar to the semiconductor device300A, except that in the semiconductor device300D, the part of the buried portion308-2that extends laterally beyond the elevated portion308-4does not extend as far as the same part in the semiconductor device300A. That is, in the semiconductor device300D, a portion316of the substrate302is exposed between the spacer304-6and the buried portion308-2, and is in direct contact with the interlayer dielectric layer310.

According to the present disclosure, the position of the lateral end, i.e., the tip in the above-described examples, as labeled inFIGS. 3A-3D, of the buried portion308-2and the position of the side surface of the elevated portion308-4can be individually controlled during the process for making the semiconductor devices300A,300B,300C, and300D. That is, the lateral end of the buried portion308-2can be made closer to the gate structure304without reducing the horizontal distance between the side surface of the elevated portion308-4and the side surface of the gate electrode304-4. For example, in an FET with a 40-nm linewidth according to the present disclosure, the horizontal distance between the lateral end of the buried portion308-2and the vertical plane on which the side surface of the gate electrode304-4is disposed, also referred to herein as the T2G distance, can be controlled to be smaller than, e.g., about 35 Å, while the horizontal distance between the side surface of the elevated portion308-4and the vertical plane on which the side surface of the gate electrode304-4is disposed, also referred to herein as the S2G distance, can be controller to be larger than, e.g., about 70 Å. Moreover, the vertical distance from the tip of the S/D recess306, i.e., the tip of the buried portion308-2to the surface of the substrate302, also referred to herein as the sigma depth can be controlled to be around 70 Å, and the vertical distance from the bottom of the S/D recess306, i.e., the bottom of the buried portion308-2to the surface of the substrate302, also referred to herein as the recess depth, can be controlled to be around 450 Å.

In the examples shown inFIGS. 3A-3D, the lateral end of the buried portion308-2forms a tip. Further, the corner formed by the buried portion308-2and the elevated portion308-4is relatively sharp. However, semiconductor devices consistent with the present disclosure are not limited by these geometric characteristics. For example,FIG. 4schematically shows another exemplary semiconductor device400consistent with the present disclosure. The semiconductor device400is similar to the semiconductor device300C, except that in the semiconductor device400, the lateral end of the buried portion308-2includes a side surface that is nearly vertical. The lower end of the side surface of the buried portion308-2can be considered to be a tip. In some embodiments, the lateral end of the buried portion308-2can also include a rounded side surface (not shown inFIG. 4). Further, in the semiconductor device400, the buried portion308-2and the elevated portion308-4meet to form a rounded corner rather than a sharp corner.

In the example shown inFIG. 4, the nearly-vertical side surface of the buried portion308-2is formed below the spacer304-6. However, similar to the examples shown inFIGS. 3A and 3D, the side surface of the buried portion308-2can either be approximately below an edge of the spacer304-6that is adjacent to the elevated portion308-4or below a position between the spacer304-6and the elevated portion308-4.

FIGS. 5A-5Gshow an exemplary process for manufacturing a semiconductor device consistent with the present disclosure, where the semiconductor device can be, for example, the semiconductor device300A shown inFIG. 3Aand includes P-channel FETs. As shown inFIG. 5A, the gate structures304are formed over the substrate302, with a portion of the substrate302exposed and not covered by the gate structures304. A capping layer502is deposited over the gate structures304and the exposed portion of the substrate302. The capping layer502can be a thin Si3N4layer and can also be referred to as a seal nitride layer.

As shown inFIG. 5B, arsenic (As) ions are implanted into the exposed portion of the substrate302through the capping layer502, to form an As-implanted region504in the substrate302. The profile of the As-implanted region504can affect the profile of the later-formed S/D recess304and thus the profile of the buried portion308-2of the source/drain308. For example, the position of the lateral end of the As-implanted region504can affect the position of the lateral end of the S/D recess306, and thus can affect the T2G distance. The closer the lateral end of the As-implanted region504to the gate structure304is, the closer the lateral end of the S/D recess306to the gate structure304is, and thus the smaller the T2G distance is. Further, the position of the bottom of the As-implanted region504can affect the position of the bottom of the S/D recess306, and thus can affect the recess depth. The lower the bottom of the As-implanted region504is, the lower the bottom of the S/D recess306is, and thus the larger the recess depth is.

Generally, the profile of the As-implanted region504can be controlled by controlling the thickness of the capping layer502and the ion implantation conditions. A thicker capping layer502would result in a shallower As-implanted region504. Further, a higher implantation energy would result in a deeper As-implanted region504. A higher implantation dosage would result in a higher As concentration in the As-implanted region504, which would in turn cause the S/D recess306to be deeper and wider. For example, the thickness of the capping layer502can be set to about 30 Å, the implantation energy can be set to about 3.5K eV, and the implantation dosage can be set to about 5×1015cm−2. Under these conditions, the resulting T2G distance, sigma depth, and recess depth are about 30 Å, about 70 Å, and about 470 Å, respectively.

The ion implantation can be a vertical implantation, in which the As ions are implanted into the substrate302vertically, i.e., at an implantation angle of 0 degree. In some embodiments, the ion implantation can be a tilted implantation, in which the As ions are implanted at a non-zero implantation angle. When other conditions are the same, the tilted implantation can result in a wider and shallower As-implanted region504, and thus a smaller T2G distance and recess depth.

Next, as shown inFIG. 5C, after the As-implanted region504is formed, the capping layer502is removed and a disposable layer506is formed over the gate structures304and the exposed portion of the substrate302. In some embodiments, the capping layer502can be removed by a wet etching process, during which, native oxide formed over the exposed portion of the substrate302can also be etched away. The disposable layer506can, for example, include a nitride layer. The disposable layer506is thicker than the capping layer502, and can be, for example, 160˜200 Å.

Then, as shown inFIG. 5D, the disposable layer506is etched back to form disposable spacers508, also referred to herein as “etching spacers,” on the side surfaces of the gate structures304. The etching back process removes a portion of the disposable layer506that is formed over the As-implanted region504, exposing a portion of the As-implanted region504for further process.

As shown inFIG. 5E, the As-implanted region504is etched using the gate structures304and the disposable spacers508as a mask to form the S/D recess306. In some embodiments, the As-implanted region504can be first etched using a dry etching process and then further etched using a wet etching process. According to the present disclosure, because of the As-implanted region504, the etching also proceeds laterally, i.e., horizontally, beneath the surface of the substrate302. As a result of the lateral etching, the S/D recess306includes undercut regions510at least beneath a portion of the disposable spacers508. As shown inFIG. 5E, the undercut regions510are directly beneath the disposable spacers508, i.e., no substrate material remains between the undercut regions510and the disposable spacers508. In some embodiments, the undercut regions510further extend beneath at least a portion of the gate structures304, such as beneath at least a portion of the spacers304-6of the gate structures304. The extension of the undercut regions510beneath at least a portion of the gate structures304can be seen in the final device shown inFIG. 3C. In some embodiments, the undercut regions510do not extend beneath the entire bottoms of the disposable spacers508, but only beneath portions of the disposable spacers508. The extension of the undercut regions510only beneath portions of the disposable spacers508can also be seen in the final device shown inFIG. 3D. In such embodiments, portions of the substrate302between the spacers304-6and the undercut regions510remain in direct contact with the disposable spacers508. The extension of the undercut regions510as used herein refers to the extension of the upper ends of the undercut regions510, i.e., the locations where the undercut regions510intersect the substrate surface.

In some embodiments, one or more cleaning processes can follow the etching processes to, for example, remove residues of the etching substances and/or undesired substances formed during the etching processes.

As shown inFIG. 5F, an epitaxial structure is formed in and over the S/D recess306by epitaxially growing, e.g., SiGe, in and over the S/D recess306. The epitaxial structure serves as the source/drain308. As shown inFIG. 5F, the epitaxial structure completely fills the S/D recess306, including the undercut regions510. That is, the buried portion308-2of the source/drain308also extends laterally directly beneath the disposable spacers508, with the top surfaces of the lateral extending parts of the buried portion308-2directly contacting the bottom surfaces of the disposable spacers508.

In some embodiments, to form an SiGe source/drain308, a buffer layer of SiGe can be first deposited in the S/D recess306and then a bulk layer of SiGe can be deposited over the buffer layer. The buffer layer can have a lower Ge concentration than the bulk layer, such that the lattice constant difference between the buffer layer and the substrate302is relatively small. This helps to prevent defects from being formed in the source/drain308. In some embodiments, a silicon cap layer is formed over the bulk layer. The silicon cap layer can later be silicided to form a contact layer.

After the source/drain308is formed, as shown inFIG. 5G, the disposable spacers508are removed, for example, by wet etching, and the interlayer dielectric layer310is formed over the gate structures304and the source/drain308, including the elevated portion308-4and the lateral extending parts of the buried portion308-2. Thus, a portion of the interlayer dielectric layer310is formed between the elevated portion308-4of the source/drain308and the bottom surface of that portion of the interlayer dielectric layer310directly contacts the top surface of the lateral extending part of the buried portion308-2.

Then, a through hole is formed in the interlayer dielectric layer310to expose a portion of the source/drain308, and a metal material, such as tungsten (W), is deposited into the through hole to form the S/D contact312. As a result, the semiconductor device300A shown inFIG. 3Ais formed.

FIG. 6schematically shows another exemplary semiconductor device600consistent with the present disclosure. The semiconductor device600includes a substrate602, two gate structures604formed over the substrate602, an S/D recess606formed in the substrate602and between the gate structures604, a source/drain608formed in the S/D recess606, an interlayer dielectric layer610covering the substrate602, the gate structures604, and the source/drain608, and an S/D contact612formed through the interlayer dielectric layer610and in contact with the source/drain608. Portions of the substrate602below the gate structures604serve as channel regions614.

The substrate602includes a semiconductor substrate, such as a P-type silicon (Si) substrate. The two gate structures604share one source/drain608and each correspond to one field-effect transistor (FET). In this example, each of the FETs of the semiconductor device600is an N-channel FET. The gate structure604includes a gate dielectric layer604-2formed over the substrate602, a gate electrode604-4formed over the gate dielectric layer604-2, and a spacer604-6formed on the side surfaces of the gate dielectric layer604-2and the gate electrode604-4. The gate structures604can be similar to the gate structures304described above, and thus their detailed description is omitted here.

The source/drain608is formed near the gate structures604and can function as either the source or the drain of the semiconductor device600. The N-channel FETs in the exemplary semiconductor device600utilize electrons, rather than holes, in the channels to form conducting currents when operating, and the mobility of electrons is usually much higher than the mobility of holes. Therefore, a same or similar material as that in the substrate602can be used for the source/drain608. Thus, the source/drain608includes an epitaxial structure made of, for example, Si that is doped with an N-type dopant, such as phosphorous-doped Si (Si:P). Since Si is used for both the substrate602and the source/drain608, the source/drain608does not include an elevated portion, as shown inFIG. 6. Further, as shown inFIG. 6, the source/drain608extends laterally toward the channel region614.

The interlayer dielectric layer610and the contact612can be similar to the interlayer dielectric layer310and the contact312in the semiconductor device300A, and thus their detailed description is omitted here.

Hereinafter, an exemplary process for manufacturing a semiconductor device consistent with the present disclosure will be described, where the semiconductor device can be, for example, the semiconductor device600shown inFIG. 6including N-channel FETs. During the process of manufacturing the semiconductor device600, the first several steps for forming the S/D recess606are similar to the steps for forming the S/D recess306in the process of manufacturing the semiconductor device300A described above with reference toFIGS. 5A-5E, and thus their detailed description is omitted here.

FIGS. 7A and 7Bshow subsequent steps in manufacturing the semiconductor device600. As shown inFIG. 7A, an epitaxial structure is formed in the S/D recess606by epitaxially growing, e.g., Si:P, in the S/D recess606. The epitaxial structure serves as the source/drain608. As shown inFIG. 7A, the epitaxial structure completely fills the S/D recess606, including undercut regions710. That is, the source/drain608also extends laterally directly beneath the disposable spacers508, with the top surfaces of the lateral extending part of the source/drain608directly contacting the bottom surfaces of the disposable spacers508.

In some embodiments, to form an Si:P source/drain608, a buffer layer of Si:P can be first deposited in the S/D recess606and then a bulk layer of Si:P can be deposited over the buffer layer. The buffer layer can have a lower P concentration than the bulk layer.

After the source/drain608is formed, as shown inFIG. 7B, the disposable spacers508are removed and the interlayer dielectric layer610is formed over the gate structures604and the source/drain608, including the lateral extending parts of the source/drain608, which are exposed due to the removal of the disposable spacers508. Thus, a portion of the interlayer dielectric layer610fills in the space left by removing the disposable spacers508and the bottom surface of that portion of the interlayer dielectric layer610directly contacts the top surface of the lateral extending part of the source/drain608.

Then, a through hole is formed in the interlayer dielectric layer610to expose a portion of the source/drain608, and a metal material, such as W, is deposited into the through hole to form the S/D contact612. As a result, the semiconductor device600shown inFIG. 6is formed.

FIGS. 8A and 8Bare images respectively showing an SiGe source/drain of a P-channel FET and an Si:P source/drain of an N-channel FET consistent with the present disclosure. The SiGe source/drain inFIG. 8Ahas a Ge concentration of about 44.7%, and no stacking fault is observed. As a comparison, the SiGe source/drain of the conventional P-channel FET shown inFIG. 2Ahas a lower Ge concentration of about 42.8%, but has clearly observable stacking faults. Further, as shown inFIG. 8B, no cat ear is observed.

FIGS. 9A and 9Bshow a comparison between electrical characteristics of a conventional P-channel FET and a P-channel FET consistent with the present disclosure. Specifically,FIG. 9Ashows an off-current, Ioff, versus an on-current, Ion. A higher Ionat the same Ioffmeans the FET has a higher hole mobility. InFIG. 9A, the circular dots represent the measurement results of the conventional FET and the triangular dots represent the measurement results of the FET consistent with the present disclosure. As shown inFIG. 9A, the Ion/Ioffratio of the FET consistent with the present disclosure is greater by about 3% than that of the conventional FET.

FIG. 9Bshows a comparison of the parasitic capacitance Cov. As shown inFIG. 9B, Covin the FET consistent with the present disclosure is less by about 8% than that of the conventional FET.