Structure and method for reducing miller capacitance in field effect transistors

A method for forming a field effect transistor (FET) device includes forming a gate conductor and gate dielectric on an active device area of a semiconductor wafer, the semiconductor wafer including a buried insulator layer formed over a bulk substrate and a semiconductor-on-insulator layer initially formed over the buried insulator layer. Source and drain extensions are formed in the semiconductor-on-insulator layer, adjacent opposing sides of the gate conductor, and source and drain sidewall spacers are formed adjacent the gate conductor. Remaining portions of the semiconductor-on-insulator layer adjacent the sidewall spacers and are removed so as to expose portions of the buried insulator layer. The exposed portions of the buried insulator layer are removed so as to expose portions of the bulk substrate. A semiconductor layer is epitaxially grown on the exposed portions of the bulk substrate and the source and drain extensions, and source and drain implants are formed in the epitaxially grown layer.

BACKGROUND

The present invention relates generally to semiconductor device processing techniques, and, more particularly, to a structure and method for reducing Miller capacitance in field effect transistors (FETs).

In the manufacture of semiconductor devices, there is a constant drive to increase the operating speed of certain integrated circuit devices such as microprocessors, memory devices, and the like. This drive is fueled by consumer demand for computers and other electronic devices that operate at increasingly greater speeds. As a result of the demand for increased speed, there has been a continual reduction in the size of semiconductor devices, such as transistors. For example, in a device such as a field effect transistor (FET), device parameters such as channel length, junction depth and gate dielectric thickness, to name a few, all continue to be scaled downward.

Generally speaking, the smaller the channel length of the FET, the faster the transistor will operate. Moreover, by reducing the size and/or scale of the components of a typical transistor, there is also an increase in the density and number of the transistors that may be produced on a given amount of wafer real estate, thus lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.

Unfortunately, reducing the channel length of a transistor also increases “short channel” effects, as well as “edge effects” that are relatively unimportant in long channel transistors. One example of a short channel effect includes, among other aspects, an increased drain to source leakage current when the transistor is supposed to be in the “off” or non-conductive state, due to an enlarged depletion region relative to the shorter channel length. In addition, one of the edge effects that may also adversely influence transistor performance is what is known as Miller capacitance. In CMOS applications, the Miller capacitance is an amplification of a gate to drain capacitance primarily dominated by a parasitic overlap capacitance (Cov) component. Overlap capacitance exists primarily as a result of the doped polycrystalline silicon gate electrode and gate dielectric that (almost invariably) overlaps with a conductive portion of the more heavily doped source/drain regions and/or the less heavily doped source/drain extension (SDE) regions (if present) of the FET. The relative contribution of the overlap capacitance to the overall device capacitance increases as the gate length is scaled down. For example, Covcan account for as much as 50% of the overall capacitance when a MOSFET has a scaled gate length of about 30 nanometers.

Accordingly, it would be desirable to be able to fabricate an FET that maintains a low series resistance between the gate and the drain and between the gate and the source of the device, while at the same time retaining beneficial short channel effects and minimizing the parasitic Miller capacitance formed by the drain overlap and/or the source overlap, depending on the device application.

SUMMARY

The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a method for forming a field effect transistor (FET) device. In an exemplary embodiment, the method includes gate conductor and gate dielectric on an active device area of a semiconductor wafer, the semiconductor wafer including a buried insulator layer formed over a bulk substrate and a semiconductor-on-insulator layer initially formed over the buried insulator layer. Source and drain extensions are formed in the semiconductor-on-insulator layer, adjacent opposing sides of the gate conductor, and source and drain sidewall spacers are formed adjacent the gate conductor. Remaining portions of the semiconductor-on-insulator layer adjacent the sidewall spacers and are removed so as to expose portions of the buried insulator layer. The exposed portions of the buried insulator layer are removed so as to expose portions of the bulk substrate. A semiconductor layer is epitaxially grown on the exposed portions of the bulk substrate and the source and drain extensions, and source and drain implants are formed in the epitaxially grown layer.

In another embodiment, a field effect transistor (FET) device includes a gate conductor and gate dielectric formed over a semiconductor-on-insulator layer, source and drain sidewall spacers formed adjacent the gate conductor, source and drain extensions formed within the semiconductor-on-insulator layer and beneath the source and drain sidewall spacers, a buried insulator structure upon which the semiconductor-on-insulator layer is formed, and doped source and drain regions formed adjacent to opposing sidewalls of the buried insulator structure, with at least a portion of the doped source and drain regions disposed below the source and drain extensions. The doped source and drain regions have a thickness sufficient for silicide contact formation therein.

DETAILED DESCRIPTION

Disclosed herein is a method and structure for reducing parasitic Miller capacitance in fully depleted field effect transistors (FETs), in which a buried source/drain MOSFET is created by removing portions of a buried insulator (e.g., oxide) layer corresponding to the source/drain locations and growing an epitaxial layer (e.g., silicon) on the exposed bulk material. This creates sufficient silicon thickness for silicidation of the source/drain contacts without the need for raised source/drain structures that have increased Miller capacitance.

Referring initially toFIG. 1, there is shown a cross sectional view of one type of conventional silicon-on-insulator (SOI) MOS transistor100, in which a bulk substrate102(e.g., silicon) has a buried oxide layer (BOX)104formed thereon. Formed over the BOX layer104is a thin layer of silicon106(i.e., the SOI layer) in which the active transistor device is defined. As is known in the art, one advantage associated with SOI devices is reduced junction capacitance, as the majority of the bulk silicon is isolated from the body107of the active transistor through the BOX layer104.

The scaled down MOSFET100, having submicron or nanometer dimensions, includes a source extension108and a drain extension110formed within an active device area of the SOI layer106. For this particular configuration of SOI FET, the total thickness of the SOI layer106(tSOI) may be on the order of about 20 nanometers (nm) to about 150 nm. The source extension108and the drain extension110are shallow doped junctions designed to minimize short channel effects in the MOSFET100having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.

The MOSFET100further includes a deep source doping region112and a deep drain doping region114, each having silicide regions116for providing contact to the source and drain of the MOSFET100. In addition, the SOI MOSFET100may include angled halo implant regions118,120on the source and drain sides of the device (for further reducing short channel effects), wherein the halo implant regions have an opposite polarity dopant with respect to the deep source and drain regions112,114. In other words, for an n-type transistor, the deep source and drain regions are doped with an n-type dopant, while the halo implants comprise a p-type dopant.

As further illustrated inFIG. 1, MOSFET100includes a gate dielectric122(e.g., an oxide) and a gate structure124formed thereon, which may be a polysilicon material, for example. As is the case with the source and drain regions, a gate silicide126is formed on the polysilicon gate124for providing low resistance contact thereto. A thin (offset) spacer128is also disposed on the sidewalls of the polysilicon gate124and gate oxide122, and may also be an oxide material that acts as a buffer liner for nitride spacers130.

In such a device, parasitic capacitance components are present. For example, in a typical CMOS application, the gate to drain capacitance is typically amplified with respect to the gate to source capacitance due to the Miller effect since the source potential is generally fixed (e.g., an NFET source coupled to a logic low potential, and a PFET source coupled to a logic high potential). On the other hand, the voltage of the drain of a CMOS device is also subject to change at the same time the gate voltage changes, thus resulting in the amplified Miller effect. As shown inFIG. 1, one component of the overall gate to drain capacitance results from the “outer fringe” capacitance (Cof) defined by the sidewall of the gate conductor124on the drain side, the dielectric of the spacer material128,130, and the drain extension110.

In addition, an “inner fringe” capacitance (Cif) is defined by the bottom of the gate conductor124, the transistor body107, and the deep drain region114. However, this component of parasitic capacitance is primarily present at gate voltages less than or equal to the threshold voltage (VT) of the device. Once the gate voltage reaches and exceeds VT, the inversion charge in the channel isolates the body and deep drain region from the gate124, rendering Cifmostly insignificant. Another component of gate to drain capacitance (and typically the most significant for scaled down devices) is the overlap capacitance of the drain extension region110beneath the gate conductor124and gate oxide122, as indicated above. Still another component that can contribute to gate to drain capacitance results from via studs (not shown) that connect the silicide contacts116to upper wiring levels of the device.

On the whole, the individual components of gate to drain capacitance (and thus Miller capacitance for a CMOS application) of the MOSFET100ofFIG. 1are generally acceptable for desired device performance. On the other hand, improved short channel effects for a scaled down device of the type shown inFIG. 1are more likely realized through, for example, halo implants118,120. However, a higher dopant concentration of the halo implants will increase the junction capacitance and reduce the breakdown voltage of the device.

FIG. 2is a cross sectional view of another previously proposed SOI MOSFET design200, aimed at improving short channel effects. As can be seen, the raised source/drain MOSFET200ofFIG. 2is characterized by an ultra thin SOI body thickness (e.g., on the order of about 3 nm to about 30 nm in thickness), which is also referred to as a fully depleted SOI device as opposed to the partially depleted SOI device ofFIG. 1. While such a configuration offers an improvement in short channel effects with respect to the device ofFIG. 1, there is an overall increase in the parasitic capacitance effects in the configuration ofFIG. 2.

On one hand, the junction capacitance of the MOSFET200is reduced with respect to that ofFIG. 1, due to the reduced body thickness and absence of halo implantations. Along the same lines, the “inner fringe” capacitance (Cif) is also reduced because there is a reduced drain perimeter associated with the reduced body thickness. However, this is more than offset by an increased “outer fringe” capacitance (Cof) as a result of the raised source/drain configuration of MOSFET200. In order to prevent a decrease in series resistance from an ultra thin silicon/silicide contact regions, additional silicon and silicide thickness is present adjacent the nitride spacers130. This therefore increases the value of Cofwith respect toFIG. 1, and to an extent that surpasses the decrease in Cofand Cj.

Accordingly,FIGS. 3(a) through3(j) illustrate an exemplary process flow for forming a buried source/drain MOSFET, in accordance with an embodiment of the invention. Although the embodiments presented herein are described in terms of ultrathin SOI devices, it will be appreciated that the methodology and structures disclosed are also applicable to various types of semiconductor bulk substrates, buried insulator materials and active device semiconductor materials, as well as thicknesses thereof.

InFIG. 3(a), the device is processed up to the point following source drain/extension implantation, but before source/drain spacer formation. For the MOSFET device300(having a fully depleted channel301), the source extension302and drain extension304are formed within an ultrathin silicon layer disposed above a buried oxide layer (BOX)306. As will also be recognized from an ultrathin SOI device, the BOX layer306is formed over a bulk silicon region308of the carrier wafer. Shallow trench isolation (STI) regions310(e.g., oxide) isolate the FET from neighboring devices.

With the exception of a sacrificial silicon nitride cap312, the formation of the gate and source/drain extension implants may follow conventional device processing, including the gate oxide314, gate electrode316(e.g., polysilicon), and the offset spacers318used to define the source and drain extensions302,304. The functions of the nitride cap312, which may be patterned and etched during the gate electrode formation, will become more evident hereinafter.

As shown inFIG. 3(b), layers used in the creation of source/drain sidewall spacers are formed over the device. These may include, for example, a spacer liner layer320and a spacer layer322(e.g., silicon nitride). The layers320,322are then patterned and etched so as to form the source/drain sidewall spacers324, as shown inFIG. 3(c). Then, as shown inFIG. 3(d), the doped silicon present in the source/drain locations is removed so as to expose a corresponding portion of the BOX layer306therebeneath, leaving only the source extension302and drain extension304(protected from etching by the source/drain sidewall spacers324and liner layer320. During this silicon removal, the silicon nitride cap312also protects the gate electrode316.

InFIG. 3(e), a photoresist layer326is patterned over the device to expose the BOX layer306corresponding to the buried source/drain formation, as well as to protect STI regions310. The exposed BOX regions are then removed so as to expose the bulk silicon layer308, as shown inFIG. 3(f). This step may be implemented, for example, through a dry etch process. Once the substrate is exposed, it may be optionally implanted in order to engineer the substrate with a dopant of a desired type. Then, the resist layer is removed, as shown inFIG. 3(g).

Referring now toFIG. 3(h), a selective epitaxial silicon layer328is grown on the exposed silicon portions of the device (the dashed line indicative of the original top surface of the bulk layer308). Again, although the exemplary embodiments disclosed herein illustrate silicon as the epitaxial material, it will be appreciated that other materials can be epitaxially grown on the bulk substrate including, for example, silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), germanium (Ge), as well as combinations thereof.

In terms of the FET device, the exposed silicon is located only at the bulk silicon regions308corresponding to the source/drain of the FET, and the source/drain extensions302,304. A crystal seam330occurs where the selective epitaxial silicon nucleating on the bulk silicon308meets the selective epitaxial silicon nucleating on the source/drain extensions302,304. As shown inFIG. 3(i), the source and drain regions332,334are implanted, thereby resulting in a “buried source/drain” device that has sufficient silicon thickness for contact silicidation. Moreover, since this source/drain silicon thickness is adjacent the remaining portion of the BOX layer306beneath the gate, the Miller capacitance problems associated with a fully depleted, raised source/drain FET are avoided.

Finally, inFIG. 3(j), the nitride cap312atop the gate electrode is removed (e.g., by RIE) and the source and drain implants are activated by a rapid thermal anneal. The silicide contacts336for the source, drain and gate are then formed in a suitable manner known in the art. The silicidation of the source and drain regions also shunts the seams330created by the epitaxial growth process.

FIGS. 4(a) through4(e) illustrate an alternative embodiment of the buried source/drain formation process described above. In this embodiment, the steps shown inFIGS. 3(a) through3(e) are carried out as before. However, before removing the photoresist layer326after the initial BOX layer etch, another (sidewall) etch of the BOX material is performed as shown inFIG. 4(a). This additional etch (which may be a dry etch or a wet etch) is designed to remove a portion of the remaining BOX layer306beneath the sidewall spacers324and source/drain extensions302,304. Essentially, the BOX layer306beneath the gate in the embodiment ofFIG. 4(a) is shorter in length than that ofFIG. 3(f). Again, at this point, the exposed bulk silicon308may be implanted to change the dopant type thereof.

Following the additional BOX etch, the resist layer is stripped as shown inFIG. 4(b), and a selective epitaxial layer328is grown on the exposed silicon of the device inFIG. 4(c). As is the case with the previous embodiment, the epitaxial silicon layer328is formed on the bulk silicon regions308corresponding to the source/drain of the FET, and the source/drain extensions302,304. The gate electrode316, being encapsulated by silicon nitride, does not have any epitaxial silicon grown thereon. Then, inFIG. 4(d), the source/drain regions332,334are implanted. As compared to the embodiment ofFIGS. 3(i) and3(j), the reduced length BOX306ofFIG. 4(d) provides for an increased width/decreased resistance of the doped source/drain epitaxial silicon, and thus brings the same into closer proximity to the channel region beneath the gate. The silicidation of the gate, source and drain contacts336(following rapid thermal processing to activate the source/drain implants, and nitride cap removal) is shown inFIG. 4(e). Again, the seams330created during the epitaxial silicon growth are shunted by silicidation.

Still another embodiment for forming a buried source/drain FET is shown inFIGS. 5(a) through5(i). In this embodiment, the steps shown inFIGS. 3(a) through3(d) are carried out as before. That is, the ultrathin silicon is removed to expose the BOX layer306, leaving only the source and drain extensions302,304beneath the sidewall spacers324. However, prior to applying a patterned photoresist layer for the selective BOX removal,FIG. 5(a) illustrates the formation of another set of spacers502, such as a silicon dioxide or silicon nitride material (and associated liner) adjacent the sidewall spacers324. As will be shown below, the additional spacers502will serve to protect the outer sidewalls of the source and drain extensions302,304from exposure during epitaxial silicon growth, thus preventing nucleation on the sidewalls. This, in turn, will facilitate an improved, smoother silicide profile with lower resistance and greater yield.

Following the formation of additional spacers502,FIG. 5(b) illustrates the patterning of photoresist layer326in preparation of the BOX recess. InFIG. 5(c), the exposed BOX layer306is vertically etched (e.g., with a dry RIE etch) to expose the bulk silicon308. As with the previous embodiments, an implant step can be performed at this point to engineer the dopant type of the substrate. Proceeding toFIG. 5(d), a horizontal etch is used to remove additional BOX sidewall material (as was done for the previous embodiment) to reduce the length of the BOX306beneath the gate. It will also be noted that the bulk substrate308could also be doped following this step.

InFIG. 5(e), the resist layer is stripped, and inFIG. 5(f), a selective epitaxial layer328is grown on the exposed silicon, including the bulk silicon308and the bottom surfaces of the source/drain extensions302,304. A crystal seam330is again formed from selective epitaxial silicon nucleating on the bulk silicon308meeting the selective epitaxial silicon nucleating on the source/drain extensions302,304. At this point, the additional spacers502and nitride cap312are removed through a dry RIE etch, as shown inFIG. 5(g). Then, the source and drain regions are implanted as shown inFIG. 5(h), and thereafter activated to diffuse the dopants therein.

Finally, inFIG. 5(i), the gate, source and drain contacts336are silicided, shunting the seams330created during the epitaxial silicon growth. As can be seen fromFIG. 5(i), the small, thinner protrusions initially formed during the epi-growth are consumed (i.e., converted to silicide) during the silicidation process. Moreover, this smoother profile also brings the sloped portion of the silicide contacts336of the source and drain in closer proximity to the channel than with respect to the earlier embodiments. Particularly, it will be observed that the source/drain silicide contacts meet with the spacers324at the bottom portions of the spacers, instead of with the sides of the spacers324as in the embodiments ofFIGS. 3(j) and4(e).