Image pickup system

An image pickup system is an image pickup system in which an image pickup device arranged at a distal end of an insertion section of an endoscope and a processor can communicate with each other. A group of multiple control parameters to be collectively transmitted and checksum codes related to the parameters are transmitted from the processor to the image pickup device, and the image pickup device reflects the control parameters on a register only when all the received multiple control parameters are normal, on the basis of the checksums.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an image pickup system which includes an endoscope provided with an image pickup device arranged at a distal end of the endoscope.

2. Description of the Related Art

Recently, endoscopes provided with an image pickup device have been widely used in a medical field and an industrial field.

A technique is also known in which various signal processings related to an endoscope are performed by a signal processing apparatus referred to as a processor, which is removably connected to the endoscope.

Furthermore, in this kind of endoscope, it is necessary to, at the image pickup device arranged at a distal end side of an insertion section, acquire multiple control parameters for controlling the image pickup device at the time of or after startup and appropriately make register settings. Note that, as the register settings, an example given in Japanese Patent Application Laid-Open Publication No. 2011-147548 is known.

The multiple control parameters are sent out from a control section configured, for example, by an FPGA. In this kind of endoscope, the control section and the like are arranged in an operation section of the endoscope, a connector connecting the endoscope and the processor, or in the processor itself because of space limitations that can be secured around the image pickup device.

SUMMARY OF THE INVENTION

An image pickup system of an aspect of the present invention is an image pickup system comprising an image pickup apparatus generating and outputting an image signal by receiving a light and performing photoelectric conversion, and a control apparatus sending out control parameters for performing drive control of the image pickup apparatus, the image pickup apparatus and the control apparatus being capable of communicating with each other, and the image pickup system comprising: a first communication section being provided in the control apparatus and transmitting multiple control parameters for controlling photographing of the image pickup apparatus to the image pickup apparatus; a second communication section being provided in the image pickup apparatus and receiving the control parameters transmitted from the first communication section; a judgment section being provided in the control apparatus and judging whether the multiple control parameters received by the second communication section are normal or not; a control-apparatus-side control section being provided in the control apparatus and transmitting, when judging that the multiple control parameters received by the image pickup apparatus are normal on the basis of a result of the judgment by the judgment section, a control signal permitting the image pickup apparatus to reflect the multiple control parameters related to the judgment result, to the image pickup apparatus via the first communication section; and a photographing control section being provided in the image pickup apparatus and being for performing photographing control by the multiple control parameters received by the second communication section, on the basis of the result of the judgment by the judgment section.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be described in detail below with reference to drawings.

First Embodiment

As shown inFIG. 1, an image pickup system1provided with an image pickup apparatus according to a first embodiment of the present invention is provided with: an endoscope2provided with an image pickup device100, a light source apparatus3to which the endoscope2is removably connected and which supplies an illumination light to the endoscope2, a processor4as a signal processing apparatus to which the endoscope2is removably connected and which performs predetermined signal processing, and a monitor5as a display apparatus which displays an image signal generated by the processor4as an endoscopic image.

The endoscope2has an elongated insertion section6to be inserted into a body cavity, an operation section7provided at a rear end of the insertion section6, and a universal cord8extended from the operation section7. The universal cord8branches into a light guide cord9and a signal cord (signal cable)10near a proximal end thereof or midway. A light source connector11at an end of the light guide cord9is removably connected to the light source apparatus3, and a signal connector12at an end of the signal cord10is removably connected to the processor4.

A light guide13for transmitting an illumination light is inserted through the insertion section6, the operation section7and the universal cord8. By connecting the light source connector11to the light source apparatus3, an illumination light from the light source apparatus3is transmitted to the light guide13, and the transmitted illumination light is emitted from a light guide distal end surface attached to an illumination window provided at a distal end portion14of the insertion section6. Note that such a configuration is also possible that a connector in which the light source connector11and the signal connector12are integrated is connected to the light source apparatus3so that a signal of the signal connector12may be handed over from or to the processor4via a cable connecting the light source apparatus3and the processor4.

The distal end portion14is provided with an observation window (image pickup window) adjacent to the illumination window, and an objective lens15which forms an optical image of an object, such as an illuminated affected part, is attached to the observation window. At an image forming position of the objective lens15, an image pickup device configured, for example, by a CMOS image sensor (hereinafter briefly referred to as a CIS)100is arranged.

The CIS100is connected to a connector16provided inside the signal connector12via an integrated coaxial cable101inserted through the insertion section6and the universal cord8, and the connector16is removably connected to the processor4.

The processor4is provided with: a power supply circuit not shown which generates power supplies with multiple power supply voltages required for operations of the image pickup device and the like, a signal processing circuit (not shown inFIG. 1) which performs predetermined signal processing for an image pickup signal outputted from the image pickup device and a control circuit (not shown inFIG. 1) which performs control, including the power supply circuit and the signal processing circuit, as well as a control section (FPGA)200for transmitting multiple control parameters for controlling the CIS100to the CIS100, which is configured, for example, by an FPGA, and a memory201which stores information about the multiple control parameters. Note that other components in the processor4will be described in detail later.

In the present embodiment, the control section (FPGA)200is adapted to read out various setting values of the multiple control parameters from the memory201and transmit the setting values to the CIS100via the integrated coaxial cable101by communication. Note that transmission operation of the multiple control parameters will be described later.

The control section200is configured by an FPGA in the present embodiment but is not limited thereto. Other communication devices are also possible.

The integrated coaxial cable101extends from an output end of the CIS100into the insertion section6, further passes through the universal cord8, and is removably connected to the processor4via the connector16provided inside the signal connector12.

The integrated coaxial cable101is a cable which connects the CIS100and the processor4and through which not only power supply to the CIS100is transmitted but also a video signal (a serial signal) on which a synchronization signal transmitted from the CIS100is superimposed, a vertical synchronization signal (VD) transmitted from the processor4, communicated contents of multiple control parameters, and an error correcting code or an error detecting code transmitted from the processor4to the CIS100, and the like are transmitted and received.

The integrated coaxial cable101is shielded with a shield member formed by an exterior member of the insertion section6. Furthermore, the shield member is electrically connected to a shield member formed by an exterior member of the operation section7, a shield member formed by an exterior member of the universal cord8, a shield member of the signal connector12and the like.

FIG. 2is a block diagram showing a configuration of an electric system in the image pickup system of the present embodiment.

The image pickup device (CIS)100is configured by a so-called CMOS (complementary metal oxide semiconductor circuit) image sensor and is configured being provided with: a light receiving element111arranged at the image forming position of the objective lens15, an AFE (analog front end)112which removes noise from a signal outputted from the light receiving element111and digitizes the signal, a synchronization superimposition circuit113which superimposes a synchronization signal on a video signal, which is an output signal of the AFE112, a P/S conversion circuit114for converting the video signal to a serial signal for transmission to output the serial signal to an outside, a video signal transmitting section115for outputting the video signal (serial signal) to the outside, a synchronization signal receiving section116which receives a vertical synchronization signal (VD) and the like from the outside, for example, from the processor4, a synchronization signal processing section117which performs predetermined processing for the synchronization signal from the outside received by the signal receiving section116(the vertical synchronization signal (VD) received from the processor4) in a predetermined case, and a timing generator (TG)118which generates its own synchronization signal in the CIS100and causing its own synchronization signal to follow the external synchronization signal for which the predetermined processing has been performed by the synchronization signal processing section117to supply the synchronization signal to respective circuits as various synchronization signals in the CIS100as well as a control parameter receiving section131which receives control parameters, and an error correcting code or an error detecting code transmitted from the control section (FPGA)200, a judgment section132which judges whether or not the received control parameters have been correctly transmitted and received, on the basis of the error correcting code or the error detecting code (in the present embodiment, a checksum code) added to communicated contents of the control parameters received by the control parameter receiving section131, and a register133which stores control parameters and the like to be used for photographing control in the CIS100.

On the other hand, the processor4is provided with: a video signal receiving section121which receives a video signal (serial signal) having video data transmitted from the CIS100, an S/P conversion circuit122which converts the video signal (serial signal) with a synchronization signal superimposed thereon, which has been received by the video signal receiving section121, to a parallel signal, a signal processing section123which performs predetermined signal processing for the received video signal and outputs the video signal to the monitor5and the like, a timing generator (TG)125which generates a vertical synchronization signal (VD) for image processing in the processor4and supplies the vertical synchronization signal (VD) to various circuits, a synchronization signal transmitting section124which transmits the vertical synchronization signal (VD) in the processor4supplied from the timing generator (TG)125to the CIS100, the above-described control section (FPGA)200which is configured, for example, by an FPGA, a control parameter transmitting section211for transmitting multiple control parameters for controlling the CIS100to the CIS100, which is configured in the control section (FPGA)200, and the memory201which stores information about the multiple control parameters.

Note that, though the control parameter transmitting section211is assumed to be configured in the control section (FPGA)200in the present embodiment, another component, the timing generator (TG)125may be configured in the FPGA.

In the present embodiment, the control section (FPGA)200reads out various setting values of the multiple control parameters from the memory201at the time of startup and transmits the setting values from the control parameter transmitting section211in the control section (FPGA)200to the CIS100via the integrated coaxial cable101, for example, on the basis of an I2C interface. After the startup also, corresponding control parameters are transmitted via communication in order to change settings for a photographing mode, a gain setting, an electronic shutter setting, a cutout position and the like as necessary.

Though the I2C interface is adopted as a communication system in the present embodiment, the communication system is not limited thereto, and, another communication system, for example, an SPI interface may be adopted.

Next, multiple control parameters transmitted in the present embodiment will be described.

In the present embodiment, the control section (FPGA)200is adapted to read out various setting values of multiple control parameters from the memory201and transmit the setting values to the CIS100via the integrated coaxial cable101as described above. The “multiple control parameters” are classified into some groups. Multiple control parameters belonging to each group do not have a meaning until all the control parameters in the group are normally transmitted. That is, multiple control parameters belonging to a certain group are treated as a preset set of integrated information in the present embodiment.

The multiple control parameters transmitted in the image pickup system of the present embodiment are classified, for example, into following groups.

Group A includes multiple control parameters for brightness (light adjustment), and, more specifically, the multiple control parameters are as follows:

(b) Position of electronic shutter

(c) Binning setting (for example, a setting for addition of pixels, settings for how many pixels are to be added, the direction of the addition and the like)

There is a possibility that, if a part of these control parameters are reflected, unintentional inappropriate brightness control is performed. For example, since brightness changes as the number of added pixels changes, it is desirable to perform control of the binning setting simultaneously with control of the gain setting and the electronic shutter setting.

Group B is a control parameter group for address information about a correction position, and, more specifically, two parameters of a parameter for x-coordinate data and a parameter for y-coordinate data correspond to Group B. Here, it is apparent that a correct operation is not performed even if only one control parameter is reflected. Both are to be accurately transmitted. Note that all address information is targeted.

Group C is a control parameter group for specifying a predetermined “range” on a screen such as a cutout range. More specifically, there are various specification methods for specifying a cutout range, and, for example, a parameter for a cutout starting point position and a parameter for an ending point position correspond to Group C. Description will be made on a case where both of the parameter for a starting point position and the parameter for an ending point position are accurately transmitted and a case the parameters are not accurately transmitted, with the use ofFIG. 3.

FIG. 3is a diagram illustrating an example of transmission of a parameter specifying a cutout range among the multiple control parameters transmitted in the image pickup system of the first embodiment.

For example, in the case of changing a cutout range to a position shown inFIG. 3(B)in a state in which a starting point position and an ending point position shown inFIG. 3(A)are specified as an initial state of the cutout range, the position in FIG.3(B) is reflected if both of the parameter for the starting point position and the parameter for the ending point position are accurately transmitted. However, for example, if the parameter for the starting point position is accurately transmitted but the parameter for the ending point position is not accurately transmitted, a relationship between the starting point position and the ending point position is in an abnormal state, and a cutout range does not exist, as shown inFIG. 3(C).

Note that, though the above three examples are given as the control parameter groups in the present embodiment, it goes without saying that the control parameter groups are not limited thereto, and the invention as claimed in the application concerned may be applied to another preset set of integrated information.

Next, operation in the present embodiment will be described.

In the present embodiment, an error correcting code (for example, a Hamming code or the like) or an error detecting code (a parity bit, a checksum or the like) is transmitted together with the communicated contents of the multiple control parameters described above.

That is, at the time of or after startup, the control section (FPGA)200reads out various setting values of multiple control parameters from the memory201, in the processor4, and transmits an error correcting code or an error detecting code (a parity bit, a checksum or the like) together with communicated contents of multiple control parameters from the control parameter transmitting section211.

Description will be made below on an example of transmitting communicated contents of the multiple control parameters of Group A described above with a checksum code as the error detection code added thereto.

FIG. 4is a diagram showing an example of transmitting communicated contents of control parameters about brightness (light adjustment) transmitted in the image pickup system of the first embodiment with a checksum code added thereto, and, more specifically, shows an example of transmitting a gain setting, an electronic shutter setting and a binning setting with a checksum code for all these functions added thereto.

The control parameter receiving section131in the CIS100receives communicated contents of a gain setting, an electronic shutter setting and a binning setting, and a checksum code for all these functions which are transmitted from the control parameter transmitting section211in the control section (FPGA)200.

After that, the judgment section132judges whether or not the received control parameters have been correctly transmitted and received, on the basis of the checksum code added to the communicated contents of the control parameters received by the control parameter receiving section131.

If the checksum result is OK as a result of the judgment by the judgment section132, all of the gain setting, the electronic shutter setting and the binning setting are reflected on the register133.

On the other hand, if the checksum result described above is NG as a result of the judgment by the judgment section132, the judgment section132performs control so that none of the gain setting, the electronic shutter setting and the binning setting is reflected on the register133. That is, if some setting value is already stored in the register133, control is performed so that update with the newly received setting values is not performed.

Note that, though none of the new control parameter settings is reflected on the register133in the case of the checksum result being NG, in the present first embodiment as described above, content indicating that the checksum result is NG, that is, content indicating that the communication result is NG may be stored in another register not shown in the CIS100instead of or together with the above.

Otherwise, the content indicating that the communication result is NG may be notified to the control section (FPGA)200in the processor4via a signal line for transmitting a video signal from the CIS100or another signal line arranged in advance between the CIS100and the processor4.

As described above, according to the first embodiment, it is possible to provide an image pickup system in which a CMOS image sensor is arranged at a distal end of an insertion section of an endoscope, and preset multiple control parameters required for photographing control are transmitted from a processor side to a CMOS image sensor side, the image pickup system being capable of always performing normal photographing control by treating the control parameters required for photographing control as a set of integrated information, and performing control so that information about the control parameters is reflected on a register in the CMOS image sensor only when all the multiple control parameters have been normally transmitted and contents of the register are not updated when all the multiple control parameters have not been normally transmitted.

Second Embodiment

An image pickup system of the second embodiment of the present invention is configured similarly to the first embodiment. However, the communicated contents of the multiple control parameters, and the transmitted contents of the error correcting code or the error detecting code which are transmitted from a control parameter transmitting section211to a CIS100are different. Since the other components are equal to those of the first embodiment, detailed description thereof is omitted here.

FIG. 5is a diagram showing an example of transmitting communicated contents of control parameters about brightness (light adjustment) transmitted in the image pickup system of the second embodiment with checksum codes added thereto, and, more specifically, shows an example of transmitting a gain setting, an electronic shutter setting and a binning setting with a checksum code added to each thereof.

In the second embodiment, a control parameter receiving section131in the CIS100receives communicated contents of a gain setting, an electronic shutter setting and a binning setting, and a checksum code combined with each thereof which are transmitted from the control parameter transmitting section211in a control section (FPGA)200.

After that, a judgment section132judges whether or not the received multiple control parameters have been correctly transmitted and received, on the basis of the checksum codes of the respective control parameters added to the communicated contents of the control parameters received by the control parameter receiving section131.

If all the checksum results are OK as a result of the judgment by the judgment section132, all of the gain setting, the electronic shutter setting and the binning setting are reflected on a register133.

On the other hand, if any of the respective checksum results is NG as a result of the judgment by the judgment section132, the judgment section132performs control so that none of the gain setting, the electronic shutter setting and the binning setting is reflected on the register133. In this case, if some setting value is already stored in the register133, control is performed so that update with the newly received setting values is not performed, similarly to the first embodiment.

Note that, though none of the new control parameter settings is reflected on the register133in the case of any of the checksum results being NG in the present second embodiment also similarly to the first embodiment described above, content indicating that the checksum result is NG, that is, content indicating that the communication result is NG may be stored in another register not shown in the CIS100or the content indicating that the communication result is NG may be notified to the control section (FPGA)200in a processor4via a signal line for transmitting a video signal from the CIS100or another signal line arranged in advance between the CIS100and the processor4, instead of or together with the above.

Note that, thoughFIG. 5shows an example in which the gain setting, the electronic shutter setting and the binning setting combined with their respective checksum codes are continuously transmitted, the present embodiment is not limited thereto. Whether or not the multiple control parameters have been transmitted as a set of integrated information may be judged by specifying the number of kinds to be transmitted in a header in advance and detecting whether or not all the kinds of control parameters have been transmitted, by the control parameter receiving section131or the judgment section132, which is a receiver.

As described above, according to the second embodiment, it is possible to provide an image pickup system in which a CMOS image sensor is arranged at a distal end of an insertion section of an endoscope, and preset multiple control parameters required for photographing control are transmitted from a processor side to a CMOS image sensor side, the image pickup system being capable of always performing normal photographing control by treating the control parameters required for photographing control as a set of integrated information, and performing control so that information about the control parameters is reflected on a register in the CMOS image sensor only when all the multiple control parameters have been normally transmitted and, for all the control parameters, contents of the register are not updated when any of the control parameters has not been normally transmitted, similarly to the first embodiment.

Third Embodiment

An image pickup system of the third embodiment of the present invention is configured similarly to the first and second embodiments. However, the communicated contents of the multiple control parameters, and the transmitted contents of the error correcting code or the error detecting code which are transmitted from a control parameter transmitting section211to a CIS100are different from both of the first and second embodiments. Since the other components are equal to those of the first embodiment, detailed description thereof is omitted here.

FIG. 6is a diagram showing an example of transmitting communicated contents of a control parameter about brightness (light adjustment) transmitted in the image pickup system of the third embodiment with checksum codes added thereto, and, more specifically, shows such an example that is similar to the second embodiment in that a gain setting, an electronic shutter setting and a binning setting are transmitted with a checksum code added to each thereof but that only the checksum codes are collected when being transmitted.

In the third embodiment also, a control parameter receiving section131in the CIS100receives communicated contents of a gain setting, an electronic shutter setting and a binning setting, and a checksum code combined with each thereof which are transmitted from a control parameter transmitting section211in a control section (FPGA)200, similarly to the second embodiment.

After that, a judgment section132judges whether or not the received multiple control parameters have been correctly transmitted and received, on the basis of the checksum codes of the respective control parameters added to the communicated contents of the control parameters received by the control parameter receiving section131.

If all the checksum results are OK as a result of the judgment by the judgment section132, all of the gain setting, the electronic shutter setting and the binning setting are reflected on a register133, similarly to the first and second embodiments.

On the other hand, if any of the respective checksum results is NG as a result of the judgment by the judgment section132, the judgment section132performs control so that none of the gain setting, the electronic shutter setting and the binning setting is reflected on the register133, similarly to the second embodiment. In this case, if some setting value is already stored in the register133, control is performed so that update with the newly received setting values is not performed, similarly to the first and second embodiments.

In the present third embodiment also, content indicating that the checksum result is NG, that is, contents that a communication result is NG may be stored in another register not shown in the CIS100, or the content that the communication result is NG may be notified to the control section (FPGA)200in a processor4via a signal line for transmitting a video signal from the CIS100or another signal line arranged in advance between the CIS100and the processor4, similarly to the first and second embodiments described above.

As described above, according to the third embodiment, it is possible to provide an image pickup system in which a CMOS image sensor is arranged at a distal end of an insertion section of an endoscope, and preset multiple control parameters required for photographing control are transmitted from a processor side to a CMOS image sensor side, the image pickup system being capable of always performing normal photographing control by treating the control parameters required for photographing control as a set of integrated information, and performing control so that information about the control parameters is reflected on a register in the CMOS image sensor only when all the multiple control parameters have been normally transmitted and, for all the control parameters, contents of the register are not updated when any of the control parameters has not been normally transmitted, similarly to the second embodiment.

Fourth Embodiment

The image pickup system of the first embodiment described above performs the judgment about whether multiple control parameters transmitted from a processor4side to a CIS100side have been normally transmitted or not by the CIS100. In comparison, an image pickup system of the fourth embodiment of the present invention is characterized in performing the judgment on a processor4A side.

Note that only such parts that are different from the first embodiment will be described here, and description of components similar to those of the first embodiments is omitted.

FIG. 7is a block diagram showing a configuration of an electric system in the image pickup system of the fourth embodiment of the present invention.

As shown inFIG. 7, an image pickup system1A provided with an image pickup apparatus according to the fourth embodiment of the present invention is provided with: an endoscope2A provided with an image pickup device (CIS)100A, a light source apparatus to which the endoscope2A is removably connected and which supplies an illumination light to the endoscope2A, a processor4A as a signal processing apparatus to which the endoscope2A is removably connected and which performs predetermined signal processing, and a monitor as a display apparatus which displays an image signal generated by the processor4A as an endoscopic image.

Similarly to the first embodiment, the image pickup device (CIS)100A in the image pickup system1A of the fourth embodiment is configured by a so-called CMOS (complementary metal oxide semiconductor circuit) image sensor arranged at a distal end of an insertion section and connected to the processor4A via an integrated coaxial cable101A inserted through the insertion section and a universal cord.

The integrated coaxial cable101A extends from an output end of the CIS100A into the insertion section, further passes through the universal cord, and is removably connected to the processor4A via a connector provided inside the signal connector.

The integrated coaxial cable101A is similar to those of the first to third embodiments in that it is a cable connecting the CIS100A and the processor4A. In addition to transmission of power supply supplied to the CIS100A, a video signal (serial signal) on which a synchronization signal transmitted from the CIS100A is superimposed and a vertical synchronization signal (VD) transmitted from the processor4A are transmitted and received. Additionally, a two-way communication line102connecting the processor4A and the CIS100A is held so that communicated contents of multiple control parameters and the like are transmitted and received.

Similarly to the first embodiment, the CIS100A is provided with a light receiving element111arranged at an image forming position of the objective lens15, an AFE (analog front end)112which removes noise from a signal outputted from the light receiving element111and digitizes the signal, a synchronization superimposition circuit113which superimposes a synchronization signal on a video signal, which is an output signal of the AFE112, a P/S conversion circuit114for converting the video signal to a serial signal for transmission to output the serial signal to an outside, a video signal transmitting section115for outputting the video signal (serial signal) to the outside, a synchronization signal receiving section116which receives a vertical synchronization signal (VD) and the like from the outside, for example, from the processor4, a synchronization signal processing section117which performs predetermined processing for the synchronization signal from the outside received by the signal receiving section116(the vertical synchronization signal (VD) received from the processor4) in a predetermined case, and a timing generator (TG)118which generates its own synchronization signal in the CIS100A and causing its own synchronization signal to follow the external synchronization signal for which the predetermined processing has been performed by the synchronization signal processing section117to supply the synchronization signal to respective circuits as various synchronization signals in the CIS100A.

Furthermore, the CIS100A in the fourth embodiment is configured, being provided with a control parameter transmitting/receiving section141which receives control parameters transmitted from a control section (FPGA)200aarranged in the processor4, a temporary register142which temporarily stores the control parameters received by the control parameter transmitting/receiving section141, and a main register143which stores control parameters and the like to be used for photographing control in the CIS100A.

On the other hand, the processor4A is provided with: a video signal receiving section121which receives a video signal (serial signal) having video data transmitted from the CIS100A, an S/P conversion circuit122which converts the video signal (serial signal) with a synchronization signal superimposed thereon, which has been received by the signal receiving section121, to a parallel signal, a signal processing section123which performs predetermined signal processing for the received video signal and outputs the video signal to the monitor5or the like, a timing generator (TG)125which generates a vertical synchronization signal (VD) for image processing in the processor4A and supplies the vertical synchronization signal (VD) to various circuits, and a synchronization signal transmitting section124which transmits the vertical synchronization signal (VD) in the processor4A supplied from the timing generator (TG)125to the CIS100A, similarly to the first embodiment.

Furthermore, the processor4A is provided with: the control section (FPGA)200aconfigured, for example, by an FPGA, a control parameter transmitting/receiving section211awhich transmits multiple control parameters for controlling the CIS100A, to the CIS100A via the communication line102as well as receiving return data (to be described later in detail) from the CIS100A, the control parameter transmitting/receiving section211abeing configured in the control section (FPGA)200a, a judgment section212awhich judges whether or not the multiple control parameters have been normally transmitted from the processor4A to the CIS100A, on the basis of the return data from the CIS100A, a control section213awhich performs predetermined control for treatment and the like of the multiple control parameters transmitted from the processor4A to the CIS100A, on the basis of a result of the judgment by the judgment section212a, and a memory201which stores information about the multiple control parameters.

Note that, in the present fourth embodiment also, though the control parameter transmitting/receiving section211ais assumed to be configured in the control section (FPGA)200a, another component, the timing generator (TG)125may be configured in the FPGA.

In the present fourth embodiment also, the control section (FPGA)200areads out various setting values of the multiple control parameters from the memory201at the time of startup and transmits the setting values from the control parameter transmitting/receiving section211ain the control section (FPGA)200ato the CIS100A via the integrated coaxial cable101A, for example, on the basis of the I2C interface. Even after startup, corresponding control parameters are transmitted via communication in order to change settings for a photographing mode, a gain setting, an electronic shutter setting, a cutout position setting and the like as necessary.

Furthermore, though the I2C interface is also adopted as a communication system in the present fourth embodiment, the communication system is not limited thereto, and, for example, the SPI interface may be adopted.

Furthermore, since the kinds and the like of the multiple control parameters transmitted in the image pickup system of the present fourth embodiment are similar to those of the first embodiment, and the multiple control parameters are assumed to be treated as a preset set of integrated information, detailed description thereof is omitted here.

Next, operation in the present embodiment will be described.

In the image pickup system of the present fourth embodiment, at the time of or after startup, the control section (FPGA)200areads out various setting values of the multiple control parameters from the memory201in the processor4A and transmits the multiple control parameters from the control parameter transmitting/receiving section211ato the CIS100A via the communication line102in the integrated coaxial cable101A.

In comparison, when receiving the multiple control parameters (for example, communicated contents of a gain setting, an electronic shutter setting and a binning setting) transmitted from the control parameter transmitting/receiving section211ain the control section (FPGA)200a, the control parameter transmitting/receiving section141in the CIS100A temporarily stores the received contents into the temporary register142. Note that the contents stored in the temporary register142is not reflected on operation of the CIS100A.

The control parameter transmitting/receiving section141transmits the contents of the received multiple control parameters to the control parameter transmitting/receiving section211ain the processor4A via the communication line102in the integrated coaxial cable101A. Note that the communicated contents transmitted from the control parameter transmitting/receiving section141to the control parameter transmitting/receiving section211ais called “return data” in the detailed description of the preferred embodiments in the present specification.

Note that, in the present fourth embodiment, a sequence is assumed in which, when receiving the multiple control parameters from the processor4A, the control parameter transmitting/receiving section141temporarily stores the communicated contents into the temporary register142as well as immediately transmitting the communicated contents to the control parameter transmitting/receiving section211aon the processor4A side as the “return data”. However, the sequence is not limited thereto, and a sequence is also possible in which the control parameter transmitting/receiving section141temporarily stores the communicated contents into the temporary register142and does not start transmission of the return data until receiving a request to transmit the “return data” from the processor4A.

When receiving the “return data” from the CIS100A, the control parameter transmitting/receiving section211aof the processor4A transmits the “return data” to the judgment section212a.

The judgment section212acompares the received “return data” with the “transmitted contents of the multiple control parameters” transmitted from the processor4A to the CIS100A previously, and transfers a result of the comparison to the control section213a.

If the judgment result is OK, the control section213adoes not do anything. On the other hand, if the judgment result is NG, the control section213atransmits a control signal to the effect that the “transmitted contents of the multiple control parameters” transmitted last should be discarded, to the CIS100A.

On the other hand, the CIS100A discards data of the “transmitted contents of the multiple control parameters” stored in the temporary register142only in the case of receiving the control signal to the effect that the “transmitted contents of the multiple control parameters” should be discarded.

Note that, though the control signal to the effect that the “transmitted contents of the multiple control parameters” transmitted last should be discarded is transmitted to the CIS100A if the judgment result is NG, in the present fourth embodiment, the operation is not limited thereto. The control parameter transmitting/receiving section141is not necessarily required to explicitly perform the discard operation but is only required to perform such an operation that the communicated contents stored in the temporary register142are not reflected on the main register143.

For example, it is also possible to have a flag indicating whether or not to perform reflection and reflect the data of the temporary register142on the main register143according to the flag. Otherwise, it is also possible to perform control so that, even if the data is reflected, overwriting with harmless data (for example, contents determined to be reflected last) is performed.

Note that, though transmitted contents of control parameters transmitted from the processor4A to the CIS100A and return data from the CIS100A are compared to judge whether the transmitted contents are correct or incorrect in the fourth embodiment, the judgment is not limited thereto, and it is also possible to transmit and receive an error correcting code (for example, a Hamming code or the like) or an error detecting code (a parity bit, a checksum or the like) together with communicated contents of the multiple control parameters and judge whether the communicated contents are correct or incorrect on the basis of the error correcting code or the error detecting code, similarly to the first to third embodiments.

As described above, according to the fourth embodiment, it is possible to provide an image pickup system in which a CMOS image sensor is arranged at a distal end of an insertion section of an endoscope, and preset multiple control parameters required for photographing control are transmitted from a processor side to a CMOS image sensor side, the image pickup system being capable of always performing normal photographing control by treating the control parameters required for photographing control as a set of integrated information, and performing control so that information about the control parameters is reflected on a register in the CMOS image sensor only when all the multiple control parameters have been normally transmitted and contents of the register are not updated when all the multiple control parameters have not been normally transmitted, similarly to the embodiments described above.

Fifth Embodiment

Next, a fifth embodiment of the present invention will be described.

The image pickup system of the fourth embodiment described above compares “return data” with “transmitted contents of multiple control parameters” transmitted previously, and does not do anything if a result of the comparison is OK. The present fifth embodiment is characterized in that, if the comparison result is OK, a permission to reflect data of the temporary register142on the main register143is given from the processor4A to the CIS100A.

Since the other components, operation and advantages are similar to those of the fourth embodiment, detailed description thereof is omitted here.

Sixth Embodiment

Next, a sixth embodiment of the present invention will be described.

The image pickup system of the fourth embodiment described above is provided with the temporary register142and provided with a function as a buffer which temporarily holds multiple control parameters received from the CIS100A. The present sixth embodiment is different from the fourth embodiment in that a function corresponding to the temporary register142which temporarily holds data is not provided.

Note that only parts different from the fourth embodiment will be described here, and description of components similar to those of the fourth embodiments is omitted.

FIG. 8is a block diagram showing a configuration of an electric system in an image pickup system of the sixth embodiment of the present invention.

As shown inFIG. 8, an image pickup system1B provided with an image pickup apparatus according to the sixth embodiment of the present invention is provided with: an endoscope2B provided with an image pickup device (CIS)100B, a light source apparatus to which the endoscope2B is removably connected and which supplies an illumination light to the endoscope2B, a processor4B as a signal processing apparatus to which the endoscope2B is removably connected and which performs predetermined signal processing, and a monitor as a display apparatus which displays an image signal generated by the processor4B as an endoscopic image.

Similarly to the first embodiment, the image pickup device (CIS)100B in the image pickup system1B of the sixth embodiment is configured by a so-called CMOS (complementary metal oxide semiconductor circuit) image sensor arranged at a distal end of an insertion section and connected to the processor4B via an integrated coaxial cable101B inserted through the insertion section and a universal cord.

Similarly to the first and fourth embodiments, the CIS100B is provided with a light receiving element111arranged at an image forming position of the objective lens15, an AFE (analog front end)112which removes noise from a signal outputted from the light receiving element111and digitizes the signal, a synchronization superimposition circuit113which superimposes a synchronization signal on a video signal, which is an output signal of the AFE112, a P/S conversion circuit114for converting the video signal to a serial signal for transmission to output the serial signal to an outside, a video signal transmitting section115for outputting the video signal (serial signal) to the outside, a synchronization signal receiving section116which receives a vertical synchronization signal (VD) and the like from the outside, for example, from the processor4B, a synchronization signal processing section117which performs predetermined processing for the synchronization signal from the outside received by the synchronization signal receiving section116(the vertical synchronization signal (VD) received from the processor4B) in a predetermined case, and a timing generator (TG)118which generates its own synchronization signal in the CIS100B and causing its own synchronization signal to follow the external synchronization signal for which the predetermined processing has been performed by the synchronization signal processing section117to supply the synchronization signal to respective circuits as various synchronization signals in the CIS100A.

Furthermore, the CIS100B in the sixth embodiment is configured, being provided with a control parameter transmitting/receiving section151which receives control parameters transmitted from a control section (FPGA)200barranged in the processor4B, and a register152which stores the control parameters received by the control parameter transmitting/receiving section151as control parameters to be used for photographing control in the CIS100B.

On the other hand, the processor4B is provided with: a video signal receiving section121which receives a video signal (serial signal) having video data transmitted from the CIS100B, an S/P conversion circuit122which converts the video signal (serial signal) with a synchronization signal superimposed thereon, which has been received by the signal receiving section121, to a parallel signal, a signal processing section123which performs predetermined signal processing for the received video signal and outputs the video signal to the monitor5or the like, a timing generator (TG)125which generates a vertical synchronization signal (VD) for image processing in the processor4B and supplies the vertical synchronization signal (VD) to various circuits, and a synchronization signal transmitting section124which transmits the vertical synchronization signal (VD) in the processor4B supplied from the timing generator (TG)125to the CIS100B, similarly to the fourth embodiment.

Furthermore, the processor4B is provided with: the control section (FPGA)200bconfigured, for example, by an FPGA, a control parameter transmitting/receiving section211bwhich transmits multiple control parameters for controlling the CIS100B, to the CIS100B via the communication line102as well as receiving return data from the CIS100B, the control parameter transmitting/receiving section211bbeing configured in the control section (FPGA)200b, a judgment section212bwhich judges whether or not the multiple control parameters have been normally transmitted from the processor4B to the CIS100B, on the basis of the return data from the CIS100B, a control section213bwhich performs predetermined control for treatment and the like of the multiple control parameters transmitted from the processor4B to the CIS100B, on the basis of a result of the judgment by the judgment section212b, and a memory201which stores information about the multiple control parameters.

Next, operation in the present embodiment will be described.

In the image pickup system of the present sixth embodiment, at the time of or after startup, the control section (FPGA)200breads out various setting values of the multiple control parameters from the memory201in the processor4A and transmits the multiple control parameters from the control parameter transmitting/receiving section211bto the CIS101B via the communication line102in the integrated coaxial cable101B.

In comparison, when receiving the multiple control parameters transmitted from the control parameter transmitting/receiving section211bin the control section (FPGA)200b, the control parameter transmitting/receiving section151in the CIS100B immediately reflects contents of the received multiple control parameters on the register152as well as transmitting the contents to the control parameter transmitting/receiving section211bin the processor4B via the communication line102in the integrated coaxial cable101B as return data.

When receiving the “return data” from the CIS100B, the control parameter transmitting/receiving section211bof the processor4B transmits the “return data” to the judgment section212b.

The judgment section212bcompares the received “return data” with the “transmitted contents of the multiple control parameters” transmitted from the processor4B to the CIS100B previously, and transfers a result of the comparison to the control section213b.

If the judgment result is NG, the control section213btransmits “multiple control parameters” with the same contents as the “transmitted contents of the multiple control parameters” transmitted last, to the CIS100B.

Note that, though transmitted contents of control parameters transmitted from the processor4B to the CIS100B and return data from the CIS100B are compared to judge whether the transmitted contents are correct or incorrect in the sixth embodiment also, the judgment is not limited thereto, and it is also possible to transmit and receive an error correcting code (for example, a Hamming code or the like) or an error detecting code (a parity bit, a checksum or the like) together with communicated contents of the multiple control parameters and judge whether the communicated contents are correct or incorrect on the basis of the error correcting code or the error detecting code, similarly to the first to fourth embodiments.

As described above, according to the sixth embodiment, it is possible to provide an image pickup system in which a CMOS image sensor is arranged at a distal end of an insertion section of an endoscope, and preset multiple control parameters required for photographing control are transmitted from a processor side to a CMOS image sensor side, the image pickup system being capable of always performing normal photographing control by treating the control parameters required for photographing control as a set of integrated information, and performing control so that information about the control parameters is reflected on a register in the CMOS image sensor only when all the multiple control parameters have been normally transmitted and contents of the register are not updated when all the multiple control parameters have not been normally transmitted, similarly to the embodiments described above.

Seventh Embodiment

Next, a seventh embodiment of the present invention will be described.

The image pickup system of the sixth embodiment described above compares “return data” with “transmitted contents of multiple control parameters” transmitted previously, and, if a result of the comparison is NG, transmits “multiple control parameters” with the same contents as the “transmitted contents of the multiple control parameters” transmitted last to the CIS100B. The present seventh embodiment is characterized in that, if the comparison result is NG, an instruction to discard the “transmitted contents of the multiple control parameters transmitted last” currently stored in the register152and return the contents to contents before the contents is transmitted from the processor4B to the CIS100B.

Since the other components, operation and advantages are similar to those of the sixth embodiment, detailed description thereof is omitted here.

Eighth Embodiment

Next, an eighth embodiment of the present invention will be described.

FIG. 9is a diagram showing a whole configuration of an image pickup system of the eighth embodiment of the present invention.

The image pickup systems of the first to seventh embodiments described above are configured such that both of the control section (FPGA)200(200a,200b) and the memory201are provided in the processor4(4A,4B). The present eighth embodiment is characterized in that both of a control section (FPGA)300and a memory301corresponding to the control section (FPGA)200(200a,200b) and the memory201, respectively, are provided in the connector16on the endoscope2side.

Since the other components, operation and advantages are similar to the first to seventh embodiments, detailed description thereof is omitted here.

An object of the image pickup system of the invention as claimed in the application concerned is to provide an image pickup system capable of accurately transmitting necessary multiple control parameters, coping with disorder of a transmitted signal due to disturbance influencing a connection cable between a CIS arranged at a distal end of an insertion section of an endoscope and a control section (FPGA) arranged at a position at a relatively long distance from the CIS, and capable of always performing normal photographing control. In addition to the case where the control section (FPGA) communicating with the CIS is arranged in a processor, this problem also applies to the case where the control section (FPGA) is arranged at a connector connecting the endoscope and the processor like the present embodiment.

In the image pickup system of the present eighth embodiment, by the CIS100, the control section (FPGA)300which communicates with the CIS100and the memory301which stores information about multiple control parameters having configurations similar to those of the CIS100(100A,100B), the control section (FPGA)200(200a,200b) and the memory201, respectively, operation and advantages similar to those of the first to seventh embodiments described above are obtained.

Ninth Embodiment

Next, a ninth embodiment of the present invention will be described.

FIG. 10is a diagram showing a whole configuration of an image pickup system of the ninth embodiment of the present invention.

The present ninth embodiment is characterized in that a control section (FPGA)400and a memory401corresponding to the control section (FPGA)200(200a,200b) and the memory201are arranged in an operation section7of an endoscope2and in the connector16on the endoscope2side, respectively, similarly to the eighth embodiment described above.

In the ninth embodiment also, by a CIS100, the control section (FPGA)400which communicates with the CIS100and the memory401which stores information about multiple control parameters having configurations similar to those of the CIS100(100A,100B), the control section (FPGA)200(200a,200b) and the memory201in the first to seventh embodiments described above, respectively, operation and advantages similar to those of the first to seventh embodiments described above are obtained, similarly to the eighth embodiment described above.

Tenth Embodiment

Next, a tenth embodiment of the present invention will be described.

FIG. 11is a diagram showing a whole configuration of an image pickup system of the tenth embodiment of the present invention.

The present tenth embodiment is characterized in that both of a control section (FPGA)500and a memory501corresponding to the control section (FPGA)200(200a,200b) and the memory201, respectively, are arranged in an operation section7of an endoscope2, similarly to the eighth and ninth embodiments described above.

The tenth embodiment is also similar to the embodiments described above in that the CIS100and the control section (FPGA) which communicates with the CIS100are separated from each other by a relatively long distance. Therefore, similarly to the eighth and ninth embodiments, by the CIS100, the control section (FPGA)500which communicates with the CIS100and the memory501which stores information about multiple control parameters having configurations similar to those of the CIS100(100A,100B), the control section (FPGA)200(200a,200b) and the memory201in the first to seventh embodiment described above, respectively, operation and advantages similar to those of the first to seventh embodiments described above, operations and advantages similar to those of the first to seventh embodiments described above are obtained.

Note that, though an image pickup system provided with a CMOS image sensor as an image pickup device which is arranged at a distal end of an insertion section of an endoscope to pick up an image of an object and which is provided with a function of having a register for storing control parameters and the like for photographing control is given as an example, the present invention is not limited thereto and is also applicable to an image pickup system provided with an endoscope with a so-called CCD arranged at the distal end of an insertion section thereof and with a register for storing control parameters and the like to be used for photographing control arranged near the CCD.

Note that the present invention is not immediately limited to each embodiment described above, and components can be modified and embodied at an implementation stage within a range not departing from the spirit of the present invention. Various inventions can be formed by appropriate combination of the multiple components disclosed in each embodiment described above. For example, some components among all the components shown in the embodiments may be deleted. Furthermore, components among different embodiments may be appropriately combined.