Single-mask spacer technique for semiconductor device features

A method for fabricating vertical surround gate structures in semiconductor device arrays. The method includes forming pillars separated by vertical and horizontal trenches on a substrate. Forming a gate layer over the pillars and trenches such that the gate layer forms gate trenches in the horizontal trenches. The method includes forming fillers within the gate trenches, and planarizing the gate layer and fillers. The method also includes successively etching a first portion of the gate layer, removing the fillers, and etching a second portion of the gate layer.

BACKGROUND

This invention relates to the fabrication of semiconductor devices. More particularly, the present invention relates to a method for fabricating vertical surround gate structures in a semiconductor device array.

In semiconductor device applications, conventional planar transistors have the most mature integration process. However, in memory applications, particularly access devices (or selectors), reduction of device footprint is essential to improve memory density. Planar transistor performance is generally restricted by channel width and length. Reducing channel width or length can improve memory density at the cost of degraded device performance.

Thus vertical surround gate devices have become more attractive for such memory applications. In vertical surround gate devices the current flow is oriented in a vertical direction, providing many advantages to area efficiency. However, current reliable integration processes of vertical surround gate devices are relatively complex and expensive. In addition, in many applications, it is desirable to make the processes compatible with standard planar CMOS processes.

BRIEF SUMMARY

An aspect of the invention is a method for fabricating vertical surround gate structures in a semiconductor device array. The method includes forming a plurality of pillars on a substrate such that the pillars are separated by vertical and horizontal trenches. The method also includes forming a gate layer over the pillars and trenches such that the gate layer forms gate trenches in the horizontal trenches. The method includes forming fillers within the gate trenches, and planarizing the gate layer and fillers. The method also includes successively etching a first portion of the gate layer, removing the fillers, and etching a second portion of the gate layer.

Another aspect of the invention is a method for fabricating vertical surround gate structures in a semiconductor device array. The method includes forming a plurality of pillars on a substrate such that the pillars are separated by vertical and horizontal trenches. The method also includes forming a dielectric layer over the pillars and trenches. The method includes forming a metal gate layer over the dielectric layer. The method also includes forming a gate layer over the metal gate layer such that the gate layer forms gate trenches in the horizontal trenches. The method includes forming fillers within the gate trenches, and planarizing the gate layer and fillers. The method also includes successively etching a first portion of the gate layer, removing the fillers, and etching a second portion of the gate layer.

DETAILED DESCRIPTION

The present invention is described with reference to various embodiments of the invention. Throughout the description of the invention, reference is made toFIG. 1throughFIG. 10.

Additionally, relative terms, such as “horizontal”, “vertical”, “top”, “over”, and “down” are employed with respects to other elements in the described embodiments and figures. Such terms are meant only to describe the referenced embodiments. Therefore, the present invention encompasses alternative orientations of the suggested embodiments.

Embodiments of the present invention provide possible methods of fabricating semiconductor device features. An aspect of the present invention provides a method of fabricating a semiconductor device array with vertical surround gate structures.

FIG. 1depicts a top-down view of a semiconductor device array100after gate formation, in accordance to one embodiment of the present invention. The diagram includes cross-section A102and cross-section B104.

The diagrams fromFIG. 2A through 5Dare cross-sectional views of intermediary steps during fabrication of a semiconductor device array100structure, in accordance to one embodiment of the present invention.

FIG. 2Aschematically depicts semiconductor device array100from cross-section A102, after successively forming a first layer204, hard mask layer206, and a vertical mask pattern208over a substrate202. The diagram also depicts a plurality of vertical mask trenches209. In some embodiments, the first layer can be composed of a silicon-nitride (SiN) material.FIG. 2Bdepicts the same step in fabrication asFIG. 2A, from cross-section B104.

FIG. 2Cschematically depicts semiconductor device array100from cross-section A102, after etching exposed portions of the hard mask layer206and removing the vertical mask pattern208.FIG. 2Ddepicts the same step in fabrication asFIG. 2C, from cross-section B104.

FIG. 2Eschematically depicts semiconductor device array100from cross-section A102, after forming a horizontal masking pattern210over the hard mask layer206and a mask spacer212. One skilled in the art would recognize that the mask spacer212can be composed of any number of materials.FIG. 2Fdepicts the same step in fabrication asFIG. 2E, from cross-section B104.FIG. 2Fdepicts a plurality horizontal mask trenches211in the horizontal mask pattern210.

FIG. 3Aschematically depicts semiconductor device array100from cross-section A102, after etching exposed portions of the hard mask layer206and removing the horizontal mask pattern210.FIG. 3Bdepicts the same step in fabrication asFIG. 3A, from cross-section B104.

FIG. 3Cschematically depicts semiconductor device array100from cross-section A102, after etching portions of the first layer204, and the substrate202. The diagram also depicts a plurality of vertical trenches302.FIG. 3Ddepicts the same step in fabrication asFIG. 3C, from cross-section B104.FIG. 3Dalso depicts a plurality of horizontal trenches304.

FIG. 3Eschematically depicts semiconductor device array100from cross-section A102, after removing the hard mask layer206. The diagram depicts a plurality of pillars306.FIG. 3Fdepicts the same step in fabrication asFIG. 3C, from cross-section B104.

FIG. 4Aschematically depicts semiconductor device array100from cross-section A102, after forming a gate layer402over the pillars306and trenches302/304. In some embodiments, the gate layer402is composed of a polycrystalline silicon material.FIG. 4Bdepicts the same step in fabrication asFIG. 4A, from cross-section B104.FIG. 4Balso depicts a plurality of gate trenches404resulting from the gate layer402formation within the horizontal trenches304.

FIG. 4Cschematically depicts semiconductor device array100from cross-section A102, after forming a filler layer406over the gate layer402. In some embodiments, the filler layer is composed of a low temperature silicon-oxide (SiO) or carbon material.FIG. 4Ddepicts the same step in fabrication asFIG. 4C, from cross-section B104. The diagram also depicts the filler layer406filling in the gate trenches404.

FIG. 4Eschematically depicts semiconductor device array100from cross-section A102, after planarization of the filler layer406and gate layer404. The diagram depicts a plurality of exposed top surfaces408of the pillars306.FIG. 4Fdepicts the same step in fabrication asFIG. 4E, from cross-section B104.

FIG. 5Aschematically depicts semiconductor device array100from cross-section A102, after etching a first portion502of the gate layer402.FIG. 5Bdepicts the same step in fabrication asFIG. 5A, from cross-section B104.

FIG. 5Cschematically depicts semiconductor device array100from cross-section A102, after removal of the filler layer406, and etching a second portion504of the gate layer403.FIG. 5Ddepicts the same step in fabrication asFIG. 5C, from cross-section B104. The diagram also depicts the gate trenches404etched to extend through the gate layer402.

The diagrams fromFIG. 6A through 7Dare cross-sectional views of intermediary steps during fabrication of a semiconductor device array600structure, in accordance to one embodiment of the present invention.

FIG. 6Aschematically depicts semiconductor device array600from cross-section A102, after successively forming a dielectric layer602and metal gate layer604over the substrate202. In some embodiments, the dielectric layer602is composed of a material with a high dielectric constant, such as hafnium-oxide (HfO).FIG. 6Bdepicts the same step in fabrication asFIG. 6A, from cross-section B104.

FIG. 6Cschematically depicts semiconductor device array600from cross-section A102, after forming a gate layer402over the metal gate layer604. In this embodiment, the gate layer402fills in the vertical trenches302. In some embodiments, the gate layer402is composed of a polycrystalline silicon material.FIG. 6Ddepicts the same step in fabrication asFIG. 6C, from cross-section B104. The diagram also depicts gate trenches404resulting from the gate layer402formation within the horizontal trenches304.

FIG. 6Eschematically depicts semiconductor device array600from cross-section A102, after forming a filler layer406over the gate layer402. In some embodiments, the filler layer is composed of a low temperature silicon-oxide (SiO) or carbon material.FIG. 6Fdepicts the same step in fabrication asFIG. 6E, from cross-section B104. The diagram also depicts the filler layer406filling in the gate trenches404.

FIG. 7Aschematically depicts semiconductor device array600from cross-section A102, after planarization of the filler layer406, gate layer404, metal gate layer604, and dielectric layer602.FIG. 7Bdepicts the same step in fabrication asFIG. 7A, from cross-section B104.

FIG. 7Cschematically depicts semiconductor device array600from cross-section A102, after etching a first portion502of the gate layer402, metal gate layer604, and dielectric layer602.FIG. 7Ddepicts the same step in fabrication asFIG. 7C, from cross-section B104.

FIG. 7Eschematically depicts semiconductor device array600from cross-section A102, after removal of the filler layer406, and etching a second portion504of the gate layer403, metal gate layer604, and dielectric layer602.FIG. 7Fdepicts the same step in fabrication asFIG. 7E, from cross-section B104. The diagram also depicts the gate trenches404etched to extend through the gate layer402, metal gate layer604, and dielectric layer602.

FIG. 8is a flowchart illustrating an example method for fabricating the plurality of pillars306in accordance to one embodiment of the present invention.FIG. 8will be described with references toFIG. 1throughFIG. 3F. The method begins with forming step802. At forming step602, a first layer204is deposited over the substrate202. After forming step802, the method continues to forming step804. At forming step804, a hard mask layer206is formed over the first layer204. After forming step804, the method continues to forming step806.

At forming step806, a vertical mask pattern208is formed over the hard mask layer206(FIG. 2AandFIG. 2B). After forming step806, the method continues to etching step808. At etching step808, exposed portions of the hard mask layer206are etched and the vertical mask pattern208is removed (FIG. 2CandFIG. 2D). In some embodiments, a reactive ion etch can (RIE) is utilized to etch the hard mask layer206. After etching step808, the method continues to forming step810.

At forming step810, a horizontal mask pattern210is formed over the hard mask layer206and the mask spacer212(FIG. 2EandFIG. 2F). One skilled in the art would recognize that the mask spacer212can be formed with a variety of deposition and etching processes. After forming step810, the method continues to etching step812. At etching step812, exposed portions of the hard mask layer206are etched and the horizontal mask pattern210is removed (FIG. 3AandFIG. 3B). In some embodiments, a RIE process is utilized to etch the hard mask layer206. After etching step812, the method continues to etching step814.

At etching step814, exposed portions of the first layer204and substrate202are etched to form the plurality of pillars306(FIG. 3CandFIG. 3D). In some embodiments, a RIE process is utilized to etch the first layer204and substrate202. After etching step814, the method continues to removing step816. At removing step816, the hard mask layer206is removed from the structure (FIG. 3EandFIG. 3F). After removing step816, the method for fabricating the plurality of pillars306is complete. In some embodiments, a thermal oxidation process is utilized to form a thin oxide layer after removal of the hard mask layer206. In some embodiments, the method proceeds to forming step902or forming step1002.

FIG. 9is a flowchart illustrating an example method for fabricating the vertical surround gate structures, in accordance to one embodiment of the present invention.FIG. 9will be described with references toFIG. 4AthroughFIG. 5D. The method begins with forming step902. At forming step902, the gate layer402is formed over the pillars306and trenches302/304(FIG. 4AandFIG. 4B). After forming step902, the method proceeds to forming step904.

At forming step904, the filler layer406is formed over the gate layer402(FIG. 4CandFIG. 4D). After forming step904, the method continues to planarizing step906. At planarizing step906, the gate layer402and filler layer406are planarized (FIG. 4EandFIG. 4F). One skilled in the art would recognize that planarization can be achieved with a variety of processes, including a chemical mechanical polishing (CMP) process. After planarizing step906, the method continues to etching step908.

At etching step908, the first portion502of the gate layer402is etched (FIG. 5AandFIG. 5B). After etching step908, the method continues to removing step910. At removing step910, the filler layer406is removed. One skilled in the art would recognize that the filler layer may be removed with various different processes, including any number of selective etch processes. After removing step910, the method continues to etching step912. At etching step912, the second portion504of the gate layer402is etched (FIG. 1,FIG. 5C, andFIG. 5D). In some embodiments, the second portion504is etched utilizing a RIE process. After etching step912, the method is complete.

FIG. 10is a flowchart illustrating an example method for fabricating the vertical surround gate structures, in accordance to one embodiment of the present invention.FIG. 10will be described with references toFIG. 6AthroughFIG. 7D. The method begins with forming step1002. At forming step1002, the dielectric layer602is formed over the pillars306and trenches302/304. After forming step1002, the method continues to forming step1004. At forming step1004, the metal gate layer604is formed over the dielectric layer602(FIG. 6AandFIG. 6B). After forming step1004, the method continues to forming step1006.

At forming step1006the gate layer402is formed over the dielectric layer602(FIG. 6CandFIG. 6D). After forming step1006, the method continues to forming step1008. At forming step1008, the filler layer404is formed over the gate layer402(FIG. 6EandFIG. 6F). After forming step1008, the method continues to planarizing step1010. At planarizing step1010, the filler layer406, gate layer402, metal gate layer604, and dielectric layer602are planarized (FIG. 7AandFIG. 7B). After planarizing step1010, the method continues to etching step1012.

At etching step1012, the first portion of the gate layer402, metal gate layer604, and dielectric layer602are etched (FIG. 7CandFIG. 7D). After etching step1012, the method continues to removing step1014. At removing step1014, the filler layer406is removed. One skilled in the art would recognize that the filler layer may be removed with various different processes, including a selective etch. After removing step1014, the method continues to etching step1016. At etching step1016, the second portion504of the gate layer402, metal gate layer604, and dielectric layer602are etched (FIG. 7EandFIG. 7F). In some embodiments, the second portion504is etched utilizing a RIE process. After etching step1016, the method is complete.