Vacuum packaged single crystal silicon device

A method for forming a vibrating micromechanical structure having a single crystal silicon (SCS) micromechanical resonator formed using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anchors, capacitive air gap, isolation trenches, and alignment marks are micromachined in an active layer of the base wafer; the active layer of the resonator wafer is bonded directly to the active layer of the base wafer; the handle and dielectric layers of the resonator wafer are removed; windows are opened in the active layer of the resonator wafer; masking the active layer of the resonator wafer with photoresist; a SCS resonator is machined in the active layer of the resonator wafer using silicon dry etch micromachining technology; and the photoresist is subsequently dry stripped. A patterned SCS cover is bonded to the resonator wafer resulting in hermetically sealed chip scale wafer level vacuum packaged devices.

FIELD OF THE INVENTION

The present invention relates to methods of fabricating micromechanical resonators using Silicon-on-insulator (SOI) wafers, and in particular to methods of fabricating micromechanical resonators using single crystal silicon wafer material.

BACKGROUND OF THE INVENTION

As disclosed by Yoon, et al. in U.S. Pat. No. 6,490,147, “High-Q Micromechanical Device and Method of Tuning Same,” Dec. 3, 2002, which is incorporated herein by reference, and also by Nguyen, et al. in U.S. Pat. No. 6,249,073, “Device Including a Micromechanical Resonator Having an Operating Frequency and Method of Extending Same,” Jun. 19, 2001, which is incorporated herein by reference, vibrating micromechanical resonators formed of polycrystalline silicon, commonly known as polysilicon, are well-known as miniaturized substitutes for crystals in a variety of high-Q oscillator and filtering applications. State of the art micromechanical resonator fabrication techniques utilize polycrystalline silicon for manufacturing micromechanical resonators devices produced by means of silicon sacrificial surface micromachining.

This state of the art method of manufacturing using sacrificial surface micromachining produces polysilicon resonators or other thin film resonators having intrinsic stresses, stress gradients, or both, that effect device performance. These intrinsic stresses and stress gradients are difficult to control during manufacturing. Yet, control of these intrinsic stresses and stress gradients is critical for devices for use in applications that require high repeatability and reproducibility.

This state of the art method of manufacturing using polysilicon also requires removal of a sacrificial layer of material using wet etching techniques that complicate the manufacturing process and generally results in low yield due to difficulty in removing sacrificial material in the small gap between the resonator and the lower electrode. This method of manufacturing using polycrystalline silicon also results in stiction, which further lowers yields.

For devices requiring very small capacitive air gaps, e.g., to compensate for manufacturing tolerances or for tuning or for use as tunable resonator cum filter, the removal of sacrificial layer becomes extremely difficult as liquid or even vapor etching techniques cannot easily penetrate underneath the resonators to create a free standing structures. The removal of etched sacrificial material to form the capacitive gap is a process as well as operation yield limiter for small air gaps on the order of 300 Angstrom or smaller.

Additionally, impurities present in polysilicon thin films degrade device performance and also result in lower resonator Q.

FIGS. 1 and 2present conceptual and perspective view schematics, respectively, of a tunable capacitor10as taught by Yoon, et. al. in U.S. Pat. No. 6,490,147. The capacitor10has a bottom capacitor plate12fixed to a substrate14, and a top capacitor plate16suspended above the bottom plate12. The top capacitor plate16is also anchored to the substrate14. Both plates12and16are constructed of copper (Cu) to minimize their total series resistance in an attempt to maximize the device quality factor, Q.

A dielectric slab18is suspended between the two plates12and16and anchored to the substrate14outside the two plates12and16via spring structures20. This dielectric18is free to move by electrostatic displacement to alter either the overlap between it and the capacitor plates12and16, or the fringing fields between them. In the former case, when a DC bias is applied between the two plates12and16, the charges on the capacitor plates12and16exert an electrostatic force on the induced charges in the dielectric18to pull the dielectric18into the gap between the plates12and16, as shown inFIG. 1. The “waffle” shape of the capacitor10shown inFIG. 2is intended to minimize the travel distance, or the needed voltage, required for a given change in capacitance, and to provide etchant access paths during a step in the fabrication process for removing a thin sacrificial layer by etching.

FIGS. 3A-3Eare side sectional views which illustrate one state of the art fabrication process for producing micromechanical resonators of the type depicted by the capacitor10. The prior art process, as taught by Yoon, et. al. in U.S. Pat. No. 6,490,147, begins inFIG. 3Awith the thermal growth of a 1 micron layer30of SiO2to serve as an isolation or dielectric layer between the eventual metal structures and a silicon wafer or substrate32. Next, the bottom capacitor plate12is formed by first evaporating 300 Angstroms/2000 Angstroms a Cr/Cu seed layer34, then electroplating a 5 micron layer36of copper (Cu). A 3000 Angstrom layer38of nickel (Ni) is then electroplated above the Cu layer36to serve as a buffer layer to prevent Cu contamination of etch chambers during subsequent reactive ion etch (RIE) processes.

FIG. 3Billustrates a first 2000 Angstrom aluminum (Al) sacrificial layer40is evaporated and patterned to form vias through which a subsequent layer PECVD nitride dielectric film42adheres to the underlying Ni layer38. The nitride film42is patterned via RIE to form the movable dielectric plate18, then submerged under 0.9 micron of a second sacrificial Al film44that defines the spacing between the dielectric plate18and the eventual top metal plate16, as shown inFIG. 3C. Due to the valley-like topography between the fingers of the etched dielectric, the deposition of the 0.9 micron layer44of Al actually results in only a 0.3 micron gap between the top plate16and the dielectric18when the two are engaged.

After etching vias through the Al layer44to define top plate anchors (shown inFIG. 3C), as shown inFIG. 3D, the top plate16is formed by first evaporating a thin Cr/Cu seed layer46, then electroplating a Cu layer48through a defining photoresist mold50to a thickness sufficient to insure that the top plate16does not bend under applied actuation voltages. The PR and seed layer under the PR are removed. The two Al sacrificial layers40and44are selectively etched to release the dielectric42using a K3Fe(CN)6/NaOH solution, which attacks Al, but leaves Cu and the nitride dielectric42intact, yielding the final cross-section shown inFIG. 3E. After release, sublimation or a critical point dryer is often used to dry the capacitor10in an attempt to prevent stiction.

Additionally, cleaning and removal of the sacrificial layer is extremely difficult for small gaps, and often requires use of a surfactant.

FIG. 4illustrates a perspective view schematic of a free-free beam, flexural-mode, micromechanical device or resonator52and an electrical pick off scheme, as taught by Nguyen, et al. in U.S. Pat. No. 6,249,073. The device52includes a free-free micromechanical flexural resonator beam54supported at its flexural nodal points56by four torsional beams58, each anchored to a substrate59by rigid contact anchors60. A drive electrode62underneath the free-free resonator beam54allows electrostatic excitation via an applied AC voltage Vi, and output currents are detected directly off a DC-biased (via VP) resonator structure64. The torsional support beams58are designed with quarter-wavelength dimensions, which effect an impedance transformation that isolates the free-free resonator beam54from the rigid anchors60. Ideally, the free-free resonator beam54sees zero-impedance into its supports or beams58, and thus, effectively operates as if levitated without any supports. As a result, anchor dissipation mechanisms normally found in previous clamped-clamped beam resonators are greatly suppressed, allowing much higher device Q. However, multiple drive electrodes may be utilized for push-pull excitation. The electrodes can also be used for sensing, frequency tuning and detection of the output.

Typically, a transducer capacitor gap spacing is entirely determined via a sacrificial surface micromachining process for removing a thin sacrificial oxide layer, and wet etching of the sacrificial layer for final release of the flexural resonator beam54to create the capacitor gap.

FIGS. 5A and 5Billustrate a transducer capacitor gap spacing, as taught by Nguyen, et al. in U.S. Pat. No. 6,249,073, that is not entirely determined via a thin sacrificial oxide, as was done (with difficulty) in previous clamped-clamped beam high frequency devices. Rather, as taught by Nguyen, et al., the capacitor gap66is determined by the height of spacers or dimples68set by a timed etch. The height of the dimples68is such that when a sufficiently large DC-bias VPis applied between the drive electrode62and the resonator beam54, the whole structure comes down and rests upon the dimples68, which are located at the flexural nodal points56. The spacers68are formed either on the resonator beam54or on the substrate59.

As taught by Nguyen, et al. in U.S. Pat. No. 6,249,073, the use of dimples to set the capacitor gap spacings66is intended to permit much thicker sacrificial oxide spacers to be used, thereby alleviating previous problems due to pinholes and non-uniformity in ultra-thin sacrificial layers used when transducer capacitor gap spacing is entirely determined by sacrificial surface micromachining for removing the thin sacrificial oxide. Also, the thicker sacrificial oxide is intended to be easier to remove than previous thinner ones, which is intended to decrease the required HF release etch time and lessen the probability that etching by-products remain in the gap66where they might interfere with resonator operation and Q.

FIGS. 6A,6B and6C illustrate one state of the art fabrication method for producing micromechanical resonators as taught by Nguyen, et al. in U.S. Pat. No. 6,249,073, wherein the device52is fabricated using a five-mask, polycrystalline silicon or “polysilicon,” surface-micromachining technology described by the process flow shown in U.S. Pat. No. 6,249,073. The fabrication sequence taught by Nguyen, et al. begins with isolation layers70and72formed via successive growth and deposition of 2 micron thermal oxide and 2000 Angstrom LPCVD Si3N4, respectively, over a <100> lightly-doped p-type starting silicon wafer74. Next, 3000 Angstroms of LPCVD polysilicon is deposited at 585 degrees C. and phosphorous-doped via implantation, then patterned to form the ground planes64and interconnects. An LPCVD sacrificial oxide layer78is then deposited to a mathematically determined thickness, after which successive masking steps produce dimple and anchor openings80,82. The dimple openings82are defined via a reactive-ion etch which must be precisely controlled. Anchors openings80are simply wet-etched in a solution of buffered hydrofluoric acid (BHF).

Next, inFIG. 6B, structural polysilicon is deposited via LPCVD at 585 degrees C. and phosphorous dopants are introduced via ion-implantation to provide the flexural resonator beam54. A 2000 Angstrom-thick oxide mask is then deposited via LPCVD at 900 degrees C., after which the wafers must be annealed for one hour at 1000 degrees C. in an effort to relieve stress and distribute dopants.

As illustrated inFIG. 6C, wet etching of the sacrificial layer is used for final release of the flexural resonator beam54to create the capacitor gap66. Both the oxide mask and structural layer are patterned via SF6/O2and Cl2-based RIE etches, respectively. The structures54and58are then released via a 5 minute etch in 48.8 wt. % HF. As taught by Nguyen, et al. in U.S. Pat. No. 6,249,073, this 5 minute release etch time is significantly shorter than that required for previous clamped-clamped beam resonators, which is about 1 hour, because they did not benefit from the dimple-activated gap spacings, as taught by Nguyen, et al. The previous clamped-clamped beam resonators require sacrificial oxide thicknesses on the order of hundreds of Angstroms. After structural release by wet etching of the sacrificial layer, aluminum is evaporated and patterned over polysilicon interconnects via lift-off to reduce series resistance.

Thus, state of the art methods of manufacturing using polycrystalline silicon produces resonators having intrinsic stresses, stress gradients, or both, that effect device performance. These state of the art methods of manufacturing using polycrystalline silicon also require removal of a sacrificial layer of material using wet etching techniques that complicate the manufacturing process and generally results in low yield due to difficulty in removing sacrificial material in the small gap between the resonator and the lower electrode. This method of manufacturing using polycrystalline silicon also results in stiction, which further lowers yields, and impurities present in polysilicon thin films degrade device performance and result in lower resonator Q.

Thus, an improved device and method of manufacturing are desirable.

SUMMARY OF THE INVENTION

A method for fabrication of single crystal silicon (SCS) micromechanical resonators using a two-wafer process, including a Silicon-on-Insulator (SOI) or an insulating base wafer and a SOI resonator wafer, wherein resonator anchors, a capacitive air gap, isolation trenches, transmission lines, and alignment marks are micromachined in a single crystal silicon semiconductor material active layer of the base SOI wafer. When practiced using an insulating wafer, such as glass, Pyrex, quartz, or oxided silicon, alignment marks, capacitive air gap, transmission lines, and resonator anchors are fabricated on the insulating wafer using a combination of bulk and surface micromachining and metal deposition and etching. The single crystal silicon semiconductor material active layer of the resonator wafer is bonded directly to the active layer of the base wafer using wafer flat for alignment. The handle and dielectric layers of the resonator wafer are removed. According to one aspect of the invention, viewing windows are opened in the active layer of the resonator wafer to access alignment marks in the active layer of base wafer. Alternatively, alignment is accomplished using a conventional double sided aligner. The SCS semiconductor material active layer of the resonator wafer is masked with photoresist material; and a single crystal silicon resonator is fabricated in the single crystal silicon semiconductor material active layer of the resonator wafer using silicon dry etch micromachining technology, such as reactive ion etching (RIE) or deep reactive ion etching (DRIE). The photoresist material is subsequently removed by dry stripping.

According to one aspect of the invention, alignment for bonding the single crystal silicon (SCS) semiconductor material active layer of the resonator wafer with base wafer is accomplished using only wafer flat alignment of the two or more stacked wafers.

According to another aspect of the invention, alignment for bonding the single crystal silicon (SCS) semiconductor material active layer of the resonator wafer with the base wafer is accomplished using double sided aligner.

According to another aspect of the invention, the resonator beam anchors, capacitive air gap, transmission lines, isolation trenches, and alignment marks are machined in the active layer of the base SOI wafer further using a conventional photolithography masking and dry etching micromachining method.

According to yet another aspect of the invention, the resonator beam anchors, capacitive air gap, transmission lines, isolation trenches, and alignment marks are machined on an insulating substrate, such as Pyrex, glass, quartz, oxidized silicon, or nitride, using etching of the insulating layer and metal deposition to create these features.

According to another aspect of the invention, the two wafers are bonded by fusion bonding, anodic bonding or frit bonding methods.

According to another aspect of the invention, silicon dry etch machining the single crystal silicon resonator beam in the single crystal silicon semiconductor material active layer of the resonator wafer produces a single crystal silicon clamped-clamped resonator beam.

According to another aspect of the invention, silicon dry etch machining the single crystal silicon resonator beam in the single crystal silicon semiconductor material active layer of the resonator wafer produces a single crystal silicon clamped-free resonator beam.

According to another aspect of the invention, silicon dry etch machining the single crystal silicon resonator beam in the single crystal silicon semiconductor material active layer of the resonator wafer produces a single crystal silicon free-free resonator beam.

According to another aspect of the invention, silicon dry etch machining the single crystal silicon resonator beam in the single crystal silicon semiconductor material active layer of the resonator wafer produces a single crystal silicon membrane or disk.

According to another aspect of the invention, the single crystal silicon clamped-clamped resonator beam is an interconnected dual resonator that is structured to form a filter device.

According to one aspect of the invention, the single crystal silicon wafer mechanical resonator is structured as a clamped-clamped interconnected dual beam resonator for operation as filter.

According to one aspect of the invention, the single crystal silicon wafer mechanical resonator is structured as a clamped-free interconnected dual beam resonator for operation as filter.

According to one aspect of the invention, the single crystal silicon wafer mechanical resonator is structured as a free-free interconnected dual beam resonator for operation as filter.

According to one aspect of the invention, the single crystal silicon wafer mechanical resonator is structured as a one disk or multidisk interconnected resonator for operation as filter.

According to other aspects of the invention, an improved micromechanical resonator structured of single crystal silicon wafer material is provided using the method of the present invention.

According to yet another aspect of the invention, a method is provided for forming a hermetically sealed vibrating micromechanical structure using the vibrating micromechanical structure of the invention, the method including, in a single crystal silicon semiconductor material cover wafer having substantially planar and spaced apart top and bottom surfaces, forming a cover by etching a plurality of access holes through the cover wafer between the spaced apart top and bottom cover wafer surfaces; etching a pattern of frit trenches in the cover wafer bottom surface, the pattern including one or more frit trenches surrounding each of the access holes and one or more frit trenches completely surrounding an interior area of the wafer bottom surface; oxidizing the top and bottom cover surfaces; screen printing frit bonding material in the frit trenches; in a chamber enclosing a vacuum or other controlled atmosphere, frit bonding the cover with a micromechanical resonator device of the invention, the micromechanical resonator device having a resonator etched in a single crystal silicon semiconductor material active layer of a Silicon-On-Insulator resonator wafer and further comprising a base wafer coupled to the single crystal silicon resonator, with the cover being joined to the active layer of the resonator wafer with the one or more flit trenches that surround the interior area of the wafer bottom surface being positioned to completely surround the resonator, and with the access holes being aligned with contact pads formed on the active layer of the resonator wafer.

According to another aspect of the invention, the method also includes, in the interior area of the wafer bottom surface, etching a clearance recess corresponding to the device resonator. Additionally, the method of the invention optionally includes depositing a “getter” material within the device, for example, in the clearance recess.

According to another aspect of the invention, the method also includes etching electrically conductive paths through an oxidation layer formed by the oxidizing in the top and bottom cover surfaces.

According to another aspect of the invention, the method also includes, in one or more of the access holes, forming an electrically conductive path between the corresponding contact pad on the resonator wafer and a contact pad formed on the top surface of the cover wafer.

According to another aspect of the invention the electrically conductive path between the contact pad on resonator wafer and contact pad formed on the top surface of cover wafer can be formed be depositing metal such as gold or aluminum through an aperture mask or stencil mask.

According to another aspect of the invention the cover wafer may be thinned to a desired thickness to provide an electrically conductive path between the contact pad on resonator wafer by direct wire bonding.

According to another aspect of the invention, the method also includes, after frit bonding of cover with a micromechanical resonator device, dicing the resonator device and cover wafer as a packaged and hermetically sealed micromechanical resonator device.

These and other features and advantages of the invention will appear from the following description in which the preferred embodiment has been set forth in detail in conjunction with the accompanying drawings.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

In the Figures, like numerals indicate like elements.

The present invention is an apparatus and method for fabrication of micromechanical resonators using a two-wafer process, including a Silicon-on-Insulator (SOI) base wafer and a SOI resonator wafer, or alternatively an insulating base wafer and a single crystal silicon (SCS) or SOI resonator wafer.

FIG. 7is a cross-sectional view that illustrates the architecture of a micromechanical resonator device100of the present invention formed of a SOI base plate102formed in a SOI base wafer104and a single crystal silicon micromechanical resonator106formed in a SOI resonator wafer108(shown in subsequent Figures and described below). The SOI base and resonator wafers are a type that is generally commercially available. The SOI base wafer element104includes a buried dielectric layer110having a typical thickness of from about 0.5 to 2.0 microns that is sandwiched between relatively thicker “handle” and “active” layers112,114both of single crystal silicon (SCS) semiconductor material.

The resonator106is positioned above a capacitive air gap116in which the resonator106moves out of plane. The single crystal silicon resonator106is direct or fusion bonded at either end118,120directly to single crystal silicon anchors122,124formed in the active layer114of the base wafer104, whereby it is coupled to the base plate102at both ends to provide a resonator of the clamped-clamped type. As was known in the prior art, such clamped-clamped type resonators achieve both small mass and high stiffness with relative ease. This is paramount for communications-grade resonators, since stiffness directly influences the dynamic range of circuits utilizing such resonators.

According to one embodiment of the invention, when the base wafer104is a SOI wafer, the resonator106is direct or fusion bonded to the SCS anchors122,124. Alternatively, the resonator106is frit bonded to the SCS anchors122,124of the SOI base wafer104.

According to another embodiment of the invention, when the base wafer104is an insulating substrate of the type described herein, the resonator106is anodic or frit bonded to the anchors122,124.

Single crystal silicon (SCS) semiconductor material for resonator106is a superior structural material for microresonators compared to polycrystalline films such as polysilicon and others due to lower internal friction and consequently higher mechanical Q, lower internal stress and an independence from various process parameters exhibited by polycrystalline silicon semiconductor material.

FIG. 8is a cross-sectional view of the SOI base wafer104having the buried dielectric layer110sandwiched between relatively thicker SCS semiconductor material handle and active layers112,114whereof the SOI base plate102is formed.

FIG. 9is a cross-sectional view of the SOI base plate102and illustrates the alignment marks132created by photolithography and etching of SCS active layer114. The alignment marks132are used for reference alignments on active layer114, and for later alignment of the SOI resonator wafer108. A capacitive air gap116is also formed in the active layer114of the SOI base wafer104. This forming the capacitive air gap116in the active layer114is in direct contrast to prior art clamped-clamped, clamped-free, and free-free beam high frequency devices wherein the transducer capacitor gap spacing was determined by removal of a thin sacrificial layer. The active layer114is machined using, by example and without limitation, conventional photolithography masking and wet etching technology. Alternatively, the active layer114is machined using dry etching processes, such as either RIE (Reactive Ion Etch) or DRIE (Deep Reactive Ion Etch) processes. Such processes include, for example, the deep trench dry silicon etching processes commercially known as “BOSCH” and “ALCATEL” RIE and DRIE processes both obtain substantially vertical sidewalls of the etched features without concern for the crystallographic orientation of the etched substrate, whereby a more compact MEMS device results, which in turn enables more devices to be fabricated per wafer to produce a significant cost advantage.

By example and without limitation, the active layer114is machined using a silicon nitride deposition over which a photolithographic pattern is formed using photoresist masking material, followed by etching of the silicon nitride and stripping of the photoresist to create a silicon nitride mask over the active layer114with trenches forming the mask pattern. Silicon oxide is grown via thermal oxidation in the trenches. A silicon oxide/silicon nitride etch is performed to create the air gap116as a recess of very precise depth in the base plate active layer114. The precision of the recess that forms the air gap116is more precise than using photoresist as sacrificial material. As contrasted with prior art wet etching methods, the method of the present invention is able to provide precise and very small capacitor air gaps116because the spacing is controlled by oxidation only, rather than wet etching of a photoresist. The depth of the air gap116is a function of design and performance parameters that are particular to the application. Precisely recessed air gaps116in the order of few Angstroms can be achieved using this technique. According to one embodiment of the present invention, the thermal oxidation and subsequent etching is used to create a recess of about 300 Å in the base plate active layer114.

FIG. 10is another cross-sectional view of the SOI base plate102and illustrates micromachining of the active layer114of semiconductor material of the SOI base wafer element104, whereby mechanism features are formed. For example, the resonator anchors122,124are formed for supporting the resonator106relative to the air gap116, and transmission lines126are also formed in a pattern structured to cooperate with the resonator106. One or more isolation trenches128,130are formed that reach to the buried dielectric layer110for electrically isolating the different anchors122,124and RF transmission lines126of the mechanism features. The anchors122,124, transmission lines126, and isolation trenches128,130are formed by patterning of these features using photoresist mask material patterned by photolithography, which is followed by a silicon etch, such as RIE or DRIE, stopping at the buried oxide dielectric layer110in the SOI base wafer104. The photoresist mask material is then removed and the resulting SOI base plate102is cleaned.

FIG. 11is a side view of the SOI base wafer104fusion bonded with the SOI resonator wafer108and placed. The SOI resonator wafer element108includes a buried dielectric layer140having a thickness of from about 0.4 or thinner to about 2.0 microns that is sandwiched between relatively thicker “active” and “handle” layers142,144both of semiconductor material.

In an as yet unpatterned state, the SOI resonator wafer108is flipped vertically and, having the active layer142facing the active layer114of the SOI base wafer104having the resonator anchor features122,124separated by the capacitive air gap feature116, the RF transmission line features126, isolation trench features128,130and alignment marks feature132. The unpatterned and flipped SOI resonator wafer108is flat aligned with the SOI base wafer104using major or minor flats of both wafers. The SOI resonator wafer108requires flat alignment only because it is as yet unpatterned so that the precision alignment required of prior art methods is not necessary.

FIG. 12is a cross-sectional view of the micromechanical resonator device100of the present invention having the SOI resonator wafer108micromachined to develop the micromechanical silicon resonator106and supplemental operational features as may be required. The handle layer144and internal oxide dielectric layer140are stripped from the active layer142of the SOI resonator wafer element108. According to one embodiment of the invention, using photolithography and silicon etching, one or more windows148are etched to open access to alignment marks132on active layer114of base wafer104. The windows148are larger than the alignment marks132and in alignment therewith. The alignment marks132are used for subsequent photolithography alignment steps for SOI resonator wafer active layer142.

While alignment windows result in better alignment accuracy, alignment is optionally accomplish by another method. Alternatively, for example, alignment marks132' are formed in the backside149of the SOI base plate102and used for front to back alignment.

Next steps include phosphorous doping of the active layer142at selected locations. This is followed by metal deposition of metal such as gold or aluminum on active layer142to create contact pads150for signal lines and at least one ground connection. Next steps include metal deposition on backside149of base wafer104to create a gold or aluminum ground contact pad151for grounding of the SOI base plate102. Contact pad151on backside of base wafer104is optionally provided by a conventional blanket metal deposition step. In practice, the ground contact pad151and the ground line of contact pads150are connected to prevent floating grounds.

Using the viewing windows148to align relative to the alignment marks132on the SOI resonator wafer element108, or another alignment method, the active layer142is patterned with photoresist masking material by photolithography. Accordingly, the requirement in prior art methods for a precise fusion bond alignment is eliminated. The active layer142is silicon dry etched using either RIE or DRIE machining to define the single crystal silicon resonator106in the active layer142. Thus, in contrast to prior art methods of releasing the resonator, the present invention does not require a wet etch release because a sacrificial layer is not being removed to release the silicon resonator106of the invention. The photoresist masking material is dry stripped, whereupon the micromechanical resonator device100is free.

When joined by fusion or direct bonding, the interface146couples the single crystal silicon resonator106to the single crystal silicon anchor features122,124of the SOI base plate102. Thus, according to any embodiment of the invention, the resonator106is formed of single crystal silicon. Accordingly, several advantages over the prior art are realized by the invention. The device resonator106is a single crystal silicon. As contrasted with the polysilicon resonators of the prior art, the single crystal resonator106results in higher Q and has none of the impurities present in polycrystalline silicon or “polysilicon” thin films or other material thin films to degrade device performance. The use of single crystal silicon for the resonator106also eliminates both the intrinsic stresses and the stress gradients that effect performance of prior art devices based upon polycrystalline silicon resonators, which is a critical attribute for devices used in applications that require high repeatability and reproducibility. The dry etch release of the resonator106and complementary dry stripping of the photoresist masking material eliminate the prior art methods of sacrificial surface wet etch micromachining that complicate the prior art manufacturing process and generally results in low yield because of the difficulty in removing the sacrificial material in the small gap between the resonator and the lower electrode and results in stiction or adhesion, which further lowers yields. Rather, in contrast to the prior art methods, forming the capacitive air gap116in the active layer114of the base wafer104results in precise depth control and very small capacitor air gaps116. Micromachining of the resonator106with the active layer142of the flipped SOI resonator wafer108in place on the base plate102eliminates the precise fusion bond alignment necessary, and replaces it with the simpler flat alignment only visually through the viewing windows148.

According to embodiments of the invention wherein the base wafer104is a single crystal silicon SOI wafer, which results in single crystal silicon anchors122,124that are more rigid than anchors known in the prior art. When joined by fusion bonding, the interface146couples the resonator106into a single crystal silicon with the anchor features122,124of the SOI base plate102. Thus, according to this fusion bonded embodiment of the invention, the resonator106and anchors122,124are joined in an integrated unit formed of uniform single crystal silicon. Accordingly, additional advantages over the prior art are realized by this fusion bonded embodiment of the invention. The device resonator106is integral with the supporting anchors122,124so that the interface stresses of the prior art devices arising from material and thermal expansion coefficient differences are eliminated. Thus, as contrasted with the polysilicon resonator beams of the prior art, the integral single crystal resonator106and supporting anchors122,124of the present invention eliminates the thermal gradients and intrinsic stresses at the interface of the polycrystalline silicon resonator and the underlying silicon support anchors that occur in prior art devices and degrade device performance.

FIG. 13is a plan view of a portion of one exemplary device100of the present invention having a single crystal silicon resonator106embodied as a clamped-clamped dual beam resonator having first and second single crystal silicon resonator beams152,154connected with a coupling beam156to form a filter device. According to the method of the present invention, the first and second resonator beams152,154are coupled to the single crystal silicon support anchors122,124of the SOI base plate102by either fusion, anodic or eutectic bonding, whereby the device100is able to simultaneously achieve high-Q and high stiffness, which is paramount for communications-grade resonators.

Alternatively, the single crystal silicon resonator106is embodied as a single crystal silicon clamped-free resonator beam, a free-free resonator beam, or a single crystal silicon membrane or disk.

According to one embodiment of the present invention, the clamped-clamped resonator106is an interconnected dual resonator that is structured for operation as a filter device.

According to a different embodiment of the present invention, the single crystal silicon wafer mechanical resonator106is structured as a clamped-free interconnected dual beam resonator that is structured for operation as a filter device.

Alternatively, the single crystal silicon wafer mechanical resonator106is structured as a free-free interconnected dual beam resonator that is structured for operation as a filter device.

Alternatively, the single crystal silicon wafer mechanical resonator106is structured as a single disk or multidisk interconnected resonator that is structured for operation as a filter device.

According to different embodiments of the present invention, the active layer142of the SOI resonator wafer108is fusion bonded to the active layer114of the SOI base wafer element104into a single substrate that is micromachined to produce the resonator106, by example and without limitation the first and second single crystal silicon resonator beams152,154, which are integral with the single crystal silicon support anchors122,124of the SOI base plate102. The resulting device100provides all the advantages over the prior art of a single crystal silicon resonator, and also provides the added advantages inherent in forming the resonator beams152,154and support anchors122,124of a single integrated substrate.

According to different embodiments of the present invention, the base wafer104is an insulating wafer-type substrate, wherein the air gap116and alignment marks132,132′ are etched via bulk micro aching using wet and/or dry etching techniques in the insulating substrate. Transmission lines are formed using metal deposition in etched cavities on the substrate, for example, via E-beam metal deposition or sputtering. The glass or insulating wafer-type substrate is optionally bonded to the beam SOI wafer108using anodic or frit bonding. Such embodiments also result in the resonator106being of single crystal silicon, whereby the advantages discussed herein are realized.

FIG. 14illustrates vacuum packaging of micromechanical resonator device100of the present invention whereby the packaging operation is accomplished on the chip via wafer level processing, which results in lower fabrication costs and improved performance over prior art devices. Accordingly, the present invention provides a hermetically sealed vacuum packaged micromechanical resonator device200including the micromechanical resonator device100of the present invention formed of single crystal silicon (SCS) and sealed with a cover212also formed of single crystal silicon to protect the micromechanical resonator106.

In a cover wafer element214of single crystal silicon (SCS) semiconductor material, or other materials including but not limited to polycrystalline silicon, glasses, including low expansion borosilicate glass, and quartz, a trench216is etched as a recess for clearance of the resonator106of resonator device100. Optionally, one or more additional trenches218are etched in a bottom surface220the cover wafer element214for later screen printing of frit222for bonding to the active layer142of the device SOI resonator wafer element108. The frit trenches218are provided in a bonding pattern217that is configured to surround and isolate an interior area224of the wafer bottom surface220corresponding to the resonator106. The bonding pattern217of optional frit trenches218is also configured to surround areas226of the wafer bottom surface220corresponding to the contact pads150to isolate the contact pads150after sealing. Alternatively, bonding to the active layer142is accomplished by any conventional bonding method, including but not limited to direct or fusion bonding and low temperature bonding processes of the same, anodic and eutectic bonding, whereby the frit trenches218and screen printed frit222are eliminated. Different bonding methods are appropriate when the cover wafer element214is formed of different materials. Fusion or direct bonding requires surfaces to be single crystal silicon; any oxide, nitride or particulate will prevent fusion bonding. Anodic bonding is appropriate between silicon and low expansion borosilicate glass, such as Pyrex®. Eutectic and frit bonding can be practiced between any two surfaces without constraints such as SCS, silicon or glass.

The resonator clearance trench216and optional frit trenches218, when present, are etched using one of the commercially known silicon etching processes discussed herein, such as RIE or DRIE, or one of the conventional wet etching techniques, such as anistropically etching in a suitable etchant, such as potassium hydroxide (KOH).

Access holes228are anisotropically etched through the cover wafer element214in a pattern that is configured to expose the contact pads150on the active layer142. Alternatively access holes228are etched using one of the commercially known silicon etching processes such as RIE or DRIE. Access holes228are sized to be smaller than the area of the corresponding contact pads150on the device active layer142such that the access holes228are sealed by the contact pads150upon mating the cover212with the device active layer142. Access holes228are typically smaller than contact pads to allow hermetic sealing and to provide a well isolated electrical connection.

After fabrication of access holes228, the cover wafer element214is oxidized to form a oxidation layer230on the cover wafer bottom surface220and an opposing top surface232for electrical isolation of the cover212. Ground contacts234are then etched through the oxidation layer230on the opposing top and bottom surfaces232,220of the cover wafer214to form electrically conductive paths for grounding the cover212.

In an alternative embodiment having the cover212formed in a cover wafer element214of insulating substrate material, such as glass and quartz, the oxidation layer230on the opposing top and bottom surfaces232,220of the cover wafer214is eliminated.

Now being ready for installation, bottom surface220of the cover212is screen printed with the bonding frit material222in the pattern of frit trenches218previously etched in a configuration determined to cooperate with the active layer142for sealing the micromechanical resonator106and isolating the contact pads150after sealing. Else, the bonding pattern217is prepared in the bottom surface220the cover wafer element214for another conventional bonding method, including but not limited to direct or fusion bonding and low temperature bonding processes of the same, anodic and eutectic bonding. The bonding pattern217is prepared in a configuration that surrounds and isolates the interior area224of the wafer bottom surface220corresponding to the resonator106. The bonding pattern217also surrounds the areas226of the wafer bottom surface220corresponding to the contact pads150to isolate the contact pads150after sealing. A film of “getter” metal236is deposited nearby the SCS micromechanical resonator106formed in the active layer142of the device SOI resonator wafer element108. The getter metal236is a metal or metal alloy that can absorb gases or particulates that are released during the subsequent bonding process during fabrication or during device operation. In this example, the getter metal236is deposited in the clearance recess216.

In a chamber238, such as a glove box or bonding chamber, enclosing a vacuum or another controlled atmosphere240, the device100of the invention is sealed by frit bonding the cover212with the device SOI resonator wafer element108, which protects the micromechanical resonator106formed in the active layer142. Else, as discussed above, bonding the cover212to the active layer142is alternatively accomplished at least in the bonding pattern217according to any conventional bonding method, including but not limited to direct or fusion bonding and low temperature bonding processes of the same, anodic and eutectic bonding. Sealing in the vacuum chamber238ensures that an appropriately high vacuum is sealed within the etched cavities, including the capacitive air gap116, isolation trenches128,130alignment marks132, windows148, getter trench216, and any volume of the frit trenches218, when present, unfilled by the frit222.

The contact pads150on the top surface242of the device active layer142are exposed through alignment with the access holes228. Metal, such as gold or aluminum, is deposited through an aperture mask or a stencil type mask by a conventional metal deposition process to form electrically conductive paths or metal traces244through the access holes228between the device contact pads150and contact pads246formed on the top surface232of the cover212. The traces244and contact pads246make electrical contact with electrodes, RF lines, and ground path of the device100through the device contact pads150.

The base and resonator wafers104,108joined with the cover wafer214are diced along dicing streets248to separate the hermetically sealed packaged micromechanical SCS resonator device200from other similarly hermetically sealed packaged devices200a-200n(shown in phantom). The present invention thus provides a packaged device200formed of single crystal silicon (SCS) semiconductor material that is unknown in the prior art.

In an alternative embodiment wherein the cover wafer element214is formed of a material other than single crystal silicon (SCS) semiconductor material, such as but not limited to glass, borosilicate, and quartz, the cover212is optionally sealed to the active layer142of the device100in the bonding pattern217according to any conventional bonding method, including but not limited to anodic and eutectic bonding.

FIG. 15illustrates the hermetically sealed vacuum packaged micromechanical resonator device200of the invention including the micromechanical resonator device100of the invention formed of single crystal silicon (SCS) and sealed with a cover212also formed of single crystal silicon to protect the micromechanical resonator106. Here, cover wafer212is thinned either before or after bonding by removing material of one or both of the top and bottom surfaces232,220using any convenient method, including but not limited to grinding, sandblasting, wet etching or dry etching, to reduce the thickness of cover wafer212such that any standard wire bonding station may be used to directly make wire bonding connections250through the access hole228to the electrical contact150of the device100of the invention. Accordingly, the traces244and associated contact pads246are eliminated from the cover212.

Furthermore, the access holes228are optionally formed any convenient micromachining method, including but not limited to drilling, dicing, sandblasting, dry or wet etching.