Semiconductor device, electronic component, and electronic device

A semiconductor device includes a configuration memory that has functions of holding configuration data and generating a signal based on the configuration data, a context generator that has a function of generating a signal for controlling context switch, a clock generator that has a function of operating in a first mode or a second mode in accordance with the signal generated in the configuration memory, and a PLD. A clock signal is input to the context generator and the clock generator. The clock generator outputs the clock signal to the PLD in the first mode and stops outputting the clock signal to the PLD in the second mode.

TECHNICAL FIELD

One embodiment of the present invention relates to a semiconductor device.

In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are embodiments of semiconductor devices. In some cases, a memory device, a display device, an imaging device, or an electronic device includes a semiconductor device.

BACKGROUND ART

A programmable logic device (PLD) includes a plurality of programmable logic elements (PLEs) and a plurality of programmable switch elements (PSEs). In the PLD, data on a function of each PLE and data on connections between the PLEs by PSEs are stored as configuration data in a configuration memory. In other words, the PLD stores its circuit configuration as configuration data.

A multi-context reconfigurable device is suggested (e.g., Non-Patent Document 1). In the multi-context reconfigurable device, the circuit configuration of a PLD is changed by storing a plurality of sets of configuration data in the PLD and changing configuration data to be used. Configuration data representing a circuit configuration is referred to as context. Furthermore, switching of the circuit configuration of a PLD is referred to as context switch.

REFERENCE

DISCLOSURE OF INVENTION

Since one clock cycle with respect to time required for context switch becomes shorter as a clock frequency becomes higher, context switch is not completed in one clock period. In that case, the output data of a flip-flop included in a PLD is processed during the context switch, or with incomplete a circuit configuration that is not included in a configuration data set. As a result, data not intended by a user is generated, in which case data transfer between before and after context switch cannot be performed normally. Furthermore, in the case of an incomplete circuit in which a high-potential output signal and a low-potential output signal are supplied to the same node, shoot-through current might be generated, which leads to an increase in power consumption.

Thus, an object of one embodiment of the present invention is to provide a semiconductor device in which data transfer between before and after context switch can be performed normally even at a high clock frequency. Another object is to provide a semiconductor device in which generation of shoot-through current can be suppressed.

Another object of one embodiment of the present invention is to provide a semiconductor device that is suitable for high-speed operation. Another object is to provide a highly reliable semiconductor device. Another object is to provide a semiconductor device with reduced power consumption. Another object is to provide a semiconductor device including a transistor with a low off-state current. Another object is to provide a semiconductor device that can be used in a wide temperature range.

Another object of one embodiment of the present invention is to provide a novel semiconductor device, a novel electronic device, and the like.

Note that the objects of one embodiment of the present invention are not limited to the above objects. The objects described above do not preclude the existence of other objects. The other objects are the ones that are not described above and will be described below. The other objects will be apparent from and can be derived from the description of the specification, the drawings, and the like by those skilled in the art. One embodiment of the present invention solves at least one of the above objects and the other objects.

One embodiment of the present invention is a semiconductor device including a configuration memory, a first circuit, a second circuit, and a third circuit. The configuration memory is configured to retain configuration data. The configuration memory is configured to generate a first signal corresponding to the configuration data. A second signal is input to the first circuit and the second circuit. The first circuit is configured to generate a third signal and a fourth signal and output the third signal and the fourth signal to the configuration memory and the third circuit. The second circuit is configured to operate in a first mode or a second mode in accordance with the first signal. The second circuit outputs a fifth signal to the third circuit in the first mode and stops outputting the fifth signal to the third circuit in the second mode. The third circuit serves as a programmable logic circuit. The second signal serves as a clock signal that determines operation timing of the first circuit and the second circuit. The third signal and the fourth signal serve as signals for context switch. The fifth signal serves as a clock signal that determines operation timing of the third circuit.

The second circuit may be configured to perform switching from the first mode to the second mode after one of a potential of the third signal and a potential of the fourth signal starts to be changed from a low potential to a high potential and then to stop outputting the fifth signal for one clock to perform switching from the second mode to the first mode.

One embodiment of the present invention is a semiconductor device including first to m-th configuration memories, where m is an integer of 2 or more, a first circuit, a second circuit, and a third circuit. The first to m-th configuration memories are each configured to retain configuration data. The first to m-th configuration memories are configured to generate first to m-th digital signals each of which corresponds to the configuration data retained in a corresponding configuration memory. A first signal is input to the first circuit and the second circuit. The first circuit is configured to generate a second signal and a third signal and output the second signal and the third signal to the first to m-th configuration memories and the third circuit. The second circuit is configured to operate in a first mode or a second mode in accordance with the first to m-th digital signals. The second circuit outputs a fourth signal to the third circuit in the first mode and stops outputting the fourth signal to the third circuit in the second mode. The third circuit serves as a programmable logic circuit. The first signal serves as a clock signal that determines operation timing of the first circuit and the second circuit. The second signal and the third signal serve as signals for context switch. The fourth signal serves as a clock signal that determines operation timing of the third circuit.

The second circuit may be configured to generate binary integer data from the first to m-th digital signals in the second mode. The second circuit may be configured to perform switching from the first mode to the second mode after one of a potential of the second signal and a potential of the third signal starts to be changed from a low potential to a high potential and to perform switching from the second mode to the first mode after stopping outputting the fourth signal for clocks whose number is the integer.

The second circuit may be configured to perform switching to the second mode when a potential of one of the first to m-th digital signals becomes high.

Another embodiment of the present invention is an electronic component including the semiconductor device of one embodiment of the present invention and a lead electrically connected to the semiconductor device.

Another embodiment of the present invention is an electronic device including the electronic component of one embodiment of the present invention and at least one of a display device, a touch panel, a microphone, a speaker, an operation key, and a housing.

One embodiment of the present invention can provide a semiconductor device in which data transfer between before and after context switch can be performed normally even at a high clock frequency, or a semiconductor device in which generation of shoot-through current can be suppressed.

One embodiment of the present invention can provide a semiconductor device that is suitable for high-speed operation, a highly reliable semiconductor device, a semiconductor device with reduced power consumption, a semiconductor device including a transistor with a low off-state current, or a semiconductor device that can be used in a wide temperature range.

One embodiment of the present invention can provide a novel semiconductor device, a novel electronic device, and the like.

Note that the effects of one embodiment of the present invention are not limited to the above effects. The effects described above do not preclude the existence of other effects. The other effects are the ones that are not described above and will be described below. The other effects will be apparent from and can be derived from the description of the specification, the drawings, and the like by those skilled in the art. One embodiment of the present invention has at least one of the above effects and the other effects. Therefore, one embodiment of the present invention does not have the effects described above in some cases.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments will be described in detail with reference to the drawings. Note that the present invention is not limited to the following description, and it will be readily appreciated by those skilled in the art that modes and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated in some cases. In some cases, the same components are denoted by different hatching patterns in different drawings, or the hatching patterns are omitted.

In this specification and the like, a transistor is an element having at least three terminals of a gate, a drain, and a source. The transistor has a channel region between a drain (a drain terminal, a drain region, or a drain electrode) and a source (a source terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source.

Here, since the source and the drain are interchangeable depending on a structure, operating conditions, or the like of the transistor, it is difficult to define which is a source or a drain. Thus, the terms “source” and “drain” can be interchanged with each other depending on the situation or circumstances.

In this specification and the like, an explicit description “X and Y are connected” means that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected. Accordingly, without being limited to a predetermined connection relation, for example, a connection relation shown in drawings or texts, another connection relation is regarded as being included in the drawings or the texts.

Here, X and Y each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

Examples of the case where X and Y are directly connected include the case where an element that allows electrical connection between X and Y (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, or a load) is not connected between X and Y, and the case where X and Y are connected without an element that allows electrical connection between X and Y provided therebetween.

Note that in this specification and the like, an explicit description “X and Y are electrically connected” means that X and Y are electrically connected (i.e., X and Y are connected with another element or circuit provided therebetween), X and Y are functionally connected (i.e., X and Y are functionally connected with another element or circuit provided therebetween), and X and Y are directly connected (i.e., X and Y are connected without another element or circuit provided therebetween). That is, in this specification and the like, the term “electrically connected” is substantially the same as the term “connected.”

For example, any of the following expressions can be used for the case where a source (or a first terminal or the like) of a transistor is electrically connected to X through (or not through) Z1and a drain (or a second terminal or the like) of the transistor is electrically connected to Y through (or not through) Z2, or the case where a source (or a first terminal or the like) of a transistor is directly connected to one part of Z1and another part of Z1is directly connected to X while a drain (or a second terminal or the like) of the transistor is directly connected to one part of Z2and another part of Z2is directly connected to Y.

Examples of the expressions include “X, Y, and a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor are electrically connected to each other, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are electrically connected in this order,” “a source (or a first terminal or the like) of a transistor is electrically connected to X, a drain (or a second terminal or the like) of the transistor is electrically connected to Y, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are electrically connected in this order,” and “X is electrically connected to Y through a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are provided to be connected in this order.” When the connection order in a circuit configuration is defined by an expression similar to the above examples, a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor can be distinguished from each other to specify the technical scope.

Other examples of the expressions include “a source (or a first terminal or the like) of a transistor is electrically connected to X through at least a first connection path, the first connection path does not include a second connection path, the second connection path is a path between the source (or the first terminal or the like) of the transistor and a drain (or a second terminal or the like) of the transistor, Z1is on the first connection path, the drain (or the second terminal or the like) of the transistor is electrically connected to Y through at least a third connection path, the third connection path does not include the second connection path, and Z2is on the third connection path,” and “a source (or a first terminal or the like) of a transistor is electrically connected to X through Z1at least with a first connection path, the first connection path does not include a second connection path, the second connection path includes a connection path through the transistor, a drain (or a second terminal or the like) of the transistor is electrically connected to Y through Z2at least with a third connection path, and the third connection path does not include the second connection path.” Still another example of the expression is “a source (or a first terminal or the like) of a transistor is electrically connected to X through Z1on at least a first electrical path, the first electrical path does not include a second electrical path, the second electrical path is an electrical path from the source (or the first terminal or the like) of the transistor to a drain (or a second terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor is electrically connected to Y through Z2on at least a third electrical path, the third electrical path does not include a fourth electrical path, and the fourth electrical path is an electrical path from the drain (or the second terminal or the like) of the transistor to the source (or the first terminal or the like) of the transistor.” When the connection path in a circuit configuration is defined by an expression similar to the above examples, a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor can be distinguished from each other to specify the technical scope.

Note that the above expressions are examples and there is no limitation on the expressions. Here, X, Y, Z1, and Z2each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

Note that in general, a potential (voltage) is a relative value and its level depends on the difference from a reference potential. Therefore, a ground potential, GND, or the like is not necessarily 0 V. For example, a ground potential or GND may be defined using the lowest potential or a substantially intermediate potential in a circuit as a reference. In those cases, a positive potential and a negative potential are set using the potential as a reference.

In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to drawings.

One embodiment of the present invention relates to a semiconductor device including a controller and a PLD controlled by the controller. The controller has a function of supplying a clock signal to the PLD. The reconfiguration of the PLD, or the like, is performed on the basis of the clock signal. Note that when a clock signal is input to the PLD during the reconfiguration of the PLD, or the like, abnormal data might be captured by the PLD, for example, leading to malfunction of the semiconductor device of one embodiment of the present invention. The semiconductor device of one embodiment of the present invention performs clock gating so that a clock signal can be prevented from being input to the PLD during reconfiguration or the like. Accordingly, the semiconductor device of one embodiment of the present invention can operate normally and operate at high speed even at a high clock frequency.

FIG. 1Ais a block diagram illustrating a configuration example of the semiconductor device of one embodiment of the present invention. The semiconductor device includes a controller10and a PLD20controlled by the controller10. The controller10includes a context generator11, a configuration memory12, and a clock generator13. The PLD20includes, for example, PLEs, which are programmable logic circuits, and an input/output circuit that controls signal input and output between the PLE and an external terminal included in the semiconductor device of one embodiment of the present invention. The PLD20also includes, for example, PSEs that determine a connection relationship between the PLEs, a connection relationship between the input/output circuit and the PLEs, or the like. Note that the PLEs, the PSEs, and the like included in the PLD20each include a configuration memory.

The positional relations of circuit blocks in a block diagram are specified for description. Even when a diagram illustrates that different functions are achieved by different circuit blocks, one circuit block may be actually configured to achieve different functions. Furthermore, the functions of circuit blocks in a diagram are specified for description. Even when a diagram illustrates one circuit block performing processing, a plurality of circuit blocks may be actually provided to perform the processing.

A signal clk, a signal resetb, a signal config, and a signal contextin can be input to the context generator11. The signal clk and the signal resetb can be input to the clock generator13. The signal resetb and the signal config can be input to the PLD20.

The signal clk serves as a clock signal that determines operation timing of each circuit included in the controller10. The signal resetb serves as a reset signal for flip-flops of the circuits included in the semiconductor device of one embodiment of the present invention. The details will be described later. The signal config serves as a signal indicating a state of configuration operation. The signal contextin serves as a signal for setting a state of context.

The context generator11has functions of generating signals context[0] to context[n−1] (n is an integer of 2 or more) necessary for context switch and outputting the signals to the configuration memory12and the configuration memories included in the PLD20. The context generator11also has a function of generating a variety of signals necessary for the operation of the clock generator13. The details will be described later. The configuration memory12has functions of retaining configuration data and generating a signal mout corresponding to the retained configuration data.

The clock generator13has a function of controlling whether to output or stop outputting a signal gclk serving as a clock signal to the PLD20in accordance with the logic of a variety of signals, which are necessary for the operation of the clock generator13and are generated by the context generator11, and the logic of the signal mout generated by the configuration memory12. For example, clock gating for one clock can be performed after context switch starts in the case where the potential of the signal mout is at an H level, and no clock gating can be performed in the case where the potential of the signal mout is at an L level.

When the same reference numerals used in this specification need to be distinguished from one another, symbols for identification such as [0], [1], and [n] are added to the reference numerals in some cases. For example, symbols such as [0] and [n−1] are used to distinguish a plurality of signals context from one another.

In this specification, an H level potential and an L level potential refer to a high potential and a low potential, respectively. An L level potential can be, for example, a ground potential.

In the case where the potential of the signal resetb is at an H level, for example, reset states of the flip-flops of the circuits included in the semiconductor device of one embodiment of the present invention can be canceled to allow data setup depending on the logic of the signal clk or the signal gclk. In contrast, in the case where the potential of the signal resetb is at an L level, the flip-flops of the circuits included in the semiconductor device of one embodiment of the present invention can be made in reset states so that data setup cannot be performed. The signal config can have an H level potential while the configuration memory12performs configuration operation and an L level potential while the configuration memory12does not perform configuration operation, for example. Note that the logic of the signal mout, the signal resetb, and the signal config can be inverted as appropriate.

Although the controller10includes one configuration memory12inFIG. 1A, the controller10may include configuration memories12[0] to12[m−1] (m is an integer of 2 or more) as illustrated inFIG. 1B. In the case of the configuration illustrated inFIG. 1B, the configuration memories12[0] to12[m−1] have functions of generating signals mout[0] to mout[m−1], respectively. This means that the configuration memory12has a function of generating m-bit signals mout.

With the configuration illustrated inFIG. 1B, for example, the clock generator13can generate binary integer data on the basis of the logic of the signals mout[0] to mout[m−1], which enables clock gating to be performed on the PLD20for clocks whose number is the integer. The binary integer data can be generated to have the signal mout[0] as the least significant bit (LSB) and the signal mout[m−1] as the most significant bit (MSB), for example.

In the case where the potential of the signal mout[1] is at an H level and the potentials of the other signals mout are all at an L level, for example, the clock generator13can perform clock gating for two clocks. In the case where the potentials of the signals mout[0] and mout[1] are at an H level and the potentials of the other signals mout are all at an L level, for example, the clock generator13can perform clock gating for three clocks. In the case where the potential of the signal mout[m−1] is at an H level and the potentials of the other signals mout are all at an L level, for example, the clock generator13can perform clock gating for 2 m−1clocks. In the case where the potentials of the signals mout[0] to mout[m−1] are all at an H level, the clock generator13can perform clock gating for 2m−1 clocks.

In the case where the potentials of the signals mout[0] to mout[m−1] are all at an L level, for example, the clock generator13can perform no clock gating.

In the semiconductor device with the configuration illustrated inFIG. 1AorFIG. 1B, when clock gating is performed on the PLD20until context switch is completed, data transfer between before and after context switch can be performed in the PLD20even in high-speed clock operation. The details will be described later.

The semiconductor device of one embodiment of the present invention can have a configuration illustrated inFIG. 2AorFIG. 2B.FIGS. 2A and 2Bare block diagrams of semiconductor devices which are the same as those inFIGS. 1A and 1B, respectively, except that the signals context generated by the context generator11are the signals context[0] and context[1] and the PLD20includes a PLE21.

FIG. 3is a circuit diagram illustrating a configuration example of the controller10illustrated inFIG. 2A. The controller10includes, as described above, the context generator11, the configuration memory12, and the clock generator13.

The context generator11includes an inverter31, an inverter32, an inverter33, an inverter34, an inverter35, a flip-flop41, a flip-flop42, an AND circuit51, an AND circuit52, an AND circuit53, and an AND circuit54. The clock generator13includes a flip-flop43, an XOR circuit55, an NAND circuit56, and an AND circuit57.

An input terminal of the inverter31is electrically connected to a clock input terminal of the flip-flop41and a first input terminal of the AND circuit57. An output terminal of the inverter31is electrically connected to a clock input terminal of the flip-flop42and a clock input terminal of the flip-flop43.

An input terminal of the inverter32is electrically connected to a data output terminal of the flip-flop41and a data input terminal of the flip-flop42. An output terminal of the inverter32is electrically connected to an input terminal of the inverter33and a second input terminal of the AND circuit53.

An output terminal of the inverter33is electrically connected to a second input terminal of the AND circuit51.

An input terminal of the inverter34is electrically connected to a data output terminal of the flip-flop42, a data input terminal of the flip-flop43, a first input terminal of the AND circuit52, and a second input terminal of the XOR circuit55. An output terminal of the inverter34is electrically connected to a first input terminal of the AND circuit54.

An output terminal of the inverter35is electrically connected to a first input terminal of the AND circuit51and a first input terminal of the AND circuit53.

A data output terminal of the flip-flop43is electrically connected to a first input terminal of the XOR circuit55.

An output terminal of the AND circuit51is electrically connected to a second input terminal of the AND circuit52. An output terminal of the AND circuit53is electrically connected to a second input terminal of the AND circuit54.

A first input terminal of the NAND circuit56is electrically connected to the configuration memory12. A second input terminal of the NAND circuit56is electrically connected to an output terminal of the XOR circuit55. An output terminal of the NAND circuit56is electrically connected to a second input terminal of the AND circuit57.

The signal clk can be input to the clock input terminal of the flip-flop41and the first input terminal of the AND circuit57. The signal resetb can be input to reset input terminals of the flip-flops41,42, and43. The signal config can be input to an input terminal of the inverter35. The signal contextin can be input to a data input terminal of the flip-flop41.

The inverter31has a function of generating an inverted signal of the signal clk.

The flip-flop41has a function of generating a data output signal synchronized with the rise of the signal clk from the signal contextin. In the case where the potential of the signal contextin is at an H level, for example, the flip-flop41generates a data output signal having an H level potential at the rise of the signal clk.

The flip-flop42has a function of generating a data output signal synchronized with the fall of the signal clk from the data output signal generated by the flip-flop41. In the case where a data output signal having an H level potential is generated by the flip-flop41, for example, the flip-flop42generates a data output signal having an H level potential at the fall of the signal clk.

A circuit consisting of the inverter32, the inverter34, the inverter35, the AND circuit53, and the AND circuit54has a function of generating the signal context[0]. A circuit consisting of the inverter32, the inverter33, the inverter35, the AND circuit51, and the AND circuit52has a function of generating the signal context[1]. Note that for both of the circuits, the data output signal of the flip-flop41, the data output signal of the flip-flop42, and the signal config are input signals.

The flip-flop43has a function of generating a data output signal synchronized with the fall of the signal clk from the data output signal generated by the flip-flop42. Accordingly, the logic of the data output signal generated by the flip-flop43is changed one clock after the logic change of the data output signal generated by the flip-flop42.

The XOR circuit55has a function of outputting a signal having an H level potential when the logic of the data output signal generated by the flip-flop42is different from the logic of the data output signal generated by the flip-flop43and outputting a signal having an L level potential when the data output signals have the same logic. Context switch occurs at the same time as the logic change of the data output signal generated by the flip-flop42; thus, the XOR circuit55outputs a signal having an H level potential at the instant when context switch occurs, and outputs a signal having an L level potential at the next fall of the signal clk. In other words, the XOR circuit55enables a pulse signal to be obtained at the timing of context switch.

The NAND circuit56has a function of generating a control signal for clock gating performed on the PLD20. Clock gating can be performed on the PLD20in the case where the potential of the signal mout is at an H level and the potential of the signal output from the XOR circuit55is at an H level, and no clock gating can be performed in the other cases, for example.

The AND circuit57has a function of generating the signal gclk whose logic corresponds to the logic of the signal clk when a signal having an H level potential is output from the NAND circuit56and generating the signal gclk whose potential is fixed at an L level when a signal having an L level potential is output from the NAND circuit56.

FIG. 4Ais a circuit diagram illustrating a configuration example of the controller10illustrated inFIG. 2B.

The controller10with the configuration illustrated inFIG. 4Ais different from the controller10with the configuration illustrated inFIG. 3in including a clock gating control circuit60instead of the NAND circuit56and including the configuration memories12[0] to12[m−1].

When a signal output from the output terminal of the XOR circuit55is a signal sp, the signal clk, the signals mout[0] to mout[m−1], and the signal sp can be input to the clock gating control circuit60.

The clock gating control circuit60has a function of outputting a signal en for controlling clock gating performed on the PLD20. For example, the number of clocks during which clock gating is performed on the PLD20is determined on the basis of the logic of the signals mout[0] to mout[m−1], and the signal en having an L level potential is output for the number of clocks. The signal en is input to the second input terminal of the AND circuit57; thus, in a period during which the clock gating control circuit60outputs the signal en having an L level potential, the potential of the signal gclk is at an L level regardless of the logic of the signal clk. Meanwhile, in a period during which the clock gating control circuit60outputs the signal en having an H level potential, the logic of the signal gclk corresponds to the logic of the signal clk. This means that clock gating can be performed on the PLD20in a period during which the potential of the signal en is at an L level.

According to the above, the signal en serves as an enable signal for clock gating.

Note that the logic of the signal en may be inverted. That is, the clock generator13may have a configuration in which clock gating can be performed on the PLD20when the potential of the signal en is at an H level.

FIG. 4Billustrates a configuration example of the clock gating control circuit60illustrated inFIG. 4A. The clock gating control circuit60includes a counter circuit61and a comparator62.

The signal clk and the signal sp can be input to the counter circuit61, and the signals mout[0] to mout[m−1] can be input to the comparator62.

The counter circuit61has functions of counting clock pulses of the signal clk and outputting k-bit (k is an integer of 2 or more) signals. The comparator62has functions of comparing the binary number based on the logic of the k-bit signals output from the counter circuit61and the binary number based on the logic of the m-bit signals mout with each other and outputting the signal en whose logic is determined in accordance with the comparison result. Note that the numerical range of data on the m-bit signals mout can be controlled by an internal logic when four arithmetic operations are performed.

Described here is the operation of the clock gating control circuit60. When the potential of the signal sp is at an H level, a register included in the counter circuit61is initialized. As a result, the potentials of the k-bit signals output from the counter circuit61all become an L level. Thus, the potential of the signal en becomes an L level, leading to the start of clock gating performed on the PLD20.

Next, the counter circuit61starts counting in synchronization with the rise or fall of the signal clk. After the counting starts, the comparator62compares the binary number based on the logic of the k-bit signals output from the counter circuit61and the binary number based on the logic of the m-bit signals mout with each other, and outputs the signal en having an H level potential when the value output from the counter circuit61is greater than or equal to the value of the signal mout. Accordingly, clock gating performed on the PLD20terminates.

The above is the operation of the clock gating control circuit60. Note that after clock gating terminates, the counter circuit61counts up to full count and then stops its operation while holding the counted value, for example. The term “full count” means that the potentials of the k-bit signals output from the counter circuit61all become an H level.

Note that the circuit configurations illustrated inFIG. 3andFIGS. 4A and 4Bare only examples, and any other configuration can be employed as long as one embodiment of the present invention can be achieved. For example, the AND circuit51, the AND circuit52, the AND circuit53, the AND circuit54, the NAND circuit56, and the AND circuit57inFIG. 3may be replaced by a circuit71, a circuit72, a circuit73, a circuit74, a circuit76, and a circuit77, respectively, as illustrated inFIG. 5. For another example, the AND circuits51to54and the AND circuit57inFIG. 4Amay be replaced by the circuits71to74and the circuit77, respectively, as illustrated inFIG. 6.

FIG. 7Ais a circuit diagram illustrating a configuration example of the PLE21illustrated inFIGS. 2A and 2B. The PLE21includes a look-up table80, a flip-flop83, and a multiplexer84. The look-up table80includes configuration memories81[0] to81[16].FIG. 7Billustrates a configuration example of the look-up table illustrated inFIG. 7A.

The look-up table80is electrically connected to a data input terminal of the flip-flop83and a first input terminal of the multiplexer84. The configuration memory81[16] is electrically connected to a selection signal input terminal of the multiplexer84. A data output terminal of the flip-flop83is electrically connected to a second input terminal of the multiplexer84.

Signals in[0] to in[3] can be input to the look-up table80. The signals context[0] and context[1] can be input to the configuration memories81[0] to81[16]. The signal gclk can be input to a clock input terminal of the flip-flop83. The signal resetb can be input to a reset input terminal of the flip-flop83.

The look-up table80has a function of outputting an output signal of one of the configuration memories81[0] to81[15] in accordance with the logic of the signals in[0] to in[3], as illustrated inFIG. 7B. Similarly to the configuration memory12, the configuration memories81[0] to81[16] each have functions of retaining configuration data and generating a signal corresponding to the retained configuration data. The flip-flop83has a function of performing either retention or output to the second input terminal of the multiplexer84, of the output signal from the look-up table80depending on the logic of the signal gclk. The multiplexer84has a function of outputting, as a signal out, a signal with the logic that corresponds to the logic of one of the signal output from the look-up table80and the signal output from the data output terminal of the flip-flop83in accordance with the logic of the signal output from the configuration memory81[16].

Although the look-up table80is a 4-input look-up table here, one embodiment of the present invention is not limited thereto. For example, the look-up table80may be a 6-input look-up table or a p-input look-up table (p is an integer of 2 or more).

FIG. 8is a circuit diagram illustrating a configuration example for each of the configuration memory12illustrated inFIGS. 2A and 2Band the configuration memory81illustrated inFIGS. 7A and 7B. The configuration memory12and the configuration memory81each include a memory cell91[0], a memory cell91[1], a transistor92[0], a transistor92[1], a transistor93, and a wiring94.

AlthoughFIG. 8illustrates an example where the transistor92[0], the transistor92[1], and the transistor93are all n-channel transistors, one embodiment of the present invention is not limited thereto; some or all of the transistors may be p-channel transistors.

In this specification, an n-channel transistor is referred to as an n-ch transistor and a p-channel transistor is referred to as a p-ch transistor in some cases.

The memory cell91[0] is electrically connected to one of a source and a drain of the transistor92[0]. The memory cell91[1] is electrically connected to one of a source and a drain of the transistor92[1]. The other of the source and the drain of the transistor92[0] is electrically connected to the other of the source and the drain of the transistor92[1] and one of a source and a drain of the transistor93. The other of the source and the drain of the transistor93is electrically connected to the wiring94.

A signal data can be input to the memory cell91[0] and the memory cell91[1]. A signal word[0] can be input to the memory cell91[0]. A signal word[1] can be input to the memory cell91[1]. The signal context[0] can be input to a gate of the transistor92[0]. The signal context[1] can be input to a gate of the transistor92[1]. The signal config can be input to a gate of the transistor93.

The memory cell91[0] and the memory cell91[1] each have a function of retaining configuration data. The transistor92[0] has a function of determining, on the basis of the potential of the signal context[0], whether or not to output data based on configuration data retained in the memory cell91[0] as the signal mout to the outside of the configuration memory12and the configuration memory81. The transistor92[1] has a function of determining, on the basis of the potential of the signal context[1], whether or not to output data based on configuration data retained in the memory cell91[1] as the signal mout to the outside of the configuration memory12and the configuration memory81.

This means that, in the case where the potential of the signal context[0] is at an H level, the potential of the signal mout becomes an H level when the potential of configuration data retained in the memory cell91[0] is at an H level, whereas the potential of the signal mout becomes an L level when the potential of configuration data retained in the memory cell91[0] is at an L level, for example. Furthermore, in the case where the potential of the signal context[1] is at an H level, the potential of the signal mout becomes an H level when the potential of configuration data retained in the memory cell91[1] is at an H level, whereas the potential of the signal mout becomes an L level when the potential of configuration data retained in the memory cell91[1] is at an L level, for example.

Note that the logic of the signal context[0] and the signal context[1] can be inverted as appropriate. Furthermore, the configuration memory12and the configuration memory81can each have a configuration in which the potential of the signal mout becomes an L level when the potential of configuration data retained in the memory cell91[0] is at an H level and the potential of the signal mout becomes an H level when the potential of configuration data retained in the memory cell91[0] is at an L level, for example. Alternatively, for example, a configuration can be employed in which the potential of the signal mout becomes an L level when the potential of configuration data retained in the memory cell91[1] is at an H level and the potential of the signal mout becomes an H level when the potential of configuration data retained in the memory cell91[1] is at an L level.

The signal data has a function of supplying configuration data to the memory cell91[0] and the memory cell91[1]. The signal word[0] serves as a write control signal for controlling the writing of configuration data to the memory cell91[0]. The signal word[1] serves as a write control signal for controlling the writing of configuration data to the memory cell91[1].

The transistor93has a function of fixing the potential of the signal mout at the potential of the wiring94during configuration operation. Note that an L level potential can be applied to the wiring94, for example.

As illustrated inFIG. 9A, the memory cell91[0] illustrated inFIG. 8may include a transistor95[0] and a latch circuit96[0], and the memory cell91[1] illustrated inFIG. 8may include a transistor95[1] and a latch circuit96[1], for example. Alternatively, as illustrated inFIG. 9B, a configuration in which a signal dataB, which is data (complementary data) obtained by inverting the logic of the signal data, can be supplied to the latch circuit96[0] and the latch circuit96[1] may be employed. In that case, the signal dataB is supplied to the latch circuit96[0] through a transistor97[0] and to the latch circuit96[1] through a transistor97[1].

As illustrated inFIG. 10A, a configuration may be employed in which the memory cell91[0] includes the transistor95[0], a latch circuit98[0], magnetoresistive random access memories (MRAMs)99[0], and a wiring100[0] and the memory cell91[1] includes the transistor95[1], a latch circuit98[1], MRAMs99[1], and a wiring100[1]. Alternatively, as illustrated inFIG. 10B, a configuration may be employed in which the latch circuit98[0] is connected to the MRAMs99[0] through transistors101[0] and the latch circuit98[1] is connected to the MRAMs99[1] through transistors101[1].

Note that the memory cell91[0] and the memory cell91[1] with the configurations illustrated inFIG. 10AorFIG. 10Bdo not necessarily include the latch circuit98[0] and the latch circuit98[1].

The memory cell91[0] and the memory cell91[1] illustrated inFIG. 8can have configurations illustrated inFIG. 11. The memory cell91[0] illustrated inFIG. 11includes a transistor95A[0], a transistor95B[0], a capacitor102A[0], a capacitor102B[0], a wiring103A[0], a wiring103B[0], a transistor104A[0], a transistor104B[0], a wiring105A[0], and a wiring105B[0]. The memory cell91[1] includes a transistor95A[1], a transistor95B[1], a capacitor102A[1], a capacitor102B[1], a wiring103A[1], a wiring103B[1], a transistor104A[1], a transistor104B[1], a wiring105A[1], and a wiring105B[1].

Although described here is an example where the transistor95A[0], the transistor95B[0], the transistor95A[1], the transistor95B[1], the transistor104A[0], the transistor104B[0], the transistor104A[1], and the transistor104B[1] are all n-ch transistors, one embodiment of the present invention is not limited thereto; some or all of the transistors may be p-ch transistors.

One of a source and a drain of the transistor95A[0] is electrically connected to one terminal of the capacitor102A[0] and a gate of the transistor104A[0]. One of a source and a drain of the transistor95B[0] is electrically connected to one terminal of the capacitor102B[0] and a gate of the transistor104B[0]. The other terminal of the capacitor102A[0] is electrically connected to the wiring103A[0]. The other terminal of the capacitor102B[0] is electrically connected to the wiring103B[0].

One of a source and a drain of the transistor104A[0] is electrically connected to one of a source and a drain of the transistor92[0] and one of a source and a drain of the transistor104B[0]. The other of the source and the drain of the transistor104A[0] is electrically connected to the wiring105A[0]. The other of the source and the drain of the transistor104B[0] is electrically connected to the wiring105B[0].

One of a source and a drain of the transistor95A[1] is electrically connected to one terminal of the capacitor102A[1] and a gate of the transistor104A[1]. One of a source and a drain of the transistor95B[1] is electrically connected to one terminal of the capacitor102B[1] and a gate of the transistor104B[1]. The other terminal of the capacitor102A[1] is electrically connected to the wiring103A[1]. The other terminal of the capacitor102B[1] is electrically connected to the wiring103B[1].

One of a source and a drain of the transistor104A[1] is electrically connected to one of a source and a drain of the transistor92[1] and one of a source and a drain of the transistor104B[1]. The other of the source and the drain of the transistor104A[1] is electrically connected to the wiring105A[1]. The other of the source and the drain of the transistor104B[1] is electrically connected to the wiring105B[1].

The potentials of the wiring103A[0], the wiring103B[0], the wiring103A[1], and the wiring103B[1] can be at an L level, for example. Furthermore, the wiring105A[0] and the wiring105B[0] are supplied with potentials with opposite logic levels, and the wiring105A[1] and the wiring105B[1] are supplied with potentials with opposite logic levels. For example, the potential of the wiring105B[0] is at an L level when the potential of the wiring105A[0] is at an H level. For another example, the potential of the wiring105B[1] is at an L level when the potential of the wiring105A[1] is at an H level.

The signal data can be input to the other of the source and the drain of the transistor95A[0], the other of the source and the drain of the transistor95B[0], the other of the source and the drain of the transistor95A[1], and the other of the source and the drain of the transistor95B[1]. A signal wordA[0] can be input to a gate of the transistor95A[0]. A signal wordB[0] can be input to a gate of the transistor95B[0]. A signal wordA[1] can be input to a gate of the transistor95A[1]. A signal wordB[1] can be input to a gate of the transistor95B[1].

Note that two types of signals word[0] can be input to the memory cell91[0] with the configuration illustrated inFIG. 11. In addition, two types of signals word[1] can be input to the memory cell91[1] with the configuration illustrated inFIG. 11. The two types of signals word[0] are described as the signal wordA[0] and the signal wordB[0], and the two types of signals word[1] are described as the signal wordA[1] and the signal wordB[1].

The transistor95A[0] has a function of controlling the writing of configuration data to the capacitor102A[0]. The transistor95B[0] has a function of controlling the writing of configuration data to the capacitor102B[0]. The transistor95A[1] has a function of controlling the writing of configuration data to the capacitor102A[1]. The transistor95B[1] has a function of controlling the writing of configuration data to the capacitor102B[1].

The capacitor102A[0], the capacitor102B[0], the capacitor102A[1], and the capacitor102B[1] each have a function of retaining configuration data. The transistor104A[0] has a function of amplifying configuration data retained in the capacitor102A[0]. The transistor104B[0] has a function of amplifying configuration data retained in the capacitor102B[0]. The transistor104A[1] has a function of amplifying configuration data retained in the capacitor102A[1]. The transistor104B[1] has a function of amplifying configuration data retained in the capacitor102B[1].

Next, procedures for retention and reading of configuration data in the memory cell91[0] and the memory cell91[1] with the configurations illustrated inFIG. 11will be described. Note that the potentials of the wiring105A[0] and the wiring105A[1] are set at an H level and the potentials of the wiring105B[0] and the wiring105B[1] are set at an L level.

To retain configuration data having an H level potential in the memory cell91[0], the potentials of the signal data and the signal wordA[0] are set at an H level. As a result, a charge is held in the capacitor102A[0] and an H level potential is applied to the gate of the transistor104A[0]. Thus, the transistor104A[0] is turned on. Since the potential of the wiring105A[0] is at an H level, a signal having an H level potential is output as the signal mout when the potential of the signal context[0] becomes an H level and the transistor92[0] is turned on.

To retain configuration data having an L level potential in the memory cell91[0], the potentials of the signal data and the signal wordB[0] are set at an H level. As a result, a charge is held in the capacitor102B[0] and an H level potential is applied to the gate of the transistor104B[0]. Thus, the transistor104B[0] is turned on. Since the potential of the wiring105B[0] is at an L level, a signal having an L level potential is output as the signal mout when the potential of the signal context[0] becomes an H level and the transistor92[0] is turned on.

To retain configuration data having an H level potential in the memory cell91[1], the potentials of the signal data and the signal wordA[1] are set at an H level. To retain configuration data having an L level potential in the memory cell91[1], the potentials of the signal data and the signal wordB[1] are set at an H level.

In the memory cell91[0] with the configuration illustrated inFIG. 11, a reduction in the off-state current of the transistor95A[0] leads to long retention time of a charge written to the capacitor102A[0], and a reduction in the off-state current of the transistor95B[0] leads to long retention time of a charge written to the capacitor102B[0]. Furthermore, a reduction in the off-state current of the transistor95A[1] leads to long retention time of a charge written to the capacitor102A[1], and a reduction in the off-state current of the transistor95B[1] leads to long retention time of a charge written to the capacitor102B[1]. Here, off-state current refers to current that flows between a source and a drain when a transistor is off. In the case of an n-ch transistor, for example, when its threshold voltage is approximately 0 V to 2 V, current flowing between a source and a drain when a gate voltage is negative with respect to source and drain voltages can be referred to as off-state current. An ultralow off-state current means that, for example, an off-state current per micrometer of channel width is lower than or equal to 100 zA (zeptoamperes). Since the off-state current is preferably as low as possible, the normalized off-state current is preferably lower than or equal to 10 zA/μm or lower than or equal to 1 zA/μm, further preferably lower than or equal to 10 yA/μm (yA: yoctoamperes). Note that 1 zA is 1×10−21A and 1 yA is 1×10−24A.

To obtain such an ultralow off-state current, a channel formation region of a transistor is formed using a semiconductor with a wide bandgap. An example of such a semiconductor is an oxide semiconductor. An oxide semiconductor has a bandgap of 3.0 eV or more; thus, a transistor whose active layer or active region contains an oxide semiconductor (OS transistor) has a low leakage current caused by thermal excitation and has an ultralow off-state current. A channel formation region of an OS transistor is preferably formed using an oxide semiconductor containing at least one of indium (In) and zinc (Zn). A typical example of such an oxide semiconductor is an In-M-Zn oxide (the element M is Al, Ga, Y, or Sn, for example). By reducing impurities serving as electron donors, such as moisture or hydrogen, and also reducing oxygen vacancies, an i-type (intrinsic) or a substantially i-type oxide semiconductor can be obtained. Here, such an oxide semiconductor can be referred to as a highly purified oxide semiconductor. By using a highly purified oxide semiconductor, the off-state current normalized by channel width of an OS transistor can be as low as several yoctoamperes per micrometer to several zeptoamperes per micrometer.

In addition, the OS transistor has lower temperature dependence of off-state current characteristics than a transistor whose active layer or active region formed using silicon (hereinafter such a transistor is referred to as a Si transistor). Thus, the normalized off-state current of the OS transistor can be less than or equal to 100 zA even at high temperatures (e.g., 100° C. or higher). Accordingly, the use of an OS transistor as the transistor95A[0] enables a charge written to the capacitor102A[0] to be retained for a long time even in a high temperature environment, and the use of an OS transistor as the transistor95B[0] enables a charge written to the capacitor102B[0] to be retained for a long time even in a high temperature environment. Furthermore, the use of an OS transistor as the transistor95A[1] enables a charge written to the capacitor102A[1] to be retained for a long time even in a high temperature environment, and the use of an OS transistor as the transistor95B[1] enables a charge written to the capacitor102B[1] to be retained for a long time even in a high temperature environment. According to the above, a semiconductor device that is highly reliable even in a high temperature environment can be obtained.

Note that the transistor92[0], the transistor92[1], the transistor93, the transistor104A[0], the transistor104B[0], the transistor104A[1], and the transistor104B[1] can be Si transistors. Since Si transistors have higher field-effect mobility than that of OS transistors, the amounts of current flowing in the transistor92[0], the transistor92[1], the transistor93, the transistor104A[0], the transistor104B[0], the transistor104A[1], and the transistor104B[1] can be increased. Thus, the semiconductor device of one embodiment of the present invention can operate at high speed.

Alternatively, the transistor92[0], the transistor92[1], the transistor93, the transistor104A[0], the transistor104B[0], the transistor104A[1], and the transistor104B[1] can be OS transistors. In other words, all of the transistors included in the configuration memory12and the configuration memory81can be OS transistors.

Further alternatively, some of the transistors included in the configuration memory12and the configuration memory81can be OS transistors and the rest of the transistors can be Si transistors.

The configurations of the memory cell91[0] and the memory cell91[1] are not limited to those illustrated inFIGS. 9A and 9B,FIGS. 10A and 10B, andFIG. 11, and a resistance random access memory (ReRAM) or a flash memory may be included, for example.

Note that the circuit configurations illustrated inFIGS. 7A and 7B,FIG. 8,FIGS. 9A and 9B,FIGS. 10A and 10B, andFIG. 11are only examples, and any other configuration can be employed as long as one embodiment of the present invention can be achieved.

FIG. 12is a block diagram illustrating a configuration example of the semiconductor device of one embodiment of the present invention.FIG. 12illustrates connection relationships between circuits included in the PLD20. As described above, the semiconductor device of one embodiment of the present invention includes the controller10and the PLD20, and the controller10includes the context generator11, the configuration memory12, and the clock generator13.

The PLD20includes, in addition to the PLEs21, input/output circuits110, PSEs120, a column driver131, and a row driver132. Note that each of the PSEs120can include a configuration memory having a configuration similar to the configurations of the configuration memory12and the configuration memory81.

The input/output circuits110each have a function of controlling input and output of signals between the external terminal included in the semiconductor device of one embodiment of the present invention and the PLEs21. The PSEs120each have a function of determining connection relationships between the PLEs21, connection relationships between the PLEs21and the input/output circuits110, and the like. The column driver131has a function of generating the signal data. The row driver132has a function of generating the signal word[0] and the signal word[1].

In the example illustrated inFIG. 12, ten PLEs21are arranged to form a logic array LAa, and another ten PLEs21are arranged to form a logic array LAb. Furthermore, ten input/output circuits110are arranged to form an input/output array IOAa, and another ten input/output circuits110are arranged to form an input/output array IOAb. In addition, the PSEs120are arranged in a matrix to form a switch array SWAa, a switch array SWAb, and a switch array SWAc.

In this specification, ten PLEs21included in the logic array LAa are described as PLEs21_00to21_09, ten PLEs21included in the logic array LAb are described as PLEs21_10to21_19, ten input/output circuits110included in the input/output array IOAa are described as input/output circuits110_00to110_09, and ten input/output circuits110included in the input/output array IOAb are described as input/output circuits110_10to110_19.

InFIG. 12, the PLEs21_00to21_19are denoted by “PLE00” to “PLE19,” and the input/output circuits110_00to110_19are denoted by “IO00” to “IO19,” in some cases. Furthermore, notations for the PSEs120inFIG. 12describe the functions of the PSEs120. For example, “PLE0* to IO00” means that the PSE120is placed between an input node of the input/output circuit110_00and output nodes of the PLEs21_00to21_09.

Note that the input/output circuits110_00to110_19are electrically connected to respective external terminals. The input/output arrays IOAa and IOAb have functions of controlling input and output of signals between the external terminals included in the semiconductor device of one embodiment of the present invention and the logic arrays LAa and LAb.

An operation example of the semiconductor device having the configuration illustrated inFIG. 2Awill be described using a timing chart inFIG. 13A, and an operation example of the semiconductor device having the configuration illustrated inFIG. 2Bwill be described using a timing chart inFIG. 13B.

The timing charts inFIGS. 13A and 13Bshow the potentials of the signal clk, the signal resetb, the signal config, the signal contextin, the signal mout, the signal context[0], the signal context[1], and the signal gclk, and the configuration state of the PLD20.

When the potential of the signal context[0] is at an H level, the configuration of the PLD20corresponds to configuration data retained in the memory cell91[0] included in the configuration memory81or the like, for example. The PLD20with such a configuration is represented by “PLD20_0.” When the potential of the signal context[1] is at an H level, the configuration of the PLD20corresponds to configuration data retained in the memory cell91[1] included in the configuration memory81or the like, for example. The PLD20with such a configuration is represented by “PLD20_1.”

InFIGS. 13A and 13B, the signal gclk changes at the same time as the signal clk except for the case of clock gating. However, there is a lag by propagation delay such as gate delay or RC delay in practice.

First, the operation of the semiconductor device with the configuration illustrated inFIG. 2Ais described using the timing chart inFIG. 13A. Before Time T0, the configuration memory12performs configuration operation, and the potential of the signal config is at an H level. In addition, the potentials of the signal resetb, the signal contextin, the signal mout, the signal context[0], and the signal context[1] are at an L level.

In the PLD20, a potential that determines a circuit configuration is fixed at the initial value. In the case where the PLEs21included in the PLD20each have the configuration illustrated inFIG. 7A, for example, the potentials of the signals in[0] to in[3] and the potentials of signals output from the configuration memories81[0] to81[15] are all at an L level. This state of the PLD20is called an initial state, in some cases.

At Time T0, the configuration memory12terminates configuration operation, and the potential of the signal config is set at an L level in synchronization with the rise of the signal clk. After that, the potential of the signal mout output from the configuration memory12becomes a potential corresponding to configuration data that is retained in the memory cell91[0] illustrated inFIG. 8. Here, the potential of the signal mout is at an H level.

At Time T1, the potential of the signal resetb is set at an H level in synchronization with the rise of the signal clk. Thus, reset states of the flip-flops of the circuits included in the semiconductor device of one embodiment of the present invention are canceled.

At Time T2, the potential of the signal context[0] is set at an H level in synchronization with the fall of the signal clk. Thus, context switch starts, and the transition of the configuration of the PLD20from the initial state to the PLD20_0starts.

At Time T3, the signal clk rises, but the potential of the signal gclk remains at an L level because the clock generator13illustrated inFIG. 2Aperforms clock gating for one clock. Thus, data setup for the flip-flops included in the PLD20can be prevented until the next rise of the signal clk. Although the transition from the initial state to the PLD20_0is not completed at Time T3, the transition to the PLD20_0is completed at the next rise of the signal gclk; thus, data setup for the flip-flops included in the PLD20during context switch can be prevented. Accordingly, abnormal-data setup for the flip-flops included in the PLD20can be prevented. Thus, data transfer between before and after context switch can be performed normally.

At Time T4, the potential of the signal contextin is set at an H level. The signal contextin can be controlled asynchronously with the signal clk. This means that the potential of the signal contextin does not need to be set at an H level at the time when the signal clk rises, for example.

At Time T5, the potential of the signal context[0] is set at an L level in synchronization with the rise of the signal clk. Then, at Time T6when the signal clk falls, the potential of the signal context[1] becomes an H level. Thus, context switch starts, and the transition of the configuration of the PLD20from the PLD20_0to the PLD20_1starts.

At Time T7, the signal clk rises, but the potential of the signal gclk remains at an L level because the clock generator13illustrated inFIG. 2Aperforms clock gating for one clock. Thus, data setup for the flip-flops included in the PLD20can be prevented until the next rise of the signal clk. Although the transition from the PLD20_0to the PLD20_1is not completed at Time T7, the transition to the PLD20_1is completed at the next rise of the signal gclk; thus, data setup for the flip-flops included in the PLD20during context switch can be prevented. Accordingly, abnormal-data setup for the flip-flops included in the PLD20can be prevented. Thus, data transfer between before and after context switch can be performed normally.

Note that in the case where the potential of the signal mout is at an L level from Time T0to Time T7, the clock generator13illustrated inFIG. 2Adoes not perform clock gating at Time T3and Time T7; thus, the potential of the signal gclk becomes equal to the potential of the signal clk. Except for the above, the operation of the semiconductor device of one embodiment of the present invention is the same as that when the potential of the signal mout is at an H level.

Next, the operation of the semiconductor device having the configuration illustrated inFIG. 2Bis described using the timing chart inFIG. 13B. Before Time T0, the configuration memories12[0] to12[m−1] perform configuration operation, and the potential of the signal config is at an H level. Furthermore, the potentials of the signal resetb, the signal contextin, the signal context[0], and the signal context[1] are at an L level. In addition, the potentials of the signals mout[0] to mout[m−1] are all at an L level.

At Time T0, the configuration memories12[0] to12[m−1] terminate configuration operation, and the potential of the signal config is set at an L level in synchronization with the rise of the signal clk. After that, the potentials of the signals mout[0] to mout[m−1] become potentials corresponding to configuration data retained in the memory cells91[0] included in the configuration memories12[0] to12[m−1]. Here, the potential of the signal mout[1] is at an H level and the potentials of the other signals mout are all at an L level.

Note that when the signal mout[0] is the LSB and the signal mout[m−1] is the MSB, the case where the potentials of the signals mout[0] to mout[m−1] are all at an L level is “0” in decimal form. Furthermore, the case where the potential of the signal mout[1] is at an H level and the potentials of the other signals mout are all at an L level is “2” in decimal form. InFIG. 13B, the case where the potentials of the signals mout[0] to mout[m−1] are all at an L level is shown as “0” and the case where the potential of the signal mout[1] is at an H level and the potentials of the other signals mout are all at an L level is shown as “2.”

At Time T1, the potential of the signal resetb is set at an H level in synchronization with the rise of the signal clk. Thus, reset states of the flip-flops of the circuits included in the semiconductor device of one embodiment of the present invention are canceled.

At Time T2, the potential of the signal context[0] is set at an H level in synchronization with the fall of the signal clk. Thus, context switch starts, and the transition of the configuration of the PLD20from the initial state to the PLD20_0starts.

At Time T3, the signal clk rises, but the potential of the signal gclk remains at an L level because the clock generator13illustrated inFIG. 2Bperforms clock gating for two clocks. Thus, data setup for the flip-flops included in the PLD20can be prevented until the signal clk two clocks after the signal clk rises at Time T3. Although the transition from the initial state to the PLD20_0is not completed at Time T3, the transition to the PLD20_0is completed at the rise of the signal gclk that occurs after clock gating; thus, data setup for the flip-flops included in the PLD20during context switch can be prevented. Accordingly, abnormal-data setup for the flip-flops included in the PLD20can be prevented. Thus, data transfer between before and after context switch can be performed normally.

At Time T4, the potential of the signal contextin is set at an H level. The signal contextin can be controlled asynchronously with the signal clk. This means that the potential of the signal contextin does not need to be set at an H level at the time when the signal clk rises, for example.

At Time T5, the potential of the signal context[0] is set at an L level in synchronization with the rise of the signal clk. Then, at Time T6when the signal clk falls, the potential of the signal context[1] becomes an H level. Thus, context switch starts, and the transition of the configuration of the PLD20from the PLD20_0to the PLD20_1starts.

At Time T7, the signal clk rises, but the potential of the signal gclk remains at an L level because the clock generator13illustrated inFIG. 2Bperforms clock gating for two clocks. Thus, data setup for the flip-flops included in the PLD20can be prevented until the signal clk two clocks after the signal clk rises at Time T7. Although the transition from the PLD20_0to the PLD20_1is not completed at Time T7, the transition to the PLD20_1is completed at the rise of the signal gclk that occurs after clock gating; thus, data setup for the flip-flops included in the PLD20during context switch can be prevented. Accordingly, abnormal-data setup for the flip-flops included in the PLD20can be prevented. Thus, data transfer between before and after context switch can be performed normally.

As described above, in the semiconductor device of one embodiment of the present invention, data transfer between before and after context switch can be performed normally even at a high clock frequency. Thus, the semiconductor device of one embodiment of the present invention can operate at high speed. Furthermore, data setup for the flip-flops included in the PLD20during context switch can be prevented in the semiconductor device of one embodiment of the present invention; thus, generation of shoot-through current in the flip-flops can be suppressed. Accordingly, the power consumption of the semiconductor device of one embodiment of the present invention can be reduced. In addition, abnormal-data setup for the flip-flops included in the PLD20can be prevented, leading to an increase in the reliability of the semiconductor device of one embodiment of the present invention.

In the case of the configuration including a plurality of the configuration memories12as illustrated inFIG. 2B, for example, clock gating can be performed on the PLD20for two or more clocks. In that case, a clock frequency can be high as compared with the case of one configuration memory12; thus, the semiconductor device of one embodiment of the present invention can operate at high speed. The greater the number of the configuration memories12is, the greater the number of clocks during which clock gating can be performed on the PLD20is; accordingly, a clock frequency can be increased, leading to high operation speed of the semiconductor device of one embodiment of the present invention.

Note that the operations shown inFIGS. 13A and 13Bare only examples, and any operation can be performed as long as one embodiment of the present invention can be achieved. For example, the operation performed in synchronization with the rise of the signal clk or the signal gclk inFIGS. 13A and 13Bcan be performed in synchronization with the fall of the signal clk or the signal gclk. Furthermore, for example, the operation performed in synchronization with the fall of the signal clk or the signal gclk inFIGS. 13A and 13Bcan be performed in synchronization with the rise of the signal clk or the signal gclk.

In this embodiment, an electronic component, an imaging device, an electronic device including an electronic component, and the like will be described as examples of semiconductor devices.

FIG. 14Ais a flow chart showing an example of a method for manufacturing an electronic component. An electronic component is also referred to as a semiconductor package, an IC package, or a package. For the electronic component, there are various standards and names corresponding to the direction or the shape of terminals; hence, one example of the electronic component will be described in this embodiment.

A semiconductor device including a transistor is completed by integrating detachable components on a printed circuit board through the assembly process (post-process). The post-process can be completed through steps shown inFIG. 14A. Specifically, after an element substrate is completed in a wafer process (S1), a dicing step for dividing the substrate into a plurality of chips is performed (S2). Before the substrate is divided into a plurality of pieces, the substrate is thinned to reduce warpage or the like of the substrate caused in the wafer process and to reduce the size of the component.

The chip is picked up to be mounted on and bonded to a lead frame in a die bonding step (S3). In the die bonding step, the chip may be bonded to the lead frame with a resin or a tape. As the bonding method, a method suitable for the product can be selected. In the die bonding step, the chip may be mounted on an interposer to be bonded. In a wire bonding step (S4), a lead of the lead frame is electrically connected to an electrode on the chip with a metal fine line (wire). A silver line or a gold line can be used as the metal fine line. Either ball bonding or wedge bonding can be used as wire bonding.

A wire-bonded chip is subjected to a molding step of sealing the chip with an epoxy resin or the like (S5). The lead of the lead frame is plated. Then, the lead is cut and processed into a predetermined shape (S6). This plate processing prevents rust of the lead and facilitates soldering at the time of mounting the chip on a printed circuit board in a later step. Printing process (marking) is performed on a surface of the package (S7). Through an inspection step (S8), the electronic component is completed (S9). Integrating the foregoing semiconductor device achieves a small electronic component with low power consumption.

FIG. 14Bis a schematic perspective view of an electronic component.FIG. 14Billustrates a quad flat package (QFP) as an example. An electronic component600illustrated inFIG. 14Bincludes a lead601and a circuit portion603. In the circuit portion603, the semiconductor device of one embodiment of the present invention is fabricated. The electronic component600is mounted on a printed circuit board602, for example. A combination of a plurality of the electronic components600electrically connected to each other over the printed circuit board602can be equipped in an electronic device. A completed circuit board604is provided in a variety of electronic devices or the like.

The electronic component of this embodiment can be used for electronic devices in a wide variety of fields, such as digital signal processing, software-defined radio systems, avionic systems (electronic devices used in aircraft, e.g., communication systems, navigation systems, autopilot systems, and flight management systems), application specific integrated circuit (ASIC) prototyping, medical image processing, voice recognition, encryption, bioinformatics, emulators for mechanical systems, and radio telescopes in radio astronomy. According to this embodiment, it is possible to reduce the size and power consumption of an electronic device.

Examples of electronic devices include display devices, personal computers, and image reproducing devices provided with recording media (devices that read image data of recording media such as digital versatile discs (DVDs) and have displays for displaying images). Other examples are portable phones, game machines including portable game machines, portable information terminals, e-book readers, cameras such as video cameras and digital still cameras, goggle-type displays (head mounted displays), navigation systems, audio reproducing devices (e.g., car audio systems and digital audio players), copiers, facsimiles, printers, and multifunction printers.FIGS. 15A to 15Fillustrate specific examples of these electronic devices.

A portable game machine700illustrated inFIG. 15Aincludes a housing701, a housing702, a display portion703, a display portion704, a microphone705, a speaker706, an operation key707, a stylus708, and the like.

A portable information terminal710illustrated inFIG. 15Bincludes a housing711, a housing712, a display portion713, a display portion714, a joint715, an operation key716, and the like. The display portion713is provided in the housing711, and the display portion714is provided in the housing712. The housings711and712are connected to each other with the joint715, and an angle between the housings711and712can be changed with the joint715. Accordingly, the change in the direction of an image displayed on the display portion713or switch between display and non-display of an image may be performed by changing the angle between the housings711and712connected with the joint715. A display device with a touch panel may be used as the display portion713and/or the display portion714.

A personal computer720illustrated inFIG. 15Cincludes a housing721, a display portion722, a keyboard723, a pointing device724, and the like.

FIG. 15Dillustrates an electric refrigerator-freezer as an example of a household appliance. An electric refrigerator-freezer730includes a housing731, a refrigerator door732, a freezer door733, and the like.

A video camera740inFIG. 15Eincludes a housing741, a housing742, a display portion743, an operation key744, a lens745, a joint746, and the like. The operation key744and the lens745are provided in the housing741, and the display portion743is provided in the housing742. The housing741and the housing742are connected to each other with the joint746, and an angle between the housing741and the housing742can be changed with the joint746. The change in the direction of an image displayed on the display portion743or switching between display and non-display of an image may be performed by changing the angle between the housings741and742.

A motor vehicle750illustrated inFIG. 15Fincludes a car body751, wheels752, a dashboard753, lights754, and the like. The motor vehicle750may be engine-powered, or may be an electric vehicle or a hybrid vehicle.

Note that one embodiment of the present invention is not limited to the above electronic devices as long as the semiconductor device of one embodiment of the present invention is included.

This embodiment can be combined with any of the other embodiments described in this specification as appropriate.

EXPLANATION OF REFERENCE

This application is based on Japanese Patent Application serial no. 2015-222635 filed with Japan Patent Office on Nov. 13, 2015, the entire contents of which are hereby incorporated by reference.