Warpage control of semiconductor die

A method is provided. A bottom passivation layer is formed on a dielectric layer over a semiconductor substrate. Then, a first opening is formed in the bottom passivation layer to expose a portion of the dielectric layer. Next, a metal pad is formed in the first opening. Afterwards, a first oxide-based passivation layer is formed over the metal pad. Then, a second oxide-based passivation layer is formed over the first oxide-based passivation layer. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.

BACKGROUND

Using the packaging techniques, the semiconductor dies having the electronic components may be electrically connected to an external device, for example, a printed-circuit board (PCB). During a packaging process for forming a package structure having the semiconductor dies and the external device, several depositing, etching, and heating operations may be performed. In such a packaging process, substrate warpage is a common problem that often occurs due to different thermal expansion coefficients of a variety of layers in the semiconductor dies. A solution to tackle the problem is required.

DETAILED DESCRIPTION

The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated90degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

A package structure including a printed circuit board (PCB) and a die bonded to the PCB may be formed by various depositing, etching and heating operations, in which one of the operations may be a reflow operation for bumping the die onto the PCB. In the reflow operation, the package structure is subjected to several thermal treatments under different temperatures. A change of the temperatures in the reflow operation causes die (substrate) warpage, especially when one or more passivation layers having greater thickness and greater hardness are formed in the die to reduce a risk of die cracks. Such die warpage gets worse when the package structure includes two dies on opposite sides of a double-sided PCB, leading to a concern of double-sided board level reliability (B2LR). For example, delamination may occur in two layers of each of the dies, in which the two layers may be two metal layers in an electrical connection structure of the die. Reducing the thickness of the passivation layer having greater hardness may improve the substrate warpage problem. However, mechanical strength of the die is also reduced because of the reduced thickness of the harder passivation layer. Without sufficient mechanical strength, die cracks may occur.

Embodiments of the present disclosure are directed to providing a semiconductor die and a method for controlling warpage in packaging. In some embodiments, plural passivation layers having different hardness are sequentially formed over a semiconductor substrate of the die. To form such passivation layers, different deposition operations with different deposition rates are used, so as to form at least one of the passivation layers that is densely packed and the other passivation layers that are loosely packed. In some embodiments, a thickness of the densely packed passivation layer (or having the greater hardness) is reduced, and a passivation layer that is loosely packed (i.e., having smaller hardness) is additionally formed on the densely packed passivation layer, so that the problems of the substrate warpage can be tackled and the risk of the die cracks is also reduced. Said passivation layers form a composite passivation layer having sufficient mechanical strength, lower thermal stress and higher fracture toughness. Therefore, substrate warpage is reduced and the reliability of the package structure is improved.

FIG. 1AandFIG. 1Bare flow charts showing a method100of controlling warpage in packaging in accordance with some embodiments of the present disclosure.FIG. 2throughFIG. 16are cross-sectional views showing a method for controlling warpage in packaging at various stages.FIG. 2illustrates an initial structure including a semiconductor substrate201. The semiconductor substrate201may be a silicon substrate. Alternatively, the semiconductor substrate201may be a silicon-on-insulator substrate. The semiconductor substrate201may further include a variety of electrical circuits (not shown). The electrical circuits formed on the semiconductor substrate201may be any type of circuitry suitable for a particular application.

In accordance with some embodiments, the electrical circuits may include various n-type metal-oxide semiconductor (NMOS) and/or p-type metal-oxide semiconductor (PMOS) devices such as transistors, capacitors, resistors, diodes, photo-diodes, fuses and the like. The electrical circuits may be interconnected to perform one or more functions. The functions may include memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry or the like. It is understood that the above examples are provided for illustrative purposes only to further explain applications of the present disclosure and are not meant to limit the present disclosure in any manner.

An interlayer dielectric layer202is formed on top of the semiconductor substrate201. The interlayer dielectric layer202may be formed, for example, of a low-K dielectric material, such as silicon oxide. The interlayer dielectric layer202may be formed by any suitable method known in the art, such as spinning, chemical vapor deposition (CVD) and plasma enhanced chemical vapor deposition (PECVD). It should also be noted that one skilled in the art will recognize that the interlayer dielectric layer202may further include plural dielectric layers.

A bottom metallization layer210and a top metallization layer212are formed over the interlayer dielectric layer202. As shown inFIG. 2, the bottom metallization layer210includes a first metal line211. Likewise, the top metallization layer212includes a second metal line213. Metal lines211and213are formed of metal materials such as copper or copper alloys and the like. The metallization layers210and212may be formed through any suitable techniques (e.g., deposition, damascene and the like). Generally, the one or more inter-metal dielectric layers and the associated metallization layers are used to interconnect the electrical circuits in the semiconductor substrate201to each other to form functional circuitry and to further provide an external electrical connection.

It is noted whileFIG. 2shows the bottom metallization layer210and the top metallization layer212, one or more inter-metal dielectric layers (not shown) and the associated metallization layers (not shown) may be formed between the bottom metallization layer210and the top metallization layer212. In particular, the layers between the bottom metallization layer210and the top metallization layer212may be formed by alternating layers of dielectric (e.g., extremely low-k dielectric material) and conductive materials (e.g., copper).

A dielectric layer214is formed on top of the top metallization layer212. As shown inFIG. 2, a top metal connector215is embedded in the dielectric layer214. In particular, the top metal connector215provides a conductive channel for the metal line213and the electrical connection structure of the semiconductor device. The top metal connector215may be made of metallic materials such as copper, copper alloys, aluminum, silver, gold and any combinations thereof. The top metal connector215may be formed by suitable techniques such as CVD. Alternatively, the top metal connector215may be formed by sputtering, electroplating and the like.

Reference is made toFIG. 1AandFIG. 2. At operation102, a first passivation layer220is deposited on the dielectric layer214over a semiconductor substrate201. In some embodiments, the first passivation layer220includes a material such as undoped silicate glass (USG), silicon nitride (SiN), silicon dioxide (SiO2) or silicon oxynitride (SiON). In some embodiments, the first passivation layer220may be deposited by chemical vapor deposition (CVD), spin-coating, or other suitable techniques. The first passivation layer220may protect the metal lines211and213and top metal connector215. In some embodiments, the first passivation layer220includes a nitride layer and an oxide layer on the nitride layer. In such embodiments, a thickness of the nitride layer may be in a range from about 50 nm to about 100 nm. In such embodiments, a thickness of the oxide layer may be in a range from about 200 nm to about 1000 nm. The first passivation220having these layers possesses better electrical insulation properties and provides for better electrical protection.

Reference is made toFIG. 1AandFIG. 3. At operation104, a portion of the first passivation layer220is removed to form a first opening221, and the dielectric layer214and a conductive layer (e.g., the top metal connector215) are exposed through the first opening221. In some embodiments, removal of the first passivation layer220may be performed by forming a photoresist layer (not shown) over the first passivation layer220, patterning the photoresist layer using suitable lithography techniques, followed by an etching operation to form the first opening221.

Reference is made toFIG. 1A,FIG. 3andFIG. 4. At operation106, a metal layer230is deposited over the first passivation layer220such that the metal layer230fills the first opening221. In some embodiments, deposition of the metal layer230may be performed by physical vapor deposition (PVD), CVD, sputtering, plating or other suitable processes. In some embodiments, the metal layer230may include aluminum, aluminum alloy, copper, copper alloy or combinations thereof. For example, the metal layer230is formed of aluminum or aluminum alloy and thus can be referred to as an aluminum pad.

Reference is made toFIG. 1A,FIG. 4andFIG. 5. At operation108, the metal layer230is patterned by a photolithography operation and an etching operation, thereby forming plural metal pads232. In some embodiments, the metal pads232include a first metal pad234that is formed in the first opening221over the dielectric layer214, and second metal pads236formed on the first passivation layer220. In some embodiments, the first metal pad234electrically contacts the underlying top metal connector215, so as to provide electrical connection between the underlying integrated circuit to other external devices (e.g., a printed circuit board (PCB)). In some embodiments, a height of each of the second metal pads236may be in a range from about 1400 nm to about 2800 nm. The second metal pads236having such height are able to improve the electrical connection between the solder ball and the passivation interconnection layer(s). In some embodiments, after the metal layer230is patterned into the metal pads232, several gaps231are formed between adjacent two of the second metal pads236. Each gap231may have the same or different dimensions depending on the design of the package structure.

As described above, a composite passivation layer including several passivation layers having different hardness is then formed to improve the die warpage. Operations110,112,114and116ofFIG. 1AandFIG. 1Bfor forming the composite passivation layer is described below with reference to cross sectional views of intermediate stages of the formation of the composite passivation layer shown inFIG. 6throughFIG. 9. Each of the passivation layers has its own hardness and thickness, such that the composite passivation layer has low thermal stress, high fracture toughness and sufficient mechanical strength. A thickness of each of the passivation layers may be corresponded to a thickness of the passivation layer over the top of the second metal pads236unless particularly stated otherwise.

Reference is made toFIG. 1AandFIG. 6. At operation110, a second passivation layer240is conformally deposited over the first passivation layer220to cover the metal pads232. In some embodiments, the second passivation layer240having a first hardness is formed by a deposition operation having a deposition rate in a range from about 10 nm/second to about 30 nm/second. When the deposition rate is within such a range, a desired hardness of the second passivation layer240may be realized. For example, the first hardness of the second passivation layer240may be in a range from about 8 GPa to about 12 GPa. If the first hardness is smaller than about 8 GPa, the second passivation layer240may not provide sufficient protection to the underlying structures; however, if the first hardness is greater than about 12 GPa, delamination may occur between two adjacent passivation layers. In some embodiments, a thickness of the second passivation layer240is in a range from about 50 nm to about 400 nm. When a thickness of the second passivation layer240is smaller than about 50 nm, the second passivation layer240cannot provide sufficient protection to its underlying structures, causing charge accumulation in a subsequent operation (e.g., deposition of other passivation layer(s)) using a higher power). The charge accumulation may cause a change in a threshold voltage (Vt) or saturation current (Isat) of the electrical components arranged in the semiconductor substrate201. On the other hand, when the thickness of the second passivation layer240is greater than about 400 nm, tops of the gaps231between adjacent two of the second metal pads236are likely to be sealed (i.e., portions of the second passivation layer240on the tops of adjacent two second metal pads236contact each other), which increases challenges for subsequent gap filling operations. The unfilled gaps (or voids) may reduce the mechanical strength of the semiconductor die. In some embodiments, the second passivation layer240is formed of silicon oxide such as undoped silicate glass (USG) or silicon dioxide (SiO2). In some further embodiments, reduced modulus of the second passivation layer240may be in a range from about 68 GPa to about 102 GPa, and the second passivation layer240having the reduced modulus within such range may provide proper stress. When the reduced modulus of the second passivation layer240is not within such range, the adhesion between the second passivation layer240and its adjacent layer (e.g., the first passivation layer220or a subsequently formed passivation layer overlying the second passivation layer) may be unsatisfactory, In other embodiments, a coefficient of thermal expansion (CTE) of the second passivation layer240may be in a range from about 0.48 (*10−6·° C.−1) to about 0.72 (*10−6·° C.−1), so that the adhesion between the second passivation layer240and its adjacent layer (e.g., the first passivation layer220or a subsequently formed passivation layer overlying the second passivation layer) may be satisfactory.

In some embodiments, the second passivation layer240may be made of USG which is formed by plasma enhanced CVD (PECVD). In some embodiments, the PECVD is performed at a temperature of about 300° C. to about 500° C. by using silane (e.g., SiH4) and N2O as precursors. When the temperature is about 300° C. to about 500° C., the second passivation layer240may have a desired atomic ratio of silicon to oxygen (Si/O) for realizing a predetermined refractive index and extinction coefficient for its subsequent application, for example, Si/O may be in a range from about 1 to about 4. Ratio as used herein may refer to a resulting value of two values after said two values have been divided. In yet another embodiment, a flow rate of the silane precursor is in a range from about 600 sccm to about 750 sccm. In some other embodiments, a flow rate of the N2O is in a range from about 12000 sccm to about 20000 sccm. The flow rate of the precursors may impact both the deposition rate and the atomic ratio of the silicon to oxygen. When the flow rates of the precursors are controlled, properties such as the hardness, the refractive index or the extinction coefficient may be controlled satisfactorily.

Reference is made toFIG. 1AandFIG. 7. At operation112, a third passivation layer242is deposited over the second passivation layer240. The third passivation layer242is relatively thick and compact (i.e., having a high hardness), and thus the third passivation layer242has a stronger mechanical strength compared to, for example, the second passivation layer240. However, the third passivation layer242bears a higher thermal stress than the second passivation layer240when temperature varies, because the third passivation layer242is harder than the second passivation layer240. For example, the third passivation layer242would bear a higher compressive stress than the second passivation layer240when the package temperature cools down, thus leading to increased warpage in the third passivation layer242and hence B2LR test failure.

In some embodiments, the third passivation layer242having a second hardness is formed by a deposition operation having a deposition rate in a range from about 5 nm/second to about 15 nm/second. When the deposition rate is within such a range, a desired hardness of the third passivation layer242may be realized. For example, the second hardness of the third passivation layer242may be in a range from about 10.4 GPa to about 15.6 GPa. If the second hardness is smaller than about 10.4 GPa, the third passivation layer242may not provide sufficient protection to the underlying structures; however, if the second hardness is greater than about 15.6 GPa, delamination may occur between two adjacent passivation layers. In some embodiments, a thickness of the third passivation layer242is in a range from about 500 nm to about 1800 nm. When the thickness of the third passivation layer242is smaller than about 500 nm, the mechanical strength of the formed semiconductor die might be insufficient. On the other hand, when the thickness of the third passivation layer242is greater than about 1800 nm, the thermal stress of the third passivation layer242might cause serious warpage in packaging (e.g., when the package temperature cools down during the reflow process). In some embodiments, a ratio of the thickness of the third passivation layer242to the thickness of the second passivation layer240is in a range from about 3 to about 6. When the ratio is within such a range, warpage may be further reduced while proper mechanical strength remains. In some embodiments, the third passivation layer242is formed of silicon oxide such as USG or SiO2. In some further embodiments, reduced modulus of the third passivation layer242may be in a range from about 70.4 GPa to about 105.6 GPa, and the third passivation layer242having the reduced modulus within such range may provide proper stress. When the reduced modulus of the third passivation layer242is not within such range, the adhesion between the third passivation layer242and its adjacent layer (e.g., the second passivation layer240or a subsequently formed passivation layer overlying the third passivation layer) may be unsatisfactory, In other embodiments, a coefficient of thermal expansion (CTE) of the third passivation layer242may be in a range from about 0.4 (*10−6·° C.−1) to about 0.6 (*10−6·° C.−1), so that the adhesion between the third passivation layer242and its adjacent layer (e.g., the second passivation layer240or a subsequently formed passivation layer overlying the third passivation layer) may be satisfactory.

In some embodiments, the third passivation layer242may be made of USG which is formed by high density plasma CVD (HDPCVD), because HDPCVD can form an USG film with higher hardness than an USG film formed using PECVD. The HDPCVD performs a deposition operation and an etching operation simultaneously. The thicker third passivation layer242formed over corners of the tops of the second metal pads236may be etched to prevent the tops of the gaps231between two of the second metal pads236from being sealed. In addition, portions of the third passivation layer242over a top of each of the second metal pads236and in the gaps231are thicker than a portion of the third passivation layer242over sidewalls of each of the second metal pads236. In some embodiments, the HDPCVD is performed at a temperature of about 200° C. to about 600° C. by using silane (e.g., SiH4) and O2as precursors. When the temperature is about 200° C. to about 600° C., the third passivation layer242may have a desired atomic ratio of silicon to oxygen for realizing a predetermined refractive index and extinction coefficient for its subsequent application, for example, Si/O ratio may be in a range from about 1 to about 4. In some embodiments, a bias radio frequency (rf) power of the HDPCVD may be about 3500 W to about 7500 W. A proper deposition rate may be realized under such a bias rf power. In yet another embodiment, a flow rate of the silane precursor is in a range from about 20000 sccm to about 34000 sccm. In some other embodiments, a flow rate of the O2is in a range from about 165 sccm to about 205 sccm. The flow rate of the precursors may affect the deposition rate and the atomic ratio of the silicon to oxygen. When the flow rates of the precursors are controlled, properties such as the hardness, the refractive index or the extinction coefficient may be adequately controlled.

Reference is made toFIG. 1AandFIG. 8. At operation114, a fourth passivation layer244is conformally deposited over the third passivation layer242. The fourth passivation layer244is thinner and has lower hardness than the third passivation layer242. Therefore, the fourth passivation layer244bears lower thermal stress than the third passivation layers242when the package temperature cools down in the reflow process. Compared to merely reducing the thickness of the third passivation layer242to reduce substrate warpage, a combination of the third passivation layer242and the fourth passivation layer244has additional advantages such as sufficient mechanical strength, in addition to reducing substrate warpage. Process parameters for forming the fourth passivation layer244are described below.

In some embodiments, the fourth passivation layer244having a third hardness is formed by a deposition operation having a deposition rate in a range from about 10 nm/second to about 30 nm/second. When the deposition rate is in such a range, a desired hardness of the fourth passivation layer244may be realized. For example, the third hardness of the fourth passivation layer244may be in a range from about 8 GPa to about 12 GPa. If the third hardness is smaller than about 8 GPa, the fourth passivation layer244may not provide sufficient protection to the underlying structures; however, if the third hardness is greater than about 12 GPa, delamination may occur between two adjacent passivation layers. In some embodiments, a thickness of the fourth passivation layer244is in a range from about 200 nm to about 800 nm. When a thickness of the fourth passivation layer244is smaller than about 200 nm, the mechanical strength of the semiconductor die is insufficient. On the other hand, when the thickness of the fourth passivation layer244is greater than about 800 nm, substrate warpage cannot be reduced. In some embodiments, the thickness of the fourth passivation layer244may be the same as the thickness of the second passivation layer240. In some other embodiments, the thickness of the fourth passivation layer244may be greater than the thickness of the second passivation layer240. In some embodiments, a ratio of the thickness of the third passivation layer242to the thickness of the fourth passivation layer244is in a range from about 1.5 to about 4. When the ratio is within such a range, substrate warpage may be further improved while proper mechanical strength remains. In some embodiments, the fourth passivation layer244is formed of silicon oxide such as undoped silicate glass (USG) or silicon dioxide (SiO2). In some further embodiments, reduced modulus of the fourth passivation layer244may be in a range from about 68 GPa to about 102 GPa, and the fourth passivation layer244having the reduced modulus within such range may provide proper stress. When the reduced modulus of the fourth passivation layer244is not within such range, the adhesion between the fourth passivation layer244and its adjacent layer (e.g., the third passivation layer242or a subsequently formed passivation layer overlying the fourth passivation layer) may be unsatisfactory, In other embodiments, a coefficient of thermal expansion (CTE) of the fourth passivation layer244may be in a range from about 0.48 (*10−6·° C.−1) to about 0.72 (*10−6·° C.−1), so that the adhesion between the fourth passivation layer244and its adjacent layer (e.g., the third passivation layer242or a subsequently formed passivation layer overlying the fourth passivation layer) may be satisfactory.

In some embodiments, the fourth passivation layer244may be made of USG which is formed by plasma enhanced CVD (PECVD). In some embodiments, the PECVD is performed at a temperature of about 300° C. to about 500° C. by using silane (e.g., SiH4) and N2O as precursors. When the temperature is about 300° C. to about 500° C., the fourth passivation layer244may have a desired atomic ratio of silicon to oxygen for realizing a predetermined refractive index and extinction coefficient for its subsequent application, for example, Si/O ratio may be in a range from about 1 to about 4. In yet another embodiment, a flow rate of the silane precursor is in a range from about 600 sccm to about 750 sccm. In some other embodiments, a flow rate of the N2O is in a range from about 12000 sccm to about 20000 sccm. The flow rate of the precursors may affect the deposition rate and the atomic ratio of the silicon to oxygen. When the flow rates of the precursors are controlled, properties such as the hardness, the refractive index or the extinction coefficient may be adequately controlled. In some other embodiments, the fourth passivation layer244may be formed of a material that is different from the material of the second passivation layer240.

In some embodiments, the first hardness of the second passivation layer240is smaller than the second hardness of the third passivation layer242. In some other embodiments, the third hardness of the fourth passivation layer244is smaller than the second hardness of the third passivation layer242. In some still other embodiments, the first hardness may be equal to, smaller than or greater than the third hardness. A difference between the second hardness and the first hardness and a difference between the second hardness and the third hardness are respectively about 2.4 GPa to about 7.6 GPa, so that the composite passivation layers may have adequate toughness and strength. In some embodiments, the reduced modulus of the second passivation layer240is smaller than the reduced modulus of the third passivation layer242. In some other embodiments, the reduced modulus of the fourth passivation layer244is smaller than the reduced modulus of the third passivation layer242. In some still other embodiments, the reduced modulus of the second passivation layer240may be equal to, smaller than or greater than the reduced modulus of the fourth passivation layer244. A difference between the reduced modulus of the third passivation layer242and the second passivation layer240, and a difference between the reduced modulus of the third passivation layer242and the fourth passivation layer244are respectively about 2.4 GPa to about 37.6 GPa, so that the composite passivation layers may have adequate toughness and strength. In some embodiments, the second, third and fourth passivation layers240,242and244may have similar or the same CTE, so that proper adhesion between two adjacent passivation layers can be realized when the reflow operation is performed. Particularly, with such second, third and fourth passivation layers240,242and244sequentially arranged, the composite passivation layer has low thermal stress and high fracture toughness, and thus substrate warpage may be reduced. Furthermore, the composite passivation layer has sufficient mechanical strength to avoid cracks in the passivation layers during the packaging process.

Reference is made toFIG. 1BandFIG. 9. At operation116, the composite passivation layer further includes a fifth passivation layer246deposited over the fourth passivation layer244. In some embodiments, depositing the fifth passivation layer246may be performed by CVD, spin-coating, or other suitable techniques. In some embodiments, the fifth passivation layer246may be formed from a nitride-based dielectric material, rather than the oxide-based materials of the underlying passivation layers240-244. For example, the fifth passivation layer246includes silicon nitride (SiN), silicon oxynitride (SiON) or combinations thereof. In some embodiments, a thickness of the fifth passivation layer246is in a range from about 500 nm to about 1000 nm. A sum of the thicknesses of the second, third, fourth and fifth passivation layers240,242,244and246on top of each one of the second metal pads236is defined as T1, and a sum of thicknesses of the second, third, fourth and fifth passivation layers240,242,244and246between two of the second metal pads236is defined as T2. In some embodiments, a ratio of T2to T1is in a range about 0.6 to about 0.9. When T2/T1is smaller than 0.6, the mechanical strength of the composite passivation layer is insufficient, and cracks may occur during the packaging process. However, T2/T1greater than 0.9 is difficult to realize because of apparatus limitations.

Reference is made toFIG. 1BandFIG. 10. At operation118, portions of the second, third, fourth and fifth passivation layers240,242,244and246on the first metal pad234are removed, so as to form a second opening248, and a portion of the first metal pad234is exposed from the second opening248. In some embodiments, a photolithography operation and an etching operation are performed to define the second opening248. In some embodiments where the second, third and fourth passivation layers240,242and244are made of USG and the fifth passivation layer246is made of silicon nitride, the fifth passivation layer246may be removed by a wet process using hot H3PO4, and then the second, third and fourth passivation layers240,242and244may be removed using diluted HF. As shown inFIG. 10, the second, third, fourth and fifth passivation layers240,242,244and246partially cover the first metal pad234.

Reference is made toFIG. 1B,FIG. 10andFIG. 11. At operation120, a first buffer layer250is formed over the fifth passivation layer246. A third opening252is formed in the first buffer layer250and a portion of the first metal pad234is exposed through the third opening252. The third opening252is a combined opening of the second opening248; in other words, the third opening252is partially overlapped with the second opening248. In some embodiments, forming the first buffer layer250may include depositing a material of the first buffer layer250in the second opening248and over the fifth passivation layer246, followed by patterning the first buffer layer250to define the third opening252. In some embodiments, the material of the first buffer layer250may include polyimide, polybenzobisoxazole (PBO), benzocyclobutene (BCB), epoxy and the like, although other relatively soft, often organic, dielectric materials can also be used. The first buffer layer250serves as a stress buffer to reduce mechanical stress transfer to the passivation layers during packaging.

Reference is made toFIG. 1B,FIG. 11andFIG. 12. At operation122, a post passivation interconnection (PPI) layer260is formed over the first buffer layer250and the first metal pad234. The PPI layer260is conformal to the third opening252and electrically connected to the first metal pad234. In some embodiments, the PPI layer260is formed of a conductive material including, but not limited to, for example copper, aluminum, copper alloy, nickel, or other conductive materials. In some embodiments, the PPI layer260may be formed by a plating operation. In other embodiments, the PPI layer260electrically connects the electrical components in the semiconductor substrate201to a subsequently-formed solder ball290.

Reference is made toFIG. 1BandFIG. 13. At operation124, a second buffer layer270is formed over the PPI layer260. In some embodiments, the second buffer layer270is deposited over the PPI layer260, and then the second buffer layer270is patterned to form a fourth opening272that exposes a portion of the PPI layer260. In some embodiments, the material of the second buffer layer270may include polyimide, polybenzobisoxazole (PBO), benzocyclobutene (BCB), epoxy and the like, although other relatively soft, often organic, dielectric materials can also be used.

Reference is made toFIG. 1B,FIG. 13andFIG. 14. At operation126, an under bump metallurgy (UBM) layer280is formed in the fourth opening272and over the second buffer layer270. As shown inFIG. 14, the UBM layer280lines sidewalls of the fourth opening272and contacts the exposed portion of the PPI layer260. In some embodiments, the UBM layer280may include multiple layers of conductive materials, such as a layer of titanium and a layer of copper. Each layer in the UBM layer280may be formed using a plating process, such as electrochemical plating, although other processes of formation, such as sputtering, evaporation, electroless plating, or plasma enhanced chemical vapor deposition (PECVD), may alternatively be used depending upon the materials used for the UBM layer280.

Reference is made toFIG. 1BandFIG. 15. At operation128, a solder ball290is formed on the UBM layer280. In some embodiments, forming the solder ball290may include forming a photoresist layer (not shown) over the second buffer layer270and the UBM layer280, and patterning the photoresist layer to form a hole (not shown) that exposes the UBM layer280. The photoresist layer acts as a mold for a metal deposition process used for forming the solder ball290. In some embodiments, the photoresist material is compatible with conventional equipment and standard ancillary process chemicals used in electroplating. Next, a conductive material may fill a portion of the hole by evaporation, electroplating, or screen printing to form the solder ball290over the UBM layer280. The conductive material may be any of a variety of metals or metal alloys. For example, the conductive material may be copper, tin, silver or gold. After the solder ball290is formed, the photoresist layer may be removed.

In some embodiments, a wafer dicing operation (i.e., die sawing operation) may be performed to separate the semiconductor dies on the wafer after forming the solder ball290, as shown at operation130.

Reference is made toFIG. 1BandFIG. 16. At operation132, the semiconductor die200is bonded to a conductive element301of an external device300, thereby forming a package structure310ofFIG. 16. In some embodiments, the external device300may include, but is not limited to, a PCB board, a memory device, a CPU, or other devices possessing electrical I/O. For example, the PCB board may be a double-sided PCB board. In some embodiments, bonding the semiconductor die200to the external device300includes performing a reflow operation to form an electrical connection between the semiconductor die200and the external device300. In some embodiments, the reflow operation includes heating the package structure310from a first temperature to a second temperature, maintaining the second temperature for a time period, followed by cooling the package structure310from the second temperature to a third temperature. In some embodiments, the first temperature is in a range from about 25° C. to about 75° C. In some embodiments, the second temperature is in a range from about 230° C. to about 275° C. In some embodiments, the third temperature is in a range from about 25° C. to about 75° C. In some embodiments, the time period of the reflow operation may be from about 60 minutes to about 180 minutes. When the temperature of the reflow operation is controlled under such conditions, the electrical connection between the semiconductor die200and the external device300may be improved without increasing substrate warpage.

FIG. 17is a schematic sectional view of a package structure in accordance with some embodiments of the present disclosure. In some embodiments, two semiconductor dies200are respectively bonded to conductive elements321and323disposed on opposing two sides of an external device320, thereby forming a package structure410. In such embodiments, the external device320is a double-sided PCB board. Bonding the two semiconductor dies200onto the external device320may include the reflow operation described at operation132and with reference toFIG. 16.

In some embodiments, compared to a composite passivation layer A without the fourth passivation layer244(i.e., in which the thickness of the third passivation layer242is T3), the composite passivation layer B with the fourth passivation layer244(i.e., in which a sum of the thicknesses of the third and fourth passivation layers242and244is T3) bears a smaller thermal stress during the reflow operation. In addition, fracture strength of the composite passivation layer B is greater than fracture strength of the composite passivation layer A. Furthermore, the board level reliability of the package structure with the composite passivation layer B is greater than the board level reliability of the package structure with the composite passivation layer A.

Embodiments of the present disclosure may have at least the advantages outlined below. A combination of the passivation layer(s) having small hardness and small thickness and the passivation layer having great hardness and great thickness effectively reduces the thermal stress and increases the fracture toughness and the mechanical strength of the composite passivation layer. Therefore, substrate warpage of the semiconductor die occurring during the reflow operation is reduced, and the board level reliability of the package structure is improved.

In some embodiments, a method is provided. A bottom passivation layer is formed on a dielectric layer over a semiconductor substrate. Then, a first opening is formed in the bottom passivation layer to expose a portion of the dielectric layer. Next, a metal pad is formed in the first opening. Afterwards, a first oxide-based passivation layer is formed over the metal pad. Then, a second oxide-based passivation layer is formed over the first oxide-based passivation layer. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.

In some embodiments, a method is provided. A bottom passivation layer is formed on a dielectric layer over a semiconductor substrate. Next, a first opening is formed in the bottom passivation layer to expose a portion of the dielectric layer. Then, a metal pad is formed in the first opening and over the bottom passivation layer. Afterwards, a first oxide-based passivation layer is deposited over the metal pad at a first deposition rate. Then, a second oxide-based passivation layer is deposited over the first oxide-based passivation layer at a second deposition rate faster than the first deposition rate.

In some embodiments, semiconductor die is provided. The semiconductor die includes a semiconductor substrate, a dielectric layer over the semiconductor substrate, a metal structure in the dielectric layer, a first metal pad over the metal structure, a first oxide-based passivation layer over the first metal pad, a second oxide-based passivation layer over the first oxide-based passivation layer, and a bump electrically connected to the first metal pad. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.