SEMICONDUCTOR DEVICE

A semiconductor device includes a plurality of pads connected to an external device, a memory cell array in which a plurality of memory cells are disposed, a logic circuit configured to control the memory cell array and including a plurality of input/output circuits connected to the plurality of pads, and at least one inductor circuit connected between at least one of the plurality of pads and at least one of the plurality of input/output circuits. The inductor circuit includes an inductor pattern connected between the at least one of the plurality of pads and the at least one of the plurality of input/output circuits, and a variable pattern disposed between at least portions of the inductor pattern. The variable pattern is separated from the inductor pattern, the at least one of the plurality of pads, and the at least one of the plurality of input/output circuits.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 USC 119(a) of Korean Patent Application No. 10-2021-0079204, filed on Jun. 18, 2021, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.

BACKGROUND

Embodiments relate to a semiconductor device.

2. Description of the Related Art

Semiconductor devices include pads connected to other external devices, and the pads may be connected to an input/output circuit included in the semiconductor device and including at least one of a transmitter and a receiver.

SUMMARY

Embodiments are directed to a semiconductor device, including a plurality of pads connected to an external device; a memory cell array in which a plurality of memory cells are disposed; a logic circuit configured to control the memory cell array and including a plurality of input/output circuits connected to the plurality of pads; and at least one inductor circuit connected between at least one of the plurality of pads and at least one of the plurality of input/output circuits. The inductor circuit includes an inductor pattern connected between the at least one of the plurality of pads and the at least one of the plurality of input/output circuits, and a variable pattern disposed between at least portions of the inductor pattern. The variable pattern is separated from the inductor pattern, the at least one of the plurality of pads, and the at least one of the plurality of input/output circuits.

Embodiments are directed to a semiconductor device, including a semiconductor substrate; a plurality of elements disposed on the semiconductor substrate; and an interconnection region having a plurality of wiring patterns disposed to be connected to the plurality of elements, the plurality of wiring patterns including an inductor pattern connected to one of a plurality of pads and a variable pattern disposed on the same layer as the inductor pattern. The inductor pattern includes a first line and a second line adjacent to both sides of the variable pattern in a first direction, parallel to an upper surface of the semiconductor substrate, and the first line, the second line, and the variable pattern extend in a second direction, intersecting the first direction and parallel to the upper surface of the semiconductor substrate.

Embodiments are directed to a semiconductor device, including a plurality of pads connected to an external device; an input/output circuit connected to the plurality of pads; and at least one inductor circuit connected between at least one of the plurality of pads and the input/output circuit. The inductor circuit includes an inductor pattern connected between the at least one of the plurality of pads and the input/output circuit, and at least one variable pattern separated from the inductor pattern and adjacent to the inductor pattern. The inductor pattern includes a plurality of line patterns, and a first interval between some line patterns adjacent to the variable pattern, among the plurality of line patterns, is greater than a second interval between other portions of the line patterns not adjacent to the variable pattern.

DETAILED DESCRIPTION

FIG.1is a schematic block diagram illustrating a system including a semiconductor device according to an example embodiment.

Referring toFIG.1, a system according to an example embodiment may include a first semiconductor device10and a second semiconductor device20, and the first semiconductor device10and the second semiconductor device20may be connected to be able to communicate with each other.

The first semiconductor device10may include an internal circuit11, an input/output circuit12, and a plurality of pads13.

The second semiconductor device20may also include an internal circuit21, an input/output circuit22, and a plurality of pads23.

The internal circuit11of the first semiconductor device10and the internal circuit21of the second semiconductor device20may have different structures and may perform different functions. For example, the first semiconductor device10may be an application processor, and the internal circuit11thereof may include a CPU, a GPU, a DSP, an NPU, a memory interface, a display interface, a power circuit, and the like. As another example, the second semiconductor device20may be a memory device connected to the application processor, and the internal circuit21thereof may include a memory cell array in which memory cells are disposed, and peripheral circuits controlling the memory cell array.

The first semiconductor device10and the second semiconductor device20may exchange signals through a plurality of transmission lines30connecting the pads13and23. For example, the plurality of transmission lines30may be provided by wiring patterns formed on a printed circuit board (PCB) on which the first semiconductor device10and the second semiconductor device20are mounted. In another implementation, the first semiconductor device10and the second semiconductor device20are stacked on each other, and the plurality of transmission lines30may be provided by vertical via structures connecting the first semiconductor device10and the second semiconductor device20in a stacking direction.

When the first semiconductor device10transmits data to the second semiconductor device20, the data may be modulated into a predetermined signal and then transmitted. In this case, by securing the integrity of the signal for transmitting data, the second semiconductor device20may receive and demodulate the signal to accurately restore the data transmitted by the first semiconductor device10.

When parasitic components exist between the input/output circuit12and the plurality of pads13as well as in the input/output circuit12that modulates data to generate a signal, it may be difficult to secure the integrity of a signal for sending and receiving data.

With respect to the above, in an example embodiment, an inductor circuit may be connected to a signal path between at least one of the plurality of pads13and23and the input/output circuits12and22. The inductor circuit may include an inductor pattern having a predetermined inductance, and may include a variable pattern disposed between at least portions of the inductor pattern and separated from the inductor pattern. By controlling the total inductance of the inductor circuit by floating a variable pattern included in the inductor circuit or by connecting the variable pattern to a predetermined power voltage, the integrity of a signal exchanged between the semiconductor devices10and20may be secured and an eye margin may be improved.

FIGS.2to5are diagrams provided to illustrate an operation of a semiconductor device according to an example embodiment.

First,FIGS.2and3are diagrams illustrating a comparative example of a semiconductor device.

Referring toFIG.2, a semiconductor device50according to the comparative example may include an internal circuit51, an input/output circuit52, and a pad53.

The internal circuit51may include various circuits according to functions of the semiconductor device50, and the input/output circuit52may include a transmitter Tx and a receiver Rx. An output terminal of the transmitter Tx and an input terminal of the receiver Rx may be connected to the pad53, and an input terminal of the transmitter Tx and an output terminal of the receiver Rx may be connected to the internal circuit51.

A parasitic component CPARmay exist in a signal path between the input/output circuit52and the pad53. The signal output from the transmitter Tx to the pad53or the signal received by the receiver Rx from the pad53may be distorted due to the parasitic component CPAR, and as discussed below in connection withFIG.3, the integrity of the signal may be deteriorated and the eye margin may decrease.

Referring toFIG.3, a signal that is exchanged between the input/output circuit52and the pad53may be a signal that swings based on an intermediate voltage VCT. For example, when the receiver Rx receives a signal, a first valid period TV1(in which the receiver Rx may restore valid data) may be defined. When a rising edge or a falling edge of a clock signal that determines the operation timing of the receiver Rx exists within the first valid period TV1, the receiver Rx may accurately output data. In the comparative example illustrated inFIG.3, the first valid period TV1of the signal and a swing level ΔV1of the voltage may decrease due to the parasitic component CPAR, and as a result, the eye margin decreases, resulting in deterioration of signal integrity.

In contrast, referring toFIG.4, a semiconductor device60according to an example embodiment may include an inductor circuit LVAR.

Referring toFIG.4, the inductor circuit LVARmay be connected between an input/output circuit62and a pad63in series, e.g., one end of the inductor circuit LVARmay be connected to the input/output circuit62, and the other end may be connected to the pad63. However, the connection form of the inductor circuit LVARmay be variously modified according to example embodiments.

The inductor circuit LVARmay have an adjustable or variable inductance instead of a fixed inductance. For example, at least a portion of the inductor circuit LVARmay be connected to at least one circuit element included in the internal circuit61, and the inductance of the inductor circuit LVARmay be adjusted using the circuit element.

The inductance of the inductor circuit LVARmay be set or determined according to the parasitic component CPARexisting between the input/output circuit62and the pad63. The inductance of the inductor circuit LVARmay be combined with the capacitance of the parasitic component CPAR, and may be determined as a value that may secure a maximum eye margin of the signal exchanged between the input/output circuit62and the pad63.

Referring toFIG.5, by appropriately selecting the inductance of the inductor circuit LVAR, the valid period of the signal may be increased from the first valid period TV1illustrated inFIG.3to a second valid period TV2. In addition, the swing level of the voltage may also be increased to a second swing level ΔV2, which is greater than the first swing level ΔV1illustrated inFIG.3.

FIGS.6and7are diagrams schematically illustrating a semiconductor device according to an example embodiment.

First, referring toFIG.6, a semiconductor device100may have a center pad structure in which center pads115are disposed in a center region110. The center pads115may be connected to edge pads125and135(which are respectively disposed in edge regions120and130of the semiconductor device100) by a redistribution layer105.

The semiconductor device100may include a plurality of circuit elements formed on a semiconductor substrate, and a plurality of wiring patterns connected to the plurality of circuit elements. The plurality of wiring patterns may connect the plurality of circuit elements to each other, or may connect the plurality of circuit elements to the center pads115. For example, in the semiconductor device100, an input/output circuit connected to the center pads115may be disposed in the center region110. Accordingly, the length of the wiring patterns connecting the input/output circuit and the center pads115may be shortened and parasitic components may be significantly reduced.

Referring toFIG.7, a semiconductor device200may be a memory device and may include a plurality of unit memory regions210.

The semiconductor device200may be a dynamic random access memory (DRAM), and the unit memory region210may be defined as a memory bank. Each of the plurality of unit memory regions210may include a memory cell array211, a row decoder212, a sense amplifier circuit213, and a column decoder214.

The operation of the semiconductor device200may be controlled by a logic circuit205. The logic circuit205may store externally-received data in at least one of the plurality of unit memory regions210or read data from at least one of the plurality of unit memory regions210based on address information received from an external source, and may output the read data externally.

The logic circuit205may include an input/output circuit for sending and receiving signals to and from an external device. The plurality of unit memory regions210may be disposed on both or opposite sides of the logic circuit205, and the logic circuit205may be disposed in the center region of the semiconductor device200. Accordingly, by forming the semiconductor device200to have the center pad structure as in the example embodiment illustrated inFIG.6, the length of the wiring patterns connecting the input/output circuit of the logic circuit205and the center pads115may be reduced, and parasitic components may be reduced. In the present example embodiment, at least one of the wiring patterns connecting the input/output circuit and the center pads115may include an inductor circuit providing a predetermined inductance.

The inductor circuit may be implemented in various shapes, and may have an adjustable inductance instead of a fixed inductance. Accordingly, the inductance of the inductor circuit may be increased or decreased according to the capacitance of a parasitic component present in the wiring patterns, and the integrity of a signal transmitted and received through the center pads115may be improved.

FIGS.8and9are diagrams schematically illustrating an inductor circuit included in a semiconductor device according to an example embodiment.

Referring toFIG.8, a semiconductor device according to an example embodiment may include an inductor circuit300that includes an inductor pattern310and a variable pattern320.

The inductor pattern310may include a coil pattern having a spiral shape, a first connection line301and a second connection line302connected to both sides of the coil pattern, and the like. The coil pattern may include a plurality of line patterns extending in a first direction (X-axis direction) or a second direction (Y-axis direction).

Referring to the example embodiment illustrated inFIG.8, the first connection line301may be a line extending from a first end of an outer side of the coil pattern and may be disposed on the same layer as the coil pattern. The second connection line302may be a line extending from a second end of an inner side of the coil pattern and may be disposed on a layer different from that of the coil pattern. Accordingly, the first connection line301and the second connection line302may be disposed on different layers.

The variable pattern320may be physically separated from the inductor pattern310, and may be connected to at least one switch element SW. When the switch element SW is turned off, the variable pattern320may be floated, and when the switch element SW is turned on, the variable pattern320may receive a ground power voltage. The switch element SW may be turned on/off by a control signal CTR provided by the semiconductor device including the inductor circuit300.

In the region in which the variable pattern320is disposed, the spacing between the line patterns included in the inductor pattern310may vary. Referring toFIG.8, a first interval D1between some line patterns adjacent to the variable pattern320may be greater than a second interval D2between some line patterns that are not adjacent to the variable pattern320. For example, the width of the variable pattern320may be the same as the width of each of the line patterns, and in this case, the first interval D1may be at least twice as large as the second interval D2.

As the variable pattern320floats or is connected to a ground power voltage, mutual inductance between lines adjacent to both sides of the variable pattern320may be adjusted. For example, the total inductance of the inductor circuit300when the variable pattern320is floating may be greater than the total inductance of the inductor circuit300when the variable pattern320is connected to the ground power voltage. Accordingly, the semiconductor device may turn on the switch element SW using the control signal CTR when the total inductance of the inductor circuit300is to be reduced.

Next, referring toFIG.9, an inductor circuit300A may include an inductor pattern310, a first variable pattern320, and a second variable pattern330.

The first variable pattern320and the second variable pattern330may be disposed in different positions, and may be connected to a first switch element SW1and a second switch element SW2, respectively. Accordingly, the first variable pattern320and the second variable pattern330may float independently or may be connected to a ground power voltage.

Referring toFIG.9, the total inductance of the inductor circuit300A may have a maximum value when both the first variable pattern320and the second variable pattern330are floated, and the first variable pattern320and the second variable pattern330may produce a minimum value of inductance when receiving the ground power voltage. Also, when one of the first variable pattern320and the second variable pattern330floats and the other receives a ground power voltage, the total inductance may have an intermediate value. Accordingly, compared to the example embodiment illustrated inFIG.8, the total inductance of the inductor circuit300A may be more variously adjusted.

FIGS.10A to10Dare diagrams for describing operations of an inductor circuit included in a semiconductor device according to an example embodiment.

FIG.10Aillustrates a portion of an inductor circuit, in which a variable pattern is not disposed.

Referring toFIG.10A, an inductor circuit may include a first line311and a second line312, and the first line311and the second line312may be adjacent in a first direction (X-axis direction) and extend in a second direction (Y-axis direction). The inductor circuit may include an inductor pattern having a spiral shape, e.g., as described above with reference toFIGS.8and9, and the first line311and the second line312may be a portion of the inductor pattern. Accordingly, a first current I1of the first line311and a second current I2of the second line312may flow in the same direction.

In the portion of the inductor circuit illustrated inFIG.10A, another pattern is not disposed between the first line311and the second line312. Accordingly, in the portion of the inductor circuit illustrated inFIG.10A, the inductance formed by the first line311and the second line312may be defined as [L1+L2+M1], in which L1 is a self-inductance generated in the first line311by the first current I1, L2 is a self-inductance generated in the second line312by the second current I2, and M1is mutual inductance generated between the first line311and the second line312by the first current I1and the second current I2. The inductance [L1+L2+M1] generated in the portion of the inductor circuit illustrated inFIG.10Amay not be adequate to prevent degradation of signal integrity due to parasitic components of the signal path to which the inductor circuit is connected. For example, to prevent deterioration in signal integrity due to a parasitic component, an inductance lower than the inductance [L1+L2+M1] may be called for.

Similar to that described above, in an example embodiment illustrated inFIGS.10B and10C, the inductor circuit may include a first line311and a second line312, the first line311and the second line312may be adjacent in a first direction (X-axis direction) and extend in a second direction (Y-axis direction), and the inductor circuit may include an inductor pattern having a spiral shape, and the first line311and the second line312may be a portion of the inductor pattern. Referring toFIGS.10B and10C, in the present example embodiment, by disposing a variable pattern230between the first line311and the second line312and floating the variable pattern or connecting the variable pattern to the ground power voltage, the total inductance generated in the first line311and the second line312may be reduced. This will be described in more detail.

Referring toFIG.10B, the variable pattern320may be disposed between the first line311and the second line312, with the variable pattern320being disposed between the first line311and the second line312in the first direction such that the first line311and the second line312are adjacent to both sides of the variable pattern320in the first direction.

In another implementation (not shown inFIGS.10A and10B), the variable pattern320may extend in the second direction, between the first line311and the second line312.

In the example embodiment illustrated inFIG.10B, the variable pattern320is floated. Accordingly, the total inductance generated by the first line311and the second line312may be defined as [L1+L2+M2]. The mutual inductance M2(which is the mutual inductance generated between the first line311and the second line312) may have a lower value than the mutual inductance M1described above with reference toFIG.10A. In the example embodiment illustrated inFIG.10B, the variable pattern320is disposed between the first line311and the second line312such that the interval between the first line311and the second line312is increased, and as a result, the mutual inductance M2between the first line311and the second line312may decrease as compared to the mutual inductance M1ofFIG.10A.

Next, referring toFIG.10C, the variable pattern320disposed between the first line311and the second line312in the first direction, with the first line311and the second line312adjacent to both sides of the variable pattern320in the first direction, may be connected to a ground power voltage GND. In the example embodiment illustrated inFIG.10C, the distance between the first line311and the second line312is increased by the variable pattern320to obtain the effect of reducing the mutual inductance, and further, by biasing the variable pattern320to the ground power voltage GND, the mutual inductance may be further reduced. Therefore, to reduce the inductance of the inductor circuit in consideration of the parasitic component between the input/output circuit and the pad of the semiconductor device, the switch element connected to the variable pattern320may be turned on to bias the variable pattern320to the ground power voltage GND or the like, as illustrated inFIG.10C.

In an implementation (not shown), the variable pattern320may also be biased to a voltage other than the ground power voltage.

Similar to that described above, in an example embodiment illustrated inFIGS.10B and10C, the inductor circuit may include a first line311and a second line312, the first line311and the second line312may be adjacent in a first direction (X-axis direction) and extend in a second direction (Y-axis direction), and the inductor circuit may include an inductor pattern having a spiral shape, and the first line311and the second line312may be a portion of the inductor pattern. Referring toFIG.10D, a variable pattern320A may include both a region extending in the first direction and a region extending in the second direction. Accordingly, the variable pattern320A may be disposed not only between the first line311and the second line312extending in the second direction, but also between a third line313and a fourth line314extending in the first direction.

FIGS.11A to11Dare diagrams schematically illustrating an inductor circuit included in a semiconductor device according to an example embodiment.

Referring toFIGS.11A to11D, an inductor circuit according to an example embodiment may include a first line311and a second line312and a plurality of variable patterns320,330A and330B.

The first line311and the second line312may be adjacent to each other in the first direction (X-axis direction). The first line311, the second line312, and the plurality of variable patterns320,330A and330B may extend in a second direction (Y-axis direction).

Referring toFIGS.11A and11B, the first line311, the second line312and the variable patterns320and330A may be disposed in a first layer M1and a second layer M2. For example, the first variable pattern320may be disposed in the second layer M2together with the first line311and the second line312, and the second variable pattern330A may be formed in the first layer M1. As described above with reference toFIGS.8and9, the inductor pattern may include a spiral-shaped coil pattern, a first connection line301extending from the outer side of the coil pattern, and a second connection line302extending from the inner side of the coil pattern, and the second connection line302may be disposed on a layer different from the layer of the first connection line301and the coil pattern. In the present example embodiment, the first connection line301may be disposed in the same first layer M1as the second variable pattern330A.

In the present example embodiment, referring toFIG.11A, a first current I1and a second current I2may flow in the second direction, and the first variable pattern320may be biased to a ground power voltage.

In another state (not shown inFIG.11A), the second variable pattern330A may be floating.

In another state, referring toFIG.11B, both the first variable pattern320and the second variable pattern330A may be biased to the ground power voltage. Accordingly, compared to the total inductance provided by the inductor circuit in the example embodiment illustrated inFIG.11A, the total inductance provided by the inductor circuit in the example embodiment illustrated inFIG.11Bmay be lower. This is because in the example embodiment illustrated inFIG.11B, both the first variable pattern320and the second variable pattern330A are biased to the ground power voltage, such that the mutual inductance between the first and second lines311and312may be further greatly reduced relative to the example embodiment illustrated inFIG.11A.

Referring toFIGS.11C and11D, the first line311, the second line312, and the variable patterns320and330B may be disposed in the first layer M1and the second layer M2. In the present example embodiment, referring toFIGS.11C and11D, the thickness of the first variable pattern320, the first line311, and the second line312in the second layer M2may be greater than the thickness of the second variable pattern330B in the first layer M1. By forming the coil patterns and the first variable pattern320in the second layer M2to be thicker, the resistance of the inductor circuit may be lowered.

The total inductance provided by the inductor circuit may be determined similarly to that described above with reference toFIGS.11A and11B. In the example embodiment illustrated inFIG.11C, the first variable pattern320is biased to a ground power supply voltage and the second variable pattern330B is floated, whereas in the example embodiment illustrated inFIG.11D, both the first variable pattern320and the second variable pattern330B are biased to the ground power voltage. Accordingly, compared to the total inductance provided by the inductor circuit in the example embodiment illustrated inFIG.11C, the total inductance provided by the inductor circuit in the example embodiment illustrated inFIG.11Dmay be relatively lower.

FIGS.12and13are diagrams schematically illustrating a semiconductor device according to an example embodiment.

Referring first toFIG.12, a semiconductor device400according to an example embodiment may include an inductor circuit.

The semiconductor device400may include a device region TRA and an interconnection region MPA. The device region TRA may include a semiconductor substrate401and a plurality of elements410formed on the semiconductor substrate401. The interconnection region MPA may include a plurality of wiring patterns420connected to the plurality of elements410, and redistribution layers440connected to the plurality of wiring patterns420.

The plurality of elements410may include transistors formed on the semiconductor substrate401. For example, each of the plurality of elements410may include a source/drain region411and a gate structure415. The gate structure415may include a gate insulating layer412, a gate electrode layer413, and a gate spacer414. A device contact CNT may be connected to the source/drain region411and the gate structure415, and the device contact CNT may be connected to at least one of the plurality of wiring patterns420.

The plurality of wiring patterns420may be dividedly disposed on a plurality of wiring layers421-423. For example, the first wiring patterns disposed in the first wiring layer421may be connected to the plurality of elements410through the device contact CNT. The second wiring patterns disposed in the second wiring layer422may be connected to the lower wiring patterns through a first via structure V1, and the third wiring patterns disposed in the third wiring layer423may be connected to intermediate wiring patterns through a second via structure V2. In the example embodiment illustrated inFIG.12, the wiring patterns420are illustrated as being disposed in three wiring layers421-423, but the number of wiring layers in which the wiring patterns420are disposed may be variously modified.

A thickness of each of the plurality of wiring patterns420may be determined according to the wiring layers421-423on which the wiring patterns420are respectively disposed. For example, referring toFIG.12, the thicknesses of the first wiring patterns disposed in the first wiring layer421may be the smallest, whereas the thicknesses of the third wiring patterns disposed in the third wiring layer423may be the greatest. As the distance from the semiconductor substrate401in a direction perpendicular to the upper surface of the semiconductor substrate401increases, the thickness of the wiring patterns420may increase.

At least some areas of the third wiring patterns disposed in the third wiring layer423may provide a plurality of center pads430. The center pads430may be pads disposed in the center region of the semiconductor device400, and may be exposed by a first passivation layer435. The center pads430may be connected to redistribution layers440formed in a position higher than the third wiring layer423.

The redistribution layers440may include a first redistribution layer441, an RDL via442(redistribution layer via), and a second redistribution layer443. The first redistribution layer441may be a layer directly connected to the center pads430, and may be connected to the second redistribution layer443through the RDL via442. At least a portion of the second redistribution layer443may provide edge pads450disposed in an edge region of the semiconductor device400. The edge pads450may be exposed to the outside by the second passivation layer455, and may be connected to, e.g., pads of a substrate on which the semiconductor device400is mounted, through a wire or the like.

In the semiconductor device400according to the example embodiment illustrated inFIG.12, the inductor circuit may be formed in the redistribution layers440connecting the center pad430and the edge pad450.

The inductor circuit may include a spiral-shaped coil pattern, as described above, and at least two layers may be used to form the inductor circuit. For example, in the example embodiment illustrated inFIG.12, the redistribution layers440are implemented using the first redistribution layer441and the second redistribution layer443(which are respectively formed at different heights from the upper surface of the semiconductor substrate401), and form the inductor circuit in the redistribution layers440.

In further detail, the first redistribution layer441may include a first connection line extending from the inside of the coil pattern, and the second redistribution layer443may include a coil pattern and a second connection line extending from the outside of the coil pattern. Also, a variable pattern separated from the coil pattern and adjacent to the coil pattern may be formed on the second redistribution layer443.

The variable pattern may be connected to at least one switch element among the plurality of elements410, and by turning the switch element off to float the variable pattern or turning the switch element on to bias the variable pattern to the power supply voltage, the inductance of the inductor circuit may be adjusted. By adjusting the inductance of the inductor circuit, degradation of signal integrity due to parasitic components present in the interconnection region MPA may be significantly reduced, and the eye margin of a signal may be improved.

Referring toFIG.13, a semiconductor device500according to an example embodiment may include a device region TRA and an interconnection region MPA. The device region TRA may include a semiconductor substrate501and a plurality of elements510. The configuration of the plurality of elements510may be similar to that described above with reference toFIG.12.

In the example embodiment illustrated inFIG.13, the interconnection region MPA may include a plurality of wiring patterns520connected to the plurality of elements510, and redistribution layers550connected to the plurality of wiring patterns520, and the like. The plurality of wiring patterns520may be dividedly disposed on the plurality of wiring layers521-524, and the first wiring patterns disposed on the first wiring layer521may be connected to the plurality of elements510through a device contact CNT. As the distance from the upper surface of the semiconductor substrate501increases, the thickness of the wiring patterns520may increase.

In the example embodiment illustrated inFIG.13, an inductor circuit may be formed in a third wiring layer523and a fourth wiring layer524disposed on the highest positions among the wiring patterns520. As described above, when the inductor circuit includes a spiral-shaped coil pattern, at least two layers may be used to implement the inductor circuit. In the example embodiment illustrated inFIG.13, an inductor circuit may be implemented using the third wiring layer523and the fourth wiring layer524.

In further detail, a first connection line extending from the inside of the coil pattern may be formed in the third wiring layer523. In addition, a coil pattern, a second connection line extending from the outside of the coil pattern, and a variable pattern separated from the coil pattern and adjacent to the coil pattern may be formed in the fourth wiring layer524. By forming the coil pattern, the second connection line, the variable pattern, and the like on the fourth wiring layer524having a greatest thickness among layers of the wiring patterns520, the resistance of the inductor circuit may be significantly reduced.

At least a partial region of the second connection line connected to the coil pattern is exposed to the outside by a first passivation layer535, in the center region of the semiconductor device500, and may provide center pads530. The center pads530may be connected to the redistribution layers550. At least some regions of the redistribution layers550may be exposed externally by a second passivation layer555to provide edge pads560.

In the example embodiment illustrated inFIG.12, the inductor circuit may be formed on the redistribution layers440connected to the center pads430of the semiconductor device400. On the other hand, in the example embodiment illustrated inFIG.13, the inductor circuit may be formed using some of the wiring layers523and524connected to the redistribution layers550, among the layers of the wiring patterns520of the semiconductor device500. As described with reference toFIGS.12and13, the inductor circuit may be formed of wiring patterns having a relatively great thickness, and thus the resistance of the inductor circuit may be reduced, thereby significantly reducing deterioration of performance of the semiconductor device400,500due to the inductor circuit.

FIGS.14A and14Bare diagrams schematically illustrating an inductor circuit included in a semiconductor device according to an example embodiment.

Referring toFIG.14A, an inductor circuit600according to an example embodiment includes an inductor pattern610and a variable pattern620. The inductor pattern610may include a coil pattern, and a first connection line601and a second connection line602connected to both sides of the coil pattern, and the like.

The first connection line601may be a line extending from one side of the coil pattern, and the second connection line602may be a line extending from the other side of the coil pattern. In the example embodiment illustrated inFIG.14, the first connection line601and the second connection line602may be disposed on the same layer as the coil pattern. Accordingly, the inductor pattern610may be disposed on one layer.

The variable pattern620may be physically separated from the inductor pattern610and may be connected to at least one switch element SW. For example, when the switch element SW is turned off, the variable pattern620may float, and when the switch element SW is turned on, the variable pattern620may receive a ground power voltage.

In another implementation (not shown), the variable pattern620may receive a power voltage other than the ground power voltage, as a bias voltage, by turning on the switch element SW.

The switch element SW may be turned on/off by a control signal CTR provided by the semiconductor device that includes the inductor circuit600.

Mutual inductance between lines adjacent to both sides of the variable pattern620may be adjusted by disposing the variable pattern620therebetween, and floating the variable pattern620or connecting the variable pattern620to a ground power voltage. For example, the total inductance of the inductor circuit300when the variable pattern620is floating may be different from the total inductance of the inductor circuit300when the variable pattern620is connected to the ground power voltage. Accordingly, the semiconductor device may be set to a condition in which the eye margin of a signal input/output by the semiconductor device is significantly increased by turning the switch element SW on or off, and may set the switch element SW with reference to the conditions.

Referring toFIG.14B, an inductor circuit600A may include an inductor pattern610, a first variable pattern620, and a second variable pattern630. The first variable pattern620and the second variable pattern630may be disposed at different positions, and may be connected to a first switch element SW1and a second switch element SW2, respectively. Accordingly, the first variable pattern620and the second variable pattern630may each float independently or be connected to a ground power supply voltage.

In the example embodiment illustrated inFIG.14B, the total inductance of the inductor circuit600A may have a minimum value when both the first variable pattern620and the second variable pattern630are floated, and may have a maximum value when both the first variable pattern620and the second variable pattern630are biased to the ground power voltage. Also, when one of the first variable pattern620and the second variable pattern630floats and the other receives a ground power voltage, the total inductance may have an intermediate value. Accordingly, compared to the example embodiment illustrated inFIG.14A, the total inductance of the inductor circuit600A may be adjusted more variously.

FIGS.15A to15Care diagrams for describing operations of an inductor circuit included in a semiconductor device according to an example embodiment.

FIG.15Aillustrates a portion of an inductor circuit, in which a variable pattern is not disposed.

InFIGS.15A to15C, the inductor circuit may include a first line611and a second line612, and the first line611and the second line612may be adjacent in a first direction (X-axis direction), and may extend in a second direction (Y-axis direction). Here, the inductor circuit includes an inductor pattern having the shape as described above with reference toFIGS.14A and14B, and the first line611and the second line612may be a portion of the inductor pattern. Accordingly, a first current I1of the first line611and a second current I2of the second line612may flow in opposite directions.

In the portion of the inductor circuit illustrated inFIG.15A, another pattern is not disposed between the first line611and the second line612. Accordingly, in the portion of the inductor circuit illustrated inFIG.15A, the inductance formed by the first line611and the second line612may be defined as [L1−L2]. L1 may be a self-inductance generated in the first line611by the first current I1, and L2 may be a self-inductance generated in the second line612by the second current I2. Since the first current I1and the second current I2flow in opposite directions, the self-inductances generated in the first line611and the second line612, respectively, may have an effect of canceling each other. The inductance generated in the portion of the inductor circuit illustrated inFIG.15Amay not be suitable for preventing degradation of signal integrity due to parasitic components of a signal path to which the inductor circuit is connected. For example, to prevent degradation of signal integrity due to a parasitic component, an inductance greater than the inductance [L1−L2] may be called for.

In an example embodiment illustrated inFIGS.15B and15C, by disposing a variable pattern between the first line611and the second line612and floating the variable pattern or connecting the variable pattern to the ground power supply voltage, the total inductance generated by the first line611and the second line612may be increased. This will now be described in more detail with reference toFIGS.15B and15C.

First, referring toFIGS.15B and15C, the variable pattern620is disposed between the first line611and the second line612, and thus, the spacing between the first line611and the second line612in the first direction may increase. Accordingly, an effect of cancelling the inductance L1 generated in the first line611and the inductance L2 generated in the second line612from each other may be reduced, and the overall inductance of the inductor circuit may be increased.

Referring toFIG.15B, the variable pattern620may be floated. Referring toFIG.15C, the variable pattern620may be biased to a ground power voltage. A shielding effect may be provided by increasing the interval between the first line611and the second line612in the first direction. Also, by biasing the variable pattern620to the ground power voltage, and thus, the total inductance of the inductor circuit may be further significantly increased, compared with the example embodiment illustrated inFIG.15B.

In an implementation (not shown), the variable pattern620may be biased to a voltage other than the ground power voltage.

FIG.16is a diagram schematically illustrating a semiconductor device according to an example embodiment.

Referring toFIG.16, a semiconductor device700according to an example embodiment may include an inductor circuit.

The semiconductor device700may include a device region TRA and an interconnection region MPA. The device region TRA may include a semiconductor substrate701and a plurality of elements710formed on the semiconductor substrate701, and the configuration of the plurality of elements710may be similar to that described above with reference toFIGS.12and13. The interconnection region MPA may include a plurality of wiring patterns720connected to the plurality of elements710, redistribution layers740connected to the plurality of wiring patterns720, and the like.

The plurality of wiring patterns720may be dividedly disposed on the plurality of wiring layers721-723, and the thickness of each of the plurality of wiring patterns720may be determined by the wiring layers721-723on which the wiring patterns720are respectively disposed. Referring toFIG.16, the thickness of the first wiring patterns disposed on the first wiring layer721may be lower than the thickness of the third wiring patterns disposed on the third wiring layer723.

At least some regions of the third wiring patterns disposed on the third wiring layer723may provide a plurality of center pads730. The center pads730may be pads disposed in the center region of the semiconductor device700, and may be exposed by the first passivation layer735. The center pads730may be connected to the redistribution layer740, on the first passivation layer735.

The inductor circuit may be formed on the redistribution layer740, and the inductor circuit may have a shape as described above with reference toFIGS.14A and14B. Accordingly, all wiring patterns providing the inductor circuit may be formed on one layer, and the inductor circuit may be implemented with only one redistribution layer740. The inductor circuit formed in the redistribution layer740may include an inductor pattern and a variable pattern.

The variable pattern may be connected to at least one switch element among the plurality of elements710, and by turning the switch element off to float the variable pattern or turning the switch element on to bias the variable pattern to the power supply voltage, the inductance of the inductor circuit may be adjusted. By adjusting the inductance of the inductor circuit, degradation of signal integrity due to parasitic components present in the interconnection region MPA and the like may be prevented, and the eye margin of the signal may be improved.

FIG.17is a schematic diagram illustrating a semiconductor module including a semiconductor device according to an example embodiment.

Referring toFIG.17, a semiconductor module800according to an example embodiment may include a module substrate810and a semiconductor device820. The semiconductor device820may include an inductor circuit.

The semiconductor device820may be mounted on the module substrate810. The semiconductor device820may include a plurality of first pads PAD1, and the first pads PAD1may be connected to a plurality of second pads PAD2formed on the module substrate810via wires825. For example, the first pads PAD1may be edge pads provided by redistribution layers included in the semiconductor device820.

The second pads PAD2may be connected to the third pads PAD3through substrate wirings815formed on the module substrate810. The third pads PAD3may be pads for connecting the semiconductor module800to other external semiconductor devices, semiconductor modules, substrates, and the like.

As described above, the semiconductor device820may include an inductor circuit for securing signal integrity. For example, the inductor circuit may be connected between the first pads PAD1and the input/output circuit of the semiconductor device820, and may include an inductor pattern and a variable pattern. The variable pattern is separated from the inductor pattern and is a pattern adjacent to the inductor pattern, and may be floated or may receive a predetermined power supply voltage as a bias voltage. In the manufacture of the semiconductor device820, the inductor circuit may be set to provide an inductance value capable of securing signal integrity by measuring the eye margin of a signal input/output by the semiconductor device820while floating a variable pattern or biasing the variable pattern to a power supply voltage.

On the other hand, in the example embodiment illustrated inFIG.17, an inductor circuit817may also be formed on at least one of substrate wirings815connecting second pads PAD2and third pads PAD3. For example, the inductor circuit817may be formed on a signal path that transmits and receives signals at high speed. When the semiconductor device820is a memory device, the inductor circuit817may be connected to a portion of the third pads PAD3that transmits and receives data signals.

FIGS.18and19are diagrams illustrating a semiconductor device according to an example embodiment.

In an example embodiment illustrated inFIG.18, a semiconductor device900may be a volatile memory device. The semiconductor device900may include a plurality of memory cells MC connected to bit lines BL and word lines WL, and each of the plurality of memory cells MC may include a cell switch TR and a cell capacitor CC. For example, by turning on the cell switch TR and charging or discharging the cell capacitor CC, data may be stored in each of the plurality of memory cells MC, and by turning the cell switch TR on and measuring the voltage of the cell capacitor CC, data stored in each of the plurality of memory cells MC may be read.

On the other hand, in the example embodiment illustrated inFIG.19, a semiconductor device900A may be a non-volatile memory device. In the semiconductor device900A illustrated inFIG.19, memory cells MC1-MC8may be formed on a substrate in a three-dimensional structure. For example, a plurality of memory cell strings NS11-NS33included in the semiconductor device900A may be formed in a direction perpendicular to the substrate.

Referring toFIG.19, the semiconductor device900A may include the plurality of memory cell strings NS11-NS33connected between the bit lines BL1-BL3and the common source line CSL. Each of the plurality of memory cell strings NS11-NS33may include a string select transistor SST, a plurality of memory cells MC1-MC8, and a ground select transistor GST. AlthoughFIG.19illustrates that each of the plurality of memory cell strings NS11-NS33includes eight memory cells MC1-MC8, this may be varied.

The string select transistor SST may be connected to a corresponding string select line SSL1-SSL3. The plurality of memory cells MC1to MC8may be respectively connected to corresponding word lines WL1to WL8. One or more of the word lines WL1-WL8may be provided as a dummy word line. The ground select transistor GST may be connected to corresponding ground select line GSL1-GSL3. The string select transistor SST may be connected to the corresponding bit line BL1-BL3, and the ground select transistor GST may be connected to the common source line CSL.

Each of the word lines WL1-WL8may be commonly connected to the plurality of memory cells MC1-MC8disposed at the same height, and ground selection lines GSL1-GSL3and string selection lines SSL1-SSL3may be respectively separated. Although eight word lines WL1-WL8and three bit lines BL1-BL3are illustrated inFIG.19, this may be varied.

The semiconductor devices900and900A according to the example embodiments illustrated inFIGS.18and19may perform operations of receiving and storing data and outputting the stored data at high speed, and may thus operate in synchronization with a clock signal of a significantly high frequency. As the frequency of the clock signal increases, the eye margin of the signal may decrease due to capacitance of a parasitic component present in the input/output signal and in a signal path connecting the input/output signal and the pads. An inductor circuit providing an inductance capable of reducing an effect due to a capacitance of a parasitic component may be connected to the signal path connecting the input/output signal and the pads. In addition, at least one variable pattern may be included in the inductor circuit to adjust the inductance of the inductor circuit, and whether to input a bias voltage to the variable pattern may be selected. Accordingly, signal integrity may be secured in the semiconductor devices900and900A that input and output signals at high speed.

FIG.20is a schematic diagram illustrating a system including a semiconductor device according to an example embodiment.

Referring toFIG.20, a mobile device1000may include a camera1100, a display1200, an audio processing unit1300, a modem1400, DRAMs1500aand1500b,flash memory devices1600aand1600b,and input/output devices1700aand1700b,a sensor device1800, and an application processor (hereinafter, “AP”)1900.

The mobile device1000may be implemented as a laptop computer, a portable terminal, a smartphone, a tablet PC, a wearable device, a healthcare device, or an Internet-of-Things (IoT) device. Also, the mobile device1000may be implemented as a server or a personal computer.

Various components included in the mobile device1000may operate in synchronization with a predetermined clock. For example, the display1200may display a screen according to a predetermined refresh rate, and the DRAMs1500aand1500band the flash memory devices1600aand1600balso store and read data at a predetermined speed, or may operate according to a predetermined clock to send and receive the data with other external devices. The input/output devices1700aand1700band the application processor1900may also operate according to a predetermined clock.

The camera1100may capture a still image or a moving image according to a user's control. The mobile device1000may acquire specific information using a still image/video captured by the camera1100or convert the still image/video into other types of data such as text or the like and may store the converted data. The camera1100may include a plurality of cameras having different angles of view or aperture values. In addition, the camera1100may further include a camera that generates a depth image by using depth information of the subject and/or background, in addition to a camera that generates an actual image by photographing the subject.

The display1200may also be used as an input device of the mobile device1000by providing a touch screen function. In addition, the display1200may be provided integrally with a fingerprint sensor and the like to provide a security function of the mobile device1000. The audio processing unit1300may process audio data stored in the flash memory devices1600aand1600bor audio data included in contents received externally through the modem1400or the input/output devices1700aand1700b.

The modem1400modulates and transmits a signal to transmit/receive wired/wireless data, while demodulating a signal received from the outside to restore an original signal. The input/output devices1700aand1700bare devices that provide digital input/output, and may a port that may be connected to an external recording medium, an input device such as a touch screen or a mechanical button key, and an output device capable of outputting vibrations in a haptic manner or the like.

The sensor device1800may include a plurality of sensors that collect various information from the outside thereof. The sensor device1800may include an illuminance sensor that detects the brightness of light, a gyro-sensor for detecting the movement of the mobile device1000, a biosensor for obtaining biometric information from a user's body in contact with and/or close to the mobile device1000, and the like.

The AP1900may control the overall operation of the mobile device1000. In detail, the AP1900may control the display1200to display a portion of the content stored in the flash memory devices1600aand1600bon the screen. Also, when a user input is received through the input/output devices1700aand1700b,the AP1900may perform a control operation corresponding to the user input.

The AP1900may include an accelerator block1920that is a dedicated circuit for AI data operation. In another implementation, a separate accelerator chip may be provided separately from the AP1900, and a DRAM1500bmay be additionally connected to the accelerator block1920or the accelerator chip. The accelerator block1920is a function block that professionally performs a specific function of the AP1900, and may include a Graphics Processing Unit (GPU) that is a functional block that specializes in processing graphics data, a Neural Processing Unit (NPU) that is a block for professionally performing AI calculations and inference, a Data Processing Unit (DPU) that is a block that specializes in data processing, and the like.

According to example embodiments, an inductor circuit as described above may be variously employed in components connected to each other to communicate with each other in the mobile device1000. For example, according to an example embodiment, the inductor circuit may be applied to a pad for inputting/outputting a signal in at least one of the camera1100, the display1200, the audio processing unit1300, the modem1400, the DRAMs1500aand1500b,the flash memory devices1600aand1600b,the input/output devices1700aand1700b,the sensor device1800, and the AP1900, to improve the eye margin of a signal.

By way of summation and review, a parasitic component may exist in an input/output circuit and between the input/output circuit and a pad. Integrity of a signal that is input/output to the pad may be deteriorated by the parasitic component.

As set forth above, embodiments may provide a semiconductor device in which deterioration of the integrity of signals input/output through a pad may be significantly reduced by connecting an inductor having adjustable inductance to a path connecting an input/output circuit and the pad.

According to example embodiments, by connecting an inductor having adjustable inductance to a path connecting an input/output circuit and a pad, and inductance of the inductor may be set based on the capacitance of a parasitic component present in the path. Therefore, the integrity of the signal input/output through the pad may be secured despite the presence of parasitic components, and performance of a semiconductor device supporting high-speed data communication may be improved.