Power semiconductor device with reduced on-resistance and increased breakdown voltage

In one implementation, a power semiconductor device includes an active region and a termination region. A depletion trench finger extends from the active region and ends in the termination region. An arched depletion trench surrounds the depletion trench finger in the termination region, the arched depletion trench enables one or both of an increased breakdown voltage and a reduced on-resistance in the power semiconductor device.

BACKGROUND

Background Art

Group IV power transistors, such as silicon based trench metal-oxide-semiconductor field-effect transistors (trench MOSFETs) are used in a variety of applications. For example, silicon trench MOSFETs may be used to implement a power converter, such as a direct current (DC) to DC power converter. For power MOSFET applications, it is generally desirable to reduce the on-resistance (Rdson) of the transistor. In addition, it is generally advantageous to have as high a breakdown voltage as is practicable for a desired Rdson.

The Rdsonof a trench MOSFET may be reduced by increasing the carrier concentration in a vertical drift region of the MOSFET. In order to protect against voltage breakdown under such conditions, depletion trenches including buried depletion electrodes may be implemented in order to deplete the drift region when the trench MOSFET is in a blocking state. Achievement of a desirably low Rdsonand a concurrently high breakdown voltage requires that the charge contained in the regions situated adjacent the depletion trenches be consistent and carefully controlled. However, conventional power MOSFETs typically fail to provide the desired control over the charge contained at the MOSFET termination regions.

SUMMARY

The present disclosure is directed to a power semiconductor device with reduced on-resistance and increased breakdown voltage, substantially as shown in and/or described in connection with at least one of the figures, and as set forth more completely in the claims.

DETAILED DESCRIPTION

As stated above, group IV power transistors, such as silicon based trench metal-oxide-semiconductor field-effect transistors (trench MOSFETs) are used in a variety of applications. For example, silicon trench MOSFETs may be used to implement a power converter, such as a direct current (DC) to DC power converter. For most MOSFET applications, it is desirable to reduce the on-resistance (Rdson) of the transistor. In addition, it is generally advantageous to have as high a breakdown voltage as is practicable for a desired Rdson.

The Rdsonof a trench MOSFET may be reduced by increasing the carrier concentration in a vertical drift region of the MOSFET. In order to protect against voltage breakdown under such conditions, depletion trenches including buried depletion electrodes may be implemented in order to deplete the drift region when the trench MOSFET is in a blocking state. Achievement of a desirably low Rdsonand a concurrently high breakdown voltage requires that the charge contained in the regions situated adjacent the depletion trenches be consistent and carefully controlled. However, as noted above, conventional device layouts typically fail to provide the desired control over the charge contained in the semiconductor regions at the device termination.

FIG. 1is a top view of a portion of a semiconductor device showing a conventional device termination layout. Semiconductor device100may be a trench power MOSFET, for example. As shown inFIG. 1, semiconductor device100includes active region102and termination region106. As further shown inFIG. 1, active region102includes semiconductor device unit cells104, which may be trench MOSFET unit cells, for example.

Termination region106is shown to include boundary trench108and depletion trench fingers120extending from active region102toward boundary trench108. Termination region106also includes semiconductor mesa regions110asituated between the sides of adjacent depletion trench fingers120, as well as semiconductor mesa regions110bsituated between the tips of depletion trench fingers120and boundary trench108.

Each of depletion trench fingers120includes vertical field plate or buried depletion electrode124aand trench oxide122adisposed between buried depletion electrode124aand semiconductor mesa regions110aand110b. Boundary trench108includes vertical field plate or buried depletion electrode124band trench oxide122bdisposed between buried depletion electrode124band semiconductor mesa regions110b. Also shown inFIG. 1is an exemplary termination zone112in semiconductor mesa region110b.

In order to provide a trench MOSFET having a desirably low Rdsonwhile concurrently exhibiting an advantageously high breakdown voltage, the charge contained in semiconductor mesa regions110aand110bshould be consistent and carefully controlled. That is to say, the charge present in semiconductor mesa regions110aand110bshould be such that the depletion effect produced by buried depletion electrodes124aand124bis sufficient to protect against voltage breakdown throughout semiconductor mesa regions110aand110bwhen semiconductor device100is in a blocking state.

In semiconductor mesa regions110a, charge may be controlled by utilizing a layout in which depletion trench fingers120are arranged substantially in parallel, with a substantially uniform distance between the sides of adjacent parallel trenches, as shown inFIG. 1. Such a layout assures that the charge contained in semiconductor mesa regions110ais consistent along the lengths of depletion trench fingers120, and experiences substantially similar depletion by two neighboring buried depletion electrodes124ain depletion trench fingers120. In other words, the electric field produced in semiconductor mesa regions110acan be well characterized and well controlled.

In contrast to the conditions experienced by semiconductor mesa regions110a, the layout of termination region106dictates that the charge contained in termination zone112of semiconductor mesa region110bexperiences depletion from three, relatively more distant depletion sources, i.e., buried depletion electrodes124aat the tips of adjacent depletion trench fingers120, and buried depletion electrode124bin boundary trench108. As a result, the electric field produced in termination zone112, as well as semiconductor mesa regions110bas a whole, is less certain, and thus less well controlled than that produced in semiconductor mesa region110a. Consequently, semiconductor device100having the conventional device termination layout shown inFIG. 1may be susceptible to voltage breakdown in semiconductor mesa regions110b.

The present application discloses a semiconductor device having an arched depletion trench providing enhanced resistance to voltage breakdown for a particular Rdson.FIG. 2shows a top view of an exemplary implementation of such a device. Semiconductor device200includes active region202and termination region216. Semiconductor device200may be a power MOSFET, for example, such as a trench MOSFET including trench MOSFET unit cells204formed in active region202. According to the implementation shown inFIG. 2, each of trench MOSFET unit cells204includes gate240, source regions252, and channel contacts254, formed at surface214of semiconductor mesa regions210in active region202.

As shown inFIG. 2, depletion trench fingers220extend from active region202and end in termination region216. Also shown inFIG. 2is arched depletion trench230also extending from active region202into termination region216and surrounding depletion trench fingers220in termination region216. Depletion trench fingers220and arched depletion trench230each includes vertical field plate or buried depletion electrode224and trench dielectric222disposed between buried depletion electrode224and semiconductor mesa regions210. In addition,FIG. 2shows optional boundary trench208including buried depletion electrode224and trench dielectric222.

It is noted that although semiconductor device200will be described as a midvoltage (MV) silicon trench MOSFET in the interests of conceptual clarity, the termination layout disclosed inFIG. 2may be implemented for use with a variety of semiconductor device types. Thus, in other implementations, semiconductor device200may correspond to any one of a variety of power semiconductor devices. For example, in another implementation, semiconductor device200may take the form of a group IV insulated-gate bipolar transistor (IGBT) or diode, for example, or a group III-V transistor or diode, such as a III-Nitride transistor or diode. Moreover, the termination layout disclosed by the present application may be readily adapted for use in a low voltage (LV) or high voltage (HV) group IV or group III-V device.

As used herein, the phrase “group IV” refers to a semiconductor that includes at least one group IV element such as silicon (Si), germanium (Ge), and carbon (C), and may also include compound semiconductors such as silicon germanium (SiGe) and silicon carbide (SiC), for example. Group IV also refers to semiconductor materials which include more than one layer of group IV elements, or doping of group IV elements to produce strained group IV materials, and may also include group IV based composite substrates such as silicon on insulator (SOI), separation by implantation of oxygen (SIMOX) process substrates, and silicon on sapphire (SOS), for example.

In addition, the expression LV in reference to a transistor or switch describes a transistor or switch with a voltage range of up to approximately forty volts (40V), while use of MV refers to a voltage range from approximately forty volts to approximately two hundred volts (approximately 40V to 200V). Moreover, the expression HV refers to a voltage range from approximately two hundred volts to approximately twelve hundred volts (approximately 200V to 1200V), or higher.

As used herein, the phrase “group III-V” refers to a compound semiconductor including at least one group III element and at least one group V element. By way of example, a group III-V semiconductor may take the form of a III-Nitride semiconductor that includes nitrogen and at least one group III element. For instance, a III-Nitride power transistor may be fabricated using gallium nitride (GaN), in which the group III element or elements include some or a substantial amount of gallium, but may also include other group III elements in addition to gallium.

Continuing to refer toFIG. 2, distance232ais shown to extend between the sides of depletion trench fingers220and arched depletion trench230in active region202, while distance232bextends between the tips of depletion trench fingers220and arched depletion trench230in termination region216. As shown by the implementation inFIG. 2, distances232aand232bmay be similar or substantially equal. For example, distance232amay vary by less than approximately twenty percent (20%) from distance232b, such as by approximately fifteen percent (15%), or less.

As a more specific example, where semiconductor device200is implemented as an approximately one hundred volt (100 V) silicon trench MOSFET, distance232amay be approximately 1.4 micrometers (1.4 μm), while distance232bmay be approximately 1.2 μm. As a result, the charge contained in semiconductor mesa regions210is consistent throughout termination region216. Moreover, semiconductor mesa regions210are bordered along their entirety by two symmetrically arranged buried depletion electrodes224, resulting in a substantially similar depletion profile throughout termination region216when semiconductor device200is in a blocking state.

Consequently, the termination layout including arched termination trench230shown inFIG. 2enables one or more of an increased breakdown voltage and a reduced Rdsonfor semiconductor device200. For example, semiconductor device200can be configured to have an Rdsonclose to the theoretical limit for that device without being at significant risk of voltage breakdown in termination region216.

It is noted that althoughFIG. 2shows only a portion of semiconductor device200, the layout geometry represented in that figure can be symmetrical with respect to active region202. In other words, depletion trench fingers220and arched depletion trench230may extend through active region202and emerge below active region202as a mirror image of the termination region layout shown inFIG. 2. As a result, each of depletion trench fingers220may be formed as an island depletion trench finger220surrounded by semiconductor mesa regions210and arched depletion trench230. Moreover, and as noted above, arched depletion trench230may be a single continuous trench having multiple adjoining cells, each cell surrounding one of island depletion trench fingers220. Furthermore, it is reiterated that distances232aand232bmay be substantially equal, so that each cell of continuous arched depletion trench230may include semiconductor mesa region210having an elongated racetrack layout with substantially constant width.

Referring now toFIG. 3,FIG. 3shows a cross-sectional view of trench MOSFET unit cell204in active region202of semiconductor device200, inFIG. 2, in the direction of perspective lines3-3in that figure. As shown inFIG. 3, trench MOSFET unit cell304includes conductive substrate356, shown as an N+ substrate, and N type drift region318situated over conductive substrate356. Conductive substrate356may be a silicon substrate, for example, and may include N type drift region318formed in an epitaxial silicon layer disposed over conductive substrate356. Formation of an epitaxial silicon layer may be performed by any suitable method, as known in the art, such as chemical vapor deposition (CVD) or molecular beam epitaxy (MBE), for example.

More generally, however, N type drift region318may be formed in any suitable group IV layer included in trench MOSFET unit cell304. Thus, in other implementations, N type drift region318need not be formed of silicon. For example, in one alternative implementation, N type drift region318can be formed in either a strained or unstrained germanium layer formed over conductive substrate356. Moreover, in some implementations, trench MOSFET unit cell304may include additional layers, such as an N type buffer or field stop layer situated between conductive substrate356and N type drift region318(buffer or field stop layer not shown inFIG. 3).

Trench MOSFET unit cell304also includes P type channel layer314, gate340including gate dielectric342and gate electrode344formed in gate trench346, N type source regions352adjacent gate trench346, P type channel contacts354, and drain358provided by conductive substrate356. P type channel layer314is formed over N type drift region318, which in turn is formed over conductive substrate356. It is noted that P type channel layer314and P type channel contacts354may be formed through implantation and diffusion of a P type dopant, such as boron (B) in a top surface of N type drift region318. Moreover, N type source regions352may be formed through implantation and diffusion of an N type dopant, such as phosphorus (P) or arsenic (AS), for example.

Also shown inFIG. 3are depletion trench finger320and arched depletion trench330, each including buried depletion electrode324and trench dielectric322, as well as semiconductor mesa region310, and distance332aextending between the side of depletion trench finger320and arched depletion trench330. Depletion trench finger320, arched depletion trench330, buried depletion electrodes324, and trench dielectric322correspond respectively to depletion trench fingers220, arched depletion trench230, buried depletion electrodes224, and trench dielectric222, inFIG. 2. In addition, semiconductor mesa region310, P type channel layer314, gate340, N type source regions352, P type channel contacts354, and distance332a, inFIG. 3, correspond respectively to semiconductor mesa region210, surface214, gate240, source regions252, channel contacts254, and distance232a, inFIG. 2.

Gate dielectric342and trench dielectric322may be formed using any material and any technique typically employed in the art. For example, gate dielectric342and trench dielectric322may be formed of a gate oxide, such as silicon oxide (SiO2), for example, and may be deposited or thermally grown to produce gate dielectric342and trench dielectric322. Gate electrode344and buried depletion electrodes324may also be formed using any material typically utilized in the art. For example, gate electrode344and buried depletion electrodes324may be formed of conductive polysilicon.

As shown inFIG. 3, the trenches used to form depletion trench finger320and arched depletion trench330extend from the surface of P type channel layer314into N type drift region318, and are substantially deeper than gate trench346. For example, in some implementations, the trenches used to form depletion trench finger320and arched depletion trench330may be approximately 5-6 μm deep, while gate trench346may be approximately 1.0 μm deep, or less. It is reiterated that the features depicted inFIG. 3are shown for conceptual clarity and are not drawn to scale.

It is also noted that trench MOSFET unit cell304is merely an exemplary representation, and in other implementations, trench MOSFET unit cell304may include different features, or may include similar features configured differently. For example, one of ordinary skill in the art will readily recognize that in other implementations of a group IV trench MOSFET, gate electrode344and one of buried depletion electrodes324may be disposed in the same deep trench, such as the trench providing depletion trench finger320, with gate electrode344disposed over and electrically isolated from buried depletion electrode324. In such an implementation, P type channel contacts354and N type source regions352may be situated adjacent the deep trench providing depletion trench finger320, at the surface of P type channel layer314.

Buried depletion electrodes324can be used to deplete semiconductor mesa region310of N type drift region318when the trench MOSFET including trench MOSFET unit cell304is in the blocking state, when buried depletion electrodes324are tied to a low electrical potential, e.g., grounded or at a near ground potential. For example, in one implementation, buried depletion electrodes324may be electrically shorted to N type source regions352by a metallization layer formed over the active region including trench MOSFET unit cell304, or by any other technique known in the art.

As noted above, use of buried depletion electrodes324to deplete semiconductor mesa region310of N type drift region318confers several possible advantages. For example, in one implementation, depletion trench finger320and arched depletion trench330including buried depletion electrodes324enable the semiconductor device having unit cell304to sustain a higher breakdown voltage for higher voltage operation. Alternatively, or in addition, depletion trench finger320and arched depletion trench330including buried depletion electrodes324can enable an increased conductivity for N type drift region318while sustaining a desired breakdown voltage. The latter implementation may be desirable because increased conductivity in semiconductor mesa region310of N type drift region318is associated with a reduced Rdsonfor the semiconductor device having unit cell304.

Continuing toFIG. 4,FIG. 4shows a cross-sectional view of termination region216, inFIG. 2, in the direction of perspective lines4-4in that figure. As shown inFIG. 4, termination region416includes conductive substrate456, shown as an exemplary N+ conductive substrate, and N type drift region418situated over conductive substrate456. Termination region416also includes depletion trench finger420and arched depletion trench430each including buried depletion electrode424and trench dielectric422, as well as P type layer414, semiconductor mesa region410, and distance432bbetween the tip of depletion trench finger420and arched depletion trench430. Depletion trench finger420, arched depletion trench430, buried depletion electrodes424, and trench dielectric422correspond respectively to depletion trench fingers220, arched depletion trench230, buried depletion electrodes224, and trench dielectric222, inFIG. 2. In addition, semiconductor mesa region410, distance432b, and P type layer414, inFIG. 4, correspond respectively to semiconductor mesa region210, distance232b, and surface214, inFIG. 2.

Buried depletion electrodes424can be used to deplete semiconductor mesa region410of drift region418when the trench MOSFET having termination region416, is in the blocking state and buried depletion electrodes424are tied to a low electrical potential, e.g., grounded or at a near ground potential. Moreover, because distance432b/232bof between the tip of depletion trench finger420/220and the arched portion of arched depletion trench430/230is similar to or substantially the same as distance332a/232a, the depletion of semiconductor mesa region410/310/210is well characterized and consistent in both active region302/202and termination region416/216.

Thus, a power semiconductor device, such as a power MOSFET, having a termination layout including an arched depletion trench as disclosed herein, can sustain a higher breakdown voltage for a higher voltage operation. Alternatively, or in addition, the termination layout including the arched depletion trench230enables a reduced Rdsonin the semiconductor device, while sustaining a desired breakdown voltage. In some implementations, the power semiconductor device may take the form of a group IV IGBT or diode, for example, having a reduced on-resistance and/or an increased breakdown voltage. In other implementations, the power semiconductor device may take the form of a group III-V transistor or diode, such as a III-Nitride transistor or diode having a reduced on-resistance and/or an increased breakdown voltage. Moreover, and as noted above, the termination layout disclosed by the present application may be readily adapted for use in an LV, MV, or HV group IV or group III-V device. In addition, the termination layout including the arched depletion trench disclosed herein enables a compact design for the semiconductor device and may be implemented without the need for additional masks or processing steps during fabrication of the semiconductor device.