INTEGRATED CIRCUIT DEVICES INCLUDING STACKED TRANSISTORS AND METHODS OF FORMING THE SAME

A method of forming an integrated circuit device includes providing a stacked transistor structure on a substrate. The stacked transistor structure includes a first channel pattern of a first transistor and a second channel pattern of a second transistor stacked on the first channel pattern. Second source/drain regions of the second transistor are formed at opposing ends of the second channel pattern, and an oxidation process is performed to oxidize upper and lower surfaces of the second source/drain regions and side surfaces of the first channel. First source/drain regions of the first transistor are then formed at opposing ends of the first channel pattern. Related devices and fabrication methods are also discussed.

FIELD

The present disclosure relates to integrated circuit devices.

BACKGROUND

Integrated circuit devices may utilize stacked transistors to increase density and improve performance. In some instances, the stacked transistors may be complementary to each other (e.g., complementary metal-oxide-semiconductor (CMOS) transistors). For example, a Complementary-FET (CFET) layout may include multiple vertically stacked pairs of gate-all-around field effect transistors (GAAFETs), with P-type GAAFETs on one-level, N-type GAAFETs on another level (i.e., above or below), and shared gates, where each shared gate extends between and wraps around the channel patterns of the stacked pair of N-type and P-type GAAFETs. In such structures, the source/drain regions of the lower GAAFET are electrically isolated from the source/drain regions of the upper GAAFET by dielectric layers.

As a distance or pitch (e.g., contact poly pitch (CPP)) between gates of the transistors is reduced to increase the density of the integrated circuit devices, it may be more difficult to electrically isolate the upper and lower stacked transistors. Thus, it may be difficult to fabricate CMOS transistors in a stacked arrangement with a relatively high or suitable aspect ratio (A/R).

SUMMARY

According to some embodiments, a method of forming an integrated circuit device includes providing a stacked transistor structure on a substrate, the stacked transistor structure comprising a first channel pattern of a first transistor and a second channel pattern of a second transistor stacked on the first channel pattern; forming second source/drain regions of the second transistor on opposing side surfaces of the second channel pattern; performing an oxidation process to oxidize portions of upper and lower surfaces of the second source/drain regions and opposing side surfaces of the first channel pattern to form first isolation patterns; and then forming first source/drain regions of the first transistor on the opposing side surfaces of the first channel pattern.

In some embodiments, the first source/drain regions are between the substrate and the portions of the lower surfaces of the second source/drain regions that were oxidized.

In some embodiments, forming the second source/drain regions includes forming an insulating layer on the opposing side surfaces of the first channel pattern; and epitaxially growing the second source/drain regions of the second transistor on the opposing side surfaces of the second channel pattern.

In some embodiments, the method further includes forming leakage protection regions comprising insulating patterns on the substrate adjacent the opposing side surfaces of the first channel pattern, where the first source drain/regions are formed on the leakage protection regions.

In some embodiments, forming the leakage protection regions includes recessing the substrate adjacent the opposing side surfaces of the first channel pattern to provide recessed surfaces; and forming the insulating patterns on the recessed surfaces of the substrate adjacent the opposing side surfaces of the first channel pattern. The insulating layer may be formed on the recessed surfaces of the substrate and on the opposing ends of the first channel pattern prior to forming the second source/drain regions, and may be recessed or otherwise reduced in thickness after forming the second source/drain regions to form the insulating patterns in some embodiments.

In some embodiments, forming the leakage protection regions includes performing the oxidation process to form the insulating patterns on surfaces of the substrate adjacent the opposing side surfaces of the first channel pattern.

In some embodiments, forming the first source/drain regions includes removing the side surfaces of the first channel pattern that were oxidized to expose the opposing ends of the first channel patterns; and then epitaxially growing the first source/drain regions of the first transistor at the opposing ends of the first channel pattern.

In some embodiments, the method further includes forming second or additional isolation patterns between the first isolation patterns and upper surfaces of the first source/drain regions, where the first isolation patterns and the second isolation patterns form a device isolation pattern that provides electrical isolation between the first and second source/drain regions.

In some embodiments, prior to forming the second isolation pattern, the method further includes forming epitaxial blocking liner layers on the upper and lower surfaces of the second source/drain regions that were oxidized to form the first isolation patterns. The first isolation patterns, the epitaxial blocking liner layers on the lower surfaces of the second source/drain regions, and the second isolation patterns form a device isolation pattern that provides electrical isolation between the first and second source/drain regions.

In some embodiments, the first source/drain regions comprise a same material composition as the first channel pattern and the substrate.

In some embodiments, the second source/drain regions comprise a different material composition than the first source/drain regions.

In some embodiments, the first source/drain regions are of a first conductivity type, and the second source/drain regions are of a second conductivity type that is opposite to the first conductivity type.

In some embodiments, the second channel pattern comprises silicon, and responsive to performing the oxidation process, silicon portions are provided between the upper and lower surfaces of the second source/drain regions that were oxidized.

In some embodiments, forming the first and second source drain regions is performed without forming blocking spacers on the opposing ends of the second channel pattern, and where the first and second channel patterns have a same channel length.

According to some embodiments, a method of forming an integrated circuit device includes providing a stacked transistor structure directly on a substrate, the stacked transistor structure comprising a first channel pattern of a first transistor and a second channel pattern of a second transistor stacked on the first channel pattern; forming second source/drain regions of the second transistor at opposing ends of the second channel pattern; forming leakage protection regions comprising insulating patterns on the substrate adjacent the opposing ends of the first channel pattern; and then forming first source/drain regions of the first transistor at opposing ends of the first channel pattern, where the first source/drain regions are between the second source/drain regions and the leakage protection regions.

In some embodiments, forming the second source/drain regions includes forming an insulating layer on the opposing side surfaces of the first channel pattern; and epitaxially growing the second source/drain regions of the second transistor on the opposing side surfaces of the second channel pattern.

In some embodiments, forming the leakage protection regions includes recessing the substrate adjacent the opposing ends of the first channel pattern to provide recessed surfaces; forming an insulating layer on the recessed surfaces of the substrate and on opposing ends of the first channel pattern prior to forming the second source/drain regions; and reducing a thickness of the insulating layer to provide the insulating pattern after forming the second source/drain regions.

In some embodiments, the method further includes performing an oxidation process to oxidize upper and lower surfaces of the second source/drain regions and side surfaces of the first channel pattern, prior to forming the first source/drain regions. Forming the first source/drain regions may include removing the side surfaces of the first channel pattern that were oxidized to expose the opposing ends of the first channel pattern; and then epitaxially growing the first source/drain regions of the first transistor at the opposing ends of the first channel pattern.

In some embodiments, forming the leakage protection regions may include performing the oxidation process to form the insulating patterns on surfaces of the substrate adjacent the opposing ends of the first channel pattern.

In some embodiments, the oxidized lower surfaces of the second source/drain regions may provide first isolation patterns, and the method may further include forming second isolation patterns between the first isolation patterns and upper surfaces of the first source/drain regions, where the first isolation patterns and the second isolation patterns form device isolation patterns that electrically isolates the first source/drain regions from the second source/drain regions.

In some embodiments, the method may further include forming epitaxial blocking liner layers on the oxidized upper and lower surfaces of the second source/drain regions, where the first isolation patterns, the epitaxial blocking liner layers on the lower surfaces of the second source/drain regions, and the second isolation patterns form device isolation patterns that electrically isolate the first source/drain regions from the second source/drain regions.

According to some embodiments, an integrated circuit device includes a stacked transistor structure directly on a substrate, the stacked transistor structure comprising a first channel pattern of a first transistor and a second channel pattern of a second transistor stacked on the first channel pattern; first source/drain regions of the first transistor at opposing ends of the first channel pattern; second source/drain regions of the second transistor at opposing ends of the second channel pattern; and leakage protection regions comprising insulating patterns on the substrate adjacent the opposing ends of the first channel pattern, where the first source/drain regions are between the second source/drain regions and the leakage protection regions.

In some embodiments, the substrate may include recessed surfaces adjacent the opposing ends of the first channel pattern, and the insulating patterns at least partially fill the recessed surfaces of the substrate adjacent the opposing ends of the first channel pattern.

In some embodiments, the insulating patterns may be oxidized surfaces of the substrate adjacent the opposing ends of the first channel pattern.

In some embodiments, the second source/drain regions may include oxidized upper and lower surfaces, the oxidized lower surfaces of the second source/drain regions may provide first isolation patterns. The integrated circuit device may further include second or additional isolation patterns between the first isolation patterns and upper surfaces of the first source/drain regions, where the first isolation patterns and the second isolation patterns electrically isolate the first source/drain regions from the second source/drain regions.

In some embodiments, epitaxial blocking liner layers are provided on the oxidized upper and lower surfaces of the second source/drain regions. The first isolation patterns, the epitaxial blocking liner layers on the oxidized lower surfaces of the second source/drain regions, and the second isolation patterns form device isolation patterns that electrically isolate the first source/drain regions from the second source/drain regions.

In some embodiments, the first source/drain regions and the first and second channel patterns comprise silicon, the second source/drain regions comprise a different material than the first source/drain regions, and silicon portions are provided between the oxidized upper and lower surfaces of the second source/drain regions.

According to some embodiments, an integrated circuit device includes a stacked transistor structure on a substrate, the stacked transistor structure comprising a first channel pattern of a first transistor and a second channel pattern of a second transistor stacked on the first channel pattern; first source/drain regions of the first transistor at opposing ends of the first channel pattern; and second source/drain regions of the second transistor at opposing ends of the second channel pattern, where the second source/drain regions comprise oxidized upper and lower surfaces; and epitaxial blocking liner layers on the oxidized upper and lower surfaces of the second source/drain regions.

In some embodiments, the oxidized lower surfaces of the second source/drain regions provide first isolation patterns, and the integrated circuit device may further include second or additional isolation patterns between the first isolation patterns and upper surfaces of the first source/drain regions, where the first isolation patterns, the epitaxial blocking liner layers on the lower surfaces of the second source/drain regions, and the second isolation patterns electrically isolate the first source/drain regions from the second source/drain regions.

In some embodiments, the integrated circuit device further includes leakage protection regions comprising insulating patterns on the substrate adjacent the opposing ends of the first channel pattern, where the first source/drain regions are between the second source/drain regions and the leakage protection regions.

In some embodiments, the first source/drain regions and the first and second channel patterns may include silicon, the second source/drain regions may include a different material than the first source/drain regions, and silicon portions may be provided between the oxidized upper and lower surfaces of the second source/drain regions.

Other devices, apparatus, and/or methods according to some embodiments will become apparent to one with skill in the art upon review of the following drawings and detailed description. It is intended that all such additional embodiments, in addition to any and all combinations of the above embodiments, be included within this description, be within the scope of the invention, and be protected by the accompanying claims.

DETAILED DESCRIPTION OF EMBODIMENTS

In embodiments described herein, a stacked transistor structure may include a first transistor and a second transistor. The first transistor may be a first type of transistor (e.g., a n-type metal-oxide-semiconductor (NMOS) transistor) and the second transistor may be a second type of transistor (e.g., a p-type metal-oxide-semiconductor (PMOS) transistor). The first and second types of transistors may be complementary to each other (e.g., CMOS transistors), and in some embodiments the stacked transistor may be or may include a stack of CMOS transistors. The first and second transistors may be stacked in any order (e.g., with the first transistor on top of the second transistor, or the second transistor on top of the first transistor), resulting in a stack comprising a top device (also referred to herein as an upper device or upper transistor, relative to an underlying substrate) and a bottom device (also referred to herein as a lower device or lower transistor, relative to the underlying substrate).

Some embodiments of the present disclosure may arise from realization that as CPP between transistor gates decreases, isolation between upper and lower devices (e.g., for CMOS configurations) in stacked arrangements with high A/R may become more difficult. Also, control of source/drain leakage current may become more important in stacked arrangements with high A/R.

Embodiments of the present disclosure provide integrated circuit devices having stacked transistor structures (such as a CPP 3D stacked FET in a CMOS configuration) with relatively high A/R. Some embodiments achieve electrical isolation between upper and lower devices of the stacked transistor structures using oxidation processes (e.g., plasma oxidation or thermal oxidation), and in particular embodiments, oxidation of (i) sidewalls of the channel patterns of the lower devices and (ii) the outermost layers or surfaces of the source/drain regions of the upper devices. For example, after growing an upper epitaxial layer for the upper source/drain regions (e.g., having a boron-doped silicon (B: Si) layer at the outermost part or at upper and lower surfaces), oxidation may be performed on the channel patterns of the lower devices and on surfaces (e.g., upper and/or lower surfaces) of the source/drain regions of the upper devices (e.g., the upper epitaxial layers), and then the lower device source/drain regions (e.g., the lower epitaxial layers) may be grown to fabricate a CMOS transistor.

Embodiments of the present disclosure may thereby form upper and lower device isolation patterns by oxidation of outermost layers or surfaces of the upper device source/drain regions. Embodiments of the present disclosure may further form leakage protection areas in the stacked transistor structure, for example, by forming lower device source/drain regions over a recess in the substrate that is at least partially filled with an oxide or other insulating pattern). In some embodiments, CMOS devices can be created from relatively small CPP 3D stacked FET with high A/R through oxidation of the outermost surfaces of an Si layer of upper device source/drain regions, while creating a leakage protection area. As such, embodiments of the present disclosure may prevent electrical contact between the top transistor (e.g., the upper S/D) and the bottom transistor (e.g., the lower S/D) in a stacked transistor structure, even as CPP is reduced.

FIG.1is a cross-sectional view illustrating an example configuration of a semiconductor integrated circuit device100according to some embodiments of the present disclosure. As shown inFIG.1, an integrated circuit device includes a stacked transistor structure105including first and second transistors101,102vertically stacked on a substrate110. The first transistor101includes at least one first channel pattern111between conductive gate patterns104. The second transistor102includes at least one second channel pattern112between gate patterns104. In the example ofFIG.1, multiple second channel patterns112are stacked on multiple first channel patterns111, with the gate patterns104alternatingly stacked between the channel patterns111,112, but embodiments of the present disclosure may include fewer or more channel patterns than shown. The channel patterns may be provided by semiconductor materials, such as silicon (Si). The stacked transistor structure105may further include inner spacers108(e.g., formed of insulating or dielectric materials, for example, SiOCN or other low-k dielectric material), and additional semiconductor (e.g., Si) and insulator (e.g., SiN, SiO) layers stacked on the channel patterns.

First source/drain regions121of the first transistor101are provided on opposing sides (also referred to herein as opposing ends) of the first channel patterns111, and second source/drain regions122of the second transistor102are provided on opposing sides or ends of the second channel patterns112. Gate insulating patterns106(e.g., silicon nitride patterns) may be provided on opposing sides of the gate patterns104to electrically insulate the gate patterns104from the first and second source/drain regions121and122. In some embodiments, the first source/drain regions121may include a same material or material composition as the first channel pattern and the substrate110. For example, the first channel patterns111and the first source/drain regions121may be implemented as silicon layers. In some embodiments, the second source/drain regions122may include a different material or material composition than the first source/drain regions121. For example, the second channel patterns112may be implemented as silicon germanium (SiGe) layers.

In the example ofFIG.1, the first (lower) transistors101and second (upper) transistors102have complementary conductivity types, e.g., to provide a CMOS device. In particular, the first transistors101may have a first conductivity type (e.g., n-type), while the second transistors102may have a second conductivity type (e.g., p-type) that is opposite to the first conductivity type, or vice versa. That is, stacked transistor structures105according to embodiments of the present disclosure are not limited to particular orientations of transistors having the different conductivity types. Moreover, the first and second transistors101and102may have the same conductivity type (e.g., both the first and second transistors101and102may be n-type, or both the first and second transistors101and102may be p-type) in some embodiments. Also, while illustrated with reference to first and second transistors101and102, it will be understood that stacked transistor structures105according to embodiments of the present disclosure are not limited to two-transistor arrangement, and may include additional transistors (e.g., third transistors, fourth transistors, etc.) that are vertically stacked on the substrate110.

Still referring toFIG.1, upper and lower surfaces122U and122L of the second source/drain regions122include insulating (e.g., oxidized) portions that provide first isolation patterns115between the first source/drain regions121and the second source/drain regions122. For example, as described in greater detail below with reference toFIGS.5Ato5H2and FIGS.6A to6H2, one or more oxidation processes (such as plasma oxidation or thermal oxidation) may be performed on exposed upper122U and/or lower surfaces122L of the second source/drain regions122such that oxide layers are formed, also referred to herein as oxidized portions or surfaces of the second source/drain regions122. In some embodiments, portions of the second source/drain regions122may not be fully oxidized, such that non-oxidized semiconductor (e.g., silicon) portions122X remain or are otherwise provided between the upper and lower surfaces122U and122L of the second source/drain regions122and the oxidized portions thereof that provide the first isolation patterns115.

Second isolation patterns116may be provided on the first isolation patterns115(e.g., on the oxidized upper and lower surfaces122U and122L of the second source/drain regions122). The first and second isolation patterns115and116between the second source/drain regions122and the first source/drain regions121collectively define device isolation patterns118that provide electrical isolation between the first and second transistors101and102. In particular, the oxidized lower surfaces122L of the second source/drain regions122that provide the first isolation patterns115and the second isolation patterns116may define device isolation patterns118that provide electrical isolation between the lower surfaces122L of the second source/drain regions122and upper surfaces121U of the first source/drain regions121. The device isolation patterns118including the first isolation patterns115and second isolation patterns116as described herein may effectively provide electrical isolation between the first and second transistors101and102even as CPP is reduced and/or A/R is increased.

As also shown inFIG.1, leakage protection regions120are provided on the substrate110adjacent the opposing sides of the first channel pattern, such that the first source/drain regions121are between the second source/drain regions122and the leakage protection regions120. The leakage protection regions120may be implemented by insulating patterns120aformed in or on the substrate110. For example, in some embodiments as described in greater detail below with reference toFIGS.5Ato5H2, the substrate110may include recessed surfaces110R adjacent the opposing sides113of the first channel patterns111, and the insulating patterns120aat least partially fill the recessed surfaces110R to provide the leakage protection regions120. In some embodiments, the insulating patterns120amay be oxide-based (e.g., silicon oxide) patterns. In some embodiments, the insulating patterns120amay be nitride-based (e.g., silicon nitride) patterns. Other insulating materials (e.g., SiO2, SiON, SiOCN, SiBCN, SiCN, etc.) may also be used as the insulating patterns120a, such that the leakage protection regions120may be the same material or may be a different material than the first and second isolation patterns115and116. The leakage protection regions120are thereby provided between the first source/drain regions121and the substrate110.

FIG.2is a cross-sectional view illustrating an example configuration of a semiconductor integrated circuit device200according to some embodiments of the present disclosure. As shown inFIG.2, an integrated circuit device200includes a similar stacked transistor structure105as described above with reference to the integrated circuit device100ofFIG.1, including first channel patterns111of a first transistor101and second channel patterns112of a second transistor102stacked on the first channel pattern, first source/drain regions121of the first transistor101on opposing sides of the first channel pattern, and second source/drain regions122of the second transistor102on opposing sides of the second channel pattern. Upper and lower surfaces122U and122L of the second source/drain regions122include insulating (e.g., oxidized) portions or layers thereon that provide first isolation patterns115. In some embodiments, non-oxidized semiconductor portions122X of the second source/drain regions122may remain or may otherwise be provided between the upper and lower surfaces122U and122L of the second source/drain regions122and the oxidized portions thereof that provide the first isolation patterns115. Second isolation patterns116are provided between the lower surfaces122L of the second source/drain regions122and upper surfaces121U of the first source/drain regions121.

In addition,FIG.2further illustrates that one or more blocking liner layers230are provided on the first isolation patterns115(e.g., the oxidized portions) on the upper and lower surfaces122U and122L of the second source/drain regions122. The blocking liner layers230may be configured to prevent epitaxial growth, and may also be referred to herein as epitaxial blocking liner layers230or epi blocking liners230. The epi blocking liners230formed on the upper and lower surfaces122U and122L of the second source/drain regions122may have the same thickness, or may have different thicknesses. The epi blocking liners230may provide further separation and electrical isolation between the first and second transistors101and102in the stacked transistor structure105. As such, the first isolation patterns115on lower surfaces122L of the second source/drain regions122, the epitaxial blocking liner layers230, and the second isolation patterns116collectively define device isolation patterns218that provide electrical isolation between the first and second source/drain regions121and122. In some embodiments, the epi blocking liners230may have a thickness of about 4 nm or less, which may be sufficient to provide electrical isolation between the first and second transistors101and102without substantially increasing capacitance.

The blocking liner layers230may include a different material than the first and second isolation patterns115and116in some embodiments. For example, where the first and second isolation patterns115and116are formed as oxide layers, the epi blocking liners230may be formed as nitride layers. The oxidized lower surfaces122L of the second source/drain regions122that provide the first isolation patterns115, the nitride epitaxial blocking liner layers230, and the second isolation pattern may thereby define an oxide-nitride-oxide (ONO) structure that provides electrical isolation between the first and second source/drain regions121and122.

As in the integrated circuit device100ofFIG.1, the integrated circuit device200further includes leakage protection regions120provided by insulating patterns120aon the substrate110adjacent the opposing sides of the first channel pattern and between the first source/drain regions121and the substrate110. The leakage protection regions120may be formed of the same material or a different material than the first and second isolation patterns115,116and/or the epitaxial blocking liner layers230. For example, in some embodiments, the leakage protection regions120may be oxide-based (e.g., SiO) patterns. In some embodiments, the leakage protection regions120may be nitride-based (e.g., SiN) patterns.

FIG.3is a cross-sectional view illustrating an example configuration of a semiconductor integrated circuit device300according to some embodiments of the present disclosure. As shown inFIG.3, an integrated circuit device300includes a similar stacked transistor structure105as described above with reference to the integrated circuit device100ofFIG.1, including first channel patterns111of a first transistor101and second channel patterns112of a second transistor102stacked on the first channel patterns111, first source/drain regions121of the first transistor101on opposing sides of the first channel patterns111, and second source/drain regions122of the second transistor102on opposing sides of the second channel pattern. Upper and lower surfaces122U and122L of the second source/drain regions122include insulating (e.g., oxidized) portions that provide first isolation patterns115. In some embodiments, non-oxidized semiconductor portions122X of the second source/drain regions122may remain or may otherwise be provided between the upper and lower surfaces122U and122L of the second source/drain regions122and the oxidized portions thereof that provide the first isolation patterns115. Second isolation patterns116are provided between the lower surfaces122L of the second source/drain regions122and upper surfaces121U of the first source/drain regions121. The combination of the second isolation patterns116and the oxidized lower surfaces122L of the second source/drain regions122that define the first isolation patterns115form a device isolation pattern that provides electrical isolation between the first and second source/drain regions121and122, as in the embodiment ofFIG.1.

In addition, the integrated circuit device300includes leakage protection regions320provided by insulating patterns320aon the substrate110adjacent the opposing sides of the first channel pattern, where the leakage protection regions320are between the first source/drain regions121and the substrate110. The integrated circuit device300ofFIG.3may differ from the integrated circuit device100ofFIG.1in implementation of the leakage protection regions320. In particular, the insulating patterns320athat provide the leakage protection regions320may be formed on surfaces of the substrate110adjacent the opposing sides of the first channel pattern, for instance, by one or more oxidation processes. For example, as described in greater detail below with reference toFIGS.6Ato6H2, the insulating patterns320amay be oxide patterns formed by oxidizing surfaces of the substrate110adjacent the opposing sides of the first channel pattern. In some embodiments, the insulating patterns320adefining the leakage protection regions320may be formed during the same oxidation process used to oxidize the upper and lower surfaces122U and122L of the second source/drain regions122to provide the first isolation patterns115.

FIG.4is a cross-sectional view illustrating an example configuration of a semiconductor integrated circuit device400according to some embodiments of the present disclosure. As shown inFIG.4, an integrated circuit device400includes a similar stacked transistor structure105as described above with reference to the integrated circuit device300ofFIG.3. In addition,FIG.4further illustrates that one or more epitaxial blocking liner layers230are provided on the first isolation patterns115(e.g., the oxidized portions) on the upper and lower surfaces122U and122L of the second source/drain regions122, similar to the integrated circuit device200ofFIG.2. As such, the combination of the first isolation patterns115on the lower surfaces122L of the second source/drain regions122, the epitaxial blocking liner layers230, and the second isolation patterns116collectively define device isolation patterns218that provide electrical isolation between the first and second source/drain regions121and122.

The epitaxial blocking liner layers230may include a different material (e.g., nitride) than the first and second isolation patterns115and116(e.g., oxide) in some embodiments. For example, as discussed above with reference to the embodiment ofFIG.2, the oxidized lower surfaces122L of the second source/drain regions122that provide the first isolation patterns115, the epitaxial blocking liner layers230, and the second isolation patterns116define an oxide-nitride-oxide (ONO) structure that provides electrical isolation between the first and second source/drain regions121and122. In some embodiments, the epi blocking liners230may have a thickness of about 4 nm or less, which may be sufficient to provide electrical isolation between the first and second transistors101and102without substantially increasing capacitance.

As such, embodiments of the present disclosure may allow for improved fabrication of device isolation patterns118,218between the source/drain regions of upper and lower transistors101,102(with or without epitaxial blocking liner layers230), and/or leakage protection regions120,320between the source/drain regions of the lower transistors and the substrate110in a stacked transistor structure105. In some embodiments, the source/drain regions of the upper transistors may be formed prior to forming the source/drain regions of the lower transistors in the stacked structure, as described in greater detail below with reference toFIGS.5Ato5H2and6A to6H2. However, embodiments of the present disclosure are not limited to such a fabrication order. For example, in embodiments where the upper and lower transistors have complimentary conductivity types (e.g., CMOS devices), first source/drain regions121that include the same material as the first channel patterns111may be epitaxially grown from ends of the first channel patterns111after fabricating second source/drain regions122that include a different material than the second channel patterns112(such that oxidized surfaces of the first channel patterns111may be re-grown during formation of the first source/drain regions121), regardless of the relative positions of the first and second source/drain regions121and122in the stacked structure, such that fabrication operations for forming blocking spacers on side surfaces of the channel patterns111,112during growth of the source/drain regions may be omitted.

FIGS.5A,5B,5C,5D,5E,5F,5G1,5G2,5H1, and5H2are schematic cross-sectional views illustrating methods of fabricating semiconductor integrated circuit devices according to some embodiments of the present disclosure. The methods ofFIGS.5Ato5H2are described below with reference toFIG.7, which is a flowchart700illustrating methods of fabricating semiconductor integrated circuit devices according to some embodiments of the present disclosure.

As shown inFIGS.5A and7, a stacked transistor structure105including a first channel pattern of a first transistor101and a second channel pattern of a second transistor102stacked on the first channel pattern is provided directly on a substrate110(block702). In particular, as shown inFIG.5A, a layer stack including alternating gate layers and channel layers is formed directly on a substrate110, free of buried oxide layers or punch through stopper ion implanted regions therebetween. The layer stack is patterned to form a stacked transistor structure105including alternating gate patterns104and channel patterns111,112on the substrate110. Gate insulating patterns106and inner spacers108may be formed along side surfaces of the gate patterns104and channel patterns111,112. The inner spacers108may be formed of a low-k material (e.g., a nitride, such as SiOCN) or other insulating material. The gate insulating patterns106may be formed of an insulating material (e.g., SiN) different than that of the inner spacers108.

Still referring toFIG.5A, the substrate110is recessed adjacent the opposing sides113of the first channel patterns111to form recessed surfaces110R or recesses (relative to the surfaces of the substrate110having the stacked transistor structures105thereon), and an insulating layer120L is formed in the recesses110R. For example, the substrate110may be etched (e.g., during the patterning of the alternating gate layers and channel layers) to form the recesses110R, and the recesses110R may be filled with an insulating layer120L (e.g., silicon oxide). In some embodiments, a spin on glass (SOG) and high A/R polysilicon (HARP) etching and deposition process may be performed to form the insulating layer in the recesses110R, and a chemical mechanical polishing (CMP) process may be performed to form the insulating layer with a substantially planar surface opposite the substrate110. As shown inFIG.5B, the insulating layer120L is recessed to expose opposing sides of the second (upper) channel patterns.

As shown inFIGS.5C and7, second source/drain regions122of the second transistor102are formed on the opposing sides114of the second channel patterns112(block704). The second source/drain regions122may include a second semiconductor material that is different from a first semiconductor material of the second channel patterns112. For example, the second channel patterns112may be silicon (Si), while the second source/drain regions122may be silicon germanium (SiGe). In some embodiments, the second source/drain regions122may be formed by selective epitaxial growth at the opposing sides114of the second channel patterns112. That is, forming the second source/drain regions122may include epitaxially growing the second source/drain regions122of the second transistor102on the opposing sides114of the second channel patterns112while the insulating layer120L remains on the opposing sides113of the first channel patterns111(thereby preventing growth thereon without additional fabrication steps for forming and subsequently removing blocking spacers). The upper and lower surfaces122U and122L of the second source/drain regions122may include portions122X of the first semiconductor material thereon. InFIG.5D, the insulating layer120L may be further recessed to expose side surfaces111S of the first (lower) channel patterns.

As shown inFIGS.5E and7, an oxidation process is performed to oxidize upper and lower surfaces122U and122L of the second source/drain regions122(block706). The oxidation process may be, for example, plasma oxidation or thermal oxidation. The oxidized upper and lower surfaces122U and122L of the second source/drain regions122form first isolation patterns115. In some embodiments, the upper and lower surfaces122U and122L of the second source/drain regions122may not be fully oxidized, such that non-oxidized portions122X of the first semiconductor material (e.g., silicon) may remain between the upper and lower surfaces122U and122L of the second source/drain regions122and the oxidized portions thereof that provide the first isolation patterns115. For example, responsive to performing the oxidation process, the upper122U and/or lower surfaces122L of the second source/drain regions122may include a silicon sub layer122X and a silicon oxide sub layer115on the silicon sub layer122X. In addition, the side surfaces111S of the first channel patterns111(which were exposed by recessing the insulating layer120L inFIG.5D) are oxidized during the oxidation process (block706).

As shown inFIGS.5F and7, insulating patterns120aare formed on the substrate110adjacent the opposing sides of the first channel pattern to provide leakage protection regions120(block706). In the example ofFIG.5F, the insulating patterns120aof the leakage protection regions120are formed by further removing or recessing or otherwise reducing a thickness of the insulating layer120L. In addition, the oxidized side surfaces111S of the first channel pattern are removed inFIG.5F, such that opposing sides or ends of the first channel patterns111are recessed relative to the gate insulating patterns106on side surfaces of the gate patterns104. For example, a pre-cleaning operation may be performed to remove the oxidized side surfaces111S of the first channel patterns111to expose the opposing ends of the first channel patterns111. In some embodiments, the pre-cleaning operation may also reduce a thickness of the leakage protection regions120on the substrate110adjacent the opposing sides113of the first channel patterns111. That is, in some embodiments, the pre-cleaning process to remove the oxidized side surfaces111S of the first channel patterns111can be performed in same step as reducing the thickness of the insulating layer120L to form the insulating patterns120aof the leakage protection regions120.

As shown in FIGS.5G1and7, first source/drain regions121of the first transistor101are formed on the opposing sides of the first channel pattern (block708), and between the leakage protection regions120on the substrate110and the lower surfaces122L of the second source/drain regions122that were oxidized. The first source/drain regions121may include a first semiconductor material that is the same as that of the first channel patterns111. For example, the first channel patterns111and the first source/drain regions121may be silicon. The first source/drain regions121may be formed by selective epitaxial growth at the opposing sides113of the first channel patterns111, from which the oxidized portions were removed inFIG.5F. That is, forming the first source/drain regions121may include epitaxially growing the first source/drain regions121of the first transistor101on the opposing sides of the first channel pattern after forming the second source/drain regions122of the second transistor, without additional fabrication steps for forming and removing blocking spacers on the opposing sides114of the second channel patterns112to prevent undesired epitaxial growth. Also, by epitaxially growing the first source/drain regions121of the same semiconductor material at the opposing ends113of the first channel patterns111, portions of the first channel patterns111that were removed when removing the oxidized side surfaces111S may be re-grown, such that the overall lengths of the first channel patterns111are restored or otherwise maintained. As such, the first and second channel patterns111and112may have the same or substantially similar channel lengths.

As shown in FIGS.5G2and7, in some embodiments, one or more epitaxial blocking liner layers230may be optionally formed on the oxidized upper and lower surfaces122U and122L of the second source/drain regions122that form the first isolation patterns115(block710). The epitaxial blocking liner patterns may be formed of a different insulating material (e.g., a nitride material) than the oxide material of the first isolation patterns115. The epitaxial blocking liner patterns may further be formed on the upper surfaces121U of the first source/drain regions121, and on sidewall portions vertically extending between the first source/drain regions121and the second source/drain regions122, with a same thickness or with a different thickness than on the upper and lower surfaces122U and122L of the second source/drain regions122. In some embodiments, the epitaxial blocking liner layers230may have a thickness of about 4 nm or less.

As shown in FIGS.5H1,5H2, and7, second isolation patterns116are formed between the oxidized lower surfaces122L of the second source/drain regions122and upper surfaces121U of the first source/drain regions121(block712), as well as on the oxidized upper surfaces of the second source/drain regions122. In the example of FIG.5H1, the oxidized lower surfaces122L of the second source/drain regions122(which form the first isolation patterns115) and the second isolation patterns116collectively define the device isolation patterns118that provide electrical isolation between the first and second source/drain regions121and122. In the example of FIG.5H2, the oxidized lower surfaces122L of the second source/drain regions122(which form the first isolation patterns115), the epitaxial blocking liner layers230, and the second isolation patterns116collectively define the device isolation patterns118. In FIG.5H2, the device isolation patterns118may provide a multi-layer structure including alternating layers of different materials (e.g., an ONO structure or ONON structure) that provide electrical isolation between the first and second source/drain regions121and122.

FIGS.6A,6B,6C,6D,6E,6F,6G1,6G2,6H1, and6H2are schematic cross-sectional views illustrating methods of fabricating semiconductor integrated circuit devices according to further embodiments of the present disclosure. The methods ofFIGS.6Ato6H2are described below with reference to the flowchart700ofFIG.7,

As shown inFIGS.6A and7, a stacked transistor structure105including a first channel pattern of a first transistor101and a second channel pattern of a second transistor102stacked on the first channel pattern is provided directly on a substrate110(block702), free of buried oxide layers or punch through stopper ion implanted regions therebetween. In particular, as similarly described above with reference toFIG.5A, a stacked structure including alternating gate layers and channel layers is formed directly on a substrate110, the stacked structure is patterned to form a stacked transistor structure105including alternating gate patterns104and channel patterns111,112on the substrate110, and gate insulating patterns106and inner spacers108may be formed along side surfaces of the gate patterns104and channel patterns111,112.

Still referring toFIG.6A, an insulating layer120L (e.g., silicon oxide) is formed on surfaces of the substrate110at opposing sides of the stacked transistor structure105, for example, using a SOG and HARP deposition process. The surfaces of the substrate110including the insulating layer120L thereon may be coplanar with the surface of the substrate110including the stacked transistor structure105. That is, in contrast to the example ofFIG.5A, the substrate110may not be recessed prior to forming the insulating layer120L thereon. A CMP process may be performed to form the insulating layer120L with a substantially planar surface opposite the substrate110. As shown inFIG.6B, the insulating layer120L is recessed to expose opposing sides of the second (upper) channel patterns.

As shown inFIGS.6C and7, second source/drain regions122of the second transistor102are formed on the opposing sides114of the second channel patterns112(block704), in a manner similar to that described above with reference toFIG.5C. As such, the second source/drain regions122may include a second semiconductor material (e.g., SiGe) that is different from a first semiconductor material of the second channel patterns112(e.g., Si). The second source/drain regions122may be formed by selective epitaxial growth at the opposing sides114of the second channel patterns112while the insulating layer120L remains on the opposing sides113of the first channel patterns111, thereby preventing growth thereon without additional fabrication steps for forming and subsequently removing blocking spacers. The upper and lower surfaces122U and122L of the second source/drain regions122may include portions of the first semiconductor material thereon.

InFIG.6D, the insulating layer120L may be removed to expose sides surfaces111S of the first (lower) channel patterns, and to expose the surfaces of the substrate110at opposing sides of the stacked transistor structure105. For example, a SOG strip process may be performed to remove the insulating layer120L at the side surfaces111S of the first channel patterns111and at the surfaces of the substrate110therebetween.

As shown inFIGS.6E and7, an oxidation process (e.g., plasma or thermal oxidation) is performed to oxidize upper and lower surfaces122U and122L of the second source/drain regions122(block706). As similarly discussed above with reference toFIG.5E, the oxidized upper and lower surfaces122U and122L of the second source/drain regions122form first isolation patterns115. Likewise, as discussed above, the upper and lower surfaces122U and122L of the second source/drain regions122may not be fully oxidized, such that non-oxidized portions of the first semiconductor material (e.g., silicon) may remain.

In addition, the side surfaces111S of the first channel patterns111and the surfaces of the substrate110adjacent or between the opposing sides113of the first channel patterns111(which were exposed by removing the insulating layer120L inFIG.6D) are oxidized during the oxidation process (block706). That is, the surfaces of the substrate110adjacent the opposing sides of the first channel pattern may be oxidized during the same oxidation process used to form the oxidized upper and lower surfaces122U and122L of the second source/drain regions122to provide the first isolation patterns115.

As shown inFIGS.6F and7, the oxidized surfaces of the substrate110are reduced in thickness to form insulating patterns320a(i.e., oxide patterns) on the substrate110adjacent the opposing sides of the first channel pattern to provide leakage protection regions320(block706). The oxidized side surfaces111S of the first channel pattern are also removed, such that the opposing sides or ends of the first channel patterns111are recessed relative to the gate insulating patterns106on side surfaces of the gate patterns104. For example, a pre-cleaning process may be performed to remove the oxidized side surfaces111S of the first channel patterns111and/or to reduce the thickness of the oxidized surfaces of the substrate110adjacent the opposing sides113of the first channel patterns111.

As such, in contrast to forming the leakage protection regions by recessing the substrate110and forming an insulating layer120L on the recessed surfaces110R of the substrate110(as in the examples ofFIGS.5Ato5H2), the insulating patterns320aof the leakage protection regions320may be formed on surfaces of the substrate110adjacent the opposing sides of the first channel pattern, without recessing the substrate110and in the same oxidation process (block706) used to form the first isolation patterns115on the upper and lower surfaces122U and122L of the second source/drain regions122.

As shown in FIGS.6G1and7, first source/drain regions121of the first transistor101are formed on the opposing sides of the first channel pattern (block708) between the oxide patterns320aof the leakage protection regions320and the oxidized lower surfaces122L of the second source/drain regions122. The first source/drain regions121may include a first semiconductor material (e.g., Si) that is the same as that of the first channel patterns111. The first source/drain regions121may be formed by selective epitaxial growth at the opposing sides113of the first channel patterns111(from which the oxidized portions were removed inFIG.6F), without additional fabrication steps for forming and removing blocking spacers on the opposing sides114of the second channel patterns112to prevent undesired epitaxial growth, and such that the first and second channel patterns111and112may have the same or substantially similar channel lengths (by re-growing the portions of the first channel patterns111that were removed inFIG.6F).

As shown in FIGS.6G2and7, in some embodiments, one or more epitaxial blocking liner layers230of a different insulating material (e.g., a nitride material) may be optionally formed on the oxidized upper and lower surfaces122U and122L of the second source/drain regions122(block710), as well as on the upper surfaces121U of the first source/drain regions121, and on sidewall portions vertically extending between the first source/drain regions121and the second source/drain regions122, as similarly described above with reference to FIG.5G2.

As shown in FIGS.6H1,6H2, and7, second isolation patterns116are formed between the oxidized lower surfaces122L of the second source/drain regions122and upper surfaces121U of the first source/drain regions121(block712), as well as on upper surfaces122U of the second source/drain regions122. In the example of FIG.6H1, the first isolation patterns115and the second isolation patterns116collectively define the device isolation patterns118that provide electrical isolation between the first and second source/drain regions121and122. In the example of FIG.6H2, the first isolation patterns115, the epitaxial blocking liner layers230, and the second isolation patterns116collectively define the device isolation patterns118with a multi-layer structure including alternating layers of different materials (e.g., an ONO structure or ONON structure).

Advantages of structures, features, or operations for using oxidation processes disclosed herein may include, for example, fabrication of upper and lower transistors in a stacked transistor structure while omitting formation of blocking spacer layers, which may typically be used in CMOS implementation methods with small CPP. Also, an epi blocking liner (e.g., an SiN liner) of top and bottom devices can optionally use the same thickness. The epi blocking liner may provide further separation and electrical isolation between the upper and lower transistors in the stacked transistor structure. In some embodiments, the epi blocking liner may have a thickness of about 4 nm or less, which may be sufficient to provide electrical isolation between the upper and lower transistors without substantially increasing unintended or undesired capacitance. That is, the epi blocking liner may be formed as thin as possible to provide sufficient electrical isolation between the upper and lower source/drain regions while minimizing increased capacitance. However, embodiments of the present disclosure are not limited thereto.

Some conventional devices may form a bottom device through inner spacer blocking of a top device, and then forming a top device. However, due to the inner spacer formation, the channel length of the top and bottom device may be different. Also, some conventional devices may isolate top and bottom transistor structures through SD EPI oxidation when forming CMOS in CFET, but may not provide leakage protection as described herein. Rather, such conventional devices may be formed on substrates including punch through stopper ion implantation (PTS IIP) or buried oxide (BOX) layers, in contrast to the operations for forming the stacked transistor structure including the channel patterns and gate patterns directly on a surface of the substrate, and subsequently providing leakage protection areas on surfaces of the substrate between adjacent channel pattern stacks as described herein. Thus, embodiments of the present disclosure may address or overcome limitations relating to blocking spacer formation, top and bottom isolation implementation methods in small CPP, and/or unequal channel lengths between upper and lower transistor structures, while reducing or minimizing leakage current.

Embodiments of the present disclosure may thereby provide methods for fabricating 3D stacked transistor structures with improved isolation between the upper and lower transistors by performing one or more oxidation processes (plasma or thermal) as described herein. The oxidation process(es) may oxidize the upper transistor S/D regions (to form first isolation patterns, which may include epitaxial blocking patterns thereon); the sides of the lower transistor channel regions (for subsequent removal and regrowth during formation of the lower S/D regions); and in some embodiments, surfaces of the substrate at the base of the stacked transistor structures (to form leakage protection regions). This may allow first isolation patterns to be formed on the underside of the upper S/D regions before forming the lower S/D regions, while forming the upper and lower transistor channel regions with the same channel lengths, and eliminating fabrication process steps to form blocking spacers.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Further, all terms should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In the description above, each example embodiment is described with reference to regions of particular conductivity types. It will be appreciated that opposite conductivity type devices may be formed by simply reversing the conductivity of the n-type and p-type layers in each of the above embodiments. Thus, it will be appreciated that the present invention covers both n-channel and p-channel devices for each different device structure.

It will be understood that, although the terms “first,” “second,” etc. are used throughout this specification to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. The term “and/or” includes any and all combinations of one or more of the associated listed items.

Spatially relative terms such as “below” or “above” or “upper” or “lower” or “top” or “bottom” may be used herein to describe a relationship of one element, layer or region to another element, layer or region based on a frame of reference (e.g., a substrate), as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

Example embodiments are described herein with reference to the accompanying drawings, which may include cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures). Many different forms and embodiments are possible without deviating from the teachings of this disclosure. Accordingly, the disclosure should not be construed as limited to the example embodiments set forth herein. As such, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined herein. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected.

Embodiments of the invention are also described with reference to a fabrication operations and flowchart diagrams. It will be appreciated that the steps shown in the fabrication operations and flowchart diagrams need not be performed in the order shown.