Sense-write circuit for random access memory

A sense-write circuit for use with a emitter coupled logic memory array is provided. A first differential stage includes a pair of emitter-coupled transistors connected to a current source controlled by a chip select voltage. A first one of the emitter-coupled transistors has its base connected to a first reference voltage and the second one of said transistors has its base coupled to a write enable input. The collector of a first one of the emitter-coupled transistors serves as a current source for a second differential stage including a second pair of emitter-coupled transistors, a first one having its base connected to a second reference voltage and the second having its base coupled to a data input conductor. The two respective outputs of the second differential stage are coupled to emitter follower drivers, and are also independently coupled through a pair of respective diode-connected transistors to the collector of the first transistor of the first emitter coupled pair.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The invention relates to improvements in sense-write circuits for random 
access memories. 
2. Brief Description of the Prior Art 
A variety of sense-write circuits for ECL (emitter-coupled logic) memory 
arrays are known in the art. One example of such a circuit is described in 
U.S. Pat. No. 3,919,566, and typical decoding circuitry for an ECL memory 
array is described in U.S. Pat. No. 3,914,620, both by Millhollan, et al 
and both assigned to the present assignee. Both of the above patents are 
incorporated herein by reference. The known ECL sense-write circuits 
utilize two differential stages, one for establishing a sense voltage on a 
bit sense line of the memory array, and the other operating to establish 
the Write-Data and Write-Data voltages on the bit-sense lines during write 
operations. Separate current sources are required for each of the 
differential stages. The topology in integrated circuit layout for 
multiple differential stages does not optimize use of chip area. 
Needlessly complex interface circuitry between the differential stages and 
the bit-sense lines in the memory array is required. 
SUMMARY OF THE INVENTION 
It is an object of the invention to provide a sense-write circuit utilizing 
differential stages in a tree configuration such that only one current 
source is required. 
Another object of the invention is to provide a sense-write buffer for a 
memory array and requiring a minimum number of components in construction 
and a minimum of interconnection of components. 
Briefly described, the invention is a sense-write circuit including first 
and second transistors having their emitters coupled to a first current 
source. Third and fourth transistors are provided having their emitters 
coupled to the collector of the first transistor. The base of the first 
transistor is coupled to a write signal, and the base of the third 
transistor is coupled to a data input signal. First and second rectifying 
devices are coupled between the respective collectors of the third and 
fourth transistors and the collector of the second transistor. The 
collectors of the third and fourth transistors are coupled by means of 
buffering and amplifying circuitry to a pair of bit sense lines of a 
storage cell.

DESCRIPTION OF THE INVENTION 
Referring to the FIGURE, it is seen that sense-write buffer 12 includes 
transistor 15 having its emitter coupled to a V.sub.EE voltage supply 
conductor 16 through a resistor 15A, its base connected to a conductor 
V.sub.CS (chip select), and its collector connected to node 17. Resistor 
15A determines the current through transistor 15 for a given voltage 
applied to V.sub.CS. Transistors 18 and 19 have their emitters connected 
to node 17. Transistor 18 has its base connected to node 22, which is 
connected to the emitter of transistor 23 and to one terminal of resistor 
24, which has its other terminal connected to V.sub.EE. Transistor 23 has 
its base and collector connected to the emitter of transistor 25, which 
has its collector connected to V.sub.CC and its base connected to write 
enable input 26. Transistor 18 has its collector connected to node 20. 
Transistors 27 and 28 have their emitters connected to node 20. Transistor 
27 has its base connected to Data-In input 29 and its collector connected 
to node 30, which is connected to one terminal of resistor 32. The other 
terminal of resistor 32 is connected to one end of resistor 34, the other 
end of which is connected to V.sub.CC conductor 35. Transistor 28 has its 
base connected to first reference voltage V.sub.BB. The collector of 
transistor 28 is connected to node 31, which is also connected to one end 
of resistor 33, the other terminal of which is connected to resistor 34. 
Transistor 19 has its base connected to second reference voltage 
V.sub.BB'. Typical values of the supply voltages and reference voltages 
are V.sub.CC = 0 volts, V.sub.EE = -5.2 volts, V.sub.BB = -1.3 volts, 
V.sub.BB' = -2.9 volts. Typically, V.sub.BB and V.sub.BB' and V.sub.CS are 
generated by temperature tracking voltage reference circuits provided on 
the same integrated circuit chip of the entire memory. Diode-connected 
transistor 41 has its base and collector connected to node 30 and its 
emitter connected to node 21, which is also connected to the collector of 
transistor 19. Diode-connected transistor 40 has its base and collector 
connected to node 31 and its emitter connected to node 21. Node 30 is 
connected to the input of an emitter follower including transistors 36 and 
resistor 37. Node 31 is connected to the base of the input transistor 38 
of an emitter follower including transistor 38 and resistor 39. The FIGURE 
also shows a typical ECL storage cell 14, which includes transistors 52, 
58, 59 and 55, and also the resistors 54 and 53 and diodes 57 and 59A. 
This storage cell is well known and will not be described in further 
detail. See the above mentioned U.S. Pat. Nos. 3,919,566 and 3,914,620, 
incorporated herein by reference. 
A typical integrated circuit random access memory would include a plurality 
of storage cells such as 14 arranged in rows and columns. Row selection 
and column selection circuitry suitable for selecting rows and columns of 
such a memory are well known and implementable by those skilled in the 
art. Output 42 of emitter follower 36, 37 is connected to the base of 
transistor 45 and to a plurality of other transistors in other columns of 
storage cells corresponding to transistor 45. Similarly, second emitter 
follower output 43 is connected to the base of transistor 48 and to 
comparable other transistors. 
Sense-write buffer 12 operates in two modes, a write mode and a sensing 
mode. The voltage V.sub.CS will normally be generated by a level 
translating circuit coupled between the base of transistor 15 and a chip 
enable input, not shown. 
A differential transistor pair 18, 19 is controlled by the write enable 
input 26. The differential pair 27, 28 is controlled by a Data-In input 
29. The outputs on nodes 42 and 43 are given as a function of the write 
enable and Data-In inputs. 
______________________________________ 
INPUT OUTPUT 
______________________________________ 
Write Data Node Node 
Enable In 42 43 
0 0 Sense-level Sense-level 
0 1 Sense-level Sense-level 
1 0 1 0 
1 1 0 1 
______________________________________ 
Typical levels for the above table are sense level = -1.3 volts, "0" = -1.7 
volts, and "1" = -0.8 volts. 
The memory array storage cell 14 is typical of an ECL storage cell, and the 
circuits (44, 45) and (47, 48) connected, respectively, to the bit sense 
lines 50 and 51 are conventional. If nodes 42 and 43 are both at a proper 
sense voltage, such as -1.3 volts, then it can be recognized that two 
separate differential amplifiers are formed by means of the transistors 45 
and 52 and current source 61 on one side and transistors 48 and 55 and 
current source 62 on the other side if the storage cell is selected by 
bringing row selection conductor 60A to -1.0 volts. The collector nodes of 
a storage cell provide the data inputs to the two differential amplifiers, 
and the sense levels at nodes 42 and 43 provide the reference voltage for 
the two differential amplifiers thus formed. The sense voltage of -1.3 
volts is designed to be midway between the two collector voltages of a 
selected storage cell. Therefore, only one of the transistors 45 or 48 
will be in the on condition, and the storage cell state is sensed as a 
voltage difference between resistors 44 and 47 at the data out terminals 
46 and 49 during a sensing operation. 
During a read operation, the levels of nodes 42 and 43 are established as 
follows. Write enable input 26 will be low, assuming that the chip is 
selected, so that transistor 15 is on. Transistor 18 will be off, and 
current I will flow through transistor 19. Diode-connected transistors 40 
and 41 are essentially identical, matched devices, so that the current 
through them is equally divided. Since no current flows through node 20, 
transistors 27 and 28 are off, and a current equal to I/2 flows through 
each of matched resistors 32 and 33. (Resistor 34 can be utilized to 
provide an offset, if desired.) Therefore, the voltages at nodes 30 and 31 
are equal, and consequently the voltages at nodes 42 and 43 are also 
equal, each being a V.sub.BE drop below nodes 30 and 31, respectively. 
A write operation occurs when write-enable input 26 is high, so that 
transistor 18 is on, and transistor 19 is off. Then transistors 40 and 41 
are also off, and current "I" flows through transistor 18. Current "I" 
flows through either transistor 27 or 28, depending on whether Data-In 
input 29 is high or low. Thus, the switch current "I" flows through either 
resistor 32 or 33, depending on the voltage of Data-In, at one of nodes 30 
or 31, so that one will be relatively low and the other will be relatively 
high. The voltages on nodes 30 and 31 will be translated through 
transistors 36 and 38 to nodes 42 and 43, and these voltages will in turn 
be translated through transistors 45 and 48 to bit-sense lines 50 and 51, 
respectively, and the logic state represented by these voltages will be 
written into memory cell 14 if it is selected.