Ion flow barrier structure for interconnect metallization

A method for forming an ion flow barrier between conductors includes forming a barrier material through a via in an interlevel dielectric layer and onto a first metal layer and recessing the barrier material to form a thickness of the barrier material on the first metal layer in the via, the thickness forming an ion flow barrier. A second metal layer is deposited in the via over the ion flow barrier such that, during operation, the ion flow barrier reduces ion flow between the first metal layer and the second metal layer while maintaining low resistance.

BACKGROUND

Technical Field

The present invention relates to semiconductor processing, and more particularly to an ion flow barrier and methods for fabrication to reduce electromigration of ions while maintaining low resistance interconnect interfaces.

Description of the Related Art

Reliability and electromigration performance are negatively impacted as barrier thickness is downscaled in back end of the line (BEOL) Cu interconnects. In addition to risks associated with barrier continuity on sidewalls, discontinuities in the barrier (such as TaN) at a via bottom lead to breakdown of “short-length” criterion. This criterion requires blocking of Cu ion flow at a via bottom to prevent massive Cu ion migration from level to level.

SUMMARY

A method for forming an ion flow barrier between conductors includes forming a barrier material through a via in an interlevel dielectric layer and onto a first metal layer and recessing the barrier material to form a thickness of the barrier material on the first metal layer in the via, the thickness forming an ion flow barrier. A second metal layer is deposited in the via over the ion flow barrier such that, during operation, the ion flow barrier reduces ion flow between the first metal layer and the second metal layer while maintaining low resistance. In other embodiments, the ion flow barrier is formed by reacting the barrier material with the first metal layer.

Another method for forming an ion flow barrier between conductors includes forming a barrier material through a via in an interlevel dielectric layer and onto a first metal layer; annealing the barrier material to react with the barrier material with the first metal layer to form an ion flow barrier; recessing the barrier material to expose the ion flow barrier in the via; and depositing a second metal layer in the via over the ion flow barrier such that, during operation, the ion flow barrier reduces ion flow between the first metal layer and the second metal layer while maintaining low resistance.

A device having an ion flow barrier between conductors includes a first metal layer, an interlevel dielectric layer formed on the first metal layer and having a via formed through the interlevel dielectric layer and an ion flow barrier. The ion flow barrier is formed in the via and has a thickness of barrier material. The ion flow barrier includes a material different from the first metal layer and the second metal layer. A second metal layer is formed on the ion flow barrier in the via such that, during operation, the ion flow barrier reduces ion flow between the first metal layer and the second metal layer while maintaining low resistance.

DETAILED DESCRIPTION

In accordance with the present principles, devices and methods for fabrication of such devices are provided that include an ion flow barrier structure to prevent metal ion flow through an interconnect via bottom. The ion flow barrier structure enables highly reliable metallization at low via resistance. As interconnect feature sizes shrink, barrier thickness needs to be scaled to maximize metal volume and to enable low line and via resistance. Scaling sidewall barrier thickness permits the maximization of metal volume in interconnects, and scaling barrier thickness at via bottom allows reduction of via resistance. To meet reliability targets, the presence of an ion flow barrier is employed to prevent interconnect metal ion flow through a via bottom. Such an ion flow barrier needs low resistivity materials, compatible with metallization process flows.

In particularly useful embodiments, the metallizations may include Cu although other highly conductive materials and in particular metals may be employed. Some embodiments may include an inert ion barrier disposed between metallizations on different metal layers. The inert ion barrier may include, e.g., W. Some embodiments may include an active or dynamic ion barrier disposed between metallizations on different metal layers. The active ion barrier may include, e.g., CuPt. Other materials may also be employed for the inert and/or the active ion barriers.

The present principles may be employed in any semiconductor device or integrated circuit. The ion barriers as described herein may be formed between any two conductors to prevent electromigration due to ion flow. The present principles may also be employed in vertical as well and horizontal interconnects, and may be employed in contacts at tops of vias as well as or in addition to the bottoms of vias.

It is to be understood that the present invention will be described in terms of a given illustrative architecture or architectures; however, other architectures, structures, substrate materials and process features and steps may be varied within the scope of the present invention.

It should also be understood that material compounds will be described in terms of listed elements, e.g., CuPt. These compounds include different proportions of the elements within the compound, e.g., CuPt includes CuxPt1-xwhere x is less than or equal to 1, etc. In addition, other elements may be included in the compound and still function in accordance with the present principles. The compounds with additional elements will be referred to herein as alloys.

Referring now to the drawings in which like numerals represent the same or similar elements and initially toFIG. 1, a partially fabricated semiconductor device10is depicted showing a first metal layer12(Mx) and an interlevel dielectric layer (ILD) or layers14, which are processed to form a via16at a via level (Vx). The first metal layer12is described as being first in the relative sense for ease of reference. The first metal layer12may be any metal layer in a plurality of metal layers or metal structures as the case may be. In addition, the ILD14may include any number of configurations including, e.g., a level top surface on both sides of the via16, multiple dielectric layers, dual damascene structures where a via and metal line are formed together, etc.

A liner22may be formed over surfaces of the ILD14. The liner22may include materials such as, e.g., Ta, TaN, TiN or other suitable materials. The liner22may be removed from a surface of the first metal layer12within the via16or may remain on the metal layer12. After the liner deposition, which may include a sputtering process, an etch process may be performed (e.g., a reactive ion etch (RIE)), to remove the liner22from the bottom of the via16.

Electromigration of material is more pronounced in regions of reduced area. Such areas may include regions where a contact through a via connects to a metal line or metal node. In accordance with the present principles, an ion flow barrier structure is formed to prevent metal ion flow through an interconnect via bottom, enabling highly reliable metallization at a low via resistance.

A barrier material18is formed in the via16and in a trench20(if present, e.g., if a metal line is to be formed with a via contact). The barrier material18includes an inert material in one embodiment. The inert material includes an inert metal having good conductive properties. In one embodiment, the inert material includes W. In other embodiments, the inert material may include Mo, MoTa, MoRu, RuTa, RuW, TaW, TiW, alloys of these and other materials and similar alloys including alternative W-based alloys. The barrier material18may be sputtered, deposited by evaporation methods, deposited by chemical vapor deposition methods or any other suitable deposited method.

Barrier material18may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), and/or atomic layer deposition (ALD) including any thermal or plasma (e.g., Ar, H2, He) pre-treatment processes prior to barrier deposition. Process temperatures for barrier deposition can range from about 20° C. to about 350° C., while typical pre-treatment process temperatures can range from about 80° C. to about 400° C.

Referring toFIG. 2, a planarization process is performed to planarize the barrier material18. The planarization process may include a chemical mechanical polishing (CMP) process. The barrier material18is then recessed to remove the barrier material18from the trench20and down into a bottom of the via16to form an ion flow barrier24. The recess process may include a RIE selective to the liner22and/or the ILD14. The ion flow barrier24may include a thickness of between 1 nm and 10 nm, although other thicknesses may be employed.

An additional liner26may optionally be formed on the exposed surfaces including the barrier24. The liner26may include the liner24or may be employed instead of liner24. Liner26may include the same materials as liner24.

Referring toFIG. 3, a metal deposition process is performed to form metallizations including, e.g., metal lines30(Mx+1) and contacts28(Vx). The contacts28include the ion barrier24. The metal lines30and contacts28may include Cu and/or its alloys. Other metals may also be employed. A planarization process may be employed to planarize the deposited material (e.g., CMP) to form metal lines30and/or contacts28.

Processing may continue with the formation of additional metal layers and contacts (along with ILD layers). The additional contacts may include ion flow barriers24formed in a same way or may include variations on the size and composition of the ion flow barrier24in accordance with the design of the device10.

Referring toFIG. 4, another partially fabricated semiconductor device50is depicted showing a first metal layer52(Mx) and an interlevel dielectric layer (ILD) or layers54, which are processed to form a via56at a via level (Vx). The first metal layer52is described as being first in the relative sense. The first metal layer52may be any metal layer or metal structures as the case may be. In addition, the ILD54may include any number of configurations including, e.g., a level top surface on both sides of the via56, multiple dielectric layers, dual damascene structures where a via and metal line are formed together, etc.

A liner62may be formed over surfaces of the ILD54. The liner62may include materials such as, e.g., Ta, TaN, TiN or other suitable materials. The liner62may be removed from a surface of the first metal layer52within the via56or may remain on the metal layer52. After the liner deposition, which may include a sputtering process, an etch process may be performed (e.g., a reactive ion etch (RIE)), to remove the liner52from the bottom of the via56.

In accordance with the present principles, an ion flow barrier structure is formed to prevent metal ion flow through an interconnect via bottom, enabling highly reliable metallization at a low via resistance. A barrier material58is formed in the via56and in a trench60(if present, e.g., if a metal line is to be formed with a via contact). The barrier material58includes a dynamic material in one embodiment. The barrier material58may be deposited by a sputter-etch or other deposition process to deposit ion flow starting material or barrier material58. The barrier material58may include, e.g., Pt, Pt—W or other suitable materials. The dynamic material may include a metal having good conductive properties. In one embodiment, the dynamic material includes Pt. In other embodiments, the dynamic material may include Pt, Pd, Ni, or alloys of these and other materials and similar alloys including alternative Pt-based alloys. The barrier material58may be sputtered, deposited by evaporation methods, deposited by chemical vapor deposition methods or any other suitable deposition method.

Referring toFIG. 5, with the barrier material58in contact with the first metal layer52, an anneal process is performed to form ion flow barrier64by reacting the barrier material58with the first metal layer52. In one example, the barrier material58may include Pt and the first metal layer52may include Cu such that the ion flow barrier64includes CuPt.

Barrier material58may be formed by PVD, CVD and/or ALD including any thermal or plasma (e.g., Ar, H2, He) pre-treatment processes prior to barrier deposition. Process temperatures for barrier deposition can range from about 20° C. to about 350° C., while typical pre-treatment process temperatures can range from about 80° C. to about 400° C.

Referring toFIG. 6, the barrier material58is removed. This may include a planarization process to planarize the barrier material58. The planarization process may include a chemical mechanical polishing (CMP) process. The barrier material58is then recessed to remove the barrier material58from a trench60and down into a bottom of a via56to form an ion flow barrier64. The recess process may include a RIE selective to the liner62and/or the ILD54. The ion flow barrier64may include a thickness of between 0.5 nm and 8 nm, although other thicknesses may be employed.

An additional liner68may optionally be formed on the exposed surfaces including the barrier64. The liner68may include the liner62or may be employed instead of liner62. Liner68may include the same materials as liner62.

Referring toFIG. 7, a metal deposition process is performed to form metallizations including, e.g., metal lines70(Mx+1) and contacts72(Vx). The contacts72include the ion barrier64. The metal lines70and contacts72may include Cu and/or its alloys. Other metals may also be employed. A planarization process may be employed to planarize the deposited material (e.g., CMP) to form metal lines70and/or contacts72.

Processing may continue with the formation of additional metal layers and contacts. The additional contacts may include ion flow barriers64formed in a same way or may include variations on the size and composition of the ion flow barrier64in accordance with the design of the device50.

In accordance with the present principles, structures24and64provide an ion flow barrier, which can prevent the flow of interconnect metal ions to ensure integrity in electromigration performance. In one embodiment, the structures provide both ion flow barrier functionality as well as Cu surface diffusion mitigation. Structures24and64are placed at the bottom of a via; however, the structures24and64may also be placed at the tops of interconnects (or both). In some embodiments, the structures24and64are formed on the top and bottom of a via to act in unison as an ion flow barrier.

The structures (e.g., 24 and 64) may include an ion flow barrier structure formed with inert materials (e.g., W) or by reaction of a starting material (e.g., Pt, Pt—W) combined with a prior level material such as Cu to form, e.g. CuPt or CuPt—W. The structures (e.g., 24 and 64) may include low resistivity ion flow barrier materials such as Mo, MoTa, MoRu, RuTa, RuW, TaW, TiW and similar alloys including alternative W-based alloys for inert embodiments, and Pt, Pd, Ni, or alloys of these and other materials and similar alloys including alternative Pt-based alloys for dynamic material embodiments. The structures (e.g., 24 and 64) resist ion migration while permitting electron flow. This reduces electromigration while maintaining low resistivity at interconnects.

Referring toFIG. 8, a method for forming an ion flow barrier between conductors is illustratively shown in accordance with one embodiment. In block102, a liner may be formed on sidewalls (and/or the bottom) of a via through an interlevel dielectric layer. In block104, a barrier material is formed through a via in an interlevel dielectric layer and onto a first metal layer. The barrier material includes an inert metal. The inert metal may include one or more of W, Mo, Ta, Ru or TiW.

In block106, the barrier material is recessed to form a thickness of the barrier material on the first metal layer in the via, the thickness forming an ion flow barrier. The recessing may include a CMP process followed by a selective etch. The ion flow barrier may include a thickness of between about 1 nm and about 10 nm.

In block108, a second metal layer is deposited in the via over the ion flow barrier such that, during operation, the ion flow barrier reduces ion flow between the first metal layer and the second metal layer while maintaining low resistance. The low resistance includes a resistivity capable of meeting contact resistance specifications for a given device node or technology. In one embodiment, the second metal layer forms a contact in the via and a metal line in a trench formed in the interlevel dielectric layer. A first or additional liner may be formed and processed before forming the second metal layer.

In block110, an additional ion flow barrier is formed above or in the via. In this way, multiple ion flow barriers may be employed at a same interconnect or via. In block112, processing continues to complete the device.

Referring toFIG. 9, a method for forming an ion flow barrier between conductors is illustratively shown in accordance with another embodiment. In block132, a liner may be formed on sidewalls (and/or the bottom) of a via through an interlevel dielectric layer. In block134, a barrier material is formed through a via in an interlevel dielectric layer and onto a first metal layer. In block136, the barrier material is annealed to react with the barrier material with the first metal layer to form an ion flow barrier. The anneal process may include a rapid thermal anneal (RTA) or may include other anneal processes depending on the materials. The anneal temperatures and times will depend upon the materials and the size of the ion barrier needed for a particular application. The barrier material may include one or more of Pt or Pt—W, Pd, Ni, or alloys of these and other materials and similar alloys including alternative Pt-based alloys. The ion flow barrier may include one or more of CuPt or CuPt—W after the anneal. The ion flow barrier may include a thickness of between about 0.5 nm and about 8 nm.

In block138, the barrier material is recessed to expose the ion flow barrier in the via. The recess process may include CMP followed by a selective etch. In block140, a second metal layer is deposited in the via over the ion flow barrier such that, during operation, the ion flow barrier reduces ion flow between the first metal layer and the second metal layer while maintaining low resistance. In one embodiment, the second metal layer forms a contact in the via and a metal line in a trench formed in the interlevel dielectric layer. A first or additional liner may be formed and processed before forming the second metal layer.

In block142, an additional ion flow barrier is formed above or in the via. In this way, multiple ion flow barriers may be employed at a same interconnect or via. In block144, processing continues to complete the device.