Power semiconductor device trench having field plate and gate electrode

A method of processing a power semiconductor device includes: providing a semiconductor body with a trench extending into the semiconductor body along an extension direction and including an insulator; providing a monolithic electrode zone within the trench; and removing a section of the monolithic electrode zone within the trench to divide the monolithic electrode zone into at least a first electrode structure and a second electrode structure arranged separately and electrically insulated from each other.

TECHNICAL FIELD

This specification refers to embodiments of a method of processing a power semiconductor device and to embodiments of a power semiconductor device. In particular, the specification is directed to embodiments of a power semiconductor device having a trench that includes each of gate electrode structure and a field electrode structure, and to embodiments of a method of processing such power semiconductor device.

BACKGROUND

Many functions of modern devices in automotive, consumer and industrial applications, such as converting electrical energy and driving an electric motor or an electric machine, rely on power semiconductor devices. For example, Insulated Gate Bipolar Transistors (IGBTs). Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and diodes, to name a few, have been used for various applications including, but not limited to switches in power supplies and power converters.

A power semiconductor device usually comprises a semiconductor body configured to conduct a load current along a load current path between two load terminals of the device. Further, the load current path may be controlled by means of an insulated electrode, sometimes referred to as gate electrode. For example, upon receiving a corresponding control signal from, e.g., a driver unit, the control electrode may set the power semiconductor device in one of a conducting state and a blocking state.

In some cases, the gate electrode may be included within a trench of the power semiconductor device, wherein the trench may exhibit, e.g., a stripe configuration or a needle configuration.

Further, such trench occasionally includes more than only one electrode, e.g., two or more electrodes that are arranged separately from each other and sometimes also electrically insulated from each other. For example, a trench may comprise both a gate electrode and a field electrode, wherein the gate electrode can be electrically insulated from each of the load terminals, and wherein the field electrode can be electrically connected to one of the load terminals.

SUMMARY

According to an embodiment, a method of processing a power semiconductor device comprises providing a semiconductor body that includes a trench, the trench extending into the semiconductor body along an extension direction and comprising an insulator; providing a monolithic electrode zone within the trench; removing a section of the monolithic electrode zone within the trench to divide the monolithic electrode zone into at least a first electrode structure and a second electrode structure arranged separately and electrically insulated from each other.

According to a further embodiment, a power semiconductor device comprises a semiconductor body coupled to a first load terminal and a second load terminal and configured to conduct a load current between said terminals, the power semiconductor device including: a trench extending into the semiconductor body along an extension direction and comprising an insulator; a first electrode structure included in the trench and configured to control the load current; a second electrode structure included in the trench and being arranged separately and electrically insulated from the first electrode structure; wherein the first electrode structure and the second electrode structure are spatially displaced from each other along the extension direction such that they do not exhibit a common extension range along the extension direction; and wherein the first electrode structure and the second electrode structure are further spatially displaced from each other along a first lateral direction such that they do not overlap along the first lateral direction.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings which form a part hereof and in which are shown by way of illustration specific embodiments in which the invention may be practiced.

In this regard, directional terminology, such as “top”, “bottom”, “below”, “front”, “behind”, “back”, “leading”, “trailing”, “below”, “above” etc., may be used with reference to the orientation of the figures being described. Because parts of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation, and is not meant as a limitation of the invention. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention includes such modifications and variations. The examples are described using specific language which should not be construed as limiting the scope of the appended claims. The drawings are not scaled and are for illustrative purposes only. For clarity, the same elements or manufacturing steps have been designated by the same references in the different drawings if not stated otherwise.

The term “horizontal” as used in this specification intends to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or of a semiconductor structure. This can be for instance the surface of a semiconductor wafer or a die. For example, both the first lateral direction X and the second lateral direction Y mentioned below can be horizontal directions, wherein the first lateral direction X and the second lateral direction Y may be perpendicular to each other.

The term “vertical” as used in this specification intends to describe an orientation which is substantially arranged perpendicular to the horizontal surface, i.e., parallel to the normal direction of the surface of the semiconductor wafer. For example, the extension direction Z mentioned below may be an extension direction that is perpendicular to both the first lateral direction X and the second lateral direction Y.

In this specification, n-doped is referred to as “first conductivity type” while p-doped is referred to as “second conductivity type”. Alternatively, opposite doping relations can be employed so that the first conductivity type can be p-doped and the second conductivity type can be n-doped.

In the context of the present specification, the terms “in ohmic contact”, “in electric contact”, “in ohmic connection”, and “electrically connected” intend to describe that there is a low ohmic electric connection or low ohmic current path between two regions, sections, zones, portions or parts of a semiconductor device or between different terminals of one or more devices or between a terminal or a metallization or an electrode and a portion or part of a semiconductor device. Further, in the context of the present specification, the term “in contact” intends to describe that there is a direct physical connection between two elements of the respective semiconductor device; e.g., a transition between two elements being in contact with each other may not include a further intermediate element or the like.

In addition, in the context of the present specification, the term “electric insulation” is used, if not stated otherwise, in the context of its general valid understanding and thus intends to describe that two or more components are positioned separately from each other and that there is no ohmic connection connecting those components. However, components being electrically insulated from each other may nevertheless be coupled to each other, for example mechanically coupled and/or capacitively coupled and/or inductively coupled. To give an example, two electrodes of a capacitor may be electrically insulated from each other and, at the same time, mechanically and capacitively coupled to each other, e.g., by means of an insulation, e.g., a dielectric.

Specific embodiments described in this specification pertain to, without being limited thereto, a power semiconductor device exhibiting a stripe cell or needle cell configuration, such as a power semiconductor transistor, that may be used within a power converter or a power supply. Thus, in an embodiment, the semiconductor device is configured to carry a load current that is to be fed to a load and/or, respectively, that is provided by a power source. For example, the semiconductor device may comprise one or more active power semiconductor cells, such as a monolithically integrated diode cell, and/or a monolithically integrated transistor cell, and/or a monolithically integrated IGBT cell, and/or a monolithically integrated RC-IGBT cell, and/or a monolithically integrated MOS Gated Diode (MGD) cell, and/or a monolithically integrated MOSFET cell and/or derivatives thereof. Such diode cell and/or such transistor cells may be integrated in a power semiconductor module. A plurality of such cells may constitute a cell field that is arranged with an active region of the power semiconductor device.

The term “power semiconductor device” as used in this specification intends to describe a semiconductor device on a single chip with high voltage blocking and/or high current-carrying capabilities. In other words, such power semiconductor device is intended for high current, typically in the Ampere range, e.g., up to several ten or hundred Ampere, and/or high voltages, typically above 15 V, more typically 100 V and above, e.g., up to at least 400 V. For example, the processed semiconductor device described below may be a semiconductor device exhibiting a stripe cell configuration or a needle cell configuration and can be configured to be employed as a power component in a low-, medium- and/or high voltage application.

For example, the term “power semiconductor device” as used in this specification is not directed to logic semiconductor devices that are used for, e.g., storing data, computing data and/or other types of semiconductor based data processing

FIG. 1schematically and exemplarily illustrates a method2of processing a power semiconductor device1—in the following also simply referred to as “semiconductor device”—in accordance with one or more embodiments. Some steps of the method2are illustrated by a respective section of a vertical cross-section of the processed component of the semiconductor device1. The illustrated cross-sections are in parallel to a plane defined by a first lateral direction X and an extension direction Z. The semiconductor device1being processed further extends in a second lateral direction Y that is perpendicular to each of the first lateral direction X and the extension direction Z.

In a step20of the method2, a semiconductor body10is provided that includes a trench15. The trench15extends into the semiconductor body10along the extension direction Z and can comprise an insulator16, e.g., for insulating an interior region of the trench15from the semiconductor body10.

For example, the semiconductor body10includes a drift region100, e.g., an epitaxial drift region100that is arranged on top of a substrate110. The drift region100may comprise dopants of a first conductivity type; e.g., the drift region100is n-doped. The trench15may extend along the extension direction Z into the drift region100.

The trench15of the semiconductor device1may exhibit a needle configuration, according to which the total extension of the trench15along the first lateral direction X is approximately in the same range as the total extension of the trench15along the second lateral direction Y. For example, when exhibiting the needle configuration, the trench15may have, in a plane defined by the first lateral direction X and the second lateral direction Y, one of a rectangular cross-section, a quadratic cross-section, an elliptical cross-section, a circular cross-section and a rectangular cross-section with rounded corners, to name a few possibilities.

In another embodiment, the trench15exhibits a stripe configuration, according to which the total extension along the second lateral direction Y amounts to at least a multiple of the total extension along the first lateral direction X. For example, in an embodiment, the semiconductor device1exhibits a plurality of trenches15in a stripe configuration that are arranged substantially in parallel to each other, e.g., along the first lateral direction X and cross substantially the entire active region of the semiconductor device1along the second lateral direction Y, reaching transition regions arranged between the active region and an edge region of the semiconductor device1. Generally speaking, the skilled person is acquainted with each of the needle configuration and a stripe configuration and, therefore, this aspect is not elucidated in more detail within the present specification.

In an embodiment, the insulator16forms trench sidewalls161and the trench bottom162of the trench15, as exemplarily illustrated inFIG. 1. Further, as will be explained in more detail below, prior to carrying out the next step24described below, the insulator16may be structured within the trench15, e.g., such that it exhibits, within the trench15, a varying thickness, e.g., a varying lateral thickness, along the extension direction Z.

In step24, a monolithic electrode zone13is provided within the trench15. This may include carrying out a deposition processing step. The monolithic electrode zone13may form a contiguous electrode region within the trench15. In an embodiment, the monolithic electrode zone13covers the trench bottom162and the trench sidewalls161, as illustrated.

For example, the monolithic electrode zone13comprises a metal or, respectively, is made of a metal. In an embodiment, the monolithic electrode zone13comprises or, respectively, is made out of at least one of tantalum, a silicide, titanium, titaniumnitride, polysilicon, tungsten, aluminum, copper, platinum and cobalt. Further, the monolithic electrode zone13can consist of a single layer or a layer stack, wherein the single layer or, respectively, the layers of the stack can be made out of one or more of the aforementioned materials.

In a further step28, a section of the monolithic electrode zone13is removed so as to divide the monolithic electrode zone13into at least a first electrode structure131and a second electrode structure132that are arranged separately and electrically insulated from each other.

Thus, in accordance with one or more embodiments, the two electrode structures131and132that are arranged separately and electrically insulated from each other can be created by one or more joint processing steps. For example, the two electrode structures131and132are not created separately, e.g., not sequentially one after the other, but simultaneously. In an embodiment, only a single deposition step is required for creating each of the first electrode structure131and the second electrode structure132.

Further, in accordance with one or more embodiments, the section of the monolithic electrode zone13arranged in the trench15that is removed within step28is not part of an extremity of the monolithic electrode zone13, but a section arranged in a mid-region (with respect to the extension direction Z) of the monolithic electrode zone13within the trench15. For example, in accordance with the embodiment schematically and exemplarily illustrated inFIG. 1, the section that has been removed from the monolithic electrode zone13can be arranged within the lower three quarters of the trench15. For example, the second electrode structure132extends further along the extension direction Z than the first electrode structure131.

Thus, in accordance with one or more embodiments, dividing the monolithic electrode zone13into at least the first electrode structure131and the second electrode structure132occurs within said mid-region of the trench15. For example, the trench15may exhibit a total extension along the extension direction Z, said total extension amounting to the sum of ten equal tenth parts, of which a proximal tenth part extends along the extension direction Z from the trench opening to the beginning of eight central tenth parts, and the eight central tenth parts extending along the extension direction Z to the beginning of a distal tenth part that extends along the extension direction Z to the trench bottom162. In an embodiment, dividing the monolithic electrode zone13by carrying out the removing step28occurs within said central eight tenth parts of the trench15or within more central six of said eight central tenth parts. For example, dividing the monolithic electrode zone13by carrying out the removing step28occurs within the second to fifth tenth parts (said proximal tenth part constituting the first tenth part and said distal tenth part constituting the last, i.e., the tenth part).

It shall be understood that when carrying out step28, i.e., when removing said section of the monolithic electrode zone13within the trench15, also some other parts of the monolithic electrode zone13, e.g., those that may be arranged external of the trench15, e.g., on top of a surface10-1of the semiconductor body10or, respectively, on top of the insulator16, may also be removed within step28, as illustrated inFIG. 1. For example, in an embodiment, a section of the monolithic electrode zone13that extends out of the trench15and that is supported by the surface10-1of the semiconductor body10-1or, respectively, by a section of the insulator16arranged on top of the surface10-1of the semiconductor body10, can be maintained during said removing step28, e.g., by using a lithography step. For example, the latter variant is schematically and exemplarily illustrated inFIG. 4a. In another embodiment that is schematically and exemplarily illustrated inFIG. 1, the removing step28is carried out such that the first electrode structure131does not extend out of the trench15, but is entirely included within the trench15. Both variants of carrying out the removing step28are possible, which one of the variants is eventually carried out may depend on the way of contacting the first electrode structure131and/or the second electrode structure132, as will be explained in more detail below with respect toFIG. 3,FIG. 4aandFIG. 4c.

In any case, the partial removing of the monolithic electrode zone13may be carried out by using a suitable mask. Further, said removing may include carrying out an anisotropic etch processing step.

In the following, some further optional aspects of the method2shall be explained in more detail with respect toFIGS. 1-5.

Providing the semiconductor body10within step20may include carrying out an epitaxial deposition for forming the drift region100, and an etch processing step for forming the trench15, and/or one or more oxidation and/or deposition processes for forming the insulator16.

An exemplary way of structuring (step22) the insulator16prior to providing the monolithic electrode zone13is schematically illustrated inFIG. 2. Accordingly, in a step221, the trench15may be partially filled with sacrificial material154. For example, the sacrificial material154is selectively etchable with respect to each of the semiconductor body10and the insulator16, e.g., selectively etchable with respect to each of silicon and silicon oxide, and comprises at least one of carbon and nitride.

Said partial filling may be carried out by initially filling the entire trench15with the sacrificial material154(cf. step221-1) and by subsequently carrying out an etch process (cf. step221-2) for removing an upper part of the sacrificial material154, e.g., down to a level Z1, so as to create a recess1541that this laterally confined by the insulator16along the first lateral direction X and vertically confined by the remaining sacrificial material154along the extension direction Z. For example, during this etch process, the insulator16remains substantially unmodified.

In an embodiment, after filling the entire trench15with the sacrificial material154(step221-1) and prior to carrying out the etch process (step221-2), the sacrificial material154, e.g., its part that forms a surface substantially in parallel to the semiconductor body surface10-1, e.g., a planar part of the semiconductor material154, may be subjected to a selective planarization processing step (not illustrated). This may allow for adjusting the total extension of the sacrificial material154along the extension direction Z more accurately, and said level Z1reached by means of the subsequent etch process (step221-2) can, thus, also be adjusted more accurately. Thereby, a Qgd-parameter of the semiconductor device1may be controlled in an exact manner.

Then, in step222, an insulator etch step can be carried out for removing a section of the insulator16. For example, during the insulator etch step, trench sidewalls161formed by the insulator16and arranged in an upper part151of the trench15are removed, wherein trench sidewalls161formed by the insulator16and arranged in a lower part152of the trench15remain within the trench15, as illustrated inFIG. 2.

In an embodiment, said section of the insulator16being removed in step222may include those regions that are arranged within the trench15and above the sacrificial material154and also a region that slightly extends below the sacrificial material154. For example, the insulator16is etched down to a level Z2, wherein Z2can be, e.g., equal to or greater than Z1. For example, level Z2may constitute an upper contact level where the second electrode structure132may eventually be contacted, which will be explained in more detail below.

Further, step222may also include removing the insulator16that may be arranged external of the trench15, e.g., on a surface10-1of the semiconductor body10. For example, during step222, each of the semiconductor body10and the sacrificial material154remains substantially unmodified.

Step222of removing the section of the insulator16may include carrying out at least one of an anisotropic etch processing step and an isotropic wet etch processing step.

Thus, at this processing stage, a lower part152of the trench15may be completely filled by the insulator16and the sacrificial material154, wherein the sacrificial material154may be isolated from the semiconductor body10by the insulator16. In an upper part151of the trench15, however, there can be substantially a recess into which only the sacrificial material154extends, wherein a transition between the upper part151and the lower part152can be at said level Z2.

In a next step223, a further etch step can be carried out for eliminating the sacrificial material154within the trench15. In an embodiment, the entire sacrificial material154is removed during step223. For example, this further etch step includes at least one of a selective (e.g., selective to the material of the insulator16and the material of the semiconductor body10) etch processing step and a wet etch processing step.

Then, in step224, an oxide164can be created in a region where said insulator section has previously, e.g., in step222, been removed. This can be done by depositing the oxide164and/or by carrying out a thermal oxidation step. Instead of the oxide164, also another insulator material may be created in said region. Thus, the created oxide164may contact the remaining insulator16. In the following, the formulation “insulator16” may, thus, also comprise said created oxide164. In other words, the oxide164may form a part of the insulator16. For example, the insulator16then forms the entire trench sidewalls161as well as the trench bottom162of the trench15. In accordance with one or more embodiments, the section of the insulator16that eventually electrically insulates the first electrode structure131from the semiconductor body10is created prior to creating the first electrode structure131within the trench15. This may allow for shifting the thermal budget of the oxide creation step224before the step of providing the monolithic electrode zone13, e.g., before depositing metal, in accordance with one or more embodiments.

In an embodiment, providing the monolithic electrode zone13may occur directly after forming the oxide164.

Structuring the insulator16, for example in accordance with the embodiment schematically illustrated inFIG. 2, may yield at least one step163within the trench sidewalls161. This step163within the trench sidewalls161can be arranged approximately at the level Z2. Thus, the trench sidewalls161may exhibit a step profile along the extension direction Z. Accordingly, the thickness of the insulator16in the first lateral direction X may exhibit a sharp increase at the level Z2.

Regarding now again method step24schematically and exemplarily illustrated inFIG. 1, after providing the monolithic electrode zone13within the trench15, the provided monolithic electrode zone13may form a well structure155, e.g., in the upper part151of the trench15. In the vertical cross-section schematically illustrated, the monolithic electrode zone13may thus exhibit a fork-like form, completely filling, together with the insulator16, the lower part152of the trench15and leaving a recess in the upper part151of the trench15by means of its one or more “tines”. But, it shall be understood that the monolithic electrode zone13must not necessarily fill the entire lower part152of the trench15. In an embodiment (not illustrated), the monolithic electrode zone13may form an internal recess structure that leaves a cavity within the lower part152of the trench15, wherein said cavity may be filled with an insulator material, for example.

Further, the well structure155of the monolithic electrode zone13in the upper part151of the trench15may comprise a bottom1552that may be supported by, e.g., the steps163of the insulator16. For example, in step28, when a section of the monolithic electrode zone13may be removed within the trench15so as to divide the monolithic electrode zone13into at least the first electrode structure131and the second electrode structure132, at least a part of the bottom1552of the well structure155can be removed, as schematically and exemplarily illustrated inFIG. 1.

By removing the bottom1552of the well structure155at least partially, e.g., by carrying out an anisotropic etch processing step, the monolithic electrode zone13may become divided into the first electrode structure131and the second electrode structure132, wherein said two electrode structures131and132can then be spatially displaced from each other along the extension direction Z. In an embodiment, the first electrode structure131and the second electrode structure132are spatially displaced from each other along the extension direction Z such that they do not exhibit a common extension range along the extension direction Z. For example, the second electrode structure132may be arranged entirely below the first electrode structure131, e.g., below the well structure155that has previously been formed by the monolithic electrode zone13within the upper part151of the trench15.

As has been explained above, due to the structured insulator16, the monolithic electrode zone13may be provided within the trench15such that it at least partially or completely fills the lower part152and only covers the trench sidewalls161, which may be formed, e.g., by the oxide164, in the upper part151of the trench15, leaving a recess1555within the upper part151of the trench15. Thus, when removing the section of the monolithic electrode zone13, e.g., at least a part of the bottom1552of the well structure155, the two electrode structures131,132that are arranged separately from each other may come into being, wherein the first electrode structure131may comprise a first electrode1311and a second electrode1312that are each arranged spatially displaced from the second electrode structure132. Further, the first electrode1311can be arranged at one of the trench sidewalls161and the second electrode1312can be arranged at the other one of the trench sidewalls161, thereby, e.g., laterally confining the recess1555.

In an embodiment, neither the first electrode1311nor the second electrode1312has a common extension range with second electrode structure132along the first lateral direction X. For example, a distance along the first lateral direction X between the first electrode1311and the second electrode1312is greater than a total extension of the second electrode structure132in said first lateral direction X.

FIG. 3schematically and exemplarily illustrates a section of a horizontal projection of a power semiconductor device1in accordance with one or more embodiments, e.g., a power semiconductor device1that has been processed in accordance with an embodiment of the method2exemplarily described with respect toFIGS. 1 and 2above. The horizontal projection may be in parallel to a plane defined by the two lateral directions X and Y.

In accordance with the embodiment illustrated inFIG. 3, the trench15exhibits a stripe configuration. As has been explained above, the trench15may cross substantially the entire active region1-1of the semiconductor device1along the second lateral direction Y, reaching transition regions arranged between the active region1-1and an edge region1-2of the semiconductor device1.

As illustrated, at least in a part of the active region1-1, the first electrode structure131and the second electrode structure132may be spatially displaced from each other along the first lateral direction X, e.g., such that they do not overlap along the first lateral direction X.

Further, the trench15may exhibit a total extension range along the second lateral direction Y amounting to the sum of the three lateral subregions ΔY1, ΔY2and ΔY3indicated inFIG. 3. In an embodiment, during step28, the following sections of the monolithic electrode region13are removed: In the first subregion ΔY1, only said bottom1552of the well structure155(as exemplarily illustrated inFIG. 1) is at least partially removed, e.g., by carrying out an anisotropic etch processing step; in the second subregion ΔY2, the entire well structure155is removed, wherein the section of the monolithic electrode region13arranged in the lower part152remains within the trench15; and in the third subregion ΔY3, no parts of the monolithic electrode region are removed. In another embodiment, also in the third subregion ΔY3, the entire well structure155is removed, as in the second subregion ΔY2. Removing the entire well structure155in the second subregion ΔY2and/or in the third subregion ΔY3may comprise, e.g., carrying out an additional isotropic etch step masked with a lithography step.

For example, the first subregion ΔY1amounts to at least 70%, to at least 90% or to at least 98% of the total extension range of the trench15along the second lateral direction Y; the second subregion ΔY2amounts to less than 5%, to less than 2% or to less than 1% of the total extension range of the trench along the second lateral direction Y; and the third subregion ΔY3amounts to less than 5%, to less than 2% or to less than 1% of the total extension range of the trench along the second lateral direction Y. Thus, in an embodiment, in a predominant portion of the trench15, the trench15includes each of the first electrode structure131and the second electrode structure that are arranged separately and electrically insulated from each other, e.g., spatially displaced from each other such that they do not overlap along the extension direction Z.

Further, the method2may include providing contacting means for contacting each of the first electrode structure131and the second electrode structure132from external of the trench15. In other words, the power semiconductor device1may include contacting means for contacting each of the first electrode structure131and the second electrode structure132from external of the trench15. Said contacting means or, respectively, exemplarily ways of providing said contacting means shall now be described in more detail, also with respect toFIGS. 4a-c, whereinFIG. 4aschematically and exemplarily illustrates a section of a vertical cross-section of a power semiconductor device1along a plane AA′ (indicated inFIG. 3) in accordance with one or more embodiments.FIG. 4bschematically and exemplarily illustrates a section of a vertical cross-section of a power semiconductor device1along a plane BB′ (indicated inFIG. 3) in accordance with one or more embodiments; and whereinFIG. 4cschematically and exemplarily illustrates a section of a vertical cross-section of a power semiconductor device in accordance with one or more embodiments

For example, providing the contacting means may include providing at least one of a lateral contact pad171,172, a central contact pad18and a contact pin19. Further, prior to providing the contacting means, the recess1555formed by the well structure155in the upper part151of the trench15may be filled with an insulator material168, as illustrated in each ofFIGS. 4a-c. For example, the insulator material168may electrically insulate the first electrode structure131from the second electrode structure132. In another embodiment, said recess1555is not completely filled with an insulator material, but may exhibit one or more cavities. In an embodiment, the insulator material168may include an inter-layer dielectric. Further, in order to create the contact pin19within the trench15, a deep oxide etch process may be carried out, e.g., a deep oxide etch process exhibiting low overlay tolerance. Additionally or alternatively, the second electrode structure132may be contacted with higher overlay tolerance, e.g., via a separate lithographic and isotropic etch step, in a region where the entire well structure has been removed, e.g., within the second lateral subregion ΔY2indicated inFIG. 3.

For example, referring toFIG. 4a, each of the one or more lateral contact pads171,172is entirely arranged external of the trench15and may contact the first electrode structure131, e.g. in a region where the first electrode structure131extends out of the trench15along and against the first lateral direction X, thereby forming, e.g., lateral landing pads supported by the surface10-1of the semiconductor body10, e.g., mounted on the oxide164that may cover said surface10-1. For example, the contact pads171,172may be arranged on top of said lateral landing pads that may be formed by the first electrode structure131. As has been explained above, the removing step28exemplary illustrated inFIG. 1can be carried out such that said regions of the first electrode structure131arranged slightly external of the trench15remain. In an embodiment, the one or more lateral contact pads171,172are provided at a transition region from the active region1-1to the edge region1-2, as illustrated inFIG. 3. Further, the lateral contact pads171,172may be electrically connected to a driver (not illustrated) that may provide a control signal to the first electrode structure131. In an embodiment, a first lateral contact pad171may be in contact with the first electrode1311, and the second lateral contact pad172may be in contact with the second electrode1312of the first electrode structure131. The two lateral contact pads171and172may be arranged separately from each other. It shall be understood that the first electrode1311may be electrically insulated from the second electrode1312such that the first electrode1311may be provided with an electrical potential different from an electrical potential provided to the second electrode1312, in accordance with one or more embodiments.

Regarding nowFIG. 4c, in a further embodiment, a central contact pad18may additionally or alternatively be provided. For example, the central contact pad18may extend into the trench15and may contact the first electrode structure131, e.g., each of its first electrode1311and its second electrode1312, as illustrated. For example, when choosing this way of contacting the first electrode structure131, during the removing step28, it must not necessarily be ensured that the first electrode structure131extends out of the trench15along and against the first lateral direction X. Rather, the step of removing the section of the monolithic electrode zone13can be carried out such that no part of the monolithic electrode zone13extends out of the trench15but rather that the electrode structures remain entirely within the trench15. Further, as an alternative or as an additional way of contacting the first electrode structure131, each of its first electrode1311and its second electrode1312can be contacted separately with a respective contact plug, e.g., by carrying out a high precision lithography processing step.

At this point, it shall be understood that both ways of contacting the first electrode structure131, namely by means of the one or more lateral landing paths171,172and/or by means of the central contact pad, may analogously be applied for contacting the second electrode structure132if, as illustrated inFIG. 3, in the third subregion ΔY3the monolithic electrode zone13is not divided during carrying out said removing step28.

A further possibility of contacting the second electrode structure132in accordance with one or more embodiments shall now be explained with respect toFIG. 3andFIG. 4b. For example, a contact pin19may be formed within the recess1555formed in the upper part151of the trench15by the well structure155. For example, the contact pin19is arranged within the trench15such that it laterally overlaps along the first lateral direction X and along with the second lateral direction Y with the second electrode structure132that is arranged in the lower part152of the trench15. Further, the contact pin19may be spatially displaced from the first electrode structure131and can be electrically insulated from the first electrode structure131, e.g., by means of the insulating material168. The contact pin19may thus contact the second electrode structure132with its first end191within the trench15and be configured, at its second end192arranged external of the trench15, to be contacted, e.g., by a first load terminal of the semiconductor device1, as will be explained below.

In an embodiment, one or more of the lateral contact pads171,172, the central contact pad18and the contact pin19are made of a metal.

FIG. 5schematically and exemplarily illustrates a section of a vertical cross-section of a power semiconductor device1in accordance with one or more embodiments.

For example, the semiconductor device1has been processed in accordance with an embodiment of the method2elucidated above. Thus, what has been stated above regarding the method2and the processed semiconductor device may equally apply to the semiconductor device1schematically illustrated inFIG. 5.

The power semiconductor device1may comprise a semiconductor body10coupled to a first load terminal11and a second load terminal12and configured to conduct a load current between said terminals11,12. The semiconductor body10may exhibit those regions that are necessary for forming, e.g., one or more of an IGBT-, an RC-IGBT-, a MOSFET-, a diode-, a MGD-configuration or a configuration derived therefrom that are known to the skilled person. To this end, the semiconductor body10may include a buffer region (not illustrated), also known as field-stop region, arranged in proximity to the second load terminal12, and/or one or more emitter regions also arranged in proximity to the second load terminal. Further, in proximity to the first load terminal11, there may be arranged each of a source region101and a channel region102. For example, the source region101is electrically connected to the first load terminal11, e.g., by means of one or more plugs111. The channel region102may be arranged so as to isolate the source region101from a drift region100of the semiconductor body10. For example, the drift region100and the channel region102a complementary doped; e.g., the drift region100comprises dopants of the first conductivity type and the channel region102comprises dopants of the second conductivity type. Further, the source region101may also be a semiconductor source region101and can comprise dopants of the same conductivity type as the drift region100, e.g., at a higher dopant concentration than the drift region100.

The power semiconductor device1may include a trench15extending into the semiconductor body10along the extension direction Z and comprising an insulator16, e.g., for insulating an interior region of the trench15from the semiconductor body10. For example, the load current may traverse the semiconductor body10along or against the extension direction Z, which can be a vertical direction. Each of the source region101and the channel region102may be arranged in contact with the trench sidewalls161.

Further, a first electrode structure131can be included in the trench15and configured to control the load current. Each of the source region101and the channel region102may be arranged such that they overlap with the first electrode structure131. For example, for setting the power semiconductor device1into a conducting state, during which the load current in a forward direction may be conducted between the load terminals11and12, the first electrode structure131may be provided with a control signal having a voltage within a first range so as to induce a load current path within the channel region102, e.g., an inversion channel. In an embodiment, for setting the power semiconductor device1into a blocking state, during which a forward voltage applied to the load terminals11,12may be blocked and flow of the load current in the forward direction is inhibited, the first electrode structure131may be provided with the control signal having a voltage within a second range different from the first range so as to cut off the load current path in the channel region102. Then, the forward voltage may induce a depletion region at a junction formed by a transition between the channel region102and the drift region100of the power semiconductor device, wherein the depletion region is also called “space charge region” and may mainly expand into the drift region100of the semiconductor device1. In this context, the channel region102is frequently also referred to as a “body region”, in which said load current path, e.g., an inversion channel, may be induced by the control signal to set the semiconductor device1in the conducting state. Without the load current path in the channel region102, the channel region102may form a blocking junction with the drift region100.

In addition, a second electrode structure132may be included in the trench15and can be arranged separately and electrically insulated from the first electrode structure131. The first electrode structure131and the second electrode structure132can be spatially displaced from each other along the extension direction Z such that they do not exhibit a common extension range along the extension direction Z.

The second electrode structure132may extend further along the extension direction Z than the first electrode structure131. In other words, the second electrode structure132may be arranged in a lower part152of the trench15and the first electrode structure131may be arranged in an upper part151of the trench15.

Further the insulator16may form trench sidewalls161and a trench bottom162, and the first electrode structure131may comprises at least two electrodes, a first electrode1311being arranged at one of the trench sidewalls161and a second electrode1312being arranged at the other one of the trench sidewalls161. As has been explained above, in the upper part151of the trench15, the insulator16may be formed by the oxide164that may have been produced during method step224illustrated inFIG. 2. A distance along the first lateral direction X between the first electrode1311and the second electrode1312may be greater than a total extension of the second electrode structure132in said first lateral direction X. Thus, in a vertical cross-section, neither the first electrode1311nor the second electrode1312has a common extension range with second electrode structure132along the first lateral direction X, in accordance with one or more embodiments.

In an embodiment, the first electrode1311is configured to induce a first inversion channel in a first section of the channel region102adjacent to one of the trench sidewalls161, and the second electrode1312is configured to induce a second inversion channel in a second section of the channel region102adjacent to the other one of the trench sidewalls161. For example, the first inversion channel exhibits a cut-off voltage different from the cut-off voltage of the second inversion channel. To this end, the effective thickness of the oxide164insulating the first electrode1311from the semiconductor body10may be different from the effective thickness of the oxide164insulating the second electrode1312from the semiconductor body10. Herein, a comparison between the “effective thicknesses” of the oxide164may mean that the product of the dielectric constant of the dielectric used for the oxide164insulating the first electrode1311from the first section of the channel region102multiplied with its thickness is compared to the product of the dielectric constant of the dielectric used for the oxide164insulating the second electrode1312from the second section of the channel region102multiplied with its thickness. In case said dielectrics being made of the same material, e. g. a silicon dioxide, this reduces to a comparison of the respective thicknesses. In case, e. g., the dielectric used for the oxide164insulating the first electrode1311from the first section of the channel region102has a different dielectric constant than the dielectric used for the oxide164insulating the second electrode1312, the said thicknesses may be identical to each other, while the cut-off voltages still differ.

Each of the first electrode structure131and the second electrode structure132may comprise a metal.

In an embodiment, the first electrode structure131is electrically connected to a driver (not illustrated) configured to provide said control signal, e.g., by applying a voltage between the first load terminal11and the first electrode structure131. It shall be understood that the first electrode structure131can be electrically insulated from each of the first load terminal11and the second load terminal12. Thus, the first electrode structure131may act as a control electrode structure, e.g., a gate electrode structure.

The second electrode structure132can be electrically connected to another electrical potential as the first electrode structure131; e.g., the second electrode structure132is electrically connected to the first load terminal11. Thus, the second electrode structure132may act as a field electrode structure, e.g., a field plate structure.

For contacting the first electrode structure131and the second electrode structure132, said contacting means that have been described with respect to the method2can be provided. For example, the first electrode structure131is contacted by means of the central contact pad18exemplarily illustrated inFIG. 4c, and the second electrode structure132may be contacted by the contact pin19exemplarily illustrated inFIG. 4b.

Even though, in the above, aspects of a semiconductor device exhibiting a trench in a stripe configuration and aspects of processing such semiconductor device have been explained, it shall be understood that the principles, e.g., the step of removing a section of the monolithic electrode zone13, e.g., step28, and/or the step of structuring the insulator16, e.g., step22, including steps221-1,221-2,222,223and224, as laid out above may also be applied to trench exhibiting a needle configuration.

For example, by using metal as a material for the monolithic electrode zone13, each of the first electrode structure131and the second electrode structure132may exhibit a comparatively low resistance, e.g., a lower resistance than such resistance that is achievable when using a semiconductor material, e.g., polysilicon.

The embodiments described above include the recognition that by using a first deposition for forming a first electrode structure within a trench and by using a separate deposition for forming a second electrode structure within the trench afterwards can be comparatively costly and complex. Further, when using a semiconductor material for the electrode structures, only comparatively high resistance values can be achieved.

In accordance with one or more embodiments, each of the second electrode structure132, e.g., a field plate, and the first electrode structure131, e.g., one or two gate electrodes, can be simultaneously be provided within the same trench, e.g., while at the same time avoiding the need for a high temperature process. Further in accordance with one or more embodiments, a metal is used as a material for the monolithic electrode zone13, i.e., as a material for each of the first electrode structure131and the second electrode structure132.

In the above, embodiments pertaining to semiconductor device processing methods were explained. For example, these semiconductor devices are based on silicon (Si). Accordingly, a monocrystalline semiconductor region or layer, e.g., the semiconductor body10, the drift region100, the substrate110, the source region101, the channel region102of exemplary embodiments, can be a monocrystalline Si-region or Si-layer. In other embodiments, polycrystalline or amorphous silicon may be employed.

It should, however, be understood that the semiconductor body10and components, e.g., regions100,110,101and102can be made of any semiconductor material suitable for manufacturing a semiconductor device. Examples of such materials include, without being limited thereto, elementary semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe) to name few. The aforementioned semiconductor materials are also referred to as “homojunction semiconductor materials”. When combining two different semiconductor materials a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, without being limited thereto, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x) and silicon-SiGe heterojunction semiconductor materials. For power semiconductor devices applications currently mainly Si, SiC, GaAs and GaN materials are used.