Apparatus and method with improved power-down mode

A power-down circuit (72) in a lap-top computer (10) cooperates with a separate monitor circuit (80) in each of a plurality of modules (68, 74, 76) that a video-display-controller integrated circuit (36) includes. In response to various stimuli, decoding logic (78) in the power-down circuit sends respective power-down-request signals to the various monitor circuits request permission to suppress application of respective clock signals to them. If a module's operational circuitry (82) is in a state in which clock removal is safe, the monitor circuit (80) responds with an acknowledgment signal, and the power-down circuit (72) causes a clock generator to interpret application of clock signals to the respective module (68). The monitor circuit (80) may additionally detect circumstances in which removing the clock signal from the operational circuitry (82) is safe only if the clock signal can subsequently be re-applied rapidly. In those circumstances, the monitor circuit (80) generates an idle signal that causes the power-down circuit (72) to stop clocking the associated operational circuitry but continue clocking the monitor circuit. In this way, the monitor circuit can keep operating so as to detect circumstances that will necessitate re-starting operational-circuit clocking. When it detects such a condition, it rapidly de-asserts the idle signal so that the clock signal is rapidly re-applied to the associated operational circuit.

BACKGROUND OF THE INVENTION 
The present invention is directed to computer systems and in particular to 
the power-conservation systems that they employ. 
In lap-top and similar portable computers, one of the most critical 
features is the computer's power consumption: the less power the computer 
requires, the longer it can be used without recharging its batteries. In 
addition to expending a great deal of effort in reducing the power that 
various components draw when they are operating, therefore, workers in 
this art have additionally provided their computer systems with power-down 
circuitry, which turns off parts of the computer system when they are not 
needed. In U.S. Pat. No. 5,708,819 to Dunnihoo, for instance, a computer 
system's input-output controller removes power from the keyboard, 
floppy-disc controller, etc., when they are not in use. Similarly, U.S. 
Pat. No. 5,710,929 to Fung includes a power-control circuit that causes 
various of a computer's components to assume power-on, doze, sleep, 
suspend, and off states. By monitoring an input/output bus for various 
address ranges, it determines which states the various components should 
assume. And various network computer systems disclosed in U.S. Pat. No. 
5,692,197 to Narad et al. determine when to enter respective power-down 
states, from which they may "wake" in response to various external 
signals. 
While all of these approaches do serve the purpose of limiting power use, 
the fact remains that portable-computer battery life in general remains 
shorter than users would prefer. 
SUMMARY OF THE INVENTION 
I have recognized that overall power consumption can be reduced 
significantly further if separate modules within an individual integrated 
circuit employ a combination of active and passive power-down control. The 
way to implement this is to provide each of a number of the integrated 
circuit's modules with respective monitor circuits that are clocked by 
monitor-clock signals separate from main-clock signals that clock these 
modules' operational circuitry. 
Since the monitor circuits are dedicated to respective individual modules, 
they can be optimized to that particular module's activity and thus detect 
with particular exactitude the conditions in which it is safe to interrupt 
of those modules' main clock signals and thereby minimize their power 
consumption. As soon as such a condition is detected, the monitor circuit 
asserts an idle signal that causes the respective module's main-clock 
application to be inhibited. The monitor circuit is able to continue its 
monitoring operation because it is separately clocked. So it can detect 
when the module must again be activated, and it can de-assert the idle 
signal and thereby permits application of the associated main-clock 
signal. 
In accordance with the invention, though, the monitor circuit's power 
consumption, too, can be inhibited at an appropriate time. Specifically, 
the integrated circuit additionally includes a power-down controller that 
determines, typically in response to various external stimuli, when it 
would be desirable to reduce power consumption more completely. When this 
occurs, the power-down controller sends the monitor circuit a power-down 
request signal. In response to the signal, the monitor circuit determines 
whether the module is in a condition from which it is safe to remove clock 
application completely, possibly after taking action to place it in such a 
state. In any case, it sends the power-down circuit an acknowledgment 
signal when such a state is reached, and the power-down circuit then 
removes both that module's main-clock signal and the monitor-clock signal 
applied to its monitor circuit. By using this approach, the integrated 
circuit can provide the capability for a general power removal and yet 
afford a very fine-grained control of individual modules' power usage.

DETAILED DESCRIPTION OF AN ILLUSTRATIVE EMBODIMENT 
FIG. 1 depicts a computer system 10 that includes a notebook computer 12 
and an additional display device 14 interfaced with the notebook computer 
via a cable 16. The additional display device 14 is illustrated as a 
conventional television. Those ordinarily skilled in the pertinent arts 
will recognize that the television accepts signals in NTSC format and 
displays an interlaced image. Alternatively, the computer system 10 may be 
interfaced with a conventional CRT monitor using RGB signals and providing 
a non-interlaced image. The notebook computer includes various input 
devices, such as a keyboard 18, a floppy disk drive 20, and a track ball 
22. Those ordinarily skilled in the pertinent arts will recognize that the 
track ball is essentially a stationary mouse input device. The computer 
system 10 may include additional input devices, such as a hard disk drive, 
a CD-ROM, and a serial input-output (I/O) port. Several of these devices 
also function as output devices for the computer system 10 in addition to 
a liquid crystal display 24. As described hereinbelow, the display 24 is 
presented as being of dual panel type. As depicted, the notebook computer 
is being used to perform a multi-task operation. For example, the notebook 
computer 12 may be used to conduct a financial analysis, the data for 
which is displayed on LCD 24, and a graphical depiction of which is 
displayed on CRT 14. 
FIG. 2 provides a schematic block diagram of the computer system 10, with 
the input devices all subsumed within one representative block 26. The 
input devices are interfaced with a microprocessor 28, which also has an 
interface with a memory facility 30. The memory facility 30 will include 
the floppy disk drive 20, and may include a hard disk drive, CD-ROM, and 
other devices. A data bus 32 interfaces with the microprocessor 28 and 
provides an interface with the output devices, including the LCD and CRT 
image display devices 14 and 24. The other output devices for the computer 
system 10 are subsumed in a representative block 34. In order to 
facilitate the interface with the image display devices 14 and 24, the 
computer system 10 includes a video display controller (VDC) 36 
interfacing with the bus 32 and providing driving signals for the LCD 24 
and CRT 14. The VDC has an interface with dynamic random access memory 
(DRAM), represented on FIG. 2 with the schematic blocks 38. Also, the VDC 
has an interface with a power management facility 40 of the computer 
system 10. A dedicated clock 42 provides a reference clock rate to the VDC 
36. 
FIG. 3 shows that the VDC 36 includes an internal clock 44 referenced to 
the clock signal from the dedicated clock 42, and providing clock signals 
to a video section 46 of the VDC. In order to interface the video section 
46 with the bus 32, and hence with the microprocessor 28, the video 
section 46 includes a programmable host interface 48. The host interface 
48 is programmable to configure the VDC 36 for interface with a number of 
conventional bus configurations. For example, host interface 48 may be 
configured for interface with a conventional Intel 486DX local bus, with a 
VL-Bus, and with a PCI interface bus. The host interface 48 interfaces the 
bus 32 with a VGA core portion 50 of the VDC 36. This VGA core portion 50 
includes a sequencer, to be further described below, a cathode ray tube 
controller (CRTC), a graphics controller, an attribute controller, and 
conventional VGA circuitry. 
In order to allow the VGA core 50 to generate and control the text, 
graphics and other visual characters to be displayed on the CRT and LCD 
(such as a cursor and icons, for example), the VGA core is interfaced with 
a hardware cursor generator 52, a bit-BLT engine 54, and a display FIFO 
56. An additional two display FIFOs 56', and 56" are also interfaced with 
the VGA core 50 to support the computer system 10's dual-display 
operation. 
The hardware cursor generator 52 selectively provides a cursor of increased 
size (i.e., twice as large as normal, for example), which is easier to 
visually follow as it moves across a display screen, in response to 
detection of a certain preselected speed of movement of the cursor 
provided by a software program running on microprocessor 28. Thus, when a 
user of the computer system 10 uses the mouse or keyboard keys to move the 
cursor of a program, if the speed of movement reaches the preselected 
threshold, then the cursor becomes doubled or larger. The bit-BLT engine, 
as was explained earlier, provides for block transfers of bits generated 
to provide graphics and other such visual characters on the CRT and LCD 
screens 14 and 24. 
Each of the hardware cursor generator 52, bit-BLT 54, and display FIFO 56 
are also interfaced with a DRAM controller 58. This DRAM controller 58 
implements the functions of the DRAM controller/sequencer described in 
general terms above to arbitrate and implement requests for access to the 
DRAM by various functional units of the computer system 10, including 
other portions of the VDC 36. As is seen in FIG. 3, the DRAM controller 50 
has an interface with the DRAM 38. The display FIFO 56 has an interface 
(via the VGA controller 50 and DRAM controller 58) with both a palette 
controller 60 and a liquid crystal display (LCD) interface controller 62. 
The palette controller implements the standard 256-by-18 VGA palette, 
while the LCD interface controller performs frame modulation and dithering 
for 64 shades of gray and 256 K colors. 
The VDC 36 includes a power-down controller 64. This power-down controller 
has an interconnection with a power-down register 65, which itself has a 
generalized interconnection within the VDC 36. This generalized 
interconnection of the power-down-register 65 is indicated on FIG. 3 with 
the plurality of arrows leaving the register 65. 
Part of the DRAM controller 58's circuitry is timed to operate in 
synchronism with the various display FIFOs 56', and 56". Another part, 
module 68 (FIG. 4), is instead synchronized to the timing of the DRAM 38 
(FIG. 3), as FIG. 3 indicates by its DRAM clock 70. 
As will be explained below, a portion 72 of FIG. 3's power-down circuit 64 
is dedicated to controlling power application to module 68 as well as 
other modules 74 and 76, which represent similarly synchronized portions 
of the various elements that FIG. 3 depicts. FIG. 4's circuitry is 
typically replicated for each "clock zone." Each clocked element in a 
single clock zone is clocked by a clock signal of a common frequency 
associated with that zone or by a clock signal whose frequency is an 
integer submultiple of that common frequency. Also, the leading edges of 
all clocks in the same clock zone coincide. 
As FIG. 5 illustrates, the power-down circuitry 72 includes decoding logic 
78, which determines, on the basis of inputs from various of the 
video-display controller 36's input pins and the contents of its registers 
65 (FIG. 3), whether conditions are such that it is appropriate to remove 
power from all or a subset of the video-display controller 36's modules. 
If so, it sends respective request signals REQ [1:N] to the modules that 
are to be powered down. Specifically, it sends them to respective monitor 
circuits, such as module 68's monitor circuit 80. Circuit 80 treats the 
respective request signal as asking whether its respective module 68 is in 
a state from which all of its clock signals can safely be suppressed. 
In the case of the DRAM controller 58, for instance, a state may have been 
reached in which no further data are to be applied to the DRAM controller 
58 for storage into the DRAM 38. This suggests that it may be appropriate 
to power-down the DRAM controller 58, so the decode logic 78 of FIG. 5 
sends a request signal REQ.sub.1 to module 68's monitor circuit 80 to ask 
whether clock removal is safe. But module 68's operational circuitry 82 
may still be in the process of loading previously received data into the 
DRAM 38, in which case the monitor circuit 80, which observes the 
operational circuitry 82's operation, will not respond with a 
corresponding acknowledgment signal (ACK.sub.i) until that loading 
operation has been completed. When the loading operation ends, though, the 
monitor circuit 80 concludes that it is appropriate to power module 68 
down, and it accordingly asserts ACK.sub.1 to indicate this condition. 
FIG. 5's power-down circuit segment 84 is one of a number of segments that 
the power-down circuit provides for respective ones of the modules that 
FIG. 4 depicts. When a given monitor circuit asserts its acknowledgment 
signal ACK.sub.i in response to its respective request signal REQ.sub.i, 
the resultant asserted output of AND gate 86 is latched in by a D-type 
flip-flop 88 after inversion and causes an OR gate 90 to assert its 
output, which another D-type flip-flop 92 latches in after inversion. 
These flip-flops 88 and 92 receive as their common clock input a 
power-down-clock signal PD.sub.-- CLK, which FIG. 6's enabled 
skew-aligning gate 96 generates from the root-clock signal ROOT.sub.-- CLK 
that FIG. 3's clock generator 44 produces for the clock zone that the FIG. 
4 circuitry occupies. 
On PD.sub.-- CLK's next negative-going transition, FIG. 5's flip-flops 88 
and 92 latch in the values of their de-asserted inputs to de-assert clock 
signals MAIN.sub.-- CLK.sub.-- EN.sub.i and MON.sub.-- CLK.sub.-- 
EN.sub.i. The power-down circuitry 72 sends the thus de-asserted 
clock-enabling signals to clock generator 44. As FIG. 6 indicates, the 
clock generator includes a gating segment such as the illustrated gating 
segment 98 for each of FIG. 4's modules, and the de-asserted 
clock-enabling signals MAIN.sub.-- CLK.sub.-- EN.sub.i disable the gates 
100 and 102 whose out-puts MAIN.sub.-- CLK.sub.i and MON.sub.-- CLK.sub.i 
ordinarily clock a corresponding module's operational circuitry and 
monitor element, respectively. This effectively suppresses power 
dissipation in the associated (typically CMOS) module. 
In this way, various system- or chip-wide criteria may be employed to 
determine whether to request a power-down sequence, whereas a local 
monitoring circuit, which can be designed specifically for an individual 
module's characteristics, determines whether the particular module can 
actually be powered down. The monitoring circuit may additionally perform 
various functions that prepare the module for the powered-down condition. 
In accordance with my invention, though, the monitor circuits provide an 
opportunity for even finer-grained power control. In most modules, there 
are situations in which most of the circuitry could be powered down safely 
if it were possible to return power quickly under various circumstances. 
The criteria for determining whether such a state can be entered depend 
very much on the particular module's specific features, as do the 
situations that require power to be re-applied. My invention lends itself 
particularly to tailoring power removal and re-application to a particular 
module's characteristics. In accordance with the invention, the monitor 
circuits receive monitor clocks MON.sub.-- CLK.sub.i that are separate 
from the main clock signals MAIN.sub.-- CLK.sub.i by which the monitored 
operational circuitry is timed. So the monitor circuits can call for power 
removal even when power re-application may subsequently have to be 
re-applied rapidly, and they can individually monitor their associated 
operational circuitry's environment for indications that power needs to be 
reapplied. 
Specifically, when a monitor circuit detects a situation in which power 
removal is appropriate, it sends the power-down circuitry a respective 
idle signal IDLE.sub.i. As FIG. 5 shows, this causes NOR gate 90 to 
de-assert flip-flop 92's input so that a de-asserted MAIN.sub.-- 
CLK.sub.-- EN.sub.i signal will disable FIG. 6's gate 100. That gate 
thereupon suppresses the MAIN.sub.-- CLK.sub.i signal that clocks the 
associated operational circuitry. But the monitor circuitry that generates 
the idle signal still receives its separate monitor clock, so it can 
continue to operate and determine when power must be re-applied, to its 
associated operational circuitry. When it does determine that power should 
be re-applied, it de-asserts its idle signal, thereby causing its 
associated operational circuitry's main clock signal to be re-applied. 
Since a module's monitor circuit is clocked separately from its 
operational circuitry, the operational circuitry can be powered down in 
situations in which doing so would otherwise be unsafe because of the 
speed with which it may need to be powered back up. 
Although the illustrated embodiment depicts a single individual main clock 
for each individual monitor clock, there is no reason why the present 
invention's advantages cannot be realized without such a one-to-one 
correspondence. That is, a single one of the monitor circuits, which 
receives a single monitor-clock signal, could monitor a plurality of 
separately clocked operational circuits, generating a different idle 
signal for each. Also, although the illustrated embodiment employs a 
separate request signal for each of the modules, the invention's broader 
teachings can be implemented in embodiments that employ a common request 
signal for all modules, at least within the same clock zone. Finally, 
although the foregoing description specifically discusses only the 
power-down circuitry associated with a single root clock for a single 
clock zone, a typical embodiment will duplicate the illustrated power-down 
circuitry for each of its clock zones. 
So the present invention can be implemented in a wide range of embodiments 
and this constitutes a significant advance in the art.