Semiconductor package assembly with redistribution layer (RDL) trace

The invention provides a semiconductor package assembly. The semiconductor package assembly includes a substrate having a first pad and a second pad thereon. A logic die is mounted on the substrate. The logic die includes a first logic die pad coupled to the first pad. A memory die is mounted on the substrate. The memory die includes a first memory die pad. A first redistribution layer (RDL) trace has a first terminal and a second terminal. The first terminal is coupled to the first pad through the first memory die pad. The second terminal is coupled to the second pad rather than the first pad.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a semiconductor package assembly, and in particular to a memory die integrated into a system-in-package (SIP) package assembly.

Description of the Related Art

In order to ensure miniaturization and multi-functionality of electronic products and communication devices, it is desired that semiconductor packages be small in size, to support multi-pin connection, high speeds, and high functionality. The multi-functional system-in-package (SIP) package usually requires integrating discrete logic dies and memory dies. The memory die usually uses a redistribution layer (RDL) ground trace with a long length for the connection between the memory die and the logic die. In the design of a system-in-package (SIP) package for radio frequency (RF) applications, however, the long redistribution layer (RDL) ground trace causes the undesired signal integrity problem and noise coupling problem.

Thus, a novel semiconductor package assembly is desirable.

BRIEF SUMMARY OF THE INVENTION

An exemplary embodiment of a semiconductor package assembly is provided. The semiconductor package assembly includes a substrate having a first pad and a second pad thereon. A logic die is mounted on the substrate. The logic die includes a first logic die pad coupled to the second pad. A memory die is mounted on the substrate. The memory die includes a first memory die pad. A first redistribution layer (RDL) trace has a first terminal and a second terminal. The first terminal is coupled to the first pad through the first memory die pad. The second terminal is coupled to the second pad rather than the first pad.

Another exemplary embodiment of a semiconductor package assembly includes a substrate having a first pad and a second pad thereon. A memory die having a first side and a second side is mounted on the substrate. The memory die includes a memory die pad close to the first side and coupled to the first pad. A redistribution layer (RDL) trace has a first terminal close to the first side and a second terminal close to the second side. The first terminal is coupled to the first pad through the memory die pad. The second terminal is coupled to the second pad close to the second side through a first single conductive routing. A logic die is mounted on the substrate. The logic die includes a logic die pad close to the second side and coupled to the second pad.

Yet another exemplary embodiment of a semiconductor package assembly includes a substrate having a first ground pad and a second ground pad thereon. A memory die is mounted on the substrate. The memory die includes a memory ground pad coupled to the first ground pad. A redistribution layer (RDL) ground trace has a first terminal and a second terminal. The first terminal is coupled to the first ground pad through a first conductive path including the memory ground pad. The second terminal is coupled to the second ground pad through a second conductive path that is not coupled to the memory ground pad. A logic die is mounted on the substrate. The logic die includes a logic ground pad coupled to the second terminal through the second ground pad.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and the relative dimensions do not correspond to actual dimensions in the practice of the invention.

Embodiments provide a semiconductor package assembly. The semiconductor package assembly is a system-in-package (SIP). The semiconductor package assembly includes at least a logic die and at least a memory die. The memory die includes a redistribution layer (RDL) ground trace with two terminals opposite to each other. One of the two terminals is designed to be close to and to be coupled to the ground pad of the memory die. The other of the two terminals of the redistribution layer (RDL) ground trace is used as a ground pad of the logic die. The semiconductor package assembly is designed to add grounding points at the two terminals of the redistribution layer (RDL) ground trace to avoid the potential different between the two terminals of the RDL ground trace with a long length. Also, the additional grounding points for the RDL ground trace can reduce radio frequency (RF) interference due to the long RDL ground trace.

FIG. 1is a plan view of semiconductor package assemblies500aand500bin accordance with some embodiments of the disclosure.FIGS. 3-4are cross-sectional views ofFIG. 1, showing the arrangements of the substrate, the logic die, the memory die and the redistribution layer (RDL) ground trace of the memory die of the semiconductor package assembly shown inFIG. 1. For clearly showing the arrangement of the substrate, the logic die, the memory die and the redistribution layer (RDL) ground trace of the memory die of the semiconductor package assemblies500aand500b, a molding compound is not shown inFIG. 1.

As shown inFIGS. 1 and 3, the semiconductor package assembly500ais mounted on a base800through a plurality of conductive structures710. In some embodiments, the semiconductor package assembly500aserves as a system-in-package (SIP). In some embodiments, the base800may include a printed circuit board (PCB). The conductive structures710may include conductive bump structures such as copper bumps, solder ball structures, solder bump structures, conductive pillar structures, conductive wire structures, or conductive paste structures. The semiconductor package assembly500aincludes a substrate700, a semiconductor die (logic die)100a, a semiconductor die (memory die)200aand a redistribution layer (RDL) ground trace240of the memory die200a. It should be noted that the substrate700, the logic die100aand the memory die200aare discrete, individual elements of the semiconductor package assembly500a.

As shown inFIGS. 1 and 3, a substrate700is provided. The substrate700includes a die-attached surface701for the logic die100aand the memory die200amounted thereon. The substrate700includes several discrete ground pads102and104disposed close to the die-attached surface701. In some embodiments, the ground pads102and104are used for input/output (I/O) connections to ground. Therefore, the ground pads102and104also serve as ground pads of the substrate700. The substrate700may also include an interconnection (not shown) formed therein to be coupled to the ground pads102and104. In some embodiments, the substrate700may comprise a semiconductor substrate, such as a silicon substrate. In some other embodiments, the substrate700may comprise a dielectric material such as an organic material. In some embodiments, the organic material includes polypropylene (PP) with glass fiber, epoxy resin, polyimide, cyanate ester, other suitable materials, or a combination thereof.

As shown inFIGS. 1 and 3, the semiconductor die100ais disposed on the substrate700. The semiconductor die100amay be mounted on the die-attached surface701of the substrate700through an adhesive112(for example, paste) between the semiconductor die100aand the substrate700. In some embodiments, the semiconductor die100ais coupled to the substrate700through wire bonding technology. In some embodiments, and as shown inFIG. 3, the semiconductor die100ais coupled to the substrate700through conductive structures comprising conductive wires, for example, a conductive wire320a. In some embodiments, the semiconductor die100amay serve as a logic die100aincluding a central processing unit (CPU), a graphics processing unit (GPU), a dynamic random access memory (DRAM) controller, or any combination thereof.

As shown inFIGS. 1 and 3, the semiconductor die200ais stacked and mounted directly on the semiconductor die100athrough an adhesive212(for example, paste) between the semiconductor dies100aand200a. In some embodiments, the semiconductor die200amay serve as a memory die200a, for example, a dynamic random access memory (DRAM) die. In some embodiments, the semiconductor die200ais coupled to the substrate700through the wire bonding technology. As shown inFIG. 3, the semiconductor die200ais coupled to the substrate700through conductive structures comprising conductive wires, for example, conductive wires300aand310a.

As shown inFIGS. 1 and 3, the memory die200amay comprise a memory I/O die pad202and a redistribution layer (RDL) structure270aon the memory I/O die pad202of the memory die200a. In some embodiments, the memory die220amay be a DRAM die or multiple DRAM dies. The RDL structure270amay comprise at least a redistribution layer (RDL) trace240and at least a pad250a. The RDL trace240and the pad250aare used for input/output (I/O) connections to ground. In some embodiments as shown inFIG. 3, the RDL trace240serves as a RDL ground trace240. The RDL trace240is designed to be positioned at a single layered-level of the RDL structure270a. In some embodiments as shown inFIG. 3, the pad250ais disposed within an input/output (I/O) pad region210and on the top of the RDL structure270a. The pad250aserves as a ground pad of the memory die200a.

The RDL trace240is used to fan out or re-route the ground path of the memory I/O die pad202from the position of the pad250ato a specific position (for example, the specific position is close to an input/output (I/O) pad region110of the logic die100a). The RDL ground trace240of the memory die200amay have a long length. As shown inFIGS. 1 and 3, the RDL ground trace240of the memory die200ais designed to be extended from a first side220to a second side222of the memory die200afor the connection between the memory die200aand the logic die100a. The RDL ground trace240has a first terminal242and a second terminal244away from the first terminal242. The first terminal242is coupled to the pad250aclose thereto. The pad250aof the memory die200ais coupled to the ground pad102of the substrate700close thereto. In some embodiments, the first terminal242of the RDL ground trace240and the pad250aof the memory die200aare both arranged to be close to the first side220of the memory die200a. The ground pad102of the substrate700is arranged close to the first side220of the memory die200a. Also, the ground pad102of the substrate700is arranged close to the pad250aof the memory die200ato reduce the ground path from the memory die200ato the substrate700.

As shown inFIGS. 1 and 3, the pad250aof the memory die200ais coupled to the ground pad102through a conductive routing300a, for example, a bonding wire. It should be noted that the conductive routing300ais a single bonding wire which has two terminals in contact with the pad250aand the ground pad102, respectively. The conductive routing300ais not in contact with the ground pad104.

As shown inFIGS. 1 and 3, the second terminal244of the RDL ground trace240is coupled to a ground pad of the substrate700, for example, the ground pad104, rather than the ground pad102. The second terminal244of the RDL ground trace240is coupled to the ground pad104without using the pad250aand the ground pad102. In some embodiments, the second terminal244of the RDL ground trace240and the ground pad104are both arranged close to the second side222of the memory die200a. The first side220and the second side222are different sides of the memory die200a. The second terminal244of the RDL ground trace240is coupled to the ground pad104through a conductive routing310a, for example, a bonding wire. It should be noted that the conductive routing310ais a single bonding wire which has two terminals in contact with the second terminal244and the ground pad104, respectively. The single conductive routing310ais not in contact with the ground pad102and the conductive routing300a.

As shown inFIGS. 1 and 3, the logic die100amay comprise a logic device (not shown) and a redistribution layer (RDL) structure (not shown) on the logic device. The redistribution layer (RDL) structure of the logic die100amay comprise at least a redistribution layer (RDL) trace and at least a pad150a, which is used to transmit a ground signal from the logic device. In some embodiments as shown inFIG. 3, the pad150ais disposed on the top of the RDL structure. The pad150ais disposed within an input/output (I/O) pad region110of the logic die100a. The pad150aserves as a ground pad of the logic die100a.

As shown inFIGS. 1 and 3, the pad150aof the logic die100ais coupled to the ground pad104of the substrate700only through a conductive routing320a, for example, a bonding wire. In some embodiments, the pad150aof the logic die100ais not coupled to the ground pad102of the substrate700. The conductive routings300a,310aand320aare different conductive routings. That is to say, the conductive routing320ais not in contact with the conductive routings300aand310a.

The RDL structure270aof the semiconductor die200aas shown inFIG. 3may comprise a second redistribution layer (RDL) trace260and at least a pad252acoupled to the second RDL trace260, as shown inFIG. 1. In some embodiments, as shown inFIG. 1, the second RDL trace260is arranged close to and parallel to the RDL ground trace240. Similar to the RDL ground trace240, the second RDL trace260of the memory die200amay have a long length. The second RDL trace260of the memory die200ais designed to be extended from the first side220to the second side222of the memory die200a.

The second RDL trace260and the pad252aare used for input/output (I/O) connections to signals of the memory I/O die pad202. The second RDL trace260may serve as a RDL signal trace. The second RDL trace260is not coupled to the ground pads102and104of the substrate700. In some embodiments, the pad252ais also disposed on the top of the RDL structure (for example, the RDL structure270aas shown inFIG. 3). The pad252aserves as a signal pad of the memory die200a. The pad252ais located within the input/output (I/O) pad region210. Also, the pad252ais close to the pad250aand isolated from the pad250a.

As shown inFIG. 1, the second RDL signal trace260has a third terminal262and a fourth terminal264away from the third terminal262. The third terminal262of the second RDL signal trace260is located close to the first terminal242of the RDL ground trace240. Also, the fourth terminal264of the second RDL signal trace260is located close to the second terminal244of the RDL ground trace240. The third terminal262is coupled to the pad252aclose thereto. The pad252aof the memory die200ais coupled to the corresponding signal pad (not shown) of the substrate700. The fourth terminal of the second RDL signal trace260is coupled to a pad152of the logic die100athrough conductive routings330,340and a conductive structure720of the substrate700. In some embodiments, the conductive routings330and340may comprise bonding wires. The conductive structure720of the substrate700may comprise circuitries and pads.

In some embodiments as shown inFIG. 1, the pad152of the logic die100ais located close to the pad150aand is electrically isolated from the pad150a. The pad152may serve as a signal pad of the logic die100a.

As shown inFIG. 3, the semiconductor package assembly500afurther includes a molding compound750surrounding the logic die100a, the memory die200aand the conductive routings, which include the conductive routings300a,310aand320a. The molding compound750is in contact with the logic die100a, the memory die200aand the conductive routings300a,310aand320a. The molded compound750also covers the die-attached surface701of the substrate700. In some embodiments, the molded compound750may be formed of a nonconductive material, such as an epoxy, a resin, a moldable polymer, or the like. The molding compound750may be applied while substantially liquid, and then may be cured through a chemical reaction, such as in an epoxy or resin. In some other embodiments, the molding compound750may be an ultraviolet (UV) or thermally cured polymer applied as a gel or malleable solid capable of being disposed around the logic die100aand the memory die200a, and then may be cured through a UV or thermally curing process. The molding compound750may be cured with a mold.

FIG. 4is a cross-sectional view ofFIG. 1, showing the arrangements of the substrate, the logic die, the memory die and the redistribution layer (RDL) ground trace of the memory die of a semiconductor package assembly500b. Elements of the embodiments hereinafter, that are the same or similar as those previously described with reference toFIGS. 1 and 3, are not repeated for brevity. The difference between the semiconductor package assembly500aand the semiconductor package assembly500bis that the semiconductor package assembly500bincludes a semiconductor die (logic die)100bdisposed on the substrate700through the flip-chip technology. In some embodiments, the semiconductor die100bmay serve as a logic die100b. The logic die100bmay comprise at least a pad150b, which is used for input/output (I/O) connections to ground. The pad150bserves as a ground pad of the logic die100b. The pad150bis disposed within an input/output (I/O) pad region110of the logic die100b, as shown inFIG. 1.

As shown inFIG. 4, the logic die100bis flipped upside-down and is coupled to the substrate700through a conductive structure160. The conductive structure160is disposed on the pad150b. The conductive structure160bmay include at least a conductive bump structure coupled to the corresponding pad150b. The conductive bump structure may comprise copper bumps or solder bump structures, conductive pillar structures, conductive wire structures, or conductive paste structures. The pad150bof the logic die100bis coupled to the to the ground pad104of the substrate700through an interconnect320b, for example, circuits, embedded in the substrate700.

FIG. 2is a plan view of a semiconductor package assembly500cin accordance with some embodiments of the disclosure. Elements of the embodiments hereinafter, that are the same or similar as those previously described with reference toFIGS. 1, 3 and 4, are not repeated for brevity. The differences between the semiconductor package assembly500a/500band the semiconductor package assembly500cis that the semiconductor die (logic die)100a/100bof the semiconductor package assembly500cfurther includes at least a radio frequency (RF) circuit360integrated in the semiconductor die (logic die)100a/100bfor RF applications.

FIG. 5is a plan view of semiconductor package assemblies500dand500ein accordance with some embodiments of the disclosure.FIGS. 6-7are cross-sectional views ofFIG. 5, showing the arrangements of the substrate, the logic die, the memory die and the redistribution layer (RDL) ground trace of the memory die of the semiconductor package assembly shown inFIG. 5. For clearly showing the arrangement of the substrate, the logic die, the memory die and the redistribution layer (RDL) ground trace of the memory die of the semiconductor package assemblies500dand500e, a molding compound is not shown inFIG. 5. Elements of the embodiments hereinafter, that are the same or similar as those previously described with reference toFIGS. 1-4, are not repeated for brevity.

As shown inFIGS. 5 and 6, the differences between the semiconductor package assembly500a/500b(shown inFIGS. 1-3) and the semiconductor package assembly500dis that the memory die200ais disposed beside the logic die100a. Therefore, the memory die200aand the logic die100aare mounted on the die-attach surface701of the substrate700by paste212and112b, respectively.

In some embodiments as shown inFIG. 6, the logic die100ais coupled to the substrate700through the wire bonding technology. The semiconductor die100amay be mounted on the die-attached surface701of the substrate700through an adhesive112(for example, paste) between the semiconductor die100aand the substrate700.

In some embodiments as shown inFIGS. 5 and 6, the first terminal242of the RDL ground trace240, the pad250aof the memory die200aand the ground pad102of the substrate700are arranged close to the first side220of the memory die200a. The second terminal244of the RDL ground trace240, the ground pad104and the pad150aof the logic die100aare both arranged close to the second side222of the memory die200a. Also, the ground pad104is disposed between the logic die100aand the memory die200aas shown inFIG. 6.

FIG. 7is a cross-sectional view ofFIG. 5, showing the arrangements of the substrate, the logic die, the memory die and the redistribution layer (RDL) ground trace of the memory die of a semiconductor package assembly500e. Elements of the embodiments hereinafter, that are the same or similar as those previously described with reference toFIGS. 5-6, are not repeated for brevity. The differences between the semiconductor package assembly500dand the semiconductor package assembly500eis that the semiconductor package assembly500eincludes a semiconductor die100band a semiconductor die200bdisposed on the substrate700through the flip-chip technology. In some embodiments, the semiconductor die100bserves as a logic die100b, and the semiconductor die200bmay serve as a memory die200b.

As shown inFIG. 7, the logic die100bmay comprise at least a pad150b, which is used for input/output (I/O) connections to ground. The pad150bserves as a ground pad of the logic die100b.

The memory die200bmay comprise may comprise a memory I/O die pad202and a redistribution layer (RDL) structure270bon the memory I/O die pad202. The RDL structure270bmay comprise at least a redistribution layer (RDL) trace240and at least two pads250band250c. The RDL trace240and the pad250band250care used for input/output (I/O) connections to ground. In some embodiments as shown inFIG. 7, the RDL trace240serves as a RDL ground trace240. The RDL trace240is designed to be positioned at a single layered-level of the RDL structure270b. The two terminals242and244of the RDL trace240are respectively coupled to the pads250band250c. The pads250band250cserve as ground pads of the memory die200a. The pad250bis disposed within the input/output (I/O) pad region210as shown inFIG. 5. The pad250cis disposed outside of the input/output (I/O) pad region210. For example, the pad250cis disposed close to the terminal244of the RDL trace240. Also, the pad250bis designed to be free from being in contact with the pad250c.

As shown inFIG. 7, the memory die200bis flipped upside-down and is coupled to the substrate700through conductive structures266and268. The conductive structures266and268are disposed on the pads250band250c, respectively. The conductive structures266and268may include conductive bump structures coupled to the corresponding pads250band250c. Also, the conductive structure266is designed to be free from being in contact with the conductive structure268. The ground pad250bof the memory die200bis coupled to the ground pad102of the substrate700through the conductive structure266and an interconnect300b. The pad250cof the memory die200bis coupled to the to the ground pad104of the substrate700through the conductive structure268and an interconnect320bembedded in the substrate700. In some embodiments, the interconnect300band320bare disposed embedded in the substrate700. The interconnect300band320bmay comprise circuits.

As shown inFIG. 7, the logic die100bis flipped upside-down and is coupled to the substrate700through a conductive structure160. The conductive structure160is disposed on the pad150b. The conductive structure160may include at least a conductive bump structure coupled to the corresponding pad150b. The pad150bof the logic die100bis coupled to the to the ground pad104of the substrate700through the conductive structure160and the interconnect320bof the substrate700. That is to say, the interconnect320belectrically connects to the pad250cof the memory die200b, the pad150bof the logic die100band the ground pad104of the substrate700. Also, the interconnect300band the interconnect320bare discrete circuits. The interconnect300bis designed to be free from being in contact with the interconnect320b.

Embodiments provide a semiconductor package assembly. The semiconductor package assembly includes a substrate, a memory die and a logic die mounted on the substrate. The memory die includes a redistribution layer (RDL) ground trace having a first terminal and a second terminal far away from the first terminal. The first and second terminals are located close to different sides of the memory die. The first terminal of the RDL ground trace is coupled to the first ground pad of the substrate through a first conductive path comprising a pad of the memory die, which is positioned within an input/output (I/O) pad region. The second terminal of the RDL ground trace is coupled to the second ground pad of the substrate through a second conductive path different from the first conductive path. The second conductive path is free from being coupled to the pad of the memory die. The logic die includes a pad coupled to the second terminal of the RDL ground trace through the second ground pad of the substrate.

The semiconductor package assembly is designed to have grounding paths at the two terminals of the redistribution layer (RDL) ground trace of the memory die. When the RDL ground trace of the memory die has a long length, the design of the RDL ground trace can improve signal integrity by reducing the crosstalk problem. When the semiconductor package assembly includes integrated radio frequency (RF) circuits in the logic die for RF applications, the RDL ground trace of the memory die also can improve the RF desense problem by reducing the coupled noise from the circuit of the memory die to the RF circuit of the logic die.