Graphic display control method and apparatus

A graphic display control method and apparatus wherein illumination of pixels on a display screen of an interlace type CRT in a first field and a second field is controlled so that each point on a line is displayed on the display screen of the interlace type CRT by a combined illumination of a pixel in the first field and the second field or a combined illumination of one of two vertically adjacent pixels in the first field or the second field and the second pixel in the second field or the first field. The smooth line is displayed by a series of points.

BACKGROUND OF THE INVENTION 
The present invention relates to a graphic display control method and 
apparatus which use an interlace type cathode ray tube (CRT). 
In a conventional raster scan type graphic display, when a diagonal line is 
to be displayed, it is displayed stepwise because light points are only 
provided at picture cells on raster lines. Accordingly, a smoothly 
continuous diagonal line could not be displayed. 
In order to resolve the above problem, it has been proposed to construct 
each point by a plurality of picture cells capable of being imparted with 
different luminances, and change the luminances in accordance with 
fractions derived by calculating coordinates of points on the diagonal 
line so that the diagonal line is displayed as a smooth line by the change 
of the luminances of the picture cells. FIGS. 18 and 19 show examples of 
the diagonal lines displayed by the luminance modulation type graphic 
display. In FIGS. 18 and 19, black block areas represent the luminances of 
the respective picture cells. 
However, in this luminance modulation type graphic display, the line width 
is large and not uniform because each of the points forming the line 
consists of a plurality of picture cells. 
SUMMARY OF THE INVENTION 
It is an object of the present invention to provide a graphic display 
control method and apparatus which can display a smooth and non-stepwise 
line on a CRT. 
It is another object of the present invention to provide a graphic display 
control method and apparatus which can prevent flickering which is likely 
to occur in an interlace type CRT. 
It is another object of the present invention to provide a graphic display 
control method and apparatus which can display a smooth line of different 
color from a a background color on an interlace type CRT. 
In accordance with the present invention, each picture cell on a CRT screen 
can be illuminated in a first field and a second field, the illumination 
of each picture cell in the first field and the second field is controlled 
in accordance with an operational result of coordinates of each of the 
points forming the line on the CRT screen, and the illumination position 
of the picture cell is shifted in an x-direction to eliminate the stepwise 
display of the line. 
Characteristic features of the present invention reside in that a raster 
scan type CRT is interlace-swept, the illumination of each picture cell on 
the CRT screen in the first field and the second field is controlled, one 
picture cell on the CRT screen is illuminated in the first field and the 
second field to display one point on the screen or one picture cell is 
illuminated in the first field or the second field and another picture 
cell which is vertically adjacent to the one picture cell is illuminated 
in the second field or the first field to display one point on the screen 
(in other words, one point is displayed on the CRT screen by a combination 
of illuminations of two vertically adjacent picture cells in the first and 
second fields), the illumination point on the CRT screen is horizontally 
shifted, and the line is displayed by a series of points.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
FIG. 1 shows a line (L) to be displayed on an interlace type CRT. The start 
point coordinate of the line (L) is (x.sub.0, y.sub.0), the end point 
coordinate is (x.sub.0 +.DELTA.x, y.sub.0 +.DELTA.y) and the gradient is 
(.DELTA.y/.DELTA.x). 
The start point coordinate (x.sub.0, y.sub.0), the x component (.DELTA.x), 
the y component (.DELTA.y), the gradient (.DELTA.y/.DELTA.x) or 
(.DELTA.x/.DELTA.y) and the color data of the line (L) are supplied from a 
processor. In FIG. 2, numeral 1 denotes a comparator which compares the x 
component and the y component of the line (L) and produces "0" if 
.DELTA.y.ltoreq..DELTA.x and "1" if .DELTA.y&gt;.DELTA.x. When the output 
(AXIS) of the comparator 1 is "0", it means that the X-axis is the main 
axis when a DDA (digital differential analyizer) is operated, and when the 
output AXIS is "1", it means that the Y-axis is the main axis. Numeral 2 
denotes the DDA, which sequentially calculates coordinates (x.sub.1, 
y.sub.1), (x.sub.2, y.sub.2), . . . (x.sub.n, y.sub.n) of points forming 
the line (L) based on the start point coordinate (x.sub.0, y.sub.0), the x 
component (.DELTA.x), the y component (.DELTA.y) and the gradient 
(.DELTA.y/.DELTA.x) or (.DELTA.x/.DELTA.y) supplied from the processor. 
The construction of the DDA 2 will now be explained in detail. In FIG. 2, 
numerals 3X and 3Y denote an X increment register and a Y increment 
register. When (AXIS) is "0", "1" is retained in the X increment register 
3X and (.DELTA.y/.DELTA.x) is retained in the Y increment register 3Y. 
When (AXIS) is "1", (.DELTA.x/.DELTA.y) is retained in the X increment 
register 3X and "1" is retained in the Y increment register 3Y. For the 
line (L) shown in FIG. 1, .DELTA.y&lt;.DELTA.x and hence (AXIS) is "0". 
Accordingly, "1" is retained in the X increment register 3X and 
(.DELTA.y/.DELTA.x) is retained in the Y increment register 3Y. Numerals 
4X and 4Y denote an X coordinate register and a Y coordinate register, 
which comprise integer registers 5X and 5Y and fraction registers 6X and 
6Y, respectively. Numerals 7X and 7Y denote adders which add the contents 
of the X coordinate register 4X and the Y coordinate register 4Y to the 
increments retained in the X increment register 3X and the Y increment 
register 3Y, respectively. The sums are supplied to the X coordinate 
register 4X and the Y coordinate register 4Y, which retain them in place 
of the previous contents. 
In determining the coordinate (x.sub.1, y.sub.1) of the line (L) in FIG. 1, 
the X coordinate (x.sub.0) of the start point coordinate (x.sub.0, 
y.sub.0) is retained in the X coordinate register 4X, and the Y coordinate 
(y.sub.0) is retained in the Y coordinate register 4Y. The X coordinate 
(x.sub.0) in the X coordinate register 4X and "1" retained in the X 
increment register 3X are summed in the adder 7X and the sum (x.sub.0 +1) 
is retained in the X coordinate register 4X in place of (x.sub.0). 
Similarly, the Y coordinate (y.sub.0) retained in the Y coordinate 
register 4Y and (.DELTA.y/.DELTA.x) retained in the Y increment register 
3Y are summed by the adder 7Y and the sum (y.sub.0 +.DELTA.y/.DELTA.x) is 
retained in the Y coordinate register 4Y in place of (y.sub.0). 
Numeral 8 denotes a multiplexer to which the fractions retained in the 
fraction registers 6X and 6Y of the X coordinate register 4X and the Y 
coordinate register 4Y are applied. One of them is selected depending on 
the output (AXIS) of the comparator 1 and it is supplied to a comparator 
9. When the (AXIS) is "0", the fraction retained in the fraction register 
6Y of the Y coordinate register 4Y is selected and supplied to the 
comparator 9. When the (AXIS) is "1", the fraction retained in the 
fraction register 6X of the X coordinate register 4X is selected and 
supplied to the comparator 9. For the line (L) shown in FIG. 1, the (AXIS) 
is "0" and the fraction retained in the fraction register 6Y of the Y 
coordinate register 4Y is selected and supplied to the comparator 9. The 
comparator 9 determines whether the input fraction is no smaller than 0.5 
or smaller than 0.5. If it is no smaller than 0.5, an output (M) of the 
comparator 9 is "1", and if it is smaller than 0.5, M is "0". 
Numerals 10X and 10Y denote output terminals which supply the numbers 
retained in the integer registers 5X and 5Y of the X and Y coordinate 
registers 4X and 4Y, respectively. Numeral 11 denotes an adder which adds 
"1" to an output (OUT.sub.Y) at the output terminal 10Y, and numeral 12 
denotes a multiplexer which selects the output of the adder 11 or passes 
the output (OUT.sub.Y) of the output terminal 10Y. Numeral 13 denotes a 
control circuit which controls the multiplexer 12 depending on the output 
(AXIS) of the comparator 1 and the output (M) of the comparator 9. The 
multiplexer 12 is controlled by the combination of (AXIS) and (M) in the 
following manner. 
(1) When M="0" and AXIS="0": 
The output (OUT.sub.Y) of the output terminal 10 is selected and outputted 
as it is. 
(2) When M="1" and AXIS="0": 
The output (OUT.sub.Y) of the output terminal 10Y is selected and it is 
outputted as it is, and then the output of the adder 11 is selected to 
output a sum of (OUT.sub.Y) and "1". 
(3) When M="0" and AXIS is "1": 
The output (OUT.sub.Y) of the output terminal 10 is selected and it is 
outputted as it is. 
(4) When M="1" and AXIS is "1": 
The output (OUT.sub.Y) of the output terminal 10Y is selected and it is 
outputted as it is. 
The output of the multiplexer 12 is used as a Y address signal of a frame 
memory 14 and the output (OUT.sub.X) of the output terminal 10X is used as 
an X address signal of the frame memory 14. 
Numeral 15 denotes an illumination control data generator which produces 
the illumination control data "0", "1", "2" or "3" based on the output 
(AXIS) of the comparator 1 and the output M of the comparator 9. When 
M="0" and (AXIS) is "0", the illumination control data "0" is produced, 
and when M="1" and (AXIS)="0", the illumination control data "1" is first 
produced and then "2" is produced. When M="0" and (AXIS)="1", the 
illumination control data "0" is produced, and when M="1" and (AXIS)="1", 
the illumination control data "3" is produced. 
Numeral 16 denotes register for retaining a color data supplied from the 
processor. 
The DDA 2 determines the coordinates (x.sub.1, y.sub.1), (x.sub.2, y.sub.2) 
. . . (x.sub.l, y.sub.l) . . . (x.sub.n, y.sub.n) of the points forming 
the line (L) and generate corresponding X and Y address signals, and 
stores the color data and the illumination control data at the addresses 
of a first memory 17 and a second memory 18 of the frame memory 14 
designated by the X and Y address signals. 
FIG. 3 shows the relation between the X and Y address signals generated 
when X.sub.l and Y.sub.l are produced at the output terminals OUT.sub.X 
and OUT.sub.Y of the DDA 2, and M and (AXIS). 
When X.sub.l and Y.sub.l are produced at the output terminals OUT.sub.X and 
OUT.sub.Y of the DDA 2 and when M="0" and "AXIS" is "0", the X address 
signal is X.sub.l, the Y address signal is Y.sub.l and the illumination 
control data is "0". As a result, the color data is stored at the address 
of the first memory 17 of the frame memory 14 designated by X.sub.l and 
Y.sub.l, and the illumination control data "0" is stored at the address of 
the second memory 18 of the frame memory 14 designated by X.sub.l and 
Y.sub.l. 
The operation when the outputs of the DDA 2 are X.sub.l and Y.sub.l, and 
M="1" and (AXIS)="0" will now be explained. The address signals X.sub.l 
and Y.sub.l, and the color data and the illumination control data "1" are 
produced, and the color data is stored at the address of the first memory 
17 designated by X.sub.l and Y.sub.l and the illumination control data "1" 
is stored at the address of the second memory 18 designated by X.sub.l and 
Y.sub.l. Then, the address signals X.sub.l and (Y.sub.l +1), and the color 
data and the illumination control data "2" are produced, and the color 
data is stored at the address of the first memory 17 designated by X.sub.l 
and (y.sub.l +1) and the illumination control data "2" is stored at the 
address of the second memory 18 designated by X.sub.l and (y.sub.l +1). 
When M="0" and (AXIS)="1", the address signals X.sub.l and Y.sub.l, and the 
color data and the intensity control data "0" are produced, and the color 
data is stored at the address of the first memory 17 designated by X.sub.l 
and Y.sub.l and the illumination control data "0" is stored at the address 
of the second memory 18 designated by X.sub.l and Y.sub.l. 
When M="1" and (AXIS)="1", the address signals X.sub.l and Y.sub.l, and the 
color data and the illumination control data "3" are produced, and the 
color data is stored at the address of the first memory 17 designated by 
X.sub.l and Y.sub.l and the illumination control data "3" is stored at the 
address of the second memory 18 designated by X.sub.l and Y.sub.l. 
In this manner, the addresses of the frame memory 14 are determined for the 
respective points forming the line (L), and the color data and the 
intensity control data are stored at those addresses. 
A construction for reading out the color data and the illumination control 
data stored in the frame memory 14 and displaying them on the CRT is 
explained. 
In FIG. 2, numeral 19 denotes an address signal generator which generates 
an address signal in synchronism with a raster scan of the CRT 23. Numeral 
20 denotes an illumination control circuit which controls a gate circuit 
21 and a shift circuit 22 based on the illumination control data read from 
the second memory 18 of the frame memory 14. Numeral 23 denotes the 
interlace type CRT on which a first field shown by broken lines in FIG. 4 
and a second field shown by solid lines are formed. The CRT 23 has a 
display screen which has a plurality of vertically and horizontally 
arranged picture cells (pixels). The gate circuit 21 is opened and closed 
by the illumination control data supplied from the illumination control 
circuit 20 to gate or block the color data read from the first memory 17 
of the frame memory 14 to the shift circuit 22. When the illumination 
control data of the second memory 18 at the address designated by the 
address signals X.sub.l and Y.sub.l generated by the address signal 
generator 19 is "0", the gate circuit 21 is opened at timings of the first 
field and the second field of the picture cells of the CRT 23 
corresponding to the address signals X.sub.l and Y.sub.l to transmit the 
color data. When the illumination control data is "1", the gate circuit 21 
is opened to transmit the color data at the timing of the first field, and 
the gate circuit 21 is closed to block the color data at the timing of the 
second field. When the illumination control data is "2", the gate circuit 
21 is closed to block the color data at the timing of the first field and 
the gate circuit 21 is opened to transmit the color data at the timing of 
the second field. When the illumination control data is "3", the gate 
circuit 21 is opened to transmit the color data in both the first field 
and the second field. 
The shift circuit 22 shifts the color data in the X direction by 1/2 pixel 
position only when the illumination control data is "3". The color data 
may be shifted by 1/2 pixel position by delaying a clock to be supplied to 
a register of the shift circuit 22 through a delay circuit. 
FIGS. 5A-5D illustrate the illumination of one pixel (X.sub.l, Y.sub.l) on 
the CRT 23. In FIG. 5A, the illumination control data is "0", and the 
illumination occurs in both the first field and the second field. In FIG. 
5B, the illumination control data is "1" and the illumination occurs only 
in the first field. In FIG. 5C, the illumination control signal is "2" and 
the illumination occurs only in the second field. In FIG. 5D, the 
illumination control signal is "3" and the illumination occurs in both the 
first field and the second field with 1/2 pixel position shifted by the 
shift circuit 22. 
The operation for displaying a line (L.sub.1) shown in FIG. 6A on the CRT 
23 will now be explained. The line (L.sub.1) has a start point coordinate 
(x.sub.0, y.sub.0)=(1, 1), an X component .DELTA.x=8, a Y component 
.DELTA.y=2, a gradient (2/8) and an end point coordinate (x.sub.8, 
y.sub.8)=(9, 3). Since .DELTA.x (=8)&gt;.DELTA.y (=2), (AXIS)="0" and "1" is 
held in the X increment register 3X and ".DELTA.y/.DELTA.x=2/8=0.25" is 
held in the Y increment register 3Y. Thus, the X coordinates of the points 
(x.sub.1, y.sub.1) (x.sub.2, y.sub.2), . . . (x.sub.8, y.sub.8) are 
obtained by sequentially incrementing the start point coordinate "1" by 
one, and the Y coordinates are obtained by sequentially adding "0.25" to 
the start point coordinate "1". (See FIG. 6B) The (OUT.sub.X) and the 
(OUT.sub.Y) of each point are integer portions of the X and Y coordinates 
as shown in FIG. 6B. The fraction portion of the Y coordinate at each 
point is compared with "0.5" by the comparator 9, and if it is no smaller 
than 0.5, the output M="1" is produced, and if it is smaller than 0.5, the 
output M="0" is produced. In FIG. 6B, the fraction portions of the Y 
coordinates of the points (x.sub.0, y.sub.0), (x.sub.1, y.sub.1), 
(x.sub.4, y.sub.4), (x.sub.5, y.sub.5) and (x.sub.8, y.sub.8) are smaller 
than "0.5" and the output M="0" is produced for those points. On the other 
hand, the fraction portions of the Y coordinates of the points (x.sub.2, 
y.sub.2), (x.sub.3, y.sub.3), (x.sub.6, y.sub.6) and (x.sub.7, y.sub.7) 
are larger than "0.5" and the output M=1 is produced for those points. The 
X addresses supplied to the frame memory 14 are 1, 2, 3, 4, 5, 6, 7, 8 and 
9 as shown in FIG. 6B while the Y addresses are determined by the 
combination of M and AXIS). For example, the Y address at the point 
(x.sub.0, y.sub.0) is "1" because M="0" and (AXIS)="0" (see FIG. 3), the Y 
address at the point (x.sub.1, y.sub.1) is "1" because M="0" and 
(AXIS)="0", and the Y address at the point (x.sub.2, y.sub.2) is first "1" 
and then "2" because M="1" and (AXIS)="0" (see FIG. 3). The illumination 
control data at the respective points are also determined by the 
combination of M and (AXIS). For example, at the point (x.sub.0, y.sub.0), 
M="0" and (AXIS)="0" and the illumination control data is "0" (see FIG. 
3), and at the point (x.sub.2, Y.sub.2), M="1" and (AXIS)="0" and the 
intensity control data is first "1" and then "2". FIG. 6C shows the 
illumination control data stored in the second memory 18 of the frame 
memory 14. 
FIG. 7A shows the illumination status of the pixels on the screen of the 
CRT 23 in the first field. The illumination control data shown in FIG. 6C 
are sequentially read out in synchronism with the raster scan and the 
color data is controlled by the gate circuit 21 in accordance with the 
illumination control data so that the illumination status shown in FIG. 7A 
is attained in the first field. FIG. 7B shows an illumination status in 
the second field, and FIG. 7C shows the illumination status in the first 
and second fields (FIG. 7C is a superposition of FIG. 7A and FIG. 7B.) 
An operation to display a line (L.sub.2) shown in FIG. 8A on the CRT 23 
will now be explained. The line (L.sub.2) has a start point coordinate 
(x.sub.0, y.sub.0) =(1, 1), an X component .DELTA.x=2, a Y component 
.DELTA.Y=8 and a gradient .DELTA.x/.DELTA.y=2/8 =0.25. Since 
.DELTA.y&gt;.DELTA.x, (AXIS)="1". Thus, as shown in FIG. 8B, the Y addresses 
are obtained by sequentially adding "1" to the start point coordinate "1" 
while the X addresses and the illumination control data are determined by 
the combination of M and (AXIS). FIG. 8C shows the illumination control 
data stored in the second memory 18 of the frame memory 14. FIG. 9 shows 
the illumination status in the first field and the second field obtained 
when the illumination control data stored in the frame memory 14 as shown 
in FIG. 8C are sequentially read out and the gate circuit 21 and the shift 
circuit 22 are controlled in accordance with the illumination control 
data. 
A second embodiment of the present invention will now be explained. FIG. 10 
shows the circuit configuration of the second embodiment. Numerals 24X and 
24Y denote integer circuits which count as one the fractions of more than 
0.5 and cut away the rest for the number supplied from the X coordinate 
register 4X and the Y coordinate register 4Y, respectively, and numeral 25 
denotes a subtractor which subtracts "1" from the output (OUT.sub.Y) of 
the output terminal 10Y. 
FIG. 11 shows M (AXIS), X address, Y address and illumination control data 
when (OUT.sub.X) is X.sub.l and (OUT.sub.Y) is Y.sub.l. When M="0" and 
(AXIS)="0", and when M ="0" and (AXIS)="1", the illumination control data 
"0" is stored at the address of the second memory 18 of the frame memory 
14 designated by X.sub.l and Y.sub.l. When M="1" and (AXIS)="0", the 
illumination control data "1" is first stored at the address of the second 
memory 18 designated by X.sub.l and Y.sub.l, and then the illumination 
control data "2" is stored at the address designated by X.sub.l and 
(Y.sub.l -1). When M="1" and (AXIS)="1", the illumination control data "3" 
is stored at the address of the second memory 18 designated by X.sub.l and 
Y.sub.l. 
FIG. 12 shows the X and Y coordinates, the rounded X and Y coordinates (the 
outputs of the integer circuits 24X and 24Y of FIG. 10), the X address, 
the Y address and the illumination control data when the line (L.sub.1) 
shown in FIG. 6 is to be displayed in the second embodiment, and FIG. 13 
shows the illumination control data stored in the second memory 18 of the 
frame memory 14. 
FIGS. 14A-14D illustrate the illumination status of one pixel on the CRT 23 
when the illumination control data is read from the second memory 18, and 
the gate circuit 21 and the shift circuit 22 are controlled by the 
illumination control circuit 20 in accordance with the second embodiment. 
The illumination control method shown in FIG. 14A-14D is different from 
that shown in FIG. 5A-5D. The illumination status of the pixels on the CRT 
23 in the second embodiment are similar to those shown in FIGS. 7A-7C. 
FIG. 15 shows the X and Y coordinates, the rounded X and Y coordinates, M, 
(AXIS), the X address, the Y address and the illumination control data 
when the line (L.sub.2) shown in FIG. 8A is to be displayed on the CRT 23 
in the second embodiment, FIG. 16 shows the illumination control data 
stored in the second memory 18 of the frame memory 14, and FIG. 17 shows 
the illumination status on the CRT 23 obtained when the illumination 
control data is read from the second memory 18 shown in FIG. 16 and the 
gate circuit and the shift circuit 22 are controlled by the illumination 
control circuit 20. The illumination status of the CRT 23 shown in FIG. 17 
is identical to that in the first embodiment (FIG. 9). 
FIGS. 18 and 19 show examples of display on the CRT of the prior art 
luminance modulation type graphic display apparatus. Black block areas in 
FIGS. 18 and 19 represent the luminance of each pixel. In FIG. 18, the 
line (L.sub.1) shown in FIG. 6A is displayed on the CRT, and in FIG. 19, 
the line (L.sub.2) shown in FIG. 8A is displayed on the CRT. 
In the above embodiment, the illumination of the pixel is controlled in the 
first field and the second field and the illumination position of the 
pixel is shifted in the X direction so that the line is displayed smoothly 
and non-stepwise. In the above embodiment, since one point is illuminated 
in paired relation with the first field and the second field of the same 
pixel or the first field and the second field of the adjacent pixels, the 
flicker which is likely to occur in the interlace type CRT is prevented. 
The above embodiment can be attained by the same scale of hardware as the 
prior art luminance modulation type display apparatus. 
An embodiment which displays a smooth and non-stepwise color line on a 
color CRT will now be explained. FIG. 20 shows a line (L) to be displayed 
on an interlace type color CRT. The line (L) has a start point coordinate 
(x.sub.0, y.sub.0), an end point coordinates (x.sub.0 +.DELTA.x, y.sub.0 
+.DELTA.y) and a gradient (.DELTA.y/.DELTA.x). If .DELTA.x is negative, 
the start point coordinate (x.sub.0, y.sub.0) and the end point coordinate 
(x.sub.0 +.DELTA.x, y.sub.0 +.DELTA.y) are exchanged so that .DELTA.x is 
always positive for a line having any gradient. Accordingly, .DELTA.x has 
0 or a positive value in the present embodiment. 
The start point coordinate (x.sub.0, y.sub.0), the X component (.DELTA.x), 
the Y component (.DELTA.y), the gradient (.DELTA.y/.DELTA.x) or 
(.DELTA.x/.DELTA.y) and the color data for the line (L) shown in FIG. 20 
are supplied from a processor. 
FIG. 21 shows a graphic display control apparatus in accordance with the 
present embodiment. Numeral 101 denotes a comparator which compares the X 
component (.DELTA.x) and the Y component (.DELTA.y) of the line (L), and 
if .DELTA.y.ltoreq..DELTA.x, produces an output "0", and if 
.DELTA.y&gt;.DELTA.x, produces an output "1". When the output (AXIS) of the 
comparator 101 is "0", it means that the X axis is the main axis when a 
DDA (digital differential analyzer) is operated, and when (AXIS) is "1", 
it means that the Y axis is the main axis. 
Numeral 102 denotes a comparator which produces an output "0" when the 
input .DELTA.y is 0 or positive, and produces an output "1" when .DELTA.y 
is negative. When the output (SIGN) of the comparator 102 is "0", it means 
that the Y axis changes in a positive direction when the DDA is operated, 
and when the (SIGN) is "1", it means that the Y axis changes in a negative 
direction. 
Numerals 103 denotes the DDA which sequentially calculates the coordinates 
(x.sub.1, y.sub.1), (x.sub.2, y.sub.2) . . . (x.sub.n, y.sub.n) of the 
points forming the line (L) based on the start point coordinate (x.sub.0, 
y.sub.0), the X component (.DELTA.x), the Y component (.DELTA.y) and the 
gradient (.DELTA.y/.DELTA.x) or (.DELTA.x/.DELTA.y) of the line (L) 
supplied from the processor. 
The construction of the DDA 103 will now be explained in detail. In FIG. 
21, numerals 104X and 104Y denote an X increment register and a Y 
increment register. When the (AXIS) is "0", "1" is retained in the X 
increment register 104X and (.DELTA.y/.DELTA.x) is retained in the Y 
increment register 104Y. When the (AXIS) is "1", (.DELTA.x/.DELTA.y) is 
retained in the X increment register 104X and "1" is retained in the Y 
increment register 104Y. For the line (L) shown in FIG. 20, 
.DELTA.y&lt;.DELTA.x and hence the (AXIS) is "0". Accordingly, "1" is 
retained in the X increment register 104X and (.DELTA.y/.DELTA.x) is 
retained in the Y increment register 104Y. Numerals 105X and 105Y denote 
an X coordinate register and a Y coordinate register, which comprises 
integer registers 106X and 106Y and fraction registers 107X and 107Y, 
respectively. Numerals 108X and 108Y denote adders which add the contents 
of the X coordinate register 105X and the Y coordinate register 105Y to 
the increments retained in the X increment register 104X and the Y 
increment register 104Y, respectively. The sums are supplied to the X 
coordinate register 105X and the Y coordinate register 105Y which retain 
the sums in place of the previous contents. 
When the coordinate (x.sub.1, y.sub.1) of the line (L) of FIG. 20 is to be 
determined, the X coordinate (x.sub.0) of the start point coordinate 
(x.sub.0, y.sub.0) is held in the X coordinate register 105X, and the Y 
coordinate (y.sub.0) is held in the Y coordinate register 105Y. The X 
coordinate (x.sub.0) held in the X coordinate register 105X and "1" held 
in the X increment register 104X are summed by the adder 108X, and the sum 
(x.sub.0 +1) is held in the X coordinate register 105X in place of 
x.sub.0. The Y coordinate (y.sub.0) held in the Y coordinate register 105Y 
and (.DELTA.y/.DELTA.x) held in the Y increment register 104Y are summed 
by the adder 108Y and the sum (y.sub.0 +.DELTA.y/.DELTA.x) is held in the 
Y coordinate register 105Y in plce of y.sub.0. 
Numeral 109 denotes a multiplexer to which the fraction portions held in 
the fraction registers 107X and 107Y of the X coordinate register 105X and 
the Y coordinate register 105Y are supplied. One of them is selected 
depending on the output (AXIS) of the comparator 101 and supplied to a 
comparator 110. When the (AXIS) is "0", the fraction held in the fraction 
register 107Y of the Y coordinate register 105Y is selected and supplied 
to the comparator 110. When the (AXIS) is "1", the fraction held in the 
fraction register 107X of the X coordinate register 105X is selected and 
supplied to the comparator 110. For the line (L) shown in FIG. 20, the 
(AXIS) is "0" and hence the fraction held in the fraction register 107Y of 
the Y coordinate register 105Y is selected and supplied to the comparator 
110. The comparator 110 determines whether the input fraction is no 
smaller than 0.5 or smaller than 0.5. If it is no smaller than 0.5, the 
output M of the comparator 110 is "1", and if it is smaller than 0.5, the 
output M is "0". 
Numerals 111X and 111Y denote output terminals which produce the numbers 
held in the integer registers 106X and 106Y of the X and Y coordinate 
registers 105X and 105Y. Numeral 112 denotes an adder which adds one to 
the output (OUT.sub.Y) of the output terminal 111Y, and numeral 113 denote 
a multiplexer. The output of the adder 112 is selected or the output 
(OUT.sub.Y) of the output terminal 111Y is passed by the multiplexer 113. 
Numeral 114 denotes a gate circuit which produces an output (SEP) based on 
the (AXIS) and M. When the (AXIS) is "0" and M is "1", the output (SEP) is 
"1", and the output (SEP) is "0" in all other cases. 
Numeral 115 denotes a control circuit which controls the multiplexer 113 in 
accordance with the output (SEP) of the gate circuit 114, in the following 
manner. 
(1) when SEP="0": 
The output (OUT.sub.Y) at the output terminal 111Y is selected and it is 
outputted as it is. 
(2) when (SEP)="1": 
The output (OUT.sub.Y) at the output terminal 111Y is first selected and 
outputted as it is, and then the output of the adder 112 is selected to 
produce a sum of the (OUT.sub.Y) and "1". 
The output of the multiplexer 113 is used as a Y address signal for the 
frame memory 116, and the output (OUT.sub.X) of the output terminal 111X 
is used as an X address signal for the frame memory 116. 
Numeral 117 denotes a flip-flop which is reset and produces an output (F) 
"0" when the output (SEP) of the gate circuit 114 is "0", and when the 
output (SEP) is "1", the flip-flop 117 is flipped at the end of a sequence 
of processing in the DDA 103. Thus, the output F of the flip-flop 117 
alternately changes between "0" and "1" for each end of the series of 
processing by the DDA 103. 
Numeral 118 denotes a gate circuit which exclusively OR's the output F of 
the flip-flop 117 and the output (SIGN) of the comparator 102 to produce 
an output G. When F="0" and (SIGN)="0", G="0", when F="0" and (SIGN)=1, 
G="1", when F="1" and (SIGN)="0", G="1", and when F="1" and (SIGN)=1, 
G="0". 
Numeral 119 denotes a control data generator which produces the 
illumination control data "0", "1", "2" or "3" and the color control data 
"0" or "1" based on the output (AXIS) of the comparator 101, the output M 
of the comparator 110 and the output G of the gate circuit 118. The 
control data generator 119 operates in the following manner. 
(1) When AXIS="0" and M="0": 
The illumination control data is "0" and the color control data is "1". 
(2) When AXIS="0", M="1" and G="0": 
The illumination control data is "3" and the color control data is "0", and 
then the illumination control data is "3" and the color control data is 
"1". 
(3) When AXIS="0", M="1" and G="1": 
The illumination control data is "2" and the color control data is "1", and 
then the illumination control data is "2" and the color control data is 
"0". 
(4) When AXIS="1" and M="0": 
The illumination control data is "0" and the color control data is "1". 
(5) When AXIS="1" and M="1": 
The illumination control data is "1" and the color control data is "1". 
Numeral 120 denotes a register which retains the color data supplied from 
the processor. Numeral 121 denotes a control circuit which permits or 
inhibits the writing of the color data into the frame memory 116 by the 
color control data supplied from the control data generator 119. When the 
color control data is "1", it permits the writing, and when the color 
control data is "0", it inhibits the writing. 
The DDA 103 calculates the coordinates (x.sub.1, y.sub.1), (x.sub.2, 
y.sub.2), . . . (x.sub.l, y.sub.l), . . . (x.sub.n, y.sub.n) of the points 
forming the line (L), generates the X and Y address signals corresponding 
to the coordinates and stores the color data and the illumination control 
data at the addresses of the first memory 116A and the second memory 116B 
of the frame memory 116 designated by the X and Y addresses. 
FIG. 22 shows the X and Y address signals, the illumination control data, 
the color control data and the outputs M, AXIS and G, which are generated 
when X.sub.l and Y.sub.l are produced at the output terminals OUT.sub.X 
and OUT.sub.Y of the DDA 103. 
When X.sub.l and Y.sub.l are produced at the output terminals OUT.sub.X and 
OUT.sub.Y of the DDA 103, M="0", (AXIS)="0", the X address signal is 
X.sub.l, the Y address signal is Y.sub.l, the illumination control data is 
"0" and the color control data is "1". As a result, the color data 
(identified as "C.D." in FIG. 22) is stored at the address of the first 
memory 116A of the frame memory 116 designated by X.sub.l and Y.sub.l, and 
the illumination control data "0" is stored at the address of the second 
memory 116B of the frame memory 116 designated by X.sub.l and Y.sub.l. 
The operation when the outputs of the DDA 103 are X.sub.l and Y.sub.l, 
M="1" and (AXIS) is "0" will now be explained. The operation differs 
depending on the status of the flip-flop 117. When G="0", the address 
signals X.sub.l and Y.sub.l, the illumination control data "3" and the 
color control data "0" are produced, and the illumination control data "3" 
is stored at the address of the second memory 116B designated by X.sub.l 
and Y.sub.l. (The writing of the color data into the first memory 116A is 
inhibited.) 
Next, the address signals X.sub.l and (Y.sub.l +1), the illumination 
control data "3" and the color control data "1" are produced, and the 
color data is stored at the address of the first memory 116A designated by 
X.sub.l and (Y.sub.l +1), and the illumination control data "3" is stored 
at the address of the second memory 116B designated by X.sub.l and 
(Y.sub.l +1). When G="1", the address signals X.sub.l and Y.sub.l, the 
illumination control data "2" and the color control data "1" are first 
produced, and the color data is stored at the address of the first memory 
116A designated by X.sub.l and Y.sub.l, and the illumination control data 
"2" is stored at the address of the second memory 116B designated by 
X.sub.l and Y.sub.l. Then, the address signals X.sub.l and (Y.sub.l +1), 
the illumination control data " 2" and the color control data "0" are 
produced, and the illumination control data "2" is stored at the address 
of the second memory 116B designated by X.sub.l and (Y.sub.l +1). (The 
writing of the color data into the first memory 116A is inhibited.) 
When M="0" and (AXIS)="1", the address signals X.sub.l and Y.sub.l, the 
color data, the illumination control data "0" and the color control data 
"1" are produced, and the color data is stored at the address of the first 
memory 116A designated by X.sub.l and Y.sub.l, and the illumination 
control data "0" is stored at the address of the second memory 116B 
designated by X.sub.l and Y.sub.l. 
When M="1" and (AXIS)="1", the address signals X.sub.l and Y.sub.l, the 
color data, the illumination control data "1" and the color control data 
"1" are produced, and the color data is stored at the address of the first 
memory 116A designated by X.sub.l and Y.sub.l, and the illumination 
control data "1" is stored at the address of the second memory designated 
by X.sub.l and Y.sub.l. 
In this manner, the addresses of the frame memory 116 are determined for 
the respective points forming the line (L), and the color data and the 
illumination control data are stored at those addresses. 
A construction for reading out the color data and the illumination control 
data stored in the frame memory 116 and displaying them on the CRT will 
now be explained. 
In FIG. 21, numeral 122 denotes an address signal generator which generates 
an address signal in synchronism with the raster scan of a CRT 123. 
Numeral 124 denotes an illumination control circuit which controls a 
multiplexer 125 and a shift circuit 126 based on the illumination control 
data read from the second memory 116B of the frame memory 116. Numeral 123 
denotes the interlace type CRT which forms one image by a first field 
shown by broken lines in FIG. 4 and a second field shown by solid lines. 
Numeral 127 denotes a register which holds a color data for each pixel 
read from the first memory 116A of the frame memory 116 and provides a 
color data which is one pixel previous to the color data read from the 
first memory 116A, to the multiplexer 125. 
The multiplexer 125 is operated by the illumination control data supplied 
from the illumination control circuit 124 to select the color data read 
from the first memory 116A of the frame memory 116 or the one-pixel 
previous color data held in the register 127 and supply it to the shift 
circuit 126. When the illumination control data read from the second 
memory at the address designated by the address signals X.sub.l and 
Y.sub.l generated by the address signal generator 123 is "0", the current 
color data read from the first memory 116A is selected at timings of the 
first field and the second field of the CRT 123 corresponding to the 
address signals X.sub.l and Y.sub.l. When the illumination control signal 
is "1", the current color data read from the first memory 116A is selected 
in both the first field and the second field. When the illumination 
control data is "2", the current color data read from the first memory 
116A is selected at the timing of the first field, and the one-pixel 
previous color data held in the register 127 is selected at the timing of 
the second field. When the illumination control data is "3", the one-pixel 
previous color data is selected at the timing of the first field and the 
current color data is selected at the timing of the second field. 
The shift circuit 126 shifts the color data by 1/2 pixel position in the X 
direction only when the illumination control data is "1". The color data 
may be shifted by 1/2 pixel position by delaying a clock supplied to a 
register in the shift circuit 126, by a delay circuit. 
FIGS. 23A-23D show illumination status of one pixel (at X.sub.l, Y.sub.l) 
on the CRT 123. FIG. 23A shows the illumination status when the 
illumination control data is "0". The current color data read from the 
first memory 116A is displayed in both the first field and the second 
field. When the illumination data is "1" (FIG. 23B), the current color 
data is displayed on both the first field and the second field with 1/2 
pixel position shifted by the shift circuit 125. When the illumination 
control data is "2" (FIG. 23C), the curent color data is displayed in the 
first field and the one-pixel previous color data is displayed in the 
second field. When the illumination control data is "3" (FIG. 23D), the 
current color data is displayed in the second field and the one-pixel 
previous color data is displayed in the first field. 
The operation for displaying the line (L.sub.1) shown in FIG. 24A on the 
CRT 123 will now be explained. The line (L.sub.1) has a start point 
coordinate (x.sub.0, y.sub.0)=(1, 1), an X component .DELTA.x=8, a Y 
component .DELTA.y=2, a gradient 2/8 and an end point coordinate (x.sub.8, 
y.sub.8)=(9, 3). Since .DELTA.x (=8)&gt;.DELTA.y (=2), the (AXIS) is "0" and 
hence "1" is held in the X increment register 4X and 
".DELTA.y/.DELTA.x=2/8=0.25" is held in the Y increment register 4Y. 
Accordingly, the X coordinates of the points (x.sub.1, y.sub.1), (x.sub.2, 
y.sub.2), . . . (x.sub.8, y.sub.8) are obtained by sequentially adding "1" 
to the start point coordinate "1", and the Y coordinates are obtained by 
sequentially adding "0.25" to the start point coordinate "1". (See FIG. 
24B.) The (OUT.sub.X) and (OUT.sub.Y) of the respective points are integer 
portions of the X and Y coordinates as shown in FIG. 24B. The fraction 
portions of the Y coordinates of the respective points are compared with 
"0.5" in the comparator 110, and if it is no smaller than "0.5", the 
output M is "1" , and if it is smaller than 0.5, the output M is "0". In 
FIG. 24B, the fraction portions of the Y coordinates of the points 
(x.sub.0, y.sub.0), (x.sub.1, y.sub.1), (x.sub.4, y.sub.4), (x.sub.5, 
y.sub.5) and (x.sub.8, y.sub.8) are smaller than "0.5" and the output M is 
"0" for those points. The fraction points of the Y coordinates of the 
points (x.sub.2, y.sub.2), (x.sub.3, y.sub.3), (x.sub.6, y.sub.6) and 
(x.sub.7, y.sub.7) are larger than " 0.5" and the output M is "1" for 
those points. The X address supplied to the frame memory 116 sequentially 
assumes 1, 2, 3, 4, 5, 6, 7, 8 and 9 as shown in FIG. 24B while the Y 
address is determined by the combination of M and (AXIS). For example, in 
FIG. 24B, the Y address for the point (x.sub.0, y.sub.0) is "1" because 
M="0" and (AXIS)="0" (see FIG. 22), the Y address for the point (x.sub.1, 
y.sub.1) is "1" because M="0" and (AXIS)=0, and the Y address for the 
point (x.sub.2, y.sub.2 ) is first "1" and then "2" because M="1" and 
(AXIS)="0" (see FIG. 22). 
Since the line (L.sub.1) of FIG. 24A has a positive gradient, the (SIGN) is 
"0", and the G, the illumination control data and the color control data 
at each point are determined by the combination of M and (AXIS). For 
example, for the point (x.sub.0, y.sub.0), M="0", (AXIS)="0", (SEP)="0", 
F="0" and G="0", and hence the illumination control data is "0" and the 
color data is "1" (writing permitted) (see FIG. 22). For the points 
(x.sub.2, y.sub.2), M="1", (AXIS)="0", (SEP)="0", F="0" and G="0" and 
hence the illumination control data is "3" and the color data is "0" 
(writing inhibited). For the point (x.sub.3, y.sub.3), M="1", (AXIS)="0", 
(SEP)="0", F="1" at the end of DDA and G="1", and hence the illumination 
control data is "3" and the color data is "1" (writing permitted). 
FIGS. 24C and 24D show the color data and the illumination control data 
stored in the first memory 116A and the second memory 116B of the frame 
memory 116. For the pixels for which no color is written, the color data 
before writing of the line (L) remain unchanged. (In the present example, 
the background color is blue (B) and the line (L) is displayed in red 
(R)). 
FIG. 25A shows the illumination status of the pixels on the screen of the 
CRT 123 in the first field. The illumination control data and the color 
data shown in FIGS. 24C and 24D are sequentially read out in synchronism 
with the raster scan and the color data is selected by the multiplexer 125 
in accordance with the illumination control data so that the illumination 
status shown in FIG. 25A is obtained in the first field. FIG. 25B shows 
the illumination status in the second field and FIG. 25C shows the 
illumination status in the first field and the second field. (FIG. 25C is 
a superposition of FIGS. 25A and 25B). Hatched areas in FIG. 25 show blue 
illumination as the backgound color, thick framed areas show red 
illumination and arrows show illumination by the one-pixel previous color 
data held in the register 127. 
The operation for displaying the line (L.sub.2) shown in FIG. 26A on the 
CRT 123 will now be explained. The line (L.sub.2) has a start point 
coordinate (x.sub.0, y.sub.0)=(1, 1), an X component .DELTA.x=2, a Y 
component .DELTA.y=8 and a gradient (.DELTA.x/.DELTA.y=2/8=0.25). Since 
.DELTA.y&gt;.DELTA.x, the (AXIS) is "1". Thus, the Y addresses are obtained 
by sequentially adding "1" to the start point coordinate "1" while the X 
addresses and the illumination control data are determined by the 
combination of M and (AXIS). The G does not affect the writing of the 
illumination control data and the color data, and the writing of the color 
data is always permitted. 
FIGS. 26C and 26D show the color data and the illumination control data 
stored in the first memory 116A and the second memory 116B of the frame 
memory 116. 
FIG. 27 shows the illumination status in the first field and the second 
field obtained when the illumination control data and the color data 
stored in the frame memory 116 as shown in FIGS. 26C and 26D are 
sequentially read and the multiplexer 125 and the shift circuit 126 are 
controlled by the illumination control data. 
In the above embodiment, since the illumination and the coloring of the 
pixels are controlled in the first field and the second field, and the 
illumination positions of the pixels are shifted in the X direction, the 
line is displayed non-stepwise and smoothly. In the above embodiment, 
since each point is illuminated with the first field and the second field 
of the same pixel being paired or with the first field and the second 
field of the adjacent pixels being paired, the flickering which is likely 
to occur in an interlace type CRT is prevented. When the line is displayed 
on a colored background, the above performance is also attained.