Closed loop CPU performance control

The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves scaling the voltage/frequency of the processor based on the number of frames per second being input to a frame buffer in order to reduce or eliminate choppiness in animations shown on a display of the computing device. Another embodiment of the invention involves scaling the voltage/frequency of the processor based on a utilization rate of the GPU in order to reduce or eliminate any bottleneck caused by slow issuance of instructions from the CPU to the GPU. Yet another embodiment of the invention involves scaling the voltage/frequency of the CPU based on specific types of instructions being executed by the CPU. Further embodiments include scaling the voltage and/or frequency of a CPU when the CPU executes workloads that have characteristics of traditional desktop/laptop computer applications.

TECHNICAL FIELD

The present invention relates generally to power management in a mobile computing device. More particularly, the present invention relates to power management techniques that correlate to central processor unit (CPU) activity, memory controller (MC) activity, graphics processing unit (GPU) activity, and user interface (UI) frame rate activity within the mobile computing device.

BACKGROUND

Conventional computing devices (e.g., desktop computers and laptop computers) typically implement one or more algorithms directed to controlling the operating clock frequency and voltage of processors included therein, such as a CPU and a GPU. These algorithms are directed to monitoring the CPU/GPU for workloads that take more than a threshold amount of time to complete. Consider, for example, a time-intensive image processing workload that takes several minutes for a CPU/GPU to execute when the CPU/GPU are in a low-performance operating mode. In this example, the algorithms detect that the workload meets certain criteria (e.g., the threshold amount of time has passed or processor duty factor has exceeded a threshold) and cause the CPU/GPU to switch from a low-performance operating mode to a mid-performance or a high-performance operating mode so that the workload is completed sooner. These algorithms enable conventional computing devices to reduce power for short, bursty workloads while providing high performance for long-running compute tasks.

Notably, recent years have shown a proliferation in the usage of mobile computing devices with performance characteristics, energy constraints and interactive user interfaces that are different from those of desktop/laptop computers, which affect the types of workloads users execute on mobile devices. More specifically, unlike traditional long-running pure-compute tasks, mobile applications instead emphasize interactive performance for visual scenarios such as web browsing, gaming and photography. Consequently, the aforementioned algorithms—which are directed to identifying and responding to complex, time-intensive workloads—are not as effective when implemented in mobile devices since the algorithms cannot accurately determine when the operating mode of the CPU/GPU should be modified.

SUMMARY

This paper describes various embodiments that relate to the operation of CPU performance control algorithms within a mobile computing device. In contrast to conventional approaches, these performance control algorithms can operate based on feedback received from various components included in the mobile computing device, such as a frame buffer, a GPU and a memory controller. For example, instead of focusing solely on the amount of time a workload spends executing on the CPU, the techniques presented herein measure the smoothness of UI animations presented on a display of the mobile computing device, the utilization rates of the GPU or memory interfaces, and the types of instructions being executed by the CPU.

One embodiment of the invention sets forth a method for updating an operating mode of a processor. The method includes the steps of monitoring a cycle-to-cycle jitter associated with a rate by which a user interface (UI) is animated, and, further, adjusting an operating mode of the processor based on the cycle-to-cycle jitter. Adjusting the operating mode of the processor comprises adjusting the voltage and/or frequency at which the processor is operating. Moreover, monitoring the cycle-to-cycle jitter comprises analyzing a rate of change in a number of frames per second (NFPS) being input to a frame buffer associated with the processor. Further, monitoring the cycle-to-cycle jitter comprises establishing: a jitter control signal based on short-term sampling of the NFPS being input to the frame buffer, and a trend control signal based on long-term sampling of the NFPS being input to the frame buffer.

Another embodiment of the invention sets forth a method for optimizing operations of a CPU in a mobile computing device having the CPU configured to issue instructions to a GPU. The method includes the steps of determining that a utilization rate of the GPU is exceeding a threshold level, determining that the CPU is operating in a sub-optimal operating mode, and causing the CPU to enter into an optimal operating mode where the CPU generates instructions for execution by the GPU at a faster rate. Causing the CPU to enter into the optimal operating mode includes establishing a control signal by a control signal generator. Causing the CPU to enter into the optimal operating mode includes adjusting the voltage and/or frequency at which the CPU is operating. The method can further include the steps of determining that the utilization rate of the GPU is no longer exceeding the threshold level, and causing the CPU to return to a more energy-efficient operating mode.

A third embodiment of the invention sets forth a method for updating an operating mode of a CPU. The method includes the steps of determining that the CPU is tasked with executing instructions that are associated with a high instruction-per-cycle density, and causing the CPU to enter into a high-performance operating mode to cause an increase in the rate at which the CPU executes the instructions. The instructions can comprise integer arithmetic instructions, vector floating point (VFP) arithmetic instructions, single-instruction multiple-data (SIMD) arithmetic instructions, and load-store instructions. The method can further include the steps of establishing: an integer arithmetic control signal based on the rate at which integer arithmetic instructions are being executed by the CPU, a VFP control signal based on the rate at which VFP arithmetic instructions are being executed by the CPU, a SIMD control signal based on the rate at which SIMD arithmetic instructions are being executed by the CPU, and a load-store control signal based on the rate at which load-store instructions are being executed by the CPU.

Yet another embodiment of the invention sets forth a method for optimizing operations of a CPU in a mobile computing device having the CPU configured to perform transactions with a memory controller that manages access to a dynamic random-access memory (DRAM) and a flash memory. The method includes the steps of determining that the data throughputs of memory controller exchanges with one or more agents are exceeding threshold levels, determining that the CPU is operating in a sub-optimal operating mode, and causing the CPU to enter into an optimal operating mode where the CPU performs transactions with the memory controller at a faster rate. The agents can include the CPU itself or a flash memory subsystem.

An additional embodiment of the invention sets forth a method for updating an operating mode of a CPU while executing workloads that have characteristics of traditional desktop/laptop computer applications. The method includes the steps of determining that a utilization rate of the CPU is exceeding a threshold level, determining that the interactive user interface is updating below a threshold rate, and causing the CPU to enter into a high-performance operating mode to allow the mobile device to complete the task more quickly.

Other embodiments include a non-transitory computer readable medium storing instructions that, when executed by a processor, cause the processor to carry out any of the method steps described above. Further embodiments include a system that includes at least a processor and a memory storing instructions that, when executed by the processor, cause the processor to carry out any of the method steps described above. Yet other embodiments include a system having a management co-processor separate from the main CPU capable of, either in cooperation with or in place of the main CPU, carrying out any of the method steps described above.

In the figures, elements referred to with the same or similar reference numerals include the same or similar structure, use, or procedure, as described in the first instance of occurrence of the reference numeral.

DETAILED DESCRIPTION

Representative applications of apparatuses and methods according to the presently described embodiments are provided in this section. These examples are being provided solely to add context and aid in the understanding of the described embodiments. It will thus be apparent to one skilled in the art that the presently described embodiments can be practiced without some or all of these specific details. In other instances, well known process steps have not been described in detail in order to avoid unnecessarily obscuring the presently described embodiments. Other applications are possible, such that the following examples should not be taken as limiting.

As set forth above, embodiments of the invention are directed to scaling the voltage and/or frequency of a CPU included in a mobile computing device. In particular, the embodiments are directed to alleviating a variety of performance and energy efficiency issues that are often exhibited by mobile computing devices and that are not well-addressed by conventional power-management techniques. As set forth in greater detail below, the embodiments alleviate these performance and energy efficiency issues by implementing techniques that focus on various aspects of how processes are carried out within the mobile computing device. For example, one embodiment of the invention involves scaling the voltage and/or frequency of the CPU based on the number of frames per second (NFPS) being input to a frame buffer in order to reduce or eliminate choppiness in animations shown on a display of the mobile computing device. Another embodiment of the invention involves scaling the voltage and/or frequency of the CPU based on a utilization rate of the GPU in order to reduce or eliminate any bottleneck caused by slow issuance of instructions from the CPU to the GPU. A third embodiment of the invention involves scaling the voltage and/or frequency of the CPU based on the throughput of data transiting the memory controller. A fourth embodiment of the invention involves scaling the voltage and/or frequency of the CPU based on specific types of instructions being executed by the CPU. An additional embodiment of the invention involves scaling the voltage and/or frequency of the CPU based on the duty factor of the CPU for workloads that cause a user interface to animate below a threshold rate.

As noted above, one existing performance issue exhibited by mobile computing devices involves the smoothness of animations shown on a display of the mobile computing device. For example, choppy display of an animation (e.g., scrolling of a web page) contributes to a poor user experience and should be eliminated whenever possible. Accordingly, one embodiment of the invention involves scaling the voltage and/or frequency of the CPU based on the number of frames-per-second (NFPS) being supplied to a frame buffer included in the mobile computing device. In particular, a monitor measures short-term “jitter” in the NFPS being input to the frame buffer as well as the long-term stability of the NFPS being input to the frame buffer to determine whether the CPU is operating at a power and/or frequency sufficient to produce smooth animations. More specifically, when the monitor observes changes in the NFPS, the monitor increases the voltage and/or frequency of the CPU to smooth out the NFPS. Conversely, when the monitor observes that the NFPS is stable, the monitor decreases the voltage and/or frequency of the CPU in order to conserve energy.

Another existing performance issue exhibited by mobile computing devices involves the bottleneck that often occurs between instructions issued by CPU to the GPU. For example, the CPU can operate in a sub-optimal mode when the activity of the GPU is such that the GPU requests new instructions from the CPU at a rate faster than the CPU can produce the new instructions (e.g., during GPU benchmark tests). While in the sub-optimal mode, the CPU can operate at a sub-optimal voltage and/or frequency. Accordingly, when it is determined that a utilization rate of the GPU is exceeding a threshold level and that the CPU is operating in a sub-optimal operating mode, the CPU can be configured to enter into an optimal operating mode, which increases the rate at which the CPU generates instructions to be executed by the GPU. Adjusting the operating mode of the CPU can include adjusting the voltage and/or frequency at which the CPU is operating. Later, when it can be determined that the utilization rate of the GPU is no longer exceeding the threshold level, the CPU can be configured to enter back into the sub-optimal operating mode. In this manner, critical GPU workloads—such as graphics benchmarks—are not hindered by the CPU when the CPU is operating at a sub-optimal voltage and/or frequency.

Yet another existing performance issue exhibited by mobile computing devices involves the bottleneck that is introduced when the CPU manages data flows between the memory controller and one or more memory agents. For example, the CPU can operate in a sub-optimal mode when encoding a video and writing the result to DRAM at a rate slower than a rate at which the memory interface is capable of operating. As another example, the CPU can operate in a sub-optimal mode when executing a flash memory subsystem device driver for the purpose of reading data from the flash memory subsystem, where executing the driver slowly may increase access latency. While in the sub-optimal mode, the CPU can operate at a sub-optimal voltage and/or frequency. Accordingly, when it is determined that a read or write throughput of traffic between the CPU and the memory controller is exceeding threshold levels—or, that the read or write throughput of traffic between the flash memory subsystem and the memory controller is exceeding threshold levels, and that the CPU is operating in a sub-optimal operating mode—the CPU can be configured to enter into an optimal operating mode. Later, when it can be determined that these throughputs are no longer exceeding the threshold levels, the CPU can be configured to enter back into the sub-optimal operating mode.

Another existing energy efficiency issue exhibited by mobile computing devices involves erroneously increasing the voltage and/or frequency of the CPU solely based on the utilization rate of the CPU. For example, a simple spin loop workload—such as a loop that frequently checks for a specific condition to be met—may increase the utilization rate of the CPU to 99% and cause, via conventional algorithms, the voltage and/or frequency of the CPU to be increased. Importantly, in this example, such an increase in no way promotes a faster completion of the spin loop, so energy is wasted in doing so. However, some specific workloads executed by the CPU—such as those involving integer arithmetic, VFP arithmetic, SIMD arithmetic and load-store operations—can benefit from an increase in the voltage and/or frequency of the CPU. Accordingly, yet another embodiment of the invention involves the monitor analyzing the rate at which certain types of instructions are being executed by the CPU and scaling the voltage and/or frequency of the CPU based on the rate. In this manner, wasteful CPU performance increases can be avoided, thereby saving energy.

Another existing energy efficiency issue exhibited by mobile computing devices involves erroneously increasing the voltage and/or frequency of the CPU solely based on the utilization rate of the CPU while executing workloads for which a user is not waiting for results. For example, a video game containing a spinloop may exhibit high CPU utilization, but increasing the voltage and/or frequency of the CPU by conventional algorithms will increase CPU power while possibly not increasing the NFPS produced by the game. By contrast, a circuit layout optimization tool may also exhibit high CPU utilization, but here increasing the voltage and/or frequency of the CPU by conventional algorithms may reduce the time a user must wait for the result of the computation. Accordingly, another embodiment of the invention involves monitoring the UI frame rate and increasing the voltage and/or frequency of the CPU by conventional algorithms only when the UI frame rate is below a threshold and the CPU utilization is above a threshold. When the UI is not a principal component of the workload, this embodiment permits the energy budget of the mobile device to be biased towards CPU-based computation.

According to these techniques, the default operating mode of the CPU is minimum performance, and increased performance is provided only to workloads that can benefit from such an increase. For example, by scaling the operating mode of the CPU relative to UI frame rate smoothness, interactive applications that do not benefit from the higher performance of newer CPUs can save tens to thousands of milliwatts relative to existing power management algorithms. At the same time, high-end graphical applications are permitted to access the full compute performance of both the CPU and the GPU. High-throughput data transaction workloads are similarly permitted to access the full compute performance of the CPU. Monitoring arithmetic and load-store instruction densities enables a distinction to be established between workloads that perform useful computations with additional CPU performance and those that do not, thereby saving hundreds of milliwatts on applications that task the CPU with executing “busy loops.” Finally, by considering the UI frame rate, the use of conventional algorithms that increase CPU performance in response to high CPU utilization can be enabled when the user is waiting for a time-intensive computation to complete, but disabled for animation workloads that may not benefit from increased performance.

As set forth above, various embodiments of the invention are directed to scaling of the voltage and/or frequency of a CPU included in a mobile computing device. A detailed description of the embodiments is provided below in conjunction withFIGS. 1,2A-2E,3A-3C, and4A-4E. In particular,FIG. 1illustrates a block diagram of a mobile computing device100configured to implement embodiments of the invention. As shown inFIG. 1, mobile computing device100includes subsystems such as CPU102, a memory controller103, a system memory104, GPU106, frame buffer108, and display device110. As is well-known, CPU102generates and transmits instructions103to GPU106for execution, where GPU106consumes the instructions at a rate that is influenced at least by the utilization rate of GPU106and a rate at which CPU102is generating and transmitting the instructions103to GPU106. Frame buffer108is configured to continually receive and store an updated sequence of frames that are eventually output to display device110. Also shown inFIG. 1are monitor112and power manager114, which are loaded in system memory104and configured to execute on mobile computing device100. In one embodiment, system memory104include both a DRAM subsystem (not illustrated) and a flash memory subsystem (not illustrated) that are managed by the memory controller103. Although not illustrated inFIG. 1, each of monitor112and power manager114can run on an operating system (OS) that is configured to execute on mobile computing device100. Additionally, monitor112and power manager114can run on a management co-processor (not illustrated) that is separate and distinct from the CPU102.

As described in greater detail below, monitor112is configured to implement various techniques directed toward identifying circumstances where a change in the voltage and/or frequency of CPU102is beneficial to the overall performance of mobile computing device100and energy savings within mobile computing device100. In particular, monitor112receives, from a number of controllers, control signals that scale with a focus on a particular activity within mobile computing device100, e.g., the rate of change in the NFPS being input to the frame buffer108, the utilization rate of GPU106, the data throughputs of the memory controller103, the rate at which specific types of instructions are being executed by CPU102, or the rate at which a user interface is being updated. In turn, monitor112processes the control signals and outputs the control signals to power manager114, whereupon the power manager114correspondingly scales the voltage and/or frequency of CPU102. For example, one control signal can slowly increase in value (e.g., the utilization rate of GPU106) and cause the power manager114to correspondingly increase the voltage and/or frequency of CPU102, thereby reducing or eliminating a potential bottleneck that might occur between the rate at which GPU106is able to consume instructions issued by CPU102.

In one embodiment, each controller produces a scalar value—also referred to herein as a “control effort”—that takes on a value from 0 to 255, where larger values are expressions of a desire for higher performance. Each of the controllers produces a control effort value independently of the other controllers. As described in greater detail below, the control effort value that determines the CPU102performance configuration is the maximum of the individual control efforts. Given the winning control effort, the mapping to a CPU102performance configuration may vary. In one embodiment, the range 0-255 may be linearly mapped to qualified CPU102frequencies. In a related embodiment, the mapping may instead be linear in CPU102voltage rather than frequency. In another embodiment, the mapping may involve the use of frequency/voltage dithering to produce a more precise mapping through pulse width modulation techniques. In yet another embodiment, the mapping may also determine the number of CPU102cores that may be concurrently active in a multi-core environment. For example, a lower control effort value may restrict the mobile computing device100to single-core operation as a means of conserving energy. In yet another embodiment, the mapping may also determine the selection of a primary core or secondary core, where the primary core is more powerful than the secondary core and is configured to operate during high demand periods, and where the secondary core is less powerful than the primary core and is configured to operate during low demand periods.

FIG. 2Aillustrates a conceptual diagram200of the embodiment directed to scaling the voltage and/or frequency of CPU102based on the NFPS being input to frame buffer108. As shown inFIG. 2A, the NFPS being input to frame buffer108is represented by frame rate202, which is analyzed by monitor112and observed by a user of mobile computing device100via display device110. Jitter component204, which is managed by monitor112, is configured to analyze (via the outermost loop ofFIG. 2A) short-term changes (i.e., cycle-to-cycle jitter) in the NFPS being input to frame buffer108within a short-term threshold amount of time. Notably, the NFPS being input to frame buffer108is correlated to the smoothness of user interfaces (UIs) that are displayed on display device110, which significantly impacts overall user experience. In one embodiment, the cycle-to-cycle jitter is defined as the difference in instantaneous frame rates over two consecutive frame rate samples. Consider, for example, the absolute times of three sequential frame buffer108updates T1, T2and T3, where the instantaneous frame rate F(1to2)=1/(T2−T1) and the instantaneous frame rate F(2to3)=1/(T3−T2). According to this example, the cycle-to-cycle jitter associated with this sequence is equal to the absolute value of (F(2to3)−F(1to2)), which is then output by jitter component204and compared at comparator206against a jitter threshold Tj208(e.g., three frames per second (FPS)).

As shown inFIG. 2A, comparator206is configured to output a jitter delta ej(t)210to jitter control signal generator212. When the output of jitter component204is less than jitter threshold Tj208, the jitter delta ej(t)210is negative, which is what allows the comparator206to unwind when performance is sufficient to enable smooth animation. The jitter control signal generator212can be any form of a controller filter that is closed-loop stable. In one embodiment, the jitter control signal generator212can be an integrator that, in turn, integrates jitter deltas ej(t)210as they are output by comparator206and outputs a jitter control signal cj(t)214. In one embodiment, jitter control signal generator212can be configured to apply a gain Kjto the integrated jitter deltas ej(t)210in order to amplify the jitter control signal cj(t)214. Next, the jitter control signal cj(t)214is directed to max-selector232, which outputs a maximum of the jitter control signal cj(t)214, or a trend control signal ct(t)230that is produced according to the innermost loop ofFIG. 2Adescribed below.

More specifically, the innermost loop ofFIG. 2Arepresents monitor112analyzing long-term changes that occur in the NFPS being input to frame buffer108within a long-term threshold amount of time. Specifically, a long-term sample216and a long-term sample218are analyzed at comparator220to produce a trend value that represents the rate of change of the NFPS being input to frame buffer108over the long-term threshold amount of time. The absolute value of the trend value is then compared at comparator222against a trend threshold Tt224(e.g., one FPS), and comparator222outputs a trend delta et(t)226to trend control signal generator228. The trend control signal generator228can be any form of a controller filter that is closed-loop stable. In one embodiment, the trend control signal generator228can be an integrator that, in turn, integrates trend deltas et(t)226as they are output by comparator222and outputs the trend control signal ct(t)230. The trend control signal generator228can also be configured to apply a gain Ktto the integrated trend deltas et(t)226in order to amplify the trend control signal ct(t)230.

In some cases, an animation can exhibit high short-term jitter but is still stable over the long term. For example, a game that is not performance-limited but that uses imprecise frame rate timing may display this behavior. To avoid unnecessarily increasing CPU102performance for these cases, a linkage can exist between the jitter and trend controllers. More specifically, if the trend control effort is below some small value epsilon, a jitter value of zero (instead of the actual measured jitter sample) is supplied to the jitter delta term calculator, which has the effect of forcing the jitter loop to unwind so long as the trend loop is also unwound.

As noted above, max-selector232is configured to output a maximum of jitter control signal cj(t)214, or trend control signal ct(t)230, as a power management control signal234to power manager114. In turn, power manager114scales the voltage and/or frequency of CPU102according to power management control signal234. Accordingly, monitor112enables the performance of CPU102to scale dynamically in order to reduce or eliminate choppiness in the NFPS being input to frame buffer108, thereby providing energy savings and enhancing overall user experience.

Notably, at some point, most animations stop. Accordingly, embodiments of the invention incorporate a threshold amount of time after observing the last frame buffer108update (e.g., tens or hundreds of milliseconds). If no new update arrives in that time, the integrators are reset (and, therefore, the control efforts) to zero. As a result, shortly after an animation ends, the UI control loop will cease to have an influence on the operating mode of CPU102.

FIG. 2Billustrates a method270for updating an operating mode of CPU102based on monitoring a cycle-to-cycle jitter associated with a rate by which a user interface (UI) is refreshed, according to one embodiment of the invention. Although the method steps270are described in conjunction withFIGS. 1 and 2A, persons skilled in the art will understand that any system configured to perform the method steps, in any order, is within the scope of the invention.

As shown inFIG. 2B, the method270begins at step272, which monitors a cycle-to-cycle jitter associated with a rate by which a user interface (UI) is refreshed. At step274, monitor112adjusts an operating mode of the CPU based on the cycle-to-cycle jitter.

FIGS. 2C-2Eillustrate a method230for scaling the voltage and/or frequency of CPU102based on the NFPS being input to frame buffer108, according to one embodiment of the invention. Although the method steps230are described in conjunction withFIGS. 1 and 2A, persons skilled in the art will understand that any system configured to perform the method steps, in any order, is within the scope of the invention.

As shown inFIG. 2C, the method230begins at step231, where monitor112is configured to monitor frames being input into the frame buffer108. At step232, monitor112establishes a first short-term sample of a NFPS being input into the frame buffer108. At step234, monitor112establishes a second short-term sample of the NFPS being input into the frame buffer108. At step236, monitor112establishes a jitter value by taking the absolute value of the difference between the first short-term sample and the second short-term sample. Notably, steps231-236represent jitter component204described above in conjunction withFIG. 2A.

At step240, monitor112outputs a jitter delta value to a jitter integrator. At step242, monitor112integrates, at the jitter integrator, the jitter delta value with previously-output jitter delta values to produce a jitter-based power management control signal. At step244, monitor112outputs the jitter-based power management control signal.

At step245, which is illustrated inFIG. 4D, monitor112monitors frames being input into the frame buffer108. At step246, monitor112establishes a first long-term sample of the NFPS being input to the frame buffer108. At step248, monitor112establishes a second long-term sample of the NFPS being input to the frame buffer108. At step250, monitor112establishes a trend value by taking the absolute value of the difference between the first long-term sample and the second long-term sample. Notably, steps245-250represent long-term sample216, long-term sample218, and comparator220described above in conjunction withFIG. 2A.

At step254, monitor112outputs a trend delta value to a trend integrator. At step256, monitor112integrates, at the trend integrator, the trend delta value with previously-output trend delta values to produce a trend-based power management control signal. At step258, monitor112outputs the trend-based power management control signal.

Turning now toFIG. 2E, at step260, monitor112determines whether the jitter-based control signal is greater than the trend-based control signal. Notably, step260represents max-selector232described above in conjunction withFIG. 2A. If, at step260, monitor112determines that the jitter-based control signal is greater than the trend-based control signal, then the method230proceeds to step262, where monitor112scales the power and/or frequency of CPU102according to the jitter-based control signal. Otherwise, the method230proceeds to step264, where monitor112scales the power and/or frequency of CPU102according to the trend-based control signal.

FIG. 3Aillustrates a conceptual diagram300of the embodiment directed to scaling the power and/or frequency of CPU102based on the utilization rate of GPU106. As shown inFIG. 3A, the conceptual diagram300includes a single loop that is directed to analyzing the utilization rate of GPU106. In particular, GPU106provides GPU utilization rate feedback302to comparator304, which is configured to compare the GPU utilization rate feedback302to a GPU utilization threshold Tg306(e.g., 99%).

If the GPU utilization threshold Tg306is exceeded by the GPU utilization rate feedback302, then comparator304outputs a delta eg(t)308to control signal generator310. The control signal generator310can be any form of a controller filter that is closed-loop stable. In one embodiment, control signal generator310can be an integrator that, in turn, integrates deltas eg(t)308as they are output by comparator304and outputs a GPU control signal cg(t)312to power manager114. Control signal generator310can be configured to apply a gain Kgto the integrated deltas eg(t)308in order to amplify the power management control signal314. In turn, power manager114receives the power management control signal314and accordingly scales the power and/or frequency of CPU102. In this manner, the performance of CPU102scales with the utilization rate of GPU106so that CPU102is able to issue instructions at a rate that is commensurate with the rate at which GPU106is consuming the instructions. As a result, bottlenecks that often occur between CPU102and GPU106are reduced or eliminated, thereby enhancing overall performance of mobile computing device100and ensuring that the full potential of GPU106is not hindered by lack of CPU102performance.

FIG. 3Billustrates a method330for entering CPU102into an optimal operating mode based on a utilization rate of GPU106, according to one embodiment of the invention. Although the method steps330are described in conjunction withFIGS. 1 and 3A, persons skilled in the art will understand that any system configured to perform the method steps, in any order, is within the scope of the invention.

As shown inFIG. 3B, the method330begins at step331, where monitor112is configured to monitor the output of GPU106. At step332, monitor112samples a current utilization rate of GPU106. At step334, monitor112determines whether the current utilization rate exceeds a GPU utilization threshold. If, at step334, monitor112determines that the current utilization rate exceeds the GPU utilization threshold, then the method330proceeds to step335. At step335, monitor112determines whether CPU102is operating in a sub-optimal operating mode. If, at step335, monitor112determines that CPU102is operating in a sub-optimal operating mode, then the method330proceeds to step336. Otherwise, the method330proceeds back to step331, where steps331-335are repeated until the current utilization rate exceeds the GPU utilization threshold and CPU102is operating in a sub-optimal operating mode. At step336, monitor112causes CPU102to enter into an optimal operating mode where CPU102generates instructions for execution by GPU106at a faster rate.

FIG. 3Cillustrates a method350for scaling the power and/or frequency of CPU102based on the utilization rate of GPU106, according to one embodiment of the invention. Although the method steps350are described in conjunction withFIGS. 1 and 3A, persons skilled in the art will understand that any system configured to perform the method steps, in any order, is within the scope of the invention.

As shown inFIG. 3C, the method350begins at step351, where monitor112is configured to monitor the output of GPU106. At step352, monitor112samples a current utilization rate of GPU106. At step356, monitor112outputs a GPU utilization delta value to a GPU utilization integrator. Notably, steps351-356represent comparator304and control signal generator310described above in conjunction withFIG. 3A. At step358, monitor112integrates, at the GPU utilization integrator, the GPU utilization delta value with previously-output GPU utilization delta values to produce a GPU utilization-based power management control signal. At step360, monitor112scales the power and/or frequency of CPU102according to the GPU utilization-based power management control signal.

FIG. 4Aillustrates a conceptual diagram400of the embodiment directed to analyzing the rate at which certain types of instructions are being executed by CPU102and scaling the power and/or frequency of CPU102based on the rate. As shown inFIG. 4A, monitor112analyzes the rate at which four specific types of instructions are being executed: integer arithmetic instructions402(the outermost loop), SIMD arithmetic instructions414(the second outermost loop), VFP instructions426(the third outermost loop), and load/store instructions438(the innermost loop). Workloads exhibiting high instruction-per-cycle densities of these instruction types are often well-optimized and can benefit from increases in the power and/or frequency of CPU102.

Beginning with the outermost loop, the integer arithmetic instructions402are compared at comparator404against an integer threshold Ti406(e.g., two hundred fifty instructions per cycle). If the integer threshold Ti406is exceeded by the rate at which integer arithmetic instructions402are being processed by CPU102, then comparator404outputs an integer delta ei(t)408to integer control signal generator410. The integer control signal generator410can be any form of a controller filter that is closed-loop stable. In one embodiment, the integer control signal generator410can be an integrator that, in turn, integrates integer deltas ei(t)408as they are output by comparator404and outputs an integer control signal ci(t)412. Next, the integer control signal ci(t)412is directed to max-selector449, which, as described in greater detail below, outputs a maximum of the integer control signal ci(t)412, a SIMD control signal cn(t)424that is produced according to the second outermost loop ofFIG. 4A, a VFP control signal cv(t)436that is produced according to the third outermost loop ofFIG. 4A, or a load/store control signal cL(t)448that is produced according to the innermost loop ofFIG. 4A.

At the second outermost loop ofFIG. 4A, the SIMD arithmetic instructions414are compared at comparator416against a SIMD threshold Tn418(e.g., one hundred fifty instructions per cycle). If the SIMD threshold Tn418is exceeded by the rate at which SIMD arithmetic instructions414are being processed by CPU102, then comparator416outputs a SIMD delta en(t)420to SIMD control signal generator422. The SIMD control signal generator422can be any form of a controller filter that is closed-loop stable. In one embodiment, the SIMD control signal generator422can be an integrator that, in turn, integrates SIMD deltas en(t)420as they are output by comparator416and outputs the SIMD control signal cn(t)424to max-selector449.

At the third outermost loop ofFIG. 4A, the VFP instructions426are compared at comparator430against a VFP threshold Tv428(e.g., fifty instructions per cycle). If the VFP threshold Tv428is exceeded by the rate at which VFP instructions426are being processed by CPU102, then comparator430outputs a VFP delta ev(t)432to VFP control signal generator434. The VFP control signal generator434can be any form of a controller filter that is closed-loop stable. In one embodiment, the VFP control signal generator434can be an integrator that, in turn, integrates VFP deltas ev(t)432as they are output by comparator430and outputs the VFP control signal cv(t)436to max-selector449.

At the innermost loop ofFIG. 4A, the load/store instructions438are compared at comparator442against a load/store threshold TL439. If the load/store threshold TL439is exceeded by the rate at which load/store instructions438are being processed by CPU102, then comparator442outputs a load/store delta eL(t)444to load/store control signal generator446. The load/store control signal generator446can be any form of a controller filter that is closed-loop stable. In one embodiment, the load/store control signal generator446can be an integrator that, in turn, integrates load/store deltas eL(t)444as they are output by comparator442and outputs the load/store control signal cL(t)448to max-selector449.

As noted above, max-selector449is configured to output a maximum of the integer control signal ci(t)412, the SIMD control signal cn(t)424, the VFP control signal cv(t)436, and the load/store control signal cL(t)448as a power management control signal440to power manager114. In turn, power manager114scales the power and/or frequency of CPU102according to power management control signal440. Accordingly, monitor112enables the performance of CPU102to scale dynamically when specific types of instructions that benefit from such a scaling are being executing by CPU102. Notably, monitor112can be further configured to provide similar scaling in response to other types of instructions being executed by CPU102, such as load/store instructions.

FIGS. 4B-4Eillustrate a method450for analyzing the rate at which certain types of instructions are being executed by CPU102and scaling the voltage and/or frequency of CPU102based on the rate, according to one embodiment of the invention. Although the method steps450are described in conjunction withFIGS. 1 and 4A, persons skilled in the art will understand that any system configured to perform the method steps, in any order, is within the scope of the invention.

As shown inFIG. 4B, the method450begins at step452, where monitor112samples a first rate at which SIMD instructions are being executed by a central processing unit (CPU). At step456, monitor112outputs a SIMD delta value to a SIMD arithmetic integrator. At step458, monitor112integrates, at the SIMD arithmetic integrator, the SIMD arithmetic delta value with previously-output SIMD arithmetic delta values to produce a SIMD arithmetic-based power management control signal.

Turning now toFIG. 4C, at step460, monitor112samples a second rate at which vector floating point (VFP) instructions are being executed by CPU102. At step464, monitor112outputs a VFP arithmetic delta value to a VFP arithmetic integrator. At step466, monitor112integrates, at the VFP arithmetic integrator, the VFP arithmetic delta value with previously-output VFP delta values to produce a VFP-based power management control signal.

Turning now toFIG. 4D, at step468, monitor112samples a third rate at which load/store instructions are being executed by CPU102. At step472, monitor112outputs a load/store delta value to a load/store integrator. At step474, monitor112integrates, at the load/store integrator, the load/store delta value with previously-output load/store delta values to produce a load/store-based power management control signal.

Turning now toFIG. 4E, at step476, monitor112samples a fourth rate at which integer arithmetic instructions are being executed by CPU102. At step480, monitor112outputs an integer arithmetic delta value to an integer arithmetic integrator. At step482, monitor112integrates, at the integer arithmetic integrator, the integer arithmetic delta value with previously-output integer arithmetic delta values to produce an integer arithmetic-based power management control signal.

At step484, monitor112selects a largest of the SIMD arithmetic-based power management control signal, the VFP-based power management control signal, and the integer arithmetic-based power management control signal. At step486, monitor112scales a power level of the CPU based on the selected power management control signal.

As previously noted herein, embodiments of the invention also include a method for optimizing operations of the CPU102where the CPU102is configured to perform transactions with the memory controller103that manages access to a DRAM and a flash memory. According to one embodiment, memory controller103is configured to separately measure the throughput of traffic to and from the CPU102and also separately measure the throughput of traffic to and from the flash memory subsystem. This technique provides increased CPU102performance for high-throughput data transaction workloads, e.g., video encoding and high-performance photography. Once memory activity exceeds the relevant threshold(s), CPU performance is elevated.

FIG. 5Aillustrates a conceptual diagram of an embodiment directed to analyzing a rate at which the CPU102performs transactions with the memory controller103, according to one embodiment of the invention. As shown inFIG. 5A, monitor112analyzes the throughput of traffic to and from the CPU and also the throughput of traffic to and from the flash memory subsystem, which is represented inFIG. 5Aas: flash memory OUT502(the outermost loop), flash memory IN514(the second outermost loop), CPU OUT526(the third outermost loop), and CPU IN538(the innermost loop), respectively.

Beginning with the outermost loop, flash memory OUT502is compared at comparator504against a flash memory OUT threshold Ti506. If flash memory OUT threshold Ti506is exceeded by the rate of flash memory OUT502, then comparator504outputs a flash memory OUT delta ei(t)508to flash memory OUT control signal generator510. The flash memory OUT control signal generator510can be any form of a controller filter that is closed-loop stable. In one embodiment, the flash memory OUT control signal generator510can be an integrator that, in turn, integrates flash memory OUT deltas ei(t)508as they are output by comparator504and outputs a flash memory OUT control signal ci(t)512. Next, the flash memory OUT control signal ci(t)512is directed to max-selector549, which, as described in greater detail below, outputs a maximum of the flash memory OUT control signal ci(t)512, a flash memory IN control signal cn(t)524that is produced according to the second outermost loop ofFIG. 5A, a CPU OUT control signal cv(t)536that is produced according to the third outermost loop ofFIG. 5A, or a CPU IN control signal cL(t)548that is produced according to the innermost loop ofFIG. 5A.

At the second outermost loop ofFIG. 5A, flash memory IN514is compared at comparator516against a flash memory IN threshold Tn518. If flash memory IN threshold Tn518is exceeded by the rate of flash memory IN514, then comparator516outputs a flash memory IN delta en(t)520to flash memory IN control signal generator522. The flash memory IN control signal generator522can be any form of a controller filter that is closed-loop stable. In one embodiment, the flash memory IN control signal generator522can be an integrator that, in turn, integrates flash memory IN deltas en(t)520as they are output by comparator516and outputs the flash memory IN control signal cn(t)524to max-selector549.

At the third outermost loop ofFIG. 5A, CPU OUT526is compared at comparator530against a CPU OUT threshold Tv528. If CPU OUT threshold Tv528is exceeded by the rate of CPU OUT526, then comparator530outputs a CPU OUT delta ev(t)532to CPU OUT control signal generator534. The CPU OUT control signal generator534can be any form of a controller filter that is closed-loop stable. In one embodiment, the CPU OUT control signal generator534can be an integrator that, in turn, integrates CPU OUT deltas ev(t)532as they are output by comparator530and outputs the CPU OUT control signal cv(t)536to max-selector549.

At the innermost loop ofFIG. 5A, CPU IN538is compared at comparator542against a CPU IN threshold TL539. If CPU IN threshold TL539is exceeded by the rate of CPU IN538, then comparator542outputs a CPU IN delta eL(t)544to CPU IN control signal generator546. The CPU IN control signal generator546can be any form of a controller filter that is closed-loop stable. In one embodiment, the CPU IN control signal generator546can be an integrator that, in turn, integrates CPU IN deltas eL(t)544as they are output by comparator542and outputs the CPU IN control signal cL(t)548to max-selector549.

As noted above, max-selector549is configured to output a maximum of the flash memory OUT control signal ci(t)512, the flash memory IN control signal cn(t)524, the CPU OUT control signal cv(t)536, and the CPU IN control signal cL(t)548as a power management control signal540to power manager114. In turn, power manager114scales the power and/or frequency of CPU102according to power management control signal540. Accordingly, monitor112enables the performance of CPU102to scale dynamically when executing high-throughput data transaction workloads, e.g., video encoding and high-performance photography.

FIG. 5Billustrates a method550for optimizing operations of CPU102when CPU102is configured to perform transactions with memory controller103and memory controller103is configured to manage access to a DRAM and a flash memory, according to one embodiment of the invention. As shown, the method550begins at step552, where monitor112samples first, second, third, and fourth rates at which traffic is being throughput through a memory controller, where the first rate and the second rate correspond to traffic throughput to/from the CPU102, respectively, and the third rate and the fourth rate correspond to traffic throughput to/from a flash memory subsystem, respectively.

At step554, monitor112outputs, for each of the first, second, third, and fourth rates, a throughput delta value to a first, second, third, and fourth throughput integrator, respectively. At step556, monitor112, at each of the first, second, third, and fourth throughput integrators, integrate the first, second, third, and fourth throughput delta values, respectively, with previously-output first, second, third, and fourth throughput delta values, respectively, to produce first, second, third, and fourth throughput-based power management control signals, respectively.

At step558, monitor112selects a largest of the first, second, third, and fourth throughput-based power management control signals. At step560, monitor112scales a power level of the CPU102on the selected power management control signal.

FIG. 6Aillustrates a conceptual diagram600of an embodiment directed to scaling the voltage and/or frequency of the CPU102when the CPU102executes workloads that have characteristics of traditional desktop/laptop computer applications, according to one embodiment of the invention. In particular, according to this embodiment, the voltage and/or frequency of the CPU102is only scaled when the mobile computing device100does not appear to be executing a UI-oriented workload. As illustrated inFIG. 6A, the technique involves two control loops, where the first control loop is configured to monitor CPU102for a CPU complex (or “package”) utilization measurement601, and where the second control loop is configured to monitor CPU102for a core utilization measurement613.

According to the embodiment illustrated inFIG. 6A, the first control loop involves measuring a fraction of the sample interval in which at least one core of CPU102is active. The complex utilization measurement601is compared at comparator602against a complex utilization target603(e.g., 99%), and a delta eU(t)604is output by comparator602to an integrator605. Next, the output of integrator605is fed into a max-selector628, which outputs a maximum of the output of the integrator605and an integrator624of the second loop (described in greater detail below).

The second control loop involves measuring the duty factor of the cores of the CPU102by adding up the time each core spends active. For example, a dual-core CPU102would report a utilization of 100% if both of the cores were active throughout an entire sample interval. As shown inFIG. 6A, the core utilization measurement613is compared at comparator614against a core utilization target615(e.g., 90%), and a delta eu(t)616is output by comparator614to an integrator624. Next, the output of integrator624is fed into the max-selector628, which, as noted above, outputs a maximum of the output of the integrator605and the integrator624. Finally, component630takes into account whether or not a threshold NFPS are being input into the frame buffer108. In particular, if a threshold NFPS (e.g., 15 FPS) are being input into the frame buffer108, then the output of the max-selector628is not fed into the power manager114; otherwise, the output of the max-selector628is fed into the power manager114, and the voltage and/or frequency of the CPU102is scaled according to the output of the max-selector628.

FIG. 6Billustrates a method650for scaling the voltage and/or frequency of a CPU when the CPU executes workloads that have characteristics of traditional desktop/laptop computer applications, according to one embodiment of the invention.

As shown, the method650begins at step652, where monitor112generates a first control signal based at least in part on measuring a sample interval in which at least one core of a central processing unit (CPU) is active. At step654, monitor112generates a second control signal based at least in part on measuring an amount of time that each core of the CPU is active. At step656, monitor112selects a maximum of the first control signal and the second control signal. At step658, monitor112determines if a user interface activity level exceeds a threshold (e.g., by monitoring a NFPS being input into the frame buffer108). If, at step658, monitor112determines that the user interface activity level exceeds the threshold, then method650ends; otherwise, at step660, monitor112scales a voltage and/or frequency of the CPU based on the control signal selected at step656.

Although the foregoing invention has been described in detail by way of illustration and example for purposes of clarity and understanding, it will be recognized that the above described invention may be embodied in numerous other specific variations and embodiments without departing from the spirit or essential characteristics of the invention. Certain changes and modifications may be practiced, and it is understood that the invention is not to be limited by the foregoing details, but rather is to be defined by the scope of the appended claims.