An enveloping curves generator is disclosed that guarantees that one curve will envelop or overlap another when both are traversing from one logic level to another, and where the other overlaps the first when both traversing the other direction. In one case, a steering FET controlled by an input signal drives a first output high via a circuit. That first output going high, after a delay, drives a second output high. When the input goes low, a second steering FET controlled by the input signal drives the second output low. That second output going low, after a delay, drives the first output low. No latching is provided in the present invention.

CROSS REFERENCE TO OTHER PATENTS

The present application is related to U.S. Pat. No. 6,838,920 B1 that issued Jan. 4, 2005. This issued patent is commonly owned with the present application, and this patent is hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to signal generation, and more particularly to generation of signals with profiles or curves guaranteed to envelop or overlap other signals or curves, even when variations of chip processing and operating environments are considered.

2. Background Information

One problem, found in many circuits where transistors are stacked, occurs when one transistor is turning off and the other is turning on. If there is an overlap where both are on, even briefly, relatively large current spikes may occur. These spikes may cause circuit malfunctions.

In many applications there is a continuing need for circuit designs where “break before make” or, possibly, “make before break” operations are required. Ensuring such a sequential operation can relieve the spiking problem and such is an objective of the present invention.

U.S. Pat. No. 6,838,920 B1 ('920), mentioned above, provides a circuit that ensures these sequential operations. This circuit may be used to advantage in many applications. Prior artFIGS. 1 and 2are taken directly fromFIGS. 1 and 2in '920 patent. An operative feature of the '920 patent is latching that is prominently discussed and claimed therein.

Referring toFIGS. 1 and 2of the present application, it can be seen that when IN goes high, Q2turns on and Q1turns off. Q1and Q2are steering FET's that direct the input signal to operate the circuit as discussed. Q1operates to hold point A high, but Q1turning off has no effect since the inverter I3also holds point A high. Point A is also the input to inverter I1, so O2, the output of I1remains low. Meanwhile, point B, which was high, is driven low by Q2turning on as IN goes high. Point B is held high by I2(since O2remains low), but Q2is designed to overcome I2's drive and force point B low. When point B goes low, O1is driven high by I4with item20indicating the initial source of O1going high is IN going high. When O1goes high, the latch on point A via I3is released. Thus, point A goes low and O2goes high via I1as indicated by item22. The feed back around the loops of inverters ensures that O2goes high well after (by two gate delays at least) and in response to O1going high. The arrows inFIG. 2show the imposed sequence of signals, the enveloping is evident.

Correspondingly, when IN goes low, Q1turns on and Q2turns off. Q1drives point A high, but Point B remains low regardless of Q2, since the latching I2drives B low. Here Q1overcomes the I3latch that was driving point A low. Then, in sequence, O2goes low24driving point B high, which drives O1low26via I4. I4, in turn, drives point A high which latches point O1high. These operations are well shown in the traces shown inFIG. 2.

In each of the above operations, please note that Q2drives point B low by overcoming the drive of I2; and that Q1drives point A high overcoming the drive of I3. This contention serves to slow the circuit frequency of operation, affects low voltage operation, dissipates power, and impairs the wave forms/duty cycle of the resulting signals. The present invention is directed to these limitations of the circuit inFIG. 1and other known prior art circuits, while providing their and other advantages.

SUMMARY OF THE INVENTION

In view of the foregoing background discussion, the present invention provides a non-latching enveloping curves generator and method, where an input signal, via steering transistors, devices or circuits causes a first output signal to change logic states, and that change causes a second output to change logic states. The net effect is that, in response to the input signal changing from one logic state to a second, the first logic output changes levels before the second. When the input signal changes back, the second logic output changes levels before the first. The effect is that one output curve envelops the other.

In one preferred embodiment, the steering devices are a PMOS and an NMOS transistor, and the generator includes inverters connected in series. In this circuit when the second steering FET is turned off, the first steering FET is turned on. This places a high at the input of a first inverter. The output of that inverter is a first output that travels low. That low travels through a second inverter whose high output travels through a first on switch to a third inverter. This third inverter's output is a second output that always goes low after the first output goes low.

When the first steering FET is turned off, the second steering FET is turned on. This places a low at the input of the third inverter. The output of that inverter is the second output that travels high. That high travels through a fourth inverter whose low output travels through a second on switch to the input of the first inverter. The output of the first inverter is the first output and it is driven high. This first output always goes high after the second output goes high. The first switch is turned off in this case, and the second switch is turned off in the first case, described above.

In other preferred embodiments, non-inverters and combinations of inverters and non-inverters may be used to advantage.

It will be appreciated by those skilled in the art that although the following Detailed Description will proceed with reference being made to illustrative embodiments, the drawings, and methods of use, the present invention is not intended to be limited to these embodiments and methods of use. Rather, the present invention is of broad scope and is intended to be defined as only set forth in the accompanying claims.

DETAILED DESCRIPTION OF AN ILLUSTRATIVE EMBODIMENT

FIG. 3Aillustrates an embodiment of the present invention. The IN input signal is connected to the gates of two steering devices, a first steering FET, Q1and a second steering FET, Q2. In this instance, P and N type MOSFET's are illustrated, but other transistor devices or circuits may be used to accomplish the same function, as would be known to those skilled in the art. When IN is high,FIG. 3Billustrates the status of the circuit. Here, Q1is off and Q2is on, and second node point B′ is low and O1is driven high via second circuit inverter I4. Q3is a second switch functionally connects the second circuit output O1, via I3, to the first node A.′ I4drives I3that drives point A″ low. Q3is on so first node point A′ is low and first circuit I1drives O2high. I2drives point B″ high, but a first switch, Q4, functionally connected, via I2, from the first circuit I1output and the second node B′, is off so there is no latching of point B′ via Q4.

FIG. 3Cillustrates the timing and operations, as the schematic ofFIG. 3Byields to the schematic ofFIG. 3D, when IN goes low. ReferencingFIGS. 3C and 3D, when IN goes low Q1turns on, Q2turns off, Q3turns off and Q4turns on. At this point the circuit ofFIG. 3Dapplies. Point A′ is driven high via Q1, and since Q3is off, Q1does not have to overcome the drive of I3as inFIG. 1described above. O2goes low30via I1driving point B″ high via I2. B″ high drives point B′ high via Q4, and I4drives O1low32. Notice the O1low drives A″ high, but, since Q3is off, A″ high does not connect to A′ and the circuit is not latched.

When IN is low, the circuit inFIG. 3Dapplies, and as IN goes high the timing signals ofFIG. 3Eillustrate the timing as the schematic ofFIG. 3Dyields to that ofFIG. 3B. When IN goes high, Q1turns off, Q2turns on, Q3turns on, and Q4turns off, and the circuit ofFIG. 3Bapplies. Point B′ is driven low via Q2, and since Q4is off, Q2does not have to overcome the latching drive of I2as inFIG. 1. B′ low drives O1high34via I4, that in turn drives A″ low via I3. A″ low drives A′ low via the on Q3, and O2high36via I1. Note that I2drives point B″ low, but that low does not latch since Q4is off.

FIG. 3Fillustrates an embodiment of one inverter, in this case I1. The gates of a PMOS Q10and the NMOS Q12are tied together to A′, and the drains of each are tied together to form O2. The source of Q10is tied to Vdd and the source of Q12is tied to ground. This arrangement is a well known push/pull stacking of transistors to form an inverter. Other circuit devices and components may be used as is known to those skilled in the art. Also, the present embodiments shown inFIGS. 3A-3Fillustrate inverters or inverting circuits, but non-inverting circuits (herein defined with one or more inputs) may be used or even combinations of inverters and non-inverters may be used. Also, other circuits may be used with the inverters/non-inverters in other applications. In addition, resistors may be added to the circuit, as in the incorporated patent mentioned above, to provide circuit delays if desired.

Notice that the timing diagrams ofFIG. 3CandFIG. 3Edemonstrate the same enveloping or overlapping of the outputs O1and O2as illustrated inFIG. 2, but without the steering transistors, Q1and Q2, having to overcome output drives of the inverters as described above. This fact leads to advantages that are evident inFIGS. 4A,5A, and6A.

FIGS. 4A,4B,5A,5B,6A and6B are measurements made at 25° C. and similar size devices are used in each circuit.FIGS. 4A,5A, and6A are for the inventive circuit ofFIG. 3A, andFIGS. 4B,5B and6B are for the prior art circuit ofFIG. 1. In each case, the waveforms showing a double waveform, one trace solid and one trace dotted, are the enveloping curves O1and O2, as discussed herein.

The waveforms inFIGS. 4A and 4Bare at a Vdd supply voltage of 3.5V. This measurement was to compare supply currents. The current drawn from the Vdd supply for operation inFIG. 4A(new) was about 0.5 ma, while the current from Vdd inFIG. 4B(prior art) was about 2.0 ma. The inventive circuit dissipates less power than does the prior art circuit.

The Vdd supply voltage, for the waveforms inFIGS. 5A and 5BandFIGS. 6A and 6B, is 1.5V. The respective currents drawn from Vdd forFIG. 5A(new) is 0.16 ma and forFIG. 5B(prior art) is 0.45 ma. The respective currents drawn from Vdd forFIG. 6A(new) is 1.6 ma and forFIG. 6B(prior art) is 5.3 ma. It is noted that in each case the new circuit drew less current and thus dissipated less power than the prior art circuit. Again these comparisons are with similar device sizes at room temperature.

Comparing the traces inFIG. 5A(new) with those inFIG. 5B(prior art), there is a defined output, O1/O2, inFIG. 5A, while there is some un-usable noise-like response inFIG. 5B.

Comparing the traces inFIG. 6A(new) with those inFIG. 6B(prior art), each with a high frequency input of about 1.4 GHz, it is evident that the new circuit provides a useable output of both O1and O2while the prior art circuit outputs are unusable.

FIG. 7Aillustrates another embodiment of the present invention. Here, there are two non-inverting circuits, G1and G2, arranged back to back with intervening switches Q5and Q6. When IN is high, Q1and Q4are off, while Q2and Q3are on.FIG. 7Billustrates this case. O1and O2are both high. The timing sequence is enveloping, as before, forFIG. 3A, except there is only one gate delay between the outputs. Specifically, when Q2turns on, G2drives O1low, which, in turn, drives O2low via G1.

FIG. 7Dillustrates the same enveloping operating of the circuit ofFIG. 7A.

FIG. 7Eillustrates one example of how a non-inverting circuit, comprised of series inverters, may be used for G1and G2. Of course, other circuits and combinations of circuits may used to advantage.

FIG. 8Aillustrates another embodiment, except one non-inverting gate G1is replaced by two inverters in series. In this case, the polarity of one output may be reversed. This timing is shown inFIG. 8B, where the enveloping remains but one signal is inverted with respect to the other output.FIG. 8Cillustrates another embodiment where inverters are used.

Although the preferred embodiments are illustrated using MOSFET's herein, other devices may be used as known to those skilled in the art. Some examples of such other devices include: bipolar transistors, insulated gate bipolar transistors, hybrid forms of transistors, and combinations thereof. In addition, as known to those skilled in the art, the inverter and non-inverting gates may be comprised of different arrangements of circuit components, e.g. cascade and totem pole type circuits, among others.

It should be understood that above-described embodiments are being presented herein as examples and that many variations and alternatives thereof are possible. Accordingly, the present invention should be viewed broadly as being defined only as set forth in the hereinafter appended claims.