Method for restoring a timing controller and driving device for performing the method

A method of restoring a timing controller includes generating an error condition signal from a timing controller by checking abnormality of an image signal and a control signal provided from an image board, feeding back the error condition signal to the image board, and restoring the timing controller based on the error condition signal.

This application claims priority to Korean Patent Application No. 2010-0123643, filed on Dec. 6, 2010, and all the benefits accruing therefrom under 35 U.S.C. §119, the content of which in its entirety is herein incorporated by reference.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

Exemplary embodiments of the present invention relate to a method of restoring a timing controller and a driving apparatus for performing the method. More particularly, exemplary embodiments of the present invention relate to a method of restoring a timing controller to enhance display quality of a display panel by removing an error condition of the timing controller in advance, and a driving apparatus for performing the method.

(2) Description of the Related Art

Generally, a display device includes devices such as a liquid crystal display (“LCD”) device, a plasma panel display (“PDP”) device, an organic light-emitting diode (“OLED”) device, a field emission display (“FED”) device, for example.

The display device typically includes a timing controller that controls a timing of a control signal or an image signal to provide a display panel with a controlled control signal or a controlled image signal. That is, the timing controller is a core integrated circuit which generates on/off timing signals of active switches on a display panel and performs a converting process of an image data for enhancing a response speed of liquid crystals and display quality.

In general, the timing controller requires various parameters and a look-up table (“LUT”) to control the timing controller and drive the display panel in an optimum condition.

The parameters or the LUT are stored in a storage element such as an electrically erasable programmable read only memory (“EEPROM”), for example, and are loaded in the timing controller using an inter-integrated circuit (“I2C”) communication when power is applied from an image board. When all parameters are loaded in the timing controller, the timing controller is in a state for driving an LCD device.

A conventional timing controller is started at a time in which all parameters are loaded in the timing controller from the EEPROM. However, even though all parameters are loaded in the timing controller from the EEPROM, a display error on a display panel of the LCD device may occur.

When an input of the timing controller is abnormal or a margin of an inner element for an input of the timing controller is lacking, display defects may occur. When a logic error is caused at a mounting condition that is not anticipated, display defects may occur.

Thus, a condition, in which display defects of the timing controller occur, may be detected in advance at a state that the display panel is not driven. Moreover, a plan capable of removing the condition so as to prevent the display defects is required.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention provide a method of restoring a timing controller for removing an error condition of the timing controller in advance.

Exemplary embodiments of the present invention also provide a driving apparatus for performing the above-mentioned method.

In an exemplary embodiment, a method of restoring a timing controller includes generating an error condition signal from a timing controller by checking abnormality of an image signal and a control signal provided from an image board, feeding back the error condition signal to the image board, and restoring the timing controller based on the error condition signal.

In an exemplary embodiment, the generating the error condition signal may include calculating coefficients from the image signal based on a look-up table loaded from an external storage part, comparing the coefficients and the control signal with reference data stored in the external storage part, and generating the error condition signal when the coefficients and the control signal are different from the reference data.

In an exemplary embodiment, the generating the error condition signal may further include counting pulses of the error condition signal, and outputting the error condition signal when a counted number of the pulses of the error condition signal corresponds to a predetermined value.

In an exemplary embodiment, the generating the error condition signal may further include counting pulses of the error condition signal, and outputting the error condition signal when a counted number of the pulses of the error condition signal corresponds to a predetermined value.

In an exemplary embodiment, the comparing the control signal with the reference data may include comparing a clock signal and a data enable signal with the reference data stored in the external storage part.

In an exemplary embodiment, the generating the error condition signal may include detecting a plurality of error conditions different from each other and outputting a plurality of error condition signals based on the plurality of error conditions, and storing the plurality of error condition signals.

In an exemplary embodiment, the stored error condition signals are transmitted to the image board through an inter-integrated circuit (I2C) communication, when the image board requests the plurality of error condition signals.

In an exemplary embodiment, the restoring the timing controller may include altering the calculated coefficients.

In an exemplary embodiment, the generating the error condition signal may include detecting a plurality of error conditions different from each other and outputting a plurality of error condition signals, and performing a logical disjunction on the plurality of error condition signals to output the error condition signal.

In an exemplary embodiment, the restoring the timing controller may include initiating the timing controller.

In an exemplary embodiment, a driving apparatus includes a timing controller which generates an error condition signal by checking abnormality of an image signal and a control signal, and an image board which provides the image signal and the control signal to the timing controller and restores the timing controller based on the error condition signal provided from the timing controller.

In an exemplary embodiment, the timing controller may include a logic part which provides the image signal and the control signal to the timing controller and restores the timing controller based on the error condition signal provided from the timing controller, and an error-detecting part which compares the coefficients and the control signal to generate the error condition signal when the coefficients and the control signal are different from reference data.

In an exemplary embodiment, the timing controller may further include a counter which counts pulses of the error condition signal to output the error condition signal when a counted number of the pulses of the error condition signal corresponds to a predetermined number.

In an exemplary embodiment, the error-detecting part may include a plurality of detecting parts which detects a plurality of error conditions different from each other to output error condition signals, and a register which stores the plurality of error condition signals.

In an exemplary embodiment, the error-detecting part may transmit the stored error condition signals to the image board through an inter-integrated circuit (“I2C”) communication, when the image board requests the error condition signals.

In an exemplary embodiment, the image board may alter the coefficients to restore the timing controller.

In an exemplary embodiment, the error condition signal may include at least one of information on existence or nonexistence of an error condition, an error condition type, a command required for the image board corresponding to the error condition kinds, and a register value needed for operating the image board.

In an exemplary embodiment, the error-detecting part may include a plurality of detecting parts which detects a plurality of error conditions to output a plurality of error condition signals, and an arithmetic part which performs a logical disjunction on the plurality of error condition signals to output the error condition signal.

In an exemplary embodiment, one of the error condition signals may be outputted to the image board through an output terminal of the timing controller.

In an exemplary embodiment, the image board may initiate the timing controller to restore the timing controller when the error condition signal is inputted thereto.

In exemplary embodiments of the present invention, the timing controller detects an error condition to feed back an error condition signal to an image board, and the image board restores the timing controller based on the error condition signal. Thus, display defects due to an abnormal operation of the timing controller are effectively prevented, and a display quality of a display device is thereby substantially enhanced.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is a block diagram illustrating an exemplary embodiment of a driving apparatus according to the present invention.FIG. 2is a block diagram illustrating an alternative exemplary embodiment of the driving apparatus shown inFIG. 1.FIG. 3is a waveform diagram illustrating a data enable signal for explaining an error condition signal shown inFIG. 2.FIG. 4is a block diagram illustrating an exemplary embodiment of a timing controller shown inFIG. 2for explaining a coefficient error signal.FIG. 5is a table showing an example of a checksum stored on an external storage part shown inFIG. 4.FIG. 6is a table showing an example of coefficients calculated by a logic part shown inFIG. 4.

Referring toFIGS. 1 and 2, the driving apparatus10includes an image board100and a timing controller300. For convenience of description, a display panel200, a data driving part210and a gate driving part230that are driven by the driving apparatus10are described inFIG. 1.

The image board100provides the timing controller300with a first image signal DATA1and a first control signal CONT1. The image board100receives an image signal from an external device (not shown), and then scales the image signal to the first image signal DATA1corresponding to a resolution of the display panel200.

The first image signal DATA1may be transmitted to the timing controller300in a low voltage differential signaling (“LVDS”) method. The first control signal CONT1may include a vertical synchronizing signal, a horizontal synchronizing signal, a main clock signal, a data enable signal DE, for example. The vertical synchronizing signal corresponds to a time during which a single frame is displayed. The horizontal synchronizing signal corresponds to a time during which a single frame line. Thus, the horizontal synchronizing signal includes pulses corresponding to the number of pixels included in the single frame line. The data enable signal corresponds to a time during which data is supplied to a pixel.

The timing controller300generates a second image signal DATA2using the first image signal DATA1, and generates a plurality of timing signals for driving the display panel200using the first control signal CONT1. The timing signals include a data control signal CONT2and a gate control signal CONT3.

In one exemplary embodiment, the data control signal CONT2may include a horizontal synchronizing signal, a load signal, an inversion signal, a data clock signal, for example, for controlling a driving of the data driving part210. The gate control signal CONT3may include a vertical synchronizing signal, a gate clock signal, a gate enable signal, for example, for controlling a driving of the gate driving part230.

The timing controller300generates an error condition signal FF based on the first image signal DATA1and the first control signal CONT1. The error condition signal FF is a signal for detecting an abnormal driving of the timing controller300in advance, and is fed back to the image board100.

The image board100restores the timing controller300based on the error condition signal FF provided from the timing controller300.

The timing controller300includes a logic part310and an error-detecting part330. The logic part310calculates coefficients, used to convert the first image signal DATA1into the second image signal DATA2, based on a look-up table read out from an external storage part. The second image signal DATA2is outputted to the data driving part210.

The error-detecting part330generates the error condition signal FF based on the first image signal DATA1and the first control signal CONT1. The error-detecting part330compares the coefficients and the first control signal CONT1with reference data stored in the external storage part, and generate the error condition signal FF when the coefficients and the first control signal CONT1are different from the reference data. A detailed description of a feedback of the error condition signal FF and a restoration of the timing controller300will be described later in detail.

The display panel200includes an array substrate, an opposite substrate and a liquid crystal layer disposed between the array substrate and the opposite substrate. The display panel200includes a plurality of data lines DL, a plurality of gate lines GL crossing the data lines DL, and a plurality of pixels P electrically connected to the data lines DL and the gate lines GL.

In one exemplary embodiment, for example, the first gate lines GL may extend along a first direction, and the data lines DL may extend along a second direction substantially perpendicular to the first direction. Each pixel P includes a switching element TR, a liquid crystal capacitor CLC and a storage capacitor CST.

The data driving part210converts the second image signal DATA2into a data voltage of an analog type using the data control signal CONT2and a gamma reference voltage Vgamma. The data driving part210outputs the data voltage to the data lines DL of the display panel200.

A gamma voltage generating part (not shown) generates the gamma reference voltage to provide the data driving part210with the gamma reference voltage. In an exemplary embodiment, the gamma voltage generating part may be disposed within the data driving part210. In an alternative exemplary embodiment, the gamma voltage generating part may be disposed within the timing controller300.

In an exemplary embodiment, the data driving part210may be disposed, e.g., directly mounted, on the display panel200or may be connected to the display panel200in a tape carrier package (“TCP”) structure. In an alternative exemplary embodiment, the data driving part210may be integrated into the display panel200.

The gate driving part230generates a gate signal in response to the gate control signal CONT3. The gate driving part230generates the gate signal using an on voltage Von, an off voltage Voff and a common voltage Vcom to output the gate signal to the gate lines GL of the display panel100.

In an exemplary embodiment, the gate driving part230may be disposed, e.g., directly mounted, on the display panel200or may be connected to the display panel200in a TCP structure. In an alternative exemplary embodiment, the gate driving part230may be integrated into the display panel200.

In such an exemplary embodiment, it is described that the display panel200is employed in a liquid crystal display (“LCD”) device. In an alternative exemplary embodiment, the display panel200may be employed in other types of display device, such as a plasma panel display (“PDP”) device, an organic light-emitting diode (“OLED”) device and a field emission display (“FED”) device, for example.

As described above, the display panel200displays an image based on the second image signal DATA2, a data control signal CONT2and the gate control signal CONT3provided from the timing controller300. Thus, when the timing controller300is abnormally driven, display quality of an image displayed on the display panel200is thereby reduced.

In an exemplary embodiment, the error condition signal FF for detecting an abnormal driving condition of the timing controller300is generated from the error-detecting part330and transmitted to be fed back to the image board100. The image board100that receives the error condition signal FF may restore the timing controller300based on the error condition signal FF.

Accordingly, the abnormal driving condition of the timing controller300is detected and removed in advance, such that a malfunction of the display device, which is generated by the abnormal driving of the timing controller300, is effectively prevented.

As shown inFIG. 2, the timing controller300and the image board100exchange signals with each other in an inter-integrated circuit (“I2C”) communication.

The I2C communication is a two-wire communication interface, and these two wires typically includes a serial data line (“SDA”) provided for inputting/outputting data and a serial clock line (“SCL”) provided for controlling a data communication between the timing controller300and the image board100and for generating a clock. The timing controller300and the image board100that are connected in the I2C communication are identified by a unique address, and each of the timing controller300and the image board100may transmit or receive data.

A data may be delivered between the timing controller300and the image board100by a master-slave protocol. A master starts a data transmission and generates clocks. Remaining circuits except the master correspond to a slave which sends and receives data.

When a power-on signal is applied from the image board100, the timing controller300reads out a parameter or a look-up table from the external storage part (refer toFIG. 4). In an exemplary embodiment, the timing controller part and the external storage part may transmit signals using the I2C communication. In such an embodiment, the timing controller300may be a master mode device, and the external storage part may be a slave mode device.

The external storage part may be an electrically erasable programmable read only memory (“EEPROM”). The external storage part may store a plurality of look-up tables, the coefficients and various parameters used to check abnormality of the first control signal, e.g., check whether the first control signal CONT1is abnormal or not.

When the timing controller300loads the parameter or the look-up table, the timing controller300is converted from a master mode to a slave mode. That is, when a driving of the timing controller300is prepared, the I2C communication between the timing controller300and the external storage part ends.

Then, in an exemplary embodiment, the I2C communication is performed between the timing controller300and the image board100. In such an embodiment, the image board100may be in a master mode, and the timing controller300may be in a slave mode.

A signal is periodically transmitted between the serial data line SDA and the serial clock line SCL in the timing controller300and the image board100. The image board100may periodically check the abnormal driving condition of the timing controller300, e.g., whether an abnormal driving condition occurs in the timing controller300or not, through the serial data line SDA and the serial clock line SCL.

When absence of the abnormal driving condition in the timing controller300is checked, the timing controller300outputs the second image signal DATA2, the data control signal CONT2and the gate control signal CONT3for driving the display panel200. When the abnormal driving condition occurs in the timing controller300, the timing controller300does not output the signals for driving the display panel200to feed back the error condition signal FF to the image board100.

The error condition signal FF may be generated based on the first image signal DATA1and the first control signal CONT1provided from the image board100. In one exemplary embodiment, for example, the error-detecting part330compares coefficients calculated by the logic part310and the first control signal CONT1with reference data read out from the external storage part, and then the error-detecting part330generates the error condition signal FF when the coefficients and the first control signal CONT1are different from the reference data.

The error-detecting part330may include a plurality of detecting parts and a register340. In one exemplary embodiment, for example, as shown inFIG. 2, the error-detecting part330may include a first detecting part331, a second detecting part332and a third detecting part333. In such an embodiment, the error-detecting part330includes three detecting parts. In an alternative exemplary embodiment, the error-detecting part330may include two detecting parts or no less than four detecting parts.

The first to third detecting parts331,332and333may detect different types of abnormal driving condition, and thereby output the first error condition signal FF1, a second error condition signal FF2and a third error condition signal FF3, respectively.

In an exemplary embodiment, the first to third error condition signals FF1, FF2and FF3may be one of a clock error signal, a data enable error signal and a coefficient error signal. Hereinafter, for convenience of description, it will be described that the first to third error condition signals FF1, FF2and FF3will be defined as a clock error signal, a data enable error signal and a coefficient error signal, respectively.

The first detecting part331checks abnormality of a clock signal CLK, e.g., whether a clock signal CLK is an abnormal or not, and thereby outputs the clock error signal. In one exemplary embodiment, for example, when the clock signal is not applied, the first detecting part331may output the clock error signal. The clock signal CLK may be one of a main clock signal, a data clock signal and a gate clock signal. The first detecting part331compares the clock signal CLK with a reference parameter stored in the external storage part. When it is checked that the clock signal CLK is not identical to the reference parameter, the first detecting part331may output the clock error signal.

The second detecting part332checks abnormality of the data enable signal DE, e.g., whether the data enable signal DE is abnormal or not, and thereby outputs the data enable error signal. Referring toFIG. 3, when a high interval HP of the data enable signal DE is not maintained during a predetermined time, the second detecting part332may output the data enable error signal. In one exemplary embodiment, for example, when the display panel200has a resolution of 1,366×768 pixels, a maintain time of the high interval of the data enable signal DE may be a time corresponding to 1,366 pixels.

In such an embodiment, the external storage part may store a minimum value and a maximum value corresponding to a time during which the high interval HP of the data enable signal DE is to be maintained. When the maintain time of the high interval HP of the data enable signal DE is not within a range between the minimum value and the maximum value, the second detecting part332may output the data enable error signal.

In an exemplary embodiment, when a summation interval of a high interval HP and a low interval LP of the data enable signal DE is not maintained during a predetermined interval, the data enable error signal may be outputted.

In such an embodiment, the external storage part may store a minimum value and a maximum value of the summation interval. When the summation interval is not within a range between the minimum value and the maximum value, the second detecting part332may output the data enable error signal.

In an exemplary embodiment, when the data enable signal DE in a frame interval FP is not maintained during a predetermined interval, the data enable error signal may be outputted.

In such an embodiment, the external storage part may store a minimum value and a maximum value of an interval, during which the data enable signal DE is to be maintained in the frame interval FP. When a maintain time is not between the minimum value and the maximum value within the frame interval FP of the data enable signal DE, the second detecting part332may output the data enable error signal. In one exemplary embodiment, for example, when the display panel200has a resolution of 1,366×768 pixels, the data enable signal DE may have 768 pulses for the frame interval FP.

In an exemplary embodiment, when a summation interval of the frame interval FP and a blank interval BP of the data enable signal DE is not maintained during a predetermined interval, the data enable error signal may be outputted.

In such an embodiment, the external storage part may store a minimum value and a maximum value of an interval that the frame interval FP and the blank interval BP of a data enable signal DE are added together. The second detecting part332may output the data enable error signal, when an interval that the frame interval FP and the blank interval BP of the data enable signal DE are added together is not in a range between the minimum value and the maximum value.

The third detecting part333checks abnormality of coefficients calculated by the logic part301, e.g., whether coefficients calculated by the logic part310are abnormal or not, and thereby outputs the coefficient error signal. Referring toFIG. 4, the logic part310may include a first storage part311, a calculating part313and a second storage part315. The logic part310may further include an interpolating part317.

The first storage part311stores a look-up table (“LUT”) loaded from an external storage part20and the first image signal DATA1provided from the image board100. The calculating part313calculates coefficients COEF based on the LUT stored in the first storage part311and the first image signal DATA1.

The second storage part315stores the coefficients COEF calculated by the calculating part313. The coefficients COEF calculated by the calculating part313may be all coefficients or partial coefficients required for driving the display panel200. When the coefficients COEF calculated by the calculating part313are partial coefficients, the interpolating part317may calculate remaining coefficients COEF.

The coefficient COEF stored in the second storage part315may be provided to the third detecting part333. The third detecting part333may include a checksum comparison part334. The checksum comparison part334may compare a total sum value N of a sequential total sum of the calculated coefficients COEF and a checksum value CS stored in the external storage part20with a predetermined value F.

In one exemplary embodiment, for example, as shown inFIG. 5, the total sum value N has 256 addresses ADD, e.g., from 0 to 255, and the predetermined value F is calculated as a value of 252 in advance to be stored in the external storage part20. The addresses ADD and the coefficients COEF are in one-to-one (1:1) correspondence. As shown in a table ofFIG. 6, the coefficients COEF calculated at the calculating part313are arranged in accordance with the addresses ADD.

When the total sum value of the sequential total sum N of the calculated coefficients COEF and the checksum value CS stored in the external storage part20is equal to the predetermined value F, the coefficients COEF are normally calculated by the calculating part313.

When the total sum value of the sequential total sum N of the calculated coefficients COEF and the checksum value CS stored in the external storage part20is different from the predetermined value F, the coefficients COEF are abnormally calculated by the calculating part313, and the third detecting part333may output the coefficient error signal.

The register340stores the first to third error condition signals FF1, FF2and FF3outputted from the first to third detecting parts331,332and333. Then, the first to third error condition signals FF1, FF2and FF3are transmitted to the image board100, when the image board100requests the first to third error condition signals FF1, FF2and FF3. Since an I2C communication is performed between the timing controller300and the image board100with a predetermined period, information of the register340is periodically scanned.

Each of the first to third error condition signals FF1, FF2and FF3may include at least one of information on existence or nonexistence of an error condition, an error condition type, a command for the image board100corresponding to types of the error condition, and a register values for operating the image board100.

The existence or nonexistence of an error condition is information which notifies existence of an abnormal driving condition of the timing controller300. In one exemplary embodiment, for example, the existence or nonexistence of an error condition corresponds to zero (0) when a driving condition of the timing controller300is normal, and the existence or nonexistence of an error condition corresponds to 1 when a driving condition of the timing controller300is abnormal. The error condition type is information corresponding to a type of abnormal driving condition of the timing controller300. In one exemplary embodiment, for example, when data of the error condition type has 3 bits, 8 abnormal driving conditions may be identified.

The command for the image board100is information which notifies the image board100a function that the image board100should be performed in accordance with the error condition kinds. In one exemplary embodiment, for example, when the command for the image board100is 3 bits data, the number of functions of the image board100may be designated into eight. In one exemplary embodiment, for example, the command for the image board100may be a reset signal applied to the timing controller300.

The register values for operating the image board100may be inner monitoring information of the timing controller300used to perform a function of the image board100. In one exemplary embodiment, for example, the register values may be a count value of a counter which will be described in detail later.

The image board100may restore the timing controller300based on the first to third error condition signals FF1, FF2and FF3. The image board100may perform a restoration of the timing controller300based one a command included in the first to third error condition signals FF1, FF2and FF3.

The image board100applies a reset signal to the timing controller300or changes a value of coefficients COF calculated by the logic part310to restore the timing controller300.

In an exemplary embodiment, the image board100applies a new clock signal CLK to the timing controller300when the clock error signal is applied thereto, and applies a new data enable signal DE to the timing controller300when the data enable error signal is applied thereto, such that the timing controller300may be restored.

In an exemplary embodiment, the timing controller300feeds back the first to third error condition signals FF1, FF2and FF3to the image board100through an I2C communication, such that a type of the error condition may be checked by the image board100and thus suitable actions may be possible, e.g., the error condition may be effectively prevented based on the type of the error condition.

FIG. 7is a block diagram illustrating an alternative exemplary embodiment of the driving apparatus according to the present invention.

Referring toFIG. 7, the driving apparatus includes an image board100and a timing controller500. The timing controller500includes a logic part310and an error-detecting part360which includes a plurality of detecting parts, e.g., the first detecting part331, the second detecting part332and the third detecting part333, and an arithmetic part350.

The logic part310and the detecting parts331,332and333ofFIG. 7are substantially the same as the logic part310and the detecting parts331,332and333ofFIG. 2, and thus any repetitive detailed explanation thereof will hereinafter be omitted.

The first to third detecting parts331,332and333detect different types of abnormal driving condition, and thereby output a first error condition signal FF1, a second error condition signal FF2and a third error condition signal FF3, respectively. The first to third error condition signals FF1, FF2and FF3may be one of a clock error signal, a data enable error signal and a coefficient error signal.

The arithmetic part350calculates a logical disjunction of the first to third error condition signals FF1, FF2and FF3. In an exemplary embodiment, the arithmetic part350may include an OR gate. When one of the first to third error condition signals FF1, FF2and FF3is high, the arithmetic part350outputs an error condition signal FF.

The timing controller500feeds back the error condition signal FF to the image board100. The timing controller500designates one of output terminals to an output terminal of the error condition signal FF, and outputs the error condition signal FF through the output terminal of the error condition signal FF.

When the error condition signal FF is inputted to the image board100, the image board100may apply a reset signal to the timing controller500to restore the timing controller500.

In an exemplary embodiment, the error condition signal FF is outputted using an output terminal of the timing controller500, such that a restoring of the timing controller500may be effectively realized without a design change of the timing controller500.

FIG. 8is a block diagram illustrating another alternative exemplary embodiment of the driving apparatus according to the present invention.

Referring toFIG. 8, the driving apparatus30is substantially the same as the driving apparatus10ofFIG. 1except for a counter370. The same or like elements shown inFIG. 8have been labeled with the same reference characters as used above to describe the exemplary embodiments of the driving apparatus shown inFIG. 1, and thus, any repetitive detailed description thereof will hereinafter be omitted or simplified.

The driving apparatus inFIG. 8includes an image board100and a timing controller700. The timing controller700includes a logic part310, an error-detecting part330and a counter370.

The counter370counts pulses of the error condition signal FF outputted from the error-detecting part330, and records the counted number of the pulses.

Since the error condition signal FF is generated with respect to a real input of the timing controller700, the error condition signal FF may also have real time characteristics. When the abnormal driving condition is not continued and restored, the error condition signal FF is restored. That is, a temporary abnormal driving condition is not found, such that a restoration of the timing controller700may not be performed when the error condition signal FF is not maintained in a predetermined time.

The timing controller700feeds back the error condition signal FF to the image board100when the number of error condition signal FF corresponds to, e.g., identical to, a predetermined value. In one exemplary embodiment, for example, the predetermined value may be three. In such an embodiment, when a same type of abnormal driving condition is repeated no less than three times, the timing controller700feeds back the error condition signal FF to the image board100.

The error condition signal FF may be fed back to the image board100through an I2C communication. In an exemplary embodiment, one of output terminals of the timing controller500is designated as an output terminal of the error condition signal FF, and then the error condition signal FF may be fed back to the image board100through an output terminal of the error condition signal FF.

The image board100restores the timing controller700when the error condition signal FF is fed back thereto. The image board100applies a reset signal to the timing controller700, or alters coefficient values COEF calculated by the logic part310, such that the timing controller700may be restored.

In an exemplary embodiment, the image board100applies a new clock signal CLK to the timing controller700when the clock error signal is applied thereto, and applies a new data enable signal DE to the timing controller700when the data enable error signal is applied thereto, such that the timing controller700may be restored.

In an exemplary embodiment, the driving apparatus30may further include the counter370, such that the timing controller700may be restored when the error condition signal FF is maintained. Thus, a restoring efficiency of the timing controller700is substantially enhanced.

FIG. 9is a flowchart showing an exemplary embodiment of a method of restoring a timing controller shown inFIG. 1.FIG. 10is a signal timing diagram showing a restoring process of the timing controller shown inFIG. 9.

Referring toFIGS. 9 and 10, the image board100provides the timing controller300with a first image signal DATA1and a first control signal CONT1(step S100).

When a power-on signal POWER-ON is output from the image board100, the timing controller300reads out parameters and a look-up table from the external storage part (refer toFIG. 4).

When the parameters and the look-up table are loaded to the timing controller300, an I2C communication is performed between the timing controller300and the image board100. In such an embodiment, signals may be transmitted between the timing controller300and the image board100through the serial data line SDA and the serial clock line SCL with a predetermined period T.

The timing controller300checks abnormality of the first image signal DATA1and the first control signal CONT1, e.g., whether or not the first image signal DATA1and the first control signal CONT1are abnormal (step S200). The timing controller300provides the display panel200with an output signal when the first image signal DATA1and the first control signal CONT1are normal, e.g., when there is no abnormality in the first image signal DATA1and the first control signal CONT1(step S400).

The output signal of the timing controller300may be a plurality of timing signals generated based on the first control signal CONT1and a second image signal DATA2converted from the first image signal DATA1. The timing signals may include a data control signal CONT2and a gate control signal CONT3.

The display panel200displays an image based on the second image signal DATA2, the data control signal CONT2and the gate control signal CONT3that are provided from the timing controller300.

When the first image signal DATA1and the first control signal CONT1are abnormal, the timing controller300generates an error condition signal FF without providing the display panel200with an output signal (step S300).

The timing controller300includes a logic part310and an error-detecting part330. The logic part310calculates coefficients for converting the first image signal DATA1into the second image signal DATA2based on a look-up table read out from the external storage part. The second image signal DATA2is outputted to the data driving part210. The external storage part may be an EEPROM.

The error-detecting part330generates the error condition signal FF based on the first image signal DATA1and the second control signal CONT1. The error-detecting part330may compare the coefficients and the first control signal CONT1with reference data stored in the external storage part. When the coefficients and the first control signal CONT1are different from the reference data, the error-detecting part330generates the error condition signal FF.

In an exemplary embodiment, the timing controller700may further include a counter370. In such an embodiment, the counter370counts pulses of the error condition signal FF outputted from the error-detecting part330, and feeds back the error condition signal FF to the image board100when a counted number of the pulses corresponds to a predetermined number.

The error-detecting part330may include a plurality of detecting parts and a register340. At least one of the error-detecting parts330may check abnormality of a clock signal CLK, e.g., whether or not the clock signal CLK is abnormal, to output the clock error signal. In an exemplary embodiment, at least one of the error-detecting parts30may check abnormality of a data enable signal, e.g., whether or not the data enable signal DE is abnormal, to output the data enable error signal. In such an embodiment, a reference parameter for the clock signal CLK and the data enable signal DE may be stored in the external storage part.

In an exemplary embodiment, at least one of the error-detecting parts330may check abnormality of coefficients COEF calculated by the lock part310, e.g., whether or not the coefficients COEF calculated by the logic part310are abnormal, to output the coefficient error signal. In such an embodiment, the error-detecting part330may check whether or not the coefficients COEF are normally calculated using a checksum value CS stored in the external storage part.

The timing controller300feeds back an error condition signal FF to the image board100(step S500).

An error condition signal FF outputted from the plural detecting parts is stored in the register340. Since an I2C communication is performed between the timing controller300and the image board100with a predetermined period, information of the register340is periodically scanned. In an exemplary embodiment, the information of the register340may be periodically scanned by rescan signal Rscan. When an error condition is generated at ‘A’ point in the driving condition of the timing controller TCON ofFIG. 10, the timing controller700notifies an abnormal condition to the image board100through a data line SDA.

The error condition signal FF may include at least one of information on existence or nonexistence of an error condition, an error condition type, a command for the image board100corresponding to the error condition kinds, and a register value for operating the image board.

The image board100restores the timing controller300based on the error condition signal FF (step S700).

The image board100restores the timing controller300based on the first to third error condition signals FF1, FF2and FF3. The image board100may perform a restoring process of the timing controller300based on a command of the image board100, which is included in the first to third error condition signals FF1, FF2and FF3.

In an exemplary embodiment, the image board100may apply a reset signal RST to the timing controller300, as shown inFIG. 10, to restore the timing controller300. In such an embodiment, the timing controller700may be restored in a normal state at a point ‘B’ in the driving condition of the timing controller TCON as shown inFIG. 10.

In an exemplary embodiment, the image board100may alter the coefficients COEF calculated by the logic part310to restore the timing controller300. In an alternative exemplary embodiment, the image board100may apply a new clock signal CLK to the timing controller300when the clock error signal is applied thereto, and apply a new data enable signal DE to the timing controller300when the data enable error signal is applied thereto to restore the timing controller300.

In an exemplary embodiment, the error condition signal FF is fed back to the image board100through I2C communication between the timing controller300and the image board100. In an alternative exemplary embodiment, as shown inFIG. 7, the timing controller500may designate one of output terminals of the timing controller500into an output terminal of the error condition signal FF, and may output the error condition signal FF through the output terminal of the error condition signal FF.

In an exemplary embodiment, the timing controller300feeds back the first to third error condition signals FF1, FF2and FF3to the image board100through an I2C communication, such that the type of error conditions is effectively checked by the image board100and thus suitable actions may be possible, e.g., the error condition may be effectively prevented based on the checked type of the error condition.

As described above, in such an embodiment, the timing controller detects an error condition to feed back an error condition signal to an image board, and the image board restores the timing controller based on the error condition signal. Thus, display defects due to an abnormal operation of the timing controller are effectively prevented, and display quality of a display device is thereby substantially enhanced.

In an exemplary embodiment, the timing controller feeds back the first to third error condition signals to the image board through an I2C communication, such that types of error condition are checked by the image board and thus suitable actions may be possible, e.g., the error condition may be effectively prevented based on the type of the error condition.

In an alternative exemplary embodiment, an output terminal of the timing controller is designated as an output terminal of the error condition signal to output the error condition signal. In such an embodiment, a restoring of the timing controller may be easily realized without a design change of the timing controller.