Electronic device

A semiconductor structure includes a first nitride semiconductor layer; a second nitride semiconductor layer and a first conductive structure. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The first conductive structure is disposed on the second nitride semiconductor layer. The first conductive structure functions as one of a drain and a source of a transistor and one of an anode and a cathode of a diode.

BACKGROUND

1. Field of the Disclosure

The disclosure relates to an electronic device, and particularly to a group III-V electronic device.

2. Description of the Related Art

Components including direct bandgap semiconductors, for example, semiconductor components including group III-V materials or group III-V compounds (Category: III-V compounds) can operate or work under a variety of conditions or in a variety of environments (e.g., at different voltages and frequencies) due to their characteristics.

The semiconductor components may include a heterojunction bipolar transistor (HBT), a heterojunction field effect transistor (HFET), a high-electron-mobility transistor (HEMT), a modulation-doped FET (MODFET), or the like

SUMMARY

In some embodiments, a semiconductor structure includes a first nitride semiconductor layer; a second nitride semiconductor layer and a first conductive structure. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The first conductive structure is disposed on the second nitride semiconductor layer. The first conductive structure functions as one of a drain and a source of a transistor and one of an anode and a cathode of a diode.

In some embodiments, a semiconductor structure includes a first nitride semiconductor layer, a transistor and a diode. The transistor has a drain and a source on a first surface of the first nitride semiconductor layer. The diode has an anode and a cathode on the first surface of the first nitride semiconductor layer. The anode and the cathode of the diode are arranged in a direction substantially parallel to the first surface of the first nitride semiconductor layer.

DETAILED DESCRIPTION

Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.

FIG.1illustrates a schematic diagram of an electronic device1, in accordance with some embodiments of the present disclosure. The electronic device1can include a transistor T1and a diode D1.

In some embodiments, the transistor T1may be formed of or include a direct bandgap material, such as an III-V compound, which includes but is not limited to, for example, GaAs, InP, GaN, InGaAs and AlGaAs. In some embodiments, the transistor T1can include a group III nitride transistor. In some embodiments, the transistor T1can include a GaN-based transistor. In some embodiments, the transistor T1can include a high-electron-mobility transistor (HEMT). In some embodiments, the diode D1may include a Schottky diode (or Schottky barrier diode (SBD)).

The transistor T1may have a gate (G), a drain (D) and a source (S). In some embodiments, the transistor T1may be or include a “normally-off” type of transistor. For example, in operation, if a voltage (i.e., Vgs) applied between the gate and the source of the transistor T1is equal to or greater than a threshold voltage (Vth) of the transistor T1, the transistor T1can be turned on to contact a current (e.g., from the drain to the source). If the voltage (i.e., Vgs) applied between the gate and the source of the transistor T1is less than the threshold voltage (Vth) of the transistor T1, the transistor T1would be turned off. In other embodiments, the transistor T1may be or include a “normally-on” type of transistor depending on different design specifications.

As shown inFIG.1, the diode D1is connected to the transistor T1in parallel. For example, the drain of the transistor T1is electrically connected to a cathode of the diode D1, and the source of the transistor T1is electrically connected to an anode of the diode D1. In some embodiments, the electronic device1can work in a power device (e.g., a DC-DC circuit). When the electronic device1works as or in a power device, the transistor T1may be frequently switched (e.g., turn on and turn off). By connecting the diode D1with the transistor T1in parallel, the equivalent on-resistance of the electronic device1would decrease, which can reduce the power consumption of the electronic device1.

FIG.2illustrates a schematic diagram of an electronic device2, in accordance with some embodiments of the present disclosure. In some embodiments, the electronic device2as shown inFIG.2may be or include a DC-DC circuit. For example, the electronic device2as shown inFIG.2may be or include a buck converter (or a step-down converter). For example, the electronic device2can be configured to step down voltage (while stepping up current) from its input voltage Vin to its output voltage Vout. The electronic device2can include the electronic device1as illustrated inFIG.1, a transistor T2, an inductor L1, a capacitor C1, a resistor R1and a controller (or driver)21.

The controller21is connected to the gate of the transistor T1and the gate of the transistor T2. In some embodiments, the controller21is configured to transmit complementary signal to the transistors T1and T2to control on/off state of the transistors T1and T2. For example, if the signal transmitted to the transistor T1has a logical value “1,” the signal transmitted to the transistor T2would have a logical value “0,” and vice versa. For example, the controller21is configured to ensure that one of the transistors T1and T2is turned off while the other is turned on, so as to perform synchronous rectification.

The gate of the transistor T2is connected to the controller21to receive a signal from the controller21. The drain of the transistor T2is connected to receive the input voltage Vin. The source of the transistor T2is connected to the drain of the transistor T1and the inductor L1. In the case that the signal received by the gate of the transistor T2is higher than a threshold voltage of the transistor T2(e.g., the signal inputted to the transistor T2has a logical value “1”), the transistor T2is turned on to conduct current, otherwise, the transistor T2is turned off.

In some embodiments, the transistor T2may be formed of or include a direct bandgap material, such as an III-V compound, which includes but is not limited to, for example, GaAs, InP, GaN, InGaAs and AlGaAs. In some embodiments, the transistor T2can include a group III nitride transistor. In some embodiments, the transistor T2can include a GaN-based transistor. In some embodiments, the transistor T2can include a HEMT.

The gate of the transistor T1is connected to the controller21to receive another signal from the controller21, which is complementary to the signal received by the transistor T2. The drain of the transistor T1is connected to the drain of the transistor T2and the inductor L1. The source of the transistor T1is connected to ground. In the case that the signal received by the gate of the transistor T1is higher than a threshold voltage of the transistor T1(e.g., the signal inputted to the transistor T1has a logical value “1”), the transistor T1is turned on to conduct current, otherwise, the transistor T1is turned off.

The inductor L1is connected between the drain of the transistor T1or T2and the output of the electronic device2. The capacitor C1is connected between the output of the electronic device2and ground. The resistor R1is connected between the output of the electronic device2and ground.

In some embodiments, in operation, when the controller21is configured to turn on the transistor T2and to turn off the transistor T1(e.g., the electronic device2is at on-state), the transistor T2is configured to conduct current to the inductor L1, the capacitor C1and the resistor R1. When the current begins to increase, the inductor L1is configured to produce an opposing voltage across its terminals in response to the changing current. This voltage drop counteracts the input voltage Vin and therefore reduces the output voltage Vout. For example, the output voltage Vout may be substantially equal to the input voltage Vin minus the voltage drop of the inductor L1and the voltage drop (e.g., VDS) between the drain and the source of the transistor T2. Over time, the rate of change of current decreases, and the voltage across the inductor L1also decreases, which may increase the output voltage Vout. During this time, the inductor L1is configured to store energy in the form of a magnetic field. In the case that the controller21is configured to turn off the transistor T2and to turn on the transistor T1(e.g., the electronic device2is at off-state), the electronic device2is disconnected from the input voltage Vin, and the current would decrease. The decreasing current would produce a voltage drop across the inductor (opposite to the voltage drop at on-state), and the inductor L1is configured to work as a current source. The stored energy in the inductor's magnetic field supports the current flowing from the transistor T1to the output of the electronic device2through the inductor L2to make up for the reduction in the output voltage Vout.

FIG.3illustrates a cross-sectional view of a semiconductor structure3, in accordance with some embodiments of the present disclosure. In some embodiments, the electronic device1as described and illustrated with reference toFIG.1can have a similar or same the cross-sectional view of the semiconductor structure3as shown inFIG.3.

For example, the semiconductor structure3as shown inFIG.3includes a transistor T1and a diode D1connected in parallel as shown inFIG.1. The semiconductor structure3includes a substrate30, a buffer layer31, semiconductor layers32and33, an insulation layer34, a doped semiconductor layer362, conductive structures361,363,365,366,371,372,373,374,391,392,393,394, field plates381,382,383and passivation layers351,352,353,354,355,356,357,358.

The substrate30may include, for example, but is not limited to, silicon (Si), doped Si, silicon carbide (SiC) or other suitable material(s). In some embodiments, the substrate30may include a p-type semiconductor material. The substrate30may include a p-type semiconductor material having a doping concentration of about 1017atoms/cm3to about 1021atoms/cm3. The substrate30may include a p-type semiconductor material having a doping concentration of about 1019atoms/cm3to about 1021atoms/cm3. The substrate30may include a p-type semiconductor material having a doping concentration of about 1020atoms/cm3to about 1021atoms/cm3. In some embodiments, the substrate30may include a p-type doped silicon layer. In some embodiments, the substrate30may include a silicon layer doped with arsenic (As). In some embodiments, the substrate30may include a silicon layer doped with phosphorus (P). In some embodiments, the substrate30may include an n-type semiconductor material. The substrate30may include an n-type semiconductor material having a doping concentration of about 1017atoms/cm3to about 1021atoms/cm3. The substrate30may include an n-type semiconductor material having a doping concentration of about 1019atoms/cm3to about 1021atoms/cm3. The substrate30may include an n-type semiconductor material having a doping concentration of about 1020atoms/cm3to about 1021atoms/cm3. In some embodiments, the substrate30may include an n-type doped silicon layer. In some embodiments, the substrate30may include a silicon layer doped with boron (B). In some embodiments, the substrate30may include a silicon layer doped with gallium (Ga).

The buffer layer31may be disposed on the substrate30. In some embodiments, the buffer layer31may include nitrides. In some embodiments, the buffer layer31may include, for example, but is not limited to, aluminum nitride (AlN). In some embodiments, the buffer layer31may include, for example, but is not limited to, aluminum gallium nitride (AlGaN). In some embodiments, the buffer layer31may include a multilayer structure. In some other embodiments, the buffer layer31can include a single layer structure.

The semiconductor layer32may be disposed on the buffer layer31. The semiconductor layer32may include a III-V material or compound. The semiconductor layer32may include, for example, but is not limited to, a group III nitride. The semiconductor layer32may include, for example, but is not limited to, gallium nitride (GaN). The semiconductor layer32may include, for example, but is not limited to, aluminum nitride (AlN). The semiconductor layer32may include, for example, but is not limited to, indium nitride (InN). The semiconductor layer32may include, for example, but is not limited to, a compound of InxAlyGa(1-x-y)N, where x+y≤1. The semiconductor layer32may include, for example, but is not limited to, a compound of AlyGa(1-y)N, where y≤1.

The semiconductor layer33may be disposed on the semiconductor layer32. The semiconductor layer33may include, for example, but not limited to, a group III nitride. The semiconductor layer33may include, for example, but not limited to, a compound of AlyGa(1-y)N, where y≤1. The semiconductor layer33may include, for example, but is not limited to, GaN. The semiconductor layer33may include, for example, but is not limited to, AlN. The semiconductor layer33may include, for example, but is not limited to, InN. The semiconductor layer33may include, for example, but is not limited to, a compound of InxAlyGa(1-x-y)N, where x+y≤1.

A heterogeneous interface can be formed between the semiconductor layer33and the semiconductor layer32. The semiconductor layer33may have a relatively greater band gap than the semiconductor layer32. For example, the semiconductor layer33may include AlGaN, the AlGaN may have a band gap of about 4 eV, the semiconductor layer32may include GaN, and GaN may have a band gap of about 3.4 eV.

In some embodiments, the semiconductor layer32may function as or include an electron channel region (or channel layer). The channel region may include a two-dimensional electron gas (2DEG) region, which is generally available in a heterostructure. In the 2DEG region, the electron gas can move freely in a two-dimensional direction (or lateral direction), but is limited in the movement in another dimension (e.g. vertical direction). In some embodiments, the channel region can be formed within the semiconductor layer32. In some embodiments, the channel region can be formed adjacent to an interface between the semiconductor layer32and the semiconductor layer33.

In some embodiments, the semiconductor layer33may function as a barrier layer. For example, the semiconductor layer33may function as a barrier layer provided on the semiconductor layer32.

The insulation layer34is disposed on the semiconductor layer33. In some embodiments, the insulation layer34may be disposed on a portion of a top surface of the doped semiconductor layer362exposed from the conductive structure363. In some embodiments, the insulation layer34is disposed on a portion of a top surface of the conductive structure363exposed from the conductive structure375. The insulation layer34may include a dielectric material. The insulation layer34may include nitride. The insulation layer34may include, for example, but not limited to, silicon nitride (Si3N4). The insulation layer34may include oxide. The insulation layer34may include, for example, but not limited to, silicon oxide (SiO2).

The doped semiconductor layer362may be disposed on the semiconductor layer33. In some embodiments, the doped semiconductor layer362may penetrate the insulation layer34and contact a top surface of the semiconductor layer33. The doped semiconductor layer362may include a doped III-V material. In some embodiments, the doped semiconductor layer362may include a p-type III-V group material. The doped semiconductor layer362may include, for example, but not limited to, a p-type group III nitride. The doped semiconductor layer362may include, for example, but is not limited to, p-type GaN. The doped semiconductor layer362may include, for example, but is not limited to, a p-type AlN. The doped semiconductor layer362may include, for example, but is not limited to, a p-type InN. The doped semiconductor layer362may include, for example, but is not limited to, p-type AlGaN. The doped semiconductor layer362may include, for example, but is not limited to, p-type InGaN. The doped semiconductor layer362may include, for example, but is not limited to, a p-type InAlN. When the doped semiconductor layer362includes a p-type III-V group material, the doped material of the doped semiconductor layer362may include, for example, but is not limited to, at least one of Mg, Zn, and Ca.

The doped semiconductor layer362may also include other p-type semiconductor materials. The doped semiconductor layer362may include, for example, but is not limited to, p-type CuO. The doped semiconductor layer362may include, for example, but is not limited to, p-type NiOx. When the doped semiconductor layer362includes p-type CuO, the doping material of the doped semiconductor layer362may include, for example, but is not limited to, at least one of Mg, Zn, and Ca. When the doped semiconductor layer362includes p-type NiOx, the doped material of the doped semiconductor layer362may include, for example, but is not limited to, at least one of Mg, Zn, and Ca.

The doped semiconductor layer362may include a p-type semiconductor material having a doping concentration of about 1017atoms/cm3to about 1021atoms/cm3. The doped semiconductor layer362may include a p-type semiconductor material having a doping concentration of about 1019atoms/cm3to about 1021atoms/cm3. The doped semiconductor layer362may include a p-type semiconductor material having a doping concentration of about 1020atoms/cm3to about 1021atoms/cm3.

The conductive structure363may be disposed on the doped semiconductor layer362. The doped semiconductor layer362is disposed between the conductive structure363and the semiconductor layer33. In some embodiments, the conductive structure363may include metal. The conductive structure363may include, for example, but is not limited to, gold (Au), platinum (Pt), titanium (Ti), palladium (Pd), nickel (Ni), and tungsten (W). In some embodiments, the conductive structure363cmay include alloy. The conductive structure363may include, for example, but is not limited to, titanium nitride (TiN).

The conductive structure375may be disposed on the conductive structure363. The conductive structure375may serve as a through via. The conductive structure375may serve as a through via electrically connecting the conductive structure363to the outside. For example, the conductive structure375may be disposed on the passivation layer354and penetrate the passivation layers351,352,353and354to electrically connect to the conductive structure363. The conductive structure375may include metal. The conductive structure375may include a metal compound. The conductive structure375may include, for example, but not limited to, copper (Cu), tungsten (W), titanium (Ti), titanium nitride (TiN), or aluminum copper (Al—Cu).

In some embodiments, the conductive structure375(or the conductive structure363) may function as a gate (or a gate terminal) of the transistor T1. For example, the conductive structure375may be configured to control the channel region (or the 2DEG) in the semiconductor layer32. For example, the conductive structure375may be applied with a voltage to control the channel region in the semiconductor layer32. For example, the conductive structure375may be applied with a voltage to control the channel region in the semiconductor layer32and below the conductive structure375. For example, the conductive structure375may be applied with a voltage to control the conduction or control the conduction between the conductive structure361and the conductive structure365.

The conductive structure361is disposed on the semiconductor layer33. The conductive structure361may be disposed on the passivation layer352. The conductive structure361may penetrate the passivation layers351,352and the insulation layer34. The conductive structure361may conduct a top surface of the semiconductor layer33. The conductive structure361may include a metal. In some embodiments, the conductive structure361may include, for example, but not limited to, aluminum (Al), titanium (Ti), palladium (Pd), nickel (Ni), and tungsten (W). In some embodiments, the conductive structure361may include a metal alloy. The conductive structure361may include, for example, but not limited to, titanium nitride (TiN). In some embodiments, the conductive structure361may be or include a multi-layer structure. For example, the conductive structure361may include Ti, AlSi, Ti and TiN.

The conductive structure371may be disposed on the conductive structure361. The conductive structure371may serve as a through via. The conductive structure371may serve as a through via electrically connecting the conductive structure361to the outside. For example, the conductive structure371may penetrate the passivation layers353,354,355and356to electrically connect to the conductive structure361. The conductive structure371may include metal. The conductive structure371may include a metal compound. The conductive structure371may include, for example, but not limited to, copper (Cu), tungsten (W), titanium (Ti), titanium nitride (TiN), or aluminum copper (Al—Cu). In some embodiments, the conductive structure371(or the conductive structure361) may function as a source (or a source terminal) of the transistor T1.

The insulation layer364is disposed on the semiconductor layer33. The insulation layer364is disposed on the passivation layer351. In some embodiments, the insulation layer364may penetrate the passivation layer351, the insulation layer34and a portion of the semiconductor layer33. For example, the passivation layer351, the insulation layer34and a portion of the semiconductor layer33may cover a least a portion of a lateral surface (or sidewall) of the insulation layer364. In other embodiments, the insulation layer364may not extend within the semiconductor layer33. For example, a bottom surface of the insulation layer364is in contact with a top surface of the semiconductor layer33. The insulation layer364may include a dielectric material. The insulation layer364may include nitride. The insulation layer364may include, for example, but not limited to, silicon nitride (Si3N4). The insulation layer364may include oxide. The insulation layer364may include, for example, but not limited to, silicon oxide (SiO2).

The conductive structure365is disposed on the semiconductor layer33. The conductive structure365is disposed on the insulation layer364. In some embodiments, the conductive structure365may penetrate the passivation layer351, the insulation layer34and a portion of the semiconductor layer33. In other embodiments, the conductive structure365may not extend within the semiconductor layer33. For example, a bottom surface of the conductive structure365is in contact with a top surface of the semiconductor layer33. The conductive structure365may include a metal. In some embodiments, the conductive structure365may include, for example, but not limited to, titanium (Ti) and nickel (Ni). In some embodiments, the conductive structure365may include a metal alloy. The conductive structure365may include, for example, but not limited to, titanium nitride (TiN).

The conductive structure376is disposed on the conductive structure365. The conductive structure376may serve as a through via. The conductive structure376may serve as a through via electrically connecting the conductive structure365to the outside. For example, the conductive structure376may be disposed on the passivation layer354and penetrate the passivation layers352,353and354to electrically connect to the conductive structure365. The conductive structure376may include metal. The conductive structure376may include a metal compound. The conductive structure376may include, for example, but not limited to, copper (Cu), tungsten (W), titanium (Ti), titanium nitride (TiN), or aluminum copper (Al—Cu). In some embodiments, the conductive structure376(or the conductive structure365) may function as an anode of the diode D1.

In some embodiments, the conductive structure365may be disposed between the conductive structure363and the conductive structure366. For example, a distance between the conductive structure365and the conductive structure363is less than a distance between the conductive structure366and the conductive structure363. For example, the conductive structure365is closer to the conductive structure363than the conductive structure366. For example, the conductive structure366is farther from the conductive structure363than the conductive structure365.

The conductive structure366is disposed on the semiconductor layer33. The conductive structure366may be disposed on the passivation layer352. The conductive structure366may penetrate the passivation layers351,352and the insulation layer34. The conductive structure366may conduct a top surface of the semiconductor layer33. The conductive structure366may include a metal. In some embodiments, the conductive structure366may include, for example, but not limited to, aluminum (Al), titanium (Ti), palladium (Pd), nickel (Ni), and tungsten (W). In some embodiments, the conductive structure366may include a metal alloy. The conductive structure366may include, for example, but not limited to, titanium nitride (TiN). In some embodiments, the conductive structure366may be or include a multi-layer structure. For example, the conductive structure366may include Ti, AlSi, Ti and TiN.

The conductive structure373may be disposed on the conductive structure366. The conductive structure373may serve as a through via. The conductive structure373may serve as a through via electrically connecting the conductive structure366to the outside. For example, the conductive structure373may penetrate the passivation layers353,354,355and356to electrically connect to the conductive structure366. The conductive structure373may include metal. The conductive structure373may include a metal compound. The conductive structure373may include, for example, but not limited to, copper (Cu), tungsten (W), titanium (Ti), titanium nitride (TiN), or aluminum copper (Al—Cu).

In some embodiments, the conductive structure373(or the conductive structure366) may function as a drain (or a drain terminal) of the transistor T1. In some embodiments, the conductive structure373(or the conductive structure366) may function as a cathode of the diode D1. In some embodiments, the conductive structure373(or the conductive structure366) may function as both the drain of the transistor T1and the cathode of the diode D1. For example, the cathode of the diode D1and the drain of the transistor T1share an electrical contact or electrode (i.e., the conductive structure373or366).

The field plate381is disposed on the passivation layer353. The field plate381may be covered by the passivation layer354. The field plate382is disposed on the passivation layer354. The field plate382may be covered by the passivation layer355. The field plate383is disposed on the passivation layer355. The field plate382may be covered by the passivation layer356. The field plate381, the field plate382and the field plate383are not in contact with each other. The field plate381, the field plate382and the field plate383are spaced apart from each other. In some embodiments, the field plate381, the field plate382and the field plate383may be partially or fully overlapping in a direction substantially perpendicular to a top surface of the substrate30. In some embodiments, the field plate381can be at zero potential. The field plate382can be at zero potential. The field plate383can be at zero potential.

In some embodiments, the field plate381can be connected to the conductive structure371(e.g., the source terminal), the conductive structure375(e.g., the gate terminal) and/or the conductive structure373(e.g., the drain terminal) through other conductor structures. The field plate382can be connected to the conductive structure371, the conductive structure375and/or the conductive structure373through other conductor structures. The field plate383can be connected to the conductive structure371, the conductive structure375and/or the conductive structure373through other conductor structures.

The field plate381can reduce the electric field between the gate terminal (e.g., the doped semiconductor layer362) and the drain terminal (e.g., the conductive structure366). For example, the field plate381can reduce the electric field adjacent to the drain terminal. The field plate382can reduce the electric field between the gate terminal and the drain terminal. For example, the field plate382can reduce the electric field adjacent to the drain terminal. The field plate383can reduce the electric field between the gate terminal and the drain terminal. For example, the field plate383can reduce the electric field adjacent to the drain terminal.

The field plate381can allow the electric field between the conductor structures (for example, the doped semiconductor layer365and the conductive structure366) to distribute evenly, improve the tolerance to voltage, and permit the voltage to release slowly, thereby improving the reliability of the transistor T1. The field plate382can allow the electric field between the conductor structures (for example, the doped semiconductor layer365and the conductive structure366) to distribute evenly, improve the tolerance to voltage, and permit the voltage to release slowly, thereby improving the reliability of the transistor T1. The field plate383can allow the electric field between the conductor structures (for example, the doped semiconductor layer365and the conductive structure366) to distribute evenly, improve the tolerance to voltage, and permit the voltage to release slowly, thereby improving the reliability of the transistor T1.

Although the drawing of the present disclosure depicts that the semiconductor structure3has three field plates, the present disclosure is not limited thereto. In some embodiments, the semiconductor structure3may include more or less field plates.

The conductive structure391is disposed on the passivation layer356and electrically connected to the conductive structure371. The conductive structure393is disposed on the passivation layer356and electrically connected to the conductive structure373. The conductive structure391and the conductive structure393may include metal. The conductive structure391and the conductive structure393may include a metal compound. The conductive structure391and the conductive structure393may include, for example, but not limited to, copper (Cu), tungsten carbide (WC), titanium (Ti), titanium nitride (TiN), or aluminum copper (Al—Cu).

The conductive structure392is disposed on the passivation layer357and electrically connected to the conductive structure391through the conductive structure372. For example, the conductive structure372may function as a through via. The conductive structure372may penetrate the passivation layer357to electrically connect the conductive structure392with the conductive structure391. The conductive structure394is disposed on the passivation layer357and electrically connected to the conductive structure393through the conductive structure374. For example, the conductive structure374may function as a through via. The conductive structure374may penetrate the passivation layer357to electrically connect the conductive structure394with the conductive structure393. The conductive structure392and the conductive structure394may include metal. The conductive structure392and the conductive structure394may include a metal compound. The conductive structure392and the conductive structure394may include, for example, but not limited to, copper (Cu), tungsten (W), titanium (Ti), titanium nitride (TiN), or aluminum copper (Al—Cu).

The passivation layer358is disposed on the passivation layer357. The passivation layer358covers a portion of the conductive structures392and394. The passivation layer358exposes another portion of the conductive structures392and394for electrical connections. In some embodiments, the passivation layers351,352,353,354,355,356,357and358may include the same material. Alternatively, the passivation layers351,352,353,354,355,356,357and358may include different materials. The passivation layers351,352,353,354,355,356,357and358may serve as an interlayer dielectric layer. The passivation layers351,352,353,354,355,356,357and358may include a dielectric material. The passivation layers351,352,353,354,355,356,357and358may include a nitride. The passivation layers351,352,353,354,355,356,357and358may include, for example, but not limited to, silicon nitride (Si3N4). The passivation layers351,352,353,354,355,356,357and358may include an oxide. The passivation layers351,352,353,354,355,356,357and358may include, for example, but not limited to, silicon oxide (SiO2).

In some comparative embodiments, the transistor T1and the diode D1of the electronic device1as shown inFIG.1are discretely disposed on a circuit board (e.g., a printed circuit board (PCB) or a mother board) and electrically connected to each other at the package level or the circuit board level. However, the separate dies or components (e.g., the transistor T1and the diode D1) increase fabrication cost, packaging cost, area consumed on a circuit board, and result in increased parasitic inductance, capacitance and resistance due to interconnections required at the packaging level and/or the circuit board level.

In accordance with the embodiments, as shown inFIG.3, the transistor T1and the diode D1are monolithically integrated into the semiconductor structure3. For example, the diode D1and the transistor T1are integrated on a single substrate30(or on a single semiconductor layer32or33). By integrating the diode D1and the transistor T1, the size and the manufacturing cost of the semiconductor structure3can be reduced. Furthermore, as shown inFIG.3, since the cathode of the diode D1and the drain of the transistor T1share an electrical contact or electrode (i.e., the conductive structure366or373), the size and the manufacturing cost of the semiconductor structure3can be further reduced. In addition, the issues of parasitic inductance, capacitance and resistance can be mitigated.

FIG.4A,FIG.4B,FIG.4C,FIG.4D,FIG.4E,FIG.4F,FIG.4G,FIG.4H,FIG.4I,FIG.4JandFIG.4Killustrate several operations in manufacturing a semiconductor structure, in accordance with some embodiments of the present disclosure. In some embodiments, the operations illustrated inFIG.4A,FIG.4B,FIG.4C,FIG.4D,FIG.4E,FIG.4F,FIG.4G,FIG.4H,FIG.4I,FIG.4JandFIG.4Kcan be used to manufacture the semiconductor structure3as shown inFIG.3.

Referring toFIG.4A, a substrate30is provided. A buffer layer31is disposed on the substrate30. A semiconductor layer32is formed on the buffer layer31. In some embodiments, the semiconductor layer32may be formed on the buffer layer31by, for example, epitaxial growth or any other suitable operations. A semiconductor layer33is formed on the semiconductor layer32. In some embodiments, the semiconductor layer33may be formed on the semiconductor layer32by, for example, epitaxial growth or any other suitable operations.

A doped semiconductor layer362is formed on the semiconductor layer33. A conductive structure363is formed on the doped semiconductor layer362. In some embodiments, the doped semiconductor layer362and the conductive structure363may be formed on the following operations: (i) forming a doped semiconductor layer on the semiconductor layer33to fully cover the semiconductor layer33; (ii) forming a metal layer on the doped semiconductor layer to fully cover the doped semiconductor layer; and (iii) removing a portion of the doped semiconductor layer and the metal layer to form the doped semiconductor layer362and the conductive structure363as shown inFIG.4A.

In some embodiments, in operation (i), the doped semiconductor layer can be formed by epitaxial growth by metal organic chemical vapor deposition (MOCVD), and a dopant is doped therein. In some embodiments, in operation (ii), the metal layer can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), plating, and/or other suitable deposition steps. In some embodiments, the metal layer is formed in a Gate First process, that is, before the source (e.g., the conductive structure361) and the drain (e.g., the conductive structure366) are formed.

In some embodiments, in operation (iii), a patterned hard mask is disposed over the metal layer. The doped semiconductor layer362and the conductive structure363can then be formed by etching a portion of the metal layer and the doped semiconductor layer. In some embodiments, the etching operation may include dry etching, wet etching, or a combination of dry and wet etching. In some embodiments, the patterned hard mask may include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), or the like. In some embodiments, the etchant for etching the metal layer may be or include aqueous ammonia (NH4OH), hydrogen peroxide (H2O2), sulfuric acid (H2SO4), hydrofluoric acid (HF), ammonium fluoride (NH4F), or a mixture of the foregoing compounds.

Referring toFIG.4B, an insulation layer34is formed on the semiconductor layer33. In some embodiments, the insulation layer34may be formed on a portion of a top surface of the doped semiconductor layer362exposed from the conductive structure363. In some embodiments, the insulation layer34is formed on a top surface of the conductive structure363. In some embodiments, the insulation layer may be formed by a deposition or any other suitable operations.

Referring toFIG.4C, a passivation layer351is formed to cover the insulation layer34, the conductive structure363and the doped semiconductor layer362. In some embodiments, the passivation layer351may be formed by, CVD, high density plasma (HDP) CVD, spin-on, sputtering, or any other suitable operations. A portion of the passivation layer351and a portion of the insulation layer34are then removed to form an opening351h(or a hole or a recess) to expose a portion of the semiconductor layer33. In some embodiments, a portion of the semiconductor layer33may be removed as shown inFIG.4C. In some embodiments, the opening351hmay be formed by etching or any other suitable operations.

Referring toFIG.4D, an insulation layer49is formed on the passivation layer351. The insulation layer49is further formed within the opening351hand on a portion of the semiconductor layer33exposed from the passivation layer351. Then, a portion of the insulation layer49is removed to form an opening49h. In some embodiments, the portion of the insulation layer49may be removed by etching or any other suitable operations.

Referring toFIG.4E, a metal layer is formed on the insulation layer49and within the opening49h. A portion of the metal layer and the insulation layer49is then removed to form the insulation layer364and the conductive structure365as shown inFIG.4E. In some embodiments, the portion of the metal layer and the insulation layer49may be removed by etching or any other suitable operations.

Referring toFIG.4F, a passivation layer352is formed on the passivation layer351. The passivation layer352covers the conductive structure365. In some embodiments, the passivation layer352may be formed by, CVD, HDP CVD, spin-on, sputtering, or any other suitable operations. A portion of the passivation layers351,352and the insulation layer34is removed to form openings to expose a portion of a top surface of the semiconductor layer33. The conductive structures361and366are respectively formed within the openings to contact the portion of the top surface of the semiconductor layer33. In some embodiments, the conductive structures361and366may be formed by deposition operations, such as CVD, PVD, electroplating or any other suitable operations. In some embodiments, the conductive structures361and362form an intermetallic compound with the semiconductor layer33through rapid thermal anneal (RTA), thereby forming an Ohmic contact to the channel region within the semiconductor layer32.

Referring toFIG.4G, a passivation layer353is formed on the passivation layer352. The passivation layer353covers a portion of the conductive structures361and366. In some embodiments, the passivation layer353may be formed by, CVD, HDP CVD, spin-on, sputtering, or any other suitable operations. A field plate381is then formed on the passivation layer353. In some embodiments, the field plate381may be formed by depositing a conductor material, depositing a metal by sputtering, and then patterning by dry etching.

Referring toFIG.4H, a passivation layer354is formed on the passivation layer353. The passivation layer354covers the field plate381. In some embodiments, the passivation layer354may be formed by, CVD, HDP CVD, spin-on, sputtering, or any other suitable operations. A field plate382is then formed on the passivation layer354. In some embodiments, the field plate382may be formed by depositing a conductor material, depositing a metal by sputtering, and then patterning by dry etching.

A portion of the passivation layers351,352,353and354is removed to form openings to expose a portion of a top surface of each of the conductive structures363and365. The conductive structures375and376are then respectively formed within the openings to contact the portion of the top surface of the conductive structures363and365. In some embodiments, the conductive structures375and376may be formed by deposition operations, such as CVD, PVD, electroplating or any other suitable operations.

Referring toFIG.4I, a passivation layer355is formed on the passivation layer354. The passivation layer355covers the field plate382and a portion of the conductive structures375and376. In some embodiments, the passivation layer355may be formed by, CVD, HDP CVD, spin-on, sputtering, or any other suitable operations. A field plate383is then formed on the passivation layer355. In some embodiments, the field plate383may be formed by depositing a conductor material, depositing a metal by sputtering, and then patterning by dry etching.

Referring toFIG.4J, a passivation layer356is formed on the passivation layer355. The passivation layer356covers the field plate383. In some embodiments, the passivation layer356may be formed by, CVD, HDP CVD, spin-on, sputtering, or any other suitable operations.

A portion of the passivation layers353,354,355and356is removed to form openings to expose a portion of a top surface of each of the conductive structures361and366. The conductive structures371and373are then respectively formed within the openings to contact the portion of the top surface of the conductive structures361and366. Conductive structures391and393are then formed on the passivation layer356and respectively contact the conductive structures371and373. In some embodiments, the conductive structures371,373,391and393may be formed by deposition operations, such as CVD, PVD, electroplating or any other suitable operations.

Referring toFIG.4K, a passivation layer357is formed on the passivation layer356. The passivation layer357covers the conductive structures391and392. In some embodiments, the passivation layer357may be formed by, CVD, HDP CVD, spin-on, sputtering, or any other suitable operations.

A portion of the passivation layer357is removed to form openings to expose a portion of a top surface of each of the conductive structures391and393. The conductive structures372and374are then respectively formed within the openings to contact the portion of the top surface of the conductive structures391and393. Conductive structures392and394are then formed on the passivation layer357and respectively contact the conductive structures372and374. In some embodiments, the conductive structures372,374,392and394may be formed by deposition operations, such as CVD, PVD, electroplating or any other suitable operations.

A passivation layer358is formed on the passivation layer357. The passivation layer358covers the conductive structures392and394. In some embodiments, the passivation layer358may be formed by, CVD, HDP CVD, spin-on, sputtering, or any other suitable operations. A portion of the passivation layer358is then removed to form openings to expose a portion of a top surface of each of the conductive structures392and394for electrical connections.

As used herein, the terms “approximately”, “substantially”, “substantial” and “about” are used to describe and account for small variations. When used in conduction with an event or circumstance, the terms can refer to instances in which the event of circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise. The term “substantially coplanar” can refer to two surfaces within micrometers (μm) of lying along a same plane, such as within 10 within 5 within or within 0.5 μm of lying along the same plane. When referring to numerical values or characteristics as “substantially” the same, the term can refer to the values lying within ±10%, ±5%, ±1%, or ±0.5% of an average of the values.

The foregoing outlines features of several embodiments and detailed aspects of the present disclosure. The embodiments described in the present disclosure may be readily used as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or achieving the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure.