Electric power conversion device and electric power conversion system

In a control unit for drive-controlling a switching element unit of each power conversion device, a voltage correction amount calculation unit calculates a correction amount corresponding to voltage drop due to impedance between the switching element unit and filter reactor. A voltage command correcting unit corrects a voltage command generated by the voltage command generation unit, using the correction amount. Thus, for a power conversion device 21 that has a small output impedance, correction is performed so as to increase the output impedance, and a PLL unit changes the frequency in accordance with active power calculated from output voltage and output current of the power conversion device, so as to uniform power allocations.

TECHNICAL FIELD

The present invention relates to a power conversion device and a power conversion system, and in particular, relates to technology of parallel operation control in which a plurality of power conversion devices are operated in parallel while load allocations to the plurality of power conversion devices are uniformed.

BACKGROUND ART

In a power conversion system in which a plurality of power conversion devices are driven in parallel to supply powers to a load, there is variation among the output impedances in manufacturing of the power conversion devices even if the power conversion devices have the same specifications. Therefore, variation also occurs in load allocations at the time of load inrush, due to the variation among the output impedances.

In order to suppress occurrence of variation in load allocations as described above, there is a conventional method in which, when a plurality of power conversion devices are operated while being connected in parallel, each power conversion device adjusts, in accordance with an active component of its own output current or its own output active power, a reference phase of output voltage so as to reduce the active component of its own output current or its own output active power. It is noted that a synchronous generator also has such a droop characteristic and the droop characteristic is one of characteristics in parallel operations of a plurality of power generators in a power grid.

For example, Patent Document 1 discloses the following parallel operation system. A plurality of power conversion devices each adjust a reference phase of its own output voltage and the amplitude of output voltage in accordance with its own output current, thereby balancing output powers of the power conversion devices performing parallel operations. Further, a resistance is assumed to be provided in series between a load and a harmonic filter connected to the output end of each power conversion device, voltage drop due to the virtual resistance is calculated from the output current, and the voltage drop is subtracted from a voltage command, whereby resonance among the power conversion devices is suppressed. Thus, even if the line impedances between the load and the respective power conversion devices are different, equal allocation for a nonlinear load such as a rectifier load can be performed and each power conversion device can stably perform parallel operation.

Patent Document 2 discloses that, in a complex power generation system such as a micro-grid, each power conversion device is regarded as a power generator having an internal electromotive voltage command and an impedance, and a plurality of power conversion devices each adjust a reference phase of its own output voltage in accordance with its own output active power, and adjust the internal electromotive voltage command in accordance with its own output reactive power, thereby balancing output powers of the power conversion devices performing parallel operations. Further, the power conversion devices have current control, and when a virtual internal impedance is connected between a power supply of measured voltage and a power supply of internal electromotive voltage, the value of current flowing through the internal impedance is outputted as a command value for output current.

CITATION LIST

Patent Document

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

In the parallel operation system of the power conversion devices disclosed in Patent Document 1 above, since the droop characteristic between active current and a phase is used, each power conversion device needs to detect an active component of its own output current. In general, in order to detect an active component of output current, it is necessary to compare the output current with a sine-wave signal as a reference. Thus, in Patent Document 1, the active component of output current is detected through comparison between output current and a reference phase of output voltage.

However, a time period of one cycle or longer of output voltage is needed for detecting the active component of output current. Therefore, there is a problem that it is impossible to uniform output powers of the power conversion devices when instantaneous power change occurs due to load variation or the like.

That is, when instantaneous power change occurs due to load variation or the like, the allocation is determined in accordance with the output impedance of each power conversion device. Therefore, due to variation in the output impedances of the respective power conversion devices, variation also occurs in instantaneous power allocations. Then, if the output powers cannot be balanced, power allocation to the power conversion device having a small output impedance becomes too great so that the device might be stopped, for example.

In the parallel operation system of the power conversion devices disclosed in Patent Document 2, since a droop characteristic between active power and a phase is used, each power conversion device needs to detect its own output active power. Also in this case, a time period of one cycle or more of output voltage is needed for detecting output active power. Therefore, as in Patent Document 1, there is a problem that it is impossible to uniform output powers of the power conversion devices when instantaneous power change occurs.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a power conversion device and a power conversion system in which, while a plurality of power conversion devices are driven in parallel to supply powers to a load, allocated powers can be uniformed even when instantaneous power change occurs.

Solution to the Problems

A power conversion device according to the present invention includes a switching element unit for converting voltage of a DC power supply connected externally, to voltage corresponding to a voltage command, to supply AC power to a load, and the power conversion device includes: a filter reactor and a filter capacitor for smoothing output of the switching element unit; an output reactor provided between the load and the filter capacitor; a reactor current detection unit for detecting reactor current flowing through the filter reactor; an output voltage detection unit for detecting output voltage of the power conversion device; an output current detection unit for detecting current flowing through the output reactor, as output current; and a control unit for drive-controlling the switching element unit on the basis of detection outputs from the reactor current detection unit, the output voltage detection unit, and the output current detection unit. The control unit includes a voltage command generation unit for generating the voltage command for controlling the output voltage of the power conversion device, a PWM signal generation unit for generating a PWM signal for driving the switching element unit, on the basis of the voltage command, and a PLL unit for changing a frequency of the output voltage in accordance with active power calculated on the basis of the output voltage and the output current. The control unit further includes a voltage correction amount calculation unit for calculating a voltage command correction amount on the basis of the reactor current, and a voltage command correcting unit which corrects the voltage command in accordance with the voltage command correction amount and outputs the corrected voltage command to the PWM signal generation unit.

A power conversion system according to the present invention includes a plurality of the above power conversion devices, and the plurality of power conversion devices are operated in parallel to supply AC power to the load.

Effect of the Invention

In the power conversion device according to the present invention, the voltage command correction amount is calculated on the basis of the reactor current, to correct the voltage command, and thus the output impedance of the power conversion device can be adjusted in accordance with the reactor current. In the case where a plurality of power conversion devices are operated in parallel to supply powers to a load, variation among the output impedances due to variation among the impedances of the filter reactors of the power conversion devices is suppressed. Thus, even when instantaneous power change occurs, concentration of power allocation is prevented and power allocations to the power conversion devices can be improved to be uniformed.

In addition, in the power conversion system in which the plurality of power conversion devices are operated in parallel to supply powers to a load, as described above, variation among the output impedances of the power conversion devices is suppressed, and thus, when instantaneous power change occurs, output powers of the power conversion devices can be uniformed, and stable control with high reliability can be achieved.

DESCRIPTION OF EMBODIMENTS

FIG. 1is a configuration diagram showing an entire power conversion system according to embodiment 1 of the present invention.

The power conversion system in the present embodiment 1 has a configuration in which two power conversion devices21a,21bperform parallel operations, and DC voltages are supplied from the DC power supply60to the respective power conversion devices21a,21b. The outputs of the two power conversion devices21a,21bare synthesized to be supplied to an AC load61.

Here, the DC power supply60is used in common for the two power conversion devices21a,21b. However, as shown inFIG. 2, DC power supplies60a,60bmay be connected individually to the respective power conversion devices21a,21b. In addition, here, the power conversion devices21a,21bequally supply AC powers to the AC load61.

In the power conversion system of the present embodiment 1, the number of the power conversion devices21a,21bperforming parallel operations is two. However, in the present invention, the number of the power conversion devices performing parallel operations is not limited to two, but may be three or more. Although only two power conversion devices21a,21bperform parallel operations, in the present invention, it is possible to perform parallel operations with a device having a droop characteristic of a frequency with respect to output power such as a power generator.

FIG. 3is a diagram showing the configuration of a power conversion device applied to the power conversion system inFIG. 1andFIG. 2. Here, the power conversion devices21a,21bshown inFIG. 1andFIG. 2basically have the same configuration. Therefore, unless the respective power conversion devices21a,21bare specifically discriminated, they are collectively denoted by reference character21, i.e., referred to as power conversion devices21.

As shown inFIG. 3, the power conversion device21includes a bus capacitor200, a switching element unit2, a filter reactor3, a filter capacitor4, an output reactor5, a reactor current detection unit6, an output voltage detection unit7, an output current detection unit8, a control unit10, an input terminal1, and an output terminal9.

The bus capacitor200is connected in parallel between the input terminal1and the switching element unit2, and the other side of the switching element unit2is connected to the filter reactor3. The filter reactor3and the output reactor5are connected in series between the switching element unit2and the output terminal9, and the filter capacitor4is connected in parallel between the filter reactor3and the output reactor5.

For the bus capacitor200, the capacitance value may be selected so that voltage of the bus capacitor200does not become smaller than predetermined voltage when output of the power conversion device21is sharply changed. Here, the predetermined voltage is voltage of the bus capacitor200that allows the power conversion device21to output normal voltage (for example, if output voltage of the power conversion device21is 200 Vrms, the predetermined voltage is about 283 V, which is the amplitude of the output voltage).

For the filter reactor3and the filter capacitor4, the inductance value and the capacitance value may be selected so that harmonic components of voltage pulsed by the switching element unit2on the basis of voltage of the external DC power supply60are reduced so as to obtain a voltage signal having a predetermined frequency component. Here, the predetermined frequency component is in a frequency range (for example, 50 Hz or 60 Hz) of a power grid. For the output reactor5, the capacitance value may be selected so as to suppress harmonic components of output current of the power conversion device21. Here, harmonic components are components having approximately a frequency at which the switching element unit2performs switching operation.

The reactor current detection unit6is connected between the switching element unit2and the filter reactor3and detects current flowing through the filter reactor3. The output voltage detection unit7is for detecting voltage outputted from the power conversion device21, and inFIG. 3, is connected in parallel with the filter capacitor4. In this case, with voltage drop due to the output reactor5regarded as small, voltage of the filter capacitor4is considered to be the voltage outputted from the power conversion device21. The output current detection unit8is for detecting current outputted from the power conversion device21, and inFIG. 3, is connected between the filter capacitor4and the output reactor5and detects current flowing through the output reactor5as the output current.

It is noted that, since the reactor current detection unit6is for detecting current flowing through the filter reactor3, the reactor current detection unit6may be connected between the filter reactor3and the filter capacitor4. In addition, since the output current detection unit8is for detecting current outputted from the power conversion device21, the output current detection unit8may be connected between the output reactor5and the output terminal9.

Further, the output voltage detection unit7may be connected on the output terminal9side of the output reactor5.

InFIG. 3, IL is reactor current (hereinafter, referred to as reactor current IL, reactor current, or IL as appropriate) detected by the reactor current detection unit6, Vc is output voltage (hereinafter, referred to as output voltage Vc, output voltage, or Vc as appropriate) detected by the output voltage detection unit7, Io is output current (hereinafter, referred to as output current Io, output current, or Io as appropriate) detected by the output current detection unit8, S1and S2are PWM signals outputted from a PWM (Pulse Width Modulation) signal generation unit14, φ is an internal phase outputted from a PLL unit15, VL* denotes a correction amount outputted from a voltage correction amount calculation unit12, Vref is a voltage command outputted from a voltage command generation unit11, and Vref* is a corrected voltage command outputted from a voltage command correcting unit13. Hereinafter, the details of each part composing the power conversion device21will be described.

The switching element unit2converts voltage of the external DC power supply60connected to the input terminal1, to voltage corresponding to the voltage command.

The switching element unit2is formed as a single-phase inverter composed of four semiconductor switching elements201to204so as to have a full-bridge configuration, in which a first leg and a second leg are connected in parallel. The first leg is formed by connecting the semiconductor switching element201of an upper arm and the semiconductor switching element202of a lower arm in series to each other, and the second leg is formed by connecting the semiconductor switching element203of an upper arm and the semiconductor switching element204of a lower arm in series to each other. As the semiconductor switching elements201to204, for example, IGBTs or MOSFETs to which diodes are connected in antiparallel are used.

The semiconductor switching elements201to204are turned on or off in accordance with PWM signals S1, S2outputted from the control unit10, thereby deforming voltage of the DC power supply60inputted from the input terminal1, into a pulse shape. Specifically, the semiconductor switching elements201,204are turned on or off by the PWM signal S1, and the semiconductor switching elements202,203are turned on or off by the PWM signal S2.

Here, the case where the switching element unit2is formed as a single-phase inverter and supplies power to a single-phase AC load61is shown. However, the switching element unit2may be formed as a three-phase inverter and supply three-phase AC power to a three-phase AC load.

The pulse voltage outputted from the switching element unit2passes through the filter reactor3, the filter capacitor4, and the output reactor5provided between the switching element unit2and the output terminal9, so as to be formed in a sine waveform.

The control unit10receives the detection signals IL, Vc, Io from the detection units6,7,8and outputs PWM signals S1, S2for drive-controlling the switching element unit2. The control unit10includes the voltage command generation unit11, the voltage correction amount calculation unit12, the voltage command correcting unit13, the PWM signal generation unit14, and the PLL (Phase Locked Loop) unit15. In this case, the internal configuration of the control unit10may be implemented by hardware or may be implemented by software. Further, the internal configuration of the control unit10may be implemented by a combination of hardware and software. Hereinafter, the details of each part composing the control unit10will be specifically described. Here, the case of generating PWM signals by bipolar modulation will be described. However, without limitation thereto, another PWM signal generation method using unipolar modulation or the like may be used.

FIG. 4is a block diagram showing the internal configuration of the voltage command generation unit11included in the control unit10.

The voltage command generation unit11receives output voltage Vc, output current Io, and an internal phase φ, and outputs a voltage command Vref for controlling output voltage Vc of the power conversion device21. The voltage command generation unit11includes an effective voltage commander30, an effective value calculator (RMS)31, a subtractor32, a voltage controller33, a multiplier34, a gain (K)300, a sine-wave generator (SIN)301, a cosine-wave generator (COS)302, and an adder303.

The voltage command generation unit11is for correcting a steady voltage effective value variation due to the filter reactor3, the output reactor5, and the voltage correction amount calculation unit12. In addition, for cross current of reactive power due to voltage amplitude error between the power conversion devices21, the voltage command generation unit11also has a function of adjusting the voltage amplitude so as to suppress the cross current of the reactive power.

InFIG. 4, Vr* is an effective voltage command outputted from the effective voltage commander30, and Vcrms is a voltage effective value outputted from the effective value calculator31and corresponds to the effective value of output voltage Vc. In addition, ΔVrms is an error of the voltage effective value Vcrms from the effective voltage command Vr*, ΔVr* is a control quantity outputted from the voltage controller33, Vrefrms is the effective value of the voltage command Vref, and Va is the amplitude of the voltage command Vref.

The sine-wave generator301receives the internal phase φ and outputs a sine wave sin φ. The cosine-wave generator302receives the internal phase φ and outputs a cosine wave cos φ.

The effective voltage commander30receives the output current Io, the output voltage Vc, the sine wave sin φ, and the cosine wave cos φ, and outputs the effective voltage command Vr* as a control target for output voltage Vc of the power conversion device21.

The effective value calculator31receives output voltage Vc and outputs the voltage effective value Vcrms of output voltage Vc.

The subtractor32subtracts the voltage effective value Vcrms outputted from the effective value calculator31, from the effective voltage command Vr*, thereby outputting an error ΔVrms (=Vr*−Vcrms).

The voltage controller33receives the error ΔVrms and performs control calculation so that the error ΔVrms approaches 0, thereby outputting the control quantity ΔVr*. The voltage controller33is for correcting the effective value of voltage outputted from the power conversion device21, and specifically, corrects error of the output voltage effective value that occurs due to voltage drop of the filter reactor3. In this case, the voltage controller33corrects voltage error in a steady state when a sufficient time period has elapsed since sharp load change, in order to control the effective value of voltage outputted from the power conversion device21.

The voltage controller33is configured to perform proportional control or configured by connecting proportional control and a low-pass filter in series, for example. If the voltage controller33has an integral element, when the plurality of power conversion devices21perform parallel operations and different detection errors are superimposed on the output voltage detection units7of the respective power conversion devices21, the error ΔVrms inputted to the voltage controller33of each power conversion device21does not converge to 0 and the integral value of the voltage controller33might continue to increase. Therefore, if the voltage controller33employs the control configuration that does not include the integral element as described above, the control error due to the integral element is eliminated.

The adder303sums the effective voltage command Vr* from the effective voltage commander30and the control quantity ΔVr* from the voltage controller33, to correct the effective voltage command Vr*, thereby outputting the effective value Vrefrms of the voltage command Vref (Vrefrms=Vr*+ΔV*).

The gain300receives the effective value Vrefrms of the voltage command Vref and multiplies the effective value Vrefrms by √2 which is a gain for conversion to voltage amplitude, thereby outputting an amplitude Va of the voltage command Vref (Va=Vrefrms×√2).

The multiplier34multiplies the amplitude Va and the sine wave sin φ, thereby outputting the voltage command Vref.

FIG. 5is a block diagram showing the internal configuration of the effective voltage commander30included in the voltage command generation unit11. It is noted that a “fundamental wave” which is used as appropriate in the following description refers to a component having the same frequency as the frequency of the internal phase φ of the power conversion device21(for example, reactive power of a fundamental wave refers to reactive power of a component having the same frequency as that of the internal phase φ).

As described above, the effective voltage commander30receives the output current Io, the output voltage Vc, the sine wave sin φ, and the cosine wave cos φ, and outputs the effective voltage command Vr* for output voltage Vc of the power conversion device21.

The effective voltage commander30includes a reactive power calculator320, a droop characteristic calculator321, a reference voltage commander322, and an adder323.

InFIG. 5, Q is fundamental wave reactive power, Vr is a reference effective value which is the effective value of reference voltage, and ΔVr is a correction amount for the reference effective value Vr. It is noted that the reference effective value Vr is the effective value of reference voltage which is common between the plurality of power conversion devices21operated in parallel, and as the reference effective value Vr, a common constant value is given to the plurality of power conversion devices21.

The reactive power calculator320receives the output current Io, the output voltage Vc, the cosine wave cos φ, and the sine wave sin φ, and outputs the fundamental wave reactive power Q outputted from the power conversion device21. The fundamental wave reactive power Q is reactive power of a component having the frequency of the internal phase φ and contained in output of the power conversion device21. In calculation of the fundamental wave reactive power Q, it suffices that the polarity and the magnitude of reactive power having a specific frequency can be calculated. Here, as shown by the following Expression (1), the fundamental wave reactive power Q is calculated from a result of discrete Fourier transform of output voltage Vc and output current Io with respect to the internal phase φ component.

Here, Tvc is the cycle of output voltage Vc, Tc is the calculation cycle, m is the number of calculations in which processing with a calculation cycle of Tc is performed during the cycle Tvc, n is a calculation number counted from zero-crossing of Vc (1 corresponds to the oldest value, m corresponds to the latest value, and n corresponds to the present value), Vcn is the present value of output voltage Vc, Ion is the present value of output current Io, φn is the present internal phase, Vc sin is a fundamental sine-wave effective value component of Vc, Vc cos is a fundamental cosine-wave effective value component of Vc, Io sin is a fundamental sine-wave effective value component of Io, and Io cos is a fundamental cosine-wave effective value component of Io. As for the fundamental wave reactive power Q, the polarity when the power conversion device21outputs reactive power with a leading phase is defined as positive.

The droop characteristic calculator321receives the fundamental wave reactive power Q, and calculates and outputs the correction amount ΔVr so as to reduce the fundamental wave reactive power Q outputted from the power conversion device21. Specifically, a value obtained by multiplying the fundamental wave reactive power Q by a gain Kq becomes the correction amount ΔVr (ΔVr=Q×Kq).

Here, in the case where the gain Kg is set so that a correction amount ΔVr of 0.05 p.u. is outputted relative to fundamental wave reactive power Q of 1 p.u., this state is equivalent to a state in which a reactance (inductance) component corresponding to 0.05 p.u. relative to the fundamental wave component is connected between the switching element unit2(including inside) and the output terminal9.

For example, in the case of power conversion device with 200 Vrms and rating of 1 kVA, the gain Kq is set at 0.01 Vrms/Var (200 Vrms×0.05 p.u./(1 kVA×1 p.u.)=0.01 Vrms/Var). Thus, the correction amount ΔVr is outputted so as to cause voltage drop equivalent to that caused when a reactance of 2Ω (200 Vrms×200 Vrms×0.05 p.u./1 kVA=2Ω) is connected between the switching element unit2(including inside) and the filter capacitor4.

Therefore, in the case where the plurality of power conversion devices21are operated in parallel, if cross current of fundamental wave reactive power between the power conversion devices21is great, the gain Kq is set to be great. Thus, voltage error between the power conversion devices21reduces, so that cross current of fundamental wave reactive power can be reduced. In the case where allocations of fundamental wave reactive power to the power conversion devices21are different due to the wiring impedance or the like of each power conversion device21, the gain Kq may be adjusted for each power conversion device21. The gain Kq may be set considering the above circumstances.

The reference voltage commander322outputs the reference effective value Vr. As described above, in the case where the plurality of power conversion devices21perform parallel operations, the reference effective value Vr is the same for all the power conversion devices21.

The adder323adds the correction amount ΔVr to the reference effective value Vr, thereby outputting the effective voltage command Vr* (Vr*=Vr*+ΔVr).

When the plurality of power conversion devices21perform parallel operations, if the voltage amplitude of the fundamental wave component of output voltage Vc varies between the power conversion devices21, error voltage due to the variation is applied to the output reactor5and current due to the error voltage flows between the power conversion devices21. In particular, the error voltage due to error of the voltage amplitude is mainly constituted of a sine-wave component, and therefore sine-wave component voltage is applied to the output reactor5, so that cosine-wave component current flows between the power conversion devices21. That is, in terms of power, reactive power flows as cross current between the power conversion devices21.

In the present embodiment, as described above, the effective voltage commander30includes the droop characteristic calculator321and thereby generates the effective voltage command Vr* having a droop characteristic with respect to the fundamental wave reactive power Q so as to reduce the fundamental wave reactive power Q. As shown inFIG. 6, the effective voltage command Vr* is obtained by adding a droop characteristic (correction amount ΔVr) with respect to the fundamental wave reactive power Q, to the reference effective value Vr.

FIG. 7is a block diagram showing the internal configuration of the reactive power calculator320included in the effective voltage commander30.

The reactive power calculator320receives the output current Io, the output voltage Vc, the sine wave sin φ, and the cosine wave cos φ, calculates the fundamental wave reactive power Q through calculation shown by the above Expression (1), and outputs the fundamental wave reactive power Q.

The reactive power calculator320includes a zero-cross signal output device360, a signal delaying device361, a fixed signal output device362, an integrator363, a sampling-and-holding device364, a sine-wave voltage measuring device365, a cosine wave voltage measuring device366, a sine-wave current measuring device367, a cosine wave current measuring device368, multipliers369,370, and a subtractor371. In the following description regarding signals, positive and negative signals are used. However, Hi and Lo signals may be used, for example.

InFIG. 7, Sz is a zero-cross signal, and Szd is a delayed zero-cross signal.

The zero-cross signal output device360receives output voltage Vc. Then, if the output voltage Vc is positive, the zero-cross signal output device360outputs a positive zero-cross signal Sz, and if the output voltage Vc is negative, the zero-cross signal output device360outputs a negative zero-cross signal Sz. At this time, due to variation in the output voltage Vc, zero-crossing might be detected a plurality of times within a short time period (for example, shorter than 5 ms) (chattering). As measures for such chattering, after zero-crossing is detected, detection of zero-crossing may be masked (the zero-cross signal Sz may be prevented from changing) during a certain time period (for example, 5 ms). In addition, hysteresis may be provided for the positive/negative determination of output voltage Vc (for example, when output voltage Vc is 1 V or higher, output voltage Vc may be determined to be positive, and when output voltage Vc is −1 V or lower, output voltage Vc may be determined to be negative).

The signal delaying device361receives the zero-cross signal Sz and outputs the delayed zero-cross signal Szd which is delayed by a signal corresponding to one calculation step of the reactive power calculator320. The signal delaying device361provides a delay between the signal (zero-cross signal Sz) for sampling and holding, and a signal (delayed zero-cross signal Szd) for resetting the integrator. Thus, the order of sampling-and-holding operation performed in accordance with the zero-cross signal Sz and operation of resetting the integrator is ensured.

The fixed signal output device362outputs a fixed value that is a signal value “1”. This signal is accumulated by the integrator363, to obtain an elapsed time of measurement of the cycle of output voltage Vc.

The integrator363receives output of the fixed signal output device362and the delayed zero-cross signal Szd, and outputs a cycle measurement value of output voltage Vc obtained by integrating output of the fixed signal output device362. When the delayed zero-cross signal Szd changes from negative to positive, the integrator363resets the integral value to 0 and integrates output of the fixed signal output device362. In the integration, a value obtained by multiplying a calculation step period by output of the fixed signal output device362is accumulated every calculation step. Thus, output of the integrator363becomes an elapsed time since the timing at which the delayed zero-cross signal Szd changed from negative to positive.

The sampling-and-holding device364receives output of the integrator363and the zero-cross signal Sz, and outputs the cycle Tvc of output voltage Vc. The sampling-and-holding device364updates output of the sampling-and-holding device364to output of the integrator363at a timing at which the zero-cross signal Sz changes from negative to positive. Output of the sampling-and-holding device364does not change at the other timings. Through this operation, a cycle with which output voltage Vc changes from negative to positive can be measured.

The sine-wave voltage measuring device365receives the output voltage Vc, the sine wave sin φ, the cycle Tvc of output voltage Vc, the zero-cross signal Sz, and the delayed zero-cross signal Szd, and calculates a sine wave sin φ component of the output voltage Vc, thereby outputting the fundamental sine-wave effective value component Vc sin of output voltage Vc.

The cosine wave voltage measuring device366receives the output voltage Vc, the cosine wave cos φ, the cycle Tvc of output voltage Vc, the zero-cross signal Sz, and the delayed zero-cross signal Szd, and calculates a cosine wave cos (component of the output voltage Vc, thereby outputting the fundamental cosine-wave effective value component Vc cos of output voltage Vc.

The sine-wave current measuring device367receives the output current Io, the sine wave sin φ, the cycle Tvc of output voltage Vc, the zero-cross signal Sz, and the delayed zero-cross signal Szd, and calculates a sine wave sin φ component of the output current Io, thereby outputting the fundamental sine-wave effective value component Io sin of output current Io.

The cosine wave current measuring device368receives the output current Io, the cosine wave cos φ, the cycle Tvc of the output voltage Vc, the zero-cross signal Sz, and the delayed zero-cross signal Szd, and calculates a cosine wave cos φ component of the output current Io, thereby outputting the fundamental cosine-wave effective value component Io cos of output current Io.

The multiplier369receives the fundamental cosine-wave effective value component Vc cos of output voltage Vc and the fundamental sine-wave effective value component Io sin of output current Io, and outputs a result (Vc cos×Io sin) of multiplication of these values. In addition, the multiplier370receives the fundamental sine-wave effective value component Vc sin of output voltage Vc and the fundamental cosine-wave effective value component Io cos of output current Io, and outputs a result (Vc sin×Io cos) of multiplication of these values. Further, the subtractor371subtracts output of the multiplier369from output of the multiplier370, that is, outputs the fundamental wave reactive power Q through calculation shown by the above Expression (1).

FIG. 8is a block diagram showing the internal configuration of the sine-wave voltage measuring device365included in the reactive power calculator320.

The sine-wave voltage measuring device365receives the output voltage Vc, the sine wave sin φ, the cycle Tvc of output voltage Vc, the zero-cross signal Sz, and the delayed zero-cross signal Szd, and performs calculation of Vc sin shown in the above Expression (1), thereby outputting the fundamental sine-wave effective value component Vc sin of output voltage Vc.

The sine-wave voltage measuring device365includes a multiplier380, an integrator381, a sampling-and-holding device382, a divider383, and a gain384.

The multiplier380receives the output voltage Vc and the sine wave sin φ, and outputs a result (Vc×sin φ) of multiplication of these values.

The integrator381receives output of the multiplier380and the delayed zero-cross signal Szd, and outputs a value obtained by accumulating output of the multiplier380. Here, the integrator381accumulates a value obtained by multiplying a calculation step period by output of the multiplier380, every calculation step, and the integral value thereof is reset at a timing at which the delayed zero-cross signal Szd changes from negative to positive.

The sampling-and-holding device392receives output of the integrator381and the zero-cross signal Sz, and updates output of the sampling-and-holding device392to output of the integrator381at a timing at which the zero-cross signal Sz changes from negative to positive. Output of the sampling-and-holding device392does not change at the other timings.

The divider383receives output of the sampling-and-holding device392and the cycle Tvc of output voltage Vc, and outputs a result of dividing output of the sampling-and-holding device392by the cycle Tvc of output voltage Vc. For the divider383, a lower limit value may be set for the cycle Tvc of output voltage Vc so as to prevent division by 0 when the cycle Tvc of output voltage Vc is 0.

The gain384receives output of the divider383and multiplies output of the divider383by √2, thereby outputting the fundamental sine-wave effective value component Vc sin.

FIG. 9is a block diagram showing the internal configuration of the cosine wave voltage measuring device366included in the reactive power calculator320.

The cosine wave voltage measuring device366receives the output voltage Vc, the cosine wave cos φ, the cycle Tvc of output voltage Vc, the zero-cross signal Sz, and the delayed zero-cross signal Szd, and performs calculation of Vc cos shown in the above Expression (1), thereby outputting the fundamental cosine-wave effective value component Vc cos of output voltage Vc.

The cosine wave voltage measuring device366includes a multiplier390, an integrator391, a sampling-and-holding device392, a divider393, and a gain394.

It is noted that the calculation of the fundamental cosine-wave effective value component Vc cos is the same as calculation obtained by changing, to cos φ, the input sin φ in the calculation of the fundamental sine-wave effective value component Vc sin described inFIG. 8. Therefore, the description thereof is omitted.

FIG. 10is a block diagram showing the internal configuration of the sine-wave current measuring device367included in the reactive power calculator320.

The sine-wave current measuring device367receives the output current Io, the sine wave sin φ, the cycle Tvc of output voltage Vc, the zero-cross signal Sz, and the delayed zero-cross signal Szd, and performs calculation of Io sin shown in the above Expression (1), thereby outputting the fundamental sine-wave effective value component Io sin of output current Io.

The sine-wave current measuring device367includes a multiplier400, an integrator401, a sampling-and-holding device402, a divider403, and a gain404.

It is noted that the calculation of the fundamental sine-wave effective value component Io sin is the same as calculation obtained by changing, to Io, the input Vc in the calculation of the fundamental sine-wave effective value component Vc sin of output voltage Vc described inFIG. 8. Therefore, the description thereof is omitted.

FIG. 11is a block diagram showing the internal configuration of the cosine wave current measuring device368included in the reactive power calculator320.

The cosine wave current measuring device368receives the output current Io, the cosine wave cos φ, the cycle Tvc of output voltage Vc, the zero-cross signal Sz, and the delayed zero-cross signal Szd, and performs calculation of Io cos shown in the above Expression (1), thereby outputting the fundamental cosine-wave effective value component Io cos of output current Io.

The cosine wave current measuring device368includes a multiplier410, an integrator411, a sampling-and-holding device412, a divider413, and a gain414.

It is noted that the calculation of the fundamental cosine-wave effective value component Io cos is the same as calculation obtained by changing, to Io, the input Vc in the calculation of the fundamental cosine-wave effective value component Vc cos of output voltage Vc described inFIG. 9. Therefore, the description thereof is omitted.

FIG. 12is a block diagram showing the internal configuration of the effective value calculator31included in the voltage command generation unit11.

The effective value calculator31receives output voltage Vc and outputs the voltage effective value Vcrms of output voltage Vc. The effective value calculator31includes a zero-cross signal output device340, a multiplier341, integrators342,345, sampling-and-holding devices343,346, a fixed signal output device344, a signal delaying device347, a divider348, and a square-root device349.

The effective value calculator31performs calculation of the voltage effective value Vcrms as shown by the following Expression (2).

Here, Tvc is the cycle of output voltage Vc, Tc is the calculation cycle, m is the number of calculations in which processing with a calculation cycle of Tc is performed during the cycle Tvc, n is a calculation number counted from zero-crossing of Vc (1 corresponds to the oldest value, m corresponds to the latest value, and n corresponds to the present value), and Vcn is the present value of output voltage Vc.

The zero-cross signal output device340receives the output voltage Vc. Then, if the output voltage Vc is positive, the zero-cross signal output device340outputs a positive zero-cross signal Sz, and if the output voltage Vc is negative, the zero-cross signal output device340outputs a negative zero-cross signal Sz. At this time, due to variation in the output voltage Vc, zero-crossing might be detected a plurality of times within a short time period (for example, shorter than 5 ms) (chattering). As measures for such chattering, after zero-crossing is detected, detection of zero-crossing may be masked (the zero-cross signal Sz may be prevented from changing) during a certain time period (for example, 5 ms). In addition, hysteresis may be provided for the positive/negative determination of output voltage Vc (for example, when output voltage Vc is 1 V or higher, output voltage Vc may be determined to be positive, and when output voltage Vc is −1 V or lower, output voltage Vc may be determined to be negative).

The signal delaying device347receives the zero-cross signal Sz and outputs the delayed zero-cross signal Szd which is delayed by a signal corresponding to one calculation step of the effective value calculator31. The signal delaying device347provides a delay between the signal (zero-cross signal Sz) for sampling and holding, and a signal (delayed zero-cross signal Szd) for resetting the integrator. Thus, the order of integrator-output sampling-and-holding operation performed in accordance with the zero-cross signal Sz and operation of resetting the integrator is ensured.

The fixed signal output device344outputs a fixed value that is a signal value “1”. This signal is accumulated by the integrator345, to obtain an elapsed time of measurement of the cycle of output voltage Vc.

The integrator345receives output of the fixed signal output device344and the delayed zero-cross signal Szd, and outputs a cycle measurement value of output voltage Vc obtained by integrating output of the fixed signal output device344. When the delayed zero-cross signal Szd changes from negative to positive, the integrator345resets the integral value to 0 and integrates output of the fixed signal output device344. In the integration, a value obtained by multiplying a calculation step period by output of the fixed signal output device344is accumulated every calculation step. Thus, output of the integrator345becomes an elapsed time since the timing at which the delayed zero-cross signal Szd changed from negative to positive.

The sampling-and-holding device346receives output of the integrator345and the zero-cross signal Sz, and outputs the cycle Tvc of output voltage Vc. The sampling-and-holding device346updates output of the sampling-and-holding device346to output of the integrator345at a timing at which the zero-cross signal Sz changes from negative to positive. Output of the sampling-and-holding device346does not change at the other timings. Through this operation, a cycle with which output voltage Vc changes from negative to positive can be measured.

The multiplier341receives the output voltage Vc and outputs the square (Vc×Vc) of the output voltage Vc.

The integrator342receives output of the multiplier341and the delayed zero-cross signal Szd, and outputs a value obtained by accumulating output of the multiplier341. Here, the integrator342accumulates a value obtained by multiplying a calculation step period by output of the multiplier341, every calculation step, and the integral value thereof is reset at a timing at which the delayed zero-cross signal Szd changes from negative to positive.

The sampling-and-holding device343receives output of the integrator342and the zero-cross signal Sz, and updates output of the sampling-and-holding device343to output of the integrator342at a timing at which the zero-cross signal Sz changes from negative to positive. Output of the sampling-and-holding device343does not change at the other timings.

The divider348receives output of the sampling-and-holding device343and the cycle Tvc of output voltage Vc, and outputs a result of dividing output of the sampling-and-holding device343by the cycle Tvc of output voltage Vc.

For the divider348, a lower limit value may be set for the cycle Tvc of output voltage Vc so as to prevent division by 0 when the cycle Tvc of output voltage Vc is 0.

The square-root device349receives output of the divider348and calculates the square root of output of the divider348, thereby outputting the voltage effective value Vcrms of output voltage Vc.

The divider348is to output a real number, and if output of the divider348is equal to or smaller than 0, output of the square-root device349becomes an imaginary number. Therefore, a lower limit value (for example, lower limit value is 0) may be set for input of the divider348.

FIG. 13is a block diagram showing the internal configuration of the voltage controller33included in the voltage command generation unit11.

The voltage controller33receives the error ΔVrms obtained by subtracting the voltage effective value Vcrms from the effective voltage command Vr*, and outputs the control quantity ΔVr* so that the error ΔVrms approaches 0.

The voltage controller33includes a proportional gain (Kp)420, an integral gain (Ki)421, an integrator422, limiters423,424, and an adder425.

As described above, the voltage controller33corrects the effective value of voltage outputted from the power conversion device21, and specifically, corrects an error of the output voltage effective value that occurs due to voltage drop of the filter reactor3.

The proportional gain420and the integral gain421of the voltage controller33may be set so as to stabilize operation of the voltage controller33and obtain a desired response. The limiters423,424may be set to be greater than a voltage variation width assumed in the power conversion device21. The limiter423and the limiter424may be set to the same value. For example, in the case where the output voltage range of the power conversion device21is 180 Vrms to 220 Vrms with a rating of 200 Vrms and the voltage variation thereof is in a range of −20 Vrms to 20 Vrms, the limiters423,424are set so as to output values in a range of −30 Vrms to 30 Vrms.

Here, an example in which the voltage controller33is configured as a PI controller is shown, but the voltage controller33is not limited thereto. For example, the voltage controller33may be configured as a proportional controller or configured by connecting a proportional controller and a low-pass filter in series.

The proportional gain420receives the error ΔVrms and outputs a result (ΔVrms×Kp) obtained by multiplying the error ΔVrms by a proportional gain Kp.

The integral gain421receives the error ΔVrms and outputs a result (ΔVrms×Ki) obtained by multiplying the error ΔVrms by an integral gain Ki.

The integrator422receives output of the integral gain421, accumulates a value obtained by multiplying a calculation step period by output of the integral gain421, every calculation step, and outputs a result of the integration. Although not shown, the cumulative value of the integrator422is limited by an upper limit value or a lower limit value of the limiter423connected at a stage subsequent to the integrator422.

The limiter423has an upper limit value and a lower limit value, and receives output of the integrator422. If the received value is greater than the upper limit value of the limiter423, the limiter423outputs the upper limit value, and if the received value is smaller than the lower limit value, the limiter423outputs the lower limit value. In the other cases, the limiter423outputs the received value.

The adder425receives output of the proportional gain420and output of the limiter423, and outputs a result of adding these received values.

The limiter424has an upper limit value and a lower limit value, and receives output of the adder425. If the received value is greater than the upper limit value of the limiter424, the limiter424outputs the upper limit value, and if the received value is smaller than the lower limit value, the limiter424outputs the lower limit value. In the other cases, the limiter424outputs the received value.

Returning toFIG. 3, the voltage correction amount calculation unit12calculates the correction amount VL* for the voltage command Vref generated by the voltage command generation unit11, on the basis of reactor current IL detected by the reactor current detection unit6. The correction amount VL* for the voltage command corresponds to a phenomenon that voltage drop due to impedance occurs between the switching element unit2and the filter reactor3. An example of calculation of the correction amount VL* for the voltage command by the voltage correction amount calculation unit12is shown by the following Expression (3).

Here, VL* is a voltage command correction amount calculated by the voltage correction amount calculation unit12, IL is reactor current detected by the reactor current detection unit6, Lset is an inductance component gain, and Rset is a resistance component gain.

Specifically, as shown inFIG. 14, operation is performed such that a virtual resistance Rset and a virtual inductance Lset are present inside the switching element unit2of the power conversion device21(21a,21b). Thus, the above Expression (3) represents voltage drop in the case where the inductance Lset and the resistance Rset are connected in series and current IL flows. The first term on the right-hand side of Expression (3) corresponds to voltage drop in the inductance Lset and the second term on the right-hand side of Expression (3) corresponds to voltage drop in the resistance Rset.

Here, description will be given under the assumption that the virtual resistance Rset and the virtual inductance Lset are present inside the switching element unit2of the power conversion device21. However, without limitation thereto, the same applies even if it is assumed that the virtual resistance Rset and the virtual inductance Lset are present between the switching element unit2and the filter reactor3of the power conversion device21.

The resistance component gain Rset may be selected so as to prevent resonance of the filter reactor3, the filter capacitor4, and the virtual inductance due to the inductance component gain Lset. In addition, the resistance component gain Rset may be selected so that DC current outputted from the power conversion device21can be reduced.

If the inductance of the filter reactor3is sufficiently greater than that of the output reactor5(for example, the inductance of the output reactor5is 10 uH and the inductance of the filter reactor3is 1 mH), the inductance component gain Lset may be selected so as to reduce variation among the filter reactors3.

For example, in the case where the power conversion device21aand the power conversion device21bperform parallel operations, it is assumed that the inductance design value of the filter reactor3is 1 mH, whereas the inductance of the filter reactor3of the power conversion device21ais 1.2 mH (deviation of 20%) and the inductance of the filter reactor3of the power conversion device21bis 0.8 mH (deviation of −20%). In this case, at the time of load inrush or the like, current allocation (power allocation) to the power conversion device21bis about 1.5 times current allocation (power allocation) to the power conversion device21a. Here, if the inductance component gain Lset is set at 0.001, it appears that an inductance of 1 mH is connected inside the switching element unit2of the power conversion devices21a,21b. Thus, at the time of load inrush or the like, current allocation (power allocation) to the power conversion device21bis improved to be about 1.22 times current allocation (power allocation) to the power conversion device21a.

In this case, the inductance component gains Lset of the power conversion device21aand the power conversion device21bare both set at 0.001, but the inductance component gain Lset and the resistance component gain Rset can be set individually for each of the power conversion devices21a,21b.

As a method for differentiating the reactor current IL in the above Expression (3), for example, a method of calculating a difference between the previous value and the latest value, a method using a high-pass filter, or a method of calculating the slope by a least squares method, may be employed. As the reactor current IL in the above Expression (3), a value that has passed through a filter may be used, or a moving average value may be used. It is noted that the second term on the right-hand side of the above Expression (3) serves to prevent resonance of the filter reactor3and the filter capacitor4.

The voltage command correcting unit13corrects the voltage command Vref outputted from the voltage command generation unit11, in accordance with the correction amount VL* obtained by the voltage correction amount calculation unit12, and outputs the corrected voltage command Vref* obtained by the correction, to the next PWM signal generation unit14. An example of calculation of the corrected voltage command Vref* by the voltage command correcting unit13is shown by the following Expression (4).

This Expression (4) corresponds toFIG. 14, and each switching element unit2is to output voltage corresponding to the corrected voltage command Vref* obtained by subtracting the correction amount VL* from the voltage command Vref. This is apparently equivalent to a state in which a power supply according to the voltage command Vref, and the virtual resistance Rset and the virtual inductance Lset that cause voltage drop corresponding to the correction amount VL*, are connected in series inside the switching element unit2.

As described above, the voltage correction amount calculation unit12calculates the correction amount VL* corresponding to voltage drop due to impedance between the switching element unit2and the filter reactor3. Then, the voltage command correcting unit13corrects the voltage command Vref outputted from the voltage command generation unit11, using the correction amount VL*. Thus, it is possible to increase the output impedance of the power conversion device21in accordance with increase in reactor current IL. That is, in the case where the plurality of power conversion devices21perform parallel operations, correction is to be performed so as to increase the output impedance for the power conversion device21that has a small output impedance depending on saturation of the filter reactor3by load current concentration, and variation among the impedances of the filter reactor3. Thus, it is possible to prevent concentration of power allocation (current allocation).

Furthermore, since the correction amount VL* for the voltage command calculated by the voltage correction amount calculation unit12is also calculated with a cycle equal to or shorter than the cycle of output voltage Vc, it is possible to balance output powers of the respective power conversion devices21(221a,22b), even when instantaneous power change occurs due to variation of the AC load61or the like.

FIG. 15is a block diagram showing the internal configuration of the PWM signal generation unit14included in the control unit10.

The PWM signal generation unit14generates a PWM signal on the basis of the corrected voltage command Vref* from the voltage command correcting unit13and a carrier signal Scarr, and includes a carrier signal generator40for generating the carrier signal Scarr, a comparator41, and an inverting device42. For the purpose of simplification, a short-circuit prevention time (dead time) for the switching legs, which would be set in general, is not considered.

FIG. 16is a timing chart illustrating operation of the PWM signal generation unit14.

InFIG. 16, the carrier signal Scarr is an output signal from the carrier signal generator40, and the switching signal S1and S2are PWM signals outputted from the PWM signal generation unit14to the switching element unit2. Hereinafter, a process for generating the PWM signals will be described with reference toFIG. 15andFIG. 16.

The carrier signal generator40generates a triangular wave according to a carrier cycle. Here, the carrier signal Scarr is a triangular wave, but may be a saw-tooth wave or the like. The comparator41compares the corrected voltage command Vref* with the carrier signal Scarr from the carrier signal generator40. If the command Vref* is greater than the signal Scarr, the comparator41outputs an ON signal, and if the command Vref* is smaller than the signal Scarr, the comparator41outputs an OFF signal.

One of the output signals from the comparator41becomes the switching (PWM) signal S1. The inverting device42inverts the inputted switching (PWM) signal S1between an ON signal and an OFF signal, and outputs the resultant signal. Thus, the output signal from the inverting device42becomes the other switching (PWM) signal S2.

Here, it has been described that the carrier signal Scarr from the carrier signal generator40and the corrected voltage command Vref* are compared to generate the switching (PWM) signals S1, S2. However, in a configuration having means for detecting voltage of the input terminal1, the corrected voltage command Vref* may be normalized using the detected voltage.

FIG. 17is a block diagram showing the internal configuration of the PLL unit15included in the control unit10.

The PLL unit15receives the output voltage Vc and the output current Io and outputs the internal phase φ. The PLL unit15changes the frequency of output voltage Vc in accordance with active power P calculated from the output voltage Vc and the output current Io, and includes an active power calculator50, a droop characteristic calculator51, a change limiter52, a reference frequency command unit53, a subtractor54, and a phase generator55.

InFIG. 17, P is active power, df is a frequency correction command, dfa is a limited frequency correction command, fref is a reference frequency command, and fref* is a frequency command.

In the case where the plurality of power conversion devices21perform parallel operations, the PLL unit15corrects a phase difference between output voltages Vc of the respective power conversion devices21. Error voltage occurring due to the phase difference between output voltages Vc of the respective power conversion devices21is mainly constituted of a cosine wave component. Thus, error voltage that is a cosine wave component is applied to the output reactor5, and current determined by the error voltage and the impedance of the output reactor5flows between the power conversion devices21. Since the current flowing between the power conversion devices21is mainly constituted of a sine-wave component, cross current of active power occurs between the respective power conversion devices21. Therefore, the PLL unit15can suppress cross current of active power by detecting active power outputted from the power conversion device21and adjusting the frequency of the power conversion device21.

The active power calculator50calculates active power P from the output voltage Vc detected by the output voltage detection unit7and the output current Io detected by the output current detection unit8. As a specific method for calculating the active power, the average of a product (=Vc×Io) of output voltage Vc and output current Io over the cycle of the output voltage Vc is calculated. The product (=Vc×Io) of output voltage Vc and output current Io may be subjected to filter processing by a low-pass filter or the like.

The droop characteristic calculator51calculates the frequency correction command df in accordance with the active power P calculated by the active power calculator50. The relationship between the frequency correction command df and the active power P is shown by the following Expression (5).

Here, Kf is a droop characteristic gain.

It is noted that, here, the frequency correction command df is calculated to be proportional to the active power P, but the frequency correction command df may be calculated by applying a filter to the active power P. Further, the frequency correction command df may be calculated by using also a differential element of the active power P. In the case where the power conversion devices21performing parallel operations have different power capacities and the proportion of active power P to be allocated is adjusted for each power conversion device21, the droop characteristic gain Kf may be adjusted in accordance with the proportion of active power P to be allocated. Besides, it is also possible to adjust active power to be allotted to each power conversion device21, by setting a power command offset for the active power P.

The change limiter52receives the frequency correction command df outputted from the droop characteristic calculator51, and outputs a frequency correction command dfa obtained by limiting change in the frequency correction command df. The significance of providing this change limiter52will be described below.

In the power conversion system configured as shown inFIG. 1, it is conceivable that the power conversion devices21(21a,21b) operate in cooperation with another power conversion device (not shown) that converts power of a distributed power supply such as a photovoltaic generator to commercial power.

Such a power conversion device for a distributed power supply has an isolated operation detection function. Determination as to the isolated operation detection is performed on the basis of change in the frequency of the grid voltage interconnected with the power conversion device. Therefore, in the case where the power conversion devices21of the present embodiment operate in cooperation with a separately provided power conversion device for a distributed power supply, there is a possibility that the power conversion device for the distributed power supply erroneously detects isolated operation on the basis of change in the frequency due to the frequency correction command df and operation is stopped. Therefore, as means for preventing erroneous detection of isolated operation, the change limiter52is set for the frequency correction command df.

In some of power conversion devices for distributed power supplies, a Fault Ride Through system is applied in order to prevent all the devices from being paralleled off when disturbance occurs in a power grid due to instantaneous voltage reduction or instantaneous electric outage of the power grid. In such a power conversion device to which a Fault Ride Through system is applied, it is necessary to continue operation when a ramp-shape frequency change of 2 Hz/s occurs. Therefore, it is effective that the upper limit value of the change limiter52is set at 2 Hz/s or lower and the lower limit value thereof is set at −2 Hz/s or higher.

In the future, it is conceivable that requirements for a power conversion device for a distributed power supply will change depending on power supply-and-demand circumstances of a power grid. In this case, it is effective that the upper limit value and the lower limit value of the change limiter52are set in accordance with requirements for the power conversion device for a distributed power supply.

The reference frequency command unit53outputs the reference frequency command fref as a frequency control target for output voltage Vc of the power conversion device21. It is noted that the reference frequency command fref is set to a common value between the power conversion devices21.

The subtractor54subtracts the limited frequency correction command dfa from the reference frequency command fref outputted from the reference frequency command unit53, and outputs the value fref* (=fref−dfa) obtained by the subtraction, as a frequency command.

The phase generator55accumulates the frequency command fref* outputted from the subtractor54, thereby generating the internal phase φ of voltage Vc outputted from the power conversion device21.

As described above, the PLL unit15operates so that the frequency command fref* has a droop characteristic in accordance with active power outputted from the power conversion device21, and the frequency command fref* changes as shown inFIG. 18. Specifically, when the power conversion device21outputs positive active power P to the output terminal9side, the frequency command fref* is decreased, and when the power conversion device21outputs negative active power P to the output terminal9side, the frequency command fref* is increased.

FIG. 19is a block diagram showing the internal configuration of the active power calculator50included in the PLL unit15.

The active power calculator50receives output voltage Vc and output current Io, and performs calculation shown by the following Expression (6), thereby outputting active power P.

Here, Tvc is the cycle of output voltage Vc, Tc is the calculation cycle, m is the number of calculations in which processing with a calculation cycle of Tc is performed during the cycle Tvc, n is a calculation number counted from zero-crossing of Vc (1 corresponds to the oldest value, m corresponds to the latest value, and n corresponds to the present value), Vcn is the present value of output voltage Vc, and Ion is the present value of output current Io.

The active power calculator50includes a zero-cross signal output device520, a signal delaying device521, a multiplier522, integrators523,526, sampling-and-holding devices524,527, a fixed signal output device525, and a divider528.

InFIG. 19, Sz is a zero-cross signal and Szd is a delayed zero-cross signal.

The zero-cross signal output device520receives output voltage Vc. Then, if the output voltage Vc is positive, the zero-cross signal output device520outputs a positive zero-cross signal Sz, and if the output voltage Vc is negative, the zero-cross signal output device520outputs a negative zero-cross signal Sz. At this time, due to variation in the output voltage Vc, zero-crossing might be detected a plurality of times within a short time period (for example, shorter than 5 ms) (chattering). As measures for such chattering, after zero-crossing is detected, detection of zero-crossing may be masked (the zero-cross signal Sz may be prevented from changing) during a certain time period (for example, 5 ms). In addition, hysteresis may be provided for the positive/negative determination of output voltage Vc (for example, when output voltage Vc is 1 V or higher, output voltage Vc may be determined to be positive, and when output voltage Vc is −1 V or lower, output voltage Vc may be determined to be negative).

The signal delaying device521receives the zero-cross signal Sz and outputs the delayed zero-cross signal Szd which is delayed by a signal corresponding to one calculation step of the active power calculator50. The signal delaying device521provides a delay between the signal (zero-cross signal Sz) for sampling and holding, and a signal (delayed zero-cross signal Szd) for resetting the integrator. Thus, the order of integrator-output sampling-and-holding operation performed in accordance with the zero-cross signal Sz and operation of resetting the integrator is ensured.

The fixed signal output device525outputs a fixed value that is a signal value “1”. This signal is accumulated by the integrator526, to obtain an elapsed time of measurement of the cycle of output voltage Vc.

The integrator526receives output of the fixed signal output device525and the delayed zero-cross signal Szd, and outputs a cycle measurement value of output voltage Vc obtained by integrating output of the fixed signal output device525. When the delayed zero-cross signal Szd changes from negative to positive, the integrator526resets the integral value to 0 and integrates output of the fixed signal output device525. The integrator526accumulates a value obtained by multiplying a calculation step period by output of the fixed signal output device525, every calculation step. Thus, output of the integrator526becomes an elapsed time since the timing at which the delayed zero-cross signal Szd changed from negative to positive.

The sampling-and-holding device527receives output of the integrator526and the zero-cross signal Sz, and outputs the cycle Tvc of output voltage Vc. The sampling-and-holding device527updates output of the sampling-and-holding device527to output of the integrator526at a timing at which the zero-cross signal Sz changes from negative to positive. Output of the sampling-and-holding device527does not change at the other timings. Through this operation, a cycle with which output voltage Vc changes from negative to positive can be measured.

The multiplier522receives the output voltage Vc and the output current Io, and outputs a result (Vc×Io) of multiplication of these values.

The integrator523receives output of the multiplier522and the delayed zero-cross signal Szd, and outputs a value obtained by accumulating output of the multiplier522. Here, the integrator523accumulates a value obtained by multiplying a calculation step period by output of the multiplier522, every calculation step, and the integral value thereof is reset at a timing at which the delayed zero-cross signal Szd changes from negative to positive.

The sampling-and-holding device524receives output of the integrator523and the zero-cross signal Sz, and updates output of the sampling-and-holding device524to output of the integrator523at a timing at which the zero-cross signal Sz changes from negative to positive. Output of the sampling-and-holding device524does not change at the other timings.

The divider528receives output of the sampling-and-holding device524and the cycle Tvc of output voltage Vc, and outputs a result of dividing output of the sampling-and-holding device524by the cycle Tvc of output voltage Vc. For the divider528, a lower limit value may be set for the cycle Tvc of output voltage Vc so as to prevent division by 0 when the cycle Tvc of output voltage Vc is 0.

FIG. 20is a block diagram showing the internal configuration of the change limiter52included in the PLL unit15.

The change limiter52receives the frequency correction command df and outputs the limited frequency correction command dfa, thus providing limitation on change in the frequency correction command df per calculation step of the PLL unit15.

The change limiter52includes a subtractor540, a limiter541, an adder542, and a signal delaying device543.

The subtractor540receives the frequency correction command df and output of the signal delaying device543corresponding to the previous frequency correction command, and outputs the subtraction result thereof (frequency correction command df−previous frequency correction command). The subtraction result becomes a change amount per calculation step of the frequency correction command df (calculation step by PLL unit15).

The limiter541outputs a value obtained by limiting the change amount per calculation step of the frequency correction command df, outputted from the subtractor540. The frequency change to be limited can be set using the upper limit value and the lower limit value of the limiter541. For example, in the case of limiting change in the frequency correction command df within ±2 Hz/s, the upper limit value of the limiter541is to be set at 2×(calculation step period of PLL unit15) and the lower limit value of the limiter541is to be set at −2×(calculation step period of PLL unit15).

The adder542receives output of the limiter541and output of the signal delaying device543, and outputs the limited frequency correction command dfa which is a result of adding these received values. The limited frequency correction command dfa is inputted to the signal delaying device543, and a value obtained by delaying the input by one calculation step of the PLL unit15is outputted from the signal delaying device543. This output corresponds to the previous frequency correction command.

FIG. 21is a timing chart illustrating parallel operations of the respective power conversion devices21a,21bin the power conversion system according to the present embodiment.FIG. 22is a timing chart illustrating parallel operations of two power conversion devices A, B in a power conversion system in which the two power conversion devices A, B perform parallel operations, as a comparative example.

In the power conversion devices A, B in the comparative example, the voltage correction amount calculation unit12and the voltage command correcting unit13according to the present embodiment are not provided, and the voltage command Vref generated by the voltage command generation unit11is used for generation of PWM signals, without being corrected. The other configurations are the same as those of the power conversion devices21(21a,21b).

FIG. 21andFIG. 22show load currents (current waveforms of AC loads), output currents flowing through the power conversion devices21a, A (waveforms of currents flowing through output reactors), and output currents flowing through the other power conversion devices21b, B (waveforms of currents flowing through output reactors). It is noted that, normally, each load current is the sum of output currents of the two power conversion devices performing parallel operations.

Here, for the purpose of showing the effects of the present embodiment, in both cases ofFIG. 21andFIG. 22, the inductance components of the filter reactors3of the power conversion devices21b, B are set to be smaller than the inductance components of the filter reactors3of the power conversion devices21a, A.

AlthoughFIG. 21andFIG. 22show waveforms in single-phase configurations, the present invention is not limited to a single-phase configuration but is applicable to a three-phase configuration.

First, the comparative example shown inFIG. 22will be described.

In comparison between output current of the power conversion device A and output current of the power conversion device B, load current allocation is biased to the power conversion device B at the time of applying a load. This is because the inductance components of the filter reactors3are different between the two power conversion devices A, B. That is, since the inductance component of the filter reactor3of the power conversion device B is smaller than the inductance component of the filter reactor3of the power conversion device A, the impedance of the power conversion device B is smaller and current allocation to the power conversion device B becomes greater. As a result, instantaneous power allocation thereto also becomes greater.

Thereafter, allocations of output currents of both power conversion devices A, B are improved to be equalized, as time elapses. The reason therefor will be described below. The reference frequency command fref is corrected by the frequency correction command df from the droop characteristic calculator51included in the PLL unit15of each power conversion device A, B. Thus, a voltage phase difference occurs between the switching element unit2side end of the filter reactor3and the filter capacitor4side end of the filter reactor3. Currents of the filter reactors3of the respective power conversion devices A, B are adjusted in accordance with the voltage phase difference, and thus powers are uniformly allocated to the respective power conversion devices A, B in a steady state.

As described above, in parallel operations of the power conversion devices A, B in the comparative example, it is difficult to uniform current allocations when instantaneous power change occurs at the time of, for example, applying a load.

Next, an example of parallel operations of the power conversion devices21a,21baccording to the present embodiment, shown inFIG. 21, will be described.

In comparison between output current of the power conversion device21aand output current of the power conversion device21b, bias of current is corrected at the time of applying a load. This is because error in the inductance component of the filter reactor3as described above is corrected by the voltage correction amount calculation unit12and the voltage command correcting unit13included in each power conversion device21a,21b.

As time elapses, allocations of output currents of both power conversion devices21a,21bare improved to be equalized. The reason therefor is the same as described inFIG. 22. That is, the reference frequency command fref is corrected by the frequency correction command df from the droop characteristic calculator51included in the PLL unit15of each power conversion device21a,21b. Thus, a voltage phase difference occurs between the switching element unit2side end of the filter reactor3and the filter capacitor4side end of the filter reactor3. Currents of the filter reactors3of the respective power conversion devices21a,21bare adjusted in accordance with the voltage phase difference, and thus powers are uniformly allocated to the respective power conversion devices21a,21bin a steady state.

As described above, in the present embodiment 1, in the case where the plurality of power conversion devices21a,21bare driven in parallel to supply powers to the AC load61, the voltage correction amount calculation unit12calculates the correction amount VL* corresponding to voltage drop due to the impedance between the switching element unit2and the filter reactor3composing each power conversion device21a,21b, and the voltage command correcting unit13corrects the voltage command Vref using the correction amount VL*. Thus, for the power conversion device that has a small output impedance, correction is performed so as to increase the output impedance thereof, whereby variation in output impedances is suppressed.

Therefore, even when instantaneous power change occurs at the time of, for example, applying a load, concentration of power allocation (allocated current) is prevented and power allocations can be improved to be uniformed between the power conversion devices21a,21b. Furthermore, the PLL unit15changes the frequency of output voltage Vc in accordance with active power calculated from output voltage Vc and output current Io of each power conversion device21a,21b, whereby power allocations in a steady state can also be uniformed.

The inductance of the filter reactor3can vary also depending on the temperature of the filter reactor3. As shown inFIG. 23, in general, the inductance decreases with increase in temperature, and near the Curie temperature, the inductance sharply decreases. As a result of decrease in the inductance of the filter reactor3, the impedance of the power conversion device21decreases. Therefore, in the case where the plurality of power conversion devices21perform parallel operations, if difference occurs between the temperatures of the filter reactors3of the respective power conversion devices21, difference also occurs between the impedances of the respective power conversion devices21.

Further, if current flowing through the filter reactor3increases, the inductance decreases due to magnetic saturation, so that the impedance of the power conversion device21decreases.

In the case where the plurality of power conversion devices21perform parallel operations, load current concentrates on the power conversion device21that has a decreased impedance, and therefore overcurrent is likely to occur in that power conversion device21. As described above, even if variation occurs in impedances of the plurality of power conversion devices21performing parallel operations, in the present embodiment, each power conversion device21is operated so that current flows with impedance reduction suppressed, whereby power allocations to the power conversion devices21a,21bcan be uniformed.

Further, in the case where cross current of DC current occurs between the power conversion devices21, an effect of reducing the cross current of DC current is also obtained by setting the virtual resistance Rset in the voltage correction amount calculation unit12.

FIG. 24is a block diagram showing the configuration of a power conversion device applied to a power conversion system according to embodiment 2 of the present invention. The components that correspond to or are the same as those shown inFIG. 3in embodiment 1 are denoted by the same reference characters.

The present embodiment 2 is the same as embodiment 1 in that the control unit10includes the voltage command generation unit11, a voltage correction amount calculation unit112, the voltage command correcting unit13, the PWM signal generation unit14, and the PLL unit15. Difference from embodiment 1 is that the corrected voltage command Vref* outputted from the voltage command correcting unit13is inputted to the voltage correction amount calculation unit12, and the internal configuration of the voltage correction amount calculation unit112is also different from that in embodiment 1. Hereinafter, the details of the voltage correction amount calculation unit112will be described.

In the present embodiment 2, the voltage correction amount calculation unit112calculates the correction amount VL* for the voltage command on the basis of the reactor current IL, the output voltage Vc, and the output Vref* from the voltage command correcting unit13. As is also described in embodiment 1, the correction amount VL* of the voltage command corresponds to a phenomenon that voltage drop due to impedance occurs between the switching element unit2and the filter reactor3. An example of calculation by the voltage correction amount calculation unit112is shown by the following Expression (7).

Here, VL* is the correction amount for the voltage command, calculated by the voltage correction amount calculation unit112, IL is reactor current detected by the reactor current detection unit6, Vc is output voltage detected by the output voltage detection unit7, Vref* is the corrected voltage command corrected by the voltage command correcting unit13, Lset is the inductance component gain, KVL is the reactor voltage gain, and Rset is the resistance component gain.

Specifically, as shown inFIG. 25, operation is performed such that the virtual resistance Rset and a virtual inductance Lsetα are present inside the switching element unit2of each power conversion device21(21a,21b). The virtual inductance Lsetα is set so that the sum of the virtual inductance Lsetα and the inductance of the filter reactor3become Lset.

Voltage drop when reactor current IL flows through the inductance Lset is calculated from the reactor current IL and the inductance component gain Lset, and this corresponds to the first term on the right-hand side of Expression (7). Voltage obtained by subtracting voltage drop of the filter reactor3(corresponding to the second term on the right side in Expression (7)) from the value of the first term is defined as voltage drop due to the virtual inductance Lseta. Thus, it is possible to set the virtual inductance Lseta, considering also the inductance of the filter reactor3. Then, the voltage command Vref can be corrected so that the inductance including the actual inductance component of the filter reactor3and the virtual inductance Lsetα becomes Lset.

In Expression (7), the first term and the third term on the right-hand side are the same as the first term and the second term on the right-hand side of Expression (3) shown in the above embodiment 1, and can be calculated by the same method as in embodiment 1.

The second term on the right-hand side of Expression (7) corresponds to voltage applied to the filter reactor3, which is estimated on the basis of the output voltage Vc detected by the output voltage detection unit7and the corrected voltage command Vref* obtained by the voltage command correcting unit13. In this case, a value obtained by causing a difference between the corrected voltage command Vref* and the output voltage Vc to pass through a filter or the like may be used, or a moving average value may be used.

If the inductance component of the filter reactor3included in the inductance component Lset is desired to be reduced, it suffices that the reactor voltage gain KVL is reduced. For example, in the case where Lset is 2 mH, the inductance of the filter reactor3is 1 mH, and the reactor voltage gain KVL is 1, inductance 1 mH obtained by subtracting inductance 1 mH of the filter reactor3from Lset becomes the virtual inductance Lsetα inside the switching element unit2. On the other hand, in the case where the reactor voltage gain is 0.5, inductance 1.5 mH obtained by subtracting, from Lset, 0.5 mH which is obtained by multiplying the inductance of the filter reactor3by the reactor voltage gain KVL, becomes the virtual inductance Lsetα inside the switching element unit2.

By subtracting the second term from the first term on the right-hand side of Expression (7), it is possible to correct only error of the inductance component of the filter reactor3with respect to the inductance component gain Lset. Thus, it is possible to set the output impedance of the power conversion device21, using the inductance component gain Lset as a reference, more accurately than in the case of embodiment 1.

For example, in the case where the power conversion device21aand the power conversion device21bperform parallel operations, it is assumed that the inductance design value of the filter reactor3is 1 mH, whereas the inductance of the filter reactor3of the power conversion device21ais 1.2 mH (deviation of 20%) and the inductance of the filter reactor3of the power conversion device21bis 0.8 mH (deviation of −20%). In this case, at the time of load inrush or the like, current allocation (power allocation) to the power conversion device21bis about 1.5 times current allocation (power allocation) to the power conversion device21a.

Here, if the inductance component gain Lset is set at 0.002, it appears that the composite inductance Lset obtained by connecting the virtual inductance inside the switching element unit2and the inductance of the filter reactor3in series is 2 mH in both of the power conversion devices21a,21b. Thus, at the time of load inrush or the like, current allocations (power allocations) to the power conversion devices21a,21baare improved to be equalized.

The other configurations and operational effects are the same as those in embodiment 1, and the detailed description thereof is omitted here.

It is noted that the present invention is not limited only to the configurations of the above embodiments 1, 2, and without departing from the scope of the present invention, the configurations of each embodiment 1, 2 may be partially modified, or some of the components thereof may be omitted. In addition, the configurations of the embodiment 1, 2 may be combined with each other as appropriate.