A method, system, and apparatus for setting an on-chip password is provided. In an embodiment, a method for programming an on-chip password includes determining a desired logic state for a field-effect transistor according to the on-chip password. The desired logic state is one of a first logic state and a second logic state. The method also includes subjecting one of a source and a drain of the field-effect transistor to hot-carrier stress according to the desired logic state to produce one of a symmetric state of the field-effect transistor and an asymmetric state of the field-effect transistor. The symmetric state corresponds to one of the first and second logic states. The asymmetric state corresponds to the other one of the first and second logic states.

BACKGROUND

The disclosure relates generally to semiconductor chips and more specifically to methods, systems, and structured for forming on-chip passwords.

On-chip password or chip identification has become increasingly important, particularly with the proliferation of Internet of things (IoT). The application of on-chip password can be used for access authentication and/or to prevent counterfeits. On-chip password can be software based or hardware-based. However, a software-based password is susceptible to cyberattack. A hardware-based password is typically achieved by using eFuse (electrical fuse) or by using embedded flash memory (eFlash). However, both methods have drawbacks. Although eFuse is typically CMOS compatible (for old CMOS nodes), one problem with eFuse is that it can only be used once. In other words, one cannot flexibly change the password. Thus, for the state-of-the-art CMOS, which use high-k/metal gates, the conventional eFuse can no longer be obtained without additional process steps. In contrast to eFuse, eFlash can be re-programmed multiple times. However, the eFlash process is not compatible with the conventional CMOS.

Therefore, it would be desirable to have a method and apparatus that take into account at least some of the issues discussed above, as well as other possible issues. For example, it would be desirable to have a method and apparatus that overcome a technical problem with forming an on-chip password that can be fabricated along with CMOS and that can be programmed multiple times.

SUMMARY

According to one embodiment of the present invention, a method for programming an on-chip password includes determining a desired logic state for a field-effect transistor according to the on-chip password. The desired logic state is one of a first logic state and a second logic state. The method also includes subjecting one of a source and a drain of the field-effect transistor to hot-carrier stress according to the desired logic state to produce one of a symmetric state of the field-effect transistor and an asymmetric state of the field-effect transistor. The symmetric state corresponds to one of the first and second logic states. The asymmetric state corresponds to the other one of the first and second logic states.

According to another embodiment of the present invention, a computer for programming an on-chip password includes a processor and a non-transitory computer readable storage medium storing program code which, when executed by the processor, performs a computer-implemented method of using the computer to program an on-chip password. The program code includes program code for determining a desired logic state for a field-effect transistor according to the on-chip password, the desired logic state being one of a first logic state and a second logic state. The program code also includes program code for subjecting one of a source and a drain of the field-effect transistor to hot-carrier stress according to the desired logic state to produce one of a symmetric state of the field-effect transistor and an asymmetric state of the field-effect transistor. The symmetric state corresponds to one of the first and second logic states. The asymmetric state corresponds to the other one of the first and second logic states.

According to another embodiment of the present invention, a semiconductor device for on-chip password programming includes a field-effect transistor. The device also includes a hot-carrier stress application unit coupled to the field-effect transistor and configured to subject one of a source and a drain of the field-effect transistor to hot-carrier stress according to the desired logic state to produce one of a symmetric state of the field-effect transistor and an asymmetric state of the field-effect transistor. The symmetric state corresponds to one of the first and second logic states. The asymmetric state corresponds to the other one of the first and second logic states.

DETAILED DESCRIPTION

The present invention may be a system, a method, and/or a computer program product. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to carry out aspects of the present invention.

The illustrative embodiments recognize and take into account one or more considerations. For example, the illustrative embodiments recognize and take into account that providing an on-chip password that is reprogrammable multiple times is difficult. The illustrative embodiments recognize and take into account that one solution can use hot-carrier stress to introduce defects into the source and/or drain of a MOSFET to alter the symmetry of the MOSFET, thereby storing a logic state that can be measured by measuring the forward (i.e., normal) and reverse currents across the drain and source. In order to turn a symmetric MOSFET into an asymmetric MOSFET, hot-carrier stress is applied to one of the source and the drain to introduce defects. In order to turn an asymmetric MOSFET into a symmetric MOSFET, hot-carrier stress is applied to the other of the source or the drain from that to which hot-carrier stress was previously applied in order to introduce defects into the other side, such that both the source and the drain side contain substantially the same amount of defects. In order to turn the symmetric MOSFET back into an asymmetric state, hot-carrier stress is applied again to the one of the source and the drain to introduce additional defects that cause the MOSFET to once again be in an asymmetric state. The repeated application of hot-carrier stress may be performed to repeatedly change the MOSFET from an asymmetric state to a symmetric state or from a symmetric state to an asymmetric state.

Thus, the illustrative embodiments provide a method, apparatus, system, and computer program product for repeatedly programming an on-chip password. Thus, in an exemplary embodiment, a method for programming an on-chip password, includes determining a desired logic state for a field-effect transistor according to the on-chip password, the desired logic state being one of a first logic state and a second logic state. Next, one of a source and a drain of the field-effect transistor is subjected to hot-carrier stress according to the desired logic state to produce one of a symmetric state of the field-effect transistor and an asymmetric state of the field-effect transistor. The symmetric state corresponds to one of the first and second logic states. The asymmetric state corresponds to the other one of the first and second logic states.

Disclosed herein are methods, systems, and structures for forming an on-chip array circuit that can be used as an on-chip password. The disclosed array can be fabricated along with CMOS and can be programmed multiple times. In an embodiment, each password bit is achieved by a standard MOS transistor. In an embodiment, programming of each bit is achieved by hot-carrier stress.

A fresh MOSFET is symmetric. This means that the source and drain are interchangeable. The channel current remains the same for a fixed gate bias and a fixed source/drain bias regardless of which source/drain terminal is used as a source and which source/drain terminal is used as a drain. However, when a MOSFET is subject to hot-carrier stress (HCS), defects, such as interface traps, are generated and localized on the drain side. As a result, a MOSFET, after the first application of HCS becomes asymmetric. The channel current depends on which terminal is used as the source and which terminal is used as the drain during measurement. In an embodiment, the channel current is measured twice. In the first measurement, the terminal assignment during measurement is the same as that during HCS. In other words, the source in the HCS remains the source during the first measurement and the drain during HCS remains the drain during the first measurement. In the second measurement, the source and drain terminals are swapped. Thus, in the second measurement, the source in the HCS becomes the drain in the second measurement and the drain in the HCS becomes the source in the second measurement. The channel current in the second measurement is lower than the first measurement due to the asymmetric distribution of the defects generated by the HCS.

To set up a password for the first time, if a bit is logic “1”, the corresponding MOSFET is subjected to HCS. If a bit is logic “0”, then the corresponding MOSFET is not subjected to HCS. With an array of MOSFETs, a series of “1”s and “0”s are generated.

To change the password, each bit is first measured. In an embodiment, if the bit needs to be changed from “0” to “1”, the corresponding MOSFET is subjected to HCS. If the bit needs to be changed from “1” to “0”, the MOSFET is subjected to HCS with the original source as the drain and the original drain as the source during the new HCS, so that substantially the same amount of defects (traps) is generated on the original source side as were in the original, produced on the original drain side. After the second HCS, both the source and the drain sides have defects such that the MOSFET becomes symmetric.

To read the code, each MOSFET is measured twice. During the second measurement, the source and drain are swapped. If the channel current is comparable between these two measurements, then that MOSFET is symmetric and this indicates a logic “0” state. If the channel current is different between these two measurements, then the MOSFET is asymmetric and indicates a logic “1” state.

The process described herein can be repeated by programming each MOSFET to symmetric or asymmetric as appropriate to achieve a new password change. This process described herein can be repeated as often as the password is changed.

Although described in terms of a logic “1” state represented by a MOSFET in an asymmetric state and a logic “0” state represented by a MOSFET in a symmetric state, in other embodiments, the logic “1” state may be represented by a MOSFET in a symmetric state and the logic “0” be represented by a MOSFET in an asymmetric state.

With reference now to the figures and, in particular, with reference toFIG. 1, a diagram of a metal-oxide semiconductor field-effect transistor (MOSFET) before hot-carrier stress is depicted in accordance with an illustrative embodiment. MOSFET100includes a gate102, a source104, a channel106, a drain108, and an insulator110. The source104and drain108may be referred to as terminals and the terminals may be switched for purposes of measuring the drive current such that the drive current is measured not only in a normal mode (normal current measurement) from the source102to the drain108, but also a drive current may be measured in a reverse mode (reverse current measurement) from the drain108to the source104. Normal and reverse mode current measurements are explained in greater detail below.

FIG. 2is a diagram of MOSFET100after hot-carrier stress applied to the drain108of the MOSFET100in accordance with an illustrative embodiment. For hot-carrier stress, in order to create defects on drain108side of a MOSFET100, the following voltage condition is applied to the MOSFET100. Source terminal104is grounded (0 volt), a high voltage is applied to the drain terminal108, and a voltage greater than the threshold voltage of the MOSFET100is applied to the gate terminal102to turn on the MOSFET100. For n-type MOSFET, high energy electrons flow from source through the channel106to drain108. They are accelerated by the electrical field between source104and drain108and gain kinetic energy. When they arrive at drain108side, those high energy electrons (often referred to as “hot electrons”) creates defects near the drain108region. Similarly, for p-type MOSFET, hot carriers are hot holes instead of hot electrons. Defects can be interfaces traps such as dangling bonds between the gate dielectric and the channel106of the MOSFET100. Defects can also be hot carriers injected into the gate dielectric, or both. The effect of those defects is that they change of characteristics of the MOSFET100. For example, before hot carrier stress a MOSFET100is typically symmetric (meaning source104and drain108terminals are structurally identical). After hot carrier stress, the MOSFET100becomes asymmetric due to localized defect generation (drain side or source side depending on bias condition). The stress voltages depend on the MOSFET dimensions such as gate length, gate dielectric thickness, etc. For example, for a MOSFET with a gate length of 25 nm, and an equivalent gate dielectric thickness of about 1.5 nanometers (nm), a gate voltage can be about 1 volt (V), and 2.5V can be applied to drain108while source is grounded (0V) to create defects on drain108side. Conversely, for the same MOSFET100, defects can be generated on source104side by grounding drain108and applying 2.5V on source.

As shown, defects112are present between the gate102, channel106, and drain108of the MOSFET100. The defects112are represented by “X”s in the Figures. In the depicted example, the defects112are on the drain108side of the MOSFET100. However, in other embodiments, the hot-carrier stress could be applied to the source104side and, in that case, the defects112would be on the source104side of the MOSFET100. If it is desired to create defects on the source104side, the drain108side is grounded, applying a high voltage on source side, and a gate voltage is greater than the threshold voltage of the MOSFET100to turn it on (basically flipping the source/drain terminals104,108). The defects112cause an asymmetry in the MOSFET100that is measurable. The current from the source104to the drain108is compared to the current from the drain108to the source104. When there is an asymmetry in the MOSFET100due to the defects112, the current from the source104to the drain108is different from that of the current from the drain108to the source104. If there is no asymmetry in the MOSFET100, then the difference in the current in the two directions will be zero. It should be noted that in an embodiment, the absolute value of the drive current in either direction (e.g., source to drain or drain to source) is not important. The bit information (logic “1” or “0”) is determined by the current difference between the two measurements (in normal mode and in reverse mode). The bit information does not depend on the absolute value of the drive current. Alternatively, in an embodiment, instead of measuring the current, other device characteristics, such as, for example, threshold voltages, subthreshold slopes, transconductances, resistances are measured in normal mode and in reverse mode to determine the bit information (logic “1” or “0”). A measurement of a device characteristic in normal mode for each device characteristic is a mode in which MOSFET is biased in a normal fashion such that the source and drain operate as a source and drain respectively. A measurement of a device characteristic in a reverse mode is a measurement made in a mode in which the MOSFET is biased in a reverse fashion such that the source acts as a drain and the drain acts as a source.

FIG. 3is a diagram illustrating a MOSFET before and after hot-carrier stress and with normal and reverse current measurements in accordance with an illustrative embodiment. MOSFET302is a MOSFET before application of hot-carrier stress. As shown, MOSFET302is symmetric without defects on either the source104or drain108sides. MOSFET304is a MOSFET after application of hot-carrier stress to the drain108side of the MOSFET304thereby introducing defects112on the drain108side of the MOSFET304. MOSFET306represents a MOSFET under normal current measurement measured from the source314to the drain318. MOSFET308represents a MOSFET under a reverse current measurement from the drain318to the source314.

FIG. 4is a diagram showing the logic state corresponding to various states of the MOSFET100. In the logic state “0”, the MOSFET100is symmetrical such that the normal measurement of the current400equaling normal current measurement402from the source104to the drain108is the same as the reverse current measurement404where the source104and drain108have been swapped such that the drain108is now the source and the source104is now the drain. In the logic state “1”, the currents from the normal measurement402and from the reverse measurement404are different.

FIG. 5is a diagram showing the state of a MOSFET before and after application of hot-carrier stress for changing the logic of the MOSFET in accordance with an illustrative embodiment. In an embodiment, in order to change a MOSFET from a logic state “1” to a logic state “0”, hot-carrier stress is applied to the one of the source104, such that the MOSFET520can be returned to a symmetric state by having an equal amount of defects112on both the source104and the drain108side of the MOSFET520. In the depicted example, hot-carrier stress is applied to the source104to create defects112on the source side of the MOSFET520. The MOSFET520before the change502is shown on the upper left of the diagram and the MOSFET520after change504is shown on the upper right of the diagram. By creating defects on the source104side of the MOSFET520, the MOSFET520is changed from an asymmetric state to a symmetric state, thereby changing the logic from “1” to “0”.

In an embodiment, in order to change a MOSFET from a logic state “0” to a logic state “1”, the MOSFET530is subjected to a hot-carrier stress on the drain108in order to create an asymmetry in the MOSFET530and thereby result in the MOSFET530changing from a logic “0” to a logic “1”. In the depicted example, hot-carrier stress is applied to the drain108of the MOSFET530to cause the MOSFET to become asymmetric with respect to defects112and thereby change the MOSFET530from a logic “0” to a logic “1” state. The MOSFET530in logic state “0” before the change502is shown on the lower left of the Figure and the MOSFET530in logic state “1” after change504by creating defects on the drain108side of the MOSFET530is shown on the lower right of the Figure.

FIG. 6is a diagram showing the state of a MOSFET before and after application of hot-carrier stress for changing the logic of the MOSFET in accordance with an illustrative embodiment. The top part ofFIG. 6showing the procedure for changing a MOSFET520from a logic “1” to logic “0” is the same as shown inFIG. 5. In the example, the MOSFET630has already been subjected to hot-carrier stress on both source104and drain108, such that both the source104and the drain108contain defects112. In order to change the MOSFET630from a logic state “0” to a logic state “1”, the drain108is subjected to hot-carrier stress again in order to introduce additional defects114on the drain108side of the MOSFET630, such that the MOSFET630is once again in an asymmetric state due to the presence of additional defects114on the drain side108, than are present on the source104side. The MOSFET630before the change502is shown on the lower left of the Figure and the MOSFET630after the change504is shown on the lower right of the Figure.

Thus, the MOSFET630may be reprogrammed multiple times by applying additional hot-carrier stress to the appropriate one of the source112and the drain108in order to introduce additional defects112,114as needed to make the MOSFET630either symmetric or asymmetric as needed to change the logic from “0” or “1” to “1” or “0”.

FIG. 7is a diagram700showing saturation current as a function of voltage (Vds) between the drain and source for both unstressed and stressed MOSFETs. Graph702is a plot of the saturation current versus Vdsfor an unstressed MOSFET. An unstressed MOSFET is a MOSFET that has not been subjected to hot-carrier stress (or one that has been subjected to multiple hot-carrier stresses such that the amount of defects on the drain and the source are substantially the same). The saturation current for the unstressed MOSFET is the same for the normal current (i.e., current from source to drain) as for the reverse current (i.e., current from the drain to the source). Graph704shows the normal saturation current (i.e., current from the source to the drain) versus Vdsfor a stressed MOSFET (i.e., a MOSFET in which an asymmetry in defects on the source and drain of the MOSFET exists as a result of selectively applying hot-carrier stress to only one of the source and the drain or applied more to one of the source and the drain). Graph706shows the reverse current (i.e., current from the drain to the source) for a stressed MOSFET. As shown, the graph704of the saturation current for the stressed normal measurement of current for the MOSFET compared to the graph706of the saturation current for the stressed reverse measurement of the current for the MOSFET shows that the current is not the same for each Vdsvalue. In an embodiment, this difference in current is measured and used to determine the logic state of the MOSFET. When the normal and reverse current are the same, the MOSFET is considered to be in a first logic state (e.g., a logic state “0”) and when the normal and the reverse current are not the same, the MOSFET is considered to be in a second logic state (e.g., a logic state “1”).

FIG. 8is a diagram of a bit cell800in accordance with an illustrative embodiment. Bit cell800includes a word line (WL)802, a source line (SL)804, and a bit line (BL)806. The bit cell800also includes a MOSFET that includes a gate808connected to the WL802, a source810connected to the SL804, and a drain812connected to the BL806. The MOSFET including the gate808, source810, and drain812may be implemented as any of MOSFETs100,302,304,306,308,520,530,630. The MOSFET in bit cell800may be subjected to hot-carrier stress as appropriate to change a logic state of the MOSFET.

FIG. 9is a diagram of an array900of bit cells902. The Array900includes a plurality of bit cells902, source lines SL1, SL2, . . . SLm, a plurality of bit lines BL1, BL2, . . . BLm, and word lines WL1, WL2, . . . WLn. Each bit cell902may be implemented as any of MOSFETs100,302,304,306,308,520,530,630. The MOSFET in each of bit cells902may be subjected to hot-carrier stress as appropriate to change a logic state of the MOSFET. Each MOSFET in the bit cells902is individually and independently programmable such that each bit cell902may be in a logic state “0” or “1” independent of the logic state of any other bit cell902.

FIG. 10is a diagram of an on-chip password system1000in accordance with an illustrative embodiment. On-chip password system1000includes a user input module1002, a password reader and setter1004, a current measurer1006, an array of MOSFETs1008, a hot-carrier stress source1010, a voltage source1012, an authenticator1014, and data1016. Data1016stores data. The user input module1002receives user password input data for setting or changing the password. The user input module1002also receives user input in the form of a password that, if correct, allows the user to access data1016protected by the on-chip password.

The password reader and setter1004reads and sets the password on the array of MOSFETs1008. The current measurer1006measures the normal current and the reverse current across each of the array of MOSFETs1008. Current across the MOSFETs1008may be driven by applying a voltage cross the source and drain of each MOSFET using the voltage source1012.

The hot-carrier stress source1010applies hot-carrier stress to one of the drain or source of one of the MOSFETs1008in order to introduce defects into the source or drain side of one of the MOSFETs1008. The defects, if introduced onto only one of the drain and source sides, cause the current measurement in the normal and reverse directions to be different. If defects are introduced into both the source and drain sides of one of the MOSFETs1008, then the normal and reverse currents measured on that MOSFET1008will be the same. The logic state of each of the MOSFETs1008is determined by whether both the drain and source contain an equal amount of defects (or equal lack of defects) or whether one of the drain or source contains more defects than the other.

The password reader and setter1004works in conjunction with the current measurer1006to determine the logic state of each of the MOSFETs in the array of MOSFETs1008. The sequence of logic states of the MOSFETs in the array of MOSFETs1008is the on-chip password. This on-chip password can be adjusted by the password reader and setter1004. The password reader and setter1004also works in conjunction with the hot-carrier stress source in order to program the password into the array of MOSFETs1008.

The authenticator1014receives a user input password from user input module1002and compares the user input to the password stored in the array of MOSFETs1008. The password stored in the array of MOSFETs1008is read by password reader and setter1004. If the password entered by the user matches the stored password, then the authenticator1014grants access by the user to the data1016.

In an embodiment, system1000is a physical hardware system and includes one or more data processing systems. When more than one data processing system is present in system1000, those data processing systems are in communication with each other using a communications medium. The communications medium may be a network. The data processing systems may be selected from at least one of a computer, a server computer, a tablet, or some other suitable data processing system.

FIG. 11is a flowchart of an exemplary method1100for setting an on-chip password in accordance an illustrative embodiment. The processes inFIG. 11can be implemented in hardware, software, or both. When implemented in software, the processes can take the form of program code that is run by one of more processor units located in one or more hardware devices in one or more computer systems. For example, these processes can be implemented in password reader and setter1004running on system1000inFIG. 10. Method1100begins by determining a desired logic state for a FET (step1102). In an embodiment, the desired logic state is determined based on user input. Next, a current logic state for a FET is determined (step1104). In an embodiment, the current logic state for the FET is determined by comparing the normal and reverse currents across the source and drain of the FET. If the normal and reverse currents are equal, then the logic state is a first logic state (e.g., logic state “0”). If the normal and reverse currents are not equal, then the logic state is a second logic state (e.g., logic state “1”). Next, the method1100determines if the desired logic state is different from the current logic state (step1106). If the desired logic state is different from the current state, then one of the source or the drain is subjected to hot-carrier stress in order to introduce defects into the corresponding source or drain (step1108). If the desired logic state of the FET is not different from the current state, then the logic state of the FET is left unchanged (step1110).

FIG. 12is a flowchart of an exemplary method1200for reading the logic state of a FET in accordance with an illustrative embodiment. The processes inFIG. 12can be implemented in hardware, software, or both. When implemented in software, the processes can take the form of program code that is run by one of more processor units located in one or more hardware devices in one or more computer systems. For example, these processes can be implemented in password reader and setter1004running on system1000inFIG. 10. The method1200begins by measuring the current from the source to the drain (step1202). Next, the current from the drain to the source is measured (step1204). Next, the method1200determines if the normal current and the reverse current are equal (step1206). If the two currents are equal, then the method1200determines that the device (e.g., MOSFET) is in a logic state “0” (step1208). If the two currents are not equal, then the method1200determines that the device is in a logic state “1” (step1210). In some embodiments, the determination of whether the normal current and the reverse current are the same is made by reference to a threshold. If the difference between the two currents exceeds a threshold, then the normal current and the reverse current are deemed different and if the difference between the two currents does not exceed the threshold, then the normal current and the reverse current are deemed to be the same.

In one illustrative example, one or more technical solutions are present that overcome a technical problem with repeatedly programming an on-chip password. As a result, one or more technical solutions may provide a technical effect of allowing an on-chip password to be programmed and re-programmed multiple times. In an embodiment, hot-carrier stress is used to change the symmetry of a MOSFET by introducing defects into one of the source and the drain. If the amount of defects (or lack thereof) are approximately the same on the source and the drain, the MOSFET is symmetric and the normal and reverse currents measured across the source and the drain are approximately equal. If the amount of defects on one of the source or the drain are more than on the other side, then the MOSFET is asymmetric and the normal and reverse currents measured across the source and the drain are different. This state of the MOSFET is persistent until reprogrammed. The state of the MOSFET may be reprogrammed multiple times.

Although described primarily with a symmetric state of the MOSFET representing a logic state “0” and an asymmetric state of the MOSFET as representing a logic state “1”, in other embodiments, the symmetric state corresponds to a logic state “1” and the asymmetric state corresponds to the logic state “0”.

Turning now toFIG. 13, a block diagram of a data processing system is depicted in accordance with an illustrative embodiment. In an embodiment, data processing system1300is implemented as on-chip password system1000depicted inFIG. 10. In this illustrative example, data processing system1300includes communications framework1302, which provides communications between processor unit1304, memory1306, persistent storage1308, communications unit1310, input/output (I/O) unit1312, and display1314. In this example, communications framework1302may take the form of a bus system.

Processor unit1304serves to execute instructions for software that may be loaded into memory1306. Processor unit1304may be a number of processors, a multi-processor core, or some other type of processor, depending on the particular implementation.

Memory1306and persistent storage1308are examples of storage devices1316. A storage device is any piece of hardware that is capable of storing information, such as, for example, without limitation, at least one of data, program code in functional form, or other suitable information either on a temporary basis, a permanent basis, or both on a temporary basis and a permanent basis. Storage devices1316may also be referred to as computer-readable storage devices in these illustrative examples. Memory1306, in these examples, may be, for example, a random-access memory or any other suitable volatile or non-volatile storage device. Persistent storage1308may take various forms, depending on the particular implementation.

For example, persistent storage1308may contain one or more components or devices. For example, persistent storage1308may be a hard drive, a solid-state drive (SSD), a flash memory, a rewritable optical disk, a rewritable magnetic tape, or some combination of the above. The media used by persistent storage1308also may be removable. For example, a removable hard drive may be used for persistent storage1308.

Communications unit1310, in these illustrative examples, provides for communications with other data processing systems or devices. In these illustrative examples, communications unit1310is a network interface card.

Input/output unit1312allows for input and output of data with other devices that may be connected to data processing system1300. For example, input/output unit1312may provide a connection for user input through at least one of a keyboard, a mouse, or some other suitable input device. Further, input/output unit1312may send output to a printer. Display1314provides a mechanism to display information to a user.

Instructions for at least one of the operating system, applications, or programs may be located in storage devices1316, which are in communication with processor unit1304through communications framework1302. The processes of the different embodiments may be performed by processor unit1304using computer-implemented instructions, which may be located in a memory, such as memory1306.

These instructions are referred to as program code, computer usable program code, or computer-readable program code that may be read and executed by a processor in processor unit1304. The program code in the different embodiments may be embodied on different physical or computer-readable storage media, such as memory1306or persistent storage1308.

A computer program product1322includes computer-readable media1320. Program code1318is located in a functional form on computer-readable media1320that is selectively removable and may be loaded onto or transferred to data processing system1300for execution by processor unit1304. Program code1318and computer-readable storage media1324form computer-readable media1320in these illustrative examples. In the illustrative example, computer-readable media1320is computer-readable storage media1324.

In these illustrative examples, computer-readable storage media1324is a physical or tangible storage device used to store program code1318rather than a medium that propagates or transmits program code1318.

Alternatively, program code1318may be transferred to data processing system1300using a computer-readable signal media. The computer-readable signal media may be, for example, a propagated data signal containing program code1318. For example, the computer-readable signal media may be at least one of an electromagnetic signal, an optical signal, or any other suitable type of signal. These signals may be transmitted over at least one of communications links, such as wireless communications links, optical fiber cable, coaxial cable, a wire, or any other suitable type of communications link.

Thus, illustrative embodiments of the present invention provide an on-chip multiple programmable password.