Semiconductor device, display device, and electronic device

Objects are to provide a semiconductor device with a novel structure, to provide a semiconductor device with low power consumption, and to provide a semiconductor device with a small chip area. A digital-analog converter and a frame memory are included. The frame memory includes a sample-and-hold circuit, a correction circuit, and a source follower circuit. The sample-and-hold circuit retains the analog voltage output from the digital-analog converter. The correction circuit corrects the analog voltage retained in the sample-and-hold circuit. The source-follower circuit outputs the corrected analog voltage. The sample-and-hold-circuit, the correction circuit, and the source follower circuit each comprise a first transistor. The first transistor comprises an oxide semiconductor layer in a semiconductor layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

One embodiment of the present invention relates to a semiconductor device, a display panel, and an electronic device.

In this specification and the like, a semiconductor device refers to an element, a circuit, a device, or the like that can function by utilizing semiconductor characteristics. An example of the semiconductor device is a semiconductor element such as a transistor or a diode. Another example of the semiconductor device is a circuit including a semiconductor element. Another example of the semiconductor device is a device provided with a circuit including a semiconductor element.

2. Description of the Related Art

A source driver integrated circuit (IC) in which a frame memory and a source driver are included (for example, see Patent Document 1) has been known. Static random access memory (SRAM) is generally used for the frame memory.

REFERENCE

Patent Document

[Patent Document 1] United States Published Patent Application No. 2008/0186266

SUMMARY OF THE INVENTION

By including the frame memory in the source driver IC, transmitting/receiving data to/from a host can be reduced and thus the source driver IC can reduce power consumption. However, data stored in SRAM is digital data. Therefore, the source driver IC cannot reduce the power consumed by converting digital data to analog data.

Furthermore, as the number of pixels increases, the amount of data retained in SRAM also increases. To deal with the increase in the amount of data, miniaturization of transistors that constitute SRAM has progressed to reduce the cell areas. However, transistor miniaturization causes the increase in leakage current. As a result, power consumption is increased in a source driver IC embedded with a frame memory using SRAM.

Furthermore, SRAM has a large number of transistors and a large cell area. Therefore, the source driver IC including the frame memory with the use of SRAM causes problems such as an increase in a chip area.

In view of the above, an object of one embodiment of the present invention is to provide a novel semiconductor device that has a structure different from that of an existing semiconductor device functioning as a source driver IC, a novel display panel, and a novel electronic device. Another object of one embodiment of the present invention is to provide a semiconductor device or the like with a novel structure, in which power consumption is reduced. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device or the like with a novel structure in which a chip area is reduced.

Note that the objects of one embodiment of the present invention are not limited to the above objects. The objects described above do not disturb the existence of other objects. The other objects are objects that are not described above and will be described below. The other objects will be apparent from and can be derived from the description of the specification, the drawings, and the like by those skilled in the art. One embodiment of the present invention is to achieve at least one of the aforementioned objects and the other objects.

One embodiment of the present invention is a digital-analog converter and a frame memory. The frame memory includes a sample-and-hold circuit, a correction circuit, and a source follower circuit. The correction circuit is configured to correct the analog voltage retained in the sample-and-hold circuit. The source follower is configured to output the corrected analog voltage. The sample-and-hold-circuit, the correction circuit, and the source follower circuit each include a first transistor. The first transistor includes an oxide semiconductor layer in the semiconductor layer.

One embodiment of the present invention is a digital-analog converter, a frame memory, and a buffer circuit. The frame memory includes a sample-and-hold circuit, a correction circuit, and a source follower circuit. The correction circuit is configured to correct the analog voltage retained in the sample-and-hold circuit. The source follower is configured to output the corrected analog voltage to the buffer circuit. The sample-and-hold-circuit, the correction circuit, and the source follower circuit each include a first transistor. The first transistor includes an oxide semiconductor layer in the semiconductor layer.

One embodiment of the present invention is a digital-analog converter, a frame memory, and a buffer circuit. The frame memory includes a sample-and-hold circuit, a correction circuit, and a source follower circuit. The correction circuit is configured to correct the analog voltage retained in the sample-and-hold circuit. The source follower is configured to output the corrected analog voltage to the buffer circuit. The sample-and-hold-circuit, the correction circuit, and the source follower circuit each include a first transistor. Each of the digital analog converter and the buffer circuit includes a second transistor. The first transistor includes an oxide semiconductor layer in the semiconductor layer. The second transistor includes silicon in the semiconductor layer.

In the semiconductor device of one embodiment of the present invention, a layer including the first transistor is preferably placed above a layer including the second transistor.

Note that other embodiments of the present invention will be described in the following embodiments with reference to the drawings.

One embodiment of the present invention can provide a novel semiconductor device that has a structure different from that of an existing semiconductor device functioning as a source driver IC, a novel display panel, and a novel electronic device. Another embodiment of the present invention can provide a semiconductor device or the like with a novel structure, in which power consumption is reduced. Another embodiment of the present invention can provide a semiconductor device or the like with a novel structure in which a chip area is reduced.

Note that the effects of one embodiment of the present invention are not limited to the above effects. The effects described above do not disturb the existence of other effects. The other effects are effects that are not described above and will be described below. The other effects will be apparent from and can be derived from the description of the specification, the drawings, and the like by those skilled in the art. One embodiment of the present invention is to have at least one of the aforementioned effects and the other effects. Accordingly, one embodiment of the present invention does not have the aforementioned effects in some cases.

DETAILED DESCRIPTION OF THE INVENTION

In this specification and the like, ordinal numbers such as “first”, “second”, and “third” are used in order to avoid confusion among components. Thus, the terms do not limit the number or order of components. In the present specification and the like, a “first” component in one embodiment can be referred to as a “second” component in other embodiments or claims. Furthermore, in this specification and the like, a “first” component in one embodiment can be omitted in other embodiments or claims.

The same elements or elements having similar functions, elements formed using the same material, elements formed at the same time, or the like in the drawings are denoted by the same reference numerals in some cases, and the description thereof is not repeated in some cases.

In this embodiment, an example of a semiconductor device functioning as a source driver IC will be described.

FIG. 1is an example of a block diagram that schematically illustrates a configuration of the semiconductor device.

InFIG. 1, a semiconductor device100(shown as SDIC) includes an interface101(shown as I/F), a logic circuit102(shown as LOGIC), a latch circuit103(shown as LAT), a digital-analog converter104(shown as D/A), a frame memory105(shown as RAM), and a buffer circuit106(shown as AMP).

InFIG. 1, a digital signal output from a host processor110(shown as Host) is input to the semiconductor device100. A data signal, which is an analog signal, is output to a display device120(shown as Display) from the semiconductor device100.

The interface101has a function of decoding the digital signal input from the host processor110.

The logic circuit102has a function of arithmetically processing the digital signal, a function of distributing the digital signal to the latch circuit103by a shift register, or the like.

The latch circuit103has a function of retaining the digital signal, which is an image signal to be output to pixels of the display device.

The digital-analog converter104has a function of converting the digital signal into an analog signal and outputting the analog signal. The analog signal is an input signal DINof the frame memory105.

The buffer circuit106has a function of increasing the current supply capability of the input analog signal and outputting the resulting signal. The analog signal input to the buffer circuit106is an output signal DOUTof the frame memory105. The analog signal whose current supply capability is improved in the buffer circuit106is output to the display device120.

The frame memory105has a function of retaining the input signal DIN, which is an analog signal. The frame memory105has a function of outputting the retained analog signal as the output signal DOUTto the buffer circuit106.

A memory cell included in the frame memory105includes a transistor including an oxide semiconductor in a channel formation region (hereinafter, such a transistor is referred to as an OS transistor). The OS transistor has a low off-state current which flows in an off state. Therefore, the frame memory105including the OS transistor can retain charge corresponding to the analog signal. Furthermore, the analog signal corresponding to the charge can be output.

FIG. 2is a block diagram of the digital-analog converter104, the frame memory105, and the buffer circuit106of the semiconductor device100, and the display device120inFIG. 1.

InFIG. 2, the display device120includes a plurality of pixels121.FIG. 2shows an example of the pixels121arranged in m rows and n columns (m and n are natural numbers).

InFIG. 2, the frame memory105includes a plurality of memory cells140.FIG. 2shows an example of the memory cells140arranged in m rows and n columns (m and n are natural numbers). Note that the number of the memory cells140is the same as that of the pixels121.

Note that it is effective to arrange a greater number of the memory cells140than the number of the pixels121. With this structure, an analog signal corresponding to a data signal supplied to each pixel can be retained in the frame memory105.

In the frame memory105inFIG. 2, input signals DIN_1to DIN_n, which are output signals of the digital-analog converter104, are input to the respective lines. In the frame memory105inFIG. 2, output signals DOUT_1to DOUT_n, which are input signals of the buffer circuit106, are output to the respective lines of the display device120.

The digital-analog converter104and the buffer circuit106inFIG. 2are required to operate at high speed. Thus, a transistor including silicon in a channel formation region (hereinafter, a Si transistor) is preferably included in a channel formation region. In contrast, the frame memory105illustrated inFIG. 2, as described above, includes the OS transistor to retain charge corresponding to the analog signal.

Therefore, it is possible that the digital-analog converter104and the buffer circuit106are provided in a layer and the frame memory105is provided in another layer.FIG. 3is a schematic block diagram of the digital-analog converter104and the buffer circuit106, and the frame memory105provided in different layers.

As shown inFIG. 3, the digital-analog converter104and the buffer circuit106are provided in a first layer141. Furthermore, the frame memory105is provided in a second layer142, which is the upper layer of the first layer141. With this structure, it is possible that in the semiconductor device100, which functions as a source driver IC, the OS transistor included in the frame memory105is provided over the Si transistor included in a circuit other than the frame memory105, for example, the digital-analog converter104and the buffer circuit106.

It is necessary that the number of the memory cells140of the frame memory105is determined in accordance with the number of pixels121of the display device120. Thus, the circuit area occupied by the frame memory105increases. As described above, with the structure in which the frame memory105including the OS transistor is provided over a circuit other than the frame memory105, the circuit area occupied by the frame memory105is not increased; thus, the increase in the circuit area can be suppressed.

FIG. 4is a block diagram of the memory cell140of the frame memory105inFIG. 2. The memory cell140illustrated inFIG. 4includes a sample-and-hold circuit131(shown as S/H), a correction circuit132(shown as COR), and a source follower circuit133(shown as S/F). The input signal DINis supplied to the sample-and-hold circuit131and the correction circuit132. The output signal DOUTis output from the source follower circuit133.

FIG. 5Ashows an example of a specific circuit configuration of the memory cell140inFIG. 4.

A memory cell140A illustrated inFIG. 5Aincludes transistors M1to M5and capacitors C1and C2. All the transistors M1to M5are n-channel transistors in the following description. Gates of the transistors M1and M3are connected to a wiring for supplying a control signal EN1. A gate of the transistor M2is connected to a wiring for supplying a control signal EN2. One electrode of the capacitor C1is referred to as a node ND1inFIG. 5A. One electrode of the capacitor C2is referred to as a node ND2inFIG. 5A. A gate of a transistor M5is supplied with a reference voltage VREF. A current flowing through the transistor M5is made constant by the reference voltage VREF. A voltage VDDis applied to either one of a source and a drain of the transistor M4. A voltage VSSis applied to either one of a source and a drain of the transistor M5. Note that the voltage VDDis higher than the voltage VSS. The other electrode of the capacitor C2is supplied with a voltage V0. The voltage V0is preferably a fixed voltage, for example, a ground voltage (GND).

FIG. 5Bis a timing chart showing an operation of the circuit ofFIG. 5A.FIG. 5Billustrates signal waveforms of the control signals EN1and EN2. Furthermore,FIGS. 6A and 6B, andFIG. 7illustrate voltage of each of the transistors M1to M5and the nodes ND1and ND2in periods P1to P3in the timing chart inFIG. 5B.

In the first period P1, the control signal EN1is set at a high level and the control signal EN2is set at a low level. Here, the states of each of the transistors are illustrated inFIG. 6A. The transistors M1and M3are brought into an on state. The transistor M2is brought into an off state. Transistors in an off state are represented by a cross inFIG. 6A.

The transistor M1is turned on, so that the voltage of the node ND1becomes a voltage VDATAwhich is the input signal DIN.

The current flowing in the transistor M5flows through the transistors M4and M5. As the voltage between a gate and a source of the transistor M4(also referred to as a gate-source voltage), a voltage for making the above-described current flow is applied.FIG. 6Aillustrates the gate-source voltage of the transistor M4as VGS. Here, a voltage of the output signal DOUTbecomes (VDATA−VGS). The transistor M3is in an on state and thus, a voltage of the node ND2becomes (VDATA−VGS).

In the second period P2, the control signal EN1is set at a low level and the control signal EN2is set at a high level. Here, the states of each transistors at that time are illustrated inFIG. 6B. The transistor M2is brought into an on state. The transistors M1and M3are brought into an off state. Transistors in an off state are represented by a cross inFIG. 6B.

The transistor M2is turned on, so that the voltage of the node ND2changes from the voltage (VDATA−VGS) to the voltage VDATA. Here, the transistor M1is in an off state and thus, the node ND1is in an electrically floating state. Therefore, the voltage of the node ND1increases in accordance with the change of the voltage of the node ND2from the voltage (VDATA−VGS) to the voltage VDATA. The voltage of the ND1is increased to a voltage (VDATA+VGS) when the capacitance component of the capacitor C1is sufficiently larger than that of the node ND1. The voltage of the output signal DOUTbecomes a voltage VDATAand thus, the voltage can be corrected to a voltage VDATAof the input signal DINbecause the VGSof the transistor M4does not change.

In the third period P3, the control signal EN1is kept at a low level and the control signal EN2is set at a low level. Here, the states of each transistors at that time are illustrated inFIG. 7. The transistors M1to M3are brought into an off state. Transistors in an off state are represented by a cross inFIG. 7.

The transistors M1to M3are in an off state, so that voltages of the nodes ND1and ND2are retained at the voltage (VDATA+VGS) and the voltage VDATA, respectively. The voltage of the output signal DOUTbecomes the voltage VDATAand thus, the voltage corrected to the voltage VDATAof the input signal DINcan keep being output because the VGSof the transistor M4does not change.

As described above, the memory cell included in the frame memory105includes the OS transistor. In other words, the transistors M1to M5are OS transistors. The OS transistor has a low off-state current which flows in an off state. Therefore, the transistors M1to M3are brought into an off state and thus, voltages of the node ND1and the node ND2can be kept at the voltage (VDATA+VGS) and the voltage VDATA, respectively. Furthermore, the voltage VDATA, which is an analog signal corresponding to the voltages, can be output.

Instead of the memory cell140A illustrated inFIG. 5A, a memory cell140B illustrated inFIG. 8Acan be used.FIG. 8Aillustrates a configuration in which a backgate electrode for controlling a threshold voltage is included in each of the transistors M1to M3, which retain the voltages of the nodes ND1and ND2. The threshold voltage of each of the transistors M1to M3can be controlled by supplying a fixed voltage, for example, a voltage V0to the backgate electrode of each of the transistors M1to M3. By controlling the threshold voltage, for example, by applying a voltage for shifting the threshold voltage in a positive direction to the backgate electrode, the off-current can more surely be reduced.

As another example, a memory cell140C illustrated inFIG. 8Bhas a configuration including a backgate electrode in each of the transistors M4and M5supplying a constant current. By supplying the same voltages as those of the gate electrodes to the backgate electrodes of the transistors M4and M5, electric fields are applied from both above and below the channel formation regions and thus, the amount of current flowing through the transistors M4and M5can be increased without increasing the size of the transistors M4and M5.

FIG. 9is a diagram formed by adding a driver circuit143for controlling the operation of the frame memory105to a block diagram of the semiconductor device100inFIG. 2. Note that the display device120is omitted inFIG. 9.

The operation of the memory cells140is controlled row by row from the row [1] to [m] by the driving circuit143. The driving circuit143includes, for example, a shift register. Writing, retaining, and reading of the data signal can be controlled row by row by the driving circuit143in a manner similar to a gate driver controlling the pixels of the display device120.

The data signal output from the digital-analog converter104is directly output to the display device120in the case where the data signal retained in the frame memory105is different from the image displayed in the successive frames. Therefore, as illustrated inFIG. 10, switching circuits144are preferably provided between the frame memory105and the buffer circuit106.

The switching circuits144perform switching such that the data signal output from the digital-analog converter104is output to the buffer circuit106in the case where images displayed are different in successive frames and the data signal output from the frame memory105is output to the buffer circuit106in the case where images displayed are the same in successive frames. Therefore, by providing the switching circuits144, power necessary for an operation of the interface101, the logic circuit102, the latch circuit103, and the digital-analog converter104can be reduced, which leads to a reduction in power consumption in the semiconductor device100.

A circuit configuration of a memory cell in the case where the data signal output from the frame memory105is stopped is illustrated inFIG. 11A. A memory cell140D illustrated inFIG. 11Acorresponds to a configuration where transistors M6and M7are added to the circuit configuration of the memory cell140A illustrated inFIG. 5A. The transistors M6and M7are n-channel transistors here, like the transistors M1to M5.

Gates of the transistors M6and M7are connected to a wiring for supplying a control signal EN3. The transistors M6and M7are arranged on a path where a current of the source follower circuit133flows.

FIG. 11Bis a timing chart showing an operation of the circuit ofFIG. 11A.FIG. 11Billustrates signal waveforms of the control signal EN1, the control signal EN2, and the control signal EN3.

The operation in periods P1to P3inFIG. 11Bis basically similar to the operation inFIG. 5B. Specifically, in the periods P1and P2, the control signal EN3is set at a high level and the same operation as the operation inFIG. 5Bis performed. In the period P3other than the periods P1and P2, the control signal EN3is set at a low level and the transistors M6and M7on the path of the source follower circuit133where current flows are controlled to be in an off state.

As described above, the memory cell included in the frame memory105includes the OS transistor. That is, the transistors M1to M7are OS transistors. The OS transistor has a low off-state current which flows in an off state. Therefore, the transistors M1to M3are brought into an off state and thus, the voltages of the node ND1and the node ND2may be kept at the voltage (VDATA+VGS) and the voltage VDATA, respectively. Furthermore, the voltage VDATA, which is an analog signal corresponding to the voltages of the node ND1and the node ND2can be output.

Note that the transistor M5can be shared by the memory cells140D in the same column, which have the configuration inFIG. 11A.FIG. 12illustrates a circuit configuration in which the transistor M5is shared by memory cells140D_1and140_2in the same column.

Note that the memory cell140D_1receives an input signal DIN_1[1] and performs retention and performs output of an output signal DOUT_1[1] corresponding to the first column of the memory cell. The memory cell140D_2performs input and retention of an input signal DIN_1[2] and output of an output signal DOUT_1[2] corresponding to the second column of the memory cell. Control signals EN1[1], EN2[1], and EN3[1] are signals that control the operation of the memory cell140D_1. Control signals EN1[2], EN2[2], and EN3[2] are signals that control the operation of the memory cell140D_2.

FIG. 13is a timing chart showing an operation of the circuit configuration ofFIG. 11A.FIG. 13illustrates signal waveforms of the control signals EN1[1], EN2[1], and EN3[1] and the control signals EN1[2], EN2[2], and EN3[2].

Instead of the memory cell140A illustrated inFIG. 5A, a memory cell140E illustrated inFIG. 14Acan be used.FIG. 14Aillustrates a structure in which one electrode of the capacitor C3is connected to the node ND2. The other electrode of the capacitor C3is connected to a wiring for supplying a control signal EN2_B. The control signal EN2_B is an inverted signal of the control signal EN2.

FIG. 14Bis a timing chart that illustrates an operation of the circuit configuration ofFIG. 14A.FIG. 14Billustrates signal waves of the control signals EN1, EN2, and EN2_B.

The configurations illustrated inFIGS. 14A and 14Bcan prevent a decrease in the voltage due to parasitic capacitance of the node ND2and the transistor M2when the control signal EN2is set at a low level from a high level in a second period P2. Specifically, when the control signal EN2_B is set at a high level from a low level in the second period P2, the voltage of the node ND2is increased by the voltage decrease. Thus, the voltage of the node ND1, which is in an electrically floating state, can easily increase to the voltage (VDATA+VGS).

As another configuration, a memory cell140F ofFIG. 15has a gate capacitance of a transistor M8instead of the capacitor C3in the circuit configuration ofFIG. 14A.

Furthermore, as another configuration, a memory cell140G ofFIG. 16has a circuit configuration in which the structure added to the structure ofFIG. 14Ais applied to the circuit configuration ofFIG. 11A.

Furthermore, as another configuration, a memory cell140H ofFIG. 17has a circuit configuration in which the structure added to the structure ofFIG. 15is applied to the circuit configuration ofFIG. 11A.

As described above, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Furthermore, the semiconductor device can have a reduced chip area.

This embodiment will describe the semiconductor device that is explained in Embodiment 1 and functions as a source driver IC, a display device operated by the semiconductor device, and their variation examples.

A block diagram inFIG. 18illustrates the semiconductor device100, the host processor110, a game driver150(shown as GD), and the display device120.FIG. 18also illustrates a plurality of scan lines XL, a plurality of signal lines YL, and pixels121in the display device120. The semiconductor device100has a structure similar to that shown inFIG. 1of Embodiment 1.

The gate driver150has a function of supplying scan signals to the scan lines XL. The semiconductor device100serving as a source driver IC has a function of supplying data signals, which are analog signals, to the signal lines YL.

In the display device120, the scan lines XL and the signal lines YL are provided to be substantially orthogonal. The pixels121are provided at the intersections of the scan lines XL and the signal lines YL. For color display, the pixels121corresponding to the respective colors of red, green, and blue (RGB) are arranged in sequence. Note that the pixels of RGB can be arranged in a stripe pattern, a mosaic pattern, a delta pattern, or the like as appropriate. Without limitation to RGB, a pixel corresponding to white, yellow, or the like can be added for color display.

In the case of adding a touch sensor function to the display device120, a touch sensor160is added as in a semiconductor device100A illustrated inFIG. 19. Note that it is possible to obtain an in-cell touch panel by combining the touch sensor160and the display device120. A signal obtained by the touch sensor160can be processed by a semiconductor device100A that includes a touch sensor driver circuit181in addition to the components of the semiconductor device100. In the structure ofFIG. 19, controlling driving of the touch sensor and driving of the display device at different timings enables the reduction in malfunction of the touch sensor due to noise.

A semiconductor device100B in a block diagram ofFIG. 20includes an arithmetic device182. The arithmetic device182has a function of performing arithmetic processing on data. As an example of arithmetic processing, the arithmetic device182can execute image rotation processing, control for turning on or off a backlight, super-resolution processing, or the like. The semiconductor device100to which the arithmetic device182is added achieves higher performance.

A semiconductor device100C in a block diagram ofFIG. 21Aincludes an FPGA183. The FPGA183has a function of performing arithmetic processing on data. As an example of arithmetic processing, like the arithmetic device182, the FPGA183can execute image rotation processing, control for turning on or off a backlight, super-resolution processing, or the like.

FIG. 21Bis a block diagram illustrating a configuration memory that stores configuration data. For example, the on/off state of a switch184, which controls a connection of logic elements185, is controlled by a configuration memory186. InFIG. 21C, an example of a circuit configuration which can be used for the configuration memory186is illustrated. The configuration memory186includes transistors187and188and charge corresponding to the configuration data at a floating node FN is retained. The function of the switch184is achieved by switching the on/off state of the transistor188in accordance with the voltage of the floating node FN. The circuit configuration ofFIG. 21Ccan be similar to that of the memory cell140described in Embodiment 1, in which case it is useful to use a transistor containing an oxide semiconductor as the transistor187. With this structure, the configuration memory186of the FPGA183can be fabricated through the same process as the memory cell140.

FIGS. 22A and 22Billustrate configuration examples of the pixel121.

A pixel162A inFIG. 22Ais an example of a pixel included in a liquid crystal display device. The pixel162A includes a transistor191, a capacitor192, and a liquid crystal element193.

The transistor191serves as a switching element for controlling the connection between the liquid crystal element193and the signal line YL. The on/off state of the transistor191is controlled by a scan voltage input to its gate via the scan line XL.

The capacitor192is, for example, an element formed by stacking conductive layers.

The liquid crystal element193includes a common electrode, a pixel electrode, and a liquid crystal layer, for example. Alignment of a liquid crystal material of the liquid crystal layer is changed by the action of an electric field generated between the common electrode and the pixel electrode.

A pixel162B inFIG. 22Bis an example of a pixel included in an EL display device and includes a transistor194, a transistor195, and an EL element196. Note that inFIG. 22B, a current supply line ZL in addition to the scan line XL and the signal line YL is illustrated. The current supply line ZL is a wiring for supplying current to the EL element196.

The transistor194serves as a switching element for controlling the connection between a gate of the transistor195and the signal line YL. The on state of the transistor194is controlled by a scan voltage input to its gate through the scan line XL.

The transistor195has a function of controlling current flowing between the current supply line ZL and the EL element196, in accordance with voltage applied to the gate of the transistor195.

The EL element196is, for example, an element including a light-emitting layer provided between electrodes. The luminance of the EL element196can be controlled by the amount of current that flows in the light-emitting layer.

In this embodiment, an example of a cross-sectional structure of a semiconductor device in one embodiment of the present invention will be described with reference toFIGS. 23 to 35.

The semiconductor device described in the above embodiments can be fabricated by stacking a layer including a transistor using silicon and the like (Si transistor), a layer including a transistor using oxide semiconductor (OS transistor), and a wiring layer.

<Layer Structure of Semiconductor Device>

A schematic view of a layer structure of the semiconductor device is illustrated inFIG. 23. A transistor layer10, a wiring layer20, a transistor layer30, and a wiring layer40are stacked in this order. The wiring layer20shown as an example includes wiring layers20A and20B. Furthermore, the wiring layer40includes a plurality of wiring layers40A and40B. In the wiring layer20and/or the wiring layer40, a capacitor can be formed such that an insulator is sandwiched between conductors.

The transistor layer10includes a plurality of transistors12. The transistor12includes a semiconductor layer14and a gate electrode16. Although a layer processed into an island shape is shown as the semiconductor layer14, the semiconductor layer14may be a semiconductor layer obtained by element isolation from a semiconductor substrate. Although a gate electrode for a top-gate transistor is shown as the gate electrode16, the gate electrode16may be a gate electrode for a bottom-gate, a double-gate, or a dual-gate transistor, for example.

Each of the wiring layers20A and20B includes a wiring22that is embedded in an opening provided in an insulating layer24. The wiring22functions as a wiring for connecting elements such as transistors.

The transistor layer30includes a plurality of transistors32. The transistor32includes a semiconductor layer34and a gate electrode36. Although a layer processed into an island shape is shown as the semiconductor layer34, the semiconductor layer34may be a semiconductor layer obtained by element isolation from a semiconductor substrate. Although a gate electrode for a top-gate transistor is shown as the gate electrode36, the gate electrode36may be a gate electrode for a bottom-gate, a double-gate, or a dual-gate transistor, for example.

Each of the wiring layers40A and40B includes a wiring42that is embedded in an opening provided in an insulating layer44. The wiring42functions as a wiring for connecting elements such as transistors.

The semiconductor layer14is formed using a semiconductor material different from that for the semiconductor layer34. For example, given that the transistor12is a Si transistor and the transistor32is an OS transistor, the semiconductor material for the semiconductor layer14is silicon and that for the semiconductor layer34is an oxide semiconductor.

FIG. 24Aillustrates an example of a cross-sectional view of the semiconductor device.FIG. 24Bis an enlarged view of part of the structure inFIG. 24A.

The semiconductor device illustrated inFIG. 24Aincludes a capacitor300, a transistor400, and a transistor500.

The capacitor300is provided over an insulator602and includes a conductor604, an insulator612, and a conductor616.

The conductor604can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is particularly preferable to use tungsten. When the conductor604is formed concurrently with another component such as a plug or a wiring, a low-resistance metal material such as copper (Cu) or aluminum (Al) can be used.

The insulator612is provided to cover a side surface and a top surface of the conductor604. The insulator612has a single-layer structure or a stacked-layer structure formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or hafnium nitride.

The conductor616is provided to cover the side surface and the top surface of the conductor604with the insulator612positioned therebetween.

Note that the conductor616can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is particularly preferable to use tungsten. When the conductor616is formed concurrently with another component such as a conductor, a low-resistance metal material such as copper (Cu) or aluminum (Al) can be used.

With the structure where the conductor616included in the capacitor300covers the side surfaces and the top surface of the conductor604with the insulator612positioned therebetween, the capacitance per projected area of the capacitor300can be increased. Thus, the semiconductor device can be reduced in area, highly integrated, and miniaturized.

The transistor500is provided over a substrate301and includes a conductor306, an insulator304, a semiconductor region302that is part of the substrate301, and low-resistance regions308aand308bfunctioning as a source region and a drain region.

The transistor500is either a p-channel transistor or an n-channel transistor.

A channel formation region of the semiconductor region302, a region around the channel formation region, the low-resistance regions308aand308bserving as the source region and the drain region, and the like contain preferably a semiconductor such as a silicon-based semiconductor, more preferably single crystal silicon. Alternatively, they may contain a material containing germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), gallium aluminum arsenide (GaAlAs), or the like. They may contain silicon whose effective mass is controlled by applying stress to the crystal lattice and thereby changing the lattice spacing. Alternatively, the transistor500may be a high-electron-mobility transistor (HEMT) using GaAs and GaAlAs, or the like.

The low-resistance regions308aand308bcontain an element that imparts n-type conductivity (e.g., arsenic or phosphorus) or an element that imparts p-type conductivity (e.g., as boron) in addition to a semiconductor material used for the semiconductor region302.

The conductor306functioning as a gate electrode can be formed using a semiconductor material such as silicon containing an element that imparts n-type conductivity (e.g., arsenic or phosphorus) or an element that imparts p-type conductivity (e.g., boron), or a conductive material such as a metal material, an alloy material, or a metal oxide material.

Note that the threshold voltage can be adjusted by setting the work function with a material of the conductor. Specifically, it is preferable to use titanium nitride, tantalum nitride, or the like as the conductor. Furthermore, in order to ensure the conductivity and embeddability of the conductor, it is preferable to use a laminated layer of metal materials such as tungsten and aluminum as the conductor. In particular, tungsten is preferable in terms of heat resistance.

In the transistor500illustrated inFIG. 24A, the semiconductor region302(part of the substrate301) in which a channel is formed includes a protruding portion. Furthermore, the conductor306is provided to cover a side surface and a top surface of the semiconductor region302with the insulator304therebetween. Note that the conductor306may be formed using a material for adjusting a work function. The transistor500with such a structure is also referred to as a FIN transistor because it utilizes the protruding portion of the semiconductor substrate. An insulator serving as a mask for forming the protruding portion may be provided in contact with a top surface of the protruding portion. Although the case where the protruding portion is formed by processing part of the semiconductor substrate is described here, a semiconductor film having a protruding shape may be formed by processing an SOI substrate.

Note that the transistor500illustrated inFIG. 24Ais just an example; without limitation to the structure shown inFIG. 24A, an appropriate transistor can be used in accordance with a circuit configuration or a driving method. For example, a planar transistor500A illustrated inFIG. 25Amay be used.

An insulator320, an insulator322, an insulator324, and an insulator326are sequentially stacked and cover the transistor500.

The insulator322functions as a planarization film for eliminating a level difference caused by the transistor500or the like underlying the insulator322. A top surface of the insulator322may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to increase the level of planarity.

The insulator324functions as a barrier film that prevents hydrogen or impurities from diffusing from the substrate301, the transistor500, or the like into a region where the transistor400is formed. For example, the insulator324can be formed using nitride such as silicon nitride.

A conductor328, a conductor330, and the like that are electrically connected to the capacitor300or the transistor400are embedded in the insulator320, the insulator322, the insulator324, and the insulator326. The conductor328and the conductor330each function as a plug or a wiring. Note that a plurality of conductors functioning as plugs or wirings are collectively denoted by the same reference numeral in some cases, as described later. Furthermore, in this specification and the like, a wiring and a plug electrically connected to the wiring may be a single component. That is, there are cases where part of a conductor functions as a wiring and where part of a conductor functions as a plug.

For each of the plugs and wirings (e.g., the conductor328and the conductor330), a single-layer structure or a stacked-layer structure using a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is particularly preferable to use tungsten. It is particularly preferable to use a low-resistance conductive material such as aluminum or copper. The use of the above material can reduce the wiring resistance.

A wiring layer may be provided over the insulator326and the conductor330. For example, an insulator350, an insulator352, and an insulator354are sequentially stacked inFIG. 24A. A conductor356and a conductor358are embedded in the insulator350, the insulator352, and the insulator354. The conductor356and the conductor358each function as a plug or a wiring.

Note that for example, the insulator350is preferably formed using an insulator with a barrier property with respect to hydrogen, like the insulator324. The conductor356and the conductor358are preferably formed using a conductor with a barrier property with respect to hydrogen. The conductor with a barrier property with respect to hydrogen is formed in an opening in the insulator350with a barrier property with respect to hydrogen. This structure can separate the transistor500and the transistor400by the barrier layer, and thus can prevent diffusion of hydrogen from the transistor500to the transistor400.

As the conductor with a barrier property with respect to hydrogen, tantalum nitride can be used, for example. Stacking tantalum nitride and tungsten, which has high conductivity, can prevent diffusion of hydrogen from the transistor500while the conductivity of a wiring is ensured.

The transistor400is provided over the insulator354.FIG. 24Bis an enlarged view of the transistor400. Note that the transistor400illustrated inFIG. 24Bis just an example; without limitation to the structure shown inFIG. 24B, an appropriate transistor can be used in accordance with a circuit configuration or a driving method.

The transistor400is a transistor in which a channel is formed in a semiconductor layer containing an oxide semiconductor. The off-state current of the transistor400is low; thus, using the transistor400in a frame memory of a semiconductor device enables stored data to be retained for a long time.

An insulator210, an insulator212, an insulator214, and an insulator216are sequentially stacked over the insulator354. A conductor218, a conductor205, and the like are embedded in the insulator210, the insulator212, the insulator214, and the insulator216. The conductor218functions as a plug or a wiring that is electrically connected to the capacitor300or the transistor500. The conductor205functions as a gate electrode of the transistor400.

A material with a barrier property with respect to oxygen or hydrogen is preferably used for any of the insulators210,212,214, and216. In particular, in the case of using an oxide semiconductor in the transistor400, the reliability of the transistor400can be increased when an insulator including an oxygen excess region is provided as an interlayer film or the like around the transistor400. Accordingly, in order to diffuse oxygen from the interlayer film around the transistor400to the transistor400efficiently, layers with barrier properties with respect to hydrogen and oxygen are preferably provided such that the transistor400and the interlayer film are sandwiched therebetween.

For example, aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the barrier layers. Stacking the barrier layers achieves the function of diffusing oxygen more reliably.

An insulator220, an insulator222, and an insulator224are sequentially stacked over the insulator216. Part of a conductor244is embedded in the insulator220, the insulator222, and the insulator224. Note that the conductor218functions as a plug or a wiring that is electrically connected to the capacitor300or the transistor500.

Each of the insulators220and224is preferably an insulator containing oxygen, such as a silicon oxide film or a silicon oxynitride film. In particular, the insulator224is preferably an insulator containing excess oxygen (containing oxygen in excess of that in the stoichiometric composition). When such an insulator containing excess oxygen is provided in contact with an oxide230in which a channel region of the transistor400is formed, oxygen vacancies in the oxide can be filled. Note that the insulators220and224are not necessarily formed of the same material.

The insulator222preferably has a single-layer structure or a stacked-layer structure using an insulator containing silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3(BST), or the like. Aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide, for example, may be added to the insulator. The insulator may be subjected to nitriding treatment. A layer of silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the insulator.

Note that the insulator222may have a stacked-layer structure of two or more layers. In this case, the stacked layers are not necessarily formed of the same material and may be formed of different materials.

When the insulator222containing a high-k material is provided between the insulator220and the insulator224, electrons can be trapped in the insulator222under specific conditions, resulting in higher threshold voltage. In other words, the insulator222is negatively charged in some cases.

For example, when the insulator220and the insulator224are formed using silicon oxide and the insulator222is formed using a material having a lot of electron trap states (e.g., hafnium oxide, aluminum oxide, or tantalum oxide), electrons move from the oxide230toward the conductor205under the following conditions: the potential of the conductor205is kept higher than the potential of a source electrode and a drain electrode for 10 milliseconds or longer, typically 1 minute or longer at temperatures higher than the operating temperature or the storage temperature of the semiconductor device (e.g., at temperatures ranging from 125° C. to 450° C., typically from 150° C. to 300° C.). At this time, some of the moving electrons are trapped by the electron trap states of the insulator222.

In the transistor in which a necessary amount of electrons is trapped by the electron trap states of the insulator222, the threshold voltage is shifted in the positive direction. By controlling the voltage of the conductor205, the amount of electrons to be trapped can be controlled, and the threshold voltage can be controlled accordingly. The transistor400having this structure is a normally-off transistor, which is in a non-conduction state (also referred to as off state) even when the gate voltage is 0 V.

The treatment for trapping the electrons can be performed in the manufacturing process of the transistor. For example, the treatment can be performed at any step before factory shipment, such as after the formation of a conductor connected to a source conductor or a drain conductor of the transistor, after a wafer process, after a wafer-dicing step, or after packaging.

The insulator222is preferably formed using a material with a barrier property with respect to oxygen or hydrogen. The use of such a material can prevent release of oxygen from the oxide230and entry of impurities such as hydrogen from the outside.

An oxide230a, an oxide230b, and an oxide230care formed using a metal oxide such as an In-M-Zn oxide (M is Al, Ga, Y, or Sn). An In—Ga oxide or In—Zn oxide may be used as the oxide230. Hereinafter the oxide230a, the oxide230b, and the oxide230cmay be collectively referred to as the oxide230.

The oxide230according to the present invention is described below.

First, preferred ranges of the atomic ratio of indium, the element M, and zinc contained in an oxide according to the present invention are described with reference toFIGS. 26A to 26C. Note that the proportion of oxygen atoms is not shown inFIGS. 26A to 26C. The terms of the atomic ratio of indium, the element M, and zinc contained in the oxide are denoted by [In], [M], and [Zn], respectively.

InFIGS. 26A to 26C, broken lines indicate a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):1 (where −1≤α≤1), a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):2, a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):3, a line where the atomic ratio [In]:[M]:[Zn] is (1+a):(1−α):4, and a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):5.

Dashed-dotted lines indicate a line where the atomic ratio [In]:[M]:[Zn] is 1:1:β (where β≥0), a line where the atomic ratio [In]:[M]:[Zn] is 1:2:β, a line where the atomic ratio [In]:[M]:[Zn] is 1:3:β, a line where the atomic ratio [In]:[M]:[Zn] is 1:4:β, a line where the atomic ratio [In]:[M]:[Zn] is 2:1:β, and a line where the atomic ratio [In]:[M]:[Zn] is 5:1:β.

A dashed double-dotted line indicates a line where the atomic ratio [In]:[M]:[Zn] is (1+γ):2:(1−γ), where −1≤γ≤1. An oxide with the atomic ratio [In]:[M]:[Zn] of 0:2:1 or around 0:2:1 inFIGS. 26A to 26Ctends to have a spinel crystal structure.

FIGS. 26A and 26Billustrate examples of the preferred ranges of the atomic ratio of indium, the element M, and zinc contained in an oxide of one embodiment of the present invention.

FIG. 27illustrates an example of the crystal structure of InMZnO4with an atomic ratio [In]:[M]:[Zn] of 1:1:1. The crystal structure illustrated inFIG. 27is InMZnO4observed from a direction parallel to the b-axis. Note that a metal element in a layer that contains the element M, Zn, and oxygen (hereinafter this layer is referred to as “(M,Zn) layer”) inFIG. 27represents the element M or zinc. In that case, the proportion of the element M is the same as the proportion of zinc. The element M and zinc can be replaced with each other, and their arrangement is random.

Note that InMZnO4has a layered crystal structure (also referred to as layered structure) and includes two (M,Zn) layers that contain the element M, zinc, and oxygen with respect to one layer that contains indium and oxygen (hereinafter referred to as In layer), as illustrated inFIG. 27.

Indium and the element M can be replaced with each other. Accordingly, when the element M in the (M,Zn) layer is replaced by indium, the layer can also be referred to as (In,M,Zn) layer. In that case, a layered structure that includes two (In,M,Zn) layers with respect to one In layer is obtained.

An oxide with an atomic ratio [In]:[M]:[Zn] of 1:1:2 has a layered structure that includes three (M,Zn) layers with respect to one In layer. In other words, if [Zn] is larger than [In] and [M], the proportion of the (M,Zn) layer to the In layer becomes higher when the oxide is crystallized.

Note that in the case where the number of (M,Zn) layers with respect to one In layer is not an integer in the oxide, the oxide might have plural kinds of layered structures where the number of (M,Zn) layers with respect to one In layer is an integer. For example, in the case of [In]:[M]:[Zn]=1:1:1.5, the oxide may have a mix of a layered structure including one In layer for every two (M,Zn) layers and a layered structure including one In layer for every three (M,Zn) layers.

For example, when the oxide is deposited with a sputtering apparatus, a film having an atomic ratio deviated from the atomic ratio of a target is formed. In particular, [Zn] in the film might be smaller than [Zn] in the target depending on the substrate temperature in deposition.

A plurality of phases (e.g., two phases or three phases) exist in the oxide in some cases. For example, with an atomic ratio [In]:[M]:[Zn] around 0:2:1, two phases of a spinel crystal structure and a layered crystal structure are likely to exist. In addition, with an atomic ratio [In]:[M]:[Zn] around 1:0:0, two phases of a bixbyite crystal structure and a layered crystal structure are likely to exist. In the case where a plurality of phases exist in the oxide, a grain boundary might be formed between different crystal structures.

In addition, the oxide with a higher content of indium can have high carrier mobility (electron mobility). This is because in an oxide containing indium, the element M, and zinc, the s orbital of heavy metal mainly contributes to carrier transfer, and a higher indium content in the oxide enlarges a region where the s orbitals of indium atoms overlap; therefore, an oxide with a high indium content has higher carrier mobility than an oxide with a low indium content.

In contrast, when the indium content and the zinc content in an oxide become lower, the carrier mobility becomes lower. Thus, with an atomic ratio [In]:[M]:[Zn] of 0:1:0 or around 0:1:0 (e.g., a region C inFIG. 26C), insulation performance becomes better.

Accordingly, an oxide in one embodiment of the present invention preferably has an atomic ratio represented by a region A inFIG. 26A. With this atomic ratio, a layered structure with high carrier mobility and a few grain boundaries is easily obtained.

A region B inFIG. 26Brepresents an atomic ratio [In]:[M]:[Zn] of 4:2:3 to 4:2:4.1 and the vicinity thereof. The vicinity includes an atomic ratio [In]:[M]:[Zn] of 5:3:4, for example. An oxide with an atomic ratio represented by the region B is an excellent oxide that has particularly high crystallinity and high carrier mobility.

Note that a condition where an oxide has a layered structure is not uniquely determined by an atomic ratio. The atomic ratio affects difficulty in forming a layered structure. Even with the same atomic ratio, whether a layered structure is formed or not depends on a formation condition. Therefore, the illustrated regions each represent an atomic ratio with which an oxide has a layered structure, and boundaries of the regions A to C are not clear.

Next, the case where the oxide is used for a transistor is described.

When the oxide is used for a transistor, carrier scattering or the like at a grain boundary can be reduced; thus, the transistor can have high field-effect mobility. Moreover, the transistor can have high reliability.

An oxide with a low carrier density is preferably used for a transistor. For example, an oxide whose carrier density is lower than 8×1011/cm3, preferably lower than 1×1011/cm3, further preferably lower than 1×1010/cm3, and greater than or equal to 1×10−9/cm3is used.

A highly purified intrinsic or substantially highly purified intrinsic oxide has few carrier generation sources and thus can have a low carrier density. A highly purified intrinsic or substantially highly purified intrinsic oxide has a low density of defect states and accordingly has a low density of trap states in some cases.

Charge trapped by the trap states in the oxide takes a long time to be released and may behave like fixed charge. Thus, a transistor whose channel region is formed in an oxide with a high density of trap states has unstable electrical characteristics in some cases.

In view of the above, to obtain stable electrical characteristics of a transistor, it is effective to reduce the concentration of impurities in the oxide. To reduce the concentration of impurities in the oxide, the concentration of impurities in a film that is adjacent to the oxide is preferably reduced. Examples of impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, and silicon.

Here, the influence of impurities in the oxide is described.

When silicon or carbon, which is a Group 14 element, is contained in the oxide, defect states are formed in the oxide. Thus, the concentration of silicon or carbon in the oxide and around an interface with the oxide (the concentration obtained by secondary ion mass spectrometry (SIMS)) is set lower than or equal to 2×1018atoms/cm3, preferably lower than or equal to 2×1017atoms/cm3.

When the oxide contains alkali metal or alkaline earth metal, defect states are formed and carriers are generated in some cases. Thus, a transistor using an oxide that contains alkali metal or alkaline earth metal is likely to have normally-on characteristics. Accordingly, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide. Specifically, the concentration of alkali metal or alkaline earth metal in the oxide measured by SIMS is set lower than or equal to 1×1018atoms/cm3, preferably lower than or equal to 2×1016atoms/cm3.

When the oxide contains nitrogen, the oxide easily becomes n-type by generation of electrons serving as carriers and an increase of carrier density. Thus, a transistor in which an oxide containing nitrogen is used as a semiconductor is likely to have normally-on characteristics. For this reason, nitrogen in the oxide is preferably reduced as much as possible. For example, the nitrogen concentration in the oxide measured by SIMS is set lower than 5×1019atoms/cm3, preferably lower than or equal to 5×1018atoms/cm3, further preferably lower than or equal to 1×1018atoms/cm3, still further preferably lower than or equal to 5×1017atoms/cm3.

Hydrogen contained in an oxide reacts with oxygen bonded to a metal atom to be water, and thus causes an oxygen vacancy in some cases. Due to entry of hydrogen into the oxygen vacancy, an electron serving as a carrier is sometimes generated. Furthermore, in some cases, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron serving as a carrier. Thus, a transistor using an oxide that contains hydrogen is likely to have normally-on characteristics. Accordingly, it is preferred that hydrogen in the oxide be reduced as much as possible. Specifically, the hydrogen concentration in the oxide measured by SIMS is set lower than 1×1020atoms/cm3, preferably lower than 1×1019atoms/cm3, further preferably lower than 5×1018atoms/cm3, still further preferably lower than 1×1018atoms/cm3.

When an oxide with sufficiently reduced impurity concentration is used for a channel region in a transistor, the transistor can have stable electrical characteristics.

Next, the case where the oxide has a two-layer structure or a three-layer structure will be described. With reference toFIGS. 28A to 28C, the description is made on a band diagram of a layered structure of an oxide S1, an oxide S2, and an oxide S3and insulators that are in contact with the layered structure of an oxide S1, an oxide S2, and an oxide S3; a layered structure of the oxide S1and the oxide S2and insulators that are in contact with the layered structure of the oxide S1and the oxide S2; and a band diagram of a layered structure of the oxide S2and the oxide S3and insulators that are in contact with a layered structure of the oxide S2and the oxide S3.

FIG. 28Ais an example of a band diagram of a layered structure including an insulator I1, the oxide S1, the oxide S2, the oxide S3, and an insulator I2in the thickness direction.FIG. 28Bis an example of a band diagram of a layered structure including the insulator I1, the oxide S2, the oxide S3, and the insulator I2in the thickness direction.FIG. 28Cis an example of a band diagram of a layered structure including the insulator I1, the oxide S1, the oxide S2, and the insulator I2in the thickness direction. Note that for easy understanding, the band diagrams show the energy level of the conduction band minimum (Ec) of each of the insulator I1, the oxide S1, the oxide S2, the oxide S3, and the insulator I2.

The energy level of the conduction band minimum of each of the oxides S1and S3is closer to the vacuum level than that of the oxide S2. Typically, a difference in the energy level of the conduction band minimum between the oxide S2and each of the oxides S1and S3is preferably greater than or equal to 0.15 eV or greater than or equal to 0.5 eV, and less than or equal to 2 eV or less than or equal to 1 eV. That is, the difference in the electron affinity between the oxide S2and each of the oxides S1and S3is preferably greater than or equal to 0.15 eV or greater than or equal to 0.5 eV, and less than or equal to 2 eV or less than or equal to 1 eV.

As illustrated inFIGS. 28A to 28C, the energy level of the conduction band minimum of each of the oxides S1to S3is gradually varied. In other words, the energy level of the conduction band minimum is continuously varied or continuous junction is formed. To obtain such a band diagram, the density of defect states in a mixed layer formed at an interface between the oxides S1and S2or an interface between the oxides S2and S3is preferably made low.

Specifically, when the oxides S1and S2or the oxides S2and S3contain the same element (as a main component) in addition to oxygen, a mixed layer with a low density of defect states can be formed. For example, when the oxide S2is an In—Ga—Zn oxide, it is preferable to use an In—Ga—Zn oxide, a Ga—Zn oxide, gallium oxide, or the like as the oxides S1and S3.

At this time, the oxide S2serves as a main carrier path. Since the density of defect states at the interface between the oxides S1and S2and the interface between the oxides S2and S3can be made low, the influence of interface scattering on carrier conduction is small, and a high on-state current can be obtained.

When an electron is trapped in a trap state, the trapped electron behaves like fixed charge; thus, the threshold voltage of a transistor is shifted in the positive direction. The oxides S1and S3can make the trap state apart from the oxide S2. This structure can prevent the positive shift of the threshold voltage of the transistor.

A material whose conductivity is sufficiently lower than that of the oxide S2is used for the oxides S1and S3. Accordingly, the oxide S2, the interface between the oxides S1and S2, and the interface between the oxides S2and S3mainly function as a channel region. For example, an oxide with high insulation performance and the atomic ratio represented by the region C inFIG. 26Ccan be used as the oxides S1and S3. Note that the region C inFIG. 26Crepresents the atomic ratio [In]:[M]:[Zn] of 0:1:0 or around 0:1:0.

In the case where an oxide with the atomic ratio represented by the region A is used as the oxide S2, it is particularly preferable to use an oxide with an atomic ratio where [M]/[In] is greater than or equal to 1, preferably greater than or equal to 2 as each of the oxides S1and S3. In addition, it is suitable to use an oxide with sufficiently high insulation performance and an atomic ratio where [M]/([Zn]+[In]) is greater than or equal to 1 as the oxide S3.

One of a conductor240aand a conductor240bfunctions as a source electrode, and the other functions as a drain electrode.

The conductor240aand the conductor240bare formed to have a single-layer structure or a stacked-layer structure using any of metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, or an alloy containing any of these metals as a main component. For example, the conductor240aand the conductor240bcan have any of the following structures: a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a tantalum film or a tantalum nitride film is stacked, a two-layer structure in which an aluminum film is stacked over a titanium film, a two-layer structure in which an aluminum film is stacked over a tungsten film, a two-layer structure in which a copper film is stacked over a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked over a titanium film, a two-layer structure in which a copper film is stacked over a tungsten film, a three-layer structure in which a titanium film or a titanium nitride film, an aluminum film or a copper film, and a titanium film or a titanium nitride film are stacked in this order, and a three-layer structure in which a molybdenum film or a molybdenum nitride film, an aluminum film or a copper film, and a molybdenum film or a molybdenum nitride film are stacked in this order. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

An insulator250can have a single-layer structure or a stacked-layer structure using an insulator containing silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3(BST), or the like. Aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide, for example, may be added to the insulator. The insulator may be subjected to nitriding treatment. A layer of silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the insulator.

Like the insulator224, the insulator250is preferably an oxide insulator that contains oxygen in excess of that in the stoichiometric composition.

Note that the insulator250may have a stacked-layer structure similar to that of the insulator220, the insulator222, and the insulator224. When the insulator250contains an insulator in which a necessary amount of electrons is trapped by electron trap states, the threshold voltage of the transistor400can be shifted in the positive direction. The transistor400having this structure is a normally-off transistor, which is in a non-conduction state (also referred to as off state) even when the gate voltage is 0 V.

A conductor260functioning as a gate electrode can be formed using a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy containing any of these metals as its component, or an alloy containing any of these metals in combination, for example. Furthermore, one or both of manganese and zirconium may be used. A semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, or a silicide such as nickel silicide may be used. For example, the conductor260can have any of the following structures: a two-layer structure in which a titanium film is stacked over an aluminum film, a two-layer structure in which a titanium film is stacked over a titanium nitride film, a two-layer structure in which a tungsten film is stacked over a titanium nitride film, a two-layer structure in which a tungsten film is stacked over a tantalum nitride film or a tungsten nitride film, and a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order. Alternatively, an alloy film or a nitride film that contains aluminum and one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

The conductor260can also be formed using a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added. The conductor260can have a stacked-layer structure using the above light-transmitting conductive material and the above metal.

An insulator280is preferably formed using an oxide material from which oxygen is partly released due to heating.

As the oxide material from which oxygen is released due to heating, an oxide containing oxygen in excess of that in the stoichiometric composition is preferably used. Part of oxygen is released by heating from an oxide film containing oxygen more than that in the stoichiometric composition. The oxide film containing oxygen in excess of that in the stoichiometric composition is an oxide film in which the amount of released oxygen converted into oxygen atoms is greater than or equal to 1.0×1018atoms/cm3, preferably greater than or equal to 3.0×1020atoms/cm3in thermal desorption spectroscopy (TDS) analysis. Note that the temperature of the film surface in the TDS analysis preferably ranges from 100° C. to 700° C. or from 100° C. to 500° C.

As such a material, a material containing silicon oxide or silicon oxynitride is preferably used, for example. Alternatively, a metal oxide can be used. Note that in this specification, silicon oxynitride refers to a material that has a higher oxygen content than a nitrogen content, and silicon nitride oxide refers to a material that has a higher nitrogen content than an oxygen content.

The insulator280covering the transistor400may function as a planarization film that covers roughness thereunder.

An insulator270may be provided to cover the conductor260. When the insulator280is formed using an oxide material from which oxygen is released, the insulator270is formed using a material with a barrier property with respect to oxygen to prevent the conductor260from being oxidized by the released oxygen. With this structure, oxidation of the conductor260can be prevented, and oxygen released from the insulator280can be efficiently supplied to the oxide230.

An insulator282and an insulator284are sequentially stacked over the insulator280. The conductor244, a conductor246a, a conductor246b, and the like are embedded in the insulator280, the insulator282, and the insulator284. The conductor244functions as a plug or a wiring that is electrically connected to the capacitor300or the transistor500. Each of the conductors246aand246bfunctions as a plug or a wiring that is electrically connected to the capacitor300or the transistor400.

A material with a barrier property with respect to oxygen or hydrogen is preferably used for one or both of the insulator282and the insulator284. Accordingly, oxygen released from the interlayer film around the transistor400can be efficiently diffused into the transistor400.

The capacitor300is provided above the insulator284.

The conductor604and a conductor624are provided over the insulator602. The conductor624functions as a plug or a wiring that is electrically connected to the transistor400or the transistor500.

The insulator612is provided over the conductor604, and the conductor616is provided over the insulator612. The conductor616covers a side surface of the conductor604with the insulator612placed therebetween. That is, a capacitance is formed also on the side surface of the conductor604, so that the capacitance per projected area of the capacitor can be increased. Thus, the semiconductor device can be reduced in area, highly integrated, and miniaturized.

Note that the insulator602is provided at least in a region overlapped by the conductor604. For example, as in a capacitor300A illustrated inFIG. 25B, the insulator602may be provided only in regions overlapped by the conductor604or the conductor624so that the insulator602is in contact with the insulator612.

An insulator620and an insulator622are sequentially stacked over the conductor616. A conductor626and a conductor628are embedded in the insulator620, the insulator622, and the insulator602. Each of the conductors626and the conductor628functions as a plug or a wiring that is electrically connected to the transistor400or the transistor500.

The insulator620covering the capacitor300may function as a planarization film that covers roughness thereunder.

The above is the description of the structure example.

[Example of Manufacturing Method]

An example of a method for manufacturing the semiconductor device shown in the above structure example will be described below with reference toFIG. 29AtoFIG. 35.

First, the substrate301is prepared. A semiconductor substrate is used as the substrate301. For example, a single crystal silicon substrate (including a p-type semiconductor substrate or an n-type semiconductor substrate) or a compound semiconductor substrate containing silicon carbide or gallium nitride can be used. An SOI substrate may alternatively be used as the substrate301. The case where a single crystal silicon is used as the substrate301is described below.

Next, an element isolation layer is formed in the substrate301. The element isolation layer can be formed by a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or the like.

When a p-channel transistor and an n-channel transistor are formed on one substrate, an n-well or a p-well may be formed in part of the substrate301. For example, a p-well may be formed by adding an impurity element that imparts p-type conductivity (e.g., boron) to an n-type substrate301, and an n-channel transistor and a p-channel transistor may be formed on the same substrate.

Then, an insulator to be the insulator304is formed on the substrate301. For example, after surface nitriding treatment, oxidizing treatment may be performed to oxidize the interface between silicon and silicon nitride, whereby a silicon oxynitride film may be formed. For example, a silicon oxynitride film is obtained by performing oxygen radical oxidation after a thermal silicon nitride film is formed on the surface of the substrate301at 700° C. in an NH3atmosphere.

The insulator may be formed by a sputtering method, a chemical vapor deposition (CVD) method (including a thermal CVD method, a metal organic CVD (MOCVD) method, and a plasma-enhanced CVD (PECVD) method), a molecular beam epitaxy (MBE) method, an atomic layer deposition (ALD) method, a pulsed laser deposition (PLD) method, or the like.

Then, a conductive film to be the conductor306is formed. It is preferred that the conductive film be formed using a metal selected from tantalum, tungsten, titanium, molybdenum, chromium, niobium, and the like, or an alloy material or a compound material containing any of the metals as its main component. Alternatively, polycrystalline silicon to which an impurity such as phosphorus is added can be used. Further alternatively, a stacked-layer structure of a film of a metal nitride and a film of any of the above metals may be used. As a metal nitride, tungsten nitride, molybdenum nitride, or titanium nitride can be used. When the metal nitride film is provided, adhesiveness of the metal film can be increased; thus, separation can be prevented. Note that the threshold voltage of the transistor500can be adjusted by determining a work function of the conductor306, and therefore, a material of the conductive film is selected as appropriate in accordance with the characteristics that the transistor500needs to have.

The conductive film can be formed by a sputtering method, an evaporation method, a CVD method (including a thermal CVD method, an MOCVD method, and a PECVD method), or the like. A thermal CVD method, an MOCVD method, or an ALD method is preferably used to reduce plasma damage.

Next, a resist mask is formed over the conductive film by a photolithography process or the like, and an unnecessary portion of the conductive film is removed. After that, the resist mask is removed, whereby the conductor306is formed.

Here, a method for processing a film is described. To process a film finely, a variety of fine processing techniques can be used. For example, it is possible to use a method in which a resist mask formed by a photolithography process or the like is subjected to slimming treatment. Alternatively, it is possible that a dummy pattern is formed by a photolithography process or the like, a sidewall is formed on the dummy pattern, the dummy pattern is then removed, and a film is etched using the remaining sidewall as a resist mask. In order to achieve a high aspect ratio, anisotropic dry etching is preferably used for film etching. Alternatively, a hard mask formed of an inorganic film or a metal film may be used.

As light used to form the resist mask, it is possible to use light with the i-line (wavelength: 365 nm), the g-line (wavelength: 436 nm), or the h-line (wavelength: 405 nm) or light in which the i-line, the g-line, and the h-line are mixed. Alternatively, ultraviolet light, KrF laser light, ArF laser light, or the like can be used. Light exposure may be performed by liquid immersion exposure technique. As the light for the exposure, extreme ultraviolet (EUV) light or X-rays may be used. Moreover, an electron beam can be used instead of the light for the exposure. It is preferable to use EUV light, X-rays, or an electron beam because extremely minute processing can be performed. Note that a photomask is not needed in the case of performing exposure by scanning of a beam such as an electron beam.

An organic resin film having a function of improving the adhesion between a film to be processed and a resist film may be formed before the resist film serving as a resist mask is formed. The organic resin film can be formed by a spin coating method or the like to planarize a surface by covering a step under the film, and thus can reduce variation in thickness of the resist mask over the organic resin film. For fine processing in particular, a material serving as a film preventing reflection of light for the exposure is preferably used for the organic resin film. An example of the organic resin film having such a function includes a bottom anti-reflective coating (BARC) film. The organic resin film can be removed at the same time as the removal of the resist mask or after the removal of the resist mask.

After the conductor306is formed, a sidewall covering a side surface of the conductor306may be formed. The sidewall can be formed in such a manner that an insulator thicker than the conductor306is formed and subjected to anisotropic etching so that the insulator remains only on the side surface of the conductor306.

The insulator to be the insulator304is etched concurrently with the formation of the sidewall, whereby the insulator304is formed under the conductor306and the sidewall. Alternatively, the insulator304may be formed by etching the insulator with the conductor306or the resist mask for processing the conductor306used as an etching mask after the conductor306is formed. In this case, the insulator304is formed under the conductor306. Further alternatively, the insulator can be used as the insulator304without being processed by etching.

Then, an element that imparts n-type conductivity (e.g., phosphorus) or an element that imparts p-type conductivity (e.g., boron) is added to a region of the substrate301where the conductor306(and the sidewall) is not provided.

Subsequently, the insulator320is formed, and then heat treatment is performed to activate the aforementioned element that imparts conductivity.

The insulator320is formed with a single-layer structure or a stacked-layer structure using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride, for example. The insulator320is preferably formed using silicon nitride containing oxygen and hydrogen (SiNOH) because the amount of hydrogen released by heating can be increased. The insulator320can also be formed using silicon oxide with high step coverage that is formed by reacting tetraethyl orthosilicate (TEOS), silane, or the like with oxygen, nitrous oxide, or the like.

The insulator320can be formed by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, and a PECVD method), an MBE method, an ALD method, or a PLD method, for example. In particular, the insulator is formed preferably by a CVD method, more preferably a PECVD method because coverage can be further improved. A thermal CVD method, an MOCVD method, or an ALD method is preferably used to reduce plasma damage.

The heat treatment can be performed at a temperature higher than or equal to 400° C. and lower than the strain point of the substrate in an inert gas atmosphere such as a rare gas atmosphere or a nitrogen gas atmosphere or in a reduced-pressure atmosphere.

At this stage, the transistor500is completed.

Subsequently, the insulator322is formed over the insulator320. The insulator322can be formed using a material and a method similar to those used for forming the insulator320. Moreover, the top surface of the insulator322is planarized by a CMP method or the like (FIG. 29A).

Then, openings that reach the low-resistance region308a, the low-resistance region308b, the conductor306, and the like are formed in the insulator320and the insulator322(FIG. 29B). After that, a conductive film is formed to fill the openings (seeFIG. 29C). The conductive film can be formed by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, and a PECVD method), an MBE method, an ALD method, or a PLD method, for example.

Next, planarization treatment is performed on the conductive film to expose the top surface of the insulator322, whereby a conductor328a, a conductor328b, a conductor328c, and the like are formed (FIG. 29D). Note that arrows inFIG. 29Drepresent CMP treatment. In the specification and the drawings, the conductor328a, the conductor328b, and the conductor328ceach function as a plug or a wiring and are collectively referred to as “conductor328” in some cases. Note that in this specification, conductors functioning as a plug or a wiring are treated in a similar manner.

After the insulator322and the insulator324are formed over the insulator320, a conductor330a, a conductor330b, and a conductor330care formed by a damascene process or the like (FIG. 30A). The insulator322and the insulator324can be formed using a material and a method similar to those used for forming the insulator320. A conductive film to be the conductor330can be formed using a material and a method similar to those used for forming the conductor328.

Then, the insulator352and the insulator354are formed, and after that, a conductor358a, a conductor358b, and a conductor358care formed in the insulator352and the insulator354by a dual damascene process or the like (FIG. 30B). The insulator352and the insulator354can be formed using a material and a method similar to those used for forming the insulator320. A conductive film to be the conductor358can be formed using a material and a method similar to those used for forming the conductor328.

Next, the transistor400is formed in the following manner. After the insulator210is formed, the insulator212and the insulator214that have a barrier property against hydrogen or oxygen are formed. The insulator210can be formed using a material and a method similar to those used for forming the insulator320.

The insulator212and the insulator214can be formed by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, and a PECVD method), an MBE method, an ALD method, or a PLD method, for example. In particular, when the insulator212or the insulator214is formed by an ALD method, it is possible to form a dense insulator that includes a small number of defects such as cracks or pinholes or has a uniform thickness.

Then, the insulator216is formed over the insulator214. The insulator216can be formed using a material and a method similar to those used for forming the insulator210(FIG. 30C).

Next, openings that reach the conductor358a, the conductor358b, the conductor358c, and the like are formed in the insulator210, the insulator212, the insulator214, and the insulator216(FIG. 31A).

Subsequently, an opening is formed in a region of the insulator216where the gate electrode of the transistor400is to be formed. At this time, the openings that have been formed in the insulator216may be widened (FIG. 31B). By widening the openings formed in the insulator216, an adequate design margin for plugs or wirings to be formed in a later step can be provided.

After that, a conductive film is formed to fill the openings (seeFIG. 31C). The conductive film can be formed using a material and a method similar to those used for forming the conductor328. Then, planarization treatment is performed on the conductive film to expose a top surface of the insulator216, whereby a conductor218a, a conductor218b, a conductor218c, and the conductor205are formed (FIG. 32A). Note that arrows inFIG. 32Arepresent CMP treatment.

Then, the insulator220, the insulator222, and the insulator224are formed. The insulator220, the insulator222, and the insulator224can be formed using a material and a method similar to those used for forming the insulator210. It is particularly preferable to use a high-k material as the insulator222.

Next, an oxide to be the oxide230aand an oxide to be the oxide230bare sequentially formed. The oxides are preferably formed successively without exposure to the air.

After the oxide to be the oxide230bis formed, heat treatment is preferably performed. The heat treatment is performed at a temperature ranging from 250° C. to 650° C., preferably from 300° C. to 500° C. in an inert gas atmosphere, an atmosphere containing an oxidizing gas at 10 ppm or more, or a reduced-pressure state. Alternatively, the heat treatment may be performed in such a manner that heat treatment is performed in an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidization gas at 10 ppm or more, in order to compensate released oxygen. The heat treatment may be performed directly after the formation of the oxide to be the oxide230bor may be performed after the oxide to be the oxide230bis processed into an island shape. By the heat treatment, oxygen can be supplied from the insulator formed under the oxide230ato the oxide230aand the oxide230b, so that oxygen vacancies in the oxides can be reduced.

Then, a conductive film to be the conductor240aand the conductor240bis formed over the oxide to be the oxide230b. Subsequently, a resist mask is formed by a method similar to that described above, and an unnecessary portion of the conductive film is removed by etching. After that, unnecessary portions of the oxides are removed by etching using the conductive film as a mask. Then, the resist mask is removed. In this manner, a stack including the island-shaped oxide230a, the island-shaped oxide230b, and the island-shaped conductive film can be formed.

Subsequently, a resist mask is formed over the island-shaped conductive film by a method similar to that described above, and an unnecessary portion of the conductive film is removed by etching. Next, the resist mask is removed; thus, the conductor240aand the conductor240bare formed.

Then, an oxide to be the oxide230c, an insulator to be the insulator250, and a conductive film to be the conductor260are sequentially formed. Next, a resist mask is formed over the conductive film by a method similar to that described above, and an unnecessary portion of the conductive film is removed by etching, whereby the conductor260is formed.

Then, an insulator to be the insulator270is formed over the insulator to be the insulator250and the conductor260. The insulator to be the insulator270is preferably formed using a material with barrier properties against hydrogen and oxygen. Then, a resist mask is formed over the insulator by a method similar to that described above, and unnecessary portions of the insulator to be the insulator270, the insulator to be the insulator250, and the oxide to be the oxide230care removed by etching. After that, the resist mask is removed. Thus, the transistor400is completed.

Next, the insulator280is formed. The insulator280is preferably formed using an oxide containing oxygen in excess of that in the stoichiometric composition. After an insulator to be the insulator280is formed, planarization treatment using a CMP method or the like may be performed to improve the planarity of a top surface of the insulator.

To make the insulator280contain excess oxygen, the insulator280can be formed in an oxygen atmosphere, for example. Alternatively, a region containing excess oxygen may be formed by introducing oxygen into the insulator280that has been formed. Both the methods may be used in combination.

For example, oxygen (at least including any of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulator280that has been formed, whereby a region containing excess oxygen is formed. Oxygen can be introduced by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like.

A gas containing oxygen can be used for the oxygen introduction treatment. Examples of a gas containing oxygen include oxygen, dinitrogen monoxide, nitrogen dioxide, carbon dioxide, and carbon monoxide. In the oxygen introduction treatment, a rare gas may be contained in the gas containing oxygen. For example, a mixed gas of carbon dioxide, hydrogen, and argon can be used.

An example of the oxygen introduction treatment is a method of stacking an oxide over the insulator280using a sputtering apparatus. For example, when the insulator282is formed in an oxygen gas atmosphere with a sputtering apparatus, oxygen can be introduced into the insulator280while the insulator282is formed.

Next, the insulator284is formed. The insulator284can be formed using a material and a method similar to those used for forming the insulator210. The insulator284is preferably formed using aluminum oxide with a barrier property against oxygen or hydrogen, for example. In particular, when the insulator284is formed by an ALD method, it is possible to form a dense insulator that includes a small number of defects such as cracks or pinholes or has a uniform thickness.

By stacking the insulator284having dense film quality over the insulator282, excess oxygen introduced into the insulator280can be effectively sealed on the transistor400side (FIG. 32B).

Next, the capacitor300is formed in the following manner. First, the insulator602is formed over the insulator284. The insulator602can be formed using a material and a method similar to those used for forming the insulator210.

Then, openings that reach the conductor218a, the conductor218b, the conductor218c, the conductor240a, the conductor240b, and the like are formed in the insulator220, the insulator222, the insulator224, the insulator280, the insulator282, and the insulator284.

After that, a conductive film is formed to fill the openings, and planarization treatment is performed on the conductive film to expose a top surface of the insulator216. Thus, a conductor244a, a conductor244b, a conductor244c, the conductor246a, and the conductor246bare formed. The conductive film can be formed using a material and a method similar to those used for forming the conductor328.

Next, a conductive film604A is formed over the insulator602. The conductive film604A can be formed using a material and a method similar to those used for forming the conductor328. Then, a resist mask690is formed over the conductive film604A (FIG. 33A).

A conductor624a, a conductor624b, a conductor624c, and the conductor604are formed by etching the conductive film604A. Over-etching is performed as this etching treatment, whereby part of the insulator602can be removed at the same time (FIG. 33B). The depth of the removed portion of the insulator602needs to be larger than the thickness of the insulator612that is formed later. Formation of the conductor604with over-etching enables etching without an etching residue.

By switching the types of etching gases during the etching treatment, part of the insulator602can be removed efficiently.

As an alternative example, after the conductor604is formed, the resist mask690may be removed and part of the insulator602may be removed using the conductor604as a hard mask.

After the conductor604is formed, a surface of the conductor604may be subjected to cleaning treatment. By the cleaning treatment, an etching residue or the like can be removed.

When the insulator602and the insulator284are films of different types, the insulator284may serve as an etching stopper film. In this case, the insulator602is formed in regions overlapped by the conductor624or the conductor604as illustrated inFIG. 25B.

Then, the insulator612that covers the side surface and the top surface of the conductor604is formed (FIG. 34A). The insulator612has a single-layer structure or a stacked-layer structure formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or hafnium nitride.

For example, the insulator612preferably has a stacked-layer structure of a high-k material (e.g., aluminum oxide) and a material with high dielectric strength (e.g., silicon oxynitride). Such a structure enables the capacitor300to have sufficient capacitance due to the high-k material and increased dielectric strength due to the material with high dielectric strength. Thus, the capacitor300can be prevented from being damaged by electrostatic discharge, which leads to improvement in the reliability of the capacitor300.

Then, a conductive film616A is formed over the insulator612(FIG. 34A). The conductive film616A can be formed using a material and a method similar to those used for forming the conductor604. Subsequently, a resist mask is formed over the conductive film616A, and an unnecessary portion of the conductive film616A is removed by etching. After that, the resist mask is removed, whereby the conductor616is formed.

Then, the insulator620covering the capacitor300is formed (FIG. 34B). An insulator to be the insulator620can be formed using a material and a method similar to those used for forming the insulator602and the like.

Next, openings that reach the conductor624a, the conductor624b, the conductor624c, the conductor604, and the like are formed in the insulator620.

Then, a conductive film is formed to fill the openings, and planarization treatment is performed on the conductive film to expose a top surface of the insulator620. Thus, a conductor626a, a conductor626b, a conductor626c, and a conductor626dare formed. Note that the conductive film can be formed using a material and a method similar to those used for forming the conductor244.

Subsequently, a conductive film to be the conductor626is formed. The conductive film can be formed by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, and a PECVD method), an MBE method, an ALD method, a PLD method, or others. In particular, the conductive film is formed preferably by a CVD method, more preferably a PECVD method because coverage can be further improved. A thermal CVD method, an MOCVD method, or an ALD method is preferably used to reduce plasma damage.

The conductive film to be the conductor626can be formed using, for example, a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten; an alloy containing any of these metals as a component; or an alloy containing any of these metals in combination. Moreover, one or both of manganese and zirconium may be used. A semiconductor typified by polycrystalline silicon doped with an impurity element (e.g., phosphorus) or a silicide such as nickel silicide may be used. For example, the conductive film can have any of the following structures: a two-layer structure in which a titanium film is stacked over an aluminum film, a two-layer structure in which a titanium film is stacked over a titanium nitride film, a two-layer structure in which a tungsten film is stacked over a titanium nitride film, a two-layer structure in which a tungsten film is stacked over a tantalum nitride film or a tungsten nitride film, and a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order. Alternatively, an alloy film or a nitride film that contains aluminum and one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

Next, a resist mask is formed over the conductive film to be the conductor626by a method similar to that described above, and an unnecessary portion of the conductive film is removed by etching. Then, the resist mask is removed, whereby the conductor626a, the conductor626b, the conductor626c, and the conductor626dare formed.

Then, the insulator622is formed over the insulator620(FIG. 35). The insulator622can be formed using a material and a method similar to those used for forming the insulator602and the like.

Next, openings that reach the conductor626a, the conductor626b, the conductor626c, and the conductor626dare formed in the insulator622.

Then, a conductive film is formed to fill the openings, and planarization treatment is performed on the conductive film to expose a top surface of the insulator622; thus, a conductor628a, a conductor628b, a conductor628c, and a conductor628dare formed. Note that the conductive film can be formed using a material and a method similar to those used for forming the conductor244.

Through the above steps, the semiconductor device in one embodiment of the present invention can be manufactured.

In this embodiment, application examples of the semiconductor device described in the foregoing embodiment to a display panel, an application example of a display module, and application examples of the display module to an electronic device will be described with reference toFIGS. 36A and 36B,FIG. 37, andFIGS. 38A to 38E.

<Examples of Mounting Semiconductor Device on Display Panel>

Application examples of a semiconductor device functioning as a source driver IC to a display panel will be described with reference toFIGS. 36A and 36B.

In the example ofFIG. 36A, a source driver712and gate drivers712A and712B are provided around a display portion711of a display panel, and a source driver IC714including a semiconductor device is mounted on a substrate713as the source driver712.

The source driver IC714is mounted on the substrate713using an anisotropic conductive adhesive and an anisotropic conductive film.

The source driver IC714is connected to an external circuit board716via an FPC715.

In the example ofFIG. 36B, the source driver712and the gate drivers712A and712B are provided around the display portion711, and the source driver IC714is mounted on the FPC715as the source driver712.

Mounting the source driver IC714on the FPC715allows a larger display portion711to be provided over the substrate713, resulting in a narrower frame.

<Application Example of Display Module>

Next, an application example of a display module using the display panel illustrated inFIG. 36AorFIG. 36Bwill be described with reference toFIG. 37.

In a display module8000inFIG. 37, a touch panel8004connected to an FPC8003, a display panel8006connected to an FPC8005, a frame8009, a printed circuit board8010, and a battery8011are provided between an upper cover8001and a lower cover8002. Note that the battery8011, the touch panel8004, and the like are not provided in some cases.

The display panel illustrated inFIG. 36AorFIG. 36Bcan be used as the display panel8006inFIG. 37.

The shape and/or size of the upper cover8001and the lower cover8002can be changed as appropriate in accordance with the size of the touch panel8004and the display panel8006.

The touch panel8004can be a resistive touch panel or a capacitive touch panel and can overlap the display panel8006. A counter substrate (sealing substrate) of the display panel8006can have a touch panel function. Alternatively, a photosensor may be provided in each pixel of the display panel8006so that an optical touch panel is obtained. Further alternatively, an electrode for a touch sensor may be provided in each pixel of the display panel8006so that a capacitive touch panel is obtained. In such cases, the touch panel8004can be omitted.

The frame8009protects the display panel8006and functions as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board8010. The frame8009may also function as a radiator plate.

The printed circuit board8010is provided with a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. As a power source for supplying power to the power supply circuit, an external commercial power source or a separate power source using the battery8011may be used. The battery8011can be omitted in the case of using a commercial power source.

The display module8000may be additionally provided with a polarizing plate, a retardation plate, a prism sheet, or the like.

<Application Examples of Display Module to Electronic Device>

Next, an electronic device using the above display module for a display panel will be described. Examples of the electronic device include a computer, a portable information appliance (including a mobile phone, a portable game machine, and an audio reproducing device), electronic paper, a television device (also referred to as television or television receiver), and a digital video camera.

FIG. 38Aillustrates a portable information appliance that includes a housing901, a housing902, a first display portion903a, a second display portion903b, and the like. At least one of the housings901and902is provided with the display module including the semiconductor device of the foregoing embodiment. It is thus possible to obtain a portable information appliance with a smaller circuit area.

The first display portion903ais a panel having a touch input function, and for example, as illustrated in the left ofFIG. 38A, which of “touch input” and “keyboard input” is performed can be selected by a selection button904displayed on the first display portion903a. Since selection buttons with a variety of sizes can be displayed, the information appliance can be easily used by people of any generation. For example, when “keyboard input” is selected, a keyboard905is displayed on the first display portion903aas illustrated in the right ofFIG. 38A. Thus, letters can be input quickly by keyboard input as in a conventional information appliance, for example.

One of the first display portion903aand the second display portion903bcan be detached from the portable information appliance as shown in the right ofFIG. 38A. Providing the second display portion903bwith a touch input function makes the information appliance convenient because a weight to carry around can be further reduced and the information appliance can operate with one hand while the other hand supports the housing902.

The portable information appliance inFIG. 38Acan be equipped with a function of displaying a variety of information (e.g., a still image, a moving image, and a text image); a function of displaying a calendar, a date, the time, or the like on the display portion; a function of operating or editing information displayed on the display portion; a function of controlling processing by various kinds of software (programs); and the like. An external connection terminal (e.g., an earphone terminal or a USB terminal), a recording medium insertion portion, and the like may be provided on the back surface or the side surface of the housing.

The portable information appliance illustrated inFIG. 38Amay transmit and receive data wirelessly. Through wireless communication, desired book data or the like can be purchased and downloaded from an electronic book server.

Furthermore, the housing902inFIG. 38Amay be equipped with an antenna, a microphone function, and/or a wireless communication function so that the information appliance can be used as a mobile phone.

FIG. 38Billustrates an e-book reader910including electronic paper. The e-book reader910includes two housings911and912. The housing911and the housing912are provided with a display portion913and a display portion914, respectively. The housings911and912are connected by a hinge915and can be opened and closed with the hinge915as an axis. The housing911is provided with a power switch916, an operation key917, a speaker918, and the like. The display module including the semiconductor device of the foregoing embodiment is provided in at least one of the housings911and912. It is thus possible to obtain an e-book reader with a smaller circuit area.

FIG. 38Cillustrates a television device including a housing921, a display portion922, a stand923, and the like. The television device can be controlled by a switch of the housing921and/or a remote controller924. The display module including the semiconductor device of the foregoing embodiment is mounted on the housing921and the remote controller924. Consequently, it is possible to obtain a television device with a smaller circuit area.

FIG. 38Dillustrates a smartphone in which a main body930is provided with a display portion931, a speaker932, a microphone933, an operation button934, and the like. The display module including the semiconductor device of the foregoing embodiment is provided in the main body930. It is thus possible to obtain a smartphone with a smaller circuit area.

FIG. 38Eillustrates a digital camera including a main body941, a display portion942, an operation switch943, and the like. The display module including the semiconductor device of the foregoing embodiment is provided in the main body941. Thus, it is possible to obtain a digital camera with a smaller circuit area.

As described above, the display module including the semiconductor device of the foregoing embodiment is provided in the electronic device shown in this embodiment. It is thus possible to obtain an electronic device with a smaller circuit area.

(Supplementary Notes on Description in this Specification and the Like)

The following are notes on the description of Embodiments 1 to 4 and the structures in Embodiments 1 to 4.

<Notes on One Embodiment of the Present Invention Described in Embodiments>

One embodiment of the present invention can be constituted by appropriately combining the structure described in an embodiment with any of the structures described in the other embodiments. In the case where a plurality of structure examples are described in one embodiment, any of the structure examples can be combined as appropriate.

Note that a content (or part thereof) described in one embodiment can be applied to, combined with, or replaced with another content (or part thereof) described in the same embodiment and/or a content (or part thereof) described in another embodiment or other embodiments.

Note that in each embodiment, a content described in the embodiment is a content described with reference to a variety of diagrams or a content described with a text in the specification.

By combining a diagram (or part thereof) described in one embodiment with another part of the diagram, a different diagram (or part thereof) described in the embodiment, and/or a diagram (or part thereof) described in another embodiment or other embodiments, much more diagrams can be created.

<Notes on Description for Drawings>

In this specification and the like, terms for explaining arrangement, such as “over” and “under,” are used for convenience to indicate a positional relation between components with reference to drawings. The positional relation between components is changed as appropriate in accordance with a direction in which the components are described. Therefore, the terms for explaining arrangement are not limited to those used in the specification and can be changed to other terms as appropriate depending on the situation.

The term “over” or “below” does not necessarily mean that a component is placed directly on or directly below and directly in contact with another component. For example, the expression “electrode B over insulating layer A” does not necessarily mean that the electrode B is on and in direct contact with the insulating layer A and can also mean the case where another component is provided between the insulating layer A and the electrode B.

In a block diagram in this specification and the like, components are functionally classified and shown by blocks that are independent of each other. However, in an actual circuit and the like, such components are sometimes hard to classify functionally, and there is a case where one circuit is associated with a plurality of functions or a case where a plurality of circuits are associated with one function. Therefore, the segmentation of blocks in a block diagram is not limited by any of the components described in the specification and can be differently determined as appropriate depending on the situation.

In the drawings, the size, the layer thickness, or the region is determined arbitrarily for description convenience; therefore, embodiments of the present invention are not limited to the illustrated scale. Note that the drawings are schematically shown for clarity, and embodiments of the present invention are not limited to shapes or values shown in the drawings. For example, the following can be included: variation in signal, voltage, or current due to noise or difference in timing.

<Notes on Expressions that can be Rephrased>

In this specification and the like, the terms “one of a source and a drain” (or first electrode or first terminal) and “the other of the source and the drain” (or second electrode or second terminal) are used to describe the connection relation of a transistor. This is because the source and the drain of a transistor are interchangeable depending on the structure, operation conditions, or the like of the transistor. Note that the source or the drain of the transistor can also be referred to as a source (or drain) terminal, a source (or drain) electrode, or the like as appropriate depending on the situation.

In this specification and the like, the term “electrode” or “wiring” does not limit a function of a component. For example, an “electrode” is used as part of a “wiring” in some cases, and vice versa. Moreover, the term “electrode” or “wiring” can also mean a combination of a plurality of electrodes or wirings formed in an integrated manner.

In this specification and the like, “voltage” and “potential” can be replaced with each other. The term “voltage” refers to a potential difference from a reference potential. When the reference potential is a ground voltage, for example, “voltage” can be replaced with “potential.” A ground potential does not necessarily mean 0 V. Potentials are relative values, and a potential supplied to a wiring or the like is sometimes changed depending on the reference potential.

In this specification and the like, the terms “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, in some cases, the term “conductive film” can be used instead of “conductive layer,” and the term “insulating film” can be used instead of “insulating layer.”

This specification and the like show a 1T-1C circuit configuration where one pixel has one transistor and one capacitor and a 2T-1C circuit configuration where one pixel has two transistors and one capacitor; however, one embodiment of the present invention is not limited to these. It is possible to employ a circuit configuration where one pixel has three or more transistors and two or more capacitors. Moreover, a variety of circuit configurations can be obtained by formation of an additional wiring.

<Notes on Term Definitions>

The following are definitions of the terms mentioned in the above embodiments.

In this specification and the like, a switch is conducting or not conducting (is turned on or off) to determine whether current flows therethrough or not. Alternatively, a switch has a function of selecting and changing a current path.

For example, an electrical switch or a mechanical switch can be used. That is, a switch is not limited to a certain element and can be any element capable of controlling current.

Examples of an electrical switch include a transistor (e.g., a bipolar transistor and a MOS transistor), a diode (e.g., a PN diode, a PIN diode, a Schottky diode, a metal-insulator-metal (MIM) diode, a metal-insulator-semiconductor (MIS) diode, and a diode-connected transistor), and a logic circuit in which such elements are combined.

In the case of using a transistor as a switch, the “on state” of the transistor refers to a state in which a source and a drain of the transistor are regarded as being electrically short-circuited. The “off state” of the transistor refers to a state in which the source and the drain of the transistor are regarded as being electrically disconnected. In the case where a transistor operates just as a switch, there is no particular limitation on the polarity (conductivity type) of the transistor.

An example of a mechanical switch is a switch formed using a microelectromechanical system (MEMS) technology, such as a digital micromirror device (DMD). Such a switch includes an electrode that can be moved mechanically, and its conduction and non-conduction is controlled with movement of the electrode.

In this specification and the like, one pixel refers to one element whose brightness can be controlled, for example. Therefore, for example, one pixel corresponds to one color element by which brightness is expressed. Accordingly, in a color display device using color elements of red (R), green (G), and blue (B), the smallest unit of an image is formed of three pixels of an R pixel, a G pixel, and a B pixel.

Note that the number of colors for color elements is not limited to three, and more colors may be used. For example, RGBW (W: white) can be employed, or yellow, cyan, or magenta can be added to RGB.

In this specification and the like, a display element includes a display medium whose contrast, luminance, reflectivity, transmittance, or the like is changed by electrical or magnetic effect. Examples of a display element include an electroluminescent (EL) element, an LED chip (e.g., a white LED chip, a red LED chip, a green LED chip, and a blue LED chip), a transistor (a transistor that emits light depending on current), an electron emitter, a display element using a carbon nanotube, a liquid crystal element, electronic ink, an electrowetting element, an electrophoretic element, a plasma display panel (PDP), a display element using microelectromechanical systems (MEMS) (e.g., a grating light valve (GLV), a digital micromirror device (DMD), a digital micro shutter (DMS), Mirasol (registered trademark), an interferometric modulator display (IMOD) element, a MEMS shutter display element, an optical-interference-type MEMS display element, and a piezoelectric ceramic display), and a display element using a quantum dot. An example of a display device including EL elements is an EL display. Examples of a display device including electron emitters are a field emission display (FED) and an SED-type flat panel display (SED: surface-conduction electron-emitter display). Examples of a display device including liquid crystal elements include liquid crystal displays (e.g., a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, and a projection liquid crystal display). An example of a display device including electronic ink, electronic liquid powder (registered trademark), or electrophoretic elements is electronic paper. An example of a display device containing quantum dots in each pixel is a quantum dot display. Note that quantum dots may be provided not as display elements but as part of a backlight. The use of quantum dots enables display with high color purity. In a transflective liquid crystal display or a reflective liquid crystal display, some or all of pixel electrodes function as reflective electrodes. For example, some or all of pixel electrodes are formed to contain aluminum, silver, or the like. In such a case, a memory circuit such as SRAM can be provided under the reflective electrodes; thus, power consumption can be further reduced. In the case of using an LED chip, graphene or graphite may be provided under an electrode or a nitride semiconductor of the LED chip. Graphene or graphite may be a multilayer film in which a plurality of layers are stacked. When graphene or graphite is provided in this manner, a nitride semiconductor, for example, an n-type GaN semiconductor layer including crystals can be easily formed thereover. Furthermore, a p-type GaN semiconductor layer including crystals or the like can be provided thereover, and thus the LED chip can be formed. Note that an AlN layer may be provided between graphene or graphite and the n-type GaN semiconductor layer including crystals. The GaN semiconductor layers included in the LED chip may be formed by MOCVD. Note that when graphene is provided, the GaN semiconductor layers included in the LED chip can also be formed by a sputtering method. In a display element using MEMS, a drying agent may be provided in a space where the display element is sealed (e.g., a space between an element substrate where the display element is placed and a counter substrate opposite to the element substrate). Providing a drying agent can prevent MEMS and the like from becoming difficult to move and/or deteriorating easily because of moisture or the like.

In this specification and the like, when it is described that “A and B are connected to each other,” the case where A and B are electrically connected to each other is included in addition to the case where A and B are directly connected to each other. Here, the expression “A and B are electrically connected” means that electric signals can be transmitted and received between A and B when an object having any electric action exists between A and B.

This application is based on Japanese Patent Application serial No. 2016-014992 filed with Japan Patent Office on Jan. 29, 2016, the entire contents of which are hereby incorporated by reference.