Power matching system

A power matching system is applied to a central processing unit (CPU) power supply, which includes a power control chip to regulate the frequency of the signal applied to the CPU power supply. The power control chip includes a detecting pin. The power matching system includes a control unit and a control circuit. The control unit includes a platform controller hub (PCH) to obtain information concerning a CPU, a basic input output system (BIOS) to obtain a power rating of the CPU, and an integrated baseboard management controller (IBMC) to output a required signal to the control circuit according to the power rating established. The power control chip receives the required signal from the control circuit and regulates the frequency of the signal applied to the CPU power supply.

BACKGROUND

1. Technical Field

The present disclosure relates to a power matching system.

2. Description of Related Art

In many computer systems, a power supply can be designed to support different central processing units (CPUs), which have varying power ratings. In the case of switched-mode power supplies, the frequency of the signal applied to a DC-DC converter providing power to the CPU needs to be regulated for supporting different CPUs. However, in traditional designing, the maximum frequency of the signal to converter is selected as the default to support different CPUs, this wastes power when a CPU having a low power rating is used. Therefore, there is room for improvement in the art.

DETAILED DESCRIPTION

The disclosure, including the drawings, is illustrated by way of example and not by way of limitation. References to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one.

Referring toFIG. 1, a power matching system1is applied to a central processing unit (CPU) power supply3, which includes a power control chip30. The power control chip30is used for regulating the frequency of the signal applied to the CPU power supply3. The power matching system1in accordance with a first exemplary embodiment includes a control unit10and a control circuit20. The control unit10obtains the power rating of a CPU4and outputs a control signal to the control circuit20according to the power rating. The control circuit20receives the control signal and outputs a required signal to the power control chip30. The power control chip30receives the required signal from the control circuit20and regulates the frequency of the signal applied to the CPU power supply3.

The control unit10includes a platform controller hub (PCH)100, a basic input output system (BIOS)102connected to the PCH100, and an integrated baseboard management controller (IBMC)104connected to the BIOS102and also connected to the control circuit20. The PCH100can obtain information concerning the CPU4and store the information. The BIOS102reads the information from the PCH100and gains the power rating of the CPU4, and outputs this data to the IBMC104. The IBMC104receives the data and outputs the appropriate control signal to the control circuit20.

The control circuit20includes an electronic switch, such as a n-channel field effect transistor (FET) Q1, and resistors R1and R2. In other embodiments, the FET Q1may be a npn transistor. A gate of the FET Q1is connected to the IBMC104, to receive the control signal from the IBMC104. A source of the FET Q1is grounded. A drain of the FET Q1is connected to a detecting pin FS of the power control chip30through the resistor R1, to output the required signal. The resistor R2is connected between the detecting pin FS of the power control chip30and ground.

The power control chip30includes the detecting pin FS connected to the control circuit20, to receive the required signal from the control circuit20and regulate the frequency of the signal applied to the CPU power supply3. The type of the power control chip30may be ISL6364. In one embodiment, the power control chip30includes a constant current source, which outputs a current to the drain of the FET Q1through the detecting pin FS and the resistor R1, when the gate of the FET Q1receives a signal at a certain level, to turn on or turn off the FET Q1. At the same time, the control chip30can obtain different resistances through the detecting pin FS corresponding to the FET Q1being turned on or off. The control chip30can regulate the frequency of the signal applied to the CPU power supply3according to the received different resistances.

In one embodiment, the CPU power3can support two different CPUs, which have different power ratings. In use, when the power rating of the CPU4is 95 W, the frequency of the signal applied to the CPU power3should be regulated to 400 KHz. Now, the IBMC104outputs a high level signal to the FET Q1. The FET Q1is turned on. The power control chip30obtains the resistance of the resistors R1and R2connected in parallel through the detecting pin FS and regulates the frequency of the signal applied to the CPU power supply3to 400 KHz according to the resistance. When the power rating of the CPU4is 65 W, the frequency of the signal applied to the CPU power supply3should be regulated to 300 KHz. Now, the IBMC104outputs a low level signal to the FET Q1. The FET Q1is turned off. The power control chip30gains the resistance of the resistor R2through the detecting pin FS and regulates the frequency of the signal to the CPU power supply3to 300 KHz according to the resistance.

Referring toFIG. 2, in the second exemplary embodiment, the control circuit20includes a FET Q2and a resistor R3in place of the resistor R1and the FET Q1of the first exemplary embodiment. In other embodiments, the FET Q2may be a npn transistor. A gate of the FET Q2is connected to the IBMC104, to receive a control signal from the IBMC104. A source of the FET Q2is grounded. A drain of the FET Q2is connected to the detecting pin FS of the power control chip30through the resistor R3. In the second embodiment, the CPU power supply3can support three different CPU power ratings. In use, when the power rating of the CPU4is 130 W, the frequency of the signal applied to the CPU power supply3should be regulated to 500 KHz. Now, the IBMC104outputs high level signals to the FETs Q1and Q2. The FETs Q1and Q2are turned on. The power control chip30gains the resistance of the resistors R1, R2, and R3connected in parallel through the detecting pin FS and regulates the frequency of the signal applied to the CPU power supply3to 500 KHz according to the resistance. When the power rating of the CPU4is 95 W, the frequency of the signal applied to the CPU power supply3should be regulated to 400 KHz. Now, the IBMC104outputs a high level signal to the FET Q1and outputs a low level signal to the FET Q2. The FET Q1is turned on, and the FET Q2is turned off. The power control chip30gains the resistance of the resistors R1and R2connected in parallel through the detecting pin FS and regulates the frequency of the signal applied to the CPU power supply3to 400 KHz according to the resistance. When the power rating of the CPU4is 65 W, the frequency of the signal applied to the CPU power supply3should be regulated to 300 KHz. Now, the IBMC104outputs low level signals to the FET Q1and Q2. The FETs Q1and Q2are turned off. The power control chip30gains the resistance of the resistor R2through the detecting pin FS and regulates the frequency of the signal applied to the CPU power supply3to 300 KHz according to the resistance. Therefore, the frequency of the signal applied to the CPU power supply3can always be regulated according to the power rating of the CPU4.

The power matching system1can control the CPU power supply3to regulate the frequency of the signal applied to the CPU power supply3corresponding to different power ratings through the control unit10and the control circuit20. Therefore, the power matching system1improves the efficient use of the CPU power supply3.