Display device and a method of manufacturing the same

A display device includes an array substrate, a driving film and an adhesive member. The array substrate includes a first base substrate, a plurality of first signal pads formed on the first base substrate and a first dummy pad formed adjacent to the first signal pads. The driving film includes a base film, a plurality of output terminals formed on the base film and a first alignment mark formed adjacent to the output terminals. The adhesive member adheres the first signal pads to the output terminals, and adheres the first dummy pad to the first alignment mark.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2011-0031971, filed on Apr. 7, 2011, the disclosure of which is hereby incorporated by reference herein in its entirety.

BACKGROUND OF THE INVENTION

1. Technical Field

Example embodiments of the present invention relate to a display device and a method of manufacturing the display device. More particularly, example embodiments of the present invention relates to a display device including a flat display panel and a method of manufacturing the display device.

2. Description of the Related Art

A display device may include a display pane, a driving part and a printed circuit board (PCB). The display panel includes an array substrate including a plurality of data lines and a plurality of gate lines crossing the data lines formed on a substrate and an opposite substrate positioned opposite to the array substrate. The driving part drives the data lines and the gate lines. The PCB provides electrical signals to the display panel via the driving part.

The driving part may be mounted on the substrate (e.g., COG: Chip On Glass), or may be mounted on a separate film (e.g., COF: Chip On Film). For example, when the driving part is formed in the COF type, eight COFs to fourteen COFs may be used, and then a cost may be increased due to a number of the COFs.

Recently, a technique capable of reducing the number of the COFs by one second (½) or one third (⅓) has been developed. The technique may be very cost-efficient. However, the number of the COFs serving as the connecting part connecting the array substrate and the PCB may be reduced by ½ or ⅓, so that the COFs may be separable from the array substrate by impacts such as, for example, vibrations.

Thus, there is a need in the art for a display device having increased reliability and for a method of manufacturing the same.

SUMMARY OF THE INVENTION

Example embodiments of the present invention provide a display device increased reliability.

Example embodiments of the present invention also provide a method of manufacturing the display device.

According to an example embodiment of the present invention, a display device includes an array substrate, a driving film and an adhesive member. The array substrate includes a first base substrate, a plurality of first signal pads formed on the first base substrate and a first dummy pad formed adjacent to the first signal pads. The driving film includes a base film, a plurality of output terminals formed on the base film and a first alignment mark formed adjacent to the output terminals. The adhesive member adheres the first signal pads to the output terminals, and adheres the first dummy pad to the first alignment mark, respectively.

In an example embodiment, the first dummy pad may be formed outside the first signal pads.

In an example embodiment, the first alignment mark may include alignment portions defining an alignment groove. The array substrate may further comprise a second alignment mark aligned with the alignment groove. The first dummy pad may adhere to one of the alignment portions.

In an example embodiment, the display device may further comprise a printed circuit board (PCB) electrically connected to the array substrate. The PCB may include a second base substrate, a plurality of second signal pads formed on the second base substrate and a second dummy pad disposed adjacent to the second signal pads.

In an example embodiment, the driving film may include a plurality of input terminals and a third alignment mark. The plurality of input terminals may be spaced apart from the output terminals in a horizontal direction on the base film. The third alignment mark may be disposed adjacent to the input terminals. The second signal pads and the second dummy pad may adhere to the input terminals and the third alignment mark by the adhesive member, respectively.

In an example embodiment, the array substrate may include a plurality of pixel areas. The array substrate may further include a plurality of data lines electrically connected to the first signal pads respectively and a plurality of gate lines crossing the data lines. The pixel areas may include a first side corresponding to a portion of the gate line and a second side corresponding to a portion of the data line. The first side may be longer than the second side.

In an example embodiment, the array substrate may further include a protecting layer and a plurality of transparent electrodes. The protecting layer may be formed on the first base substrate on which the first signal pads are formed, and may include contact holes exposing the first signal pads. The plurality of transparent electrodes may be formed on the protecting layer, and may be electrically connected to the first signal pads via the contact holes, respectively.

In an example embodiment, the first dummy pad may include a same material as the transparent electrode on the protecting layer.

In an example embodiment, the array substrate may further include a protecting layer, an organic layer and a plurality of transparent electrodes. The protecting layer may be formed on the first base substrate on which the first signal pads are formed, and may include first contact holes exposing the first signal pads. The organic layer may be formed on the protecting layer, and may include second contact holes exposing the first signal pads. The plurality of transparent electrodes may be formed on the organic layer, and may be electrically connected to the first signal pads via the first and second contact holes, respectively.

In an example embodiment, the first dummy pad is formed on the organic layer and may include a same material as the transparent electrodes.

According to example embodiment of the present invention, a method of manufacturing a display device is provided. In the method, a plurality of first signal pads and a first dummy pad disposed adjacent to the first signal pads are formed on the first base substrate to form an array substrate. An adhesive is formed on the first signal pads and the first dummy pad. A driving film including a base film, a plurality of output terminals formed on the base film and a first alignment mark formed adjacent to the output terminals is disposed on the array substrate, and the output terminals and the first alignment mark may be adhered to the first signal pads and the first dummy pad, respectively.

In an example embodiment, in forming the array substrate, a plurality of gate lines may be formed on the first base substrate. A gate insulating layer may be formed on the first base substrate on which the gate lines are formed. A plurality of data lines crossing the gate lines and electrically connected to the first signal pads may be formed on the first base substrate on which the gate insulating layer is formed.

In an example embodiment, in forming the array substrate, a protecting layer may be formed on the first base substrate on which the data lines are formed. First contact holes exposing the signal pads may be formed in the protecting layer. A plurality of transparent electrodes electrically connected to the signal pads via the first contact holes respectively and the first dummy pad including a same material as the transparent electrode may be formed on the protecting layer.

In an example embodiment, in forming the array substrate, a protecting layer may be formed on the first base substrate on which the data lines are formed. An organic layer may be formed on the first base substrate on which the protecting layer is formed. First and second contact holes exposing the signal pads may be formed through the protecting layer and the organic layer, respectively. A plurality of transparent electrodes electrically connected to the signal pads respectively via the first and second contact holes and the first dummy pad including a same material as the transparent electrode may be formed on the protecting layer.

In an example embodiment, the array substrate may be divided into a plurality of pixel areas. The pixel areas may have a first side corresponding to a portion of the gate line and a second side corresponding to a portion of the data line. The first side may be longer than the second side.

In an example embodiment, the first alignment mark may include alignment portions defining an alignment groove. In adhering the output terminals and the first alignment mark with the first signal pads and the first dummy pad, respectively, the driving film including the first alignment mark may be disposed on the array substrate including a second alignment mark corresponding to the alignment groove, so that the first alignment mark may be aligned with the second alignment mark.

In an example embodiment, in the method, a printed circuit board including a plurality of second signal pads and a second dummy pad disposed adjacent to the second signal pads may be formed on a second base substrate may be formed. An adhesive may be formed on the second signal pads and the second dummy pad. The driving film may be disposed on the printed circuit board, and a plurality of input terminals opposite to the output terminals on the base film and a third alignment mark adjacent to the input terminals may adhere to the second signal pads and the second dummy pad, respectively to electrically connect the second signal pads to the first base substrate via the driving film.

According to an example embodiment of the present invention, a display device is provided. The display device includes an array substrate including a first base substrate, a plurality of first signal pads and a first alignment mark formed on the first base substrate and a first dummy pad formed outside of the first signal pads and adjacent to the first alignment mark, a printed circuit board (PCB), a driving film formed between the array substrate and the PCB and which electrically connects the array substrate to the PCB. The driving film including a base film including a first overlap area which overlaps the array substrate and a second overlap area spaced apart from the first overlap area and which overlaps the PCB, a plurality of output terminals and a plurality of input terminals formed on the first overlap area and the second overlap area of the base film, respectively, a driving chip disposed between the first and second overlap areas and electrically connected to the output terminals and the input terminals and a second alignment mark formed adjacent to the output terminals in the first overlap area. The display device further includes an adhesive member disposed between the array substrate and the driving film adhering the first signal pads and the first dummy pad of the array substrate to the output terminals and the second alignment mark of the driving film, respectively and disposed between the PCB and the driving film adhering the driving film to the PCB.

According to a display device and a method of manufacturing the same of example embodiments of the present invention, a dummy pad is formed on the array substrate, and the dummy pad adheres to an alignment mark of the driving film, so that the driving film is prevented from separating from the array substrate. Thus, the reliability of the display device may be increased.

In addition, when signal pads are formed on the array substrate, a dummy pad may be simultaneously formed on the array substrate. Thus, the adhesive strength between the driving film and the array substrate may be increased without adding another process.

FIG. 1is a plan view illustrating a display device according to an example embodiment of the present invention.FIG. 2is an exploded plan view of ‘A’ portion ofFIG. 1.

Referring toFIGS. 1 and 2, a display device1000includes, for example, a display panel100, a driving film200and an adhesive member300. The display device1000may further include a print circuit board (PCB)400. The display panel100includes an array substrate110, an opposite substrate120facing to the array substrate110and a liquid crystal layer (not shown) between the array substrate110and the opposite substrate120.

The array substrate110is divided into a display area DA overlapping the opposite substrate120and displaying an image and a peripheral area PA surrounding the display area DA. The array substrate110includes, for example, a first base substrate111, a gate line GL, a data line DL, a switching element SW, a pixel electrode PE1, a gate driver112, a gate fan-out part113, a data fan-out part114, a first signal pad115, a first alignment mark116and a dummy pad117.

For example, the gate line GL, the data line DL, the switching element SW and the pixel electrode PE1are formed in the display area DA of the array substrate110. The gate line GL extends in a first direction D1and arranges in a second direction D2crossing the first direction D1in parallel. The data line DL extends in the second direction D2and arranges in the first direction D2in parallel. It is noted that example embodiments of the present invention are not limited to the above-mentioned positions for the gate lines GL and data lines DL. Alternatively, for example, the data line DL may extend the first direction D1and be arranged in the second direction D2crossing the first direction D1in parallel and the gate line GL may extend in the second direction D2and be arranged in the first direction D2in parallel.

The switching element SW includes a gate electrode electrically connected to the gate line GL, a source electrode electrically connected to the data line DL and a drain electrode spaced apart from the source electrode and electrically connected to the pixel electrode PE1.

Adjacent gate lines GL to each other of the gate lines GL and adjacent data lines DL to each other of the data lines DL may define a pixel area P. The pixel area P may include a first side and a second side shorter than the first side. The display device1000according to the present example embodiment ofFIG. 1has a structure in which a distance between the adjacent gate lines GL to each other is narrower than that between the adjacent data lines DL. Thus, the first sides of the pixel area P which are relatively long sides are the gate lines GL between the adjacent data lines DL, and the second sides of the pixel area P which are relatively short sides are the data lines DL between the adjacent gate lines GL. It is noted that example embodiments of the present invention are not limited to above structure but rather, for example, alternatively, the distance between the adjacent gate lines GL may be wider than the distance between the adjacent data lines DL.

The display device1000according to the present example embodiment ofFIG. 1may have more gate lines GL and less data lines DL than those of a display device having a structure that a distance between the adjacent gate lines GL to each other is wider than that between the adjacent data lines DL. For example, the display device1000according to the present example embodiment ofFIG. 1includes two driving films200and the two driving films200include driving chips respectively, so that a number of the gate lines GL may be 1080×3, and the number of the data lines DL may be 1920. Alternatively, for example, the display device includes one driving film and the driving film includes a driving chip, so that the number of the gate lines GL may be 768×3, and the number of the data lines DL may be 1368. It is noted that example embodiments of the present invention are not limited to the above mentioned numbers for gate lines GL and data lines DL in the display device1000but rather, alternatively, for example, the number of data lines DL may be greater than the number of gate lines GL.

The gate driver112, the gate fan-out part113, the data fan-out part114, the first signal pad115, the first alignment mark116and the dummy pad117are formed in the peripheral area PA.

The gate driver112may be directly mounted on the first base substrate111.

The gate fan-out part113includes a gate fan-out line GPL. The gate fan-out line GPL is formed between the gate line GL and the gate driver112, and electrically connects the gate line GL to the gate driver112. The gate driver112may sequentially drive the gate line GL.

The data fan-out part113includes a data fan-out line DPL and at least one gate driving line GDL. The data fan-out line DPL is formed between the data line DL and the driving film200, and electrically connects the data line DL to the driving film200. The driving film200may provide an image signal to the data line DL.

The gate driving line GDL is formed between the gate driver112and the driving film200and is electrically connected to the gate driver112. The gate driving line GDL may provide a gate start signal, a gate driving signal a horizontal synchronization signal, etc.

The first signal pads115is electrically connected to the data fan-out lines DPL and the gate driving line GDL, and is formed in parallel to each other. The first signal pad115electrically connected to the data fan-out line DPL of the first signal pads115receives a data signal provided from the PCB400via the driving film200, and provides the data signal to the data line DL.

The first alignment mark116may be formed outside the first signal pads115. The first alignment mark116is aligned with a second alignment mark250of the driving film200to align the first signal pads115and outer terminals230of the driving film200.

The first dummy pad117may be formed outside the first signal pads115and adjacent to the first alignment mark116. The first dummy pad117may be formed outside the first signal pads115and in parallel to the first signal pads115. The number of the first dummy pad117may be at least one.

When the number of the first dummy pad117is one, a width of the first dummy pad117may be equal to or smaller than that of the second alignment mark250of the driving film200. Alternatively, there is a plurality of the first dummy pads117. When there is a plurality of the first dummy pads117, the width of the first dummy pad117may be smaller than that of the second alignment mark250of the driving film200. When there is a plurality of the first dummy pads117, the conductive ball of the adhesive member300interposed between the first dummy pad117and the second alignment mark250of the driving film200may move between the adjacent first dummy pads117, so that the adhesive strength between the first dummy pad117and the second alignment mark250of the driving film200may be increased.

When there is a plurality of the first dummy pads117, a pitch between the adjacent first dummy pads117to each other may be in a range of, for example, about 50 μm to about 100 μm. For example, the pitch between the adjacent first dummy pads117to each other may be in the range of about 70 μm to about 80 μm.

For example, when the pitch between the adjacent first dummy pads117to each other is about 70 μm, a width of the first dummy pad117may be about 35 μm and a distance between the adjacent first dummy pads117to each other may be about 35 μm. For another example, when the pitch between the adjacent first dummy pads117to each other is about 80 μm, the width of the first dummy pad117may be about 40 μm and the distance between the adjacent first dummy pads117to each other may be about 40 μm.

Alternatively, the first dummy pad117may not be parallel to the first signal pads115. Instead, the first dummy pad117may have various shapes to adhere to the second alignment pad250of the driving film200.

Thus, the first dummy pad117adheres to the second alignment mark250of the driving film200formed outside the first signal pads115, so that the adhesive strength between the array substrate110and the driving film200may be increased.

FIG. 3Ais a cross-sectional view taken along a line I-I′ and a line II-II′ ofFIG. 2.

Referring toFIGS. 2 and 3A, the array substrate110further includes, for example, a gate insulating layer LY1, a protecting layer LY2, an organic layer LY3and a transparent electrode TE1.

The gate insulating layer LY1is formed on the first base substrate111having the gate electrode GE and the gate line GL, and insulates the gate line GL and the data line DL.

The protecting layer LY2is formed on the gate insulating layer LY1having the switching element SW in the display area DA and the signal pads115in the peripheral area PA, and protects the switching element SW.

The organic layer LY3is formed on the protecting layer LY2, makes the array substrate110flat, and uniformly maintains a cell gap between the array substrate110and the opposite substrate120.

A first contact hole CH1is formed in the organic layer LY3in the display area DA, so that the pixel electrode PE1is electrically connected to the drain electrode DE via the first contact hole CH1. A second contact hole CH2and a third contact hole CH3are formed in the protecting layer LY2and the organic layer LY3in the peripheral area PA, so that the transparent electrodes TE1are electrically connected to the signal pads115via the second and third contact holes CH2and CH3.

The transparent electrode TE1is formed on the signal pads115exposed by the second and third contact holes CH2and CH3and the organic layer LY3to increase physical adhesion areas and electrical contact areas between the output terminal230and the signal pads115.

The first dummy pad117is formed outside the signal pads115on the organic layer LY3and disposed adjacent to the signal pads115. Alternatively, the first dummy pad117may be formed on another region of the first base substrate111instead of the organic layer LY3such as, for example, the protecting layer LY2.

The opposite substrate120may include, for example, a second base substrate121, a color filter layer122formed on the second substrate and displaying red, green and blue colors, a common electrode layer123formed on the color filter layer122and facing the pixel electrode PE1.

The driving film200may include, for example, a base film210, a driving chip220, an output terminal230, an input terminal240and a second alignment mark250.

The driving film200is disposed between the array substrate110and the PCB400, and electrically connects the array substrate110to the PCB400. The driving film200may provide, for example, a timing control signal, a gamma voltage signal, a gate control signal, a data control signal, from the PCB400to the array substrate110.

The base film210may include a material having small thermal expansive coefficient and outstanding elasticity. For example, the base film210may include one of polyimide, acrylic, polyether nitrile, polyether sulfone, polyethylene terephthalate, polyethylene naphthalate and polyvinyl chloride. The base film210includes the material having the outstanding elasticity, so that the base film210may not need other slits used for bending for itself. Thus, a manufacturing process may be simplified.

In addition, the base film210may not need another opening of mounting the driving chip220, so that the widths of the output terminals230and the input terminals240may be minimized.

The base film210may be divided into a first overlap area OA1overlapping the array substrate110and a second overlap area OA2spaced apart from the first overlap area OA1and overlapping the PCB400. The driving chip220may be disposed between the first and second overlap areas OA1and OA2. The driving chip220is electrically connected to the output terminals230and the input terminals240.

The output terminals230include, for example, copper (Cu) or Cu alloys. It is also noted that the output terminals may also be formed of other conductive materials or metals such as, for example, aluminum (Al) or Al alloys, or silver (Ag) or Ag alloys. The output terminals230are formed, for example, in the first overlap area OA1on the base film210in parallel to each other. The output terminals230correspond to the first signal pads115, respectively, so that the output terminals230overlap the first signal pads115respectively when the first overlap area OA1of the driving film200overlap the array substrate110. Thus, the output terminals230may adhere to the first signal pads115by the adhesion member300, respectively.

The output terminals230may provide signals provided from the driving chip220to the data line DL and the gate driver112.

The input terminals240include, for example, Cu or Cu alloys. It is also noted that the input terminals240may also be formed of other conductive materials or metals such as, for example, aluminum (Al) or Al alloys, or silver (Ag) or Ag alloys. The input terminals240are formed, for example, in the second overlap area OA2on the base film210in parallel to each other, and face to the output terminals230. The input terminals240correspond to the second signal pads420of the PCB400, so that the input terminals240overlap the second signal pads420when the second overlap area OA2of the driving film200overlaps the PCB400. Thus, the input terminals240may adhere to the second signal pads420by the adhesive member300, respectively.

The input terminal240may provide the signals provided from the PCB400to the driving chip220.

The second alignment mark250is formed outside the output terminals230in the first overlap area OA1. The second alignment mark250includes at least one alignment portion, and the alignment portion may define an alignment groove. For example, referring toFIG. 2, when there are two alignment portions, the two alignment portions may define the alignment groove for aligning the first alignment mark116. The first alignment mark116of the array substrate110is aligned with the second alignment mark250of the driving film200, so that the array substrate110may be aligned with the driving film200.

The first dummy pad117formed outside the first signal pads115and adjacent to the first alignment mark116may adhere to at least one of the alignment portions251and252of the second alignment mark250.

The adhesive member300may be, for example, anisotropic conductive film (ACF) or anisotropic conductive paste (ACP). Example embodiments of the present invention are not limited to the above mentioned materials for the adhesive member300but rather the adhesive member300may include other adhesives known in the art such as, for example, non-conductive films (NCF) or non-conductive paste (NCP). In the present embodiment, the adhesive member300includes, for example, a conductive ball in an adhesive material. The adhesive member300is disposed between the array substrate110and the driving film200to adhere the driving film200to the array substrate110. For example, the adhesive member300is disposed on the first signal pads115and the first dummy pad117of the array substrate110to adhere the output terminals230and the second alignment mark250of the driving film200to the first signal pads115and the first dummy pad117of the array substrate110respectively. The adhesive member300may physically adhere the first signal pads115to the output terminals230, while the adhesive member300electrically connects the first signal pads115to the output terminals230by the conductive ball.

FIG. 3Bis a cross-sectional view taken along a line III-III′ ofFIG. 2.

Referring toFIGS. 2 and 3B, the PCB400includes, for example, a third base substrate410, a second signal pad420, a third alignment mark430and a second dummy pad440. The PCB400provides the signals provided from an external device to the array substrate110via the driving film200.

The second signal pads420are formed on the third base substrate410in parallel to each other. The third alignment mark430and the second dummy pad440are formed outside the second signal pads420. The second dummy pad440is formed adjacent to the third alignment mark430.

In addition, the driving film200may further comprise, for example, a fourth alignment mark260aligning with the third alignment mark430of the PCB400, a protecting layer disposed on the output terminals230and the input terminals240and protecting the output terminals230and the input terminals240and an insulating resin filled between the base film210and the driving chip220and protecting the driving chip220from an external impact. The fourth alignment mark260is formed outside the input terminals240in the second overlap area OA2of the driving film200. The fourth alignment mark260may include at least one alignment portion, and the alignment portion may define an alignment groove. For example, referring toFIG. 2, when a number of the alignment portions is two, the alignment portions261and262may define the alignment groove of aligning the third alignment mark430of the PCB400. The fourth alignment mark260of the driving film200is aligned with the third alignment mark430of the PCB400, and the driving film200may be aligned with the PCB400.

The second dummy pad440formed outside the second signal pads420and adjacent to the third alignment mark430may adhere one of the alignment portions261and262of the fourth alignment mark260by the adhesive member300. The adhesive member300is disposed between the PCB400and the driving film200to adhere the driving film200to the PCB400. For example, the adhesive member300is disposed on the second signal pad240and the second dummy pad440to adhere the input terminals240and the fourth alignment mark260to the second signal pad420and the second dummy pad440of the PCB400, respectively.

FIGS. 4A to 4Dare cross-sectional views illustrating a method of manufacturing the display device ofFIG. 3A.

Referring toFIG. 4A, a gate pattern is formed on the base substrate111. The gate pattern may include, for example, a gate electrode GE, the gate line GL and the gate fan-out line GPL (shown inFIG. 1) and a gate pad and a storage electrode (as not shown). The gate insulating layer LY1is formed on the first base substrate111on which the gate pattern is formed. The semiconductor layer (SP), the ohmic contact layer (OC) and a data pattern are sequentially formed on the first base substrate111on which the gate insulating layer LY1is formed. The data pattern include, for example, the source electrode (SE), a drain electrode DE, the data line DL, the data fan-out line DPL and the gate driving line GDL (shown inFIG. 1) and the signal pad115(shown inFIG. 2).

Referring toFIG. 4B, the protecting layer LY2and the organic layer LY3are sequentially formed on the first base substrate111on which the data pattern is formed. A mask MS including a transmission portion T and a block portion B is disposed over the first base substrate111on which the protecting layer LY2and the organic layer LY3are formed. When the light is provided to the mask MS, the organic layer LY3is exposed and developed. The protecting layer LY2is etched using the organic layer LY3as a mask.

Referring toFIG. 4C, the protecting layer LY2and the organic layer LY3corresponding to the transmission portion T are removed, and then the first to third contact holes CH1, CH2and CH3are formed in the organic layer LY3and the protecting layer LY2. The transparent electrode pattern is formed on the first base substrate111on which the first to third contact holes CH1, CH2and CH3is formed. The transparent pattern includes, for example, a pixel electrode PE1, a transparent electrode TE1and the first dummy pattern117.

For example, the pixel electrode PE1is formed on the organic layer LY3partially exposing the drain electrode DE through the first contact hole CH1in the display area DA. The pixel electrode PE1is electrically connected to the drain electrode DE through the first contact hole CH1. The transparent electrode TE1is formed on the organic layer LY3exposing the first signal pads115through the second and third contact holes CH2and CH3in the peripheral area PA. The transparent electrode TE1is electrically connected to the first signal pads115through the second and third contact holes CH2and CH3. The first dummy pad117is formed outside the signal pads115on the organic layer LY3in the peripheral area PA.

Referring toFIG. 4D, the array substrate110including the first base substrate111on which the transparent pattern is assembled with the opposite substrate120. The liquid crystal is injected between the array substrate110and the opposite substrate120which are assembled with each other, so that the liquid crystal layer is formed therebetween. Alternatively, the liquid crystal is dropped on the array substrate110including the first base substrate111on which the transparent pattern, and then the array substrate on which the liquid crystal is dropped may be assembled with the opposite substrate120.

The adhesive member300is disposed on the transparent electrode PE1, the first dummy pad117and the first alignment mark116of the array substrate110assembled with the opposite substrate120.

ReferringFIG. 3Aagain, the driving film200is disposed on the array substrate110on which the adhesive member300is disposed, so that the output terminals230face the transparent electrodes TE1, respectively, and the second alignment mark250and the alignment groove defined by the alignment portions face to the first dummy pad117and the first alignment mark116, respectively. The driving film200is aligned on the array substrate110by the first and second alignment marks116and250, while the output terminals230adhere to the transparent electrodes TE1, respectively, and the second alignment mark250adheres to the first dummy pad117. The first overlap area OA1of the driving film200adheres to the array substrate110.

Referring toFIG. 3Bagain, the adhesive member300is disposed on the second signal pad420, the third alignment mark430and the second dummy pad440of the PCB400. The driving film200is disposed on the PCB400on which the adhesive member300is disposed, so that the input terminals240face the second signal pad420, respectively, and the fourth alignment mark260and the alignment groove defined the alignment portions of the fourth alignment mark260face the second dummy pad440and the third alignment mark430, respectively. The driving film200is aligned on the PCB400by the third and fourth alignment marks430and260, while the input terminals240adhere to the second signal pads420, respectively, and the fourth alignment mark260adheres to the second dummy pad440. Thus, the second overlap area OA2of the driving film200adheres to the PCB400.

The display device1000according to the present example embodiment ofFIG. 1includes, for example, the first dummy pad117formed on the organic layer LY3, and the first dummy pad117adheres to the second alignment mark250of the driving film200, so that adhesive strength between the array substrate110and the driving film200may be increased.

FIG. 5Ais a cross-sectional view illustrating a display device according to an example embodiment of the present invention taken along a line I-I′ and a line II-IF ofFIG. 2.FIG. 5Bis a cross-sectional view illustrating a display device according to an example embodiment of the present invention taken along a line ofFIG. 2.

The display device according to the present example embodiment inFIGS. 5A and 5Bis substantially the same as the display device illustrated inFIG. 1except for forming a first dummy pad on a protecting layer, and thus the same elements will refer to the display device illustrated inFIG. 1except for the forming a first dummy pad on a protecting layer.

Referring toFIGS. 5A and 5B, an array substrate110afurther includes, for example, a gate insulating layer LY1, a protecting layer LY2and a plurality of transparent electrode TE2.

The gate insulating layer LY1is formed on a first base substrate111on which a gate electrode of a switching element SW is formed to insulate the gate electrode GE with a source electrode SE and a drain electrode DE of the switching element SW.

The protecting layer LY2is formed on the gate insulating layer LY1on which the switching element SW is formed in the display area DA and the signal pads115are foamed in the peripheral area PA, and protects the switching element SW.

A first contact hole CH4is formed in the protecting layer LY2formed in the display area DA, and a pixel electrode PE2is electrically connected to the drain electrode DE through the first contact hole CH4. Second and third contact holes CH5and CH6are formed in the protecting layer LY2formed in the peripheral area PA, transparent electrodes TE2are electrically connected to the signal pads115through the second and third contact holes CH5and CH5, respectively.

The transparent electrodes TE2are formed on the signal pads115exposed by the second and third contact holes CH5and CH6and the protecting layer LY2to increase a physical contact area and an electrical contact area between the output terminals230and the signal pads115.

The first dummy pad117ais formed outside the signal pads115on the protecting layer LY2, and disposed adjacent to the signal pads115. For example, the first dummy pad117amay include a same material with the transparent electrode TE2on the protecting layer LY2. The transparent electrode TE2may include, for example, indium-tin-oxide (ITO).

FIGS. 6A and 6Bare cross-sectional views illustrating a method of manufacturing the display device ofFIGS. 5A and 5B.

Referring toFIGS. 4A and 6B, the protecting layer LY2and a photoresist layer PR are sequentially formed on the first base substrate111on which a data pattern is formed. A mask MS including a transmission portion T and a block portion B is disposed over the first base substrate111on which the protecting layer LY2and the photoresist layer PR. The light is provided to the mask MS, and then the photoresist layer PR is exposed and developed. The protecting layer LY2is etched using the photoresist layer PR as a mask. The photoresist layer PR is stripped.

Referring toFIG. 6B, the protecting layer LY2corresponding to the transmission portion T is removed, so that the first to third contact holes CH4, CH5and CH6are formed. A transparent electrode pattern is formed on the first base substrate111on which the first to third contact holes CH4, CH5and CH6are formed. The transparent electrode pattern includes, for example, the pixel electrode PE2, the transparent electrode TE2and the first dummy pattern117b.

For example, the pixel electrode PE2is foamed on the protecting layer LY2partially exposing the drain electrode DE through the first contact hole CH4in the display area DA. The pixel electrode PE2is electrically connected to the drain electrode DE through the first contact hole CH4. The transparent electrode TE2is formed on the protecting layer LY2exposing the signal pads115through the second and third contact holes CH5and CH6in the peripheral area PA. The transparent electrode TE2is electrically connected to the signal pad115through the second and third contact holes CH5and CH6. The first dummy pad117bis formed outside the signal pads115on the protecting layer LY2in the peripheral area PA.

The process that the array substrate110including the first base substrate111on which the transparent electrode pattern is formed is assembled with the opposite substrate120and the process in which the driving film200is aligned with and adhered to the array substrate110and the PCB400are substantially the same as the processes of the method of manufacturing the display device according toFIG. 1. Thus, any repetitive explanation concerning the above processes will be omitted.

The display device according to the present example embodiment ofFIGS. 5A and 5Bincludes the first dummy pad117aformed on the protecting layer LY2and the first dummy pad117aadheres to the second alignment mark250of the driving film200, so that the adhesive strength between the array substrate110aand the driving film200may be increased.

According to example embodiments of the invention, a dummy pad is formed on the array substrate, and the dummy pad adheres to an alignment mark of the driving film, so that the driving film is prevented from separating from the array substrate. Thus, reliability of the display device may be increased.

In addition, when signal pads are formed on the array substrate, a dummy pad may be simultaneously formed on the array substrate. Thus, adhesive strength between the driving film and the array substrate may be increased without adding another process.