Methods of identifying space within integrated circuit structure as mandrel space or non-mandrel space

The disclosure is directed to methods of identifying a space within an integrated circuit structure as a mandrel space or a non-mandrel space. One method may include: identifying a space between freestanding spacers as being one of: a former mandrel space created by removal of a mandrel from between the freestanding spacers or a non-mandrel space between adjacent mandrels prior to removal of the mandrel, based on a line width roughness of the space, wherein the line width roughness represents a deviation of a width of the space from a centerline axis along a length of the space.

BACKGROUND

Technical Field

The present disclosure relates to integrated circuit structures, or more particularly, to methods of identifying a space within an integrated circuit structure as a mandrel space or a non-mandrel space.

Related Art

In the microelectronics industry as well as in other industries involving construction of microscopic structures micromachines, magnetoresistive heads, continued desire to reduce the size of structural features and microelectronic devices and/or to provide greater amount of circuitry for a given chip size. Miniaturization in general allows for increased performance (more processing per clock cycle and less heat generated) at lower power levels and lower cost. Present technology is at atomic; level scaling of certain micro-devices such as logic gates, FITS and capacitors, for example. Circuit chips with hundreds of millions of such devices are common.

In order to achieve further size reductions exceeding the physical limits of trace lines and micro-devices that are embedded upon and within their semiconductor substrates, techniques that exceed lithographic capabilities have been employed. Sidewall image transfer (SIT), also known as self-aligned double patterning (SADP), is one such technique to generate sub-lithographic structures. SIT involves the usage of a sacrificial structure e.g., a mandrel, typically composed of a polycrystalline silicon and a sidewall spacer (such as silicon dioxide or silicon nitride, for example) having a thickness less than that permitted by the current lithographic ground rules formed on the sides of the mandrel (e.g., via oxidization or film deposition and etching). After removal of the mandrel, the remaining sidewall spacer is used as a hard mask (HM) to etch the layer(s) below, for example, with a directional reactive ion etch (RIE). Since the sidewall spacer has a sub-lithographic lateral dimension, width, (less than lithography allows), the structure formed in the layer below will also have a sub-lithographic lateral dimension.

SUMMARY

A first aspect of the disclosure is directed to a method. The method may include: identifying a space between freestanding spacers as being one of: a mandrel space created by removal of a mandrel from between the freestanding spacers or a non-mandrel space between adjacent mandrels prior to removal of the mandrel, based on a line width roughness of the space, wherein the line width roughness represents a deviation of a width of the space from a centerline axis along a length of the space.

A second aspect of the disclosure is directed to a method. The method may include: providing an integrated circuit structure having: a first mandrel over a substrate and a second mandrel over the substrate laterally adjacent to the first mandrel; a pair of spacers on opposing sides of each mandrel over the substrate; and a non-mandrel space between adjacent spacers of the first and second mandrels, removing each mandrel to expose the substrate thereunder, thereby defining a mandrel space between the pair of spacers of each mandrel; determining a line width roughness of each of the non-mandrel space and the mandrel space, wherein the line width roughness represents a deviation of a width of the space from a centerline axis along a length of the space; and identifying which space constitutes the non-mandrel space between the adjacent spacers and the mandrel space based on the line width roughness of the non-mandrel space and the mandrel space.

A third aspect of the disclosure is directed to a computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer device to cause the computer device to: identify a space between freestanding spacers as being one of: a mandrel space created by removal of a mandrel from between the freestanding spacers or a non-mandrel space between adjacent mandrels prior to removal of the mandrel, based on a line width roughness of the space, wherein the line width roughness represents a deviation of a width of the space from a centerline axis along a length of the space.

The foregoing and other features of the disclosure will be apparent from the following more particular description of embodiments of the disclosure.

DETAILED DESCRIPTION

The present disclosure relates to integrated circuit structures, or more particularly, to methods of identifying a space within an integrated circuit structure as a mandrel space or a non-mandrel space. Specifically, mandrel and non-mandrel spaces may be identified by determining a line width roughness of each space. Once mandrel and non-mandrel spaces are identified, parameters of the integrated circuit structure design of a subsequently formed integrated circuit structure may be adjusted based on the identifying. Specifically, one of a depositing or an etching of a spacer material in a subsequently formed integrated circuit structure may be adjusted in order to reach a desired integrated circuit structure design. The present disclosure will now be described relative to an integrated circuit structure undergoing aspects of the methods, a flow diagram showing processes according to aspects of the methods, and a system for performing and/or implementing aspects of the methods.

Turning now toFIGS. 1-2, a preliminary integrated circuit (IC) structure100is shown. IC structure100may include a substrate102having a plurality of mandrels110thereover. Substrate102may include but is not limited to silicon, germanium, silicon germanium, silicon carbide, and those consisting essentially of one or more III-V compound semiconductors having a composition defined by the formula AlX1GaX2InX3AsY1PY2NY3SbY4, where X1, X2, X3, Y1, Y2, Y3, and Y4represent relative proportions, each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relative mole quantity). Other suitable substrates include II-VI compound semiconductors having a composition ZnA1CdA2SeB1TeB2, where A1, A2, B1, and B2are relative proportions each greater than or equal to zero and A1+A2+B1+B2=1 (1 being a total mole quantity). Furthermore, a portion or entirety of substrate102may be strained. While substrate102is shown as including a single layer of semiconductor material, it is emphasized that the teachings of the disclosure are equally applicable to semiconductor-on-insulator (SOI) substrates. As known in the art, SOI substrates may include a semiconductor layer on an insulator layer on another semiconductor layer (not shown). The semiconductor layers of an SOI substrate may include any of the semiconductor substrate materials discussed herein. The insulator layer of the SOI substrate may include any now known or later developed SOI substrate insulator such as but not limited to silicon oxide.

Mandrel formation may be performed as part of a sidewall image transfer (SIT) process. While three mandrels110a-chave been illustrated, it is understood that any number of mandrels may be provided. Mandrels110a-cmay be formed by depositing a sacrificial material and then patterning the sacrificial material into the plurality of material blocks in any now known or later developed manner. In one embodiment mandrels110a-c, may include polysilicon, amorphous silicon, amorphous carbon, etc. “Depositing” may include any now known or later developed techniques appropriate for the material to be deposited including but are not limited to, for example: CVD, low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation. The patterning may include using any conventional photoresist, exposing it and etching accordingly to create mandrels110, followed by photoresist strip. As shown, the etching may result in an uneven formation of mandrels110. That is, the etching may result in a non-uniform shape, or a deviation from a straight line, of mandrels110and sidewalls thereof.

As used herein, “etching” generally refers to the removal of material from a substrate or structures formed on the substrate by wet or dry chemical means. In some instances, it may be desirable to selectively remove material from certain areas of the substrate. In such an instance, a mask may be used to prevent the removal of material from certain areas of the substrate. There are generally two categories of etching, (i) wet etch and (ii) dry etch. Wet etching may be used to selectively dissolve a given material and leave another material relatively intact. Wet etching is typically performed with a solvent, such as an acid. Dry etching may be performed using a plasma which may produce energetic free radicals, or species neutrally charged, that react or impinge at the surface of the wafer. Neutral particles may attack the wafer from all angles, and thus, this process is isotropic. Ion milling, or sputter etching, bombards the wafer with energetic ions of noble gases from a single direction, and thus, this process is highly anisotropic. A reactive-ion etch (RIE) operates under conditions intermediate between sputter etching and plasma etching and may be used to produce deep, narrow features, such as trenches.

Turning now toFIGS. 3-4, a spacer material114may be conformally deposited over substrate102and mandrels110such that spacer material114substantially surrounds mandrels110. Spacer material114may include any now known or later developed spacer material, such as, thin conformal oxide layer, such as silicon dioxide or silicon nitride.

Turning now toFIGS. 5-6, spacer material114may be etched such that spacer material114is removed from a top surface of mandrels110thereby exposing a top surface of each mandrel110. Additionally, a substantial portion of spacer material114may be removed from a top surface of substrate102between adjacent mandrels110. However, a portion of spacer material114may remain immediately adjacent to, and aligning sidewalls of, mandrels110. As a result, spacers120are formed. More particularly, a pair of spacers120are formed on opposing sides of each mandrel110. In addition, non-mandrel spaces124are defined between adjacent spacers120of adjacent pairs of mandrels110.

In other embodiments of the disclosure, the methods described herein may begin with IC structure180shown inFIGS. 5-6such that the methods may include providing an IC structure180to an IC structure fabricator. IC structure180may include mandrels110over substrate102laterally adjacent to each other; pair of spacers120on opposing sides of each mandrel over substrate102; and non-mandrel spaces124between adjacent spacers120of each mandrel110. More specifically, non-mandrel space124amay be defined between spacer120bof corresponding mandrel110aand spacer120cof corresponding mandrel110b. Additionally, non-mandrel space124bmay be defined between spacer120dof corresponding mandrel110band spacer120eof corresponding mandrel110c.

As shown inFIGS. 7-8, mandrels110may be removed to expose substrate102thereunder such that spacers120remain and include freestanding spacers120a-fthereby creating a resulting IC structure190. As a result, mandrel spaces128are defined between adjacent spacers120of each pair of spacers120of each corresponding mandrel110. For example, mandrel space128amay be defined between spacer120aand spacer120bof corresponding mandrel110a(FIGS. 5-6), mandrel space128bmay be defined between spacer120cand120dof corresponding mandrel110b(FIGS. 5-6), and mandrel space128cmay be defined between spacer120eand120fof corresponding mandrel110c(FIGS. 5-6). Each mandrel space128and non-mandrel space124may include a length of approximately 200 nanometers (nm) to approximately 10,000 nm. The SIT process may continue by using the remaining freestanding spacers120as a mask for forming sub-lithographic structures in substrate102(not shown).

An IC fabricator may need to determine which spaces are non-mandrel spaces124and which are mandrel spaces128, e.g., to modify or adjust photolithography or deposition techniques in a subsequently formed IC structure. It may be unclear simply from looking at an image of IC structure190which spaces are non-mandrel spaces124and which are mandrel spaces128. Therefore, methods according to embodiments of the disclosure may include determining a line width roughness of each space, e.g., each non-mandrel space124and each mandrel space128. Additionally, methods according to embodiments of the disclosure may include identifying a respective space between freestanding spacers120as being one of a mandrel space128created by removal of a mandrel110(FIGS. 5-6) from between spacers120or a non-mandrel space124, the latter of which exists between adjacent mandrels110prior to removal of mandrels110based on the line width roughness of the respective space. The line width roughness may represent a deviation of a width W of the respective space from a centerline axis CLA along a length L of the respective space. Line width roughness may be determined using, for example, at least one of: a scanning electron microscope (SEM), an atomic force microscope (AFM), an optical critical dimension (OCD) tool, or other top-down metrology tools. Line width roughness may be represented by the following equation:
LWR=3√{square root over (σxR2+σxL2−2 cov(xL,xR))}  Equation 1
wherein LWR represents the line width roughness, σxRrepresents the standard deviation of the line edge roughness of the right edge, σxLrepresents the standard deviation of the line edge roughness of the left edge and cov(xL, xR) represents the covariance between the left and right edge.

In a case where the line width roughness of the respective space is approximately equal to zero nm, the space may be identified as a mandrel space128. Mandrel spaces128have a line width roughness of approximately zero nm due to the fact that conformal deposition of spacer material114results in spacers120to line and, therefore, follow the shape of the corresponding mandrel110. As a result, the deviation of width W of mandrel space128is uniform. In other words, spacers120defining mandrel spaces128parallel one another. In a case where the line width roughness of the respective space is not approximately equal to zero nm, the space may be identified as a non-mandrel space124. Non-mandrel spaces124may have a line width roughness that is not approximately equal to zero due to the fact that each of the spacers120that define the non-mandrel space124correspond to a different mandrel110which may not have the same outer shape. In other words, spacers120defining non-mandrel spaces124do not parallel one another. Consequently, spacers formed thereon do not have a uniform distance apart from one another. As a result, the deviation of width W of non-mandrel space124is non-uniform. That is, one spacer120may follow the shape of one mandrel110, e.g., mandrel110a, and another spacer120may follow a shape of another, differently shaped mandrel110, e.g., mandrel110b, resulting in a non-zero line width roughness of the space, e.g., space124a. However, it is to be understood that the line width roughness of mandrel space128may not be equal to exactly zero, but in any case the line width roughness of mandrel space128will be less than a line width roughness than non-mandrel space124. Said another way, the line width roughness of non-mandrel space124is greater than a line width roughness of mandrel space128.

The methods may also include adjusting one of a depositing or an etching of a spacer material of additional freestanding spacers in a subsequently fabricated IC structure based on the identifying. That is, once the space has been identified as a non-mandrel or mandrel space, the IC fabricator is able to determine how to adjust the size of the space, the spacers, and/or the mandrels in a subsequently fabricated IC structure to obtain a desired space size, and therefore, a desired sub-lithographic structure size. For example, because mandrel spaces are formed by the removal of the mandrel between adjacent freestanding spacers, in order to adjust a size of a mandrel space, the IC fabricator can adjust a size of the mandrels in the subsequently fabricated IC structure. Additionally, because non-mandrel spaces are formed by the conformal deposition of a spacer material and an etching of the spacer material, in order to adjust a size of a non-mandrel space, the IC fabricator can adjust the amount of spacer material that is conformally deposited and/or the etching process in the subsequently fabricated IC structure.

InFIG. 9, a system is shown including a space identification system, for performing the functions described herein according to various embodiments of the disclosure. To this extent, the system200includes computer system202that can perform one or more processes described herein in order to determine a line width roughness of spaces124,128(FIGS. 7-8) in IC structure190(FIGS. 7-8), identify spaces in IC structure190, and/or adjust one of a depositing or an etching of the spacer material in a subsequently fabricated IC structure. In particular, computer system202is shown as including the space identification system204, which makes computer system202operable to identify spaces in IC structure190by performing any/all of the processes described herein and implementing any/all of the embodiments described herein.

The computer system202is shown including computing device226, which can include a processing component206(e.g., one or more processors), a storage component208(e.g., a storage hierarchy), an input/output (I/O) component210(e.g., one or more I/O interfaces and/or devices), a processing unit (PU)214, and a communications pathway212. In general, the processing component206executes program code, such as the space identification system204, which is at least partially fixed in the storage component208. While executing program code, the processing component206can process data, which can result in reading and/or writing transformed data from/to the storage component208, storage system222, and/or the I/O component210for further processing. The pathway212provides a communications link between each of the components in the computer system202. The I/O component210can comprise one or more human I/O devices, which enable a user (e.g., a human, and/or computerized user, e.g., an IC fabricator)216to interact with the computer system202and/or one or more communications devices to enable the system user216to communicate with the computer system202using any type of communications link. To this extent, the space identification system204can manage a set of interfaces (e.g., graphical user interface(s), application program interface, etc.) that enable human and/or system users216to interact with the space identification system204. Further, space identification system204can manage (e.g., store, retrieve, create, manipulate, organize, present, etc.) data260from a measurement system250, e.g., a SEM, such as image data (including SEM images of IC structure190) and line width roughness data282using any solution, e.g., via wireless and/or hardwired means.

In any event, computer system202can comprise one or more general purpose computing articles of manufacture (e.g., computing devices) capable of executing program code, such as the space identification system204, installed thereon. As used herein, it is understood that “program code” means any collection of instructions, in any language, code or notation, that cause a computing device having an information processing capability to perform a particular function either directly or after any combination of the following: (a) conversion to another language, code or notation; (b) reproduction in a different material form; and/or (c) decompression. To this extent, the space identification system204can be embodied as any combination of system software and/or application software. It is further understood that the space identification system204can be implemented in a cloud-based computing environment, where one or more processes are performed at distinct computing devices (e.g., a plurality of computing devices226), where one or more of those distinct computing devices may contain only some of the components shown and described with respect to the computing device226ofFIG. 10.

Further, space identification system204can be implemented using a set of modules232. In this case, a module232can enable the computer system202to perform a set of tasks used by the space identification system204, and can be separately developed and/or implemented apart from other portions of the space identification system204. As shown, modules232may include at least three modules including a line width roughness determinator292, a space identifier294, and an IC design adjuster296.

Turning now toFIG. 10, a flow diagram300is shown including processes of a method according to embodiments of the disclosure. The method according to this embodiment may include:

Process P1: line width roughness determinator292may determine a line width roughness of each space124,128in IC structure190(FIGS. 7-8). As discussed herein, the line width roughness of each space124,128may be determined by Equation 1 and may include using, e.g., a SEM, an AFM, or an OCD.

Process P2: space identifier294may identify each space124,128as being one of a mandrel space128created by removal of a mandrel110(FIGS. 5-6) or a non-mandrel space124between mandrels110prior to removal of the mandrels110, based on the line width roughness determined in process P1. In a case where the line width roughness of the respective space is approximately equal to zero nm, the space may be identified as a mandrel space128. In a case where the line width roughness of the respective space is not approximately equal to zero nm, the space may be identified as a non-mandrel space124. In any case, where a line width roughness of a first space is less than a line width roughness of another, adjacent space, the first space may be identified as a mandrel space128. Said another way, in a case where a line width roughness of the first space is greater than a line width roughness of another, adjacent space, the first space may be identified as a non-mandrel space124.

Process P3: IC design adjuster296may adjust a parameter, or indicate a parameter to be adjusted, during formation or fabrication of a subsequently formed IC structure such that a desired IC structure design is reached. More specifically, one of a depositing or an etching of a spacer material which is to form freestanding spacers in the subsequently formed IC structure may be adjusted and a new IC structure design parameter286may be provided to the IC fabricator and/or IC fabricator control system288.

As used herein, the term “component” means any configuration of hardware, with or without software, which implements the functionality described in conjunction therewith using any solution, while the term “module” means program code that enables the computer system202to implement the functionality described in conjunction therewith using any solution. When fixed in a storage component208of a computer system202that includes a processing component206, a module is a substantial portion of a component that implements the functionality. Regardless, it is understood that two or more components, modules, and/or systems may share some/all of their respective hardware and/or software. Further, it is understood that some of the functionality discussed herein may not be implemented or additional functionality may be included as part of the computer system202.

When the computer system202comprises multiple computing devices, each computing device226may have only a portion of space identification system204fixed thereon (e.g., one or more modules232). However, it is understood that the computer system202and space identification system204are only representative of various possible equivalent computer systems that may perform a process described herein. To this extent, in other embodiments, the functionality provided by the computer system202and space identification system204can be at least partially implemented by one or more computing devices that include any combination of general and/or specific purpose hardware with or without program code. In each embodiment, the hardware and program code, if included, can be created using standard engineering and programming techniques, respectively.

Regardless, when the computer system202includes multiple computing devices226, the computing devices can communicate over any type of communications link. Further, while performing a process described herein, the computer system202can communicate with one or more other computer systems using any type of communications link. In either case, the communications link can comprise any combination of various types of wired and/or wireless links; comprise any combination of one or more types of networks; and/or utilize any combination of various types of transmission techniques and protocols.

While shown and described herein as a method, computer program product and system for identifying spaces124,128(FIGS. 7-8) in IC structure190, it is understood that aspects of the disclosure further provide various alternative embodiments. For example, in one embodiment, disclosure provides a computer program fixed in at least one computer-readable medium, which when executed, enables a computer system to determine a line width roughness of spaces in IC structure190, identify spaces in IC structure190, and/or adjust one of a depositing or an etching of the spacer material in a subsequently fabricated IC structure. To this extent, the computer-readable medium includes program code, such as the space identification system204, which implements some or all of the processes and/or embodiments described herein. It is understood that the term “computer-readable medium” comprises one or more of any type of tangible medium of expression, now known or later developed, from which a copy of the program code can be perceived, reproduced, or otherwise communicated by a computing device. For example, the computer-readable medium can comprise: one or more portable storage articles of manufacture; one or more memory/storage components of a computing device; paper; etc.

In another embodiment, the disclosure provides a method of providing a copy of program code, such as the space identification system204, which implements some or all of a process described herein. In this case, a computer system can process a copy of program code that implements some or all of a process described herein to generate and transmit, for reception at a second, distinct location, a set of data signals that has one or more of its characteristics set and/or changed in such a manner as to encode a copy of the program code in the set of data signals. Similarly, an embodiment of the disclosure provides a method of acquiring a copy of program code that implements some or all of a process described herein, which includes a computer system receiving the set of data signals described herein, and translating the set of data signals into a copy of the computer program fixed in at least one computer-readable medium. In either case, the set of data signals can be transmitted/received using any type of communications link.

In still another embodiment, the disclosure provides a method of identifying spaces124,128(FIGS. 7-8) in IC structure190. In this case, a computer system, such as the computer system202, can be obtained (e.g., created, maintained, made available, etc.) and one or more components for performing a process described herein can be obtained (e.g., created, purchased, used, modified, etc.) and deployed to the computer system. To this extent, the deployment can comprise one or more of: (1) installing program code on a computing device; (2) adding one or more computing and/or I/O devices to the computer system; (3) incorporating and/or modifying the computer system to enable it to perform a process described herein; etc.

In still another embodiment, the disclosure provides for a computer program product comprising a computer readable storage medium (e.g., a non-transitory computer readable storage medium) having program instructions embodied therewith, the program instructions executable by a computer device to cause the computer device to: identify a space between freestanding spacers as being one of: a mandrel space created by removal of a mandrel from between the freestanding spacers or a non-mandrel space between adjacent mandrels prior to removal of the mandrel, based on a line width roughness of the space, wherein the line width roughness represents a deviation of a width of the space from a centerline axis along a length of the space.