English:
[0001] This disclosure relates to display systems, and in particular to organic light-emitting diode (OLED) displays configured to allow a reduction in pixel size.
[0002] Organic light-emitting diode (OLED) displays may include circuits which can reverse the bias of the OLED elements. By periodically reversing the bias of the OLED, the lifetime of the OLED can be extended.
[0003] The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for the desirable attributes disclosed herein.
[0004] One innovative aspect of the subject matter described in this disclosure can be implemented in an organic light-emitting diode (OLED) control circuit can be configured to receive signals from a data line, an emission line, a scan line, a high-power supply line and a low power supply line. The OLED control circuit can include an organic light-emitting diode (OLED) having an anode and a cathode, the cathode in electrical communication with the low power supply line, a driving transistor having a gate, a source, and a drain, the source of the driving transistor in electrical communication with the OLED and a drain of the driving transistor in electrical communication with the high-power supply line, a storage capacitor, a first plate of the storage capacitor in electrical communication with both the gate and the drain of the driving transistor, and a second plate of the storage capacitor in electrical communication with the low power supply line, a data switch transistor having a source in electrical communication with the data line, a drain in electrical communication with the drain of the driving transistor, and a gate in electrical communication with the scan line, and a first diode-connected transistor. The first diode-connected transistor having a gate, a drain, and a source, the drain of the first diode-connected transistor connected to the gate of the first diode-connected transistor and in electrical communication with the data line, and the source of the first diode-connected transistor in electrical communication with the anode of the OLED.
[0005] In some implementations, the circuit can additionally include a second diode-connected transistor having a source, a gate, and a drain, the drain of the second diode-connected transistor connected to the gate of the first diode-connected transistor and in electrical communication with the data line, and the source of the second diode- connected transistor in electrical communication with the first plate of the storage capacitor. The circuit can additionally include a first leak-suppressing transistor connected between the source of the first diode-connected transistor and the anode of the OLED. The circuit can additionally include a second leak-suppressing transistor connected between the source of the first diode-connected transistor and the first plate of the storage capacitor.
[0006] In some implementations, the circuit can additionally include a power conducting transistor, the power conducting transistor connected between the source of the driving transistor and the high-power supply line, the power conducting transistor having a gate in electrical communication with the emission line, a source in electrical communication with the high-power supply line, and a drain in electrical communication with the source of the power conduction transistor. The circuit can additionally include an OLED-connected transistor, the OLED-connected transistor connected between the data switching transistor and the anode of the OLED, the OLED-connected transistor having a gate in electrical communication with the emission line, a source in electrical communication with OLED, and a drain in electrical communication with the data switching transistor.
[0007] In some implementations, the OLED circuit can be configured to initialize the OLED by draining voltage from the anode of the OLED through the first diode-connected transistor to reverse the bias of the OLED. The first plate of the storage capacitor can be configured to store a reference voltage, and the reference voltage can be a function of a high data voltage applied on the on the data line and the threshold voltage of the driving transistor.
[0008] Another innovative aspect of the subject matter described in this disclosure can be implemented in an organic light-emitting diode (OLED) control circuit can be configured to receive signals from a data line, an emission line, a scan line, a high- power supply line and a low power supply line. The OLED control circuit can include an organic light-emitting diode (OLED) having an anode and a cathode, the cathode in electrical communication with the low power supply line, a driving transistor having a gate, a source, and a drain, the source of the driving transistor in electrical communication with the OLED and a drain of the driving transistor in electrical communication with the high-power supply line, means for storing a reference voltage, the reference voltage being a function of a high data voltage applied on the on the data line and the threshold voltage of the driving transistor, a data switch transistor having a source in electrical communication with the data line, a drain in electrical communication with the drain of the driving transistor, and a gate in electrical communication with the scan line, and means for initializing the OLED circuit by draining voltage from the anode of the OLED through the first diode-connected transistor to reverse the bias of the OLED.
[0009] In some implementations, the storage means can include a storage capacitor, a first plate of the storage capacitor in electrical communication with both the gate and the drain of the driving transistor, and a second plate of the storage capacitor in electrical communication with the low power supply line. The initializing means can include a first diode-connected transistor, the first diode-connected transistor having a gate, a drain, and a source, the drain of the first diode-connected transistor connected to the gate of the first diode-connected transistor and in electrical communication with the data line, and the source of the first diode-connected transistor in electrical communication with the anode of the OLED. The circuit can additionally include a second diode-connected transistor having a source, a gate, and a drain, the drain of the second diode-connected transistor connected to the gate of the first diode-connected transistor and in electrical communication with the data line, and the source of the second diode-connected transistor in electrical communication with the first plate of the storage capacitor. The circuit can additionally include a first leak-suppressing transistor connected between the source of the first diode-connected transistor and the anode of the OLED. The circuit can additionally include a second leak-suppressing transistor connected between the source of the first diode-connected transistor and the first plate of the storage capacitor.
[0010] In some implementations, the circuit can additionally include a power conducting transistor, the power conducting transistor connected between the source of the driving transistor and the high-power supply line, the power conducting transistor having a gate in electrical communication with the emission line, a source in electrical communication with the high-power supply line, and a drain in electrical communication with the source of the power conduction transistor. The circuit can additionally include an OLED-connected transistor, the OLED-connected transistor connected between the data switching transistor and the anode of the OLED, the OLED-connected transistor having a gate in electrical communication with the emission line, a source in electrical communication with OLED, and a drain in electrical communication with the data switching transistor.
[0011] Another innovative aspect of the subject matter described in this disclosure can be implemented in a method of controlling an organic light-emitting diode (OLED) circuit in electrical communication with a data line, an emission line, a scan line, a high-power supply line and a low power supply line can include initializing the OLED circuit by applying a low voltage signal on the data line, and placing an anode of an OLED in electrical communication with the low voltage signal via a diode-connected transistor, programming the OLED by applying a high voltage signal on the data line, and storing a reference voltage on a plate of a storage capacitor by charging the plate of the storage capacitor through a driving transistor of the OLED circuit, the reference voltage being a function of the high voltage signal applied on the data line and a threshold voltage of the driving transistor of the OLED circuit, and energizing the OLED by applying a current through the OLED.
[0012] In some implementations, initializing the OLED circuit can reverse the bias of the OLED. Energizing the OLED can include applying a current through the OLED which is independent of the threshold voltage of the driving transistor. The method can additionally include applying an emission signal on the emission line and simultaneously applying a scan signal on the scan line, where the emission signal is generated by driver circuitry in electrical communication with the OLED circuit, and where the scan signal is generated by the same driver circuitry.
[0013] Details of one or more implementations of the subject matter described in this disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings and the claims. Note that the relative dimensions of the following figures may not be drawn to scale.
[0014] FIG. 1 schematically illustrates an example implementation of an OLED circuit which uses a dedicated initialization voltage to reverse the polarity of the OLED circuit.
[0015] FIG. 2 illustrates examples of data signals that can be applied to the OLED circuit of FIG. 1.
[0016] FIG. 3 schematically illustrates an example implementation of an OLED circuit which can reverse the polarity of the OLED circuit without the need for a dedicated initialization voltage line.
[0017] FIGS. 4A to 4C schematically illustrate example stages in the driving scheme of the OLED circuit of FIG. 3.
[0018] FIG. 5 illustrates examples of data signals that can be applied to the OLED circuit of FIG. 3 in the driving scheme of FIGS. 4A to 4C.
[0019] FIG. 6 is a flow diagram illustrating certain stages in an example process for driving an OLED circuit such as the OLED circuit of FIG. 3.
[0020] FIG. 7A schematically illustrates an alternative implementation of an example OLED circuit.
[0021] FIGS. 7B to 7D schematically illustrate the operation of the example OLED circuit of FIG. 7A.
[0022] FIG. 8A schematically illustrates an alternative implementation of an example OLED circuit.
[0023] FIGS. 8B to 8D schematically illustrate the operation of the example OLED circuit of FIG. 8A.
[0024] FIG. 9A schematically illustrates an alternative implementation of an example OLED circuit.
[0025] FIGS. 9B to 9D schematically illustrate the operation of the example OLED circuit of FIG. 9A.
[0026] FIG. 10A schematically illustrates an alternative implementation of an example OLED circuit.
[0027] FIGS. 10B to 10D schematically illustrate the operation of the example OLED circuit of FIG. 10A.
[0028] FIG. 10A schematically illustrates another alternative implementation of an example OLED circuit.
[0029] FIGS. 10B to 10D schematically illustrate the operation of the example OLED circuit of FIG. 10A.
[0030] FIG. 11A schematically illustrates another alternative implementation of an example OLED circuit, which uses one fewer transistor than the implementation of FIG. 3
[0031] FIGS. 11B to 11D schematically illustrate the operation of the example OLED circuit of FIG. 11A.
[0032] FIG. 12A schematically illustrates another alternative implementation of an example OLED circuit, which uses two fewer transistors than the implementation of FIG. 3
[0033] FIGS. 12B to 12D schematically illustrate the operation of the example OLED circuit of FIG. 12A.
[0034] Like reference numbers and designations in the various drawings indicate like elements.
[0035] The following description is directed to certain implementations for the purposes of describing the innovative aspects of this disclosure. However, a person having ordinary skill in the art will readily recognize that the teachings herein can be applied in a multitude of different ways. The described implementations may be implemented in any device, apparatus, or system that is capable of displaying an image, whether in motion (such as video) or stationary (such as still images), and whether textual, graphical or pictorial. The concepts and examples provided in this disclosure may be applicable to organic light-emitting diode (OLED) displays, in addition to displays incorporating features from one or more display technologies.
[0036] The described implementations may be included in or associated with a variety of electronic devices such as, but not limited to: mobile telephones, multimedia Internet enabled cellular telephones, mobile television receivers, wireless devices, smartphones, Bluetooth® devices, personal data assistants (PDAs), wireless electronic mail receivers, hand-held or portable computers, netbooks, notebooks, smartbooks, tablets, printers, copiers, scanners, facsimile devices, global positioning system (GPS) receivers/navigators, cameras, digital media players (such as MP3 players), camcorders, game consoles, wrist watches, wearable devices, clocks, calculators, television monitors, flat panel displays, electronic reading devices (such as e-readers), computer monitors, auto displays (such as odometer and speedometer displays), cockpit controls and/or displays, camera view displays (such as the display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, microwaves, refrigerators, stereo systems, cassette recorders or players, DVD players, CD players, VCRs, radios, portable memory chips, washers, dryers, washer/dryers, parking meters, packaging and aesthetic structures (such as display of images on a piece of jewelry or clothing).
[0037] The lifetime of an OLED circuit may be extended by periodically reversing the bias of the OLED circuit to discharge the OLED. In some implementations of OLED arrays, each OLED circuit is in communication with a dedicated initialization voltage line, which can be used to reset the gate voltage of the driving thin-film transistor (TFT) to reverse the OLED bias. The inclusion of such dedicated initialization voltage lines, however, requires a substantial amount of area in an OLED array, as each OLED element must be in electrical communication with an initialization voltage line. In some implementations, OLED circuits can be configured to have reversible polarity without the use of a dedicated OLED circuit.
[0038] Particular implementations of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages. By providing OLED circuits which are capable of reversing polarity, the useful lifetime of an OLED panel can be extended. By omitting the initialization voltage line, however, the pixel density of the OLED panel can be increased, as each row (or column) need not include space for a dedicated initialization voltage line. Instead, each OLED circuit can be driven using a single scan signal, an emission signal, and a data signal, simplifying the design and fabrication of the OLED circuit. In some implementations of OLED circuits described herein, additional advantages may be realized, including the simplification of the panel driver circuitry. For example, in some implementations, the emission signal and the scan signal may be generated using a single scan row driver.
[0039] FIG. 1 schematically illustrates an example implementation of an OLED circuit which uses a dedicated initialization voltage to reverse the polarity of the OLED circuit. In the illustrated implementation, components of the OLED circuit 100 are in electrical communication with a data line 102, a first power supply line 104a at a high voltage, an emission line 108, first and second scan lines 106a and 106b, and an initialization voltage line 110. The OLED circuit includes seven transistors 121-127, including a driving transistor 125 which is configured to control the state of OLED 130. The OLED 130 is also connected to a second power supply 104b at a voltage lower than the high voltage of the first power supply line 104a. A capacitor 140 is connected to the gate of driving transistor 125.
[0040] The first scan line 106a is connected to the gates of transistor 123 and 127. Second scan line 106b is connected to the gates of transistors 122 and 125. The emission line 108 is connected to the gates of transistors 121 and 126. The first power supply line 104 is connected to the source of transistor 126 and to the plate of capacitor 140 opposite the gate of driving transistor 125. The initialization voltage line 110 is connected to the source of transistor 123 and to the source of transistor 127, and can be used to reset the gate voltage of the driving TFT 125 to reset the gate voltage of the driving transistor 125 reverse the bias of the OLED circuit.
[0041] FIG. 2 illustrates examples of data signals that can be applied to the OLED circuit of FIG. 1. In operation, the OLED may be initialized by applying low signal on the data line 102 and the first scan line 106a, and high signals on the emission line 108 and the second scan line 106b. The OLED may then be programmed by applying high signals on the emission line 108 and the first scan line 106a, and low signals on the data line 102 and the second scan lines 106b. Then, in an emission stage, high signals are applied on the first and second scan lines 106a and 106b, and low signals are applied on the emission line 108 and the data line 102. For a given frame, the polarity of the OLED circuit can be controlled via the initialization voltage line 110.
[0042] For the bias each of the OLED circuits in an OLED display to be reversible, an OLED display utilizing the circuit of FIG. 1 includes a dedicated initialization line in each line or row of the OLED display. The large number of dedicated initialization lines in such an OLED display impacts the possible pixel density of the OLED display. Such a design represents a tradeoff between longevity of the OLEDs within the display and pixel density. In some other implementations, however, the bias may be reversed without the need for a dedicated initialization voltage line, allowing greater pixel density along with the increased longevity from reversing the bias of the OLED.
[0043] FIG. 3 schematically illustrates an example implementation of an OLED circuit which can reverse the polarity of the OLED circuit without the need for a dedicated initialization voltage line. The reversible OLED circuit 200 includes a data line 202, a first voltage line 204a, a second voltage line 204b, a scan line 206, and an emission line 208. The data line 202 is connected to the source of data switch transistor 221 and the drains of diode-connected transistors 223 and 226. The scan line 206 is connected to the gates of transistors 221, 224, 227, and 228. The emission line 208 is connected to the gates of transistors 222 and 229. The first power supply line 204a is connected to the source of transistor 229, as well as to the plate of capacitor 240 opposite the gate of driving transistor 225.
[0044] It can be seen in FIG. 3 that the transistors 223 and 226 are diode- connected, with an electrical connection between the drain of the transistor and the gate of the transistor. As described in greater detail herein, this configuration allows the initialization of the anode of the OLED 230 without the need for a dedicated initialization voltage line, such as the initialization voltage line 110 of the OLED circuit 100 of FIG. 1. Because such diode-connected transistors can be susceptible to leakage, leak suppressing transistors 224 and 227 are connected to the sources of the diode-connected transistors 226 and 223, respectively. In some implementations, the initializing voltage for the OLED 230 can be applied directly to the OLED 230 from the data line 202 during an initialization period, rather than during an addressing period.
[0045] FIGS. 4A to 4C schematically illustrate example stages in the driving scheme of the OLED circuit of FIG. 3. FIG. 5 illustrates examples of data signals that can be applied to the OLED circuit of FIG. 3 in the driving scheme of FIGS. 4A to 4C.
[0046] FIG. 4A illustrates the OLED circuit 200 in an initialization phase. In the illustrated implementation, a low data voltage VDataLow is applied on the data line 202 and a low scan voltage VscanLow is applied on the scan line 206. Simultaneously, a high emissions voltage VEmHigh is applied on the emission line 208. This turns the power conduction transistor 229 off, along with the OLED control transistor 222. The transistors 221, 224, 227, and 228 along the scan line 206, along with the diode- connected transistors 223 and 226, are turned on.
[0048] Similarly, the voltage at location 212, at the gate of driving transistor 225 and the adjacent plate of the storage capacitor 240, will be discharged through diode- connected transistor 226 if the voltage at location 212 is sufficiently high. FIG. 4A schematically illustrates the discharge path 262 from the location 212 to the data line 202. If the voltage at location 212 is higher than (VDataLow + IVm]), where Vm is the threshold voltage of transistor 223, the voltage will be discharged to (VDataLow (V ). If the voltage at location 212 is below (VDataLow |V where V is the threshold voltage of driving transistor 225, the voltage at location 212 will be charged to (VDataLow + |V through the driving transistor 225.
[0049] Because the transistors 223 and 226 are diode-connected, their threshold voltages Vm and VTM can be used to control the voltages to which the locations 212 and 214 are discharged when a low voltage VDataLow is applied on the data line 202. The threshold voltages limit the discharge to a voltage higher than the low
[0050] FIG. 4B illustrates the OLED circuit 200 in a programming phase. In the illustrated implementation, a high data voltage VDataHigh is applied on the data line 202 and a high emissions voltage VEmHigh is applied on the emission line 208. Simultaneously, a low scan voltage VscanLow is applied on the scan line 206. The power conduction transistor 229 remains off, along with the OLED control transistor 222. In addition, the diode-connected transistors 223 and 226 are turned off. The transistors 221, 224, 227, and 228 along the scan line 206 remain on.
[0051] The voltage at location 214 will remain unaffected during this programming phase, remaining at the voltage to which it was discharged during the initialization phase, if it was not already at a low voltage. The OLED 230 thus remains at a reversed bias. The voltage at location 212, however, will be charged to a voltage which is dependent on the threshold voltage of the driving transistor 225. FIG. 4B schematically illustrates the charge path 272 from the data line 202, through driving transistor 252, to the location 212 at the gate of driving transistor. The voltage will be charged to (VDataHigh - |VTTI5|), at which point the driving transistor 225 will be turned off.
[0052] By setting the voltage at location 212 to a voltage which is dependent upon the threshold voltage Viiis, the voltage on the connected plate of the storage capacitor 240 can be set to a voltage which is dependent upon the data line voltage and the threshold voltage Viiis. Using this, the OLED circuit 200 can compensate for the threshold voltage Viiis, and drive the OLED 230 using a current which is independent of the threshold voltage Viiis.
[0053] It can be seen in FIG. 4B that if the diode-connected transistors 223 and 226 are leaky, the high voltage on the data line 202 could affect the voltage to which location 212 is charged. The threshold voltages VTO and VTO can be selected to be between -1.5 Volts and -2.5 Volts to minimize or prevent the effect of the leak current. The threshold voltage of a pMOS or nMOS transistor can be controlled by controlling the doping density during the fabrication process.
[0054] FIG. 4C illustrates the OLED circuit 200 in an emission phase. In the illustrated implementation, a low emissions voltage VEmLow is applied on the emission line 208, and a low data voltage VDataHigh is applied on the data line 202. The transistors 221, 224, 227, and 228 along the scan line 206 are turned off, and the power conduction transistor 229 and the OLED control transistor 222 are turned on.
[0055] Because the transistor 227 is turned off, the voltage at location 212 at the gate of driving transistor 225 and on the adjacent plate of storage capacitor 240 remains at (VDataHigh - |VTTI5|). Current flows through OLED 230 from the first voltage line 204a along path 282. Because the stress gate voltage is also a function of the threshold voltage VTII5 of the driving transistor 225, the current / through the OLED can be defined as a function of the square of the difference between the high voltage Vffigh and the high data voltage VDataHigh which remains stored on the storage capacitor 240. The current / through the OLED is therefore independent of the driving voltage, due to the voltage compensation which occurs during the programming phase. The high data voltage VDataHigh may be any suitable value greater than the maximum voltage across the OLED VoLEDHigh but less than the high voltage Vffigh supplied by the first voltage line 204a
[0056] It can be seen in FIG. 5 that the emission signal applied on the emission line 208 is, during each phase of the illustrated driving scheme, the inverse of the data signal applied on the data line 202. A further advantage of the OLED configuration is the ability to utilize a single row driver to generate both the emission signal and the data signal, or otherwise use at least some common circuitry to generate both the emission signal and the data signal. In addition to the increased pixel density allowed by the omission of a dedicated initialization voltage line, an OLED display which requires one scan signal and generates that scan signal and an emission signal using the same driver circuitry also can result in a decrease in border size at the edge of the display. Because the border does not need to accommodate both an emission row driver and a separate scan row driver, the border area without OLED pixels can be made smaller, resulting in an increase of active display space relative to overall display space.
[0057] FIG. 6 is a flow diagram illustrating certain stages in an example process for driving an OLED circuit such as the OLED circuit of FIG. 3. The process includes a stage 605 where the OLED circuit is initialized. A low data voltage is applied on the data line of the OLED circuit, and a low scan voltage is applied on the scan line of the OLED circuit. A high emission voltage is applied on the emission line to turn off the power conducting transistor and the OLED-connected transistor of the OLED circuit, so the OLED will not be energized. The remaining components of the OLED circuit are configured such that the voltage at the plate of a storage capacitor opposite the plate connected to a high-power source is discharged through a diode-connected transistor. Similarly, the voltage at the anode of the OLED is discharged through a diode-connected transistor. The resulting voltage at each of these locations may be dependent upon the threshold voltage of the diode-connected transistor through which they are discharged. The OLED is discharged by this process, if needed, and the bias of the OLED is now reversed.
[0058] The process includes a stage 610 where the OLED circuit is programmed. The emission line signal remains at a low emission voltage, so that the OLED remains not energized, and the bias of the OLED remains reversed. The scan signal remains at a low scan voltage, but a high data voltage is applied on the data line. The voltage at the plate of a storage capacitor opposite the plate connected to a high- power source is increased to a voltage which is a function of the high data voltage and the threshold voltage of the driving transistor of the OLED circuit, writing this information to the storage capacitor.
[0059] The process includes a stage 615 where the OLED is energized. A high emission voltage is now applied on the emission line, turning on the power conduction transistor and the OLED-connected transistor, and allowing a current to flow through the OLED, energizing the OLED. At the same time, a high scan voltage is applied on the scan line, and a low data voltage is applied on the data line. Because the voltage stored on the plate of the storage capacitor opposite the high-power source is a function of the threshold voltage of the driving conductor, the current flowing through the OLED at stage 615 is independent of the threshold voltage of the driving conductor.
[0060] The OLED circuit illustrated in FIG. 3 is merely one possible implementation of an OLED circuit having features described herein. Several other OLED circuit arrangements may be provided which include at least some of the features discussed herein.
[0061] FIG. 7A schematically illustrates an alternative implementation of an example OLED circuit. Like the OLED circuit 200 of FIG. 3, the OLED circuit 700 includes two diode-connected transistors 723 and 728. The voltage at the anode of the OLED 730 can be discharged through transistor 724 and diode-connected transistor 723 during an initialization phase of a driving scheme, and the voltage at the gate of driving transistor 725 can be discharged through transistor 727 and diode-connected transistor 726. In a subsequent programming phase, the voltage at a plate of the storage capacitor 740 can be charged to a voltage which is a function of the threshold voltage of the driving capacitor, compensating for the threshold voltage of the driving capacitor. The same drive signals may be applied to drive the OLED circuit 700 as were applied to drive the OLED circuit 200.
[0062] FIGS. 7B to 7D schematically illustrate the operation of the example OLED circuit of FIG. 7A. As can be seen in FIG. 7B, in the initialization phase, when a low scan voltage is applied on scan line 706, a low data voltage is applied on data line 702, and a high emission voltage is applied on the emission line, the voltage at location 714 at the anode of the OLED 730 may be discharged along discharge path 764 through transistor 727 and diode-connected transistor 723 if the voltage is sufficiently high. Similarly, the voltage at location 712 at the gate of driving transistor 725 may be discharged along discharge path 762 through transistor 724 and diode-connected transistor 726 if the voltage is sufficiently high.
[0063] As can be seen in FIG. 7C, in the programming phase, when a low scan voltage is applied on scan line 706, a high data voltage is applied on data line 702, and a high emission voltage is applied on the emission line, the voltage at the plate of the storage capacitor 740 will be charged to a voltage (VDataHigh - |VTTI5|). AS the potential at the plate of storage capacitor 740 is equal to the potential at location 712 at the gate of driving transistor 725, the driving transistor 725 will be turned off once the potential reaches (VDataHigh - |VTTI5|). This charging will occur along path 772 passing from the data line 702 through data switch transistor 721, driving transistor 725, and transistor 728. Transistors 724 and 727 may serve a leak-suppression function in the OLED circuit 700, particularly during this programming phase, due to possible leakage through diode- connected transistors 723 and 726.
[0064] As can be seen in FIG. 7D, in the emission phase, when a low emission voltage is applied on the emission line 708 and a low data voltage is applied on the data line 702, the OLED 730 is energized by current flowing along path 782 through power conduction transistor 729, driving transistor 725, and OLED-connected transistor 722. In some implementations, because the threshold voltage of driving transistor 725 was stored on storage capacitor 740 during the programming phase, the current through the OLED 730 will again be independent of the threshold voltage of the driving transistor 725, resulting in greater uniformity across an OLED display.
[0065] FIG. 8A schematically illustrates an alternative implementation of an example OLED circuit. The OLED circuit 800 also includes nine total transistors, including two diode-connected transistors 823 and 826. However, the OLED circuit 800 differs from the OLED circuits in that, in an initialization phase, the voltages at the anode of the OLED 830 and at the plate of the storage capacitor 840 will each be discharged through data switch transistor 821, among other transistors.
[0066] FIGS. 8B to 8D schematically illustrate the operation of the example OLED circuit of FIG. 8A. As can be seen in FIG. 8B, in the initialization phase, when a low scan voltage is applied on scan line 806, a low data voltage is applied on data line 802, and a high emission voltage is applied on the emission line, the voltage at location 814 at the anode of the OLED 830 may be discharged along discharge path 864 through diode-connected transistor 823 and transistor 824. The voltage at location 812 at the plate of storage conductor 840 may be discharged along discharge path 862 through transistor 827 and diode-connected transistor 826if the voltage is sufficiently high.
[0067] As can be seen in FIG. 8C, in the programming phase, when a low scan voltage is applied on scan line 806, a high data voltage is applied on data line 802, and a high emission voltage is applied on the emission line, the voltage at the plate of the storage capacitor 840 will be charged to a voltage (VDataHigh - |VTTI5|). AS the potential at location 812 at the plate of storage capacitor 840 is equal to the potential at the gate of driving transistor 825, the driving transistor 825 will be turned off once the potential reaches (VDataHigh - |VTTI5|). This charging will occur along path 872 passing from the data line 802 through data switch transistor 821, driving transistor 825, and transistor 828. Transistors 824 and 827 may serve a leak-suppression function in the OLED circuit 800, particularly during this programming phase, due to possible leakage through diode- connected transistor 823 and 826.
[0068] As can be seen in FIG. 8D, in the emission phase, when a low emission voltage is applied on the emission line 808 and a low data voltage is applied on the data line 802, the OLED 830 is energized by current flowing along path 882 through power conduction transistor 829, driving transistor 825, and OLED-connected transistor 822. The current through the OLED 830 will be independent of the threshold voltage of the driving transistor 825 due to the voltage compensation in the programming phase.
[0069] FIG. 9 schematically illustrates an alternative implementation of an example OLED circuit. The OLED circuit 900 also includes nine total transistors, including two diode-connected transistors 923 and 926. The data switch transistor 921 is connected between the data line 902 and the diode-connected transistors 923 and 926. The OLED circuit 900 will discharge voltages from both the plate of the storage capacitor 940 and the anode of the OLED 930 along paths which include the data switch transistor 921 in addition to one of the diode-connected transistors 923 and 926.
[0070] FIGS. 9B to 9D schematically illustrate the operation of the example OLED circuit of FIG. 9A. As can be seen in FIG. 9B, in the initialization phase, when a low scan voltage is applied on scan line 906, a low data voltage is applied on data line 902, and a high emission voltage is applied on the emission line, the voltage at location 914 at the anode of the OLED 930 may be discharged along discharge path 964 through transistor 924, diode-connected transistor 923, and data switch transistor 921. The voltage at location 912 at the plate of storage conductor 940 may be discharged along discharge path 962 through transistor 927, diode-connected transistor 926, and data switch transistor 921, if the voltage is sufficiently high. Each of these potential discharge paths pass through the data switch transistor 921 after passing through a diode-connected transistor.
[0071] As can be seen in FIG. 9C, in the programming phase, when a low scan voltage is applied on scan line 906, a high data voltage is applied on data line 902, and a high emission voltage is applied on the emission line, the voltage at the plate of the storage capacitor 940 will be charged to a voltage (VDataHigh - |VTTI5|). AS the potential at location 912 at the plate of storage capacitor 940 is equal to the potential at the gate of driving transistor 925, the driving transistor 925 will be turned off once the potential reaches (VDataHigh - |VTTI5|). This charging will occur along path 972 passing from the data line 902 through data switch transistor 921, driving transistor 925, and transistor 928. Transistors 924 and 927 may serve a leak-suppression function in the OLED circuit 900, particularly during this programming phase, due to possible leakage through diode- connected transistor 923 and 926.
[0072] As can be seen in FIG. 9D, in the emission phase, when a low emission voltage is applied on the emission line 908 and a low data voltage is applied on the data line 902, the OLED 930 is energized by current flowing along path 982 through power conduction transistor 929, driving transistor 825, and OLED-connected transistor 822. The current through the OLED 930 during the emissions phase is independent of the threshold voltage of the driving transistor 925 due to the voltage compensation in the programming phase.
[0073] FIG. 10A schematically illustrates an alternative implementation of an example OLED circuit. The OLED circuit 1000 also includes nine total transistors, including two diode-connected transistors 1023 and 1026.
[0074] FIGS. 10B to 10D schematically illustrate the operation of the example OLED circuit of FIG. 10A. As can be seen in FIG. 10B, in the initialization phase, when a low scan voltage is applied on scan line 1006, a low data voltage is applied on data line 1002, and a high emission voltage is applied on the emission line, the voltage at location 1014 at the anode of the OLED 1030 may be discharged along discharge path 1064 through transistor 1024 and diode-connected transistor 1023, if the voltage is sufficiently high. Similarly, the voltage at location 1012 at the gate of driving transistor 1025 may be discharged along discharge path 1062 through transistor 1027 and diode- connected transistor 1026 if the voltage is sufficiently high.
[0075] As can be seen in FIG. IOC, in the programming phase, when a low scan voltage is applied on scan line 1006, a high data voltage is applied on data line 1002, and a high emission voltage is applied on the emission line, the voltage at the plate of the storage capacitor 1040 will be charged to a voltage (VDataHigh - |VTTI5|). AS the potential at the plate of storage capacitor 1040 is equal to the potential at location 1012 at the gate of driving transistor 1025, the driving transistor 1025 will be turned off once the potential reaches (VDataHigh - |VTTI5|). This charging will occur along path 1072 passing from the data line 1002 through data switch transistor 1021, driving transistor 1025, and transistor 1028. Transistors 1024 and 1027 may serve a leak-suppression function in the OLED circuit 1000 due to possible leakage through diode-connected transistors 1023 and 1026.
[0076] As can be seen in FIG. 10D, in the emission phase, when a low emission voltage is applied on the emission line 1008 and a low data voltage is applied on the data line 1002, the OLED 1030 is energized by current flowing along path 1082 through power conduction transistor 1029, driving transistor 1025, and OLED-connected transistor 1022. Because the threshold voltage of driving transistor 1025 was stored on storage capacitor 1040 during the programming phase, the current through the OLED 1030 will be independent of the threshold voltage of the driving transistor 1025.
[0077] FIG. 11A schematically illustrates an alternative implementation of an OLED circuit, which uses one fewer transistor than the implementation of FIG. 3. The OLED circuit 1100 includes eight transistors, including a driving transistor 1125, a power conduction transistor 1129, an OLED-connected transistor 1122, a data switch transistor 1121, and two diode-connected transistors 1123 and 1126. The OLED circuit 1100 is equivalent to the OLED circuit 900 of FIG. 9, without the inclusion of transistor 1124.
[0078] FIGS. 11B to 11D schematically illustrate the operation of the example OLED circuit of FIG. 11A. As can be seen in FIG. 11B, in the initialization phase, when a low scan voltage is applied on scan line 1106, a low data voltage is applied on data line 1102, and a high emission voltage is applied on the emission line, the voltage at location 1114 at the anode of the OLED 1130 may be discharged along discharge path 1162 through diode-connected transistor 1123 and data switch transistor 1121 if the voltage is sufficiently high. Similarly, the voltage at location 1112 at the plate of the storage capacitor 1140 may be discharged along discharge path 1162 through transistor 1127, diode-connected transistor 1126, and data switch transistor 1121 if the voltage is sufficiently high.
[0079] As can be seen in FIG. 11C, in the programming phase, when a low scan voltage is applied on scan line 1106, a high data voltage is applied on data line 1102, and a high emission voltage is applied on the emission line, the voltage at the plate of the storage capacitor 1140 will be charged to a voltage (VDataHigh - |VTTI5|). AS the location 1112 is at the same potential as the gate of driving transistor 1125, the driving transistor 1125 will be turned off once the potential reaches (VDataHigh - |VTTI5|). This charging will occur along path 1172 passing from the data line 1102 through data switch transistor 1121, driving transistor 1125, and transistors 1127 and 1128. The leakage-suppressing transistor 1127 may suppress leakage through diode-connected transistor 1126, but no dedicated leakage-suppressing transistor is provided for diode-connected transistor 1123 in the OLED circuit 1100. Rather, leakage suppression can be provided through selection of the threshold voltage of the diode-connected transistor 1123.
[0080] As can be seen in FIG. 11D, in the emission phase, when a low emission voltage is applied on the emission line 1108 and a low data voltage is applied on the data line 1102, the OLED 1130 is energized by current flowing along path 1182 through power conduction transistor 1129, driving transistor 1125, and OLED-connected transistor 1122. In some implementations, because the threshold voltage of driving transistor 1125 was stored on storage capacitor 1140 during the programming phase, the current through the OLED 1130 will again be independent of the threshold voltage of the driving transistor 1125. The independence from the threshold voltage will result in more uniformity across an OLED display.
[0081] FIG. 12A schematically illustrates an alternative implementation of an OLED circuit, which uses two fewer transistors than the implementation of FIG. 3. The OLED circuit 1200 includes seven transistors, including a driving transistor 1225, a power conduction transistor 1229, an OLED-connected transistor 1222, a data switch transistor 1221, and two diode-connected transistors 1223 and 1228. The OLED circuit 1200 is equivalent to the OLED circuit 800 of FIG. 8, without the inclusion of leak- suppressing transistors 824 and 827.
[0082] FIGS. 12B to 12D schematically illustrate the operation of the example OLED circuit of FIG. 12A. As can be seen in FIG. 12B, in the initialization phase, when a low scan voltage is applied on scan line 1206, a low data voltage is applied on data line 1202, and a high emission voltage is applied on the emission line 1208, the voltage at location 1214 at the anode of the OLED 1230 may be discharged along discharge path 1262 through diode-connected transistor 1223 and data switch transistor 1221 if the voltage is sufficiently high. Similarly, the voltage at location 1212 at the plate of the storage capacitor 1240 may be discharged along discharge path 1262 through diode-connected transistor 1226, and data switch transistor 1221 if the voltage is sufficiently high.
[0083] As can be seen in FIG. 12C, in the programming phase, when a low scan voltage is applied on scan line 1206, a high data voltage is applied on data line 1202, and a high emission voltage is applied on the emission line 1208, the voltage at the plate of the storage capacitor 1240 will be charged to a voltage (VDataHigh - |VTTI5|). AS the location 1212 is at the same potential as the gate of driving transistor 1225, the driving transistor 1225 will be turned off once the potential reaches (VDataHigh - |VTTI5|). This charging will occur along path 1272 passing from the data line 1202 through data switch transistor 1221, driving transistor 1225, and transistor 1228. Unlike the other OLED circuits described herein, no dedicated leakage-suppressing transistor is provided for diode-connected transistors 1223 or 1226 in the OLED circuit 1100. Rather, leakage suppression can be provided through selection of the threshold voltage of the diode- connected transistor 1223 and 1226.
[0084] As can be seen in FIG. 12D, in the emission phase, when a low emission voltage is applied on the emission line 1208 and a low data voltage is applied on the data line 1202, the OLED 1230 is energized by current flowing along path 1282 through power conduction transistor 1229, driving transistor 1225, and OLED-connected transistor 1222. In some implementations, because the threshold voltage of driving transistor 1225 was stored on storage capacitor 1240 during the programming phase, the current through the OLED 1230 will again be independent of the threshold voltage of the driving transistor 1225, resulting in greater uniformity across an OLED display.
[0085] Although described herein with respect to OLED displays, the processes and structures described herein can be used in conjunction with other types of displays or any other appropriate display technology, including but not limited to display technologies which benefit from reversing the bias of the display elements.
[0087] The various illustrative logics, logical blocks, modules, circuits and algorithm processes described in connection with the implementations disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. The interchangeability of hardware and software has been described generally, in terms of functionality, and illustrated in the various illustrative components, blocks, modules, circuits and processes described throughout. Whether such functionality is implemented in hardware or software depends upon the particular application and design constraints imposed on the overall system.
[0088] The hardware and data processing apparatus used to implement the various illustrative logics, logical blocks, modules and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose single- or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, or, any conventional processor, controller, microcontroller, or state machine. A processor also may be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In some implementations, particular processes and methods may be performed by circuitry that is specific to a given function.
[0089] In one or more aspects, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this specification and their structural equivalents thereof, or in any combination thereof. Implementations of the subject matter described in this specification also can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage media for execution by, or to control the operation of, data processing apparatus.
[0090] If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. The processes of a method or algorithm disclosed herein may be implemented in a processor-executable software module which may reside on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that can be enabled to transfer a computer program from one place to another. A storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer- readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to store desired program code in the form of instructions or data structures and that may be accessed by a computer. Also, any connection can be properly termed a computer-readable medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operations of a method or algorithm may reside as one or any combination or set of codes and instructions on a machine readable medium and computer-readable medium, which may be incorporated into a computer program product.
[0091] Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein.
[0092] Additionally, a person having ordinary skill in the art will readily appreciate, the terms "upper" and "lower" are sometimes used for ease of describing the figures, and indicate relative positions corresponding to the orientation of the figure on a properly oriented page, and may not reflect the proper orientation of any device as implemented.
[0094] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Further, the drawings may schematically depict one more example processes in the form of a flow diagram. However, other operations that are not depicted can be incorporated in the example processes that are schematically illustrated. For example, one or more additional operations can be performed before, after, simultaneously, or between any of the illustrated operations. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. Additionally, other implementations are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results.

中文:
[0001]本发明涉及显示系统,且特定来说涉及经配置以允许缩减像素大小的有机发光二极管(OLED)显示器。
[0002]有机发光二极管(OLED)显示器可能包含可以使OLED元件的偏压反向的电路。通过周期性地使OLED的偏压反向,可以延长OLED的使用寿命。
[0003]本发明的系统、方法及装置各自具有数项创新方面,其中无一者单独决定本文中所揭示的所要性质。
[0004]本发明中所描述的标的物的一个创新方面可以实施在有机发光二极管(OLED)控制电路中,所述有机发光二极管控制电路可经配置以从数据线、发射线、扫描线、高电源线和低电源线接收信号。所述OLED控制电路可以包含:有机发光二极管(OLED),其具有阳极和阴极,所述阴极与所述低电源线电连通;驱动晶体管,其具有栅极、源极和漏极,所述驱动晶体管的所述源极与所述OLED电连通且所述驱动晶体管的漏极与所述高电源线电连通;存储电容器,所述存储电容器的第一极板与所述驱动晶体管的所述栅极和所述漏极两者电连通,且所述存储电容器的第二极板与所述低电源线电连通;数据切换晶体管,其具有与所述数据线电连通的源极,与所述驱动晶体管的所述漏极电连通的漏极和与所述扫描线电连通的栅极,以及第一二极管连接晶体管。所述第一二极管连接晶体管具有栅极、漏极和源极,所述第一二极管连接晶体管的所述漏极连接到所述第一二极管连接晶体管的所述栅极且与所述数据线电连通,且所述第一二极管连接晶体管的所述源极与所述OLED的所述阳极电连通。
[0005]在一些实施方案中,所述电路可以另外包含第二二极管连接晶体管,其具有源极、栅极和漏极,所述第二二极管连接晶体管的所述漏极连接到所述第一二极管连接晶体管的所述栅极且与所述数据线电连通,且所述第二二极管连接晶体管的所述源极与所述存储电容器的所述第一极板电连通。电路可以另外包含连接在所述第一二极管连接晶体管的所述源极与所述OLED的所述阳极之间的第一泄漏抑制晶体管。所述电路可以另外包含第二泄漏抑制晶体管,所述第二泄漏抑制晶体管连接在所述第一二极管连接晶体管的所述源极与所述存储电容器的所述第一极板之间。
[0006]在一些实施方案中,所述电路可以另外包含功率传导晶体管,所述功率传导晶体管连接在所述驱动晶体管的所述源极与所述高电源线之间,所述功率传导晶体管具有与所述发射线电连通的栅极,与所述高电源线电连通的源极和与所述功率传导晶体管的所述源极电连通的漏极。所述电路可以另外包含OLED连接晶体管,所述OLED连接晶体管连接在所述数据切换晶体管与所述OLED的所述阳极之间,所述OLED连接晶体管具有与所述发射线电连通的栅极,与OLED电连通的源极和与所述数据切换晶体管电连通的漏极。
[0007]在一些实施方案中,所述OLED电路可以经配置以通过将电压从所述OLED的所述阳极泄放通过所述第一二极管连接晶体管来初始化所述OLED以使所述OLED的偏压反向。所述存储电容器的所述第一极板可以经配置以存储参考电压,且所述参考电压可以为施加在所述数据线上的高数据电压和所述驱动晶体管的阈值电压的函数。
[0008]本发明中所描述的标的物的另一创新方面可以实施在有机发光二极管(OLED)控制电路中,所述有机发光二极管控制电路可经配置以从数据线、发射线、扫描线、高电源线和低电源线接收信号。OLED控制电路可以包含:有机发光二极管(OLED),其具有阳极和阴极,所述阴极与所述低电源线电连通;驱动晶体管,其具有栅极、源极和漏极,所述驱动晶体管的所述源极与所述OLED电连通且所述驱动晶体管的漏极与所述高电源线电连通;用于存储参考电压的装置,所述参考电压为施加在所述数据线上的高数据电压和所述驱动晶体管的阈值电压的函数;数据切换晶体管,其具有与所述数据线电连通的源极,与所述驱动晶体管的所述漏极电连通的漏极和与所述扫描线电连通的栅极;以及用于通过将电压从所述OLED的所述阳极泄放通过所述第一二极管连接晶体管来初始化所述OLED电路以使所述OLED的偏压反向的装置。
[0009]在一些实施方案中,所述存储装置可以包含存储电容器,所述存储电容器的第一极板与所述驱动晶体管的所述栅极和所述漏极两者电连通,所述存储电容器的第二极板与所述低电源线电连通。所述初始化装置可以包含第一二极管连接晶体管,所述第一二极管连接晶体管具有栅极、漏极和源极,所述第一二极管连接晶体管的所述漏极连接到所述第一二极管连接晶体管的所述栅极且与所述数据线电连通,且所述第一二极管连接晶体管的所述源极与所述OLED的所述阳极电连通。所述电路可以另外包含第二二极管连接晶体管,其具有源极、栅极和漏极,所述第二二极管连接晶体管的所述漏极连接到所述第一二极管连接晶体管的栅极且与所述数据线电连通,且所述第二二极管连接晶体管的所述源极与所述存储电容器的所述第一极板电连通。电路可以另外包含连接在所述第一二极管连接晶体管的所述源极与所述OLED的所述阳极之间的第一泄漏抑制晶体管。所述电路可以另外包含第二泄漏抑制晶体管,所述第二泄漏抑制晶体管连接在所述第一二极管连接晶体管的所述源极与所述存储电容器的所述第一极板之间。
[0010]在一些实施方案中,所述电路可以另外包含功率传导晶体管,所述功率传导晶体管连接在所述驱动晶体管的所述源极与所述高电源线之间,所述功率传导晶体管具有与所述发射线电连通的栅极,与所述高电源线电连通的源极和与所述功率传导晶体管的所述源极电连通的漏极。所述电路可以另外包含OLED连接晶体管,所述OLED连接晶体管连接在所述数据切换晶体管与所述OLED的所述阳极之间,所述OLED连接晶体管具有与所述发射线电连通的栅极,与OLED电连通的源极和与所述数据切换晶体管电连通的漏极。
[0011]本发明中所描述标的物的另一创新方面可以实施在一种控制与数据线、发射线、扫描线、高电源线和低电源线电连通的有机发光二极管(OLED)电路的方法中,所述方法可包含:通过以下操作来初始化OLED电路:在所述数据线上施加低压信号,且将OLED的阳极放置成经由二极管连接晶体管与所述低压信号电连通;通过以下操作来对所述OLED进行编程:在所述数据线上施加高压信号,且通过经由所述OLED电路的驱动晶体管对存储电容器的极板进行充电来将参考电压存储在所述存储电容器的所述极板上,所述参考电压为施加在所述数据线上的所述高压信号和所述OLED电路的所述驱动晶体管的阈值电压的函数;及通过施加通过所述OLED的电流来激励所述OLED。
[0012]在一些实施方案中,初始化所述OLED电路可以使所述OLED的偏压反向。激励所述OLED可以包含施加通过所述OLED的电流,所述电流与所述驱动晶体管的所述阈值电压无关。所述方法可以另外包含:在所述发射线上施加发射信号,且同时在所述扫描线上施加扫描信号,其中所述发射信号是由与所述OLED电路电连通的驱动器电路生成,且其中所述扫描信号是由所述同一驱动器电路生成。
[0013]在随附图式和以下描述中陈述本发明中所描述的标的物的一或多个实施方案的细节。根据所述描述、图式和权利要求书将明了其它特征、方面和优点。注意,以下图的相对尺寸可并不按比例绘制。
[0014]图1示意性地说明OLED电路的实例实施方案,所述OLED电路使用专用的初始化电压来使OLED电路的极性反向。
[0015]图2说明可以施加在图1的OLED电路的数据信号的实例。
[0016]图3示意性地说明OLED电路的实例实施方案,所述OLED电路可以使OLED电路的极性反向而无需专用的初始化电压线。
[0017]图4A到4C示意性地说明图3的OLED电路的驱动方案中的实例阶段。
[0018]图5说明在图4A到4C的驱动方案中可以施加在图3的OLED电路的数据信号的实例。
[0019]图6为说明用于驱动OLED电路(例如图3的OLED电路)的实例过程中某些阶段的流程图。
[0020]图7A示意性地说明实例OLED电路的替代实施方案。
[0021]图7B到7D示意性地说明图7A的实例OLED电路的操作。
[0022]图8A示意性地说明实例OLED电路的替代实施方案。
[0023]图8B到8D示意性地说明图8A的实例OLED电路的操作。
[0024]图9A示意性地说明实例OLED电路的替代实施方案。
[0025]图9B到9D示意性地说明图9A的实例OLED电路的操作。
[0026]图10A示意性地说明实例OLED电路的替代实施方案。
[0027]图10B到10D示意性地说明图10A的实例OLED电路的操作。
[0028]图10A示意性地说明实例OLED电路的替代实施方案。
[0029]图10B到10D示意性地说明图10A的实例OLED电路的操作。
[0030]图11A示意性地说明实例OLED电路的另一替代实施方案,所述实例OLED电路使用晶体管的数目比图3的实施方案少一个。
[0031]图11B到11D示意性地说明图11A的实例OLED电路的操作。
[0032]图12A示意性地说明实例OLED电路的另一替代实施方案,所述实例OLED电路使用晶体管的数目比图3的实施方案少两个。
[0033]图12B到12D示意性地说明图12A的实例OLED电路的操作。
[0034]在各种图式中相同参考编号及名称指示相同元件。
[0035]以下说明是针对用于描述本发明的创新性方面的目的的特定实施方案。然而,所属领域的技术人员应易于认识到,可以许多不同的方式来应用本文中的教示。所描述的实施方案可以实施在能够显示图像(无论是运动图像(例如视频)还是静止图像(例如,静态图像),且无论是文字图像,图形图像还是图片图像)的任何装置、设备或系统中。除了并入有来自一或多种显示技术的特征的显示器之外,本发明中提供的概念和实例还可以应用于有机发光二极管(OLED)显示器。
[0036]所描述的实施方案可以包含在各种电子装置中或与其相关联,例如,但不限于:移动电话、支持多媒体互联网的蜂窝电话、移动电视接收器、无线装置、智能手机、装置、个人数据助理(PDA)、无线电子邮件接收器、手持式或便携式计算机、上网本、笔记本、智能本、平板、打印机、复印机、扫描仪、传真装置、全球定位系统(GPS)接收器/导航器、照相机、数字媒体播放器(例如MP3播放器)、便携式摄像机、游戏机、手表、可穿戴装置、时钟、计算器、电视监视器、平板显示器、电子阅读装置(例如电子阅读器)、计算机监视器、自动显示器(例如里程表和速度计显示器)、驾驶舱控制和/或显示器、摄像机视图显示器(例如车辆中后视摄像机的显示器、电子照片、电子广告牌或标牌、投影仪、建筑结构、微波炉、冰箱、立体声系统、盒式录音机或播放器、DVD播放器、CD播放器、VCR、收音机、便携式存储芯片、洗衣机、干衣机、洗衣机/干衣机、停车收费表,封装和美学结构(例如在一件珠宝或服装上的图像显示器)。
[0037]可以通过周期性地使OLED电路的偏压反向以使OLED放电来延长OLED电路的使用寿命。在OLED阵列的一些实施方案中,每一OLED电路与专用的初始化电压线通信,所述专用的初始化电压线可以用于复位驱动薄膜晶体管(TFT)的栅极电压以使OLED偏压反向。然而,由于每一OLED元件必须与初始化电压线电连通,因此包含此类专用的初始化电压线在OLED阵列中需要大量的面积。在一些实施方案中,OLED电路可以经配置以具有可反向的极性,而无需使用专用的OLED电路。
[0038]可实施本发明中所描述的标的物的特定实施方案以实现以下潜在优点中的一或多者。通过提供能够使极性反向的OLED电路,可以延长OLED面板的使用寿命。然而,通过省略初始化电压线,可以增加OLED面板的像素密度,因为每一行(或列)不需要包含用于专用初始化电压线的空间。相反,可以使用单个扫描信号、发射信号和数据信号来驱动每一OLED电路,从而简化了OLED电路的设计和制造。在本文中所描述的OLED电路的一些实施方案中,可以实现额外优点,包含简化面板驱动器电路。例如,在一些实施方案中,可以使用单个扫描行驱动器来生成发射信号和扫描信号。
[0039]图1示意性地说明OLED电路的实例实施方案,所述OLED电路使用专用的初始化电压来使OLED电路的极性反向。在所说明的实施方案中,OLED电路100的组件与数据线102、高压处的第一电源线104a、发射线108、第一扫描线106a和第二扫描线106b以及初始化电压线110电连通。OLED电路包含七个晶体管121到127,包含经配置以控制OLED 130的状态的驱动晶体管125。OLED 130还以低于第一电源线104a的高压的电压连接到第二电源104b。电容器140连接到驱动晶体管125的栅极。
[0040]第一扫描线106a连接到晶体管123和127的栅极。第二扫描线106b连接到晶体管122和125的栅极。发射线108连接到晶体管121和126的栅极。第一电源线104连接到晶体管126的源极,且连接到与驱动晶体管125的栅极相对的电容器140的极板。初始化电压线110连接到晶体管123的源极和晶体管127的源极,且可用于复位驱动TFT125的栅极电压以复位驱动晶体管125的栅极电压使OLED电路的偏压反向。
[0041]图2说明可以施加在图1的OLED电路的数据信号的实例。在操作中,可以通过在数据线102和第一扫描线106a上施加低信号,且在发射线108和第二扫描线106b上施加高信号来初始化OLED。然后,可以通过在发射线108和第一扫描线106a上施加高信号且在数据线102和第二条扫描线106b上施加低信号来编程OLED。然后,在发射阶段,在第一扫描线106a和第二扫描线106b上施加高信号,在发射线108和数据线102上施加低信号。对于给定帧,可以经由初始化电压线110控制OLED电路的极性。
[0042]为了使OLED显示器中的OLED电路中的每一者的偏压可反向,利用图1电路的OLED显示器在OLED显示器的每一排或行中均包含专用的初始化线。在此OLED显示器中大量的专用初始化线影响OLED显示器的可能像素密度。此设计表示显示器内OLED的使用寿命与像素密度之间的折衷。然而,在一些其它实施方案中,可以不需要专用的初始化电压线来使偏压反向,从而允许更大的像素密度以及由使OLED的偏压反向而增加的使用寿命。
[0043]图3示意性地说明OLED电路的实例实施方案,所述OLED电路可以使OLED电路的极性反向而无需专用的初始化电压线。可反向OLED电路200包含数据线202、第一电压线204a、第二电压线204b、扫描线206和发射线208。数据线202连接到数据切换晶体管221的源极以及二极管连接晶体管223和226的漏极。扫描线206连接到晶体管221、224、227和228的栅极。发射线208连接到晶体管222和229的栅极。第一电源线204a连接到晶体管229的源极,以及与驱动晶体管225的栅极相对的电容器240的极板。
[0044]在图3中可以看到,晶体管223和226为二极管连接的,晶体管的漏极与晶体管的栅极之间具有电连接。如本文中更详细所描述,此配置允许OLED 230的阳极的初始化,而无需专用的初始化电压线,例如图1的OLED电路100的初始化电压线110。因为此类二极管连接晶体管可能容易泄漏,所以将泄漏抑制晶体管224和227分别连接到二极管连接晶体管226和223的源极。在一些实施方案中,可以在初始化周期期间而非在寻址周期期间将OLED 230的初始化电压从数据线202直接施加到OLED 230。
[0045]图4A到4C示意性地说明图3的OLED电路的驱动方案中的实例阶段。图5说明在图4A到4C的驱动方案中可以施加在图3的OLED电路的数据信号的实例。
[0046]图4A说明处于初始化阶段中的OLED电路200。在所说明的实施方案中,在数据线202上施加低数据电压VDataLow且在扫描线206上施加低扫描电压VScanLow。同时,在发射线208上施加高发射电压VEmHigh。上述情况将功率传导晶体管229连同OLED控制晶体管222关断。将沿着扫描线206的晶体管221、224、227和228连同二极管连接晶体管223和226接通。
[0048]类似地,位置212(在驱动晶体管225的栅极和存储电容器240的邻近极板处)处的电压将在位置212处的电压足够高的情况下通过二极管连接晶体管226放电。图4A示意性地说明从位置212到数据线202的放电路径262。如果位置212处的电压高于(VDataLow+|VTh3|),其中VTh3为晶体管223的阈值电压,所述电压将被放电到(VDataLow+|VTh3|)。如果位置212处的电压低于(VDataLow+|VTh5),其中VTh5为驱动晶体管225的阈值电压,位置212处的电压将通过驱动晶体管225充电到(VDataLow+|VTh5|)。
[0049]因为晶体管223和226为二极管连接的,所以其阈值电压VTh3和VTh6可用于当在数据线202上施加低压VDataLow时控制位置212和214被放电到的电压。阈值电压限制放电到比低压VDataLow高的电压。
[0050]图4B说明处于编程阶段中的OLED电路200。在所说明的实施方案中,在数据线202上施加高数据电压VDataHigh,且在发射线208上施加高发射电压VEmHigh。同时,在扫描线206上施加低扫描电压VScanLow。功率传导晶体管229连同OLED控制晶体管222保持关断。另外,二极管连接晶体管223和226关断。沿着扫描线206的晶体管221、224、227和228保持接通。
[0051]位置214处的电压将在其尚未处于低压的情况下在此编程阶段期间保持不受影响,保持处于其在初始化阶段器件被放电到的电压。OLED 230因此保持处于反向偏压。然而,位置212处的电压将被充电到取决于驱动晶体管225的阈值电压的电压。图4B示意性地说明从数据线202通过驱动晶体管252到在驱动晶体管的栅极处的位置212的充电路径272。电压将被充电到(VDataHigh-|VTh5|),此时驱动晶体管225将被关断。
[0052]通过将位置212处的电压设置为取决于阈值电压VTh5的电压,存储电容器240的连接极板上的电压可以被设置为取决于数据线电压和阈值电压VTh5的电压。使用上述情况,OLED电路200可以补偿阈值电压VTh5,并使用与阈值电压VTh5无关的电流驱动OLED 230。
[0053]在图4B中可以看到,如果二极管连接晶体管223和226为泄漏时,那么数据线202上的高压可能影响位置212被充电到的电压。阈值电压VTh3和VTh3可以经选择处于-1.5伏与-2.5伏之间,以最小化或防止泄漏电流的影响。可以通过在制造过程期间控制掺杂密度来控制pMOS或nMOS晶体管的阈值电压。
[0054]图4C说明处于发射阶段中的OLED电路200。在所说明的实施方案中,在发射线208上施加低发射电压VEmLow且在数据线202上施加低数据电压VDataHigh。将沿着扫描线206的晶体管221、224、227和228关断,且功率传导晶体管229和OLED控制晶体管222接通。
[0055]因为晶体管227被关断,所以位置212(在驱动晶体管225的栅极处和存储电容器240的邻近极板上)处的电压保持处于(VDataHigh-|VTh5|)。电流沿着路径282从第一电压线204a流动通过OLED 230。因为应力栅极电压也是驱动晶体管225的阈值电压VTh5的函数,所以通过OLED的电流I可以被定义为高压VHigh与高数据电压VDataHigh之间的差的平方的函数,所述高数据电压保持存储在存储电容器240上。由于在编程阶段发生的电压补偿,因此通过OLED的电流I与驱动电压无关。高数据电压VDataHigh可以为大于横跨OLED的最大电压VOLEDHigh但小于由第一电压线204a供应的高压VHigh的任何合适的值。
[0056]在图5中可以看到,施加在发射线208上的发射信号在所说明驱动方案的每一阶段期间为施加在数据线202上的数据信号的反向。OLED配置的另一优点是利用单行驱动器来生成发射信号和数据信号两者,或以其它方式使用至少一些共用电路来生成发射信号和数据信号两者的能力。除了省略专用的初始化电压线所允许的增加的像素密度外,需要一个扫描信号并使用同一驱动器电路生成所述扫描信号和发射信号的OLED显示器也可能导致显示器的边缘处边界大小的缩减。因为边界不需要容纳发射行驱动器和单独的扫描行驱动器两者,所以可以使没有OLED像素的边界区域变小,从而导致有效显示空间相对于整个显示空间增加。
[0057]图6为说明用于驱动OLED电路(例如图3的OLED电路)的实例过程中某些阶段的流程图。所述过程包含阶段605,其中初始化OLED电路。在OLED电路的数据线上施加低数据电压,且在OLED电路的扫描线上施加低扫描电压。在发射线上施加高发射电压以关断OLED电路的功率晶体管和OLED连接晶体管,因此不会激励OLED。OLED电路的其余组件经配置使得通过二极管连接晶体管将与连接到高电源的极板相对的存储电容器的极板处的电压放电。类似地,通过二极管连接晶体管将OLED的阳极处的电压放电。这些位置中的每一者处所产生的电压可以取决于借以将其放电的二极管连接晶体管的阈值电压。如果需要,通过此过程将OLED放电,且现在使OLED的偏压反向。
[0058]所述过程包含阶段610,其中对OLED电路进行编程。发射线信号保持处于低发射电压,以使得OLED保持不激励,且OLED的偏压保持反向。扫描信号保持处于低扫描电压,但在数据线上施加高数据电压。与连接到高电源的极板相对的存储电容器的极板处的电压经增加到为高数据电压和OLED电路的驱动晶体管的阈值电压的函数的电压,从而将此信息写入到存储电容器。
[0059]所述过程包含阶段615,其中OLED经激励。现在,在发射线上施加高发射电压,从而接通功率传导晶体管和OLED连接晶体管,且允许电流流动通过OLED,从而激励OLED。同时,在扫描线上施加高扫描电压,且在数据线上施加低数据电压。因为存储在与高电源相对的存储电容器的极板上的电压为驱动导体的阈值电压的函数,所以在阶段615处流动通过OLED的电流与驱动导体的阈值电压无关。
[0060]图3中所说明的OLED电路仅仅为具有本文中所描述特征的OLED电路的一种可能的实施方案。可以提供包含本文中所论述的特征中的至少一些特征的数个其它OLED电路布置。
[0061]图7A示意性地说明实例OLED电路的替代实施方案。如同图3的OLED电路200,OLED电路700包含两个二极管连接晶体管723和728。OLED 730的阳极电压可以在驱动方案的初始化阶段期间通过晶体管724和二极管连接晶体管723放电,且驱动晶体管725的栅极处的电压可以通过晶体管727和二极管连接晶体管726放电。在随后的编程阶段中,可以将存储电容器740的极板处的电压充电到为驱动电容器的阈值电压的函数的电压,从而补偿驱动电容器的阈值电压。可施加与经施加以驱动OLED电路200相同的驱动信号以驱动OLED电路700。
[0062]图7B到7D示意性地说明图7A的实例OLED电路的操作。如在图7B中可以看到,在初始化阶段中,当在扫描线706上施加低扫描电压,在数据线702上施加低数据电压,且在发射线上施加高发射电压时,位置714(在OLED 730的阳极处)处的电压可在电压足够高的情况下通过晶体管727和二极管连接晶体管723沿着放电路径764放电。类似地,位置712(在驱动晶体管725的栅极处)处的电压可在电压足够高的情况下通过晶体管724和二极管连接晶体管726沿着放电路径762放电。
[0063]如在图7C中可以看到,在编程阶段中,当在扫描线706上施加低扫描电压,在数据线702上施加高数据电压,且在发射线上施加高发射电压时,存储电容器740的极板处的电压将被充电到电压(VDataHigh-|VTh5|)。由于存储电容器740的极板处的电势等于位置712(在驱动晶体管725的栅极处)处的电势,因此一旦电势达到(VDataHigh-|VTh5|),就会关断驱动晶体管725。此充电将沿着路径772发生,所述路径从数据线702通过数据切换晶体管721、驱动晶体管725以及晶体管728。晶体管724和727可能在OLED电路700中起到泄漏抑制功能,特别是在此编程阶段期间,此归因于泄漏可能通过二极管连接晶体管723和726。
[0064]如在图7D中可以看到,在发射阶段中,当在发射线708上施加低发射电压且在数据线702上施加低数据电压时,通过沿着路径782流动通过功率传导晶体管729、驱动晶体管725以及OLED连接晶体管722的电流来激励OLED 730。在一些实施方案中,因为在编程阶段期间将驱动晶体管725的阈值电压存储在存储电容器740上,所以通过OLED 730的电流将再次与驱动晶体管725的阈值电压无关,从而横跨OLED显示器产生更大的一致性。
[0065]图8A示意性地说明实例OLED电路的替代实施方案。OLED电路800还包含总共九个晶体管,包含两个二极管连接晶体管823和826。然而,OLED电路800与OLED电路的不同之处在于,在初始化阶段中,OLED 830的阳极处和存储电容器840的极板处的电压将分别通过数据切换晶体管821以及其它晶体管放电。
[0066]图8B到8D示意性地说明图8A的实例OLED电路的操作。如在图8B中可以看到,在初始化阶段中,当在扫描线806上施加低扫描电压,在数据线802上施加低数据电压,且在发射线上施加高发射电压时,位置814(在OLED 830的阳极处)处的电压可通过二极管连接晶体管823和晶体管824沿着放电路径864放电。位置812(在存储导体840的极板处)处的电压可在电压足够高的情况下通过晶体管827和二极管连接晶体管826沿着放电路径862放电。
[0067]如在图8C中可以看到,在编程阶段中,当在扫描线806上施加低扫描电压,在数据线802上施加高数据电压,且在发射线上施加高发射电压时,存储电容器840的极板处的电压将被充电到电压(VDataHigh-|VTh5|)。由于位置812(在存储电容器840的极板处)处的电势等于驱动晶体管825的栅极处的电势,因此一旦电势达到(VDataHigh-|VTh5|),就会关断驱动晶体管825。此充电将沿着路径872发生,所述路径从数据线802通过数据切换晶体管821、驱动晶体管825以及晶体管828。晶体管824和827可能在OLED电路800中起到泄漏抑制功能,特别是在此编程阶段期间,此归因于泄漏可能通过二极管连接晶体管823和826。
[0068]如在图8D中可以看到,在发射阶段中,当在发射线808上施加低发射电压且在数据线802上施加低数据电压时,通过沿着路径882流动通过功率传导晶体管829、驱动晶体管825以及OLED连接晶体管822的电流来激励OLED 830。由于在编程阶段中的电压补偿,通过OLED 830的电流将与驱动晶体管825的阈值电压无关。
[0069]图9示意性地说明实例OLED电路的替代实施方案。OLED电路900还包含总共九个晶体管,包含两个二极管连接晶体管923和926。数据切换晶体管921连接在数据线902与二极管连接晶体管923和926之间。OLED电路900将沿着路径从存储电容器940的极板和OLED 930的阳极放电,所述路径除了二极管连接晶体管923和926中的一者外还包含数据切换晶体管921。
[0070]图9B到9D示意性地说明图9A的实例OLED电路的操作。如在图9B中可以看到,在初始化阶段中,当在扫描线906上施加低扫描电压,在数据线902上施加低数据电压,且在发射线上施加高发射电压时,位置914(在OLED 930的阳极处)处的电压可下通过晶体管924、二极管连接晶体管923和数据切换晶体管921沿着放电路径964放电。位置912(在存储导体940的极板处)处的电压可在电压足够高的情况下通过晶体管927、二极管连接晶体管926和数据切换晶体管921沿着放电路径962放电。这些电势放电路径中的每一者在通过二极管连接晶体管之后,通过数据切换晶体管921。
[0071]如在图9C中可以看到,在编程阶段中,当在扫描线906上施加低扫描电压,在数据线902上施加高数据电压,且在发射线上施加高发射电压时,存储电容器940的极板处的电压将被充电到电压(VDataHigh-|VTh5|)。由于位置912(在存储电容器940的极板处)处的电势等于驱动晶体管925的栅极处的电势,因此一旦电势达到(VDataHigh-|VTh5|),就会关断驱动晶体管925。此充电将沿着路径972发生,所述路径从数据线902通过数据切换晶体管921、驱动晶体管925以及晶体管928。晶体管924和927可能在OLED电路900中起到泄漏抑制功能,特别是在此编程阶段期间,此归因于泄漏可能通过二极管连接晶体管923和926。
[0072]如在图9D中可以看到,在发射阶段中,当在发射线908上施加低发射电压且在数据线902上施加低数据电压时,通过沿着路径982流动通过功率传导晶体管929、驱动晶体管825以及OLED连接晶体管822的电流来激励OLED 930。由于在编程阶段中的电压补偿,在发射阶段期间通过OLED 930的电流将与驱动晶体管925的阈值电压无关。
[0073]图10A示意性地说明实例OLED电路的替代实施方案。OLED电路1000还包含总共九个晶体管,包含两个二极管连接晶体管1023和1026。
[0074]图10B到10D示意性地说明图10A的实例OLED电路的操作。如在图10B中可以看到,在初始化阶段中,当在扫描线1006上施加低扫描电压,在数据线1002上施加低数据电压,且在发射线上施加高发射电压时,位置1014(在OLED 1030的阳极处)处的电压可在电压足够高的情况下通过晶体管1024和二极管连接晶体管1023沿着放电路径1064放电。类似地,位置1012(在驱动晶体管1025的栅极处)处的电压可在电压足够高的情况下通过晶体管1027和二极管连接晶体管1026沿着放电路径1062放电。
[0075]如在图10C中可以看到,在编程阶段中,当在扫描线1006上施加低扫描电压,在数据线1002上施加高数据电压,且在发射线上施加高发射电压时,存储电容器1040的极板处的电压将被充电到电压(VDataHigh-|VTh5|)。由于存储电容器1040的极板处的电势等于位置1012(在驱动晶体管1025的栅极处)处的电势,因此一旦电势达到(VDataHigh-|VTh5|),就会关断驱动晶体管1025。此充电将沿着路径1072发生,所述路径从数据线1002通过数据切换晶体管1021、驱动晶体管1025以及晶体管1028。晶体管1024和1027可能在OLED电路1000中起到泄漏抑制功能,此归因于泄漏可能通过二极管连接晶体管1023和1026。
[0076]如在图10D中可以看到,在发射阶段中,当在发射线1008上施加低发射电压且在数据线1002上施加低数据电压时,通过沿着路径1082流动通过功率传导晶体管1029、驱动晶体管1025以及OLED连接晶体管1022的电流来激励OLED 1030。因为在编程阶段期间将驱动晶体管1025的阈值电压存储在存储电容器1040上,所以通过OLED 1030的电流将与驱动晶体管1025的阈值电压无关。
[0077]图11A示意性地说明OLED电路的替代实施方案,所述OLED电路使用晶体管的数目比图3的实施方案少一个。OLED电路1100包含八个晶体管,包含驱动晶体管1125、功率传导晶体管1129、OLED连接晶体管1122、数据切换晶体管1121和两个二极管连接晶体管1123和1126。OLED电路1100等同于图9的OLED电路900,但不包含晶体管1124。
[0078]图11B到11D示意性地说明图11A的实例OLED电路的操作。如在图11B中可以看到,在初始化阶段中,当在扫描线1106上施加低扫描电压,在数据线1102上施加低数据电压,且在发射线上施加高发射电压时,位置1114(在OLED 1130的阳极处)处的电压可在电压足够高的情况下通过晶体管1123和二极管连接晶体管1121沿着放电路径1162放电。类似地,位置1112(在存储电容器1140的极板处)处的电压可在电压足够高的情况下通过晶体管1127、二极管连接晶体管1126和数据切换晶体管1121沿着放电路径1162放电。
[0079]如在图11C中可以看到,在编程阶段中,当在扫描线1106上施加低扫描电压,在数据线1102上施加高数据电压,且在发射线上施加高发射电压时,存储电容器1140的极板处的电压将被充电到电压(VDataHigh-|VTh5|)。由于位置1112处于与驱动晶体管1125的栅极相同的电势,因此一旦电势达到(VDataHigh-|VTh5|),就会关断驱动晶体管1125。此充电将沿着路径1172发生,所述路径从数据线1102通过数据切换晶体管1121、驱动晶体管1125以及晶体管1127和1128。泄漏抑制晶体管1127可以抑制通过二极管连接晶体管1126的泄漏,但没有为OLED电路1100中的二极管连接晶体管1123提供专用的泄漏抑制晶体管。相反,可以通过选择二极管连接晶体管1123的阈值电压来提供泄漏抑制。
[0080]如在图11D中可以看到,在发射阶段中,当在发射线1108上施加低发射电压且在数据线1102上施加低数据电压时,通过沿着路径1182流动通过功率传导晶体管1129、驱动晶体管1125以及OLED连接晶体管1122的电流来激励OLED 1130。在一些实施方案中,因为在编程阶段期间将驱动晶体管1125的阈值电压存储在存储电容器1140上,所以通过OLED 1130的电流将再次与驱动晶体管1125的阈值电压无关。与阈值电压无关将横跨OLED显示器产生更多一致性。
[0081]图12A示意性地说明OLED电路的替代实施方案,所述OLED电路使用晶体管的数目比图3的实施方案少两个。OLED电路1200包含七个晶体管,包含驱动晶体管1225、功率传导晶体管1229、OLED连接晶体管1222、数据切换晶体管1221和两个二极管连接晶体管1223和1228。OLED电路1200等同于图8的OLED电路800,但不包含泄露抑制晶体管824和827。
[0082]图12B到12D示意性地说明图12A的实例OLED电路的操作。如在图12B中可以看到,在初始化阶段中,当在扫描线1206上施加低扫描电压,在数据线1202上施加低数据电压,且在发射线1208上施加高发射电压时,位置1214(在OLED 1230的阳极处)处的电压可在电压足够高的情况下通过晶体管1223和二极管连接晶体管1221沿着放电路径1262放电。类似地,位置1212(在存储电容器1240的极板处)处的电压可在电压足够高的情况下通过二极管连接晶体管1226和数据切换晶体管1221沿着放电路径1262放电。
[0083]如在图12C中可以看到,在编程阶段中,当在扫描线1206上施加低扫描电压,在数据线1202上施加高数据电压,且在发射线1208上施加高发射电压时,存储电容器1240的极板处的电压将被充电到电压(VDataHigh-|VTh5|)。由于位置1212处于与驱动晶体管1225的栅极相同的电势,因此一旦电势达到(VDataHigh-|VTh5|),就会关断驱动晶体管1225。此充电将沿着路径1272发生,所述路径从数据线1202通过数据切换晶体管1221、驱动晶体管1225以及晶体管1228。与本文中所描述的其它OLED电路不同,没有为OLED电路1100中的二极管连接晶体管1223或1226提供任何专用泄漏抑制晶体管。相反,可以通过选择二极管连接晶体管1223和1226的阈值电压来提供泄漏抑制。
[0084]如在图12D中可以看到,在发射阶段中,当在发射线1208上施加低发射电压且在数据线1202上施加低数据电压时,通过沿着路径1282流动通过功率传导晶体管1229、驱动晶体管1225以及OLED连接晶体管1222的电流来激励OLED 1230。在一些实施方案中,因为在编程阶段期间将驱动晶体管1225的阈值电压存储在存储电容器1240上,所以通过OLED 1230的电流将再次与驱动晶体管1225的阈值电压无关,从而横跨OLED显示器产生更大的一致性。
[0085]尽管本文中关于OLED显示器进行了描述,但本文中所描述的过程和结构可以与其它类型的显示器或任何其它适当的显示技术(包含但不限于受益于使显示元件的偏压反向的显示技术)结合使用。
[0087]可将连同本文中所揭示的实施方案一起描述的各种说明性逻辑、逻辑块、模块、电路及算法程序实施为电子硬件、计算机软件或两者的组合。已就功能性大体阐述了硬件与软件的可互换性且在全文所描述的各种说明性组件、块、模块、电路及过程中加以说明。此功能性是实施在硬件还是软件中取决于特定应用及强加于整个系统的设计约束。
[0088]用于实施连同本文中所揭示的方面一起描述的各种说明性逻辑、逻辑块、模块和电路的硬件和数据处理设备可借助以下来实施或执行:通用单芯片或多芯片处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现场可编程门阵列(FPGA)或其它可编程逻辑装置、离散门或晶体管逻辑、离散硬件组件或其经设计以执行本文中所描述的功能的任何组合。通用处理器可为微处理器或任一习用处理器、控制器、微控制器或状态机。还可将处理器实施为计算装置的组合,例如DSP与微处理器的组合、多个微处理器、结合DSP核心的一或多个微处理器或任一其它此类配置。在一些实施方案中,可通过特定于给定功能的电路来执行特定过程和方法。
[0089]在一或多个方面中,所描述的功能可以实施在硬件、数位电子电路、计算机软件、固件(包含本说明书中所揭示的结构和其结构等效物)或其任何组合中。本说明书中所描述的标的物的实施方案还可实施为编码在计算机存储媒体上以用于由数据处理设备执行或控制数据处理设备的操作的一或多个计算机程序,即,一或多个计算机程序指令模块。
[0090]如果以软件予以实施,那么所述功能可作为一或多个指令或代码而存储于计算机可读媒体上或经由计算机可读媒体进行发射。本文中所揭示的方法或算法的过程可实施在可驻存于计算机可读媒体上的处理器可执行软件模块中。计算机可读媒体包含计算机存储媒体及包含可经启用以将计算机程序从一个地方传送到另一个地方的任何媒体的通信媒体。存储媒体可为可由计算机存取的任何可用媒体。以实例而非限制的方式,此类计算机可读媒体可包含RAM、ROM、EEPROM、CD-ROM或其它光盘存储装置、磁盘存储装置或其它磁性存储装置或可用于以指令或数据结构的形式存储所要的程序代码且可由计算机存取的任何其它媒体。此外,任何连接均可适当地称作计算机可读媒体。如本文中所使用,磁盘及光盘包含光盘(CD)、激光光盘、光学光盘、数字多功能光盘(DVD)、软盘及蓝光光盘,其中磁盘通常以磁性方式再现数据,而光盘通过激光以光学方式再现数据。上述各项的组合也应包含在计算机可读媒体的范围内。另外,方法或算法的操作可作为一个或任何代码及指令组合或集合驻存于可并入到计算机程序产品中的机器可读媒体及计算机可读媒体上。
[0091]所属领域的技术人员将轻易明了对本发明中所描述的实施方案的各种修改,且本文所界定的通用原理可应用于其它实施方案而不背离本发明的精神或范围。因此,权利要求书并非意欲限制于本文中所展示的实施方案,而是被赋予与本发明、本文中所揭示的原理及新颖特征相一致的最宽广范围。
[0092]另外,所属领域的普通技术人员应易于了解,术语“上部”和“下部”有时用于便于阐述所述图,且指示对应于所述图在适当定向的页面上的图的定向的相对位置,且可不反映如所实施的任何装置的适当定向。
[0094]类似地,虽然在所述图式中以特定次序绘示操作,但此不应理解为要求以所展示的特定次序或以顺序性次序来执行此类操作,或执行所有所说明的操作以达成所要的结果。此外,所述图式可以流程图的形式示意性地描绘一或多个实例性过程。然而,可将其它并未描绘的操作并入于示意性地说明的实例性过程中。例如,可在所说明的操作中的任一者之前、之后、同时或之间执行一或多个额外操作。在某些情形中,多任务及并行处理可为有利的。此外,上文所描述的实施方案中的各种系统组件的分离不应被理解为需要在所有实施方案中进行此分离,且所描述的程序组件及系统通常可一起整合于单个软件产品中或封装到多个软件产品中。另外,其它实施方案在以下权利要求书的范围内。在一些状况下,权利要求中所述的动作可以不同次序执行且仍达成期望的结果。