English:
[0002] A semiconductor memory device generally comprises a plurality of memory cells which are used to store a large quantity of information. Each memory cell includes a capacitor for storing electric charge and a corresponding field effect transistor for opening and closing charging and discharging passages of the capacitor. As the size of semiconductor devices continues to shrink, the area allowed to be occupied by each component of a semiconductor device decreases. Capacitors are one component that can occupy considerable area on a semiconductor die depending on the size of the capacitor and/or the number of capacitors on the die.
[0003] One example of a capacitor used in a semiconductor memory device is a metal-insulator-metal (MIM) capacitor. A traditional MIM capacitor is two-dimensional (2D). A 2D MIM capacitor has two facing metal plates which are planar and substantially parallel to each other and to the substrate. One method of increasing the capacitance of a MIM capacitor is to increase the sizes of the metal plates. However, increasing the sizes of the metal plates will consume more surface area of the substrate. A 3-dimensional (3D) MIM capacitor allows for the same capacitive surface area but consumes less surface area of a substrate. However, a 3D MIM capacitor can lose performance if a leakage current develops between the two metal plates.
[0004] Accordingly, the inventors have developed an improved 3D MIM capacitor and method of forming a 3D MIM capacitor.
[0005] In some embodiments, a method of processing a substrate comprises providing a substrate having a first polymer dielectric layer; forming a first redistribution layer (RDL) on the first polymer dielectric layer, the first RDL comprising a second polymer dielectric layer with a metal layer embedded in the second polymer dielectric layer and at least one opening in a top surface of the second polymer dielectric layer to expose at least a portion of the metal layer; constructing a 3D MIM capacitive stack on the first RDL in at least one opening in the top surface of the second polymer dielectric layer, the 3D MIM capacitive stack having a top electrode, a bottom electrode, and a capacitive dielectric layer interposed between the top electrode and the bottom electrode, the bottom electrode in electrical contact with the metal layer; depositing a dielectric layer on the 3D MIM capacitive stack and on the second polymer dielectric layer; and removing a portion of the dielectric layer to expose at least a portion of the top electrode at a bottom of at least one opening of the 3D MIM capacitive stack and to expose at least a portion of the metal layer at a bottom of at least one opening of the second polymer dielectric layer.
[0006] In some embodiments, a method of processing a substrate comprises providing a substrate having a first polymer dielectric layer; forming a first redistribution layer (RDL) on the first polymer dielectric layer, the first RDL comprising a second polymer dielectric layer with a metal layer embedded in the second polymer dielectric layer and at least one opening in a top surface of the second polymer dielectric layer to expose at least a portion of the metal layer; constructing a three- dimensional (3D) metal-insulator-metal (MIM) capacitive stack on the first RDL in at least one opening in the top surface of the second polymer dielectric layer, the 3D MIM capacitive stack having a top electrode, a bottom electrode, and a capacitive dielectric layer interposed between the top electrode and the bottom electrode, the bottom electrode in electrical contact with the metal layer; depositing a dielectric layer on the 3D MIM capacitive stack and on the second polymer dielectric layer; and removing a portion of the dielectric layer to expose at least a portion of the top electrode at a bottom of at least one opening of the 3D MIM capacitive stack and to expose at least a portion of the metal layer at a bottom of at least one opening of the second polymer dielectric layer.
[0007] In some embodiments, a substrate comprises a first polymer dielectric layer; a metal layer on the first polymer dielectric layer; a second polymer dielectric layer on the first polymer dielectric layer and the metal layer, wherein the second polymer dielectric layer comprises a plurality of openings etched to a top surface of the metal layer; a three-dimensional (3D) metal-insulator-metal (MIM) capacitive stack formed on the second polymer dielectric layer with a bottom electrode of the 3D MIM capacitive stack making electrical contact with the metal layer via at least one opening in the second polymer dielectric layer, the 3D MIM capacitive stack having a top electrode, a bottom electrode, and a capacitive dielectric layer interposed between the top electrode and the bottom electrode; a dielectric layer on the 3D MIM capacitive stack and the second polymer dielectric layer, the dielectric layer having at least one opening to the metal layer in at least one of the plurality of openings of the second polymer dielectric layer; a first contact formed on the second polymer dielectric layer, the first contact electrically connected with the metal layer; and a second contact formed on the 3D MIM capacitive stack, the second contact electrically connected to the top electrode of the 3D MIM capacitive stack.
[0010] Figures 2A-D depict stages of processing a substrate in accordance with some embodiments of the present principles.
[0011] Figures 3A-3B depict embodiments of forming a 3D MIM capacitor in accordance with some embodiments of the present principles.
[0012] Figures 4A-4B depict embodiments of forming a 3D MIM capacitor in accordance with some embodiments of the present principles.
[0013] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
[0014] Methods for processing a substrate are provided herein. The inventive methods advantageously facilitate an improved 3D MIM capacitor and method of forming a 3D MIM capacitor having reduced leakage current, enhanced system performance of the overall system (e.g., shorter connection paths), and faster processing times due to fewer required layers.
[0015] Figure 1 depicts a flow chart of a method 100 for processing a substrate in accordance with some embodiments of the present principles. Although the method 100 is shown in a functional block diagram of a particular order, processes are not required to be performed in one particular order. Some processes can be repeated and some groupings of processes can be repeated. In the same fashion, some processes may be accomplished prior to other processes and the like.
[0016] The method 100 is described in a flow diagram with respect to the structure depicted in Figures 2-4. The method 100 of the present principles may be performed in a single process chamber capable of performing both etching and deposition. Such a suitable process chamber may be a standalone process chamber, or part of a cluster tool. Alternatively, the inventive methods disclosed herein may be performed in separate chambers that also may be standalone or part of a cluster tool.
[0017] The method 100 begins at block 102 of the flow diagram by providing or depositing a first polymer dielectric layer 204 on a substrate 202 as depicted, for example, in Fig. 2A. The substrate 202 may be any suitable substrate material used in semiconductor manufacturing processes. For example, the substrate 200 may be constructed from silicon, glass, ceramic, epoxy mold compound or dielectric. The first polymer dielectric layer 204 may comprise any suitable polymer dielectric material such as polyimide or polybenzoxazole, or the like. The first polymer dielectric layer 204 is spin-coated over the substrate 202. The first polymer dielectric layer 204 may also be deposited using any suitable spin-coating process, chemical vapor deposition (CVD) process, or lithographic process. In some embodiments, the first polymer dielectric layer 204 may also be a polybenzoxazole (PBO) layer, a polyimide layer, a benzocyclobutene (BCB) layer, an epoxy layer, or a photo-sensitive material layer.
[0018] A first redistribution layer (RDL) 206 is formed on the first polymer dielectric layer 204 at block 104 of the flow diagram as shown, for example, in the cross- sectional view 200A of Fig. 2A. The first RDL 206 includes a second polymer dielectric layer 208 having a metal layer 210 and a plurality of openings 213 formed in the second polymer dielectric layer 208. The metal layer 210 may comprise any suitable conductive material used to form a metal interconnect such as copper or aluminum, or the like. The first RDL 206 is a layer to redirect connectivity and is provided over the first polymer dielectric layer 204. In some embodiments, the metal layer 210 may be formed using a plating process or deposition process, such as a physical vapor deposition (PVD) process, used in a semiconductor manufacturing processes. The second polymer dielectric layer 208 is patterned to form the plurality of openings 213. The openings 213 are formed to a top surface 21 1 of the metal layer 210. In some embodiments, the patterning process may be any suitable lithographic and/or etching process for forming openings in the second polymer dielectric layer 208. In some embodiments, the openings 213 may be a feature such as a via (e.g., such as via 212 in Figure 2B), a trench, or the like. RDLs used in some embodiments may be fan-out or fan-in.
[0019] A 3D MIM capacitive stack is then constructed on the first RDL 206 at block 106 of the flow diagram as shown, for example, in the cross-sectional view 200B of Figure 2B. The 3D MIM capacitive stack 214 may be constructed, for example, by processes provided in U.S. Patent Application No. 15/288,594, by Guan Huei See, et al., published on April 13, 2017 as 2017-0104056, and entitled Structure And Method Of Fabricating Three-Dimensional (3D) Metal-Insulator-Metal (MIM) Capacitor And Resistor In Semi-Additive Plating Metal Wiring. Figure 2C illustrates a cross-sectional view 200C of an end portion 220 of the 3D MIM capacitive stack 214 of Figure 2B. A bottom electrode layer 226 is first formed on the second polymer dielectric layer 208. The bottom layer electrode 226 has conductive properties and is typically made of a metallic-based material. A capacitive dielectric layer 224 is then formed on the bottom electrode layer 226. The dielectric material of the capacitive dielectric layer 224 can vary depending on the capacitor characteristics. In some embodiments, the capacitive dielectric layer 224 is a nitride film or a high-k dielectric material, such as hafnium oxide (Hf02), silicon nitride (Si3N4), aluminum nitride (AIN), titanium oxide (T1O2) or tantalum oxide (Ta205). A top electrode layer 222 is then formed on the capacitive dielectric layer 224. The top electrode layer 222 can be made of the same material as the bottom electrode or of a different material. The top electrode layer 222 has conductive properties as well. The layers 222-226 may be deposited using any suitable deposition process, for example a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or the like.
[0020] RDLs are often used to form conductive connections to the top electrode layer 222 and the bottom electrode layer 226. Exposure of the ends of the layers 222-226 at a sidewall 227 of the 3D MIM capacitive stack 214 can result in leakage currents that drastically reduce the performance of the 3D MIM capacitive stack 214. Previous processes required that an additional polymer dielectric layer be formed over the 3D MIM capacitive stack and then an additional RDL be formed on the additional polymer dielectric layer to reduce the leakage current. Embodiments of the present principles do not require the additional polymer dielectric layer and the additional RDL, advantageously saving processing time and materials, reducing costs, and greatly enhancing the performance of a 3D MIM capacitor by reducing leakage currents and also connection lengths. However, additional optional polymer dielectric layers and additional RDLs are not precluded from the embodiments of the present principles.
[0021] Instead of forming another polymer layer, a dielectric layer is conformally deposited on the 3D MIM capacitive stack 214 and on the second polymer dielectric layer 208 at block 108 of the flow diagram. One embodiment is shown in the cross- sectional view 200D of Figure 2D. A dielectric layer 216 may be deposited using any suitable deposition process, for example a PVD process, a CVD process, an ALD process, or the like. In some embodiments, the dielectric layer 216 is a silicon-based material such as, for example, silicon nitride, or silicon oxide. The dielectric layer 216 may have a thickness of approximately 5 nm to approximately 100 nm. In some embodiments, the dielectric layer 216 is conformally deposited so as to cover the bottom and sidewalls of openings 217 of the 3D MIM capacitive stack 214 or via 212 in the second polymer dielectric layer 208.
[0022] An etching process is then performed on the dielectric layer 216 at block 1 10 of the flow diagram. The etching process can include, but is not limited to, dry etching in a reactive ion etching chamber. In the example, the dielectric layer 216 can be etched differently in different embodiments of the present principles. In one embodiment illustrated in cross-sectional view 300A of Figure 3A, the dielectric layer 216 is etched from the surfaces until a dielectric spacer 302 remains at sidewalls 227 of the 3D MIM capacitive stack 214. In another embodiment illustrated in cross- sectional view 400A of Figure 4A, the dielectric layer 216 is etched from a bottom surface 402 of a via 212 and from bottom surfaces 404 of the 3D MIM capacitive stack 214.
[0023] After etching of the dielectric layer, a second RDL is formed on the substrate without a polymer dielectric layer on the dielectric layer and the 3D MIM capacitive stack at block 1 12 of the flow diagram. If the etching process shown in Figure 3A has been used, the cross-sectional view 300B of Figure 3B shows an embodiment of how a second RDL 304 may be formed over the 3D MIM capacitive stack 214 and the first RDL 206. The second RDL 304 forms a first contact 307 with the metal layer 210 of the first RDL 206 in a bottom 305 of the via 212. The second RDL 304 also makes a second contact 309 with the top electrode layer 222 of the 3D MIM capacitive stack 214. The second RDL 304 may be deposited using any suitable deposition process, for example an electroplating process. The second RDL 304 may comprise any suitable conductive material used to form a metal interconnect such as copper (Cu) or aluminum (Al), or the like. The dielectric spacer 302 passivates leakage current of the 3D MIM capacitive stack 214 and eliminates the need to have a third polymer dielectric layer formed over the substrate.
[0024] If the etching process shown in Figure 4A has been used, the cross-sectional view 400B of Figure 4B shows an embodiment of how a second RDL 406 may be formed over the 3D MIM capacitive stack 214 and the first RDL 206. The second RDL 406 forms a first electrical contact 407 with the metal layer 210 of the first RDL 206 at the bottom surface 402 of the via 212. The second RDL 406 also forms a second electrical contact 409 with the top electrode layer 222 of the 3D MIM capacitive stack 214 at the bottom surfaces 404 of the 3D MIM capacitive stack 214. The second RDL 406 may be deposited using any suitable deposition process, for example an electroplating process. The second RDL 406 may comprise any suitable conductive material used to form a metal interconnect such as copper (Cu) or aluminum (Al), or the like.
[0025] In both methods, the dielectric layer 216 is used to insulate the sidewalls 227 of the 3D MIM capacitive stack to reduce leakage currents. One embodiment uses dielectric spacers 302, while the other embodiment uses the dielectric layer 216 to insulate the 3D MIM capacitive stack 214. One advantage of the using the dielectric layer 216 to insulate the 3D MIM capacitor stack is that the etching process time is reduced and less etching damage is likely to occur to lower layers of the first RDL 206.
[0026] While the foregoing is directed to embodiments of the present principles, other and further embodiments of the principles may be devised without departing from the basic scope thereof.

中文:
[0002]半导体存储器器件总体包括用以存储大量信息的多个存储器单元。每个存储器单元包括用于存储电荷的电容器以及用于开启和关闭电容器的充电通道和放电通道的对应的场效应晶体管。随着半导体器件的尺寸持续缩小,允许半导体器件的每个部件所占据的面积减少。取决于电容器的尺寸和/或在管芯上的电容器的数量,电容器为在半导体管芯上可占据相当面积的一个部件。
[0003]在半导体存储器器件中所使用的电容器的一个示例为金属-绝缘体-金属(MIM)电容器。传统MIM电容器为二维(2D)的。2D MIM电容器具有两个面对面金属板,所述两个面对面金属板为平面的且基本上彼此平行且平行于基板。增加MIM电容器的电容的一种方法为增加金属板的尺寸。然而,增加金属板的尺寸将消耗更多的基板表面面积。三维(3D)MIM电容器允许相同的电容表面面积,但消耗较少的基板表面面积。然而,若在两个金属板之间发展漏电流,则3D MIM电容器可能失去性能。
[0004]因此,发明人已发展改进的3D MIM电容器和形成3D MIM电容器的方法。
[0005]在一些实施例中,一种处理基板的方法,包括以下步骤:提供具有第一聚合物介电层的基板;在第一聚合物介电层上形成第一重分配层(RDL),第一RDL包括第二聚合物介电层和至少一个开口,第二聚合物介电层具有嵌入第二聚合物介电层中的金属层,至少一个开口在第二聚合物介电层的顶部表面中用于暴露金属层的至少一部分;在第二聚合物介电层的顶部表面中的至少一个开口中,在第一RDL上构建3D MIM电容堆叠,3D MIM电容堆叠具有顶部电极、底部电极和插入顶部电极与底部电极之间的电容介电层,底部电极与金属层电接触;在3D MIM电容堆叠上以及第二聚合物介电层上沉积介电层;以及移除介电层的一部分,以在3D MIM电容堆叠的至少一个开口的底部处暴露顶部电极的至少一部分,且在第二聚合物介电层的至少一个开口的底部处暴露金属层的至少一部分。
[0006]在一些实施例中,一种处理基板的方法,包括以下步骤:提供具有第一聚合物介电层的基板;在第一聚合物介电层上形成第一重分配层(RDL),第一RDL包括第二聚合物介电层和至少一个开口,第二聚合物介电层具有嵌入第二聚合物介电层中的金属层,至少一个开口在第二聚合物介电层的顶部表面中以暴露金属层的至少一部分;在第二聚合物介电层的顶部表面中的至少一个开口中,在第一RDL上构建三维(3D)金属-绝缘体-金属(MIM)电容堆叠,3D MIM电容堆叠具有顶部电极、底部电极和插入顶部电极与底部电极之间的电容介电层,底部电极与金属层电接触;在3D MIM电容堆叠上以及第二聚合物介电层上沉积介电层;以及移除介电层的一部分,以在3D MIM电容堆叠的至少一个开口的底部处暴露顶部电极的至少一部分,且在第二聚合物介电层的至少一个开口的底部处暴露金属层的至少一部分。
[0007]在一些实施例中,一种基板包括:第一聚合物介电层;在第一聚合物介电层上的金属层;在第一聚合物介电层和金属层上的第二聚合物介电层,其中第二聚合物介电层包括经蚀刻至金属层的顶部表面的多个开口;形成在第二聚合物介电层上的三维(3D)金属-绝缘体-金属(MIM)电容堆叠,其中3D MIM电容堆叠的底部电极通过第二聚合物介电层中的至少一个开口与金属层电接触,3D MIM电容堆叠具有顶部电极、底部电极和插入顶部电极与底部电极之间的电容介电层;在3D MIM电容堆叠和第二聚合物介电层上的介电层,介电层具有在第二聚合物介电层之多个开口中的至少一个中的金属层的至少一个开口;形成在第二聚合物介电层上的第一触点,第一触点与金属层电连接;以及形成在3D MIM电容堆叠上的第二触点,第二触点电连接至3D MIM电容堆叠的顶部电极。
[0010]图2A至图2D根据本原理的一些实施例描绘处理基板的阶段。
[0011]图3A至图3B根据本原理的一些实施例描绘形成3D MIM电容器的实施例。
[0012]图4A至图4B根据本原理的一些实施例描绘形成3D MIM电容器的实施例。
[0013]为了促进理解,已尽可能地使用相同的附图标记代表附图中共用的相同元件。附图并非按照比例绘制,且为了清楚起见可简化。一个实施例的元件以及特征可有益地并入其他实施例中而无须进一步说明。
[0014]本文提供用于处理基板的方法。发明性方法有利地促进改进的3D MIM电容器以及形成3D MIM电容器的方法,所述3D MIM电容器具有降低的漏电流、整体系统的强化的系统性能(例如,较短连接路径)以及归因于较少所需层的较快的处理时间。
[0015]图1根据本原理的一些实施例描绘用于处理基板的方法100的流程图。尽管方法100显示在具有特定顺序的功能性框图中,但工艺并非必须以一个特定顺序执行。可重复一些工艺,且可重复工艺的一些群组。以相同的方式,一些工艺可在其他工艺等之前完成。
[0016]方法100参照图2至图4中描绘的结构而在流程图中说明。本原理的方法100可在能够执行蚀刻和沉积两者的单一工艺腔室中执行。此类适合的工艺腔室可为独立工艺腔室或为群集工具的部分。或者,此处所公开的发明性方法可在分开的腔室中执行,所述腔室也可为独立的或为群集工具的部分。
[0017]方法100通过例如在图2A中描绘的在基板202上提供或沉积第一聚合物介电层204而在流程图的框102处开始。基板202可为在半导体制造工艺中所使用的任何适合的基板材料。例如,基板200可以由硅、玻璃、陶瓷、环氧树脂模制化合物或介电质构建。第一聚合物介电层204可包括任何适合的聚合物介电材料,诸如聚酰亚胺、或聚苯并恶唑等等。第一聚合物介电层204旋转涂布在基板202上。第一聚合物介电层204也可使用任何适合的旋转涂布工艺、化学气相沉积(CVD)工艺或光刻工艺来沉积。在一些实施例中,第一聚合物介电层204也可为聚苯并恶唑(PBO)层、聚酰亚胺层、苯环丁烯(BCB)层、环氧树脂层或光敏感材料层。
[0018]在流程图的框104处,例如在图2A的剖面视图200A中所显示,在第一聚合物介电层204上形成第一重分配层(RDL)。第一RDL 206包括具有金属层210的第二聚合物介电层208和形成在第二聚合物介电层208中的多个开口213。金属层210可包括用以形成金属内部连接的任何适合的导电材料,诸如铜、或铝等。第一RDL 206为重新导向连接性的层,且提供在第一聚合物介电层204上。在一些实施例中,金属层210可使用电镀工艺或沉积工艺来形成,所述沉积工艺诸如是在半导体制造工艺中所使用的物理气相沉积(PVD)工艺。第二聚合物介电层208经图案化以形成多个开口213。开口213形成至金属层210的顶部表面211。在一些实施例中,图案化工艺可为任何适合的光刻和/或蚀刻工艺,用于在第二聚合物介电层208中形成开口。在一些实施例中,开口213可为特征,诸如通孔(例如,图2B中的通孔212)、沟槽等等。在一些实施例中所使用的RDL可为扇出或扇入。
[0019]接着在流程图的框106处,例如如图2B的剖面视图200B中所显示,在第一RDL 206上构建3D MIM电容堆叠。3D MIM电容堆叠214例如可通过Guan Huei See等人的在2017年4月13日公开为第2017-0104056号且名称为“半加性电镀金属布线中的三维金属-绝缘体-金属(MIM)电容器和电阻器的结构和制作方法(Structure And Method Of FabricatingThree-Dimensional(3D)Metal-Insulator-Metal(MIM)Capacitor And Resistor InSemi-Additive Plating Metal Wiring)”的美国专利申请第15/288,594号所提供的工艺而构建。图2C示出图2B的3D MIM电容堆叠214的端部分220的剖面视图200C。底部电极层226首先形成在第二聚合物介电层208上。底部电极层226具有导电特性,且通常以基于金属的材料形成。电容介电层224接着形成在底部电极层226上。电容介电层224的介电材料可取决于电容器特性而改变。在一些实施例中,电容介电层224为氮化物膜或高k介电材料,例如氧化铪(HfO2)、氮化硅(Si3N4)、氮化铝(AlN)、氧化钛(TiO2)或氧化钽(Ta2O5)。顶部电极层222接着形成在电容介电层224上。顶部电极层222可由与底部电极相同的材料形成,或由与底部电极不同的材料形成。顶部电极层222也具有导电特性。层222-226可使用任何适合的沉积工艺来沉积,例如物理气相沉积(PVD)工艺、化学气相沉积(CVD)工艺、原子层沉积(ALD)工艺等。
[0020]RDL常常用以形成至顶部电极层222和底部电极层226的导电连接。在3D MIM电容堆叠214的侧壁227处暴露层222-226的端部可导致漏电流,从而大幅降低3D MIM电容堆叠214的性能。先前工艺需要在3D MIM电容堆叠上形成额外的聚合物介电层,且接着在额外的聚合物介电层上形成额外的RDL,以减少漏电流。本原理的实施例无须额外的聚合物介电层和额外的RDL,而有利地节省处理时间和材料,降低成本,且通过降低漏电流以及连接长度而大幅强化3D MIM电容器的性能。然而,额外的可选聚合物介电层和额外的RDL并非排除在本原理的实施例之外。
[0021]取代了形成另一聚合物层,在流程图的框108处,介电层保形地沉积在3D MIM电容堆叠214上以及第二聚合物介电层208上。在图2D的剖面视图200D中示出一个实施例。可使用任何适合的沉积工艺来沉积介电层216,例如PVD工艺、CVD工艺、ALD工艺等。在一些实施例中,介电层216为基于硅的材料,诸如例如氮化硅或氧化硅。介电层216可具有大约5nm至大约100nm的厚度。在一些实施例中,介电层216保形地沉积,以便覆盖3D MIM电容堆叠214的开口217或第二聚合物介电层208中的通孔212的底部和侧壁。
[0022]接着在流程图的框110处,在介电层216上执行蚀刻工艺。蚀刻工艺可包括但不限于在反应离子蚀刻腔室中的干式蚀刻。在示例中,介电层216在本原理的不同实施例中可以以不同方式蚀刻。在图3A的剖面视图300A中示出的一个实施例中,从表面蚀刻介电层216直到在3D MIM电容堆叠214的侧壁227处留下介电间隔物(dielectric spacer)302。在图4A的剖面视图400A中示出的另一实施例中,从通孔212的底部表面402且从3D MIM电容堆叠214的底部表面404蚀刻介电层216。
[0023]在蚀刻介电层之后,在流程图的框112处,在基板上形成第二RDL而不具有在介电层和3D MIM电容堆叠上的聚合物介电层。若已使用图3A中所示的蚀刻工艺,则图3B的剖面视图300B显示如何可在3D MIM电容堆叠214和第一RDL 206上形成第二RDL 304的实施例。第二RDL 304在通孔212的底部305中与第一RDL 206的金属层210形成第一触点307。第二RDL304还与3D MIM电容堆叠214的顶部电极层222形成第二触点309。第二RDL304可使用任何适合的沉积工艺来沉积,例如电镀工艺。第二RDL 304可包括用以形成金属互连的任何适合的导电材料,诸如铜(Cu)或铝(A1)等。介电间隔物302钝化3D MIM电容堆叠214的漏电流,且消除在基板上形成第三聚合物介电层的需要。
[0024]若已使用图4A中所示的蚀刻处理,则图4B的剖面视图400B显示如何可在3D MIM电容堆叠214和第一RDL 206上形成第二RDL 406的实施例。第二RDL 406在通孔212的底部表面402处与第一RDL 206的金属层210形成第一电触点407。第二RDL 406也在3D MIM电容堆叠214的底部表面404处与3D MIM电容堆叠214的顶部电极层222形成第二电触点409。第二RDL 406可使用任何适合的沉积工艺来沉积,例如电镀工艺。第二RDL 406可包括用以形成金属互连的任何适合的导电材料,诸如铜(Cu)或铝(A1)等。
[0025]在两个方法中,介电层216用以隔绝3D MIM电容堆叠的侧壁227,以减少漏电流。一个实施例使用介电间隔物302,而另一实施例使用介电层216来隔绝3D MIM电容堆叠214。使用介电层216来隔绝3D MIM电容器堆叠的一个优点为减少蚀刻工艺时间,且对第一RDL 206的较低层可能发生较少的蚀刻损伤。
[0026]尽管上述内容针对本原理的实施例,但可在不背离本原理基本范围的情况下想到本原理的其他和进一步实施例。