English:
[0001] High speed digital logic circuits include transistors formed with thin gate oxide layers designed for high speed operation at low supply voltages. Many integrated circuits include digital logic circuits as well as interface circuitry designed to operate at higher voltages. Power BiCMOS circuit fabrication processes combine bipolar and complementary metal oxide semiconductor (CMOS) technologies to support low voltage, high speed digital logic circuits as well as higher voltage transistors to implement digital and analog input/output (IO) interface circuits, power management switches or the like. Some approaches use laterally diffused MOS (LDMOS) or drain-extended MOS (DeMOS) transistors with drain structures capable of operating at higher voltages as compared to conventional symmetric MOS transistors. LDMOS transistors include a lightly doped lateral diffused drain region between the heavily doped drain contact and the transistor channel to conduct lateral current and form a depletion region to create a voltage drop between the drain contact and the transistor gate. The reduced drain voltage at the channel allows use of a thin gate oxide and a low gate voltage transistor can be used as a switch for high drain voltage applications. However, extending the lateral drift region to accommodate higher voltages increases the triode region on-state resistance RDSON and increases the device size, device cost and specific resistance Rsp. The specific resistance Rsp is the drain-to-source on-state resistance of the transistor in a given amount of area, and can be expressed as Rsp = RDSON* Area. Also, the factor Q for transistor switching loss is related to the device input, output and reverse transfer capacitances, and low gate charge Qg, related to gate capacitance, and switching loss are important for high frequency operation. Split or stepped poly gates can be used to minimize main gate area for a reduced Qg, but this is only beneficial for a relatively high voltage rated device or a relatively long drift length. This approach also increases device size and cost and generally provides no significant device Rsp reduction. Moreover, addition of split gate structures over an extended drain increases the output or drain capacitance. Conventional LDMOS designs do not provide a complete solution for short channel devices with small pitch size for high voltage applications to reduce the specific resistance and still support efficient high frequency operation with low
[0003] FIG. 1 shows a partial sectional side elevation view of an integrated circuit including an LDMOS transistor with a trapezoidal JFET region.
[0004] FIG. 2 is a flow diagram showing a method for making an LDMOS transistor.
[0005] FIGS. 3-9 are partial sectional side elevation views of the integrated circuit at different stages of fabrication to provide the LDMOS transistor of FIG. 1.
[0006] FIG. 10 is a flow diagram showing an alternate method for making an LDMOS transistor.
[0007] FIG. 1 shows a partial view of an integrated circuit (IC) 100 with an LDMOS transistor 101 fabricated from a semiconductor substrate 102. In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. The illustrated example is an n-channel LDMOS with a trapezoidal JFET region. Other implementations are possible within the scope of this description, including p-channel LDMOS examples using oppositely doped structures and regions. In one example, the substrate 102 is a p-doped silicon substrate or wafer, with various buried layers 104, 106 and a drift region 110 formed therein. In another possible implementation, the substrate includes one or more epitaxial silicon layers (not shown) formed on a top surface, with one or more of the buried layers 102, 104, 106 and the drift region 110 formed in epitaxial layers of the substrate.
[0008] The n-channel LDMOS 101 in FIG. 1 includes an n-type buried layer (NBL) region 104 implanted in the substrate 102 using n-type dopants (e.g., phosphorus and/or As). A p-type buried layer (PBL) region 106 is formed by implanting p-type dopants (e.g., Boron) above the NBL region 104 in the substrate 102. The drift region 110 extends above the PBL region 106 in the substrate 102. The drift region 110 includes a first n-drift region portion 112 (labeled NDl in the drawing) that extends above the PBL region 106. The drift region 110 also includes a gap drift region 113 (labeled GD) including low or lightly doped n-type impurities (e.g., phosphorus) that provide a lightly doped n-type buffer region above the first n-drift region portion 112. In one example, the substrate 102 is initially p-type silicon including boron or other p-type dopants, and the gap drift region portion 113 is counter doped with phosphorus or other n-type dopants to provide the lightly doped n-type region portion 113. In some examples, the light n-type doping of the gap drift region portion 113 is created by diffused tail areas from the n-type dopants implanted into the n-drift region portions 112 and/or 114. The gap drift region portion 113 in one example has a dopant concentration that is less than the n-type dopant concentrations of the first and second n-drift region portions 112 and 114. The drift region 110 further includes a second n-drift region portion 114 (labeled ND2) that extends above the gap drift region 113 to the upper or top surface of the substrate 102.
[0009] The LDMOS transistor example 101 in FIG. 1 also includes a gate structure with a gate dielectric layer 130 formed over a top or upper surface of the substrate 102, a gate electrode structure 132 on the gate dielectric layer 130, and lateral sidewall spacers 134. A p-type body region 108 is implanted in the substrate 102, such as using boron or other p-type dopants. The p-body region 108 provides a channel region under a portion of the gate dielectric layer 130 with a channel width shown in the upper surface of p-body as a first lateral distance D 1. A heavily doped n-type drain region 138 (labeled N+) is formed in the upper surface of the substrate 102. The drain region 138 is laterally spaced from a first side of the gate structure, and a heavily doped n-type source region 136 is adjacent the channel region in the substrate 102 proximate and partially under the second side of the gate structure. The illustrated example also includes a P+ implanted region 140 adjacent to and laterally outward of the source region 136.
[0010] An isolation structure 116 (labeled STI in FIG. 1) extends partially under the gate structure and includes oxide material to define an extended drain structure. In one example, the isolation structure 116 is an oxide formed in a shallow trench using shallow trench isolation (STI) fabrication techniques. In another example, local oxidation of silicon (LOCOS) or other suitable isolation processing techniques and materials are used to form the isolation structure 116. A first end of the isolation structure 116 contacts the drain region 138, and a second end extends under the gate dielectric layer 130. The isolation structure 116 extends downward through the second highly doped region portion 1 14 and into the gap drift region portion 113. The drift region structure 110 provides a ballast drift portion of the gap drift region portion 113 between the isolation structure 116 and the PBL region 106.
[0011] The illustrated IC 100 further includes a second isolation structure (STI) 118 disposed laterally outward of the drain region 138, which also extends through the second highly doped region portion 114 and into the gap drift region portion 113. The second isolation structure 118 is adjacent a deep trench isolation structure 120, that includes implanted N+ doped sidewall structures 122 that extend from the top surface of the substrate 102 through the drift region 110 and the PBL region 106, and into the NBL region 104. In some examples, the deep trench isolation structure 120 is formed as a ring structure to surround the LDMOS transistor 101. The sidewall structures 122 are formed on opposite lateral sides of field oxide structures 124 that extend into the p substrate 102. The field oxide structures 124 laterally surround a P+ silicon structure 126 that extends from the upper surface into the p substrate 102 below the NBL region 104.
[0012] The IC 100 further includes contact structures (not shown) to provide electrical connection to one or more features of the transistor 101, along with a metallization structure (not shown) covering the transistor 101 and providing external electrical interconnection to the transistor source, drain and gate terminals, respectively designated S, D and G in FIG. 1. The metallization structure can include a pre-metal dielectric (PMD) material formed over the illustrated structure, with contact structures formed therein to provide electrical interconnection access for further upper metallization layers (not shown).
[0013] In some examples, the drift region 110 further includes a p-drift region portion 111 (labeled PD) between the PBL region 106 and the first n-drift region portion 112. When included, the p-drift region portion 111 controls the electric field distribution between the ballast drift portion of the gap drift region portion 113 under the isolation structure 116 and the PBL region 106. In some implementations, the dopant concentration of the p-drift region portion 111 can be different for LDMOS transistors designed to operate at different drain voltages.
[0014] In some examples, the illustrated structure in FIG. 1 can be replicated (e.g., to the left in FIG. 1) in symmetrical fashion about a central source structure 136 and a single p-body region 108, with another gate structure 130, 132, 134 and further laterally outward isolation and drain structures 116 and 138, where the parallel gate structures are electrically interconnected to one another, and the parallel drain structures 138 are electrically interconnected to one another, with the symmetrical structure operating as a single LDMOS transistor 101. Other symmetrical implementations are possible, such as with symmetrical parallel sets of gate structures and source structures on both lateral sides of a single central drain structure 138. Moreover, as described above, although the illustrated LDMOS transistor example 101 in FIG. 1 is an n-channel device, p-channel LDMOS transistors are possible having oppositely doped structures and regions in other implementations of the techniques described herein.
[0016] The tapered side of the p-body region 108 and the second end of the isolation structure 116 define a generally trapezoidal JFET region 150 with a wide top and a narrow bottom gate designated BG in FIG. 1. The trapezoidal JFET region 150 includes a wide top in the second n-drift region portion 114 below the gate dielectric layer 130. The narrow bottom in the gap drift region portion 113 provides a voltage controlled bottom gate BG to control the electric field distribution between the JFET region 150 and a ballast drift portion of the first n-drift region portion 112 under the isolation structure 116. The JFET region 150 provides controlled depletion in the narrow gap between the p-body region 106 and the lower STI structure corner for controlled pinch-off during the LDMOS off state to prevent excessive voltage at the gate dielectric layer 130. This facilitates use of a single thin gate dielectric layer 130 for both low voltage transistors (not shown) and the LDMOS transistor 101 in the IC 100.
[0017] Referring to FIGS. 2 and 3-9, FIG. 2 shows a method 200 to fabricate an n-channel LDMOS transistor, and FIGS. 3-9 illustrate processing of the integrated circuit 100 at various intermediate stages of fabrication to produce the LDMOS transistor of FIG. 1 according to the method 200. In other examples, P-channel LDMOS transistors can be fabricated according to the method 200 using opposite dopant implantation steps and materials. A starting substrate is provided at 202. In one example, a p-doped silicon wafer substrate is provided at 202, such as the substrate 102 in FIG. 3. In another example, a silicon on insulator (SOI) starting wafer is used. A substrate of a different semiconductor material can be provided at 202 in other implementations. In one example, an epitaxial layer (not shown) is formed on the substrate 102 using an epitaxial growth deposition process at 204, and the LDMOS transistor 101 is formed in the epitaxial layer of the substrate 102. In other implementations, the epitaxial layer and the processing at 204 are omitted. At 206, n-type dopants (e.g., phosphorus) are implanted into the substrate 102 to form BL region in the substrate 102 (e.g., BL region 104 in FIG. 3). A PBL region (e.g., region 106) is formed at 208 by implanting p-type dopants (e.g., boron) into the substrate 102 above the NBL region 104.
[0018] A drift region 110 is formed above the PBL region 106 at 110 in FIG. 2, as shown in FIGS. 3-5. In one example, a p-drift region portion (111 in FIG. 3) is formed above the PBL region 106 at 211 in FIG. 2 by implanting p-type dopants into the substrate 102 between a first depth 302 (e.g., 1.6 μπι) and a second depth 304 (e.g., 1.2 μπι) using an implantation process 300 in FIG. 3. In other implementations, the implant at 211 can be omitted. As shown in FIG. 4, n-type dopants are implanted into the substrate 102 at 212 in FIG. 2 using an implantation process 400 in FIG. 4 to form the first n-drift region portion 112 above the PBL region 106 (and above any included p-drift region 111). The implantation at 212 forms the first (e.g., deep) n-drift region portion 112 between a depth 402 (e.g., 0.5 μπι) and a second depth 404 (e.g., 1.2 μπι) shown in FIG. 4. In some examples, the second depth 404 in FIG. 4 is the same as the second depth 304 in FIG. 3, although not a strict requirement of all possible implementations. In the example of FIG. 4, the lower depth 404 of the first n-drift region portion 112 extends to the p-drift region portion 111, and is above and spaced from the PBL region 106. In other implementations, the first n-drift region portion 112 is implanted to the depth of the PBL region 106, such as where no p-drift region portion 111 is implanted.
[0019] As further shown in FIG. 5, an implantation process 500 is used at 213 in FIG. 2 to implant n-type dopants into the substrate 102 to form the second (e.g., shallow) n-drift region portion 114 to a depth 502 (e.g., zero depth at the upper surface of the substrate 102) and a second depth 504 (e.g., 0.25 μπι). The implantation at 213 forms the region portion 114 above and spaced from the first n-drift region portion 112 and leaves or defines a low doped gap drift region portion 113 between the n-drift region portions 112 and 114 (e.g., between the depths 502 and 504 in FIG. 5). In one example, the portion 113 is lightly n-doped due to diffused tail areas from the more highly doped n-drift region portions 112 and 114.
[0020] The illustrated method 200 in one example includes forming the deep trench isolation structure 120 at 214 in FIG. 2 using a process 600 in FIG. 6. Any suitable deep trench processing techniques can be used. In one example, a trench is etched through the drift region 110, the PBL region 106 and the BL region 104 and into the portion of the p substrate 102. An N+ implantation is performed to dope the trench sidewall structures 122 to a depth into the NBL region 104, and the sidewalls are oxidized to form the field oxide structures 124. A silicon deposition process with in-situ P+ doping to form the structure 126 between the oxide structures 124, leaving the deep trench isolation structure 120 shown in FIG. 6.
[0021] The process 200 continues at 216 in FIG. 2 with a shallow trench isolation process 700 in FIG. 7 to form the isolation structure 116 (labeled DRIFT STI in FIG. 7) that extends downward through the second n-drift region portion 114 and into the gap drift region portion 113. The isolation structure 116 includes a first end proximate a prospective drain region, and a second end under a prospective gate region. The second isolation structure 118 is formed laterally outward of the prospective drain region using the process 700 at 216. In one example, trenches are etched and filled with oxide to form the structures 116 and 118. Other processes can be used, such as LOCOS processing at 216 to form the isolation structures 116 and 118. In one example, the STI isolation structure 116 in FIG. 1 extends downward into the substrate structure to a depth of approximately 0.35 μπι, and the isolation structure 116 may, but need not, have an upper surface that is generally coplanar with the upper surface of the substrate 102.
[0022] At 218 in FIG. 2, a mask 802 is formed and p-type dopants are implanted into the substrate 102 using an implant process 800 as shown in FIG. 8. The masked implant at 218 forms the p-body region 108 that extends through the drift region 110 and into the PBL region 106, and provides the narrow channel region at the top or upper surface of the substrate 102. In one example, the implantation is performed at 218 using an angled implantation process 800 to preferentially diffuse implanted p-type dopants (e.g., boron) laterally toward the isolation structure (i.e., to the right in FIG. 8) to create a tapered side of the p-body 108. A short channel is formed in the narrow upper surface of the p-body when a gate dielectric layer over the area. This creates a generally trapezoidal JFET region form that is wide on the top and narrower on the bottom. The resulting tapered side of the implanted p-body region 108 is laterally spaced from the second end of the isolation structure 116 by the larger lateral channel width distance Dl at the top surface of the substrate 102, and is laterally spaced from the isolation structure 116 by the smaller distance D2 in the gap drift region portion 113.
[0023] At 214 in FIG. 2, the gate structure 130, 132, 134 is formed using any suitable gate fabrication processing 900 as shown in FIG. 9. The gate dielectric layer 130 extends over the channel region, trapezoidal JFET and a portion of the isolation structure 116 to form a short channel compact gate configuration to control the prospective LDMOS transistor. The N+ source and drain regions 136 and 138 and any included P+ region 140 are formed at 222 using suitable implantation processing to provide the n-channel LDMOS structure 101 as described above in connection with FIG. 1. The processing at 222 in one example includes implanting n-type dopants into the substrate 102 to form the n-type source region 136 adjacent the channel region in the p-body region 108 and to form the n-type drain region 138 adjacent the first end of the isolation structure 116 in the second n-drift region portion 114. Further processing is performed at 224 to forms contacts, metallization structures and to complete other back end processes to finish the integrated circuit 100.
[0024] Referring also to FIG. 10, another non-limiting alternate implementation of the method 200 is illustrated. The illustrated process 200 of FIG. 2 involves forming the first and second n-drift region portions 112, 114 before forming the isolation structure 116. In the alternate implementation of FIG. 10, the first and second n-drift region portions 112, 114 are formed after forming the isolation structure 116. In this example, the processing at 202-208 is as described above in connection with FIG. 2, including forming an BL region 104 at 206 and forming a PBL region 106 at 208. A p-drift region portion 111 is optionally performed at 211, and the first n-drift region portion 112 is formed at 212. In the example of FIG. 10, the trench isolation structures are formed at 214 and STI or other isolation structures are formed at 216 as described above. At 210 in FIG. 10, the p-drift region portion 111 is optionally formed at 211, and the first n-drift region portion 112 and the shallow second n-drift region portion 114 are formed at 212 and 213 by implantation after the isolation structures are formed at 216. At 218-224, the p-body region 108 is formed, along with the gate structures, source/drain regions and final contact and metallization structures as described above.
[0025] Some described examples include short channel LDMOS transistors 101 with a trapezoid JFET region 150, a bottom gate BG, and a ballast drift region including the first n-type drift region portion 112. The LDMOS transistor 101 implements a trapezoidal JFET region 150 with a bottom gate BG and ballast drift concepts with the benefits of a short channel design and low on-state resistance and low switching loss (e.g., low RDSON*Q). The described LDMOS transistors 101 provide an improved solution compared with split or stepped gate approaches, while facilitating use of a single thin gate dielectric layer for integrated circuits 100 that include both low voltage CMOS logic transistors and LDMOS devices for higher voltage operation. In this regard, the techniques described herein are useful to provide short channel LDMOS transistor 101 at a small pitch size for high voltage applications. Also, the drift layer structure 110 and tapered p-body region 108 can be fabricated with a minimal number of implant masks and processing steps to provide a solution to support low mask count and low Rsp/R*Q integrated LDMOS suitable for power switches in high-speed applications. For example, the LDMOS transistor 101 can be used as a high or low side switch in a buck or boost DC-DC converter operated at high switching frequencies, where the extended drain reduces the output capacitance and gate capacitance to facilitate high speed, low switching loss operation while allowing relatively high drain voltages.
[0026] In some example implementations, the LDMOS structure 101 includes three implanted regions 104, 106 and 110 which can be formed via stacked blanket implants without extra masks to create a short channel region under a portion of the gate dielectric layer 130, the trapezoidal JFET region 150 (FIG. 1), and an enhanced ballast drift region in the first n-type drift region portion 112 beneath the STI isolation structure 116 that is fabricated in some implementations by body chain implants with one body mask layer. The LDMOS example 101 in FIG. 1 is isolated to the substrate 102 by a deep trench isolation ring structure 120 at a deep trench (DT) mask layer. In some fabrication process implementations, the LDMOS fabrication is compatible with existing process flows, wherein heavily doped n-type buried blanket implants are separated from the other two blanket implantation processing before an optional in-line epitaxial deposition process (e.g., prior to depositing the epitaxial silicon at 204 in FIGS. 2 and 10 described above). Various implementations are also compatible with fabrication of other devices in an integrated circuit 100, such as where the n-type drift chain implants or the n-type drift working with p-type buried chain implants (e.g., 206, 208 and/or 210 in FIGS. 2 and 10) can be processed by using one extra drift mask to mask other (e.g., non-LDMOS or non-LDMOS drain drift) regions. In one example, the implants at 210 are done with a separate mask that convers a prospective p-body region and non-LDMOS regions of the IC 100.
[0027] In the example of FIG. 1, the drift region 110 includes two n-type and one p-type chain implants in which the relatively high doped drift-shallow n-type region portion 114 can be implanted only in the device moat (non-STI) area (e.g., through subsequent implantation following formation of the isolation structure 116, as per FIG. 10 described above). The resulting structure provides reduced JFET resistance and compensating interface charge for improved device hot carrier performance. The first (e.g., deeper) n-type drift region portion 112 works with the PBL region 106 and the bottom gate BG to provide a high doped ballast region underneath drift STI to enhance charge balance and device reduced surface field (RESURF) to support high voltage operation at a small pitch dimensions to reduce Rsp and output capacitance of the LDMOS drain. The PBL region 106 enhances charge balance for the N doped, low resistance lateral current flow path in the region 112. The gap region portion 113 provides a buffer located close to the bottom and low voltage sidewall of the STI isolation structure 116. The buffer is formed by overlap of the tail areas of the first and second (deep and shallow) n-drift region portions 112 and 114 and prevents early surface electric field (E-field) accumulation due to the highly doped narrow ballast at high drain voltage levels. The buffer doping profile can be adjusted in various examples by an extra blanket implant or such adjusted doping can be provided through existing drift chain implants without an extra mask.
[0028] The tapered JFET region 150 is shaped as an inverted trapezoidal area with a wide-top to release the E-field proximate the surface to protect the potentially thin gate dielectric layer 130 used in the LDMOS 101 and in other lower voltage devices in the IC 100. The trapezoidal JFET region 150 provides a narrow bottom with a width D2, and operates as a voltage-control bottom gate BG to adjust the E-field distribution between ballast drift and the JFET 150 at target voltages, and the design can be tailored for a given target operating voltage level. In operation, the inverted trapezoidal JFET 150 and bottom gate BG reduce surface E-field even at a narrow high-doped ballast drift at high drain voltage levels to facilitate low on-state resistance in the drift region at a small lateral distance or pitch (e.g., low specific resistance Rsp). The LDMOS 101 implements a short channel region for reduced channel resistance and low gate capacitance while mitigating surface short channel punch-through. Also, the short channel length reduces the gate capacitance and thus reduces switching loss related to the gate charge Qg, which is particularly advantageous at high operating frequencies or switching speeds. The design facilitates trade-off between the on state and off state performance, and allows limited JFET resistance only in the shallow/narrow bottom gate area BG, in combination with improved device hot carrier performance and reduced overall JFET resistance due to the released surface E-field, compensated interface, and a high doped drift-shallow region.
[0029] The voltage-controlled bottom gate BG adjusts or sets the E-field distribution between ballast drift region and the JFET region 150 at target voltages and the sizing of the bottom gate BG provides controlled depletion and region pitch-off In a fully on condition, the JFET bottom gate operates with minimum deleted area at high-gate/low-drain voltages. In a quasi-off condition of the LDMOS 101, a maximum area is depleted at low-gate/high-drain voltages, and the JFET surface peak E-field (E-peak) is synchronized with a targeted design maximum operating voltage.
[0030] The described short channel LDMOS transistors 101 with a trapezoidal JFET region 150, bottom gate BG and ballast drift region to provide low R*Q and associated benefits for power switching and other applications. In other examples, the trapezoid JFET, bottom gate and ballast drift in combination with a deep nwell and a deep trench isolation structure 120 can be used, and the PBL region 106 and/or the NBL region 104 can be omitted for example, to further reduce the number of masks and process costs. In this regard, the PBL 106 and the NBL 104 can be implemented with blanket implantations without extra mask layers. In other examples, a short channel LDMOS 101 can be implemented with trapezoidal JFET region 150, bottom gate BG in combination and ballast drift, working with low cost CMOS transistors (e.g., shared with LDMOS layers) in a single IC 100, and such designs can omit one more CMOS snwell layer for further mask count reduction. Moreover, some examples employ dedicated body chain implants as a base to link-up the device short channel, bottom gate and enhanced ballast drift together for better device performance. In one example, the p-body 108 can be formed (e.g., at 218 in FIGS. 2 and 10 described above) using chain p-type implants, including a boron (B) implant at implant energy 300KeV to 2MeV, related to a particular targeted rated platform voltage, with an implant dose 9E13 to 2E12. In some examples, the p-body region is implanted at an angle 0-9 degrees to facilitate linking the device shallow-body, bottom gate and blanket p-type buried layer region 106.
[0031] In further examples, the LDMOS 101 is fabricated with a trapezoidal JFET region 150 made by dedicated shallow body co-implants stacked on the top of the p-body up/down body chain implants worked with side-wall of the STI isolation structure 116. In one example, the device short channel is formed by surface lateral diffusion between Boron and As of the shallow body co-implants for a targeted small gate channel length Lg and low gate charge Qg for low switching loss. A retrograded shallow body is made in one example by p-type Boron and n-type As co-implants, including a Boron (B) implant at implant energy 60KeV to 260KeV, and implant dose 5E14 to 1E13, with an implant angle of 7-35°, and an Arsenic (As) implant at an energy of 25KeV to 160KeV, implant dose 1E15 to 3E13, and an implant angle of 0-9°. The bottom gate area BG formed near the bottom corner of the STI isolation structure 116 in one example is generally aligned to the outermost extent of the p-body region 108/drift region junction to control the depletion region pitch-off at target control voltage levels. The spacing at the lowest doped area of the bottom gate BG from the silicon substrate upper surface in one example is from 0.25 um to 0.6 um, and the width D2 of the bottom gate BG is controlled from the space between the STI isolation structure sidewall to the gate poly edge on the source side in one example is from 0.35 um to 1.5 um, to target different rated device voltages.
[0032] In some examples using the two n-type drift region portions 112 and 114, and the p-type drift region portion 111, the drift region 110 is formed using n-type/p-type chain implants, including an n-type Phosphorus (P) implant (e.g., at 212 and 213 in FIGS. 2 and 10) at an implant energy of 160KeV to 2MeV with an implant dose 2E13 to 1E12 and an implant angle of 0-9°, in combination with a p-type Boron (B) implant (e.g., at 211 in FIGS. 2 and 10) at an implant energy of 600KeV to 2MeV with an implant dose 2E13 to 1E12 and implant angle 0 degree to 9 degree for enhanced charge balance with the built in small ballast region underneath the drift STI isolation structure 116 to facilitate low device Rsp and low output capacitance Coss. In some examples, the shallow n-type second drift region portion 114 is implanted on the top of the first n-type drift region portion 112 (e.g., with no gap region 113) after the STI isolation structure etch, and the region portion 114 is only located in non-STI areas. In this example, the implantation of the second drift region portion 114 is done by an n-type As or phosphorus or As with phosphorus implants at an implant energy of 25KeV to 500KeV with an total implant dose of 2E13 to 1E12, and an implant angle of 0-9 degrees to facilitate reduced JFET resistance and compensating interface charge with an improved device hot carrier performance. Extra lightly doped implant, p-type or n-type, are added in some examples in the drift chain implants to adjust the bottom gate (buffer area) voltage sensitivity to gate/drain voltage, in which case the n-type/p-type implant is controlled at an implant dose of 2el 1 to 2el2 with an implant projected depth range of 0.25 um to 0.6 um.
[0033] In some examples, the short channel LDMOS 111 is fabricated inside an isolation boundary, such as the illustrated combination of the NBL region 104, the PBL region 106, and the ring shaped deep trench isolation structure 120. In some examples, the isolation features include a heavily doped, isolated NBL tub region 104 implanted with thickness from 3 um to 10 um after any in-line epitaxial deposition processing, in combination with a surrounding deep N-type well structure and/or the illustrated deep trench N portions 122 of the ring shaped deep trench isolation structure 120. An adjusted p-type blanked buried implant can be added in some examples, stacked with any included implantation for the p-type drift region portion 111, as needed, to reduce platform parasitic BJT concerns, for instance, at an implant energy of 800KeV to 2.5MeV with an implant dose of 2E13 to 5E11 and an implant angle of 0-9 degrees. In some examples, the NBL region 104 and the PBL region 106 work with the deep trench structure 120 or any included deep nwell (not shown) to isolate the LDMOS transistor 101 to the substrate 102 for device high-side and isolated applications.
[0034] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

中文:
[0001]高速数字逻辑电路包括形成有薄栅极氧化物层的晶体管,被设计用于在低电源电压下高速工作。许多集成电路包括数字逻辑电路以及被设计成在较高电压下工作的接口电路。功率BiCMOS电路制造过程结合双极和互补金属氧化物半导体(CMOS)技术,以支持低电压、高速数字逻辑电路以及较高电压晶体管,从而实现数字和模拟输入/输出(IO)接口电路、功率管理开关等。一些方法使用横向扩散MOS(LDMOS)或漏极扩展MOS(DeMOS)晶体管,其漏极结构与常规的对称MOS晶体管相比,能够在较高的电压下工作。LDMOS晶体管包括在重掺杂漏极触点与晶体管沟道之间的轻掺杂横向扩散漏极区,以传导横向电流并形成耗尽区,从而在漏极触点与晶体管栅极之间产生电压降。在沟道处降低的漏极电压允许使用薄栅极氧化物,并且低栅极电压晶体管可以用作高漏极电压应用的开关。然而,扩展横向漂移区以适应较高的电压会增加三极管区导通状态电阻RDSON,并增加器件尺寸、器件成本和比电阻Rsp。比电阻Rsp是给定面积内晶体管的漏-源导通状态电阻,并且可以表示为Rsp=RDSON*面积。此外,晶体管开关损耗的因子Q与器件输入、输出和反向传输电容有关,并且与栅极电容有关的低栅极电荷Qg和开关损耗对于高频工作很重要。分裂或阶梯式多晶硅栅极可以用于最小化主栅极面积用于减少的Qg,但这仅有利于较高的额定电压器件或较长的漂移长度。这种方法还会增加器件尺寸和成本,并且通常提供不显著的器件Rsp降低。此外,在扩展的漏极上方添加分裂栅极结构会增加输出或漏极电容。常规的LDMOS设计没有为高电压应用中的具有小间距尺寸的短沟道器件提供完整的解决方案以减小比电阻,且仍支持具有低RDSON和Q的高效高频工作。
[0003]图1示出包括具有梯形JFET区的LDMOS晶体管的集成电路的局部剖面侧视图。
[0004]图2是示出制造LDMOS晶体管的方法的流程图。
[0005]图3-图9是在用于提供图1的LDMOS晶体管的不同制造阶段下集成电路的局部剖面侧视图。
[0006]图10是示出制造LDMOS晶体管的替代方法的流程图。
[0007]图1示出集成电路(IC)100的局部视图,集成电路(IC)100具有用半导体衬底102制造的LDMOS晶体管101。在附图中,相同的附图标记始终指代相同的元件,并且各种特征不一定按比例绘制。所示的示例是具有梯形JFET区的n沟道LDMOS。在本说明书的范围内,其它实施方式也是可能的,包括使用相反掺杂的结构和区域的p沟道LDMOS示例。在一个示例中,衬底102是p掺杂硅衬底或晶片,其中形成有各种掩埋层104、106和漂移区110。在另一种可能的实施方式中,衬底包括形成在顶表面上的一个或多个外延硅层(未示出),掩埋层102、104、106和漂移区110中的一个或多个形成在衬底的外延层中。
[0008]图1中的n沟道LDMOS 101包括使用n型掺杂剂(例如,磷和/或砷)注入衬底102中的n型掩埋层(NBL)区104。通过在衬底102中的NBL区104上方注入p型掺杂剂(例如,硼),形成p型掩埋层(PBL)区106。漂移区110在衬底102中的PBL区106上方延伸。漂移区110包括在PBL区106上方延伸的第一n漂移区部分112(在图中标记为ND1)。漂移区110还包括间隙漂移区113(标记为GD),间隙漂移区113包括在第一n漂移区部分112上方提供轻掺杂n型缓冲区的低或轻掺杂的n型杂质(例如,磷)。在一个示例中,衬底102最初是包括硼或其它p型掺杂剂的p型硅,并且用磷或其它n型掺杂剂对间隙漂移区部分113进行反掺杂,以提供轻掺杂n型区部分113。在一些示例中,间隙漂移区部分113的轻n型掺杂是由注入到n漂移区部分112和/或114中的n型掺杂剂的扩散尾部区域产生的。在一个示例中,间隙漂移区部分113的掺杂浓度小于第一n漂移区部分112和第二n漂移区部分114的n型掺杂浓度。漂移区110还包括第二n漂移区部分114(标记为ND2),第二n漂移区部分114在间隙漂移区113上方延伸到衬底102的上表面或顶表面。
[0009]图1中的LDMOS晶体管示例101还包括栅极结构,该栅极结构具有在衬底102的顶表面或上表面上形成的栅极电介质层130、在栅极电介质层130上的栅极电极结构132以及横向侧壁间隔物134。p型体区108被注入衬底102中,例如使用硼或其它p型掺杂剂。p体区108在栅极电介质层130的一部分下方提供沟道区,其沟道宽度在p体的上表面中示出为第一横向距离D1。在衬底102的上表面中形成重掺杂n型漏极区138(标记为N+)。漏极区138与栅极结构的第一侧横向间隔开,重掺杂n型源极区136与衬底102中的沟道区相邻,该沟道区靠近栅极结构的第二侧并部分地位于其下方。所示的示例还包括与源极区136相邻并在其横向外侧的P+注入区140。
[0010]隔离结构116(在图1中标记为STI)部分地在栅极结构下方延伸,并且包括氧化物材料以限定延伸的漏极结构。在一个示例中,隔离结构116是使用浅沟槽隔离(STI)制造技术在浅沟槽中形成的氧化物。在另一个示例中,使用硅的局部氧化(LOCOS)或其它合适的隔离处理技术和材料来形成隔离结构116。隔离结构116的第一端接触漏极区138,第二端在栅极电介质层130下方延伸。隔离结构116向下延伸穿过第二高掺杂区部分114并进入间隙漂移区部分113。漂移区结构110在隔离结构116与PBL区106之间提供间隙漂移区部分113的镇流漂移部分。
[0011]所示的IC 100还包括设置在漏极区138的横向外侧的第二隔离结构(STI)118,该第二隔离结构118也延伸穿过第二高掺杂区部分114并进入间隙漂移区部分113。第二隔离结构118与深沟槽隔离结构120相邻,深沟槽隔离结构120包括注入的N+掺杂侧壁结构122,其从衬底102的顶表面延伸穿过漂移区110和PBL区106并进入NBL区104。在一些示例中,深沟槽隔离结构120形成为环形结构,以包围LDMOS晶体管101。侧壁结构122形成在延伸到p衬底102中的场氧化物结构124的相对横向侧上。场氧化物结构124横向地包围从上表面延伸到NBL区104下方的p衬底102中的P+硅结构126。
[0012]IC100还包括触点结构(未示出)以提供与晶体管101的一个或多个特征件的电连接,以及金属化结构(未示出),从而覆盖晶体管101并提供与晶体管源极、漏极和栅极端子(在图1中分别表示为S、D和G)的外部电互连。金属化结构可以包括形成在所示结构上的金属前电介质(PMD)材料,其中形成有触点结构,以便为另外的上部金属化层(未示出)提供电互连通路。
[0013]在一些示例中,漂移区110还包括在PBL区106与第一n漂移区部分112之间的p漂移区部分111(标记为PD)。当包括p漂移区部分111时,该p漂移区部分111控制在隔离结构116下方的间隙漂移区部分113的镇流漂移部分与PBL区106之间的电场分布。在一些实施方式中,对于设计为在不同的漏极电压下工作的LDMOS晶体管,p漂移区部分111的掺杂浓度可以不同。
[0014]在一些示例中,可以关于中心源极结构136和单个p体区108以及另一栅极结构130、132、134和进一步横向向外的隔离结构116和漏极结构138以对称的方式复制(例如,图1中向左)图1中所示的结构,其中平行栅极结构彼此电互连,并且平行漏极结构138彼此电互连,该对称结构作为单个LDMOS晶体管101工作。其它对称实施方式是可能的,诸如在单个中央漏极结构138的两横向侧上具有对称平行的栅极结构和源极结构组。此外,如上所述,尽管图1中所示的LDMOS晶体管示例101是n沟道器件,但是在本文所述技术的其它实施方式中,p沟道LDMOS晶体管可能具有相反掺杂的结构和区域。
[0016]p体区108的锥形侧和隔离结构116的第二端限定大致梯形的JFET区150,JFET区150具有宽顶部和窄底部栅极,在图1中标记为BG。梯形JFET区150包括在栅极电介质层130下方的第二n漂移区部分114中的宽顶部。间隙漂移区部分113中的窄底部提供电压控制的底栅BG,以控制JFET区150与隔离结构116下方的第一n漂移区部分112的镇流漂移部分之间的电场分布。JFET区150在p体区106与下STI结构拐角之间的窄间隙中提供受控耗尽,用于在LDMOS截止状态期间的受控夹断,以防止栅极电介质层130处的过高电压。这有利于将单个薄栅极电介质层130用于IC 100中的低压晶体管(未示出)和LDMOS晶体管101。
[0017]参考图2和图3-图9,图2示出制造n沟道LDMOS晶体管的方法200,图3-图9示出在根据方法200生产图1的LDMOS晶体管的各个制造中间阶段下集成电路100的处理。在其它示例中,可以根据方法200使用相反的掺杂剂注入步骤和材料来制造P沟道LDMOS晶体管。在202处提供起始衬底。在一个示例中,在202处提供p掺杂硅晶片衬底,诸如图3中的衬底102。在另一个示例中,使用绝缘体上硅(SOI)起始晶片。在其它实施方式中,可以在202处提供不同半导体材料的衬底。在一个示例中,在204处使用外延生长沉积过程在衬底102上形成外延层(未示出),并且在衬底102的外延层中形成LDMOS晶体管101。在其它实施方式中,省略外延层和204处的处理。在206处,将n型掺杂剂(例如,磷)注入到衬底102中,以在衬底102中形成NBL区(例如,图3中的NBL区104)。在208处,通过将p型掺杂剂(例如,硼)注入到NBL区104上方的衬底102中,形成PBL区(例如,区106)。
[0018]如图3-图5所示,漂移区110在图2中的110处形成在PBL区106上方。在一个示例中,在图2中的211处,通过使用图3中的注入过程300将p型掺杂剂注入到第一深度302(例如,1.6μm)与第二深度304(例如,1.2μm)之间的衬底102中,在PBL区106上方形成p漂移区部分(图3中的111)。在其它实施方式中,可以省略211处的注入。如图4所示,在图2中的212处,使用图4中的注入过程400将n型掺杂剂注入到衬底102中,以在PBL区106上方(以及任何包括的p漂移区111上方)形成第一n漂移区部分112。在212处的注入在深度402(例如,0.5μm)与第二深度404(例如,1.2μm)之间形成第一(例如,深)n漂移区部分112,如图4所示。在一些示例中,图4中的第二深度404与图3中的第二深度304相同,尽管不是所有可能实施方式的严格要求。在图4的示例中,第一n漂移区部分112的较低深度404延伸到p漂移区部分111,并且位于PBL区106上方并与其间隔开。在其它实施方式中,将第一n漂移区部分112注入到PBL区106的深度,诸如没有注入p漂移区部分111的地方。
[0019]如图5中进一步所示,在图2中的213处使用注入过程500将n型掺杂剂注入到衬底102中,以形成到达深度502(例如,衬底102的上表面处的零深度)和第二深度504(例如,0.25μm)的第二(例如,浅)n漂移区部分114。在213处的注入形成在第一n漂移区部分112上方并与其间隔开的区域部分114,并且在n漂移区部分112与n漂移区部分114之间(例如,在图5中的深度502与深度504之间)留下或限定低掺杂间隙漂移区部分113。在一个示例中,由于从更高掺杂的n漂移区部分112和114扩散的尾部区域,部分113被轻度n掺杂。
[0020]在一个示例中,所示的方法200包括使用图6中的过程600在图2中的214处形成深沟槽隔离结构120。可以使用任何合适的深沟槽处理技术。在一个示例中,穿过漂移区110、PBL区106和NBL区104并进入部分的p衬底102来蚀刻沟槽。执行N+注入以将沟槽侧壁结构122掺杂到进入NBL区104中的某深度,并且将侧壁氧化以形成场氧化物结构124。硅沉积过程利用原位P+掺杂,以在氧化物结构124之间形成结构126,从而留下图6所示的深沟槽隔离结构120。
[0021]过程200在图2中的216处继续,利用图7中的浅沟槽隔离过程700形成向下延伸穿过第二n漂移区部分114并进入间隙漂移区部分113的隔离结构116(图7中标记为DRIFT(漂移)STI)。隔离结构116包括靠近预期漏极区的第一端和在预期栅极区下方的第二端。在216处,使用过程700在预期漏极区的横向外侧形成第二隔离结构118。在一个示例中,将沟槽蚀刻并用氧化物填充以形成结构116和118。可以使用其它过程诸如在216处的LOCOS过程,以形成隔离结构116和118。在一个示例中,图1中的STI隔离结构116向下延伸到衬底结构中大约0.35μm的深度,并且隔离结构116可以但不必具有与衬底102的上表面大致共面的上表面。
[0022]在图2中的218处,形成掩模802,并且使用如图8所示的注入过程800将p型掺杂剂注入到衬底102中。在218处的掩模注入形成延伸穿过漂移区110并进入PBL区106的p体区108,并且在衬底102的顶表面或上表面处提供窄沟道区。在一个示例中,在218处,使用成角度的注入过程800执行注入,以优先将注入的p型掺杂剂(例如,硼)横向地朝向隔离结构(即,图8中向右)扩散,从而产生p体108的锥形侧。当在该区域上形成栅极电介质层时,在p体的窄上表面中形成短沟道。这形成了大致梯形的JFET区,其顶部宽且底部窄。注入的p体区108的所得锥形侧在衬底102的顶表面处与隔离结构116的第二端横向间隔较大的横向沟道宽度距离D1,并且在间隙漂移区部分113中与隔离结构116横向间隔较小的距离D2。
[0023]在图2中的214处,使用如图9所示的任何合适的栅极制造过程900来形成栅极结构130、132、134。栅极电介质层130在沟道区、梯形JFET和部分的隔离结构116上延伸,以形成短沟道紧凑型栅极构造,从而控制预期的LDMOS晶体管。在222处,使用合适的注入过程形成N+源极区136和N+漏极区138以及任何包括的P+区140,以提供如上结合图1所述的n沟道LDMOS结构101。在一个示例中,在222处的处理包括将n型掺杂剂注入到衬底102中,以与p体区108中的沟道区相邻形成n型源极区136,并与第二n漂移区部分114中的隔离结构116的第一端相邻形成n型漏极区138。在224处执行进一步的处理,以形成触点、金属化结构并完成其它后端处理,从而完成集成电路100。
[0024]还参考图10,示出方法200的另一个非限制性替代实施方式。图2所示的过程200包括在形成隔离结构116之前形成第一n漂移区部分112和第二n漂移区部分114。在图10的替代实施方式中,在形成隔离结构116之后,形成第一n漂移区部分112和第二n漂移区部分114。在该示例中,在202-208处的处理如上结合图2所述,包括在206处形成NBL区104和在208处形成PBL区106。在211处可选地执行p漂移区部分111,并且在212处形成第一n漂移区部分112。在图10的示例中,如上所述,在214处形成沟槽隔离结构,并且在216处形成STI或其它隔离结构。在图10中的210处,在216处形成隔离结构之后,通过注入在211处可选地形成p漂移区部分111,并且在212和213处形成第一n漂移区部分112和浅的第二n漂移区部分114。在218-224处,形成p体区108,以及如上所述的栅极结构、源极/漏极区和最终的触点和金属化结构。
[0025]一些描述的示例包括短沟道LDMOS晶体管101,其具有梯形JFET区150、底栅BG和包括第一n型漂移区部分112的镇流漂移区。LDMOS晶体管101实现梯形JFET区150,该梯形JFET区150具有底栅BG和镇流漂移概念,其具有短沟道设计和低导通状态电阻以及低开关损耗(例如,低RDSON*Q)的优点。与分裂或阶梯式栅极方法相比,所描述的LDMOS晶体管101提供改善的解决方案,同时便于集成电路100使用单个薄栅极电介质层,集成电路100包括低电压CMOS逻辑晶体管和用于较高电压工作的LDMOS器件。在这方面,本文描述的技术可用于为高电压应用提供小间距尺寸的短沟道LDMOS晶体管101。此外,可以用最少数量的注入掩模和处理步骤来制造漂移层结构110和锥形p体区108,以提供支持适用于高速应用中的功率开关的低掩模计数和低Rsp/R*Q集成LDMOS的解决方案。例如,LDMOS晶体管101可以用作在高开关频率下工作的降压或升压DC-DC转换器中的高侧或低侧开关,其中扩展的漏极减小输出电容和栅极电容,以促进高速、低开关损耗工作,同时允许较高的漏极电压。
[0026]在一些示例性实施方式中,LDMOS结构101包括三个注入区104、106和110,它们可以经由堆叠的毯式注入来形成而无需额外的掩模,以产生栅极电介质层130的一部分下方的短沟道区、梯形JFET区150(图1)、以及STI隔离结构116下方的第一n型漂移区部分112中的增强镇流漂移区,在一些实施方式中,通过具有一个体掩模层的体链式(body chain)注入来制造该镇流漂移区。图1中的LDMOS示例101通过深沟槽(DT)掩模层处的深沟槽隔离环结构120与衬底102隔离。在一些制造过程实施方式中,LDMOS恶意与现有过程流程兼容,其中在可选的内联(in-line)外延沉积过程之前(例如,在上述图2和图10中的204处沉积外延硅之前),将重掺杂n型掩埋毯式注入与其他两个毯式注入过程分离。各种实施方式也与集成电路100中的其他器件的制造兼容,诸如其中通过使用一个额外的漂移掩模来掩蔽其它(例如,非LDMOS或非LDMOS漏极漂移)区,可以处理n型漂移链式注入或与p型掩埋链式注入(例如,图2和图10中的206、208和/或210)一起工作的n型漂移。在一个示例中,在210处的注入是用单独的掩模来完成的,该掩模转换IC 100的预期p体区和非LDMOS区。
[0027]在图1的示例中,漂移区110包括两个n型和一个p型链式注入,其中较高掺杂的漂移浅n型区部分114可以仅注入在器件缘沟(非STI)区中(例如,通过形成隔离结构116之后的后续注入,如上述图10所示)。所得结构提供减小的JFET电阻和补偿的界面电荷,以改善器件热载流子性能。第一(例如,较深的)n型漂移区部分112与PBL区106和底栅BG一起工作,以在漂移STI下方提供高掺杂的镇流区,从而增强电荷平衡和器件减小的表面场(RESURF)以支持以小间距尺寸进行的高电压工作,从而减小Rsp和LDMOS漏极的输出电容。PBL区106增强了区112中的N掺杂低电阻横向电流流动路径的电荷平衡。间隙区部分113提供靠近STI隔离结构116的底部和低电压侧壁的缓冲(buffer)。该缓冲通过第一和第二(深和浅)n漂移区部分112和114的尾部区域的重叠而形成,并且防止由于高漏极电压电平下的高掺杂窄镇流而导致的早期表面电场(E场)累积。在各种示例中,可以通过额外的毯式注入调整缓冲掺杂分布,或者可以通过现有的漂移链式注入来提供这种调整的掺杂而无需额外的掩模。
[0028]锥形JFET区150成形为具有宽顶部的倒梯形区域,以释放表面附近的E场,从而保护在LDMOS 101和IC 100中的其它较低电压器件中使用的潜在薄栅极电介质层130。梯形JFET区150提供具有宽度D2的窄底部,并且用作电压控制的底栅BG,以在目标电压下调整镇流漂移与JFET 150之间的E场分布,并且该设计可以针对给定的目标工作电压电平进行定制。在工作中,即使在高漏极电压电平下的窄的高掺杂镇流漂移下,倒梯形JFET 150和底栅BG也会减小表面E场,以有助于在小横向距离或间距(例如,低比电阻Rsp)下的漂移区中低导通状态电阻。LDMOS 101实现短沟道区,用于减小的沟道电阻和低栅极电容,同时减轻表面短沟道穿通。此外,短沟道长度减小栅极电容,从而减小与栅极电荷Qg有关的开关损耗,这在高工作频率或开关速度下尤其有利。该设计有助于在导通状态性能与截止状态性能之间进行权衡,并且仅在浅/窄底栅区域BG中允许有限的JFET电阻,结合由于释放的表面E场、补偿的界面和高掺杂漂移浅区而改善的器件热载流子性能和减小的整体JFET电阻。
[0029]电压控制的底栅BG在目标电压下调整或设置镇流漂移区与JFET区150之间的E场分布,并且底栅BG的尺寸提供受控的耗尽和区间距截止(pitch-off)。在完全导通的条件下,JFET底栅在高栅极/低漏极电压下以最小的耗尽区域工作。在LDMOS 101的准截止条件下,在低栅极/高漏极电压下耗尽最大区域,并且JFET表面峰值E场(E峰)与目标设计最大工作电压同步。
[0030]所描述的具有梯形JFET区150、底栅BG和镇流漂移区的短沟道LDMOS晶体管101为功率开关和其它应用提供低R*Q和相关的益处。在其它示例中,可以将梯形JFET、底栅和镇流漂移与深n阱和深沟槽隔离结构120结合使用,并且例如可以省略PBL区106和/或NBL区104,以进一步减少掩模的数量和过程成本。在这方面,PBL 106和NBL 104可以通过毯式注入实现,而无需额外的掩模层。在其它示例中,短沟道LDMOS 101可以通过梯形JFET区150、结合底栅BG和镇流漂移来实现,并与单个IC 100中的低成本CMOS晶体管(例如,与LDMOS层共享)一起工作,并且这种设计可以省略一个或多个CMOS n阱层,以进一步减少掩模计数。另外,一些示例采用专用体链式注入作为基础,将器件短沟道、底栅和增强的镇流漂移连接在一起,以获得更好的器件性能。在一个示例中,p体108可以使用链式p型注入来形成(例如,在上述图2和图10中的218处),链式p型注入包括注入能量为300KeV至2MeV的硼(B)注入,该硼(B)注入与特定目标额定平台电压相关,且注入剂量为9E13至2E12。在一些示例中,p体区以0-9度的角度注入,以便于连接器件浅体、底栅和毯式p型掩埋层区106。
[0031]在进一步的示例中,LDMOS 101用梯形JFET区150制成,该梯形JFET区150由堆叠在与STI隔离结构116的侧壁一起工作的p体上/下体链式注入的顶部上的专用浅体共注入制成。在一个示例中,器件短沟道通过浅体共注入的硼与砷之间的表面横向扩散而形成,用于目标小栅极沟道长度Lg和低栅极电荷Qg以降低开关损耗。在一个示例中,通过p型硼和n型砷共注入来制造逆向的浅体,该共注入包括注入能量为60KeV至260KeV、注入剂量为5E14至1E13、注入角度为7-35°的硼(B)注入和能量为25KeV至160KeV、注入剂量为1E15至3E13、注入角度为0-9°的砷(As)注入。在一个示例中,在STI隔离结构116的底部拐角附近形成的底栅区BG通常与p体区108/漂移区结的最外范围对准,以将耗尽区间距截止控制在目标控制电压电平。在一个示例中,底栅BG的最低掺杂区域与硅衬底上表面的间隔为0.25μm至0.6μm,并且在一个示例中,通过从STI隔离结构侧壁到源极侧的栅极多晶硅边缘之间的间隔将底栅BG的宽度D2控制为0.35μm至1.5μm,以针对不同的额定器件电压。
[0032]在使用两个n型漂移区部分112和114以及P型漂移区部分111的一些示例中,使用n型/p型链式注入形成漂移区110,包括注入能量为160KeV至2MeV、注入剂量为2E13至1E12且注入角度为0-9°的n型磷(P)注入(例如,在图2和图10中的212和213处),并结合注入能量为600KeV至2MeV、注入剂量为2E13至1E12且注入角度为0度至9度的P型硼(B)注入(例如,在图2和图10中的211处),用于具有在漂移STI隔离结构116下方内置小镇流区的增强的电荷平衡,以有助于低器件Rsp和低输出电容Coss。在一些示例中,在STI隔离结构蚀刻之后,将浅n型第二漂移区部分114注入在第一n型漂移区部分112的顶部(例如,没有间隙区113)上,并且区部分114仅位于非STI区域中。在这个示例中,通过注入能量为25KeV至500KeV、总注入剂量为2E13至1E12且注入角度为0-9度的n型砷或磷或磷与砷注入来完成第二漂移区部分114的注入,以有助于减小JFET电阻并通过改善的器件热载流子性能来补偿界面电荷。在一些示例中,在漂移链式注入中添加额外的p型或n型轻掺杂注入,以调节底栅(缓冲区域)电压对栅极/漏极电压的灵敏度,在这种情况下,n型/p型注入被控制在2e11至2e12的注入剂量,注入投影深度范围为0.25μm至0.6μm。
[0033]在一些示例中,短沟道LDMOS 111被制造在隔离边界内,诸如所示的NBL区104、PBL区106和环形深沟槽隔离结构120的组合。在一些示例中,隔离特征包括在任何内联外延沉积处理之后注入厚度为3μm至10μm的重掺杂隔离NBL槽区104,结合周围的深N型阱结构和/或环形深沟槽隔离结构120的所示深沟槽N部分122。在一些示例中,可以添加经调整的p型空白掩埋注入,并根据需要与p型漂移区部分111的任何包括的注入堆叠,以减少平台寄生BJT问题,例如,注入能量为800KeV至2.5MeV、注入剂量为2E13至5E11且注入角度为0-9度。在一些示例中,NBL区104和PBL区106与深沟槽结构120或任何包括的深n阱(未示出)一起工作,以将LDMOS晶体管101与衬底102隔离,用于器件高侧和隔离应用。
[0034]在权利要求的范围内,在描述的实施例中修改是可能的,并且其它实施例也是可能的。