English:
[0003] FIGURE 1 is a diagram illustrating an embodiment of a computer device power management system;
[0004] FIGURE 2 is a diagram illustrating an embodiment of a controller circuit of a power management system;
[0005] FIGURE 3 is an exemplary timing diagram based on signals associated with the controller circuit of FIGURE 2; and
[0006] FIGURE 4 is a flow diagram illustrating an embodiment of a computer device power management method.
[0007] The preferred embodiments of the present invention and the advantages thereof are best understood by referring to FIGURES 1-4 of the drawings, like numerals being used for like and corresponding parts of the various drawings.
[0008] FIGURE 1 is a diagram illustrating an embodiment of a computer device power management system 10. In the embodiment illustrated in FIGURE 1 , system 10 is implemented in a computer device 12. Computer device 12 may comprise any type of computing device having a processor 14 such as, but not limited to, a notebook or laptop computer, personal digital assistant, tablet computer, or other type of portable or non-portable electronic device. In the embodiment illustrated in FIGURE 1 , computer device 12 is configured to be powered by an alternating current (AC) adapter 20 and/or a battery 22. In FIGURE 1, battery 22 is illustrated as being an internal battery. However, it should be understood that battery 22 may also comprise an external battery. Processor 14 may comprise a general processing platform or a processing platform associated with a graphics generator/system or other type of function.
[0009] In the embodiment illustrated in FIGURE 1 , system 10 comprises a controller 30 for managing and/or otherwise controlling a power draw by computer device 12 from adapter 20 and/or battery 22. Controller 30 may comprise hardware, software, firmware or a combination thereof. For example, in the embodiment illustrated in FIGURE 1 , controller 30 comprises logic 32 which may be an ordered listing of executable instructions that can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device, and execute the instructions. In the context of this document, a "computer-readable medium" can be any means that can contain, store, communicate, propagate or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer-readable medium can be, for example, but is not limited to, an electronic, magnetic, optical, electro-magnetic, infrared, or semi-conductor system, apparatus, device, or propagation medium. In the embodiment illustrated in FIGURE 1 , controller 30 is illustrated as being disposed within a basic input/output system (BIOS) 40. However, it should be understood that controller 30 may be otherwise stored and/or located.
[0010] In FIGURE 1 , processor 14 is configured having a plurality of different power states such that each power state comprises a different predetermined operating frequency for processor 14. For example, in the embodiment illustrated in FIGURE 1 , processor 14 is configured having a power state PO (indicated by 50), a power state P1 (indicated by 52), a power state P2 (indicated by 54), through a power state Pn (indicated by 60). In this example, power state PO represents an operating frequency of processor 14 at its maximum or normal operating frequency, and each of power states PI-Pn represents an incrementally decreasing and predetermined operating frequency of processor 14 (e.g., power state P1 having an operating frequency less than PO, power state P2 having an operating frequency less than P1 , etc.). However, it should be understood that the power states of processor 14 may be otherwise identified and/or ordered (e.g., power state PO representing the lowest power state and Pn representing the highest power state). In FIGURE 1 , controller 30 also comprises a timer 34 (e.g., an internal timer preferably implemented in firmware). Timer 34 is used to limit a quantity of power state changes performed on processor 14 during a predetermined time period, thereby preventing power state changes from occurring too often (which would detrimentally affect processor 14 performance and cause overly-frequent processing interruptions). Thus, for example, in some embodiments, timer 34 is used to limit a quantity of power state changes of processor 14 to one per second; however, it should be understood that other timing scenarios may be used.
[0011] In operation, controller 30 monitors the amount of current drawn from adapter 20 and/or battery 22 and throttles processor 14 (e.g., while within a particular power state) to prevent adapter 20 and/or battery 22 from reaching their respective rated current limit. For example, an overcurrent condition is generally defined when computer device 12 tries to draw a level of current from adapter 20 and/or battery 22 that approaches and/or otherwise reaches their respective rated current limit. Adapter 20 and/or battery 22 is configured to generate and/or otherwise transmit an analog current limit signal indicating the overcurrent condition. The analog current signal received by controller 30 from adapter 20 and/or battery 22 is used to generate an overcurrent protection (OCP) signal which is used to throttle processor 14. For example, the OCP signal is generally a pulse-width-modulated (PWM) signal with a fixed amplitude (e.g., 3.3 volts). As used herein, to "throttle" or "throttling" of processor 14 means that the operating speed or frequency of processor 14 is throttled by periodically stopping the clock of processor 14 for a desired percentage of time, thereby reducing the effective speed or frequency of processor 14 and, correspondingly, the amount of power drawn from adapter 20 and/or battery 22.
[0012] In addition to throttling of processor 14, controller 30 is configured to automatically and/or dynamically adjust a power state of processor 14 based on a level of throttling of processor 14. For example, embodiments of system 10 monitor a level of throttling of processor 14 to determine when a decrement or increment to a power state of processor 14 should be performed. Thus, for example, if the level of throttling of processor 14 increases beyond a predetermined threshold, controller 30 automatically decrements the power state of processor 14, thereby resulting in a reduced power draw from adapter 20 and/or battery 22. Correspondingly, as the load on adapter 20 and/or battery 22 decreases and the level of throttling of processor 14 decreases, controller 30 automatically increments the power state of processor 14. Generally, a decrease in the power state of processor 14 results in a decrease in the voltage used to power processor 14, thereby resulting in a significant savings in power drawn from adapter 20 and/or battery 22.
[0013] FIGURE 2 is a diagram illustrating an embodiment of a controller circuit 70 of controller 30. In the embodiment illustrated in FIGURE 2, circuit 70 comprises resistors R1, R2, and R3forming a divider 72 for inputting two different reference voltages, indicated by VUPPERand VLOWER,to comparators 74 and 76, respectively. Further, circuit 70 comprises a low pass filter 78 comprising a resistor R4and a capacitor Ci for generating an averaged OCP signal (identified as AVG-OCP) from the OCP signal. The AVG-OCP signal is indicative of the averaged level of throttling of processor 14 (FIGURE 1). In the embodiment illustrated in Figure 2, circuit 70 also comprises resistors R5and R6coupled to inputs to comparators 74 and 76, respectively, resistors R7and R8coupled across comparators 74 and 76, respectively, and resistors R9and R10coupled between respective outputs of comparators 74 and 76 and a logic level voltage (e.g., 3.3 volts). As illustrated in FIGURE 2, the output of comparator 74 is defined as an increment signal (illustrated as11INC" in FIGURE 2), and the output of comparator 76 is defined as a decrement signal (illustrated as "DEC" in FIGURE 2).
[0014] In operation, the outputs of comparators 74 and 76 are used to determine whether to increment or decrement the power state of processor 14 (FIGURE 1) based on the level of throttling of processor 14 as indicated by the average OCP signal. The operation of circuit 70 will be better understood by referring to FIGURE 3 which is an exemplary embodiment of a timing diagram based on signals associated with circuit 70 illustrated in FIGURE 2. In the embodiment illustrated in FIGURE 3, the timing diagram indicates the state of the OCP signal
[0015] Referring to FIGURES 2 and 3, the output of comparator 74 (the increment signal) is HI whenever the averaged OCP signal (AVG-OCP) is below a fixed threshold (VUPPER) and is LO whenever the averaged OCP signal (AVGJDCP) is above a fixed threshold (VUPPER). Further, the output of comparator 76 (the decrement signal) is HI whenever the averaged OCP signal (AVG-OCP) is below a fixed voltage threshold (VLOWER) and LO whenever the averaged OCP signal (AVG-OCP) is above a fixed voltage threshold (VL0WER). Thus, referring to FIGURE 3 at or around timing position T1, the OCP signal indicates that processor 14 (FIGURE 1) is being throttled; as a result, the averaged OCP signal (AVG-OCP) begins to increase from approximately zero volts, indicating an increasing level of throttling of processor 14. As illustrated in FIGURE 3, the increment and decrement signals are both in a HI state at timing position T1. because the AVG-OCP signal is lower than both the VUPPER and VLOWERthresholds.
[0016] At timing position T2, the AVG-OCP signal increases above VLOWER. thereby indicating an increasing level of throttling of processor 14 (FIGURE 1) and resulting in the decrement signal being LO. As the level of throttling of processor 14 increases, at timing position T3, the AVG-OCP signal increases above VUPPER, thereby resulting in increment signal being LO. In response to both increment and decrement signals being LO, controller 30 and/or BIOS 40 causes a decrement in the power state of processor 14 from state PO to state P1. Thus, in the P1 power state, the operating frequency of processor 14 and the voltage used to power processor 14 are reduced, as well as the current drawn from adapter 20 and/or battery 22.
[0017] At timing position T4, the level of throttling has decreased such that the AVG-OCP signal is lower than VUPPER, thereby resulting in the increment signal being HI. At timing position T5, a further reduction in the amount of throttling of processor 14 results in the AVG-OCP signal decreasing to below VLOWER. thereby resulting in the decrement signal being HI. In the embodiment illustrated in FIGURE 3, the internal timer (e.g., timer 34 of FIGURE 1) is used to determine whether to increment or decrement the power state of processor 14. For example, in some embodiments, at each increment/decrement of a power state of processor 14, the internal timer 34 is initiated. After internal timer 34 expires, the increment and decrement signals are evaluated. Thus, after internal timer 34 expires, if the increment and decrement signals are both HI, processor 14 is incremented, and if the increment and decrement signals are both LO, processor 14 is decremented. However, if the increment signal is HI but the decrement signal is LO after internal timer 34 expires, no incrementing/decrementing of processor 14 is performed until such time that both the increment and decrement signals are either both HI or both LO. Thus, referring to FIGURE 3, at timing position T3, internal timer 34 is initialized. At timing position T5, although both the increment and decrement signals are HI, internal timer 34 has not yet expired, so processor 14 is not yet incremented. At timing position T6, internal timer 34 expires and, because the increment and decrement signals are both HI, controller 30 and/or BIOS 40 causes an increment of the power state of processor 14 from state P1 to state PO.
[0018] At timing position T7, timer 34 expires while the increment and decrement signals are both LO, resulting in a transition of the power state of processor 14 from PO to P1. At timing position T8, internal timer 34 expires and the increment and decrement signals are again evaluated. At timing position T8, because both the increment and decrement signals remain LO (e.g., because the AVG-OCP signal remains above both VLOWER and VUPPER), controller 30 and/or BIOS 40 causes another decrement in the power state of processor 14 from power state P1 to power state P2. It should be understood that if the AVG-OCP signal remains below both VLOWER and VUPPER for additional timer 34 periods (e.g., both the increment and decrement signals remaining LO), the power state of processor 14 is incrementally decremented after each timer period until the lowest power state is reached.
[0019] At timing position T9, timer 34 expires. However, because the increment signal is HI and the decrement signal is LO, no incrementing/decrementing of processor 14 is performed until, as indicated at timing position T10, both the increment and decrement signals are HI, at which time processor 14 is incremented from power state P2 to power state P1 and timer 34 is again initialized. It should also be understood that if the AVG-OCP signal remains below both VUPpERand VLOWERfor additional timer 34 periods (e.g., both the increment and decrement signals remaining HI), the power state of processor 14 is incrementally incremented after each time period until PO is reached. Accordingly, if the AVG-OCP signal remains between the VUPPERand VLOWERthresholds (e.g., the increment signal being HI and the decrement signal being LO), the power state of processor 14 remains unchanged.
[0020] In the embodiment illustrated in FIGURE 1 and 2, throttling and adjustment of a power state of a single processor is described. However, it should be understood that the above-described system 10 and method may be used on multiple processing platforms. For example, throttling and power-state shifting may be performed in a graphics memory processor, a graphics engine processor, or other processing platform together or separately. Further, in the embodiment illustrated in FIGURE 2, circuit 30 is configured to output two signals (i.e., the increment and decrement signals). However, it should be understood that circuit 30 may be otherwise configured (e.g., to output a single signal for either incrementing or decrementing the power state of a processor). Further, it should be understood that the function(s) of circuit 30 may be performed entirely or at least partially by software/firmware.
[0021] FIGURE 4 is a flow diagram illustrating an embodiment of a computer device power management method. The method begins at block 400, where timer 34 is checked. At decision block 402, a determination is made whether timer 34 has expired. If timer 34 has expired, the method proceeds to decision block 404, where a determination is made whether the increment and decrement signals are both HI. If the increment and decrement signals are both HI, the method proceeds to decision block 406, where a determination is made whether the power state of processor 14 is at its highest available level (e.g., PO). If the power state of processor 14 is not yet at its highest level, the method proceeds to block 408 where the power state of processor 14 is incremented by one state or level (e.g., from P2 to P1). The method proceeds to block 410 where timer 34 is initialized and/or otherwise started. If at decision block 406 it is determined that the power state of processor 14 is at its highest level, no power state adjustment is performed on processor 14 and the method proceeds to block 400 where timer 34 is again checked and/or monitored.
[0022] If at decision block 404 it is determined that the increment and decrement signals are not both HI, the method proceeds to decision block 412, where it is determined whether the increment and decrement signals are both LO. If the increment and decrement signals are not both LO, no power state adjustment is performed on processor 14 and the method proceeds to block 400 where timer 34 is again checked and/or monitored. If at decision block 412 it is determined that the increment and decrement signals are both LO, the method proceeds to decision block 414, where it is determined whether processor 14 is at its lowest available power state. If processor 14 is at its lowest available power state, no power state adjustment is performed on processor 14 and the method proceeds to block 400 where timer 34 is again checked and/or monitored. If at decision block 414 it is determined that processor 14 is not yet at its lowest available power state, the method proceeds to block 416, where the power state of processor 14 is decremented by one state or level (e.g., from P1 to P2). The method proceeds to block 410 where timer 34 is initialized and/or otherwise started.
[0023] Thus, in operation, based on the level of throttling of processor 14 as indicated by the averaged OCP signal (as also indicated by the HI or LO conditions of increment and decrement signals output by comparator 74 and 76), the power state of processor 14 is incremented or decremented one or more levels to control a power draw of computer device 12. Accordingly, embodiments of system 10 provide for variable processor control using both throttling and power state adjustments to control a power draw from adapter 20 and/or battery 22. It should be understood that in the described method, certain functions may be omitted, accomplished in a sequence different from that depicted in FIGURE 4, or simultaneously performed. Also, it should be understood that the method depicted in FIGURE 4 may be altered to encompass any of the other features or aspects of the invention as described elsewhere in the specification. Further, embodiments may be implemented in software and can be adapted to run on different platforms and operating systems.

中文:
[0003]图1是示出计算机设备功率管理系统的实施例的原理图;
[0004]图2是示出功率管理系统的控制器电路的实施例的原理图;
[0005]图3是基于与图2的控制器电路相关的信号的示例性时序图;并且
[0006]图4是示出计算机设备功率管理方法的实施例的流程图。
[0007]通过参照附图的图1到4,可以很好地理解本发明的优选实施例及其优点,对于不同附图中相同和相应的部分使用相同的附图标记。
[0008]图1是示出计算机设备功率管理系统10的实施例的原理图。在图1所示的实施例中,在计算机设备12中实施系统10。计算机设备12可包括具有处理器14的任何类型的计算机设备,例如,但不限于,笔记本电脑或膝上型电脑、个人数字助理、平板计算机,或者其它类型的便携式或非便携式电子设备。在图1所示的实施例中,计算机设备12被配置为用交流(AC)适配器20和/或电池22供电。在图1中,电池22被示为内部电池。然而,应当理解的是,电池22也可以包括外部电池。处理器14可包括通用处理平台或与图形发生器/系统或其它类型的功能相关的处理平台。
[0009]在图1所示的实施例中,系统10包括控制器30,其用于管理和/或控制计算机设备12从适配器20和/或电池22吸取的功率。控制器30可包括硬件、软件、固件或它们的组合。例如,在图1所示的实施例中,控制器30包括可以是可执行指令的有序列表的逻辑32,该有序列表可以嵌入由指令执行系统、设备或装置使用的或与它们联系使用的任何计算机可读介质中,指令执行系统、设备或装置例如基于计算机的系统、包含处理器的系统,或可从指令执行系统、设备或装置中取得指令并执行指令的其它系统。在本文档的上下文中,“计算机可读介质”可以是可包含、存储、传送、传播或传输由指令执行系统、设备或装置使用的或与它们联系使用的程序的任何手段。计算机可读介质可以是,例如,但不限于,电子、磁、光、电磁、红外或半导体系统、设备、装置,或传播介质。在图1所示的实施例中,控制器30被示为被布置在基本输入/输出系统(BIOS)40内。然而,应当理解的是,可以用别的方式存储和/或设置控制器30。
[0010]在图1中,处理器14被配置为具有多个不同的功率状态,使得每个功率状态包括用于处理器14的不同的预定工作频率。例如在图1所示的实施例中,处理器14被配置为具有功率状态P0(用50标出)、功率状态P1(用52标出)、功率状态P2(用54标出),直到功率状态Pn(用60标出)。在该实例中,功率状态P0表示处理器14在其最大或正常工作频率处的工作频率,并且功率状态P1到Pn中的每个功率状态表示递减的并且预定的处理器14的工作频率(例如,功率状态P1具有小于P0的工作频率,功率状态P2具有小于P1的工作频率,等等)。然而,应当理解的是,可以用别的方式标识和/或排列处理器14的功率状态(例如,功率状态P0表示最低功率状态而Pn表示最高功率状态)。在图1中,控制器30还包括定时器34(例如优选地在固件中实施的内部定时器)。定时器34用于限制在预计时间周期内在处理器14上执行的功率状态改变的数量,从而防止功率状态改变过于频繁地发生(这会对处理器14的性能有不利影响,并且会导致过频的处理中断)。因此,例如,在一些实施例中,定时器34用于将处理器14的功率状态改变的数量限制为每秒一次;然而,应当理解的是,可以使用其它的定时方案。
[0011]在操作中,控制器30监控从适配器20和/或电池22吸取的电流量并将处理器14减速(例如,当在特定的功率状态中时)以防止适配器20和/或电池22达到它们各自的额定电流限制。例如,过流条件一般定义当计算机设备12试图从适配器20和/或电池22吸取的电流等级接近和/或达到它们各自的额定电流限制时。适配器20和/或电池22被配置为生成和/或发送表明过流条件的模拟电流限制信号。控制器30从适配器20和/或电池22接收的模拟电流信号被用于生成用于将处理器14减速的过流保护(OCP)信号。例如,OCP信号一般是具有固定幅度(例如,3.3伏)的脉宽调制(PWM)信号。如在文中所用,处理器的“减速”表示通过将处理器14的时钟周期性地停止所需的百分比的时间来减低处理器14的工作速度或频率,从而减少处理器14的有效速度或频率,并且相应地减少从适配器20和/或电池22吸取的功率量。
[0012]除了处理器14的减速以外,控制器30被配置为基于处理器14的减速等级来自动地和/或动态地调节处理器14的功率状态。例如,系统10的实施例监控处理器14的减速等级,以便确定应当在何时执行对处理器14的功率状态的递增或递减。因此,例如,如果处理器14的减速等级增加到超过预定的阈值,控制器30自动地递减处理器14的功率状态,从而导致从适配器20和/或电池22吸取的功率减少。相应地,随着适配器20和/或电池22上的负荷的降低以及处理器14的减速等级的降低,控制器30自动地递增处理器14的功率状态。一般来说,处理器14的功率状态的降低导致用于为处理器14供电的电压的降低,从而导致显著地节约了从适配器20和/或电池22吸取的功率。
[0013]图2是示出控制器30的控制器电路70的实施例的原理图。在图2所示的实施例中,电路70包括形成分压器72的电阻器R1、R2和R3,该分压器72用于向比较器74和76分别输入由VUPPER和VLOWER标出的两个不同的参考电压。另外,电路70包括用于从OCP信号生成平均OCP信号(标为AVG_OCP)的低通滤波器78,该低通滤波器78包括电阻器R4和电容器C1。AVG_OCP信号表明处理器14的平均减速等级(图1)。在图2所示的实施例中,电路70还包括分别连接到比较器74和76的输入的电阻器R5和R6、分别跨比较器74和76连接的电阻器R7和R8,以及连接在比较器74和76各自的输出与逻辑级电压(例如,3.3伏)之间的电阻器R9和R10。如图2所示,比较器74的输出被定义为增量信号(在图2中示为“INC”),并且比较器76的输出被定义为减量信号(在图2中示为“DEC”)。
[0014]在操作中,比较器74和76的输出被用于确定是否基于如平均OCP信号所表明的处理器14的减速等级来递增或递减处理器14(图1)的功率状态。通过参照图3将更好地理解电路70的操作,图3是基于与图2所示的电路70相关的信号的时序图的示例性实施例。在图3所示的实施例中,时序图示出OCP信号的状态(例如,0伏或3.3伏)、AVG_OCP信号的电压等级(例如,0伏和3.3伏之间)、增量(INC)和减量(DEC)信号的状态、处理器14的功率状态,以及控制器30的内部定时器34。
[0015]参照图2和3,只要平均OCP信号(AVG_OCP)低于固定阈值(VUPPER),比较器74的输出(增量信号)为高(HI),并且只要平均OCP信号(AVG_OCP)高于固定阈值(VUPPER),比较器74的输出为低(LO)。另外,只要平均OCP信号(AVG_OCP)低于固定电压阈值(VLOWER),比较器76的输出(减量信号)为HI,并且只要平均OCP信号(AVG_OCP)高于固定电压阈值(VLOWER),比较器76的输出(减量信号)为LO。因此,参照图3,在时序位置T1处或在时序位置T1附近,OCP信号表明处理器14(图1)被减速;因此,平均OCP信号(AVG_OCP)从大约0伏开始增加,表明处理器14的增加的减速等级。如图3所示,由于AVG_OCP信号比VUPPER和VLOWER阈值都要低,在时序位置T1处增量和减量信号都在HI状态中。
[0016]在时序位置T2处,AVG_OCP信号增加到VLOWER之上,从而表明处理器14(图1)的增加的减速等级,并导致减量信号为LO。随着处理器14的减速等级的增加,在时序位置T3处,AVG_OCP信号增加到VUPPER之上,从而导致增量信号为LO。对增量和减量信号都为LO响应,控制器30和/或BIOS 40使处理器14的功率状态从状态P0递减到状态P1。因此,在P1功率状态中,不仅从适配器20和/或电池22吸取的电流减少,而且处理器14的工作频率和用于为处理器14供电的电压也降低。
[0017]在时序位置T4处,减速等级已经降低,使得AVG_OCP信号低于VUPPER,从而导致增量信号为HI。在时序位置T5处,处理器14的减速量的进一步减少导致AVG_OCP信号降低至VLOWER以下,从而导致增量信号为HI。在图3所示的实施例中,内部定时器(例如,图1的定时器34)用于确定是否递增或递减处理器14的功率状态。例如,在一些实施例中,每当处理器14的功率状态递增/递减时,启动内部定时器34。在定时器34到期之后,评估增量和减量信号。因此,在内部定时器34到期之后,如果增量和减量信号都为HI,处理器14的功率状态递增,并且如果增量和减量信号都为LO,处理器14的功率状态递减。然而,如果在内部定时器34到期之后增量信号为HI而减量信号为LO,不执行处理器14的功率状态的递增或/递减,直到增量和减量信号都为HI或都为LO的时刻为止。因此,参照图3,在时序位置T3处初始化内部定时器34。在时序位置T5处,尽管增量和减量信号都为HI,内部定时器34还没有到期,因而不递增处理器14的功率状态。在时序位置T6处,内部定时器34到期,并且由于增量和减量信号都为HI,控制器30和/或BIOS 40使处理器14的功率状态从状态P1递增到状态P0。
[0018]在时序位置T7处,定时器34到期而且增量和减量信号都为LO,这导致处理器14的功率状态从P0转变到P1。在时序位置T8处,内部定时器34到期,并且重新评估增量和减量信号。在时序位置T8处,由于增量和减量信号保持为LO(例如,由于AVG_OCP信号保持高于VLOWER和VUPPER),控制器30和/或BIOS 40使处理器14的功率状态从功率状态P1再次递减到功率状态P2。应当理解的是,如果AVG_OCP信号在其它的定时器34周期里保持低于VLOWER和VUPPER(例如,增量和减量信号都保持为LO),在每个定时器周期之后,处理器14的功率状态逐次递减,直到达到最低的功率状态为止。
[0019]在时序位置T9处,定时器34到期。然而,由于增量信号为HI而减量信号为LO,不执行处理器14的递增/递减,直到,如在时序位置T10处所示的,增量和减量信号都为HI为止,在该时刻处理器14从功率状态P2递增到功率状态P1,并且重新初始化定时器34。还应当理解的是,如果AVG_OCP信号在其它的定时器34周期里保持低于VUPPER和VLOWER(例如,增量和减量信号都保持为HI),在每个定时器周期之后,处理器14的功率状态逐次递增,直到达到P0为止。因此,如果AVG_OCP信号保持在VUPPER和VLOWER阈值之间(例如,增量信号为HI而减量信号为LO),处理器14的功率状态保持不变。
[0020]在图1和2所示的实施例中,描述了单个处理器的功率状态的减速和调节。然而,应当理解的是,可在多个处理平台上使用上述系统10和方法。例如,可以在图形存储器处理器、图形引擎处理器,或其它处理平台中一起或独立地执行减速和功率状态转换。另外,在图2所示的实施例中,电路30被配置为输出两个信号(即,增量和减量信号)。然而,应当理解的是,可以用别的方式配置电路30(例如,输出用于递增或递减处理器功率状态的单个信号)。另外,应当理解的是,电路30的功能可以全部或至少部分地由软件/固件来执行。
[0021]图4是示出计算机设备功率管理方法的实施例的流程图。该方法在检查定时器34的块400处开始。在判定块402处,确定定时器34是否已到期。如果定时器34已到期,方法前进至判定块404,其中确定增量和减量信号是否都为HI。如果增量和减量信号都为HI,方法前进至判定块406,其中确定处理器14的功率状态是否在其最高的可用等级(例如,P0)。如果处理器14的功率状态还不在其最高等级,方法前进至块408,其中处理器14的功率状态递增一个状态或等级(例如,从P2到P1)。方法前进至块410,其中初始化和/或启动定时器34。如果在判定块406处确定处理器14的功率状态在其最高等级,不在处理器14上执行功率状态调节,并且方法前进至块400,其中重新检查和/或监控定时器34。
[0022]如果在判定块404处确定增量和减量信号不都为HI,方法前进至判定块412,其中确定增量和减量信号是否都为LO。如果增量和减量信号并非都为LO,不在处理器14上执行功率状态调节,并且方法前进至块400,其中重新检查和/或监控定时器34。如果在块412处确定增量和减量信号都为LO,方法前进至判定块414,其中确定处理器14是否在其最低的可用功率状态。如果处理器14在其最低的可用功率状态,不在处理器14上执行功率状态调节,并且方法前进至块400,其中重新检查和/或监控定时器34。如果在判定块414处确定处理器14还未在其最低的可用功率状态,方法前进至块416,其中处理器14的功率状态递减一个状态或等级(例如,从P1到P2)。方法前进至块410,其中初始化和/或以其它方式启动定时器34。
[0023]因此,在操作中,基于如平均OCP信号所表明(也如比较器74和76输出的增量和减量信号的HI或LO条件所表明)的处理器14的减速等级,处理器14的功率状态递增或递减一个或多个等级以控制计算机设备12的功率消耗。因此,系统10的实施例提供利用减速和功率状态调节来控制从适配器20和/或电池22吸取的功率的可变的处理器控制。应当理解的是,在上述方法中,可能省略了以不同于图4所示的顺序的顺序来完成的,或者同时执行的特定功能。并且,应当理解的是,可以改变图4所示的方法,以涵盖在本说明书中的其它部分中描述的本发明的任何其它特征或方面。另外,实施例可在软件中实施,并且可适合于在不同的平台和操作系统上运行。