English:
[0001] Battery powered devices often include electronic safeguards to prevent damage to the internal electronics in the event of reverse battery installation, accidental short circuiting, or other inappropriate operation. Such electronic safeguards ensure that any reverse current flow and reverse bias voltage is low enough to prevent damage to either the battery itself or the device's internal electronics. One front-end component that manufacturers often employ to effect reverse battery protection is the series diode. In higher power systems (e.g., two amps or higher), the voltage drop across a series diode can cause excessive amounts of power dissipation. More recently, field-effect transistors have been employed to implement reverse battery protection. The most recent metal-oxide-semiconductor field-effect transistors (MOSFETs) have very low resistance and are therefore ideal for providing reverse current protection with minimal loss. However, the use of a FET to protect the battery during reverse current situations involves the use of a controller to regulate the voltage drop across the FET, and the controller itself consumes marginal power.
[0004] Described examples include a method of controlling a transistor including first, second and third terminals, in which a voltage level at the first terminal controls in part a current flow from the second terminal to the third terminal. According to the method, a voltage existing across the second and third terminals of the transistor is received. The voltage existing across the second and third terminals of the transistor is used to power a control circuit. The control circuit generates a control voltage based on the voltage existing across the second and third terminals of the transistor. The control circuit provides the control voltage to the first terminal of the transistor.
[0005] FIG. 1 is a schematic circuit diagram of a circuit that includes a battery powering a load and that employs a transistor serving as reverse-current protection.
[0006] FIG. 2 is a schematic circuit diagram of an NFET transistor and an associated controller.
[0007] FIG. 3 is a flow chart representing a method of controlling a transistor.
[0008] Example embodiments are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this disclosure.
[0010] FIG. 1 is a schematic circuit diagram of a circuit 100 that includes a battery 110 powering a load 120 and that employs a transistor 130 serving as reverse-current protection. FIG. 1 shows an n-channel FET (NFET) 130 in the power path of the circuit 100, but a p-channel FET could be employed instead of the NFET, with corresponding changes in circuit operation. The reverse-current protection transistor 130 can also be implemented with other transistor types besides field-effect transistors. In circuit 100, the body diode 135 of NFET 130 is oriented in the direction of normal current flow. The NFET 130 allows current flow in the forward direction, i.e., from the source 140 to the drain 145 of NFET 130 (i.e., from the battery 110 to the load 120), and blocks current in the reverse direction, i.e., from the drain 145 to the source 140 of NFET 130. A controller 160 receives inputs from the source 140 and the drain 145 of the NFET 130. The controller 160 generates a control signal, or gate driver signal, based on the drain-to- source voltage Vds- The controller 160 provides the gate driver signal to the gate 150 of the NFET 130. In this way, the controller 160 regulates the drain-to-source voltage VdSin a control loop. In an illustrative aspect of example embodiments, the controller 160 also receives its power from the voltage drop across the NFET 130, i.e., from the drain-to-source voltage VdS.
[0011] FIG. 2 is a schematic circuit diagram of an NFET transistor 230 and an associated controller 260. In FIG. 2, NFET 230 corresponds to NFET 130 of FIG. 1, and controller 260 corresponds to controller 160 of FIG. 1. The controller 260 includes a voltage conversion circuit 265, an oscillator 270, a reservoir capacitor 275, a differential amplifier 280, and an offset voltage source 285. The controller 260 receives its power from the voltage drop across the NFET 230, i.e., from the drain-to-source voltage VdS. In an illustrative embodiment, the controller 260 receives all of its power from the drain-to-source voltage VdS, without receiving any additional power from other power sources. The voltage conversion circuit 265 receives the drain-to-source voltage VdSof the NFET 230 and converts it to a voltage level appropriate for powering components of the controller, such as differential amplifier 280. In certain illustrative embodiments, the voltage converter 265 includes a capacitive charge pump circuit, while in other illustrative embodiments, the voltage conversion circuit 265 includes an inductive voltage boost circuit. The oscillator 270 receives the drain-to-source voltage VdSof the NFET 230, generates an oscillating signal, and provides the oscillating signal to the voltage conversion circuit 265 to drive the charge pump circuit. The oscillating signal generated by the oscillator 270 can be a square wave, a pulsed DC signal, or any other type of oscillating signal. The reservoir capacitor 275 stores the supply voltage generated by the voltage conversion circuit 265. The reservoir capacitor 275 can be either internal to the controller 260 or can be external. The controller 260 can be implemented in some cases without the reservoir capacitor. The supply voltage generated by the voltage converter 265 is used to power a control circuit, represented in FIG. 2 by the differential amplifier 280 and the offset voltage source 285, that regulates the drain-to-source voltage Vdsof the NFET 230 by controlling the voltage of a control signal provided to the gate 250 of the NFET 230 in a control loop based on the drain-to-source voltage VdS. In the illustrative embodiment of FIG. 2, the voltage of the offset voltage source 285 is added to the source voltage of the NFET 230, and the summed voltage signal is provided to the non-inverting input of the differential amplifier 280. The voltage level of the offset voltage source 285 corresponds to a target voltage level of the drain-to-source voltage VdS. The drain voltage of the NFET 230 is provided to the inverting input of the differential amplifier 280. The output of the differential amplifier 280 is provided to the gate 250 of the NFET 230. In this way, the control circuit represented by the differential amplifier 280 and the offset voltage source 285 works to maintain the drain-to-source voltage VdSat a voltage level substantially corresponding to the target voltage represented by the offset voltage source 285.
[0012] In operation, at startup, because of the body diode orientation of the N-channel FET 230, there will be initial current flowing through the body diode 235 if the load 120 is on. Therefore, even if the controller 260 is not powered, this will not interrupt the flow of current. However, as the current starts to flow through the body diode 235, a voltage will be generated across the source 240 and drain 245 of the NFET 230, specifically the voltage of a PN junction. This voltage can vary from NFET to NFET, and across temperatures, but nominally may be around 0.5V - 0.7V. This voltage is also seen by the controller 260, across the source terminal 240 and the drain terminal 245 of the NFET 230. Using this voltage, the controller 260 will have enough voltage to turn on and startup its own circuitry, namely the voltage conversion circuit 265 and the oscillator 270.
[0013] The voltage conversion circuit 265 uses the body voltage, i.e., the drain-to-source voltage Vds(0.5V - 0.7V) to generate an internal supply voltage. In the illustrative embodiment of FIG. 2, this internal supply voltage is shown to be approximately 5 V, but this voltage level is merely illustrative, and other internal supply voltage levels can be used. In an illustrative embodiment, the voltage converter 265 generates anywhere from approximately 0.5 mWatts to 10 mWatts. The controller 260 then enters the regulation mode, in which it varies the gate voltage of the NFET 230 in a controlled loop to keep the drain-to-source voltage VdSat the desired target level. In the illustrative embodiment of FIG. 2, this target voltage is shown to be
[0014] The regulated source-to-drain voltage VdSof the FET 230 is dependent on the threshold voltage (Vthreshoid) of the NFET device used. Therefore, the regulation self-adjusts when Vthreshoid fluctuates across temperature by varying the gate voltage to match the VdS.
[0015] In the illustrative embodiment of FIG. 2, the controller 260 is shown to include a single voltage conversion circuit 265. In an alternative embodiment, the controller 260 may include two separate voltage conversion circuits to accommodate the two different VdSlevels that exist at start-up and in the regulation mode. For example, the controller 260 can include a first voltage conversion circuit configured to receive a VdSof 0.5V - 0.7V at start-up and convert the VdSto the level of the internal supply voltage (e.g., 5V), and a second voltage conversion circuit configured to receive a VdSof approximately 50mV in the regulation mode and convert that VdSto the level of the internal supply voltage. Alternatively a single voltage conversion circuit 265 can be figured to operate at the VdSlevels of both the start-up and regulation modes. Similarly, while FIG. 2 shows a single oscillator 270, in an alternative embodiment the controller 260 can include two separate oscillators to accommodate the two different VdSlevels that exist at start-up and in the regulation mode.
[0016] FIG. 3 is a flow chart representing a method of controlling a transistor including first, second and third terminals, in which a voltage level at the first terminal controls in part a current flow from the second terminal to the third terminal. At step 300, a voltage existing across the second and third terminals of the transistor is received. At step 310, the voltage existing across the second and third terminals of the transistor is used to power a control circuit. At step 320, the control circuit generates a control voltage based on the voltage existing across the second and third terminals of the transistor. At step 330, the control circuit provides the control voltage to the first terminal of the transistor.
[0017] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

中文:
[0001]电池供电设备通常包括电子保护设施以防止万一反向电池安装、意外短路或其他不当操作对内部电子器件的损害。这样的电子保护设施确保任何反向电流和反向偏压足够低以防止对电池本身或设备的内部电子器件的损害。制造商通常用来实现反向电池保护的一个前端组件是串联二极管。在较高的功率系统(例如,两安培或更高)中,串联二极管两端的电压降可能导致过量的功耗。最近,场效应晶体管已经被用来实施反向电池保护。最近的金属氧化物半导体场效应晶体管(MOSFET)具有非常低的电阻并且因此非常适合以最小的损耗提供反向电流保护。然而,在反向电流情况期间使用FET来保护电池包括使用控制器来调节FET两端的电压降,并且控制器本身消耗微小的功率。
[0004]所描述的示例包括一种控制具有第一、第二和第三端子的晶体管的方法,其中在第一端子处的电压水平部分控制从第二端子流到第三端子的电流。根据该方法,接收存在于晶体管的第二和第三端子两端的电压。存在于晶体管的第二和第三端子两端的电压被用来为控制电路供电。控制电路基于存在于晶体管的第二和第三端子两端的电压产生控制电压。控制电路向晶体管的第一端子提供该控制电压。
[0005]图1是包括为负载供电的电池并且使用用于反向电流保护的晶体管的电路的示意电路图。
[0006]图2是NFET晶体管和相关的控制器的示意电路图。
[0007]图3是表示控制晶体管的方法的流程图。
[0008]参照附图描述示例性实施例,其中相同的附图标记被用来表示相似或等效的元件。一些行为或事件可以以不同的顺序发生和/或与其他行为或事件并行地发生。此外,可能不需要一些示出的行为或事件来实施根据本公开的方法。
[0010]图1是包括为负载120供电的电池110和使用用于反向电流保护的晶体管130的电路100的示意电路图。图1示出在电路100的电源路径中的n沟道FET(NFET)130,但是也可以使用p沟道FET来代替NFET,其中电路操作也相应地改变。除了场效应晶体管之外,反向电流保护晶体管130也可以用其他晶体管类型来实施。在电路100中,NFET 130的体二极管135被定向在正常的电流的方向。NFET 130允许正向方向上的电流,即,从NFET 130的源极140到漏极145(即,从电池110到负载120),并且阻止反向方向上的电流,即,从NFET 130的漏极145到源极140。控制器160接收来自NFET 130的源极140和漏极145的输入。控制器160基于漏源电压Vds产生控制信号或栅极驱动信号。控制器160向NFET 130的栅极150提供栅极驱动信号。以这种方式,控制器160在控制回路中调节漏源电压Vds。在示例实施例的说明性方面中,控制器160也从NFET 130两端的电压降,即,从漏源电压Vds接收其功率。
[0011]图2是NFET晶体管230和相关的控制器260的示意电路图。在图2中,NFET 230对应于图1中的NFET 130,并且控制器260对应于图1中的控制器160。控制器260包括电压转换电路265、振荡器270、存储电容器275、差分放大器280,以及偏置电压源285。控制器260从NFET230两端的电压降,即,从漏源电压Vds接收其功率。在说明性性实施例中,控制器260从漏源电压Vds接收其所有功率,而不从其他电源接收任何额外的功率。电压转换电路265接收NFET230的漏源电压Vds并且将其转换成适合为控制器的组件(例如差分放大器280)供电的电压水平。在某些说明性实施例中,电压转换器265包括电容式电荷泵电路,而在其他说明性实施例中,电压转换器265包括感应式升压电路。振荡器270接收NFET 230的漏源电压Vds、产生振荡信号,并且向电压转换电路265提供振荡信号以驱动电荷泵电路。由振荡器270产生的振荡信号可以是方波、脉冲DC信号,或任何其他类型的振荡信号。存储电容器275储存由电压转换电路265产生的电源电压。存储电容器275可以在控制器260的内部或者可以在外部。控制器260可以在没有存储电容器的一些情况下被实施。由电压转换器265产生的电源电压被用来为在图2中由差分放大器280和偏置电压源285表示的控制电路供电,该控制电路通过在控制回路中基于漏源电压Vds控制被提供给NFET 230的栅极250的控制信号的电压来调节NFET 230的漏源电压Vds。在图2中的说明性实施例中,偏置电压源285的电压被添加到NFET 230的源极电压,并且求和的电压信号被提供给差分放大器280的非反相输入端。偏置电压源285的电压水平对应于漏源电压Vds的目标电压水平。NFET 230的漏极电压被提供给差分放大器280的反相输入端。差分放大器280的输出被提供给NFET 230的栅极250。以这种方式,由差分放大器280和偏置电压源285表示的控制电路用于将漏源电压Vds维持在基本上对应于由偏置电压源285表示的目标电压的电压水平。
[0012]在操作中,在启动时,因为n沟道FET 230的体二极管取向,如果负载120接通则将有流过体二极管235的初始电流。因此,即使控制器260没有被供电,这也不会中断电流的流动。然而,当电流开始流过体二极管235时,将在NFET 230的源极240和漏极245两端产生电压,具体为PN结的电压。这个电压可以从NFET到NFET以及跨温度变化,但标称上可能大约为0.5V-0.7V。在NFET 230的源极端子240和漏极端子245两端,控制器260也可以看到该电压。使用这个电压,控制器260将有足够的电压导通并启动它自己的电路,即电压转换电路265和振荡器270。
[0013]电压转换电路265使用体电压,即,漏源电压Vds(0.5V-0.7V)来产生内部电源电压。在图2的说明性实施例中,该内部电源电压被显示为大约5V,但是这个电压水平仅仅是说明性的,并且可以使用其他内部电源电压水平。在一个说明性实施例中,电压转换器265产生从大约0.5mW至10mW的任何功率。控制器260然后进入调节模式,其中它在受控回路中改变NFET 230的栅极电压以将漏源电压Vds维持在期望目标水平。在图2的说明性实施例中,目标电压被显示为50mV,但是这个电压水平仅仅是说明性的,并且可以使用其他目标Vds水平。在一个说明性实施例中,控制器260将栅极电压维持在恰好足够高以给出足够的Vds从而保持电压转换电路265运行并产生内部电源电压(5V)的水平。如上所述,该内部电源电压被用来为差分放大器280和/或其他控制电路供电。
[0014]NFET 230的经调节的源漏电压Vds取决于所使用的NFET器件的阈值电压(Vthreshold)。因此,当Vthreshold跨温度波动时该调节通过改变栅极电压来进行自调整以匹配Vds。
[0015]在图2的说明性实施例中,控制器260被显示为包括单个电压转换电路265。在替代实施例中,控制器260可以包括两个独立的电压转换电路以适应在启动时和在调节模式中存在的两个不同的Vds水平。例如,控制器260可以包括被配置为在启动时接收0.5V-0.7V的Vds并且将该Vds转换成内部电源电压(即,5V)的水平的第一电压转换电路,和被配置为在调节模式中接收大约50mV的Vds并且将Vds转换成内部电源电压的水平的第二电压转换电路。可替换地,单个电压转换电路265可以被配置在启动和调节模式两者的Vds水平下工作。类似地,尽管图2显示单个振荡器270,然而在替代实施例中,控制器260可以包括两个独立的振荡器以适应在启动时和在调节模式中存在的两个不同的Vds水平。
[0016]图3是表示控制包括第一、第二和第三端子的晶体管的方法的流程图,其中在第一端子处的电压水平部分控制从第二端子流到第三端子的电流。在步骤300处,接收存在于晶体管的第二和第三端子两端的电压。在步骤310处,使用存在于晶体管的第二和第三端子两端的电压为控制电路供电。在步骤32 0处,控制电路基于存在于晶体管的第二和第三端子两端的电压产生控制电压。在步骤330处,控制电路向晶体管的第一端子提供控制电压。
[0017]在权利要求的范围内,所描述的实施例的修改时可能的,并且其他实施例时可能的。