English:
[0002] Shrinking semiconductor integrated circuit feature sizes have placed increasing challenges on semiconductor integrated circuit design. For example, minimum feature sizes of high density memory cells are frequently less than corresponding feature sizes of peripheral circuits. As a result, leakage current in unselected memory cells (ILEAK) may adversely affect correct sensing of a selected memory cell on a common bit line. This is particularly true of nonvolatile memories such as Flash EEPROM and ROM memories. However, this undesirable leakage current may also adversely affect standby current of volatile SRAM memories. Moreover, undesirable leakage current may compromise operation of both embedded memories in System on Chip (SoC) applications and stand-alone memories.
[0003] In a first embodiment, a memory array has a word line and a bit line. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line
[0005] FIG. 1 is a diagram of a memory circuit according to example embodiments.
[0006] FIG. 2 is a simplified circuit diagram of memory blocks 106 and 108 of FIG. 1.
[0007] FIG. 3 is a circuit diagram of source line (SL) bias circuits 104 and 110 of FIG. 1 coupled to respective memory blocks 106 and 108.
[0008] FIG. 4 is a circuit diagram showing operation of memory sector 102 of FIG. 1 during a memory read operation according to example embodiments.
[0009] FIG. 5 is a timing diagram showing operation of memory sector 102 of FIG. 4 during the memory read operation.
[0010] Example embodiments reduce leakage current in unselected memory cells for both nonvolatile and volatile memory systems.
[0011] FIG. 1 is a diagram of a memory circuit 100 according to example embodiments. The memory circuit, often referred to as a macro, may be used for a System on a Chip (SoC), embedded memory, or stand alone memory applications. The diagram shows four memory sectors 102, 120, 130, and 140. Additional memory sectors may be included as indicated by ellipses. Each memory sector is substantially the same, so only memory sector 102 will be described in detail. In the following discussion, the same reference numerals are used to describe substantially the same circuit elements. Memory sector 102 includes memory blocks 106 and 108 and respective source line bias circuits 104 and 110 as will be described in detail. Each memory block includes N word lines (WL) and M bit lines (BL), where N and M are positive integers. Each word line corresponds to a respective row of memory cells, and each bit line corresponds to a respective column of memory cells. The choice of N and M depends on the memory requirements for a particular application. For example, N may be 256, 512, or other value and may include additional rows of memory cells for redundancy. Correspondingly M may be 256, 512, 1024, or other value and may include other columns of memory cells for redundancy or parity bits for error correction (ECC) memory. For example, N may be 256 or 512 and M may 2304, where 256 columns are dedicated to ECC parity bits
[0012] The memory circuit of FIG. 1 also includes row decode and drive circuit 114 to select appropriate word lines in response to applied address signals. A source line (SL) decode circuit 116 decodes applied address signals to control source line bias circuits 104 and 110 and may include corresponding control logic. High voltage drive circuit 118 decodes and applies high voltage signals to selected control gates (CG) and erase gates (EG) for programming and erasing memory cells of blocks 106 and 108. Circuit 112 applies write drive (WRDRIVE) signals to write date to the memory cells. Circuit 112 also includes an 8: 1 multiplex circuit to selectively couple a local bit line (LBL) signal to a global bit line (GBL). The global bit line is selectively coupled to a sense amplifier in circuit 122 by global bit line multiplexer GMUX. After amplification, data signals are subsequently multiplexed by a read multiplex (RMUX) circuit to input/output (I/O) terminals of the SoC.
[0013] FIG. 2 is a simplified circuit diagram of memory blocks 106 and 108 of FIG. 1. Block 106 is coupled to receive word lines WL0 through WLN/2-1 and control gate leads CG0 through CGN/2- 1. Block 106 is also coupled to receive bit lines BL0 through BLM-1. Block 106 includes a memory cell formed at each intersection of a respective word line and bit line such as the memory cell formed by transistors 200 and 202 and the memory cell formed by transistors 204 and 206. Transistor 202 provides access to floating gate transistor 202. Likewise, transistor 204 provides access to floating gate transistor 206. Transistors 202 and 206 have control gates coupled to receive signals CGO and CGN/2- 1, respectively. Transistors 202 and 206 also have respective floating erase gates (EG) indicated by dashed lines. The source of each floating gate transistor of block 106 is coupled to source line SL104 from SL BIAS circuit 104.
[0014] Block 108 is similar to block 106 and is coupled to receive word lines WLN/2 through WLN-1 and control gate leads CGN/2 through CGN-1. Block 108 is also coupled to receive bit lines BL0 through BLM-1, which are shared with block 106. A memory cell is formed at each intersection of a respective word line and bit line of block 108 such as the memory cell formed by transistors 208 and 210 and the memory cell formed by transistors 212 and 214. Transistor 208 provides access to floating gate transistor 210. Likewise, transistor 212 provides access to floating gate transistor 214. Transistors 210 and 214 have control gates coupled to receive signals CGN/2 and CGN-1, respectively. Transistors 210 and 214 also have respective floating erase gates (EG) indicated by dashed lines. The source of each floating gate transistor of block 108 is coupled to source line SL110 from SL BIAS circuit 110.
[0015] FIG. 3 is a circuit diagram of source line (SL) bias circuits 104 and 110 of FIG. 1 coupled to respective memory blocks 106 and 108. In the following description, transistor sizes are specified as width/length (W/L) in units of micrometers. These transistor sizes are examples and may vary with different values of N and M (FIG. 1). SL bias circuit 104 includes n-channel transistor 300 (3.9/0.4) connected in series with n-channel transistor 302 (1.95/0.07) between supply voltage leads VDD (horizontal line) and VSS (small triangle). SL bias circuit 104 also includes n-channel transistor 304 (3.0/0.07) connected in series with n-channel transistor 306 (1.0/1.0) between source line SL104 and supply voltage lead VSS. A common terminal 301 of transistors 300 and 302 is connected to a common terminal of transistors 304 and 306. SL bias circuit 110 is similar to SL bias circuit 104 and includes n-channel transistor 310 (3.9/0.4) connected in series with n-channel transistor 312 (1.95/0.07) between supply voltage leads VDD and VSS. SL bias circuit 110 also includes n-channel transistor 314 (3.0/0.07) connected in series with n-channel transistor 316 (1.0/1.0) between source line SLl lO and supply voltage lead VSS. A common terminal 311 of transistors 310 and 312 is connected to a common terminal of transistors 314 and 316.
[0016] Operation of SL bias circuit 104 is similar to operation of SL bias circuit 110, so only operation of SL bias circuit 104 will be described in detail. Transistor 300 is coupled to receive control signal VSF104, and transistor 302 is coupled to receive complementary control signal VSF104 OFF. When memory sector 102 is not accessed, control signals VSF104 and VSF104 OFF are low and high, respectively. Thus, transistor 300 is off, transistor 302 is on, and lead 301 is driven to supply voltage VSS. Control signal VRD BUF is held high, so transistors 304 and 306 are both on, and transistor 304 drives SL104 to supply voltage VSS at lead 301. In the same manner, control signals VSF110 and VSF110 OFF are low and high, respectively, and transistor 314 drives SLl lO to supply voltage VSS at lead 311.
[0017] When a memory cell of block 108 is accessed in a read mode, control signals VSF110 and VSF110 OFF remain low and high, respectively, and SLl lO remains at supply voltage VSS. However, control signals VSF104 and VSF104 OFF transition to high and low levels, respectively. Thus, transistor 300 is on and transistor 302 is off. Transistor 300 acts as a source follower and drives lead 301 to an n-channel transistor threshold voltage below supply voltage VDD (VDD - Vtn). Control signal VRD BUF remains high, so transistors 304 and 306 are both on. Thus, transistor 304 drives SL104 to VDD - Vtn. Transistor 306 is a relatively high resistance transistor and acts as a bleeder or keeper device to assure lead 301 does not rise above VDD - Vtn.
[0018] SL bias circuits of example embodiments are highly advantageous for several reasons. First, access time to a memory cell in block 108 is not compromised, because SLl lO is held at supply voltage VSS during a read operation. Second, SL104 is raised to VDD - Vtn when the memory cell in block 108 is accessed. Thus, memory cells in block 106 connected to the same bit line as the accessed memory cell of block 108 have greatly reduced leakage current. A typical read current of an erased memory cell is approximately 25 μΑ. However, leakage of unselected memory cells on a selected conventional bit line may be as much as 16 μΑ/kbit. This excessive leakage current adversely affects the signal-to-noise ratio (SNR) of data from an accessed memory cell. Raising a source line of unselected memory cells on a selected bit line by as little as 200 mV above supply voltage VSS will reduce leakage current by approximately two orders of magnitude (100 x), thereby greatly improving the SNR of the accessed memory cell. Third, source follower transistor 300 quickly drives lead 301 to VDD - Vtn, so leakage current is reduced before sensing data from the accessed memory cell. Fourth, transistor 302 assures that lead 301 will not rise to a level greater than VDD - Vtn to adversely affect reliability. Finally, the SL bias circuits of example embodiments produce no static power dissipation. Moreover, SL bias circuits such as SL bias circuit 104 may include several circuits such as transistors 300 through 306, wherein each individual SL bias circuit is decoded by appropriate column address signals. Thus, source line capacitance driven by each SL bias circuit may be limited to memory cells of a few respective bit lines of a respective sector.
[0019] FIG. 4 is a circuit diagram showing operation of memory sector 102 of FIG. 1 during a memory read operation according to example embodiments. Operation of the circuit is described with reference to the timing diagram of FIG. 5 for a read operation of the memory cell at the intersection of WL0and BL0. In the following discussion, transistors 400 and 402 represent all lumped memory cells in block 106 connected to BL0. Transistors 404 and 406 represent all lumped memory cells in block 108 connected to BL0. Initially, VSF104 and VSF1 10 are low (0.0 V) and VSF104 OFF and VSF1 10 OFF are high (1.2 V). VRD BUF is high (3.0 V), so transistors 304, 306, 314, and 316 are on. Source lines SL104 and SLn0, therefore, are held at VSS (0.0 V) by transistors 304 and 314, respectively. At time tO, VSF110 goes high (1.2 V), and VSF110 OFF goes low (0.0 V). As described hereinabove, this drives SLn0to VDD - Vtn (0.6 V). As a result, current ILEAK through memory cell 404/406 is substantially zero. At time tl, word line WL0goes high (1.3 V) and turns on access transistor 200 (FIG. 2). As a result, current IREAD flows through memory cell 200/202, and current ILEAK (N/2-1) flows through the unselected memory cells of block 106 connected to bit line BL0. For large N, therefore, leakage current due to unselected memory cells connected to bit line BL0is advantageously reduced by half. Bit line BL0is selectively coupled to one input terminal of sense amplifier 412 by local bit line multiplex circuit 408 and global bit line multiplex circuit 410. Reference current source 414 is coupled to the other input terminal of sense amplifier 412. Sense amplifier 412 is initially precharged high, so the differential current at the input terminals produces a differential input voltage. At time t2, sense amplifier enable signal SAEN goes high (1.2 V) to amplify the difference voltage. Read multiplex circuit 416 selectively applies the amplified difference voltage (DATA) to output circuit 122.
[0020] As described hereinabove, SL bias circuits of example embodiments substantially improve the SNR at the sense amplifier. For example, if 256 memory cells are on BLO (N = 256), in each of blocks 106 and 108, leakage current is reduced from 8 μΑ to 4 μΑ through BLO. Read current remains approximately 25 μΑ, so net current at the sense amplifier is 21 μΑ rather than 17 μΑ. This is a 24% improvement in signal strength at the sense amplifier. Further SNR improvement is possible by increasing the number of blocks per sector, thereby increasing the number of source lines per bit line. For example, if four blocks are in a sector with 128 memory cells on each source line, leakage current is reduced from 8 μΑ to 2 μΑ through BLO. Read current remains approximately 25 μΑ, so net current at the sense amplifier is 23 μΑ rather than 17 μΑ. This is a 35% improvement in signal strength at the sense amplifier.
[0021] Other circuit components may be used to increase the source line voltage of unselected memory cells on a selected bit line. Moreover, example embodiments are equally applicable to other memory circuits such as read only memory (ROM) circuits. Example embodiments may also be applied to static random access memory (SRAM) circuits or various logic circuits to reduce standby current.
[0022] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

中文:
[0002]缩小的半导体集成电路特征尺寸对半导体集成电路设计提出了越来越多的挑战。例如,高密度存储器单元的最小特征尺寸通常小于外围电路的对应特征尺寸。结果,未选择的存储器单元中的泄漏电流(ILEAK)可能不利地影响对公共位线上的所选择的存储器单元的正确感测。对于诸如快闪EEPROM和ROM存储器的非易失性存储器尤其如此。然而,这种不希望的泄漏电流也可能不利地影响易失性SRAM存储器的待机电流。此外,不期望的泄漏电流可能损害片上系统(SoC)应用和独立存储器两者中的嵌入式存储器的操作。
[0003]在第一实施例中,存储器阵列具有字线和位线。存储器阵列的多个存储器单元中的每个具有连接到位线的第一端子和在第一端子与相应的第二端子之间的电流路径。多个存储器单元中的第一存储器单元具有第二端子,其经耦合以在被字线选择时接收第一电源电压。多个存储器单元中的第二存储器单元具有第二端子,其经耦合以在第一存储器单元被字线选择时接收与第一电源电压不同的电压。
[0005]图1是根据示例实施例的存储器电路的图。
[0006]图2是图1的存储器块106和108的简化电路图。
[0007]图3是耦合到相应的存储器块106和108的图1的源极线(SL)偏置电路104和110的电路图。
[0008]图4是示出根据示例实施例的在存储器读取操作期间图1的存储器扇区102的操作的电路图。
[0009]图5是示出在存储器读取操作期间图4的存储器扇区102的操作的时序图。
[0010]示例实施例减少了非易失性和易失性存储器系统两者中未选择的存储器单元中的泄漏电流。
[0011]图1是根据示例实施例的存储器电路100的图。存储器电路(通常称为宏)可用于片上系统(SoC)、嵌入式存储器或独立存储器应用。该图示出了四个存储器扇区102、120、130和140。可以包括附加的存储器扇区,如椭圆(省略号)所说明。每个存储器扇区基本相同,因此将仅详细描述存储器扇区102。在下面的讨论中,相同的附图标记用于描述基本相同的电路元件。存储器扇区102包括存储器块106和108以及相应的源极线偏置电路104和110,如将详细描述的。每个存储器块包括N个字线(WL)和M个位线(BL),其中N和M是正整数。每个字线对应于相应的一行存储器单元,并且每个位线对应于相应的一列存储器单元。N和M的选择取决于特定应用的存储器要求。例如,N可以是256、512或其他值,并且可以包括用于冗余的存储器单元的附加行。相应地,M可以是256、512、1024或其他值,并且可以包括用于冗余或用于纠错(ECC)存储器的奇偶校验位的存储器单元的其他列。例如,N可以是256或512并且M可以是2304,其中256列专用于ECC奇偶校验位。
[0012]图1的存储器电路还包括行解码和驱动电路114,以响应于所施加的地址信号而选择适当的字线。源极线(SL)解码电路116对所施加的地址信号进行解码以控制源极线偏置电路104和110,并且源极线(SL)解码电路116可以包括对应的控制逻辑。高电压驱动电路118对所选择的控制栅极(CG)和擦除栅极(EG)进行解码并施加高电压信号,以编程和擦除块106和108的存储器单元。电路112施加写入驱动(WRDRIVE)信号以将日期写入存储器单元。电路112还包括8:1多路复用电路,以选择性地将局部位线(LBL)信号耦合到全局位线(GBL)。全局位线通过全局位线多路复用器GMUX选择性地耦合到电路122中的感测放大器。在放大之后,数据信号随后由读取多路复用(RMUX)电路多路复用到SoC的输入/输出(I/O)端子。
[0013]图2是图1的存储器块106和108的简化电路图。块106经耦合以接收字线WL0至WLN/2-1和控制栅极引线CG0至CGN/2-1。块106还经耦合以接收位线BL0至BLM-1。块106包括形成在相应的字线和位线的每个交叉点处的存储器单元,例如由晶体管200和202形成的存储器单元以及由晶体管204和206形成的存储器单元。晶体管202提供对浮栅晶体管202的访问。同样,晶体管204提供对浮栅晶体管206的访问。晶体管202和206具有控制栅极,其经耦合以分别接收信号CG0和CGN/2-1。晶体管202和206还具有由虚线指示的相应浮动擦除栅极(EG)。块106的每个浮栅晶体管的源极从源极线偏置(SL BIAS)电路104耦合到源极线SL104。
[0014]块108类似于块106,并且经耦合以接收字线WLN/2至WLN-1和控制栅极引线CGN/2至CGN-1。块108还经耦合以接收与块106共享的位线BL0至BLM-1。存储器单元形成在块108的相应的字线和位线的每个交叉点处,例如由晶体管208和210形成的存储器单元以及由晶体管212和214形成的存储器单元。晶体管208提供对浮栅晶体管210的访问。同样,晶体管212提供对浮栅晶体管214的访问。晶体管210和214具有控制栅极,其经耦合以分别接收信号CGN/2和CGN-1。晶体管210和214还具有由虚线指示的相应的浮动擦除栅极(EG)。块108的每个浮栅晶体管的源极从SL BIAS电路110耦合到源极线SL110。
[0015]图3是耦合到相应的存储器块106和108的图1的源极线(SL)偏置电路104和110的电路图。在以下描述中,晶体管尺寸被指定为以微米为单位的宽度/长度(W/L)。这些晶体管尺寸是示例,并且可以随N和M(图1)的不同值而变化。SL偏置电路104包括在电源电压引线VDD(水平线)和VSS(小三角形)之间与n沟道晶体管302(1.95/0.07)串联连接的n沟道晶体管300(3.9/0.4)。SL偏置电路104还包括在源极线SL104和电源电压引线VSS之间与n沟道晶体管306(1.0/1.0)串联连接的n沟道晶体管304(3.0/0.07)。晶体管300和302的公共端子301连接到晶体管304和306的公共端子。SL偏置电路110类似于SL偏置电路104并且包括在电源电压引线VDD和VSS之间与n沟道晶体管312(1.95/0.07)串联连接的n沟道晶体管310(3.9/0.4)。SL偏置电路110还包括在源极线SL110和电源电压引线VSS之间与n沟道晶体管316(1.0/1.0)串联连接的n沟道晶体管314(3.0/0.07)。晶体管310和312的公共端子311连接到晶体管314和316的公共端子。
[0016]SL偏置电路104的操作类似于SL偏置电路110的操作,因此将仅详细描述SL偏置电路104的操作。晶体管300经耦合以接收控制信号VSF104,并且晶体管302经耦合以接收补偿控制信号VSF104_OFF。当未访问存储器扇区102时,控制信号VSF104和VSF104_OFF分别为低和高。因此,晶体管300截止,晶体管302导通,并且引线301被驱动至电源电压VSS。控制信号VRD_BUF保持为高,因此晶体管304和306都导通,并且晶体管304在引线301处驱动SL104至电源电压VSS。以相同的方式,控制信号VSF110和VSF110_OFF分别为低和高,并且晶体管314在引线311处驱动SL110至电源电压VSS。
[0017]当以读取模式访问块108的存储器单元时,控制信号VSF110和VSF110_OFF分别保持为低和高,并且SL110保持在电源电压VSS。然而,控制信号VSF104和VSF104_OFF分别转变为高电平和低电平。因此,晶体管300导通,并且晶体管302截止。晶体管300用作源极跟随器并将引线301驱动到比电源电压VDD低的n沟道晶体管阈值电压(VDD-Vtn)。控制信号VRD_BUF保持高,因此晶体管304和306都导通。因此,晶体管304将SL104驱动到VDD-Vtn。晶体管306是相对高电阻的晶体管,并且用作分压器(bleeder)或保持器(keeper)器件以确保引线301不会升高到VDD-Vtn以上。
[0018]出于若干原因,示例实施例的SL偏置电路非常有利。首先,对块108中的存储器单元的访问时间不受影响,因为在读取操作期间SL110保持在电源电压VSS。其次,当访问块108中的存储器单元时,SL104升高到VDD-Vtn。因此,块106中的存储器单元(其连接到的位线与块108中的被访问存储器单元的位线相同)具有极大地减少的泄漏电流。擦除的存储器单元的典型读取电流约为25μA。然而,在所选择的传统位线上的未选择的存储器单元的泄漏可能高达16μA/kbit。该过大的泄漏电流不利地影响来自所访问的存储器单元的数据的信噪比(SNR)。将所选择的位线上的未选择的存储器单元的源极线提升至比电源电压VSS仅仅高200mV,将使泄漏电流减少大约两个数量级(100x),从而极大地改善所访问的存储器单元的SNR。第三,源极跟随器晶体管300快速地将引线301驱动到VDD-Vtn,因此在从所访问的存储器单元感测数据之前减少了漏电流。第四,晶体管302确保引线301不会上升到大于VDD-Vtn的电平从而不利地影响可靠性。最后,示例实施例的SL偏置电路不产生静态功耗。此外,诸如SL偏置电路104的SL偏置电路可以包括诸如晶体管300至306的若干电路,其中每个单独的SL偏置电路由适当的列地址信号解码。因此,由每个SL偏置电路驱动的源极线电容可以限于相应扇区的几个相应位线的存储器单元。
[0019]图4是示出根据示例实施例的在存储器读取操作期间图1的存储器扇区102的操作的电路图。参考图5的时序图描述针对在WL0和BL0的交叉点处的存储器单元的读取操作的电路的操作。在下面的讨论中,晶体管400和402表示连接到BL0的块106中的所有集总存储器单元。晶体管404和406表示连接到BL0的块108中的所有集总存储器单元。最初,VSF104和VSF110为低(0.0V),并且VSF104_OFF和VSF110_OFF为高(1.2V)。VRD_BUF为高(3.0V),因此晶体管304、306、314和316导通。因此,源极线SL104和SL110分别由晶体管304和314保持在VSS(0.0V)。在时间t0,VSF110变高(1.2V),并且VSF110_OFF变低(0.0V)。如上所述,这将SL110驱动到VDD-Vtn(0.6V)。结果,通过存储器单元404/406的电流ILEAK基本上为零。在时间t1,字线WL0变高(1.3V)并导通访问晶体管200(图2)。结果,电流IREAD流过存储器单元200/202,并且电流ILEAK x(N/2-1)流过连接到位线BL0的块106的未选择的存储器单元。因此,对于大的N,由于连接到位线BL0的未选择的存储器单元引起的泄漏电流有利地减少了一半。位线BL0通过局部位线多路复用电路408和全局位线多路复用电路410选择性地耦合到感测放大器412的一个输入端子。参考电流源414耦合到感测放大器412的另一输入端子。感测放大器412最初被预充电为高,因此输入端子处的差分电流产生差分输入电压。在时间t2,感测放大器使能信号SAEN变高(1.2V)以放大差电压。读取多路复用电路416选择性地将放大的差电压(DATA)施加到输出电路122。
[0020]如上所述,示例实施例的SL偏置电路实质上改善了感测放大器处的SNR。例如,如果256个存储器单元在BL0上(N=256),则在块106和108中的每个中,通过BL0的泄漏电流从8μA减小到4μA。读取电流保持约25μA,因此感测放大器处的净电流为21μA而不是17μA。这是感测放大器处的信号强度的24%的提高。通过增加每个扇区的块的数量,从而增加每个位线的源极线数量,可以进一步改善SNR。例如,如果一个扇区中有四个块,其中每个源极线上有128个存储器单元,则通过BL0的泄漏电流从8μA减小到2μA。读取电流保持约25μA,因此感测放大器处的净电流为23μA而不是17μA。这是感测放大器处的信号强度的35%的提高。
[0021]可以使用其他电路组件来增加所选择的位线上的未选择的存储器单元的源极线电压。此外,示例实施例同样适用于其他存储器电路,例如只读存储器(ROM)电路。示例实施例还可以应用于静态随机存取存储器(SRAM)电路或各种逻辑电路以减少待机电流。
[0022]在权利要求的范围内,在所描述的实施例中修改是可能的,并且其他实施例也是可能的。