English:
[0002] Most microwave radar systems for low cost applications such as automotive collision warning systems use Doppler signal processing. The Doppler effect (or Doppler shift) is the change in frequency of a reflected wave (or other periodic event) for an observer moving relative to its target. Doppler signal processing may be used to separate reflecting signal from spurious noise and to measure moving target velocity. However, Doppler detection is challenging, because the return signal is from reflection not from a baseband station. Thus, a low noise Doppler detector is needed. The BARrier Injection Transit- Time (BARITT) diode, as a discrete device, has demonstrated high sensitivity in self-mixing microwave Doppler systems. However, discrete device systems have undesirably high fabrication cost and complexity for low cost applications.
[0003] In described examples, an integrated circuit includes a transistor and a vertically oriented BARITT diode. The BARITT diode has a source disposed proximate to a top surface of a substrate of the integrated circuit, a drift region disposed in semiconductor material of the substrate below the source, and a collector disposed in the semiconductor material of the substrate below the drift region. A dielectric isolation structure laterally surrounds the drift region, extending from the source to the collector.
[0004] FIG. 1 is a cross section of an example integrated circuit containing a BARITT diode.
[0005] FIG. 2 A through FIG. 2F are cross sections of the integrated circuit of FIG. 1, depicted in key stages of an example formation process.
[0006] FIG. 3 is a cross section of another example integrated circuit containing a BARITT diode.
[0007] FIG. 4 is a cross section of another example integrated circuit containing a BARITT diode.
[0008] FIG. 5 is a cross section of a further example integrated circuit containing a BARITT diode, formed on an SOI substrate.
[0009] FIG. 6 is a cross section of another example integrated circuit containing a BARITT diode.
[0010] The figures are not necessarily drawn to scale. Example embodiments can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring example embodiments. Some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with example embodiments.
[0011] A vertically oriented BARITT diode may be formed in an integrated circuit by forming a collector of a first conductivity type in silicon-based semiconductor material of a substrate of the integrated circuit at a depth of at least one micron below a top surface of the substrate, and forming a source directly over the collector, proximate to the top surface. The semiconductor material of the substrate between the source and the collector provides a drift region of the BARITT diode. A dielectric isolation structure laterally surrounds the drift region and extends from the source to the collector. The source may be a heavily doped region of the semiconductor material of the substrate, may include a Schottky barrier, and may include a silicon-germanium layer. The collector may be a buried layer in the substrate. The dielectric isolation structure may be field oxide.
[0012] Examples disclosed herein will describe BARITT diodes with p-type drift regions. Analogous BARITT diodes with n-type drift regions may be formed with appropriate changes in dopant and conductivity polarities.
[0013] FIG. 1 is a cross section of an example integrated circuit containing a BARITT diode. The integrated circuit 100 includes a substrate 102 which includes a p-type semiconductor material 104 having a dopant density of l x lO14cm"3to l x lO16cm"3, which corresponds to a bulk resistivity of about 100 ohm-cm to 1 ohm cm. The integrated circuit 100 includes an n-channel metal oxide semiconductor (NMOS) transistor 106 and the BARITT diode 108.
[0014] The NMOS transistor 106 is disposed in a shallow p-type well 110 and includes a gate dielectric layer 112 disposed at a top surface 114 of the substrate 102 and a gate 116 disposed on the gate dielectric layer 112. Optional gate sidewall spacers 118 may be disposed adjacent to the gate 116. The MOS transistor includes n-type source and drain regions 120 in the substrate 102 adjacent to the gate 116. The shallow p-type well 110 may be isolated from the p-type semiconductor material 104 by a first deep n-type well 122 which extends in the substrate 102 below the shallow p-type well 110. Field oxide 124 with a shallow trench isolation (STI) structure, as depicted in FIG. 1, may laterally isolate the NMOS transistor 106.
[0015] The BARITT diode 108 includes a source 126, a vertically oriented drift region 128 disposed in the substrate 102 immediately below the source 126, and a collector 130 disposed in the substrate 102 immediately below the drift region 128. A dielectric isolation structure 132 laterally surrounds the drift region 128. The drift region 128 and the dielectric isolation structure 132 extend vertically from the source 126 to the collector 130. The drift region 128 is free of an external electrical connection besides the source 126 and the collector 130.
[0016] In this example, the source 126 may be an n-type region in the substrate 102. The source 126 of the BARITT diode 108 and the source and drain regions 120 of the NMOS transistor 106 may have substantially equal n-type dopant distributions as a result of being formed concurrently. The drift region 128 may be a portion of the p-type semiconductor material 104, with an average dopant density of 1 x 1014cm"3to 1 x 1016cm"3. The drift region 128 may be free of additional dopants beyond the dopants of the p-type semiconductor material 104, so that a dopant distribution in the drift region 128 is advantageously more uniform than obtained by implanting dopants into the substrate 102. The collector 130 may be an n-type buried layer 130 with an average dopant density of at least l x lO18cm"3, which may advantageously reduce a series resistance of the BARITT diode 108. The dielectric isolation structure 132 may be field oxide 124 formed by an STI process, possibly formed concurrently with the field oxide 124 isolating the NMOS transistor 106. The drift region 128 may have an average width 134 of 1 micron to 5 microns with a round lateral shape which may advantageously reduce a size of the BARITT diode 108 compared to other lateral shapes. The round lateral shape may also reduce recombination of carriers in the drift region 128 at the dielectric isolation structure 132, compared to other lateral shapes, which may advantageously reduce noise in current through the BARITT diode 108. The drift region 128 may have a height 136 of 2 microns to 5 microns to provide a desired operating frequency of the BARITT diode
[0017] In this example, the BARITT diode 108 may include a second deep n-type well 138 in the substrate 102 outside of the dielectric isolation structure 132, extending to the collector 130. The second deep n-type well 138 may have a similar distribution of n-type dopants as the first deep n-type well 122 as a result of being formed concurrently. The BARITT diode 108 may further include an n-type collector contact region 140 in the substrate 102 above and contacting the second deep n-type well 138. The collector contact region 140 and the source and drain regions 120 of the NMOS transistor 106 may have substantially equal dopant distributions as a result of being formed concurrently. The BARITT diode 108 may be surrounded by an optional deep trench 142 which laterally isolates the collector 130 and the second deep n-type well 138 from the p-type semiconductor material 104. Integrating the BARITT diode 108 in the integrated circuit 100 with other components such as the NMOS transistor 106 may advantageously reduce a fabrication and assembly cost of an electronic system containing the integrated circuit 100.
[0018] FIG. 2A through FIG. 2F are cross sections of the integrated circuit of FIG. 1, depicted in key stages of an example formation process. Referring to FIG. 2A, formation of the integrated circuit 100 begins with providing the substrate 102, which may be a silicon wafer or other suitable substrate. The collector 130 is formed in the p-type semiconductor material 104 of the substrate 102 in the area for the BARITT diode 108. The substrate 102 may start as a silicon wafer with a first portion of the p-type semiconductor material 104 extending to a top surface of the silicon wafer. The first portion of the p-type semiconductor may possibly be a first p-type epitaxial layer formed on a bulk heavily doped silicon wafer. N-type dopants such as arsenic and antimony are implanted into the portion of the p-type semiconductor material 104 in the area for the BARITT diode 108 and subsequently diffused during a thermal drive process which grows an oxide layer on the silicon wafer. The oxide layer is removed and a second p-type epitaxial layer is formed on the first epitaxial layer to provide the substrate 102. The n-type dopants further diffuse during formation of the second epitaxial layer to form the collector 130 as the n-type buried layer 130. Other methods of forming the collector 130 are within the scope of this example.
[0019] Referring to FIG. 2B, the optional deep trench 142 may be formed by a deep reactive ion etch (DRIE) process followed by thermal oxide growth and oxide fill by semi-atmospheric chemical vapor deposition (SACVD). The deep trench 142 may possibly include a field plate of poly crystalline silicon, referred to herein as poly silicon. The deep trench 142 may be formed concurrently with other deep trenches in the integrated circuit 100, advantageously reducing fabrication cost. The field oxide 124 around the area for the MOS transistor 106 and the dielectric isolation structure 132 around the drift region 128 in the area for the BARITT diode 108 may be formed concurrently using an STI process. The STI process begins with forming a polish stop layer such as silicon nitride over the top surface 114 of the substrate 102. Isolation trenches are etched through the stop layer and into the substrate 102. A layer of thermal oxide is grown on sidewalls and bottoms of the isolation trenches, and the isolation trenches are subsequently filled, primarily with silicon dioxide-based dielectric material. The dielectric material may be formed, such as by SACVD, high density plasma (HDP), atmospheric chemical vapor deposition (APCVD) or a high aspect ratio process (HARP) using ozone and tetraethyl orthosilicate (TEOS). The dielectric material is subsequently removed from over the stop layer by a chemical mechanical polish (CMP) process, leaving the dielectric material in the isolation trenches. The stop layer is subsequently removed. In this example, the deep trench 142 surrounds and abuts the collector 130.
[0020] Referring to FIG. 2C, a deep n-well mask 144 is formed over the substrate 102 so as to expose the area for the BARITT diode 108, blocking the drift region 128. In this example, the deep n-well mask 144 also exposes the area for the NMOS transistor 106. The deep n-well mask 144 may include photoresist and possibly anti -reflection material, and may be formed by a photolithographic process.
[0021] N-type dopants such as phosphorus are implanted into the substrate 102 where exposed by the deep n-well mask 144. The n-type dopants may have a total dose of l x lO12cm"2to l x lO13cm"2. The substrate 102 is subsequently annealed to activate the implanted n-type dopants. In the area for the BARITT diode 108, the implanted n-type dopants form the second deep n-type well 138 outside of the dielectric isolation structure 132, extending down to the collector 130. In the area for the NMOS transistor 106, the implanted n-type dopants form the first deep n-type well 122. Forming the second deep n-type well 138 and the first deep n-type well 122 concurrently may advantageously reduce fabrication cost and complexity of the integrated circuit 100. The deep n-well mask 144 is subsequently removed, such as by an ash process followed by a wet clean process.
[0022] Referring to FIG. 2D, a shallow p-well mask 146 is formed over the substrate 102 so as to expose the area for the MOS transistor 106 and cover the area for the BARITT diode 108. The shallow p-well mask 146 may be formed by a similar process as the deep n-well mask 144 of FIG. 2C, although the shallow p-well mask 146 may be thinner than the deep n-well mask 144 due to a lower implant energy of p-type dopants blocked by the shallow p-well mask 146 than an implant energy of n-type dopants blocked by the deep n-well mask 144.
[0023] P-type dopants such as boron are implanted into the substrate 102 where exposed by the shallow p-well mask 146. The p-type dopants may be implanted in several doses with a total dose of 1 x 10 cm"to 1 x 10 cm". The substrate 102 is subsequently annealed to activate the implanted p-type dopants. In the area for the NMOS transistor 106, the implanted p-type dopants form the shallow p-type well 110 which provides a desired threshold voltage for the NMOS transistor 106. In this example, the drift region 128 of the BARITT diode 108 is free of additional dopants beyond the dopants of the p-type semiconductor material 104. The shallow p-well mask 146 is subsequently removed, such as described with respect to the deep n-well mask 144.
[0024] Referring to FIG. 2E, the gate dielectric layer 112 is formed at the top surface 114 of the substrate 102 and the gate 116 is formed on the gate dielectric layer 112. The gate dielectric layer 112 may be formed by thermal oxidation of silicon in the substrate 102. The gate 116 may be formed by forming a layer of poly silicon on the gate dielectric layer 112, forming a gate mask over the layer of polysilicon, and etching the layer of polysilicon to leave the gate 116. The gate sidewall spacers 118 are subsequently formed adjacent to lateral surfaces of the gate 116. The gate sidewall spacers 118 may be formed, such as by forming one or more conformal layers of silicon nitride and/or silicon dioxide over the gate 116 and the top surface 114 of the substrate 102, then removing the conformal layers from horizontal surfaces of the gate 116 and the top surface 114 by an anisotropic plasma etch such as a reactive ion etch (RIE) process, leaving the gate sidewall spacers 118 in place adjacent to the gate 116.
[0025] Referring to FIG. 2F, a source/drain mask 148 is formed over the substrate 102 so as to expose the area for the NMOS transistor 106 and the area of the second deep n-type well 138 of the BARITT diode 108. In this example, the source/drain mask 148 also exposes the area for the drift region 128 of the BARITT diode 108. The source/drain mask 148 may be formed by a similar process as the shallow p-well mask 146 of FIG. 2D, although the source/drain mask 148 may be thinner than the shallow p-well mask 146 due to a lower implant energy of n-type dopants blocked by the source/drain mask 148 than an implant energy of p-type dopants blocked by the shallow p-well mask 146.
[0026] N-type dopants such as phosphorus, arsenic and possibly antimony are implanted into the substrate 102 where exposed by the source/drain mask 148. The n-type dopants may have a total dose of l x lO14cm"2to l x lO16cm"2. The substrate 102 is subsequently annealed to activate the implanted n-type dopants. In the area for the NMOS transistor 106, the implanted n-type dopants form the n-type source and drain regions 120 in the substrate 102 adjacent to the gate 116. In the area for the BARITT diode 108, the implanted n-type dopants form the n-type collector contact region 140 in the substrate 102 above and contacting the second deep n-type well 138, and form the source 126 as an n-type diffused region 126 over the drift region 128. The source/drain mask 148 is subsequently removed, such as described with respect to the deep n-well mask 144 of FIG. 2C, to provide the structure of FIG. 1.
[0027] FIG. 3 is a cross section of another example integrated circuit containing a BARITT diode. The integrated circuit 300 is formed on a substrate 302 which includes a p-type semiconductor material 304 having a dopant density of l x lO14cm"3to l x lO16cm"3. The integrated circuit 300 includes an NPN Schottky bipolar transistor 306 and the BARITT diode 308.
[0028] The NPN Schottky bipolar transistor 306 has an n-type emitter 350 formed in the substrate 302, extending from a top surface 314 of the substrate 302 to a depth of less than 1 micron. The emitter 350 may have a dopant density greater than l x lO18cm"3, and may be formed by implanting n-type dopants such as phosphorus, arsenic and possibly antimony into the substrate 302 followed by annealing the substrate 302 to activate the implanted n-type dopants. The NPN Schottky bipolar transistor 306 has a p-type base 352 formed in the substrate 302 under, and surrounding, the emitter 350. The base 352 extends to the top surface 314 of the substrate 302 and may extend to a depth of 1 micron to 3 microns in the substrate 302. The base 352 may be formed as a p-type well as described in reference to FIG. 2D. The NPN Schottky bipolar transistor 306 has an n-type collector 354 formed in the substrate 302 under, and surrounding the base 352. The collector 354 may be formed as a deep n-type well as described in reference to FIG. 2C. The collector 354 may be augmented by an n-type buried layer 358 formed in the substrate 302 under, and contacting, the collector 354. The n-type buried layer 358 may be formed as described in reference to FIG. 2A. A collector contact region 322 is formed as a heavily doped n-type sinker in the substrate 302 to connect to the n-type buried layer 358. The collector contact region 322 is laterally isolated from the base 352 by field oxide 324. A Schottky barrier contact 356 is formed at the top surface 314 of the substrate 302, contacting the base 352 and the collector contact region 352 of the NPN Schottky bipolar transistor 306. For example, the Schottky barrier contact 356 may include molybdenum, platinum, chromium, tungsten, platinum silicide, or palladium silicide. The NPN Schottky bipolar transistor 306 may be laterally surrounded by a deep trench 342 as depicted in FIG. 3.
[0029] The BARITT diode 308 includes a source 326, a vertically oriented drift region 328 formed in the substrate 302 immediately below the source 326, and a collector 330 disposed in the substrate 302 immediately below the drift region 328. A dielectric isolation structure 332 laterally surrounds the drift region 328. The drift region 328 and the dielectric isolation structure 332 extend vertically from the source 326 to the collector 330. The drift region 328 is free of an external electrical connection besides the source 326 and the collector 330.
[0030] In this example, the source 326 may be a Schottky barrier contact 326 formed at the top surface 314 of the substrate 302, which may advantageously improve a power efficiency of the BARITT diode 308. The source 326 of the BARITT diode 308 and the Schottky barrier contact 356 of the NPN Schottky bipolar transistor 306 may have substantially equal compositions as a result of being formed concurrently.
[0031] The drift region 328 may be a portion of the p-type semiconductor material 304, as described in reference to FIG. 1. The drift region 328 may be free of additional dopants beyond the dopants of the p-type semiconductor material 304. The collector 330 may be an n-type buried layer 330 as described in reference to FIG. 1 and formed as described in reference to FIG. 2 A. The collector 330 of the BARITT diode 308 may be advantageously formed concurrently with the n-type buried layer 358 of the NPN Schottky bipolar transistor 306. The dielectric isolation structure 332 may be field oxide formed by an STI process as depicted in FIG. 3, advantageously formed concurrently with the field oxide 324 in the NPN Schottky bipolar transistor 306. In this example, the BARITT diode 308 may include a heavily doped n-type sinker 338 in the substrate 302 outside of the dielectric isolation structure 332, extending to the collector 330. The n-type sinker 338 may advantageously be formed concurrently with the n-type sinker 322 of the NPN Schottky bipolar transistor 306. The BARITT diode 308 may further include an n-type collector contact region 340 in the substrate 302 above and contacting the deep n-type well 338. The collector contact region 340 and the emitter 350 of the PN Schottky bipolar transistor 306 may have substantially equal dopant distributions as a result of being formed concurrently, accruing additional advantages of fabrication cost reduction and simplification. The BARITT diode 308 may optionally be surrounded by another instance of the deep trench 342 which laterally isolates the collector 330 and the deep n-type well 338 from the p-type semiconductor material 304. Integrating the BARITT diode 308 in the integrated circuit 300 with other components such as the NPN Schottky bipolar transistor 306 may advantageously reduce a fabrication and assembly cost of an electronic system containing the integrated circuit 300.
[0032] FIG. 4 is a cross section of another example integrated circuit containing a BARITT diode. The integrated circuit 400 is formed on a substrate 402 which includes a p-type semiconductor material 404 having a dopant density of l x lO14cm"3to l x lO16cm"3. The integrated circuit 400 includes an NPN bipolar transistor 406 and the BARITT diode 408.
[0034] The BARITT diode 408 includes a source 426, a vertically oriented drift region 428 formed in the substrate 402 immediately below the source 426, and a collector 430 disposed in the substrate 402 immediately below the drift region 428. A dielectric isolation structure 432 laterally surrounds the drift region 428. The drift region 428 and the dielectric isolation structure 432 extend vertically from the source 426 to the collector 430. The drift region 428 is free of an external electrical connection besides the source 426 and the collector 430.
[0035] In this example, the source 426 may be a layer of n-type polysilicon 464 formed on a silicon germanium epitaxial layer 462 at the top surface 414 of the substrate 402, which may advantageously improve a power efficiency of the BARITT diode 408. The layer of n-type polysilicon 464 of the source 426 and the emitter 456 of the NPN bipolar transistor 406 may have substantially equal compositions as a result of being formed concurrently, accruing advantages of fabrication cost reduction and simplification. The silicon germanium epitaxial layer 462 of the source 426 and the base 452 of the NPN bipolar transistor 406 may also have substantially equal compositions as a result of being formed concurrently, accruing additional advantages of fabrication cost reduction and simplification. In this example, the drift region 428 extends to the top surface of the substrate 402. The drift region 428 may be a portion of the p-type semiconductor material 404, as described in reference to FIG. 1. The drift region 428 may be free of additional dopants beyond the dopants of the p-type semiconductor material 404. The collector 430 may be an n-type buried layer 430 as described in reference to FIG. 1 and formed as described in reference to FIG. 2A. The dielectric isolation structure 432 may be field oxide formed by an STI process as depicted in FIG. 4, possibly formed concurrently with other field oxide elements in the integrated circuit 400, accruing further advantages of fabrication cost reduction and simplification.
[0036] In this example, the BARITT diode 408 may include a heavily doped n-type sinker 438 in the substrate 402 outside of the dielectric isolation structure 432, extending to the collector 430. The BARITT diode 408 may further include an n-type collector contact region 440 in the substrate 402 above and contacting the deep n-type well 438. The collector contact region 440 and the collector contact regions 460 of the NPN bipolar transistor 406 may have substantially equal dopant distributions as a result of being formed concurrently, accruing the aforementioned advantages of fabrication cost reduction and simplification. The BARITT diode 408 may optionally be surrounded by a deep trench 442 which laterally isolates the collector 430 and the deep n-type well 438 from the p-type semiconductor material 404. Integrating the BARITT diode 408 in the integrated circuit 400 with other components such as the NPN bipolar transistor 406 may advantageously reduce a fabrication and assembly cost of an electronic system containing the integrated circuit 400.
[0037] FIG. 5 is a cross section of a further example integrated circuit containing a BARITT diode, formed on a silicon-on-insulator (SOI) substrate. The SOI substrate 502 includes a p-type semiconductor material 504 in a device layer 570 over a buried oxide layer 566. The p-type semiconductor material 504 has a dopant density of l x lO14cm"3to l x lO16cm"3. The buried oxide layer 566 is disposed on a handle wafer 568 of the SOI substrate 502. The integrated circuit 500 includes an NMOS transistor 506 and the BARITT diode 508 in the device layer 570. In this example, the NMOS transistor 506 and the BARITT diode 508 are laterally isolated by deep trenches 542.
[0038] In this example, the NMOS transistor 506 is formed in a shallow p-type well 510 as described in reference to FIG. 1 and FIG. 2D. The NMOS transistor 506 has the elements described in reference to the NMOS transistor 106 of FIG. 1.
[0039] The BARITT diode 508 includes a source 526, a vertically oriented drift region 528 disposed in the substrate 502 immediately below the source 526, and a collector 530 disposed in the substrate 502 immediately below the drift region 528. A dielectric isolation structure 532 laterally surrounds the drift region 528. The drift region 528 is free of an external electrical connection besides the source 526 and the collector 530. The drift region 528 and the dielectric isolation structure 532 extend vertically from the source 526 to the collector 530. The source 526 may be formed as described in any of the examples disclosed herein. The drift region 528 may be a portion of the p-type semiconductor material 504 and may be free of additional dopants beyond the dopants of the p-type semiconductor material 504. In this example, the collector 530 may be formed by lateral diffusion of n-type dopants of a deep n-type well 538 which extends to a top surface 514 of the substrate 502 outside of the dielectric isolation structure 532. The deep n-type well 538 may be formed as described in reference to FIG. 2C. N-type collector contact regions 540 may be formed in the deep n-type well 538 outside of the dielectric isolation structure 532, as described in reference to FIG. 2F. Integrating the BARITT diode 508 in the integrated circuit 500 with other components such as the NMOS transistor 506 may accrue the advantages discussed in reference to the other examples disclosed herein.
[0040] FIG. 6 is a cross section of another example integrated circuit containing a BARITT diode. The integrated circuit 600 is formed in a substrate 602 which may be a silicon wafer, possibly with an epitaxial layer, or may be an SOI substrate. The substrate 602 includes a p-type semiconductor material 604 having a dopant density of l x lO14cm"3to l x lO16cm"3, which extends to a top surface 614 of the substrate 602. The integrated circuit 600 includes the BARITT diode 608 and at least one transistor, such as the transistors described in the examples disclosed herein.
[0041] In this example, the BARITT diode 608 includes a distributed source 626 with a first source segment 626a and a separate second source segment 626b, a distributed vertically oriented drift region 628, with a first drift region segment 628a and a separate second drift region segment 628b, disposed in the substrate 602 immediately below the first source segment 626a and the second source segment 626b respectively, and a collector 630 disposed in the substrate 602 immediately below the distributed drift region 628. A dielectric isolation structure 632 laterally surrounds the first drift region segment 628a and the second drift region segment 628b. The drift region 628 is free of an external electrical connection besides the source 626 and the collector 630. The drift region 628 and the dielectric isolation structure 632 extend vertically from the source 626 to the collector 630.
[0042] The source 626 may be formed as described in any of the examples disclosed herein. The drift region 628 may be a portion of the p-type semiconductor material 604 and may be free of additional dopants beyond the dopants of the p-type semiconductor material 604. The collector 630 may be formed as described in any of the examples disclosed herein. A deep n-type well 638 and an n-type collector contact region 640 may be formed in the substrate 602 outside of the dielectric isolation structure 632 surrounding the first drift region segment 628a and the second drift region segment 628b. The BARITT diode 608 may be surrounded by an optional deep trench 642 which laterally isolates the collector 630 and the deep n-type well 638 from the p-type semiconductor material 604. Forming the BARITT diode with the distributed source 626 and the distributed drift region 628, surrounded by the deep n-type well 638, may advantageously enable operation of the BARITT diode 608 at a desired current while providing a desired low series resistance.
[0043] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

中文:
[0002]用于例如汽车碰撞警报系统的低成本应用的大多数微波雷达系统使用多普勒信号处理。多普勒效应(或多普勒频移)是观测器相对于其目标移动的反射波(或其它周期性事件)的频率的改变。可以使用多普勒信号处理来将反射信号与寄生噪声分离并测量移动目标的速度。然而,多普勒检测具挑战性,这是因为回波信号是来自反射而非来自基带站。因此,需要低噪声多普勒检测器。作为离散装置,势垒注入渡越时间(BARrier InjectionTransit-Time;BARITT)二极管已在自混频微波多普勒系统中展现较高敏感度。然而,对于低成本应用,离散装置系统的制造成本和复杂度不合期望地较高。
[0003]在所描述实例中,一种集成电路包含晶体管和经竖直定向的BARITT二极管。BARITT二极管具有:源极,其被安置成接近于所述集成电路的衬底的顶部表面;漂移区,其被安置在所述衬底的半导体材料中在所述源极下方;以及集电极,其被安置在所述衬底的所述半导体材料中在所述漂移区下方。一种介电隔离结构侧向地环绕所述漂移区,从所述源极延伸到所述集电极。
[0004]图1是含有BARITT二极管的实例集成电路的横截面。
[0005]图2A到2F是实例形成工艺的关键阶段中描绘的图1的集成电路的横截面。
[0006]图3是含有BARITT二极管的另一实例集成电路的横截面。
[0007]图4是含有BARITT二极管的另一实例集成电路的横截面。
[0008]图5是形成在SOI衬底上含有BARITT二极管的另外实例集成电路的横截面。
[0009]图6是含有BARITT二极管的另一实例集成电路的横截面。
[0010]所述图式未必按比例绘制。可在不具有特定细节中的一或多个或在具有其它方法的情况下实践实例实施例。在其它情况下,未详细展示熟知结构或操作以避免混淆实例实施例。一些动作可以不同次序发生和/或与其它动作或事件同时发生。此外,实施根据实例实施例的方法不需要所有所说明的动作或事件。
[0011]可以通过以下操作而在集成电路中形成经竖直定向的BARITT二极管:在集成电路的衬底的基于硅的半导体材料中在衬底的顶部表面下方的至少一微米的深度处形成具有第一导电类型的集电极;和直接在集电极上接近于顶部表面形成源极。衬底的在源极与集电极之间的半导体材料提供BARITT二极管的漂移区。介电隔离结构侧向地环绕漂移区且从源极延伸到集电极。源极可以是衬底的半导体材料的重掺杂区,可以包含肖特基势垒,且可以包含硅锗层。集电极可以是衬底中的内埋层。介电隔离结构可以是场氧化物。
[0012]本文中所公开的实例将描述具有p型漂移区的BARITT二极管。具有n型漂移区的类似BARITT二极管可以经形成掺杂剂和导电性极性进行适当改变。
[0013]图1是含有BARITT二极管的实例集成电路的横截面。集成电路100包含衬底102,衬底102包含掺杂剂密度为1×1014cm-3到1×1016cm-3的p型半导体材料104,所述掺杂剂密度对应于为约100ohm-cm到1ohm cm的体电阻率。集成电路100包含n沟道金属氧化物半导体(NMOS)晶体管106和BARITT二极管108。
[0014]NMOS晶体管106安置在浅p型阱110中且包含安置在衬底102的顶部表面114处的栅极介电层112和安置在栅极介电层112上的栅极116。任选的栅极侧壁间隔件118可以被安置成邻近于栅极116。NMOS晶体管包含衬底102中邻近于栅极116的n型源极和漏极区120。可以通过第一深n型阱122来将浅p型阱110与p型半导体材料104隔离,第一深n型阱122在衬底102中在浅p型阱110下方延伸。如图1中所描绘的具有浅沟槽隔离(STI)结构的场氧化物124可以侧向地隔离NMOS晶体管106。
[0015]BARITT二极管108包含源极126、安置在衬底102中紧接在源极126下方的经竖直定向的漂移区128,以及被安置在衬底102中紧接在漂移区128下方的集电极130。介电隔离结构132侧向地环绕漂移区128。漂移区128和介电隔离结构132从源极126竖直地延伸到集电极130。漂移区128不含除了源极126和集电极130以外的外部电连接件。
[0016]在这个实例中,源极126可以是衬底102中的n型区。由于同时形成,所以BARITT二极管108的源极126与NMOS晶体管106的源极和漏极区120可以具有基本上相同的n型掺杂剂分布。漂移区128可以是p型半导体材料104的一部分,平均掺杂剂密度是1×1014cm-3到1×1016cm-3。漂移区128可以不含除了p型半导体材料104的掺杂剂以外的额外掺杂剂,使得相较于通过将掺杂剂植入到衬底102中所获得的掺杂剂分布,漂移区128中的掺杂剂分布有利地更均一。集电极130可以是平均掺杂剂密度为至少1×1018cm-3的n型内埋层130,所述平均掺杂剂密度可以有利地减小BARITT二极管108的串联电阻。介电隔离结构132可以是通过STI工艺形成的场氧化物124,场氧化物124有可能与隔离NMOS晶体管106的场氧化物124同时形成。漂移区128的平均宽度134可以是1微米到5微米,其具有圆形侧向形状,与其它侧向形状相比较,此可以有利地减小BARITT二极管108的大小。与其它侧向形状相比较,圆形侧向形状还可减小介电隔离结构132处漂移区128中的载剂的再结合,此可以有利地减少电流穿过BARITT二极管108的噪声。漂移区128的高度136可以是2微米到5微米,从而提供BARITT二极管108所希望的操作频率。
[0017]在这个实例中,BARITT二极管108可以包含衬底102中在介电隔离结构132外部的第二深n型阱138,其延伸到集电极130。由于同时形成,所以第二深n型阱138的n型掺杂剂的分布可以与第一深n型阱122的n型掺杂剂分布相似。BARITT二极管108可以进一步包含衬底102中在第二深n型阱138上方并与第二深n型阱138接触的n型集电极接触区140。由于同时形成,所以NMOS晶体管106的集电极接触区140与源极和漏极区120可以具有基本上相同的掺杂剂分布。BARITT二极管108可以被任选的深沟槽142环绕,深沟槽142侧向地将集电极130和第二深n型阱138与p型半导体材料104隔离。在集成电路100中将BARITT二极管108与例如NMOS晶体管106的其它组件集成可以有利地降低含有集成电路100的电子系统的制造和装配成本。
[0018]图2A到2F是实例形成工艺的关键阶段中描绘的图1的集成电路的横截面。参看图2A,形成集成电路100开始于提供衬底102,衬底102可以是硅晶片或其它合适的衬底。集电极130在BARITT二极管108的区域中形成在衬底102的p型半导体材料104中。衬底102可以以硅晶片开始,其中p型半导体材料104的第一部分延伸到硅晶片的顶部表面。p型半导体的第一部分有可能是形成在重掺杂块体硅晶片上的第一p型外延层。在BARITT二极管108的区域中将例如砷和锑的n型掺杂剂植入到p型半导体材料104的部分中,且所述n型掺杂剂随后在热驱动工艺期间发生扩散,热驱动工艺使氧化层在硅晶片上生长。移除氧化层,且将第二p型外延层形成在第一外延层上以提供衬底102。n型掺杂剂在形成第二外延层以形成集电极130期间进一步扩散成n型内埋层130。形成集电极130的其它方法处于本实例的范围内。
[0019]参看图2B,可以通过深反应性离子蚀刻(DRIE)工艺,接着通过半大气压化学气相沉积(SACVD)的热氧化物生长和氧化物填充来形成任选的深沟槽142。深沟槽142有可能包含多晶硅的场板,其在本文中被称作多晶硅。深沟槽142可以与集成电路100中的其它深沟槽同时形成,从而有利地降低制造成本。围绕NMOS晶体管106的区域的场氧化物124和在BARITT二极管108的区域中围绕漂移区128的介电隔离结构132可以使用STI工艺同时形成。STI工艺开始于在衬底102的顶部表面114上形成例如氮化硅的抛光终止层。隔离沟槽经蚀刻穿过终止层并且进入衬底102。热氧化物层生长在隔离沟槽的侧壁和底部上,且随后主要用基于二氧化硅的介电材料来填充隔离沟槽。可以例如通过SACVD、高密度等离子体(HDP)、大气压化学气相沉积(APCVD)或使用臭氧和原硅酸四乙酯(TEOS)的高纵横比工艺(HARP)来形成介电材料。随后通过化学机械抛光(CMP)工艺从终止层上移除介电材料,从而在隔离沟槽中留下介电材料。随后移除终止层。在这个实例中,深沟槽142环绕并邻接于集电极130。
[0020]参看图2C,深n阱掩模144形成在衬底102上以便暴露粘连漂移区128的BARITT二极管108的区域。在这个实例中,深n阱掩模144还暴露NMOS晶体管106的区域。深n阱掩模144可以包含光致抗蚀剂以及有可能的抗反射材料,且可以通过光刻工艺行成。
[0021]将例如磷的n型掺杂剂植入到通过深n阱掩模144暴露的衬底102中。n型掺杂剂的总剂量可以是1×1012cm-2到1×1013cm-2。随后使衬底102退火以激活经植入的n型掺杂剂。在BARITT二极管108的区域中,经植入的n型掺杂剂形成在介电隔离结构132外部的第二深n型阱138,向下延伸到集电极130。在NMOS晶体管106的区域中,经植入的n型掺杂剂形成第一深n型阱122。同时形成第二深n型阱138和第一深n型阱122可以有利地降低集成电路100的制造成本和复杂度。随后移除深n阱掩模144,例如通过灰化工艺接着通过湿法清洗工艺。
[0022]参看图2D,浅p阱掩模146形成在衬底102上以便暴露NMOS晶体管106的区域并覆盖BARITT二极管108的区域。浅p阱掩模146可以通过与图2C的深n阱掩模144相似的工艺形成,但由于被浅p阱掩模146阻挡的p型掺杂剂的植入能量低于被深n阱掩模144阻挡的n型掺杂剂的植入能量,所以浅p阱掩模146可比深n阱掩模144薄。
[0023]将例如硼的p型掺杂剂植入到通过浅p阱掩模146暴露的衬底102中。可以用1×1012cm-2到1×1014cm-2的总剂量将p型掺杂剂植入在若干剂量中。随后使衬底102退火以激活经植入的p型掺杂剂。在NMOS晶体管106的区域中,形成浅p型阱110,浅p型阱110向NMOS晶体管106提供所要的阈值电压。在这个实例中,BARITT二极管108的漂移区128不含除了p型半导体材料104的掺杂剂以外的额外掺杂剂。随后移除浅p阱掩模146,例如关于深n阱掩模144所描述。
[0024]参看图2E,栅极介电层112形成在衬底102的顶部表面114处,且栅极116形成在栅极介电层112上。栅极介电层112可以通过硅在衬底102中的热氧化而形成。栅极116可以通过以下操作形成:在栅极介电层112上形成多晶硅层;在多晶硅层上形成栅极掩模;以及蚀刻多晶硅层以留下栅极116。栅极侧壁间隔件118随后邻近于栅极116的侧向表面而形成。可以例如通过以下操作形成栅极侧壁间隔件118:在栅极116和衬底102的顶部表面114上形成一或多个氮化硅和/或二氧化硅保形层;接着通过例如反应性离子蚀刻(RIE)工艺的各向异性等离子体蚀刻而从栅极116和顶部表面114的水平表面移除保形层,从而在邻近于栅极116的适当位置留下栅极侧壁间隔件118。
[0025]参看图2F,源极/漏极掩模148形成在衬底102上以便暴露NMOS晶体管106的区域和BARITT二极管108的第二深n型阱138的区域。在这个实例中,源极/漏极掩模148还暴露BARITT二极管108的漂移区128的区域。源极/漏极掩模148可以通过与图2D的浅p阱掩模146相似的工艺形成,但由于被源极/漏极掩模148阻挡的n型掺杂剂的植入能量低于被浅p阱掩模146阻挡的p型掺杂剂的植入能量,所以源极/漏极掩模148可比浅p阱掩模146薄。
[0026]将例如磷、砷以及有可能锑的n型掺杂剂植入到通过源极/漏极掩模148暴露的衬底102中。n型掺杂剂的总剂量可以是1×1014cm-2到1×1016cm-2。随后使衬底102退火以激活经植入的n型掺杂剂。在NMOS晶体管106的区域中,经植入的n型掺杂剂在衬底102中形成邻近于栅极116的n型源极和漏极区120。在BARITT二极管108的区域中,经植入的n型掺杂剂在衬底102中形成n型集电极接触区140在第二深n型阱138上方并与第二深n型阱138接触,且在漂移区128上形成源极126以成为n型扩散区126。随后移除源极/漏极掩模148,例如关于图2C的深n阱掩模144所描述,从而提供图1的结构。
[0027]图3是含有BARITT二极管的另一实例集成电路的横截面。将集成电路300形成在衬底302上,衬底302包含掺杂剂密度为1×1014cm-3到1×1016cm-3的p型半导体材料304。集成电路300包含NPN肖特基双极晶体管306和BARITT二极管308。
[0028]NPN肖特基双极晶体管306具有形成在衬底302中的n型发射极350,从衬底302的顶部表面314延伸到小于1微米的深度。发射极350的掺杂剂密度可以大于1×1018cm-3,且发射极350可以通过以下操作形成:将例如磷、砷和有可能锑的n型掺杂剂植入到衬底302中,接着使衬底302退火以激活经植入的n型掺杂剂。NPN肖特基双极晶体管306具有形成在衬底302中在发射极350下并环绕发射极350的p型基极352。基极352延伸到衬底302的顶部表面314且可以在衬底302中延伸到1微米到3微米的深度。基极352可以形成为p型阱,如参考图2D所描述。TNPN肖特基双极晶体管306具有形成在衬底302中在基极352下并环绕基极352的n型集电极354。集电极354可以形成为深n型阱,如参考图2C所描述。集电极354可以通过n型内埋层358而扩增,n型内埋层358形成在衬底302中在集电极354下并与集电极354接触。n型内埋层358可以如参考图2A所描述而形成。集电极接触区322形成为衬底302中连接到n型内埋层358的重掺杂n型沉块(sinker)。集电极接触区322通过场氧化物324侧向地与基极352隔离。肖特基势垒触点356形成在衬底302的顶部表面314处,与NPN肖特基双极晶体管306的基极352和集电极接触区352接触。举例来说,肖特基势垒触点356可以包含钼、铂、铬、钨、硅化铂或硅化钯。NPN肖特基双极晶体管306可以被深沟槽342侧向地环绕,如图3中所描绘。
[0029]BARITT二极管308包含源极326、形成在衬底302中紧接在源极326下方的经竖直定向的漂移区328,以及安置在衬底302中紧接在漂移区328下方的集电极330。介电隔离结构332侧向地环绕漂移区328。漂移区328和介电隔离结构332从源极326竖直地延伸到集电极330。漂移区328不含除了源极326和集电极330以外的外部电连接件。
[0030]在这个实例中,源极326可以是形成在衬底302的顶部表面314处的肖特基势垒触点326,其可以有利地改进BARITT二极管308的功率效率。由于同时形成,所以BARITT二极管308的源极326与NPN肖特基双极晶体管306的肖特基势垒触点356可以具有基本上相同的组成。
[0031]漂移区328可以是p型半导体材料304的一部分,如参考图1所描述。漂移区328可以不含除了p型半导体材料304的掺杂剂以外的额外掺杂剂。集电极330可以是如参考图1所描述的n型内埋层330且如参考图2A所描述而形成。BARITT二极管308的集电极330可以有利地与NPN肖特基双极晶体管306的n型内埋层358同时形成。介电隔离结构332可以是如图3中所描绘的通过STI工艺形成的场氧化物,其有利地与NPN肖特基双极晶体管306中的场氧化物324同时形成。在这个实例中,BARITT二极管308可以包含衬底302中除了介电隔离结构332以外的重掺杂n型沉块338,其延伸到集电极330。n型沉块338可以有利地与NPN肖特基双极晶体管306的n型沉块322同时形成。BARITT二极管308可以进一步包含衬底302中在深n型阱338上方并与深n型阱338接触的n型集电极接触区340。由于同时形成,所以集电极接触区340与NPN肖特基双极晶体管306的发射极350可以具有基本上相同的掺杂剂分布,从而累积制造成本降低并简化的额外优点。BARITT二极管308可以任选地被深沟槽342的另一例子环绕,深沟槽342的另一例子侧向地隔离集电极330和深n型阱338与p型半导体材料304。在集成电路300中将BARITT二极管308与例如NPN肖特基双极晶体管306的其它组件集成可以有利地降低含有集成电路300的电子系统的制造和装配成本。
[0032]图4是含有BARITT二极管的另一实例集成电路的横截面。将集成电路400形成在衬底402上,衬底402包含掺杂剂密度为1×1014cm-3到1×1016cm-3的p型半导体材料404。集成电路400包含NPN双极晶体管406和BARITT二极管408。
[0034]BARITT二极管408包含源极426、形成在衬底402中紧接在源极426下方的经竖直定向的漂移区428,以及安置在衬底402中紧接在漂移区428下方的集电极430。介电隔离结构432侧向地环绕漂移区428。漂移区428和介电隔离结构432从源极426竖直地延伸到集电极430。漂移区428不含除了源极426和集电极430以外的外部电连接件。
[0035]在这个实例中,源极426可以是形成在衬底402的顶部表面414处的硅锗外延层462上的n型多晶硅层464,其可以有利地改进BARITT二极管408的功率效率。由于同时形成,所以源极426与NPN双极晶体管406的发射极456的n型多晶硅层464可以具有基本上相同的组成,从而累积制造成本降低并简化的优点。由于同时形成,所以源极426与NPN双极晶体管406的基极452的硅锗外延层462还可具有基本上相同的组成,从而累积制造成本降低并简化的额外优点。在这个实例中,漂移区428延伸到衬底402的顶部表面。漂移区428可以是p型半导体材料404的一部分,如参考图1所描述。漂移区428可以不含除了p型半导体材料404的掺杂剂以外的额外掺杂剂。集电极430可以是如参考图1所描述的n型内埋层430且如参考图2A所描述而形成。介电隔离结构432可以是如图4中所描绘的通过STI工艺形成的场氧化物,其有可能与集成电路400中的其它场氧化物元件同时形成,从而累积制造成本降低并简化的另外优点。
[0036]在这个实例中,BARITT二极管408可以包含衬底402中除了介电隔离结构432以外的重掺杂n型沉块438,延伸到集电极430。BARITT二极管408可以进一步包含衬底402中在深n型阱438上方并与深n型阱438接触的n型集电极接触区440。由于同时形成,所以集电极接触区440与NPN双极晶体管406的集电极接触区460可以具有基本上相同的掺杂剂分布,从而累积前述制造成本降低并简化的优点。BARITT二极管408可以任选地被深沟槽442环绕,深沟槽442侧向地隔离集电极430和深n型阱438与p型半导体材料404。在集成电路400中将BARITT二极管408与例如NPN肖特基双极晶体管406的其它组件集成可以有利地降低含有集成电路400的电子系统的制造和装配成本。
[0037]图5是形成在绝缘体上硅(SOI)衬底上含有BARITT二极管的另外实例集成电路的横截面。SOI衬底502包含装置层570中在内埋氧化物层566上的p型半导体材料504。p型半导体材料504的掺杂剂密度为1×1014cm-3到1×1016cm-3。将内埋氧化物层566安置在SOI衬底502的处置晶片568上。集成电路500包含装置层570中的NMOS晶体管506和BARITT二极管508。在这个实例中,NMOS晶体管506与BARITT二极管508通过深沟槽542而被侧向地隔离。
[0038]在这个实例中,NMOS晶体管506形成在浅p型阱510中,如参考图1和图2D所描述。NMOS晶体管506具有参考图1的NMOS晶体管106所描述的元件。
[0039]BARITT二极管508包含源极526、安置在衬底502中紧接在源极526下方的经竖直定向的漂移区528,以及安置在衬底502中紧接在漂移区528下方的集电极530。介电隔离结构532侧向地环绕漂移区528。漂移区528不含除了源极526和集电极530以外的外部电连接件。漂移区528和介电隔离结构532从源极526竖直地延伸到集电极530。源极526可以如本文中所公开的实例中的任一个中所描述而形成。漂移区528可以是p型半导体材料504的一部分且可以不含除了p型半导体材料504的掺杂剂以外的额外掺杂剂。在这个实例中,集电极530可以通过深n型阱538的n型掺杂剂的侧向扩散而形成,n型阱538延伸到在介电隔离结构532外部的衬底502的顶部表面514。n型阱538可以如参考图2C所描述而形成。n型集电极接触区540可以形成在n型阱538中,在介电隔离结构532外部,如参考图2F所描述。在集成电路500中将BARITT二极管508与例如NMOS晶体管506的其它组件集成可以累积参考本文中所公开的其它实例所论述的优点。
[0040]图6是含有BARITT二极管的另一实例集成电路的横截面。将集成电路600形成在衬底602中,衬底602可以是有可能具有外延层的硅晶片,或可以是SOI衬底。衬底602包含掺杂剂密度为1×1014cm-3到1×1016cm-3的p型半导体材料604,其延伸到衬底602的顶部表面614。集成电路600包含BARITT二极管608和至少一个晶体管,例如本文中所公开的实例中所描述的晶体管。
[0041]在这个实例中,BARITT二极管608包含:分布式源极626,其具有第一源极段626a和单独的第二源极段626b;分布式经竖直定向的漂移区628,其具有第一漂移区段和单独的第二漂移段628b,第一漂移区段628a和第二漂移区段628b被安置在衬底602中分别紧接在第一源极段626a和第二源极段626b下方;以及集电极630,其被安置在衬底602中紧接在分布式漂移区628下方。介电隔离结构632侧向地环绕第一漂移区段628a和第二漂移区段628b。漂移区628不含除了源极626和集电极630以外的外部电连接件。漂移区628和介电隔离结构632从源极626竖直地延伸到集电极630。
[0042]源极626可以如本文中所公开的实例中的任一个中所描述而形成。漂移区628可以是p型半导体材料604的一部分且可以不含除了p型半导体材料604的掺杂剂以外的额外掺杂剂。集电极630可以如本文中所公开的实例中的任一个中所描述而形成。深n型阱638和n型集电极接触区640可以形成在衬底602中,在环绕第一漂移区段628a和第二漂移区段628b的介电隔离结构632外部。BARITT二极管608可以被任选的深沟槽642环绕,深沟槽642侧向地隔离集电极630和深n型阱638与p型半导体材料604。形成具有被深n型阱638环绕的分布式源极626和分布式漂移区628的BARITT二极管可以有利地实现在所要电流下操作BARITT二极管608,同时提供所要的低串联电阻。
[0043]在所描述的实施例中可能进行修改,且其它实施例在权利要求的范围内为可能的。