English:
[0001] Disclosed embodiments are directed to a Magnetoresistive Random Access Memory (MRAM) cell. More particularly, exemplary embodiments are directed to a magnetic tunnel junction (MTJ) storage element and to methods of integrating the same with logic integration of the MRAM cell.
[0002] Magnetoresistive Random Access Memory (MRAM) is a non-volatile memory technology that uses magnetic elements. For example, Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) uses electrons that become spin-polarized as the electrons pass through a thin film (spin filter). STT-MRAM is also known as Spin Transfer Torque RAM (STT-RAM), Spin Torque Transfer Magnetization Switching RAM (Spin-RAM), and Spin Momentum Transfer (SMT- RAM).
[0003] Fig. 1 illustrates a conventional STT-MRAM bit cell 100. The STT-MRAM bit cell 100 includes magnetic tunnel junction (MTJ) storage element 105 (also referred to as "MTJ stack"), a transistor 101, a bit line 102 and a word line 103. The MTJ stack is formed, for example, from a pinned layer 124 and a free layer 120, each of which can hold a magnetic moment or polarization, separated by an insulating tunneling barrier layer 122. There is conventionally an anti-ferromagnetic (AFM) layer and a cap layer (not shown) in the MTJ stack. The AFM layer is used to pin the magnetic moment of the pinned layer. The cap layer is used as a buffer layer between the MTJ and metal interconnects. The polarization of the free layer can be reversed by applying current in a specific direction such that the polarity of the pinned layer and the free layer are either substantially aligned or opposite. The resistance of the electrical path through the MTJ varies depending on the alignment of the polarizations of the pinned and free layers. This variation in resistance can be used to program and read the bit cell 100, as is known. The STT-MRAM bit cell 100 also includes a source line 104, a sense amplifier 108, read/write circuitry 106 and a bit line reference 107. Those skilled in the art will appreciate the operation and construction of the memory cell 100 as known in the art.
[0004] MRAM cells are commonly integrated with various other logic gates and electronic components such as transistors, capacitors, metal wires, etc., in the development of memory devices. Accordingly, it is desirable that the process of manufacturing MTJ elements remains compatible with the constraints inherent to manufacture of integrated circuits. However, it is well known that semiconductor technology scaling is not uniform across all components involved in the manufacture of integrated circuits. For example, metal wire width and sizes of Vertical Interconnect Access (commonly known as "via") are scale by about 70% from one generation to the next. However, interlayer metal dielectric (IMD) thickness scaling is much smaller than 70% because diffusion cap layers cannot scale that fast. Therefore, the capacitors scale down at a much slower rate. More particularly, scaling down of height of MTJ cells is even slower and in comparison to other electronic components in integrated circuits, the scaling is almost non-existent in the current state of the art.
[0005] The disproportionate rate of scaling in different components gives rise to various challenges in the design and manufacture of integrated circuits. With regard to circuits involving the use of MRAM cells, there are numerous problems associated with integration of rapidly shrinking electronic components with relatively unchanging MRAM sizes. For purposes of this discussion, electronic components such as transistors, metal wires, capacitors, vias, etc, which are not a part of the MRAM cell are generally referred to as "logic elements"; and the process of their integration is referred to as "logic process". The integration process of MRAM elements is generally referred to as "MRAM process". It is desirable for the MRAM process to be compatible with the related logic process. Therefore, it would be beneficial to embed the MRAM process into the logic process flow.
[0006] A cross-sectional view of a memory device including at least one MRAM cell is illustrated in FIG. 2. Elements of a particular device layer "x", the layer below, "x-1", and the layer above, "x+1", are shown. Both logic elements and MRAM components are illustrated in juxtaposition. The logic elements are generally represented by metal wires M'x/Mx and M'x-l/Mx-1 in layers x, and x-1 respectively; via V'x in layer x; insulating layers Caplx and Cap2x in layer x, and Cap 1 x+1 and Cap2x+1 in layer x+1. The MRAM components comprise an MTJ stack (such as MTJ105) formed between top electrode (TE) and bottom electrode (BE); metal wires Mx and Mx-1 (constituting, for example, bit line 102 and source line 104) in layers x and x-1 respectively; inter-metal- dielectric layers IMDx and IMDx-1; via Vx in layer x; and insulating layers Caplx and
[0007] With continuing reference to FIG. 2, L2 represents the height of the MRAM cell including the bottom electrode BE, MTJ stack, and top electrode TE. In general, the vertical distance between metal wires in adjacent layers is the maximum space available for forming the MRAM cell. Accordingly, the MRAM cell in layer x must be contained within metal wires Mx and Mx-1. However, as shown in FIG. 2, this available vertical space is also shared by elements such as vias, insulating layers, and common IMD layer. Accounting for the vertical space consumed by these elements, LI represents the effective vertical space between the metal layers that is available for the MRAM cell. Trends in technology scaling reveal that the vertical space between layers is rapidly shrinking. However, as previously noted, the thickness of cap layer is not scaling down at the same rate and the scaling rate is slower. Further, as illustrated, a bi-layer insulating structure may be utilized in order to balance mechanical stress introduced by the bottom electrode BE, imposing further restrictions on the available space.
[0008] As a result, the available vertical space for formation of the MRAM cell, LI, is less than the actual height, L2, of the MRAM cell. Therefore there is an overlap where the MRAM cell intrudes into the metal wire Mx, as shown. The intrusion creates several problems. Firstly, the danger of a short-circuit is created between the metal Mx and the sidewalls and/or the tunneling barrier layer of the MTJ stack. The issue may be exacerbated in devices with a high density of MRAM cells, because the thin IMD filling between multiple MRAM cells may be insufficient to protect the sidewalls of the cells during etching and metallization processes. Moreover, the introduction of bi-layer insulating caps elevates the vertical position of the MTJ element, thereby increasing the intrusion with metal Mx.
[0009] Generally, MRAM height is not amenable to further scaling down. Accordingly, the thickness of metal wire Mx needs to be reduced and the metal pattern should be smaller than top electrode TE, in order to avoid the intrusion. Because top electrode TE is a conductor layer, thinning of the metal wire above the MTJ element is not disadvantageous, as it acts as a local connection. Additionally, metal wire recesses between MTJ cells may cause short circuits between the metal wires if the IMD fill has defects such as seams. Accordingly, there is a need in the art for techniques and apparatuses where MRAM cells may be integrated in memory devices in a manner compatible with the logic formation processes.
[0010] Exemplary embodiments are directed to apparatuses and methods for improving layouts of MRAM cells and integration with the logic in a common layer.
[0011] For example, an exemplary embodiment includes a semiconductor device comprising a magnetic tunnel junction (MTJ) storage element configured to be disposed in a common interlayer metal dielectric (IMD) layer with a logic element and a reduced thickness metal wire in the common IMD layer coupled to the MTJ storage element that is smaller in thickness then a corresponding metal wire of the logic element.
[0012] Another embodiment can include a method of forming a semiconductor device comprising: forming a magnetic tunnel junction (MTJ) storage element in a common interlayer metal dielectric (IMD) layer with a logic element; and forming a reduced thickness metal wire in the common IMD layer coupled to the MTJ storage element that is smaller in thickness then a corresponding metal wire of the logic element.
[0013] Another embodiment can include a semiconductor device comprising: a magnetic tunnel junction (MTJ) storage means formed in a interlayer metal dielectric (IMD) layer with a logic means; and a reduced thickness means for conducting in the common IMD layer coupled to the MTJ storage means that is smaller in thickness then a corresponding conducting means of the logic means.
[0014] Another embodiment can include a method of forming a semiconductor device comprising: a step for forming a magnetic tunnel junction (MTJ) storage element in a common interlayer metal dielectric (IMD) layer with a logic element; and a step for forming a reduced thickness metal wire in the common IMD layer coupled to the MTJ storage element that is smaller in thickness then a corresponding metal wire of the logic element.
[0015] Another embodiment can include a method of forming a semiconductor device comprising a magnetic tunnel junction (MTJ) storage element disposed in a common interlayer metal dielectric (IMD) layer with a logic element, the method comprising: depositing an MTJ storage element comprising a pinned layer, a tunneling barrier layer and a free layer on a bottom electrode in the common IMD layer; patterning the MTJ storage element; depositing a sidewall cap layer on sidewalls of the MTJ storage element; depositing a top electrode on the MTJ storage element; patterning the top electrode and the bottom electrode; depositing a portion of the common IMD layer; depositing a second metal wire on the top electrode; patterning the second metal wire to form a metal island that is smaller than the top electrode; depositing another portion of the common IMD layer; depositing a second cap layer on the common IMD layer to separate the common IMD layer from a top IMD layer; and forming a third metal wire in the top IMD layer, wherein the third metal wire is coupled to the second metal wire.
[0016] Another embodiment can include a method of forming a semiconductor device comprising a magnetic tunnel junction (MTJ) storage element disposed in a common interlay er metal dielectric (IMD) layer with a logic element, the method comprising: forming a first cap layer comprising a first portion and a second portion; patterning the second portion to form an opening for a bottom electrode; depositing the bottom electrode, such that the bottom electrode is in contact with a first metal wire in the first portion; depositing an MTJ storage element on the bottom electrode; depositing a sidewall cap layer on sidewalls of the MTJ storage element; depositing a top electrode on the MTJ storage element; depositing a second metal wire on the top electrode, wherein the second metal wire has reduced thickness in comparison to a corresponding metal wire of the logic element; depositing at least part of the common IMD layer; and depositing a second cap layer on the common IMD layer to separate the common IMD layer from a top IMD layer.
[0018] FIG. 1 is an illustration of a conventional MRAM circuit with an MTJ storage element.
[0019] FIG. 2 is a cross-sectional view of a conventional memory device comprising logic elements and MRAM cells.
[0020] FIG. 3 is a cross-sectional view of an exemplary embodiment including MRAM cells integrated with logic.
[0022] FIG. 5 details the process flow in forming a memory device including MRAM cells according to an exemplary embodiment.
[0023] FIG. 6 illustrates another exemplary embodiment including MRAM cells integrated with logic.
[0024] FIG. 7 illustrates yet another exemplary embodiment including MRAM cells integrated with logic.
[0025] FIG. 8 details the process flow in forming a memory device including MRAM cells according to another exemplary embodiment.
[0026] Aspects of the various embodiments are disclosed in the following description and related drawings directed to specific embodiments. Alternate embodiments may be devised without departing from the scope of the invention. Additionally, well-known elements of the various embodiments will not be described in detail or will be omitted so as not to obscure the relevant details of the various embodiments.
[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising,", "includes" and/or "including", when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
[0029] It will be appreciated that with conventional techniques, it is difficult to integrate the process of forming MRAM cells in a manner that is compatible with the logic process in semiconductor integrated circuits. Exemplary embodiments beneficially avoid the problem of MTJ cells substantially intruding into metal wires by providing a reduced thickness metal wire in the common IMD layer coupled to the MTJ, thereby providing for relatively easy integration of MRAM cells with logic elements.
[0030] FIG. 3 illustrates an exemplary embodiment 300. The spacing between bottom cap layer (Caplx and Cap2x) and top cap layer (Caplx+1 and Cap2x+1) is maintained as in the conventional configuration. The portions elements below the bottom cap layer (IMDx-1 and Mx-1) are also similar to the conventional configuration. To maintain the spacing, a two prong solution is provided to alleviate the problems of insufficient space in IMD layer x for MRAM cells and metal wire Mx.
[0031] First, the metal wire Mx is isolated from the MTJ cell by confining the metal wire Mx to an island adjacent top electrode TE and surrounded by an optional insulator, Cap3x. This configuration improves etch margin and reduces the short circuit danger. Further, the sidewalls of the MTJ stack may also be encapsulated in an insulating layer, Side Capx, to provide additional insulation to the layers of the MTJ stack.
[0032] Second, the size of metal wire Mx is reduced, both in thickness (vertical dimension) and area (which allows confinement to the metal island). The reduced thickness allows vertical room for forming the MRAM cell without a recession of metal wire Mx into the other layers. However, since the overall metal cross-sectional area is reduced, metal wire Mx (i.e. the bit line) may not be capable of supporting the current density required for proper functioning of the MRAM cell. Therefore, the bit line can be formed from a metal connection in layer x+1. A top via top Vx can connect metal Mx to via Vx+1. Metal wire Mx+1 (illustrated with partial thickness) may be coupled to via Vx+1. Metal Mx+1 can then be use as the new bit line having appropriate dimensions for supporting the bit line current density. As a result, the direction of current flow changes from horizontal to vertical in metal wire Mx, and the cross-sectional area of Mx can be configured to be sufficient to support the current density used for normal operation of the MRAM cell. For consistency of illustration, the various "logic" elements are M'X- 1, V'x, M'x, V'x+1 and M'x+1 are illustrated. Further, it will be appreciated from the juxtaposition of logic elements M'x-1, V'x, M'x, V'x+1 and M'x+1 that the exemplary embodiments successfully integrate MRAM cells that are fully compatible with the logic formation process.
[0033] FIGS. 4A-B illustrate schematic top views of two orientations of the MTJ stack according to the embodiment 300. In each of FIGS 4A and 4B, metal wire Mx+1 (not shown) can be generally oriented in the direction of the Y-axis (similar to Mx-1). In FIG. 4A, the MTJ stack is oriented in the X-axis, substantially perpendicular to the direction of Mx+1 and Mx-1. FIG. 4B illustrates an orientation of the MTJ stack in the Y-axis, substantially parallel to of Mx+1 and Mx-1. In both cases, the top electrode TE is formed to confine metal wire Mx to an island, such that metal wire Mx is isolated from the MTJ stack. Additionally, it will be appreciated that the orientation of the MTJ stack may be chosen to be any angle that lies between substantially parallel and substantially perpendicular, such as a 45 degree angle or other acute angle, for example. Flexibility in choosing various angles of orientation of the MTJ stack based on layout dimensions can provide a reduction in field disturbance that is created by current flowing through the metal wires.
[0034] FIG. 5 illustrates a flowchart detailing the process of integrating the MRAM device according to embodiment 300. At block 502, the metal wire Mx-1 in IMD layer x-1 is patterned. Insulating cap layers Caplx and Cap2x in layer x can be deposited next, in block 504. The cap layers Caplx and Cap2x are patterned, in block 506, in order to form via Vx, which is deposited. Next, the bottom electrode BE, is deposited on the cap layers (Caplx and Cap2x) and via Vx, in block 508, along with the deposition of the MTJ stack. The MTJ stack may comprise the various elements, e.g., pinned layer, tunneling barrier layer, free layer, anti-ferromagnetic (AFM) layer and cap layer, as is known in the art. Next, the MTJ stack is patterned and a sidewall cap layer (Side_Capx) is deposited in block 510. Inter-metal-dielectric IMDx is deposited in the regions between MRAM cells and other logic cells in layer x, at block 512. The top of the MTJ stack is subjected to a planarization process (e.g., Chemical Mechanical Polishing (CMP)). Top electrode TE and optional insulating layer Cap3x are deposited in block 514, and the top electrode TE and bottom electrode BE are patterned. Next, in block 516, dielectric IMDx is deposited again, in order to fill open regions of layer x. IMD CMP process can be used for the planarization of IMDx layer. Top via top Vx and metal Mx can then be patterned and deposited in block 518 to form the top via and metal wire Mx, which forms a metal island, as discussed herein. Caplx+1, Cap2x+1, and IMDx+1 are deposited in block 520, and patterned to form via Vx+1. Finally, in block 522 metal Mx+1 formed and coupled to metal Mx through vias top Vx and Vx+1. It will be appreciated that the foregoing process sequences were described solely for illustration and not limitation of the various embodiments. Various sequences may be combined and/or the order rearranged to achieve the configurations illustrated and discussed in relation to FIGS. 3, 4 A and 4B. Further, the corresponding operations for forming the logic elements have not been described, as they are well known in the art, and any compatible process may be used.
[0035] FIG. 6 illustrates another exemplary embodiment, 600. The overlap problem is avoided in this embodiment by lowering the position of the MRAM cell in layer cap2x. This is accomplished by excluding the use of Via Vx to connect bottom electrode BE to metal wire Mx-1 , and forming BE directly on top of metal Mx-1. The positions of cap layers Caplx and Cap2x are altered. Caplx is now formed around Mx-1, and bottom electrode BE is embedded in Cap2x, as shown. Thus, in comparison to conventional designs, the position of the MRAM cell is lowered by approximately the thickness of the two cap layers Caplx and Cap2x. Metal wire Mx can be used as the bit line and can be formed on top of the top electrode TE. As depicted, there may be minimal thinning or recessing of Mx (in the vertical direction). However, generally the thinning will not have a significant impact on performance of the device. Moreover, the metal wire Mx is well isolated by top electrode TE, from the sidewalls and tunneling barrier layer. Accordingly, the danger of a short-circuit taking place is avoided.
[0036] However, in an alternative configuration, any detrimental impact due to the minimal thinning of Mx can be avoided using the configuration illustrated in FIG. 7. In embodiment 700, the metal wire Mx is reduced in thickness in layer x, and connected to metal Mx+1 (not shown) in layer x+1, through via Vx+1. Metal Mx+1 can be sized appropriately to be used as the new bit line, similar to embodiment 300. Accordingly, the recessed size of metal Mx does not affect the performance, because metal Mx+1 can be designed to carry the current load in layer x+1, while the reduction of Mx facilitates the integration of the MRAM cell in layer x. Additionally, similar to the embodiment of FIG.3, it will be appreciated that metal wire Mx is used to facilitate a vertical conduction path which alleviates any negative impact due the thinning of Mx. Also, in this configuration, the metal wire Mx is isolated by top electrode TE, from the sidewalls and tunneling barrier layer and the danger of a short-circuit taking place is avoided.
[0037] The process flow for integration of MRAM cells integrated with logic according to embodiments 600 and 700 is illustrated in FIG. 8. At block 802, Caplx is deposited on IMDx-1 layer. Metal wire Mx-1 in layer x-1 is patterned and deposited, in block 804. Next, the bottom electrode BE is deposited directly on top of Mx-1 followed by deposition of the MTJ stack, in block 806. Then, the MTJ stack is patterned and a sidewall cap Side Capx is deposited in block 808. Inter-metal-dielectric IMDx is deposited in the regions between MRAM cells and other logic cells in layer x, at block 810, and a planarization process is performed on the top of the MTJ stack . Top electrode TE is deposited in block 812, and the top electrode TE is patterned. Cap layer Cap2x is then deposited as shown in FIGS. 6 and 7, embedding BE, in block 814. Next, in block 816, dielectric IMDx is deposited again, in order to fill any open regions of layer x, and a process of Chemical Mechanical Polishing (CMP) can be performed to for planarization. For the embodiment of FIG. 6, Mx and insulating cap layers in layer x+1, (Caplx+1 and Cap2x+1) can be formed, as is well known. For the embodiment of FIG. 7, metal wire Mx is patterned and deposited, in block 818, to form a metal island. Insulating cap layers in layer x+1, (Caplx+1 and Cap2x+1) and IMDx+1 are deposited in block 820, and patterned, in order to form via Vx+1. In block 822, metal Mx+1 is coupled to metal Mx through via Vx+1. Once again, it will be appreciated that the foregoing process sequences were described solely for illustration and not limitation of the various embodiments. Various sequences may be combined and/or the order rearranged to achieve the configurations illustrated and discussed in relation to FIGS. 6 and 7. Further, the corresponding operations for forming the logic elements have not been described, as they are well known in the art, and any compatible process may be used.
[0038] The embodiments disclosed herein overcome problems faced in conventional techniques of integrating MRAM cells with corresponding logic layers. Exemplary embodiments solve the problems of restrictive vertical space for the formation of MRAM cells; problems of overlap between metal wires and the MTJ stack; and potential short-circuits between metal wires and the MTJ stack.
[0039] From the foregoing description, it will be appreciated that the MRAM integration in some exemplary embodiments includes the formation of metal island from Mx and coupling Mx with another metal layer (e.g., Mx+1), as described in embodiment 300. This technique is fully compatible with conventional logic formation processes and requires no change to the formation of the logic elements. Alternate embodiments 600 and 700 include lowering the location of the MTJ stack in layer x, by forming BE directly on top of Mx-1 and altering the position of the bi-layer insulating caps Caplx and Cap2x accordingly, as shown in FIGS. 6-7. Both embodiments 600 and 700 include a modification to the baseline logic formation process, where the position of bi- layer insulating caps (e.g., Caplx and Cap2x) is altered. Embodiment 700 further includes the formation of metal island from Mx and coupling Mx with another metal layer (e.g., Mx+1), as in embodiment 300.
[0040] Those of skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
[0041] Further, those of skill in the art will appreciate that the various illustrative logical blocks, modules, circuits, algorithm, and/or process sequences described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the invention.
[0042] It will be appreciated that semiconductor devices including the MTJ storage elements described herein may be included within a mobile phone, portable computer, hand-held personal communication system (PCS) unit, portable data units such as a personal data assistant (PDA), GPS enabled device, navigation device, settop box, music player, video player, entertainment unit, fixed location data unit such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof. Accordingly, embodiments of the disclosure may be suitably employed in any device which includes active integrated circuitry including memory having MTJ storage elements as disclosed herein.
[0043] The foregoing disclosed devices and method can be designed and can be configured into GDSII and GERBER computer files, stored on a computer readable media. These files may in turn be provided to fabrication handlers who fabricate devices based on these files. The resulting products are semiconductor wafers that are then cut into semiconductor die and packaged into a semiconductor chip. The chips are then employed in devices described herein.
[0044] Accordingly, embodiments can include machine-readable media or computer-readable media embodying instructions which when executed by a processor transform the processor and any other cooperating elements into a machine for performing the functionalities described herein as provided for by the instructions.
[0045] While the foregoing disclosure shows illustrative embodiments, it should be noted that various changes and modifications could be made herein without departing from the scope of the invention as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the embodiments described herein need not be performed in any particular order. Furthermore, although elements of the embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

中文:
[0001]所揭示的实施例是针对磁阻式随机存取存储器(MRAM)单元。更具体来说,示范性实施例是针对磁性隧道结(MTJ)存储元件以及将MTJ存储元件与MRAM单元的逻辑集成相集成的方法。
[0002]磁阻式随机存取存储器(MRAM)是使用磁性元件的非易失性存储器技术。举例来说,自旋转移力矩磁阻式随机存取存储器(STT-MRAM)使用电子,所述电子在穿过一薄膜(自旋滤波器)时变为自旋极化。STT-MRAM也称为自旋转移力矩RAM(STT-RAM)、自旋力矩转移磁化切换RAM(自旋RAM)以及自旋动量转移(SMT-RAM)。
[0003]图1说明常规STT-MRAM位单元100。STT-MRAM位单元100包含磁性隧道结(MTJ)存储元件105(也称为“MTJ堆叠”)、晶体管101、位线102和字线103。MTJ堆叠例如由钉扎层124和自由层120形成,钉扎层124和自由层120中的每一者可保持磁矩或极化,且由绝缘隧穿势垒层122分离。在MTJ堆叠中常规上存在反铁磁(AFM)层和盖层(未图示)。AFM层用以固定钉扎层的磁矩。盖层用作MTJ与金属互连件之间的缓冲层。可通过在特定方向上施加电流以使得钉扎层和自由层的极性大体上对准或相反来反转自由层的极化。穿过MTJ的电路径的电阻取决于钉扎层和自由层的极化的对准而变化。如已知的那样,此电阻变化可用以对位单元100进行编程和读取。STT-MRAM位单元100还包含源极线104、读出放大器108、读取/写入电路106和位线参考107。所属领域的技术人员将了解如此项技术中已知的存储器单元100的操作和构造。
[0004]在存储器装置的开发中,MRAM单元通常与各种其它逻辑门和例如晶体管、电容器、金属线等电子组件集成。因此,希望制造MTJ元件的工艺保持与集成电路的制造所固有的限制相容。然而,众所周知,半导体技术缩放在集成电路制造中涉及的所有组件上不是均匀的。举例来说,垂直互联存取(通常称为“通孔”)的金属线宽度和大小从一代到下一代缩放大约70%。然而,金属层间电介质(IMD)厚度缩放比70%小得多,因为扩散盖层无法如此快地缩放。因此,电容器以慢得多的速度缩减。更具体来说,MTJ单元的高度的缩减甚至更慢,且与集成电路中的其它电子组件相比,缩放在现有技术水平下几乎是不存在的。
[0005]不同组件的缩放的不成比例的速度带来了集成电路设计和制造中的各种挑战。关于涉及MRAM单元的使用的电路,存在与具有相对不改变的MRAM大小的快速缩小到电子组件的集成相关联的许多问题。为了本文论述的目的,将并非MRAM单元的一部分的例如晶体管、金属线、电容器、通孔等电子组件大体上称为“逻辑元件”,且将其集成工艺称为“逻辑工艺”。将MRAM元件的集成工艺大体上称为“MRAM工艺”。希望MRAM工艺与相关的逻辑工艺兼容。因此,将MRAM工艺嵌入逻辑工艺流程中将是有益的。
[0006]图2中说明包含至少一个MRAM单元的存储器装置的横截面图。展示特定装置层“x”、下方的层“x-1”和上方的层“x+1”的元件。并置地说明逻辑元件和MRAM组件。逻辑元件大体上由分别在层x和x-1中的金属线M′x/Mx和M′x-1/Mx-1、层x中的通孔V′x、层x中的绝缘层Cap1x和Cap2x以及层x+1中的绝缘层Cap1x+1和Cap2x+1表示。MRAM组件包括形成于顶部电极(TE)与底部电极(BE)之间的MTJ堆叠(例如MTJ105)、分别在层x和x-1中的金属线Mx和Mx-1(例如组成位线102和源极线104)、金属间电介质层IMDx和IMDx-1、层x中的通孔Vx,以及层x中的绝缘层Cap1x和Cap2x和层x+1中的绝缘层Cap1x+1和Cap2x+1。绝缘盖层用作用于金属线的扩散势垒层。各种盖层可由已知绝缘体形成,例如由例如SiC、SiN膜和类似物等材料形成。此外将了解,常规的材料和处理技术可用于本文讨论的各种逻辑、金属和IMD元件。
[0007]继续参见图2,L2表示包含底部电极BE、MTJ堆叠和顶部电极TE的MRAM单元的高度。大体上,邻近层中的金属线之间的垂直距离是可用于形成MRAM单元的最大空间。因此,层x中的MRAM单元必须包含在金属线Mx和Mx-1内。然而,如图2所示,此可用的垂直空间还由例如通孔、绝缘层和共同IMD层等元件共享。考虑到由这些元件消耗的垂直空间,L1表示可用于MRAM单元的金属层之间的有效垂直空间。技术缩放的趋势揭示了层之间的垂直空间正在快速缩小。然而,如上所述,盖层的厚度并未以相同速度缩减且缩放速度较慢。此外,如所说明,可利用双层绝缘结构以便平衡由底部电极BE引入的机械应力,从而对可用空间施加另外的限制。
[0008]因此,用于MRAM单元的形成的可用垂直空间L1小于MRAM单元的实际高度L2。因此存在MRAM单元侵入到金属线Mx中的重叠,如图所示。所述侵入产生若干问题。首先,在金属Mx与MTJ堆叠的侧壁和/或隧穿势垒层之间产生短路的危险。在具有高密度的MRAM单元的装置中此问题可能加剧,因为填充于多个MRAM单元之间的薄IMD可能不足以在蚀刻和金属化工艺期间保护单元的侧壁。而且,双层绝缘顶盖的进入升高了MTJ元件的垂直位置,进而增加对金属Mx的侵入。
[0009]大体上,MRAM高度不受进一步缩减的影响。因此,金属线Mx的厚度需要减小且金属图案应小于顶部电极TE,以便避免侵入。因为顶部电极TE是导体层,所以MTJ元件上方的金属线的薄化并非不利的,因为其充当局部连接。另外,MTJ单元之间的金属线存取可在IMD填充物具有例如接缝等缺陷的情况下造成金属线之间的短路。因此,此项技术中需要技术和设备,其中MRAM单元可以与逻辑形成工艺兼容的方式集成在存储器装置中。
[0010]示范性实施例是针对用于改善MRAM单元的布局和在共同层中与逻辑的集成的设备和方法。
[0011]举例来说,示范性实施例包含一种半导体装置,其包括:磁性隧道结(MTJ)存储元件,其经配置以与逻辑元件一起安置于共同金属层间电介质(IMD)层中;以及所述共同IMD层中耦合到所述MTJ存储元件的减小厚度的金属线,其厚度小于所述逻辑元件的对应金属线。
[0012]另一实施例可包含一种形成半导体装置的方法,其包括:在共同金属层间电介质(IMD)层中与逻辑元件一起形成磁性隧道结(MTJ)存储元件;以及在所述共同IMD层中形成耦合到所述MTJ存储元件的减小厚度的金属线,所述减小厚度的金属线厚度小于所述逻辑元件的对应金属线。
[0013]另一实施例可包含一种半导体装置,其包括:磁性隧道结(MTJ)存储装置,其与逻辑装置一起形成于金属层间电介质(IMD)层中;以及所述共同IMD层中耦合到所述MTJ存储装置的用于导电的减小厚度的装置,所述减小厚度的装置厚度小于所述逻辑装置的对应导电装置。
[0014]另一实施例可包含一种形成半导体装置的方法,其包括:用于在共同金属层间电介质(IMD)层中与逻辑元件一起形成磁性隧道结(MTJ)存储元件的步骤;以及用于在所述共同IMD层中形成耦合到所述MTJ存储元件的减小厚度的金属线的步骤,所述减小厚度的金属线厚度小于所述逻辑元件的对应金属线。
[0015]另一实施例可包含一种形成半导体装置的方法,所述半导体装置包括与逻辑元件一起安置于共同金属层间电介质(IMD)层中的磁性隧道结(MTJ)存储元件,所述方法包括:在所述共同IMD层中的底部电极上沉积包括钉扎层、隧穿势垒层和自由层的MTJ存储元件;图案化所述MTJ存储元件;在所述MTJ存储元件的侧壁上沉积侧壁盖层;在所述MTJ存储元件上沉积顶部电极;图案化所述顶部电极和所述底部电极;沉积所述共同IMD层的一部分;在所述顶部电极上沉积第二金属线;图案化所述第二金属线以形成小于所述顶部电极的金属岛状物;沉积所述共同IMD层的另一部分;在所述共同IMD层上沉积第二盖层以使所述共同IMD层与顶部IMD层分离;以及在所述顶部IMD层中形成第三金属线,其中所述第三金属线耦合到所述第二金属线。
[0016]另一实施例可包含一种形成半导体装置的方法,所述半导体装置包括与逻辑元件一起安置于共同金属层间电介质(IMD)层中的磁性隧道结(MTJ)存储元件,所述方法包括:形成包括第一部分和第二部分的第一盖层;图案化所述第二部分以形成用于底部电极的开口;沉积所述底部电极,使得所述底部电极与所述第一部分中的第一金属线接触;在所述底部电极上沉积MTJ存储元件;在所述MTJ存储元件的侧壁上沉积侧壁盖层;在所述MTJ存储元件上沉积顶部电极;在所述顶部电极上沉积第二金属线,其中所述第二金属线与所述逻辑元件的对应金属线相比具有减小的厚度;沉积所述共同IMD层的至少一部分;以及在所述共同IMD层上沉积第二盖层以使所述共同IMD层与顶部IMD层分离。
[0018]图1是具有MTJ存储元件的常规MRAM电路的说明。
[0019]图2是包括逻辑元件和MRAM单元的常规存储器装置的横截面图。
[0020]图3是包含与逻辑集成的MRAM单元的示范性实施例的横截面图。
[0022]图5详细说明形成根据示范性实施例的包含MRAM单元的存储器装置的过程流程。
[0023]图6说明包含与逻辑集成的MRAM单元的另一示范性实施例。
[0024]图7说明包含与逻辑集成的MRAM单元的又一示范性实施例。
[0025]图8详细说明形成根据另一示范性实施例的包含MRAM单元的存储器装置的过程流程。
[0026]以下针对具体实施例的描述和相关附图中揭示各种实施例的方面。在不脱离本发明的范围的情况下可设想替代实施例。另外,将不详细描述或者将省略各种实施例的众所周知的元件,以便不混淆各种实施例的相关细节。
[0028]本文使用的术语是仅用于描述特定实施例的目的且不希望限制实施例。如本文使用,单数形式“一”和“所述”既定也包含复数形式,除非上下文清楚地另外指示。将进一步了解,术语“包括”和/或“包含”在本文中使用时指定所陈述特征、整数、步骤、操作、元件和/或组件的存在,但不排除一个或一个以上其它特征、整数、步骤、操作、元件、组件和/或其群组的存在或添加。
[0029]将了解,关于常规技术,在半导体集成电路中难以用与逻辑工艺兼容的方式来集成形成MRAM单元的工艺。示范性实施例通过如下方式有益地避免了MTJ单元大体上侵入金属线中的问题:在共同IMD层中提供耦合到MTJ的减小厚度的金属线,进而提供MRAM单元与逻辑元件的相对容易的集成。
[0030]图3说明示范性实施例300。如常规配置中那样维持底部盖层(Cap1x和Cap2x)与顶部盖层(Cap1x+1和Cap2x+1)之间的间距。底部盖层下方的部分元件(IMDx-1和Mx-1)也类似于常规配置。为了维持间距,提供双尖解决方案以减轻用于MRAM单元和金属线Mx的IMD层x中的不足空间的问题。
[0031]首先,通过将金属线Mx限定到邻近于顶部电极TE且由任选的绝缘体Cap3x包围的岛状物来使金属线Mx与MTJ单元隔离。此配置改善了蚀刻裕量且减少了短路危险。此外,MTJ堆叠的侧壁也可囊封在绝缘层Side_Capx中以对MTJ堆叠的层提供额外绝缘。
[0032]其次,在厚度(垂直尺寸)和面积(允许限定到金属岛状物)上减小金属线Mx的大小。减小的厚度允许用于形成MRAM单元的垂直空间,而无需金属线Mx凹入到其它层中。然而,由于总体金属横截面积减小,因此金属线Mx(即,位线)可能不能支持MRAM单元的适当工作所需的电流密度。因此,位线可由层x+1中的金属连接形成。顶部通孔top_Vx可将金属Mx连接到通孔Vx+1。金属线Mx+1(以部分厚度说明)可耦合到通孔Vx+1。金属Mx+1可随后用作具有用于支持位线电流密度的适当尺寸的新位线。因此,电流的方向在金属线Mx中从水平改变为垂直,且Mx的横截面积可经配置以足以支持用于MRAM单元的正常操作的电流密度。为了说明的一致性,说明各种“逻辑”元件M′X-1、V′x、M′x、V′x+1和M′x+1。此外,从逻辑元件M′x-1、V′x、M′x、V′x+1和M′x+1的并置将了解到,示范性实施例成功地集成了与逻辑形成工艺完全兼容的MRAM单元。
[0033]图4A到4B说明根据实施例300的MTJ堆叠的两个定向的示意性俯视图。在图4A和4B中的每一者中,金属线Mx+1(未图示)可大体上定向于Y轴的方向上(类似于Mx-1)。在图4A中,MTJ堆叠定向于X轴上,大体上垂直于Mx+1和Mx-1的方向。图4B说明MTJ堆叠在Y轴上的定向,大体上平行于Mx+1和Mx-1的定向。在两种情况下,形成顶部电极TE以将金属线Mx限定到岛状物,使得金属线Mx与MTJ堆叠隔离。另外将了解,可将MTJ堆叠的定向选择为位于大体上平行与大体上垂直之间的任何角度,例如45度角或其它锐角。基于布局尺寸而选择MTJ堆叠的各种定向角度的灵活性可提供因电流流过金属线而产生的场干扰的减少。
[0034]图5说明详述根据实施例300的集成MRAM装置的工艺的流程图。在框502处,将IMD层x-1中的金属线Mx-1图案化。在框504中,接着可沉积层x中的绝缘盖层Cap1x和Cap2x。在框506中将盖层Cap1x和Cap2x图案化,以便形成沉积的通孔Vx。接着,在框508中,连同MTJ堆叠的沉积一起在盖层(Cap1x和Cap2x)和通孔Vx上沉积底部电极BE。MTJ堆叠可包括各种元件,例如钉扎层、隧穿势垒层、自由层、反铁磁(AFM)层和盖层,如此项技术中已知。接着,在框510中图案化MTJ堆叠且沉积侧壁盖层(Side_Capx)。在框512处,在MRAM单元与层x中的其它逻辑单元之间的区中沉积金属间电介质IMDx。MTJ堆叠的顶部经受平面化工艺(例如,化学机械抛光(CMP))。在框514中沉积顶部电极TE和任选的绝缘层Cap3x,且将顶部电极TE和底部电极BE图案化。接着,在框516中,再次沉积电介质IMDx,以便填充层x的开口区。IMD CMP工艺可用于IMDx层的平面化。随后可在框518中图案化且沉积顶部通孔top_Vx和金属Mx以形成顶部通孔和金属线Mx,其形成如本文讨论的金属岛状物。在框520中沉积Cap1x+1、Cap2x+1和IMDx+1,且对其进行图案化以形成通孔Vx+1。最终,在框522中,形成金属Mx+1且通过通孔top_Vx和Vx+1将其耦合到金属Mx。将了解,描述上述工艺序列仅用于说明而不是限制各种实施例。可组合各种序列和/或可重新布置次序以实现关于图3、4A和4B说明和讨论的配置。此外,尚未描述用于形成逻辑元件的对应操作,因为其是此项技术中众所周知的,且可使用任何兼容的工艺。
[0035]图6说明另一示范性实施例600。在此实施例中通过降低层cap2x中的MRAM单元的位置来避免重叠问题。这是通过不使用通孔Vx将底部电极BE连接到金属线Mx-1而是直接在金属Mx-1的顶部上形成BE来实现的。更改盖层Cap1x和Cap2x的位置。Cap1x现在在Mx-1周围形成,且底部电极BE嵌入在Cap2x中,如图示。因此,与常规设计相比,MRAM单元的位置降低了大约两个盖层Cap1x和Cap2x的厚度。金属线Mx可用作位线且可形成于顶部电极TE的顶部上。如所描绘,可存在Mx的最小薄化或凹入(垂直方向上)。然而,大体来说薄化将不会对装置的性能具有显著影响。而且,金属线Mx通过顶部电极TE与侧壁和隧穿势垒层良好地隔离。因此,避免了短路发生的危险。
[0036]然而,在替代配置中,使用图7中说明的配置可避免由于Mx的最小薄化带来的任何有害影响。在实施例700中,金属线Mx在层x中的厚度减小,且通过通孔Vx+1连接到层x+1中的金属Mx+1(未图示)。金属Mx+1可经适当设定大小以用作新位线,类似于实施例300。因此,金属Mx的凹入大小不影响性能,因为金属Mx+1可经设计以载运层x+1中的电流负载,而Mx的减小促进了层x中的MRAM单元的集成。另外,类似于图3的实施例,将了解,金属线Mx用以促进垂直传导路径,其减轻了由于Mx的薄化带来的任何消极影响。而且,在此配置中,金属线Mx通过顶部电极TE与侧壁和隧穿势垒层隔离,且避免了短路发生的危险。
[0037]图8中说明根据实施例600和700与逻辑集成的MRAM单元的集成的工艺流程。在框802处,在IMDx-1层上沉积Cap1x。在框804中图案化且沉积层x-1中的金属线Mx-1。接着,在框806中,直接在Mx-1的顶部上沉积底部电极BE且随后沉积MTJ堆叠。接着,在框808中图案化MTJ堆叠且沉积侧壁盖Side_Capx。在框810处在MRAM单元与层x中的其它逻辑单元之间的区中沉积金属间电介质IMDx,且在MTJ堆叠的顶部上执行平面化工艺。在框812中沉积顶部电极TE,且图案化顶部电极TE。在框814中,随后如图6和7所示沉积盖层Cap2x,从而嵌入BE。接着,在框816中,再次沉积电介质IMDx,以便填充层x的任何开口区,且可执行化学机械抛光(CMP)工艺以用于平面化。对于图6的实施例,如众所周知,可形成Mx和层x+1中的绝缘盖层(Cap1x+1和Cap2x+1)。对于图7的实施例,在框818中图案化且沉积金属线Mx以形成金属岛状物。在框820中沉积层x+1中的绝缘盖层(Cap1x+1和Cap2x+1)以及IMDx+1,且进行图案化以便形成通孔Vx+1。在框822中,将金属Mx+1通过通孔Vx+1耦合到金属Mx。再次,将了解,描述上述工艺序列仅用于说明而不是限制各种实施例。可组合各种序列和/或可重新布置次序以实现关于图6和7说明和讨论的配置。此外,尚未描述用于形成逻辑元件的对应操作,因为其是此项技术中众所周知的,且可使用任何兼容的工艺。
[0038]本文揭示的实施例克服了集成MRAM单元与对应逻辑层的常规技术中面临的问题。示范性实施例解决了用于形成MRAM单元的有限垂直空间的问题、金属线与MTJ堆叠之间的重叠问题,以及金属线与MTJ堆叠之间的潜在短路。
[0039]从以上描述将了解,在一些示范性实施例中,MRAM集成包含从Mx形成金属岛状物且将Mx与另一金属层(例如,Mx+1)耦合,如实施例300中描述。此技术与常规逻辑形成工艺完全兼容且不需要对逻辑元件的形成的改变。替代实施例600和700包含通过如下方式降低层x中的MTJ堆叠的位置:直接在Mx-1的顶部上形成BE,且相应地更改双层绝缘盖Cap1x和Cap2x的位置,如图6到7所示。实施例600和700均包含对基线逻辑形成工艺的修改,其中更改双层绝缘盖(例如,Cap1x和Cap2x)的位置。实施例700进一步包含从Mx形成金属岛状物且将Mx与另一金属层(例如,Mx+1)耦合,如实施例300中那样。
[0040]所属领域的技术人员将了解,可使用多种不同技艺和技术中的任一种来表示信息和信号。举例来说,可通过电压、电流、电磁波、磁场或磁性粒子、光场或光学粒子或者其任何组合来表示整个以上描述中可能参考的数据、指令、命令、信息、信号、位、符号和码片。
[0041]此外,所属领域的技术人员将了解,结合本文所揭示的实施例描述的各种说明性逻辑块、模块、电路、算法和/或过程序列可实施为电子硬件、计算机软件或所述两者的组合。为了清楚说明硬件与软件的这种可交换性,上文已大体上在其功能性方面描述了各种说明性组件、块、模块、电路和步骤。将此类功能性实施为硬件还是软件取决于特定应用和对整个系统施加的设计限制。熟练的技术人员可针对每一特定应用以不同方式实施所描述的功能性,但不应将此类实施方案决策解释为造成与本发明范围的脱离。
[0042]将了解,包含本文描述的MTJ存储元件的半导体装置可包含在移动电话、便携式计算机、手持式个人通信系统(PCS)单元、例如个人数据助理(PDA)等便携式数据单元、具有GPS功能的装置、导航装置、机顶盒、音乐播放器、视频播放器、娱乐单元、例如仪表读取设备等固定位置数据单元或者存储或检索数据或计算机指令的任一其它装置或其任一组合内。因此,本发明的实施例可合适地用于包含包括具有如本文揭示的MTJ存储元件的存储器的有源集成电路的任一装置中。
[0043]上文揭示的装置和方法可经设计且可经配置为存储在计算机可读媒体上的GDSII和GERBER计算机文件。这些文件又可提供给基于这些文件而制造装置的制造处置者。所得的产品是半导体晶片,所述半导体晶片接着被切割为半导体裸片且封装为半导体芯片。所述芯片接着用于本文描述的装置中。
[0044]因此,实施例可包含实施指令的机器可读媒体或计算机可读媒体,所述指令在由处理器执行时将处理器和任何其它协作的元件变换为用于执行由所述指令提供的本文描述的功能性的机器。
[0045]虽然上述本发明展示了说明性实施例,但应注意,在不脱离由所附权利要求书界定的本发明的范围的情况下,在本文中可做出各种改变和修改。根据本文描述的实施例的方法权利要求的功能、步骤和/或动作无需以任何特定次序执行。此外,虽然可能以单数形式描述或主张实施例的元件,但复数形式是预期的,除非明确陈述限于单数形式。