English:
[0001] An enhancement mode gallium nitride (GaN) transistor is a recent development. In a GaN transistor, a P-type GaN (pGaN) gate is grown on top of aluminum gallium nitride (AlGaN)/GaN structure to create a positive threshold voltage. Known pGaN gate structures, however, do not have optimized thicknesses, which can lead to dielectric failure if the pGaN structure is too thick, or can lead to an over-conductance of current if the pGaN gate structure is too thin.
[0003] FIG. 2 shows a circuit diagram of the known GaN transistor 1 from FIG. 1. FIG. 2 shows that the dielectric 8 is in parallel with the gate diode. It is to be understood that reference numbers used herein refer to FIGS. 1 and 2.
[0004] FIG. 3 shows how transconductance (input voltage vs output current) varies for gates with pGaN structures having different thicknesses t. As the pGaN thickness t increases, transconductance decreases and gate diode forward drop increases. In particular, FIG. 3 shows that a gate with a pGaN structure having a thickness t of 300 A has a higher transconductance than a gate with a pGaN structure having a thickness t of 600A, which has a higher transconductance than a gate having a pGaN structure with a thickness t of lOOOA. A higher gate voltage is required to fully enhance the devices that have a thicker pGaN structure. If the gate dielectric fails before the device is fully enhanced, maximum performance of the device cannot be achieved.
[0006] FIG. 5 shows the gate I-V characteristics for a pGaN structure with a thickness t of IOOOA. The data in FIG. 5 shows that the gate having a pGaN structure with a thickness t of IOOOA failed when 8V- 12V was applied to the gate. Thus, a thickness t of 1000 A is too thick for a pGaN structure because the gate behaves like a dielectric. Dielectric failure is catastrophic and can occur before the 2 DEG heteroj unction is fully enhanced or can occur as a result of gate overshoot (shown below) during fast switching.
[0007] FIG. 6 shows the gate I-V characteristics for a pGaN structure having a thickness t of IOOOA. As can be seen in the graph in FIG 3., a gate having a pGaN structure with a thickness t of IOOOA has not fully turned on at 6 volts, which increases the risk of dielectric failure.
[0008] FIG. 7 shows the overshoot associated with a gate. As can be seen from the graph, the fluctuations in voltage can be extreme at the high switching speed shown. If the threshold voltage of the gate is close to the withstand voltage of the dielectric, the dielectric will likely rupture as a result of gate overshoot that may exceed the withstand voltage level. Gates having pGaN structures with thicknesses t much less than the withstand voltage are less likely to be adversely affected by gate overshoot because the voltage applied to activate the gate will not be as close to the withstand voltage, meaning that the gate overshoot is not likely to meet or exceed to the withstand voltage.
[0009] It is apparent from the foregoing that 1000 A is too thick for a pGaN gate structure in an enhancement mode GaN transistor. It would desirable, therefore, to provide an enhancement mode GaN transistor with a pGaN gate that is sufficiently thin to avoid the risk of dielectric failure.
[0010] The present invention is directed to an enhancement mode GaN transistor having a pGaN gate structure thin enough to avoid dielectric failure. In one embodiment, for 5V gate voltage applications, this thickness is in the range of 4OθA to 900 A. In a preferred embodiment, the thickness is 600A. Such thicknesses are thick enough to avoid over-conductance of current.
[0011] FIG. 1 is a cross section of an enhancement mode GaN transistor.
[0012] FIG. 2 is a circuit diagram of an enhancement mode GaN transistor.
[0013] FIG. 3 is a graph showing how transconductance varies for gates of varying thicknesses.
[0014] FIG. 4 is a graph showing the gate P-N junction I- V characteristics for devices with gates of varying thicknesses.
[0015] FIG. 5 shows the gate P-N junction I- V characteristics of a gate having a pGaN structure with a thickness t of lOOOA.
[0016] FIG. 6 is a graph showing the gate P-N junction I- V characteristics for a pGaN structure with a thickness t of IOOOA compared with a structure with a thickness t of 600 A, showing that the device with a IOOOA gate has not turned on (thus allowing current to flow) at 6 volts, which increases the risk of dielectric failure.
[0017] FIG. 7 is a graph showing the overshoot associated with prior art gates.
[0018] The present invention is directed to an enhancement mode GaN transistor having a pGaN gate thickness in the range of 400 A to 9OθA. Such a range is thin enough to avoid dielectric failure. As described below, such a range is also thick enough to avoid the problems associated with pGaN gates that are too thin. In a preferred embodiment, the pGaN gate thickness is 600A.
[0019] The pGaN gate structure is Mg doped and activated to p-type conductivity. In one embodiment, the pGaN gate structure is a semi-insulating GaN that is doped with Mg and compensated with hydrogen.
[0020] As shown in FIG. 4, a gate having a pGaN structure with a thickness of 6OθA is sufficiently thick to conduct a measurable amount of current. FIG. 4 also shows that a gate having a pGaN structure with a thickness t of 300 A conducts an immeasurable amount of current with any amount of positive or negative voltage applied. Thus, a thickness of 3OθA is too thin for a pGaN structure.
[0021] As shown in FIG. 6, a gate with pGaN structure having a thickness of 600 A turned on before dielectric failure occurred, thus avoiding dielectric failure. Dielectric failure is also less likely with a gate having a pGaN structure with a thickness of 6OθA because the gate turns on at a voltage much lower than the withstand voltage of the dielectric, meaning that gate overshoot is less likely to push the gate voltage near the withstand voltage.
[0022] The above gate thicknesses and measurements relate to a device operated at a rated gate voltage of 5 V. Obviously, at lower rated gate voltages, the thickness of the pGaN structure would be correspondingly reduced.

中文:
[0001]近期研发了增强型氮化镓(GaN)晶体管。在GaN晶体管中,在铝镓氮(AlGaN)/GaN结构的顶部上生长P-型GaN(pGaN)栅极以便产生正的阈值电压。但是,已知的pGaN栅极结构不具有最佳的厚度,如果pGaN结构过厚则可导致电介质失效,或者如果pGaN栅极结构过薄则可导致电流的过电导(over-conductance)现象。
[0003]图2示出图1所示的已知GaN晶体管1的电路图。图2示出电介质8与栅极二级管是并联的。应该理解,在此使用的附图标记适用于图1和图2。
[0004]图3示出栅极的跨导(输入电压对输出电流)随着具有不同厚度t的pGaN结构如何变化。当pGaN厚度t增加时,跨导降低并且栅极二级管的正向压降增加。具体的,图3示出具有厚度为300埃的pGaN结构的栅极跨导大于具有厚度为600埃的pGaN结构的栅极跨导,具有厚度为600埃的pGaN结构的栅极跨导大于具有厚度为1000埃的pGaN结构的栅极跨导。需要更高的栅极电压来充分增强具有较厚pGaN结构的器件。如果在器件充分增强之前,栅极电介质失效,则不能够获得器件的最佳性能。
[0006]图5示出具有厚度t为1000埃的pGaN结构的栅极的I-V特性。图5中的数据示出当将8V-12V的电压施加到栅极时,具有厚度t为1000埃的pGaN结构的栅极失效。因为栅极的表现类似于电介质,因此对于pGaN结构而言,1000埃的厚度太厚。电介质失效是灾难性的,且可在二维电子气异质结充分增强之前发生或在快速开关切换的过程中由于栅极过冲(如下所示)而发生。
[0007]图6示出具有厚度t为1000埃的pGaN结构的栅极的I-V特性。从图3中的曲线图可见,具有厚度t为1000埃的pGaN结构的栅极在6伏时不能被完全导通,这就增加了电介质失效的危险。
[0008]图7示出与栅极相关联的过冲。从曲线图中可见,电压波动在所示最高开关切换速度下是最高的。如果栅极的阈值电压与电介质的耐受电压接近,则由于可超过耐受电压水平的栅极过冲,电介质将很可能被破坏。具有比耐受电压低很多的厚度t的pGaN结构的栅极不大可能受到栅极过冲的负面影响,因为施加以便激活栅极的电压将不接近耐受电压,也就意味着栅极过冲不太可能达到或超过耐受电压。
[0009]从前述可以明了,1000埃对于增强型GaN晶体管中的pGaN栅极结构过厚。因此希望提供一种增强型GaN晶体管,具有足够薄以避免电介质失效的pGaN栅极。
[0010]本发明涉及一种具有足够薄以避免电介质失效的pGaN栅极结构的增强型GaN晶体管。在一个实施例中,对于5V栅极电压的应用而言,该厚度在400埃到900埃的范围内。在优选实施例中,该厚度为600埃。这些厚度足够厚以避免电流的过电导(over-conductance)。
[0011]图1是增强型GaN晶体管的横断面视图。
[0012]图2是增强型GaN晶体管的电路图。
[0013]图3是示出对于栅极而言,跨导随着厚度变化而如何变化的曲线图。
[0014]图4是示出具有不同厚度栅极的器件的栅极P-N结I-V特性的曲线图。
[0015]图5示出具有厚度t为1000埃的pGaN结构的栅极的栅极P-N结I-V特性。
[0016]图6是示出具有厚度t为1000埃的pGaN结构与具有厚度t为600埃的结构的栅极P-N结I-V特性的曲线图,该曲线图示出具有1000埃栅极的器件在6V时未被导通(从而允许电流流动),这使得电介质失效的危险增加。
[0017]图7是示出与现有技术栅极相关联的过冲的曲线图。
[0018]本发明涉及具有厚度在400埃至900埃范围内的pGaN结构的增强型GaN晶体管。该范围足够薄以避免电介质失效。如下所述,该范围也足够厚以避免与pGaN栅极过薄相关的问题。在优选实施例中,pGaN栅极厚度为600埃。
[0019]pGaN栅极结构是掺杂镁的并且激活成P-型导电性。在一个实施例中,所述pGaN栅极结构是掺杂镁的且用氢补偿的半绝缘GaN。
[0020]如图4中所示,具有厚度为600埃的pGaN结构的栅极足够厚以便传导可测量的电流量。图4还示出在施加任意量的正压或负压的情况下,具有厚度t为300埃的pGaN结构的栅极传导不可测量的电流量。因此,300埃的厚度对于pGaN结构而言过薄。
[0021]如图6中所示,具有厚度为600埃的pGaN结构的栅极在电介质发生失效之前被导通,因此避免了电介质失效。在具有厚度为600埃的pGaN结构的栅极的情况下,电介质失效不大可能,因为栅极在比电介质的耐受电压低很多的电压下导通,也就意味着栅极过冲不太可能使栅极电压接近耐受电压。
[0022]上述栅极厚度和测量涉及在5V额定栅极电压下工作的器件。显然,在较低的额定栅极电压下,pGaN结构的厚度将相应减小。