English:
[0002] In microelectronic devices, stoichiometric silicon nitride layers are desirably formed, which simultaneously have low stress that is less than 1000 megapascals (MPa), and low hydrogen content that is less than 5 atomic percent. Such films would be useful for a variety of microelectronic applications. Silicon nitride films formed by plasma enhanced chemical vapor deposition (PECVD) may have low stress, but have high hydrogen content, above 15 atomic percent, which can cause reliability problems and poor etch resistance. Films formed by low pressure chemical vapor deposition (LPCVD) have low hydrogen content, but high stress, above 1000 MPa, which can cause device performance problems.
[0003] In described examples, a microelectronic device contains a high performance silicon nitride layer, which is stoichiometric within 2 atomic percent, has a low stress of 600 MPa to 1000 MPa, and has a low hydrogen content, less than 5 atomic percent. The high performance silicon nitride layer is formed by an LPCVD process. The LPCVD process uses ammonia and dichlorosilane gases in a ratio of 4 to 6, at a pressure of 150 millitorr to 250 millitorr, and at a temperature of 800°C to 820°C.
[0004] FIG. 1 depicts an LPCVD furnace in an example process of forming a high performance silicon nitride on microelectronic devices and FIG. 1A is an expanded view of the silicon nitride layer formed on the microelectronic devices within the furnace of FIG. 1.
[0005] FIG. 2 is a cross section of an example semiconductor device with a high performance silicon nitride layer.
[0006] FIG. 3 A and FIG. 3B are cross sections of the semiconductor device of FIG. 2, depicted in key stages of formation.
[0008] FIG. 5 A and FIG. 5B are cross sections of the integrated circuit of FIG. 4, depicted in key stages of fabrication.
[0009] FIG. 6A and FIG. 6B are cross sections of an example microelectronic mechanical system (MEMS) device with a high performance silicon nitride layer, depicted in key stages of fabrication.
[0010] The figures are not drawn to scale. Some acts may occur in different orders and/or concurrently with other acts or events. Not all illustrated acts or events are required to implement a methodology in accordance with example embodiments.
[0011] A high performance silicon nitride layer, which is stoichiometric within 2 atomic percent, has a low stress of 600 MPa to 1000 MPa, and has a low hydrogen content, less than 5 atomic percent, is formed by an LPCVD process. The LPCVD process uses ammonia and dichlorosilane gases in a ratio of 4 to 6, at a pressure of 150 millitorr to 250 millitorr, and at a temperature of 800°C to 820°C. The combination of stoichiometry, low stress and low hydrogen content were not expected to be provided by the disclosed process conditions, and were discovered during investigations of LPCVD processes. For the purposes of this disclosure, stoichiometric silicon nitride has a silicon:nitrogen atomic ratio of 3 :4.
[0012] FIG. 1 depicts an LPCVD furnace in an example process of forming a high performance silicon nitride on microelectronic devices. The LPCVD furnace 100 holds the microelectronic devices 102 on substrates, such as semiconductor wafers, in a boat 104. The boat 104 is held in a reaction chamber 106 of the LPCVD furnace 100. The reaction chamber 106 is heated to a temperature of 800°C to 820°C by heating elements 108 of the LPCVD furnace 100 disposed around the reaction chamber 106. Ammonia (NH3) and dichlorosilane (DCS) gases are introduced into the reaction chamber 106 at a ratio of 4 to 6. Pressure inside the reaction chamber 106 is maintained at 150 millitorr to 250 millitorr by an exhaust system 110, such as including a combination of an exhaust pump and an adjustable exhaust valve. As shown in the expanded view of FIG. 1 A, the high performance silicon nitride layer 112 is formed on the microelectronic devices 102 by reaction of nitrogen in the ammonia and silicon in the dichlorosilane. Formation of the high performance silicon nitride layer 112 is continued until a desired thickness is attained. Subsequently, flows of the ammonia and dichlorosilane are ended and the microelectronic devices 102 are extracted from the LPCVD furnace 100.
[0013] Formation of the high performance silicon nitride layer 112 by maintaining the temperature at 800°C to 820°C, the ratio of ammonia to dichlorosilane at 4 to 6, and the pressure at 150 millitorr to 250 millitorr advantageously provides a silicon:nitrogen atomic ratio within 2 percent of the ratio 3 :4, a low stress of 600 MPa to 1000 MPa, and a low hydrogen content of less than 5 atomic percent. The high performance silicon nitride layer 112 may have an index of refraction of 2.0 to 2.1 as a result of being formed by the process described in reference to FIG. 1. Further, the high performance silicon nitride layer 112 may have a dielectric breakdown strength of greater than 12 megavolts per centimeter (MV/cm), which may advantageously contribute to higher reliability of the microelectronic devices 102. Increasing the ratio of ammonia to dichlorosilane reduces the stoichiometry and the dielectric breakdown strength, which may disadvantageous^ contribute to lower reliability. Reducing the ratio of ammonia to dichlorosilane disadvantageously increases the stress. Reducing the temperature and increasing the pressure also disadvantageously increases the stress.
[0014] FIG. 2 is a cross section of an example semiconductor device with a high performance silicon nitride layer. The semiconductor device 200 is formed on a semiconductor substrate 202, such as a stack gallium nitride and aluminum gallium nitride epitaxial layers, and possibly other III-V layers. A cap layer 204 of gallium nitride is disposed on the substrate 202. A high performance silicon nitride layer 206 is disposed on the cap layer 204 on two sides of a gate 208 and between a source 210 and drain 212 of a gallium nitride field effect transistor (GaN FET) 214 of the semiconductor device 200. The gate 208 may partially overlap the high performance silicon nitride layer 206. For example, the high performance silicon nitride layer 206 may be 10 nanometers to 20 nanometers thick.
[0015] Contact metal 216 is disposed on the substrate 202 in the source 210 and drain 212. A field plate dielectric layer 218 is disposed over the gate 208 and the high performance silicon nitride layer 206, around the contact metal 216. Source metal 220 makes an electrical connection to the contact metal 216 in the source 210 and overlaps the gate 208 and extends partway to the drain 212 over the field plate dielectric layer 218 to provide a field plate for the GaN FET 214. Drain metal 222 makes electrical connection to the contact metal 216 in the drain 212. Additional dielectric layers and metal layers may be formed to provide low resistance connections to the GaN FET 214.
[0016] The low stress of the high performance silicon nitride layer 206 advantageously improves on-state current in the GaN FET 214 compared to a GaN FET with a silicon nitride layer having high stress. The low hydrogen content of the high performance silicon nitride layer 206 advantageously reduces charge trapping and improves reliability of the GaN FET 214 compared to a GaN FET with a silicon nitride layer having a high hydrogen content.
[0017] FIG. 3 A and FIG. 3B are cross sections of the semiconductor device of FIG. 2, depicted in key stages of formation. Referring to FIG. 3A, the cap layer 204 is formed on the substrate 202 by an epitaxial process. A portion of the cap layer 204 and the substrate 202 may be removed to provide a lateral isolation boundary 224 for the GaN FET 214. The high performance silicon nitride layer 206 is formed on the cap layer 204 by an LPCVD process as described in reference to FIG. 1. An etch mask 226 is formed over the high performance silicon nitride layer 206 to cover areas for the high performance silicon nitride layer 206 of the completed GaN FET 214 of FIG. 2. The etch mask 226 may include photoresist formed by a photolithographic process, and may possibly include an anti -reflection layer.
[0018] Referring to FIG. 3B, a reactive ion etch (RIE) process 228 containing fluorine (F) removes the high performance silicon nitride layer 206 where exposed by the etch mask 226. Reactant gas flows and a pressure in the RIE process 228 may be adjusted to provide sloped edges on the high performance silicon nitride layer 206 as depicted in FIG. 3B. Subsequently, the etch mask 226 is removed, such as by an ash process. Fabrication of the semiconductor device 200 is continued to provide the structure of FIG. 2. The method described in reference to FIG. 3A and FIG. 3B advantageously provides the patterned high performance silicon nitride layer 206 with the desired properties of low stress and low hydrogen content.
[0019] FIG. 4 is a cross section of an example integrated circuit with a high performance silicon nitride layer. The integrated circuit 400 is formed on a semiconductor substrate 402 such as a silicon wafer. The integrated circuit 400 includes a p-channel metal oxide semiconductor (PMOS) transistor 404 and/or an n-channel metal oxide semiconductor (NMOS) transistor 406. Field oxide 408 is disposed in the substrate 402 to laterally isolate the PMOS transistor 404 and the NMOS transistor 406.
[0020] The PMOS transistor 404 is disposed in an n-type well 410 extending below the field oxide 408. The PMOS transistor 404 includes a gate dielectric layer 412 on the n-type well 410 and a gate 414 on the gate dielectric layer 412. Offset spacers 416 are disposed on lateral surfaces of the gate 414. P-type source and drain regions 418 are disposed in the n-type well 410 on two sides of the gate 414. The source and drain regions 418 include source/drain extensions 420 extending under the gate 414 and deep source/drain regions 422 adjacent to the gate 414.
[0021] Gate sidewall spacers 424 are disposed adjacent to the gate 414, on the offset spacers 416. The gate sidewall spacers 424 include one or more layers of high performance silicon nitride, with low stress and low hydrogen content. Metal silicide 426 is disposed on the source and drain regions 418 adjacent to the gate sidewall spacers 424, and possibly on the gate 414. The gate sidewall spacers 424 provide lateral separation between a channel layer immediately below the gate dielectric layer 412 and the deep source/drain regions 422, and between the channel layer and the metal silicide 426 on the source and drain regions 418. The high performance silicon nitride in the gate sidewall spacers 424 may be within 10 nanometers of the semiconductor substrate 402. The low stress of the gate sidewall spacers 424 may advantageously reduce stress in the channel layer, and so improve an on-state current and/or an off-state current of the PMOS transistor 404. The low hydrogen content of the gate sidewall spacers 424 may advantageously improve reliability of the PMOS transistor 404.
[0022] Similarly, the NMOS transistor 406 is disposed in a p-type well 428 extending below the field oxide 408. The NMOS transistor 406 includes a gate dielectric layer 430 on the p-type well 428 and a gate 432 on the gate dielectric layer 430. Offset spacers 434 are disposed on lateral surfaces of the gate 432. N-type source and drain regions 436 are disposed in the p-type well 428 on two sides of the gate 432. The source and drain regions 436 include source/drain extensions 438 extending under the gate 432 and deep source/drain regions 440 adjacent to the gate 432. Gate sidewall spacers 442 including one or more high performance silicon nitride layers are disposed adjacent to the gate 432. The gate sidewall spacers 424 of the PMOS transistor 404 and the gate sidewall spacers 424 of the NMOS transistor 406 may possibly have a same layer structure as a result of being formed concurrently. Metal silicide 444 is disposed on the source and drain regions 436 adjacent to the gate sidewall spacers 442, and possibly on the gate 432. The NMOS transistor may accrue advantages from the low stress and low hydrogen content of the gate sidewall spacers 442 similar to those described in reference to the PMOS transistor 404.
[0023] FIG. 5 A and FIG. 5B are cross sections of the integrated circuit of FIG. 4, depicted in key stages of fabrication. Referring to FIG. 5A, the p-type source/drain extensions 420 are formed by implanting p-type dopants into the n-type well 410 using the gate 414 and offset spacers 416 of the PMOS transistor 404 as an implant mask, so that the source/drain extensions 420 do not extend completely under the gate 414. Similarly, the n-type source/drain extensions 438 are formed by implanting n-type dopants into the p-type well 428 using the gate 432 and offset spacers 434 of the NMOS transistor 406 as an implant mask, so that the source/drain extensions 438 do not extend completely under the gate 432. The substrate 402 is subsequently annealed to activate the implanted dopants.
[0024] A high performance silicon nitride layer 450 is formed over the gate 414, the offset spacers 416 and the source/drain extensions 420 of the PMOS transistor 404 and over the gate 432, the offset spacers 434 and the source/drain extensions 438 of the NMOS transistor 406. The high performance silicon nitride layer 450 is formed by an LPCVD process as described in reference to FIG. 1, which provides at least a partially conformal layer as depicted in FIG. 5 A, so that a thickness of the high performance silicon nitride layer 450 on vertical surfaces of the offset spacers 416 and 434 is sufficient to form the gate sidewall spacers 424 and 442 of FIG. 4, respectively.
[0025] Referring to FIG. 5B, an anisotropic RIE process 452 containing fluorine (F) removes the high performance silicon nitride layer 450 of FIG. 5A over horizontal surfaces of the gate 414 and the source/drain extensions 420 of the PMOS transistor 404 and over the gate 432 and the source/drain extensions 438 of the NMOS transistor 406, leaving the high performance silicon nitride layer 450 to form the gate sidewall spacers 424 on the vertical surfaces of the offset spacers 416 of the PMOS transistor 404, and to form the gate sidewall spacers 442 on the vertical surfaces of the offset spacers 434 of the NMOS transistor 406. The conformal aspect of the LPCVD process to form the high performance silicon nitride layer 450 enables the gate sidewall spacers 424 and 442 to be formed without a photolithographic operation, advantageously reducing fabrication cost and complexity of the integrated circuit 400.
[0026] FIG. 6A and FIG. 6B are cross sections of an example microelectronic mechanical system (MEMS) device with a high performance silicon nitride layer, depicted in key stages of fabrication. Referring to FIG. 6A, the MEMS device 600 is formed in a silicon substrate 602, such as a single crystalline silicon wafer. A cavity 604 is formed in the substrate 602 leaving material of the substrate 602 above the cavity 604 in the form of a cantilevered element 606 such as a perforated membrane 606. The perforated membrane 606 may be part of a sensor, such as a thermal sensor or a microphone, or may be part of an actuator such as a speaker. It may be desirable to partially isolate the perforated membrane 606 from adjacent regions 608 of the substrate 602. A layer of high performance silicon nitride 610 is formed on the perforated membrane 606 and interior surfaces of the cavity 604 and adjacent regions 608 of the substrate 602. The high performance silicon nitride layer 610 is formed by an LPCVD process as described in reference to FIG. 1 to have low stress and a low hydrogen content, which provides at least a partially conformal layer, so that the high performance silicon nitride layer 610 covers all exposed surfaces of the perforated membrane 606 as depicted in FIG. 6A. Due to restricted access to the cavity 604 through the perforated membrane 606, the high performance silicon nitride layer 610 is thicker on a top surface of the perforated membrane 606 outside of the cavity 604 than on a bottom surface of the perforated membrane 606 facing the cavity 604. The low stress of the high performance silicon nitride layer 610 advantageously reduces deformation of the perforated membrane 606 due to the unequal thickness on the top and bottom surfaces of the perforated membrane 606.
[0027] Referring to FIG. 6B, the high performance silicon nitride layer 610 is removed from a portion of the substrate 602 in the regions 608 adjacent to the perforated membrane 606. The MEMS device 600 is immersed in a crystallographic wet etch solution 612, such as a potassium hydroxide solution, which removes silicon from the substrate 602 in the areas exposed by the high performance silicon nitride layer 610 along crystal planes of the substrate 602 to form isolation cavities 614 adjacent to the perforated membrane 606. The low hydrogen content of the high performance silicon nitride layer 610 advantageously provides etch resistance to the crystallographic wet etch solution 612 at a desired thickness. The MEMS device 600 is subsequently rinsed and dried. The high performance silicon nitride layer 610 may be left in place in the completed MEMS device 600 or may be removed during subsequent fabrication processes.

中文:
[0002]在微电子器件中,期望形成化学计量的氮化硅层,其同时具有低于1000兆帕(MPa)的低应力(stress)和小于5原子百分比(at%)的低氢含量。这种薄膜将用于各种微电子应用中。通过等离子体增强化学气相沉积(PECVD)形成的氮化硅薄膜可具有低应力但是具有15at%以上的高氢含量,其能引起可靠性问题和差的抗蚀刻性。通过低压化学气相沉积(LPCVD)形成的薄膜具有低氢气含量但是具有1000MPa以上的高应力,其能引起器件性能问题。
[0003]在描述的示例中,微电子器件包含高性能氮化硅层,其化学计量在2原子百分比(at%)以内,具有600MPa至1000MPa的低应力,并且具有小于5at%的低氢含量。通过LPCVD工艺形成高性能氮化硅层。LPCVD工艺使用氨气和二氯甲硅烷气体,其比率为4比6,压力为150毫托至250毫托,且温度为800°C至820°C。
[0004]图1描述在微电子器件上形成高性能氮化硅的示例过程中的LPCVD炉(furnace),并且图1A为在图1的炉内的微电子器件上形成的氮化硅层的扩展视图。
[0005]图2是具有高性能氮化硅层的示例半导体器件的横截面图。
[0006]图3A和图3B是图2的半导体器件的横截面图,在形成的关键阶段中描述的。
[0008]图5A和图5B是图4的集成电路的横截面图,在制造的关键阶段中描述的。
[0009]图6A和图6B是具有高性能氮化硅层的示例微机电系统(MEMS)器件的横截面图,在制造的关键阶段中描述的。
[0010]附图不按照比率绘制。一些动作(act)可能以不同的顺序发生和/或与其他的动作或事件同时发生。并非所有说明的动作或事件都需要根据示例实施例来实现方法。
[0011]通过LPCVD工艺形成高性能氮化硅层,其化学计量在2原子百分比以内,具有600MPa到1000MPa的低应力,并且具有小于5原子百分比的低氢含量。LPCVD工艺使用氨气和二氯甲硅烷气体,其比率为4比6,压力为150毫托到250毫托,且温度为800°C到820°C。没有预期通过公开的工艺条件提供化学计量、低应力和低氢含量的组合,而该组合在LPCVD工艺研究中发现。针对本公开的目的,化学计量的氮化硅具有3:4的硅:氮的原子比。
[0012]图1描述在微电子器件上形成高性能氮化硅的示例过程中的LPCVD炉。LPCVD炉100包含(hold)在舟(boat)104中的衬底(例如半导体晶片)上的微电子器件102。舟104包含在LPCVD炉100的反应室106中。通过放置在反应室106周围的LPCVD炉100的加热元件108加热反应室106至800°C到820°C的温度。以4:6的比率将氨气(NH3)和二氯甲硅烷(DCS)气体引进到反应室106。在反应室106内部的压力通过排气系统110(例如包括排气泵和可调节排气阀的结合)维持在150毫托到250毫托。如图1A的扩展视图中所示,通过氨气中的氮与二氯甲硅烷中的硅的反应,在微电子器件102上形成高性能氮化硅层112。高性能氮化硅层112的形成继续进行,直到达到所需厚度。随后,停止氨气和二氯甲硅烷的气流,并且从LPCVD炉100中提取微电子器件102。
[0013]通过维持温度在800°C到820°C,氨气和二氯甲硅烷的比率为4比6,以及150毫托至250毫托的压力的高性能氮化硅层112的形成有利地提供在2%以内的硅:氮原子比,其具有3:4的比率,600MPa到1000MPa的低应力,和小于5原子百分比的低氢含量。通过参照图1所描述的工艺形成的高性能氮化硅层112可具有2.0到2.1的折射率。此外,高性能氮化硅层112可具有大于12兆伏每厘米(MV/cm)的介电击穿强度,这可有利地促进微电子器件102的更高的可靠性。增加氨气和二氯甲硅烷的比率降低化学计量和介电击穿强度,这可能不利地导致较低的可靠性。减小氨气和二氯甲硅烷的比率不利地增大应力。减小温度和增加压力也不利地增大应力。
[0014]图2是具有高性能氮化硅层的示例半导体器件的横截面图。在半导体衬底202(例如堆叠的氮化镓和氮化铝镓外延层,且可能地其他的III-V层)上形成半导体器件200。在衬底202上布置氮化镓的盖层(cap layer)204。在半导体器件200的氮化镓场效应晶体管(GaNFET)的栅极208的两侧上以及源极210和漏极212之间的盖层204上布置高性能氮化硅层206。栅极208可与高性能氮化硅层206部分重叠。例如,高性能氮化硅层206可能是10纳米到20纳米厚。
[0015]在衬底202上,在源极210和漏极212中布置触点金属216。围绕触点金属216在栅极208和高性能氮化硅层206上方布置场板介电层218。源极金属220与源极210中的触点金属216电连接,并且与栅极208重叠,并中途延伸到场板介电层218上方的漏极212,以为GaNFET 214提供场板。漏极金属222与漏极212中的触点金属216电连接。可以形成附加的介电层和金属层以提供与GaN FET 214的低电阻连接。
[0016]高性能氮化硅层206的低应力与具有高应力的氮化硅层的GaN FET相比有利地改善GaN FET 214中的开态(on-state)电流。高性能氮化硅层206的低氢含量与具有高氢含量的氮化硅层的GaN FET相比有利地减小电荷陷阱(trapping)和改善GaN FET 214的可靠性。
[0017]图3A和图3B是图2的半导体器件的横截面图,在形成的关键阶段中描述的。参照图3A,通过外延工艺在衬底202上形成盖层204。可移除盖层204的一部分和衬底202,以为GaNFET 214提供横向隔离边界224。通过LPCVD工艺在盖层204上形成高性能氮化硅层206,如参考图1所述。在高性能氮化硅层206上方形成蚀刻掩膜226来覆盖图2中完成的GaN FET 214的高性能氮化硅层206的区域。蚀刻掩膜226可包括通过光刻工艺形成的光刻胶,并且也可能包括抗反射层。
[0018]参考图3B,含氟(F)的反应离子刻蚀(RIE)过程228将在由蚀刻掩膜226暴露处的高性能氮化硅层206移除。可调整在RIE过程228中的反应气体流量和压力,以在高性能氮化硅层206上提供斜边/倾斜边缘,如图3B中描述的。随后,移除蚀刻掩膜226,例如通过灰化工艺。半导体器件200的制造被继续用于提供图2的结构。参照图3A和图3B中描述的方法有利地提供了具有低应力和低氢含量的期望性能的图案化高性能氮化硅层206。
[0019]图4是具有高性能氮化硅层的示例集成电路的横截面图。在半导体衬底402如硅晶片上形成集成电路400。集成电路400包括p-沟道金属氧化物半导体(PMOS)晶体管404和/或n-沟道金属氧化物半导体(NMOS)晶体管406。在衬底402中布置场氧化物408来横向隔离PMOS晶体管404和NMOS晶体管406。
[0020]在n型阱410中布置PMOS晶体管404,其在场氧化物408下面延伸。PMOS晶体管404包括在n型阱410上的栅极介电层412和在栅极介电层412上的栅极414。在栅极414的横向表面上布置偏移隔离层(offset spacer)416。在栅极414的两侧上在n型阱410中布置p型源极和漏极区418。源极和漏极区418包括源极/漏极扩展420和临近栅极414的深源极/漏极区422,源极/漏极扩展420在栅极414下方延伸。
[0021]在偏移隔离层416上邻近栅极414布置栅极侧壁隔离层424。栅极侧壁隔离层424包括具有低应力和低氢含量的高性能氮化硅的一个或更多个层。在源极和漏极区418上邻近栅极侧壁隔离层424以及可能在栅极414上布置金属硅化物426。栅极侧壁隔离层424在栅极介电层412正下方的沟道层和深源极/漏极区422之间,及在沟道层和源极/漏极区418上的金属硅化物426之间提供横向分离。栅极侧壁隔离层424中的高性能氮化硅可在半导体衬底402的10纳米以内。栅极侧壁隔离层424的低应力可有利地减小沟道层中的应力,并且因此改善PMOS晶体管404的开态电流和/或关态电流。栅极侧壁隔离层424的低氢含量有利地改善PMOS晶体管404的可靠性。
[0022]类似地,在p型阱428内布置NMOS晶体管406,其在场氧化物408下面延伸。NMOS晶体管406包括在p型阱428上的栅极介电层430和在栅极介电层430上的栅极432。在栅极432的横向表面上布置偏移隔离层434。在栅极432的两侧上在p型阱428内布置n型源极和漏极区436。源极和漏极区436包括源极/漏极扩展438和临近栅极432的深源极/漏极区440,源极/漏极扩展438在栅极432下方延伸。邻近栅极432布置栅极侧壁隔离层442,栅极侧壁隔离层442包括一个或更多个高性能氮化硅层。PMOS晶体管404的栅极侧壁隔离层424和NMOS晶体管406的栅极侧壁隔离层424可能由于同时形成而具有相同的层结构。邻近栅极侧壁隔离层442在源极和漏极区436上,也可能在栅极432上布置金属硅化物444。与参考PMOS晶体管404描述的类似,NMOS晶体管可以从栅极侧壁隔离层442的低应力和低氢含量获得优势。
[0023]图5A和图5B是图4的集成电路的横截面图,在制造的关键阶段中描述的。参照图5A,通过使用PMOS晶体管404的栅极414和偏移隔离层416作为注入掩膜将p-型掺杂剂注入到n-型阱410中形成p-型源极/漏极扩展420,使得源极/漏极扩展420不完全在栅极414下延伸。类似地,通过使用NMOS晶体管406的栅极432和偏移隔离层434作为注入掩膜将n-型掺杂剂注入到p-型阱428中形成n-型源极/漏极扩展438,使得源极/漏极扩展438不完全在栅极432下延伸。随后将衬底402退火以激活注入的掺杂剂。
[0024]高性能氮化硅层450在PMOS晶体管404的栅极414、偏移隔离层416、源极/漏极扩展420上和在NMOS晶体管406的栅极432、偏移隔离层434、源极/漏极扩展438上形成。通过如参照图1描述的LPCVD工艺形成高性能氮化硅层450,其至少部分提供如图5A中描述的共形层,使得在偏移隔离层416和434的垂直表面上的高性能氮化硅层450的厚度足以分别形成图4的栅极侧壁隔离层424和442。
[0025]参照图5B,含氟(F)的各向异性RIE过程452移除图5A中的在PMOS晶体管404的栅极414和源极/漏极扩展420的水平表面上、以及NMOS晶体管406的栅极432和源极/漏极扩展438上的高性能氮化硅层450,留下的高性能氮化硅层450来形成PMOS晶体管404的偏移隔离层416的垂直表面上的栅极侧壁隔离层424和形成NMOS晶体管406的偏移隔离层434的垂直表面上的栅极侧壁隔离层442。LPCVD过程的共形方面形成高性能氮化硅层450,使得在没有光刻操作的条件下形成栅极侧壁隔离层424和442,这样有利地减少集成电路400的制造成本和复杂性。
[0026]图6A和图6B是具有高性能氮化硅层的示例微机电系统(MEMS)器件的横截面图,在制造的关键阶段中描述的。参照图6A,在硅衬底602(例如单晶硅晶片)中形成MEMS器件600。在衬底602中形成腔604,其以悬臂式元件606的形式在腔604上方留下衬底602的材料,例如穿孔膜(perforated membrane)606。穿孔膜606可以是传感器(如热传感器或麦克风)的部分,或可以是致动器(如扬声器)的部分。可期望将穿孔膜606与衬底602的邻近区608部分隔离。在穿孔膜606、腔604的内部表面和衬底602的邻近区608上形成高性能氮化硅层610。通过参考如图1所描述的LPCVD工艺形成高性能氮化硅层610,此高性能氮化硅层具有低应力和低氢含量,其提供至少部分共形层,使得高性能氮化硅层610覆盖如图6A所描述的穿孔膜606所有暴露的表面。由于通过穿孔膜606进入腔604受限制,高性能氮化硅层610在腔604外侧的穿孔膜606的顶部表面上比在面对腔604的穿孔膜606的底部表面上更厚。高性能氮化硅层610的低应力有利地降低由于在穿孔膜606的顶部和底部表面上的不等厚度造成的穿孔膜606的形变。
[0027]参照图6B,在邻近穿孔膜606的区608中从衬底602的一部分移除高性能氮化硅层610。将MEMS器件600浸没在晶体学湿法刻蚀溶液612中,例如氢氧化钾溶液,其沿着衬底602的晶面将在由高性能氮化硅层610暴露的区域中的硅从衬底602移除,来形成邻近穿孔膜606的隔离腔614。高性能氮化硅层610的低氢含量以期望的厚度有利地提供对晶体学湿法刻蚀溶液612的抗蚀刻性。接着冲洗和干燥MEMS器件600。高性能氮化硅层610可留在已完成的MEMS器件600中的适当位置或者可在随后的制造过程中被移除。