English:
[0001] The present invention generally relates to integrated circuit memory devices and, more particularly, to Pseudo Static random access memory (PSRAM) devices operating in a burst access mode ("burst PSRAM").
[0002] In portable applications, such as handheld/wireless devices, the use of low power consuming memory is essential. A PSRAM device meets both low power consumption and high density requirements. A PSRAM, like a conventional dynamic random access memory (DRAM), contains dynamic memory cells but, in terms of interface and packaging, has the appearance of a static random access memory (SRAM). In the PSRAM, a refresh operation that is commonly required to maintain the stored information in dynamic memory cells is facilitated using internal means and, as such, is transparent to a system controller of the memory. Further, a PSRAM may operate in a burst mode. The burst mode enhances the speed of storing and retrieving information (or "data"). In the burst mode, specific functions must occur in a predetermined sequence. Such functions are generally performed in response to command signals produced by a system controller of the PSRAM device. The timing of the command signals is determined by a clock signal (CLK) and is registered either to an edge of the clock signal or occurring a predetermined time after the edge. To further increase data transmission rates, the PSRAM device may operate in a burst mode when an internal address counter increments an initial address to produce serial column locations. Additionally, in the burst mode, the burst PSRAM device may operate in fixed and variable latency modes where a value of the latency determines a minimal number of clock cycles that pass before a valid data output is present on a data bus.
[0003] In a single data-rate (SDR) burst PSRAM device, either a rising edge or a falling edge of the clock signal may be used as a data trigger point for the read and write operations. Herein, such operations are illustratively synchronized with the rising edge of the clock signal. Obtaining a high data transmission rate requires increasing the clock frequency or expanding a width of a system bus of the burst PSRAM device. In a fixed latency mode, burst PSRAM produces the valid data always in the programmed latency regardless of the internal condition of the device. In a variable latency mode, the burst PSRAM devices use a WAIT signal indicating to the system controller when valid data is present on a data bus in a Read cycle and when the memory is ready to accept data in a Write cycle. In the event that a Read or Write cycle collides with the execution of an internal refresh operation, the burst PSRAM asserts a few clock cycles of WAIT states until completion of the refresh operation. Otherwise, the read or write access would take place in the fastest time. The WAIT signal allows the data output and data input functions to take place at optimal time and, as such, increase operational speed of the burst PSRAM device.
[0004] FIG. 8 depicts a series of illustrative timing diagrams of signals which might appear in Read cycle on corresponding transmission lines of system and data buses of the SDR burst PSRAM device operating in a variable latency mode. In FIG. 8, the latency is illustratively equal to 3 clock cycles. Sub-series 802 and 804 include traces of the CLK signal, an Address signal, an Address Valid (ADV) signal, and a Chip Select (CS) signal and relate to a regular Read cycle and the Read cycle performed after the refresh operation, respectively.
[0005] In a double data rate (DDR) SDRAM device, both the rising and falling edges of the clock signal are trigger points for read and write operations. The DDR DRAM device doubles the peak data rate of comparable single data rate (SDR) SDRAM device using the same clock frequency. To address the increased timing accuracy requirements, a differential clock scheme is used in the DDR SDRAM devices. The DDR SDRAM uses a DQS signal which switching phase is edge-aligned with data output in Read cycles and center-aligned with data input in Write cycles to serve as a timing signal for valid data.
[0006] FIGS. 9 and 10 depict a series of illustrative timing diagrams of signals which might appear in Read and Write cycles, respectively, on corresponding transmission lines of system and data buses of a DDR SDRAM device operati ng in a fixed latency mode. In FIGS. 9 and 10, the latency is exemplary equal to 3 clock cycles, complimentary clock signal is shown with broken lines, and NOP, tDQss(nom) and DM correspond to "no operation", respectively. The rising and falling edges of the DQS signal are aligned to the edge of data outputs in Read cycle and to the center of the data inputs in Write cycle, respectively. Before the first valid data inputs or outputs, as well as after the last data inputs or outputs, the DQS signal asserts a logic low state and prepares buffers in the memory or system controller for receiving the data.
[0007] To facilitate a DDR feature in a memory device that is capable of operating in a variable latency mode by using the WAIT signal, such as PSRAM, the memory device needs the signal that may assert functionality of the DQS signal. However, an addition of the DQS signal increases the pin count of the memory and system controller and a width of the system bus, as well as may compromise timing relationship between the data strobe signal and the data.
[0008] Therefore, there is a need in the art for an improved method and circuit configuration for implementing a double data rate feature in a memory device capable of operating in a variable latency mode, such as a burst PSRAM device.
[0009] A method of operating a double data rate (DDR) burst PSRAM memory device in a variable latency mode in Read cycle and a fixed latency mode in Write cycle or in the variable latency mode in both Read and Write cycles. The method uses a WAIT_DQS signal that combines functions of a data strobe (DQS) signal and a WAIT signal that indicates to a system controller of the DDR burst PSRAM memory device when valid data is present on a data bus in Read cycle and when memory is ready to accept data in Write cycle.
[0010] In one embodiment of the method, the WAIT_DQS signal is initiated by the memory in Read cycle of a variable latency mode and by the system controller in Write cycle of a fixed latency mode.
[0011] In another embodiment of the method, in Write cycle of a variable latency mode, the memory and system controller sequentially initiate the WAIT_DQS signal.
[0014] FIG. 1 depicts a simplified functional block diagram of a DDR Burst PSRAM device in accordance with one embodiment of the present invention;
[0015] FIG. 2 depicts a portion of a system bus of the DDR Burst PSRAM device of FIG. 1 ;
[0016] FIG. 3 depicts a series of illustrative timing diagrams of signals which might appear on corresponding transmission lines of system and data buses of the DDR Burst PSRAM device of FIG. 1 in Read cycle of a variable latency mode;
[0017] FIG. 4 depicts a series of illustrative timing diagrams of signals which might appear on corresponding transmission lines of system and data buses of the DDR Burst PSRAM device of FIG. 1 in Write cycle of a fixed latency mode;
[0018] FIG. 5 depicts a series of illustrative timing diagrams of signals which might appear on corresponding transmission lines of system and data buses of the DDR Burst PSRAM device of FIG. 1 in Write cycle of a variable latency mode in one embodiment of the present invention;
[0019] FIG. 6 depicts a series of illustrative timing diagrams of signals which might appear on corresponding transmission lines of system and data buses of the DDR Burst PSRAM device of FIG. 1 in Write cycle of a variable latency mode in another embodiment of the present invention; and
[0020] FIG. 7 depicts a series of illustrative timing diagrams of signals which might appear on corresponding transmission lines of system and data buses of the DDR Burst PSRAM device of FIG. 1 in Write cycle of a variable latency mode in yet another embodiment of the present invention;
[0021] FIG. 8 depicts a series of illustrative timing diagrams of signals which might appear in Read cycle on corresponding transmission lines of system and data buses of a SDR burst PSRAM device operating in a variable latency mode;
[0022] FIG. 9 depicts a series of illustrative timing diagrams of signals which might appear in Read cycle on corresponding transmission lines of system and data buses of a DDR SDRAM device operating in a fixed latency mode; and
[0023] FIG. 10 depicts a series of illustrative timing diagrams of signals which might appear in Write cycle on corresponding transmission lines of system and data buses of a DDR SDRAM device operating in a fixed latency mode.
[0025] It is to be noted, however, that the appended drawings illustrate only exemplary embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
[0026] The present invention generally provides methods and circuit configurations for implementing a double data rate feature in memory devices capable of operating in a variable latency mode in Read and/or Write cycles, such as burst PSRAM devices.
[0027] FIG. 1 depicts a simplified functional block diagram of a system 100 using a burst PSRAM device 104. In one embodiment, the system 100 generally comprises a system controller 102, a memory 104, an address/command (i.e., system) bus 106, and a data (i.e., DQ) bus 108. The memory 104 may comprise one or more component memories (discussed below in reference to FIG. 2), where each component memory is coupled to the buses 106 and 108. The system bus 106 may comprise unidirectional and bi-directional transmission lines, while the DQ bus includes bi-directional transmission lines. The system controller 102 is typically coupled to a processor of an external electronic device 110 (e.g., computer, cell phone, and the like) using an application-specific interface 112.
[0028] In one embodiment of the invention, the system bus 106 comprises a bidirectional line 114 (shown in phantom) that transmits a WAIT_DQS signal and a plurality unidirectional transmission lines propagating conventional control and command signals. Such conventional control and command signals comprise, among other such signals, a Clock (CLK) signal, an Address (e.g., 21 -bit address word A20- A0) signal, an Address Valid (ADV) signal, a Write Enable (WE) signal, and a Chip Select (CS) signal (all discussed below in reference to FIGS. 3-7).
[0029] In one embodiment, the WAIT_DQS signal is a 3-state digital signal that combines functions of a WAIT signal and a data strobe (DQS) signal. In the burst memory devices, the WAIT signal is used to indicate to the system controller 102 when valid data is present on the DQ bus 108 in Read cycle and when the memory 104 is ready to accept data from the DQ bus 108 in Write cycle. Correspondingly, the DQS signal is used in the double data rate (DDR) SDRAM devices in Read and Write cycles to serve as a timing signal for valid data on the DQ bus 108. In the present invention, the WAIT and DQS signals are disabled or not provided to the system bus 106.
[0030] To reduce a width (i.e., number of transmission lines) of the system bus 106, the bi-directional line 114 may replace the line that otherwise may be used to transmit the WAIT signal. The bi-directional line 114 may replace the lines transmitting the WAIT signal and the lines transmitting the DQS signal.
[0031] In one embodiment, loading conditions of the bi-directional line 114 are selected to match the loading conditions of the DQ bus 108 and, in operation, facilitate matched timing relationship between the WAITJDQS signal and data. When the WAITJDQS signal is transmitted using a transmitting line that initially was designed to transmit the WAIT signal, no modification in loading conditions may be required for that transmitting line.
[0032] FIG. 2 depicts a portion of the system bus 106 of the system 100 where the memory 104 illustratively comprises a plurality of component memories 200. In FIG. 2, individual component memories are identified using the same reference numeral, except that the suffix "K", where K is an integer from 1 to N, has been added to differentiate between the component memories. The bi-directional line 114 is coupled to terminals 202 and 204« of the system controller 102 and component memories 200κ, respectively. In one exemplary embodiment, the bi-directional line 114 also provides a wired logic-OR connection between the system controller 102 and component memories 200κ- Illustratively, such a wired logic-OR connection may be facilitated using a pull-up resistor 206 that is coupled to a power line 208 of the system 100. In a further exemplary embodiment, the terminals 202 and 204κ may replace terminals of the disabled or not provided WAIT and DQS signals.
[0033] FIGS. 3-7 depict a series of illustrative timing diagrams of signals which might appear on corresponding transmission lines of the system bus 106 and data bus 108 of the DDR SDRAM device of FIG. 1 in Read cycle of a variable latency mode and in Write cycle of fixed and variable latency modes. For illustrative purposes, the same conventional timing relationships between the clock (CLK), Address (A20-A0), Address Valid (ADV#), Write Enable (WE#), and Chip Select (CS#) signals (graphs 1 , 2, 3, 4, and 5, respectively) are shown in FIGS. 3-7. Herein the sign "#" indicates that, in active state, a signal asserts a logic low state. The ADV#, WE#, and CS# signals assert for one clock cycle an active (i.e., logic low) state with an Address (Ai) has been provided on the system bus 106. The CS# signal returns to an inactive (i.e., logic high) state one-half clock cycle from an end of the data burst. In the depicted embodiments, an exemplary burst length is 4, the latency (LAT) in Read and Write cycles of both fixed and variable modes is 2. The Address (Ai) is timed by ADV# and CS# signals, asserted during a first clock cycle, and ignored thereafter in the cycle (i.e. , Read or Write cycle). Address (A20-A0) and data (DQ15-DQ0) signals appear on exemplary 21 -bit address portion of the system bus 106 and the exemplary 16-bit DQ bus 108, respectively. Valid data signals illustratively comprise a sequence (i.e., burst) of 4 data outputs (Read cycle) or data inputs (Write cycle) D0-D3 (graph 7) which are sampled using the WAIT_DQS signal (graph 6). In alternate embodiments, burst length and latency may be each either greater or smaller than in the depicted embodiments, as well as the burst length and latency may be different for Read cycles and Write cycles. In FIGS. 3- 7, the x-axes and y-axes of the respective graphs 1-7 are conventionally not shown.
[0034] FIG. 3 depicts a series of illustrative timing diagrams of signals which might appear on corresponding transmission lines of the system bus 106 and data bus 108 of the DDR burst PSRAM device of FIG. 1 that, in Read cycle, operates in a variable latency mode. Specifically, FIG. 3 depicts the CLK, A20-A0, ADV#, CS#, WAIT_DQS, and DQ15-DQ0 signals (graphs 1-3, 5-7, respectively) versus time. The WE# signal asserts logic high in Read cycle and, as such, not shown. The WAITJDQS signal is initiated (i.e., driven) by the memory 104 or one of the component memories (e.g., component memory 200κ) and comprises a preamble period T(1), a data validation period T(2), and a postamble period T(3). Prior to the preamble period T(1 ), the WAITJDQS signal asserts a high-impedance state. During the preamble period T(1), the WAITJDQS signal asserts logic low for a duration of one clock cycle on a clock signal that precedes the clock signal when the latency LAT elapses or the memory is ready to output the first valid data output DO. The logic low level of the WAIT_DQS signal indicates to the system controller 102 that valid data outputs D0-D3 are coming. Then, during the following data validation period T(2), the WAIT_DQS signal is edge- aligned to data output and toggles between logic low and logic high at every phase of data outputs to enable the system controller 102 to strobe valid data. Finally, during the postamble period T(3), the WAIT_DQS signal asserts logic low for a duration of one clock cycle following the output of last valid data D3 and then goes back into the high- impedance state through the remainder of the Read cycle. Since the burst PSRAM operates in the variable latency mode, the time (i.e., clock cycle) when the first valid data may appear on the data bus may be delayed from the given latency, depending on the internal situation of the burst PSRAM device, such as, e.g. , a refresh operation.
[0035] FIG. 4 depicts a series of illustrative timing diagrams of signals which might appear on corresponding transmission lines of the system bus 106 and data bus 108 of the DDR burst PSRAM device of FIG. 1 that, in Write cycle, operates in a fixed latency mode. In the fixed latency mode, the first data input DO is always needed at the same time after a burst command regardless of internal state of the memory 104. Specifically, FIG. 4 depicts the CLK, A20-A0, ADV#, WE#, CS#, WAIT_DQS, and DQ15-DQ0 signals (graphs 1-7, respectively) versus time. The WAITJDQS signal is initiated by the system controller 102 and comprises a preamble period T(4), a data validation period T(5), and a postamble period T(6). Prior to the preamble period T(4), the WAITJDQS signal stays in the high-impedance state. During the preamble period T(4), the WAITJDQS signal asserts logic low on a clock signal that precedes the clock signal when the latency LAT elapses or the memory is ready to ready to first valid data input DO. The low level of the WAIT_DQS signal prepares the memory 102 (or component memory 200κ) to data inputs D0-D3. Then, during the following data validation period T(5), the WAITJDQS signal is center-aligned to data inputs and toggles between logic low and logic high to enable the memory 104 (or component memory 200κ) to strobe valid input data. Finally, during the postamble period T(6), the WAIT_DQS signal asserts logic low for a duration of one clock cycle following the input of last valid data D3, and then asserts logic high through the remainder of the Write cycle.
[0036] FIG. 5 depicts a series of illustrative timing diagrams of signals which might appear on corresponding transmission lines of the system bus 106 and data bus 108 of the DDR burst PSRAM device of FIG. 1 that, in Write cycle, operates in a variable latency mode in one embodiment of the present invention. Specifically, FIG. 5 depicts the CLK, A20-A0, ADV#, WE#, CS#, WAIT_DQS, and DQ15-DQ0 signals (graphs 1-7, respectively) versus time. The WAITJDQS signal comprises an indicating period T(7), a preamble period T(8), a data validation period T(9), and a postamble period T(10). During the indicating period T(7), the WAITJDQS signal is initiated by the memory 104 or one of the component memories 200 (e.g., component memory 200«). Then, during the preamble period T(8), data validation period T(9), and postamble period T(10), the WAITJDQS signal is initiated by the system controller 102. Prior to the indicating period T(7), the WAITJDQS signal stays in the high-impedance state. During the indicating period T(7), the WAITJDQS signal asserts logic low for a duration of one clock cycle starting two clock cycles prior to beginning of the preamble period T(8). Once the system controller 102 samples a low state of the WAITJDQS signal, it starts, after 1 clock cycle, the preamble period, and the WAITJDQS signal asserts logic low for a duration of one clock cycle on a clock signal. In this embodiment, the timing diagram of the WAITJDQS signal and operations during the data validation period T(9) and postamble period T(10) are similar to the ones during the corresponding periods T(5) and T(6), respectively, described above in reference to FIG. 4.
[0037] FIG. 6 depicts a series of illustrative timing diagrams of signals which might appear on corresponding transmission lines of the system bus 106 and data bus 108 of the DDR burst PSRAM device of FIG. 1 that, in Write cycle, operates in a variable latency mode in another embodiment of the present invention. In this embodiment, the timing diagrams 1-7 and operations are similar to the ones discussed above in reference to FIG. 5, however, during the indicating period, the WAITJDQS signal asserts logic low for a duration of one clock cycle starting one clock cycle prior to beginning of the preamble period T(8). As such, the memory 104 (or component memory 200«) may be ready to data inputs D0-D3 approximately one clock cycle faster.
[0038] FIG. 7 depicts a series of illustrative timing diagrams of signals which might appear on corresponding transmission lines of the system bus 106 and data bus 108 of the DDR burst PSRAM device of FIG. 1 that, in Write cycle, operates in a variable latency mode in yet another embodiment of the present invention. In this embodiment, the timing diagrams 1-7 and operations are similar to the ones discussed above in reference to FIG. 5, however, the WAITJDQS signal asserts logic low when the chip select signal (CS#) is activated and asserts logic high when the memory 104 (or component memory 200κ) is ready to data input until beginning of the preamble period T(8).
[0039] Although the foregoing discussion referred to DDR burst PSRAM devices, other memory devices (e.g., DRAM devices) and integrated circuits can benefit from the invention.
[0040] While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

中文:
[0001]本发明通常涉及集成电路存储装置,特别是涉及以脉冲串访问模式(“脉冲串PSRAM”)工作的伪静态随机存取存储器(PSRAM)装置。
[0002]在诸如手提/无线装置的移动应用中,使用低能耗的存储器是必要的。PSRAM装置能同时满足低能耗和高密度的需求。PSRAM,类似于常规动态随机存储器(DRAM),包含动态存储单元,但由于接口和封装的原因,其具有静态随机存取存储器(SRAM)的外观。在PSRAM中,通常需要用于维持动态存储单元中保存的信息的刷新操作由于使用内部装置而变得容易,且同样地,刷新操作对于存储器系统控制器是透明的。另外,PSRAM可以以脉冲串模式运行。脉冲串模式提高了存储和检索信息(或者“数据”)的速度。在脉冲串模式中,具体的功能必须以预定顺序产生。这些功能通常响应由PSRAM装置的系统控制器所产生的命令信号执行。命令信号的时序由时钟信号(CLK)来确定,并被对齐至时钟信号边缘,或者在边缘之后的预定时间出现。为了进一步提升数据传输速率,当内部地址计数器增加初始地址来产生串行列位置时,PSRAN装置可以以脉冲串模式运行。此外,在脉冲串模式中,脉冲串PSRAM装置可以固定和可变等待时间模式下运行,其中等待时间的值确定了在有效数据输出出现在数据总线上之前所经过的时钟周期的最小数。
[0003]在单数据率(SDR)脉冲串PSRAM装置中,时钟信号的上升沿或者下降沿可以作为读和写操作的数据触发点。这里,这些操作示意性地与时钟信号上升沿同步。为了得到高数据传输率,需要提高时钟频率或者扩展脉冲串PSRAM装置的系统总线的宽度。在固定的等待时间模式下,脉冲串PSRAM总在被编程的等待时间中产生有效数据,而不管装置的内部条件如何。在可变等待时间模式下,脉冲串PSRAM装置使用WAIT信号指示系统控制器读周期中有效数据何时出现在数据总线上并且写周期中存储器何时准备接收数据。如果读或写周期与内部刷新操作相冲突,则脉冲串PSRAM声明几个时钟周期的WAIT状态直至刷新操作完成为止。否则,读或者写访问在最快的时间内发生。WAIT信号允许数据输出和数据输入功能在最佳的时间发生,并且同样地,提高脉冲串PSRAM装置的操作速度。
[0004]图8描述了一系列说明性的信号时序图,这些信号可能于读周期中出现在运作在可变等待时间模式下的SDR脉冲串PSRAM装置的系统和数据总线的相应传输线上。在图8中,等待时间示意性地等于3个时钟周期。子系列802和804包括CLK信号、地址信号、地址有效(ADV)信号、和芯片选择(CS)信号的轨迹,且其分别涉及规则的读周期和刷新操作后执行的读周期。
[0005]在双数据率(DDR)SDRAM装置中,时钟信号的上升沿和下降沿都是读和写操作的触发点。DDR DRAM装置使得用同一时钟频率的可比信号数据率(SDR)SDRAM装置的峰值数据率加倍。为了解决增加的时序精确度要求,在DDR SDRAM装置中使用差分时钟方案。DDR SDRAM使用DQS信号,其切换相位在读周期中与数据输出边沿对准,在写周期中与数据输入中心对准来作为有效数据的时序言号。
[0006]图9和10描述了一系列的示范性信号时序图,在读和写周期中,该信号可能出现在以固定等待时间模式下运作的DDR SDRAM装置的系统和数据总线的相应传输线上。在图9和10中,等待时间示例性地为3个时钟周期,互补时钟信号用虚线表示,NOP,tDQSS(nom)和DM分别相当于“无操作”。DQS信号的上升沿和下降沿分别在读周期中与数据输出的边沿、以及在写周期中与数据输入的中心对准。在第一有效数据输入或输出之前,以及在最后数据输入或输出之后,DQS信号声明逻辑低状态,并在存储器或者系统控制器中准备缓冲器以便接收数据。
[0007]为了通过使用WAIT信号有助于能够在可变等待时间模式下工作的存储器装置中的DDR特性,例如PSRAM,存储器装置需要可以声明DQS信号的功能性的信号。但是,附加DQS信号增加了存储器和系统控制器的管脚数量以及系统总线的宽度,同时可能牺牲了数据选通信号和该数据之间的时序关系。
[0008]因此,现有技术需要一个改进的方法和电路配置,以此在以可变等待时间模式运行的存储器装置中实现双倍数据率特性,例如脉冲串PSRAM装置。
[0009]一种在读周期中以可变等待时间模式、在写周期以固定等待时间模式、或者在读和写周期中以可变等待时间模式运行双数据率(DDR)脉冲串PSRAM存储器装置的方法。该方法使用结合了数据接通(DQS)信号和WAIT信号功能的WAIT DQS信号,其中WAIT信号指示DDR脉冲串PSRAM存储器装置的系统控制器在读周期中有效数据何时出现在数据总线上以及在写周期中存储器何时准备好接收数据。
[0010]本方法的一个实施例中,WAIT_DQS信号在可变等待时间模式的读周期中由存储器启动,在固定等待时间模式写周期中由系统控制器启动。
[0011]本方法的另一个实施例中,可变等待时间模式的写周期中,存储器和系统控制器依次地启动WAIT_DQS信号。
[0014]图1描述了根据本发明一个实施例的简化的DDR脉冲串PSRAM装置的功能框图;
[0015]图2描述了图1中DDR脉冲串PSRAM装置的一部分系统总线;
[0016]图3描述了一系列说明性信号时序图,在可变等待时间模式的读周期中,其可能出现在图1的DDR脉冲串PSRAM装置的系统和数据总线的相应传输线上;
[0017]图4描述了一系列说明性信号时序图,在固定等待时间模式的写周期中,其可能出现在图1的DDR脉冲串PSRAM装置系统和数据总线的相应传输线上;
[0018]图5描述了一系列说明性信号时序图,在本发明一个实施例中的可变等待时间模式的写周期中,其可能出现在图1的DDR脉冲串PSRAM装置系统和数据总线的相应传输线上;
[0019]图6描述了一系列说明性信号时序图,在本发明另一个实施例的可变等待时间模式的写周期中,其可能出现在图1的DDR脉冲串PSRAM装置系统和数据总线的相应传输线上;和
[0020]图7描述了一系列说明性信号时序图,在本发明又一个实施例中的可变等待时间模式工作的写周期中,其可能出现在图1的DDR脉冲串PSRAM装置系统和数据总线的相应传输线上;
[0021]图8描述了一系列说明性信号时序图,其可能出现于在可变等待时间模式下工作的SDR脉冲串PSRAM装置的系统和数据总线的相应传输线上的读周期中;
[0022]图9描述了一系列说明性信号时序图,其可能出现于在固定等待时间模式下工作的DDR SDRAM装置的系统和数据总线的相应传输线上的读周期中;和
[0023]图10描述了一系列说明性信号时序图,其可能出现于在固定等待时间模式下工作的DDR SDRAM装置的系统和数据总线的相应传输线上的写周期中。
[0025]然而需要指出,附加图只是阐述了本发明的示范实施例,因此不能认为以此限制了发明的范围,因为本发明允许其他等效的实施例。
[0026]本发明通常提供了在读和/或写周期中可工作于可变等待时间模式下的存储装置中,诸如脉冲串PSRAM装置中,用于实现双倍数据率特性的方法或者电路配置。
[0027]图1描述了使用脉冲串PSRAM装置104的系统100的一个简化功能性方框图。在一个实施例中,系统100通常包括系统控制器102,存储器104,地址/命令(也就是系统)总线106,和数据(也就是DQ)总线108。存储器104可以包含一个或者多个组件存储器(将在下面参考图2进行讨论),其中每个组件存储器都与总线106和108耦合。系统总线106可包含单向和双向传输线,而DQ总线包含双向传输线。系统控制器102典型地通过使用专用接口112与外部电子装置(如计算机,蜂窝电话等等)的处理器110相耦合。
[0028]在本发明的一个实施例中,系统总线106包含传递WAIT_DQS信号的双向线114(如假想所示)和传播常规控制和命令信号的多条单向传输线。这些常规控制和命令信号包括,尤其是这样的信号,时钟(CLK)信号,地址(如21比特地址字A20-A0)信号,地址有效(ADV)信号,写使能(WE)信号,和芯片选择(CS)信号(所有这些都参考图3-7加以讨论)。
[0029]在一个实施例中,WAIT_DQS信号是3态数字信号,其结合了WAIT信号和数据选通(DQS)信号的功能。在脉冲串存储器装置中,WAIT信号用于指示系统控制器102在读周期中有效数据何时出现在DQ总线108上,以及在写周期中存储器104何时准备好接收来自DQ总线108的数据。相应地,DQS信号在读和写周期中用于双倍数据率(DDR)SDRAM装置中,以作为DQ总线108上有效数据的时序信号。在本发明中,WAIT和DQS信号是禁用的或者不提供给系统总线106。
[0030]为了减小系统总线106的宽度(也就是传输线的数量),双向线114可替代否则可被用于传输WAIT信号的线。双向线114可替代传输WAIT信号的线和传输DQS信号的线。
[0031]在一个实施例中,选择双向线114的负载条件以与DQ总线108的负载条件相匹配,并且在操作中,促进WAIT_DQS信号和数据之间匹配的时序关系。当使用最初设计用来传输WAIT信号的传输线来传输WAIT_DQS信号时,对于该传输线不需要负载条件的任何改变。
[0032]图2描述了系统100的一部分系统总线106,其中存储器104示例性地包含多个组件存储器200。在图2中,使用同样的附图标记加以识别单个组件存储器,除了下标“K”已经被添加以在组件存储器之间进行区分,其中K是从1至N的整数。双向线114分别耦合到系统控制器102和组件存储器200K的端子202和204K。在一个示例实施例中,双向线114也提供了系统控制器102和组件存储器200K之间的连线逻辑OR连接。示意性地,可以使用与系统100的电源线208耦合的上拉电阻206以有助于该连线逻辑OR连接。在另一示例性实施例中,端子202和204K可以替代禁用或者未提供的WAIT和DQS信号的端子。
[0033]图3-7描述了一系列说明性信号时序图,在可变等待时间模式的读周期中,以及在固定和可变等待时间模式的写周期中,其可能出现在图1的DDRSDRAM装置的系统总线106和数据总线108的相应传输线上。为了说明的目的,在图3-7中示出了时钟(CLK)、地址(A20-A0)、地址有效(ADV#)、写使能(WE#)和芯片选择(CS#)信号(分别由图1,2,3,4,5表示)之间的相同常规时序关系。这里的符号“#”表示在活动状态下,信号声明了逻辑低状态。在系统总线106上已提供对于一个时钟周期声明带有地址(Ai)的活动(也就是逻辑低)状态的ADV#、WE#、和CS#信号。CS#信号从数据脉冲串的结束半个周期返回至不活动(也就是逻辑高)状态。在描述的实施例中,示范的脉冲串长度是4,在固定和可变模式的读和写周期的等待时间(LAT)为2。地址(Ai)由ADV#和CS#信号定时,在第一时钟周期期间被声明,并且在该周期中之后被忽略(也就是,读或写周期)。地址(A20-A0)和数据(DQ15-DQ0)信号分别出现在示范的16位DQ总线108和系统总线106的示例的21位地址部分上。有效数据信号示例性地包含4个数据输出(读周期)或者数据输入(写周期)D0-D3的序列(也就是脉冲串)(图形7),其使用WAIT_DQS信号(图形6)进行采样。在可选实施例中,脉冲串长度和等待时间可以均比所述实施例的更大或更小,同时脉冲串长度和等待时间对于读周期和写周期可以是不同的。在图3-7中,各个图形1-7的x轴和y轴通常并不显示。
[0034]图3描述了一系列说明性信号时序图,其可能出现于在读周期中,在可变等待时间模式下工作的图1的DDR脉冲串PSRAM装置的系统总线106和数据总线108的相应传输线上。特别地,图3描述了CLK,A20-A0,ADV#,CS#,WAIT_DQS和DQ15-DQ0信号(分别由图1-3,5-7表示)相对于时间的关系。WE#信号在读周期中声明逻辑高,并且同样地未显示。WAIT_DQS信号由存储器104或者组件存储器之一(如组件存储器200K)启动(也就是驱动),并且包含前同步周期T(1),数据验证周期T(2)和后同步周期T(3)。在前同步周期T(1)之前,WAIT_DQS信号声明高阻抗状态。在前同步周期T(1)中,在经过了等待时间LAT或存储器准备好输出第一有效数据输出D0时领先于该时钟信号的时钟信号上,WAIT_DQS信号声明逻辑低持续一个时钟周期的时间。WAIT_DQS信号的逻辑低电平向系统控制器102指示出有效数据输出D0-D3正来到。然后,在随后的数据有效期间(T2)中,WAIT_DQS信号与数据输出边沿对准,且于数据输出的每个相位上在逻辑低和逻辑高之间切换,使得系统控制器102选通有效数据。最后,在后同步周期T(3)中,WAIT_DQS信号跟随最后有效数据D3的输出之后声明逻辑低持续一个时钟周期的时间,然后通过剩下的读周期返回到高阻状态。因为脉冲串PSRAM在可变等待时间模式下工作,当第一有效数据可能出现在数据总线上时,根据脉冲串PSRAM装置的内部情形,例如刷新操作,该时间(也就是时钟周期)可能从给定的等待时间被延迟。
[0035]图4描述了一系列说明性信号时序图,其可能出现于写周期中在固定的等待时间模式下工作的图1的DDR脉冲串PSRAM装置的系统总线106和数据总线108相应的传输线上。在固定的等待时间模式下,在脉冲串命令后的同一时间总是需要第一数据输入D0,而不管存储器104的内部状态如何。特别地,图4描述了CLK,A20-A0,ADV#,WE#,CS#,WAIT_DQS和DQ15-DQ0信号(分别由图1-7表示)与时间的关系。WAIT_DQS信号由系统控制器102启动,并包含前同步周期T(4),数据验证周期T(5),和后同步周期T(6)。在前同步周期T(4)之前,WAIT_DQS信号处于高阻抗状态。在前同步周期T(4)中,在经过了等待时间LAT或者存储器准备好第一有效数据输入D0时,WAIT_DQS信号在领先于该时钟信号的时钟信号上声明逻辑低。WAIT_DQS信号的低电平为数据输入D0-D3准备存储器102(或者组件存储器200K)。然后,在随后的数据验证期间(T5)中,WAIT_DQS信号与数据输入中心对准,且在逻辑低和逻辑高之间切换,使得存储器104(或者组件存储器200K)选通有效输入数据。最后,在后同步周期T(6)中,WAIT_DQS信号跟随最后有效数据D3的输入之后声明逻辑低持续一个时钟周期的时间,然后通过剩下的写周期声明逻辑高。
[0036]图5描述了本发明一个实施例的一系列说明性信号时序图,其可能出现于写周期中在可变等待时间模式下工作的图1的DDR脉冲串PSRAM装置系统总线106和数据总线108的相应传输线上。特别地,图5描述了CLK,A20-A0,ADV#,WE#,CS#,WAIT_DQS和DQ15-DQ0信号(分别由图1-7表示)与时间的关系。WAIT_DQS信号包含指示周期T(7),前同步周期T(8),数据验证周期T(9),和后同步周期T(10)。在指示周期T(7)内,WAIT_DQS信号由存储器104或者任一组件存储器200(如组件存储器200K)启动。然后,在前同步周期T(8)、数据验证周期T(9)、和后同步周期T(10)内,WAIT_DQS信号由系统控制器102启动。在指示周期T(7)之前,WAIT_DQS信号处于高阻抗状态。在指示周期T(7)内,WAIT_DQS信号于前同步周期T(8)开始前的两个时钟周期开始,声明逻辑低持续一个时钟周期的时间。一旦系统控制器102采样到WAIT_DQS信号的低状态,在一个时钟周期之后,它开始前同步周期,WAIT_DQS信号于一个时钟周期上声明逻辑低持续一个时钟周期的时间。在该实施例中,数据验证周期T(9)和后同步周期T(10)期间的WAIT_DQS信号时序图和工作分别与相应周期T(5)和T(6)类似,如上参考图4所述。
[0037]图6描述了本发明另一个实施例中的一系列说明性信号时序图,其可能出现于写周期中在可变等待时间模式下工作的图1的DDR脉冲串PSRAM装置的系统总线106和数据总线108的相应传输线上。在该实施例中,虽然时序图1-7和操作与如上参考图5所述相似,但是在指示周期期间,WAIT_DQS信号于前同步周期T(8)开始前的一个时钟周期开始,声明逻辑低持续一个时钟周期的时间。因此,存储器104(或者组件存储器200K)可以为数据输入D0-D3作好准备大约加快一个时钟周期。
[0038]图7描述了本发明又一个实施例中的一系列说明性信号时序图,其可能出现于写周期中在可变等待时间模式下工作的图1的DDR脉冲串PSRAM装置的系统总线106和数据总线108的相应传输线上。在该实施例中,时序图1-7和操作与如上参考图5所述相似,但当芯片选择信号(CS#)被激活时,WAIT_DQS信号声明逻辑低,当存储器104(或者组件存储器200K)直到前同步周期T(8)开始时才为数据输入做好准备时声明逻辑高。
[0039]虽然前面的论述是参考DDR脉冲串PSRAM装置的,其他存储器装置(如DRAM装置)和集成电路也可以受益于本发明。
[0040]虽然前面的论述是根据本发明的实施例进行的,本发明的其他和进一步的实施例也可以在不脱离本发明基本范围的情况下设计出来,本发明范围由随后的权利要求确定。