English:
[0002] The microelectronic industry is under intense pressure to produce high performance devices in small package sizes at continually decreasing costs. Smart phones, portable computers, digital cameras, portable music and media players, and many other electronic products require faster memory devices with more capacity. As such, memory device manufacturers in particular seek reliable, low-cost processes for fabricating high- performance devices.
[0003] Memory devices may have large arrays of memory cells, and reducing the size of individual memory cells provides a concomitant increase in the bit density of the memory devices. Cross-point memory cells are located in the vertical overlap regions between word lines and bit lines. Cross-point memory cells include structures that undergo a stable and detectable change when exposed to a current between a word line and a corresponding bit line. Because cross-point memory cells are located in the overlap regions between bit lines and word lines, these memory cells may theoretically be formed to extremely small dimensions.
[0004] One concern of manufacturing cross-point memory cells is that the smallest features of the structures can be difficult to form using photolithography processes. For example, it is difficult to pattern the wafers to form the drain structures of a cross-point memory cell because these features are so small that they cannot be formed reliably using existing photolithography processes. It is also difficult to photo-pattern gate structures that completely surround the individual pillars in high density cross-point memory arrays. Moreover, it is very expensive to form very small features using photolithography processes because these processes require expensive equipment and materials. Additional concerns of cross-point memory arrays include reversed leakage current, serial resistance, and accurate control of current-voltage uniformity that are important for multi-level cell configurations. Therefore, it is desired to develop improved methods for forming highly integrated circuitry, and in particular cross-point memory cells, and to develop improved circuitry for such features.
[0005] Figure 1 is flow chart of an embodiment of a method for forming an array of memory cells in accordance with the technology.
[0006] Figure 2A is a cross-sectional view and Figure 2B is a top-plan view of an embodiment of a substrate at a stage of a method for forming an array of memory cells in accordance with the technology.
[0007] Figure 3A is a cross-sectional view and Figure 3B is a top-plan view of an embodiment of a substrate at another stage of a method for forming an array of memory cells in accordance with the technology.
[0008] Figure 4A is a cross-sectional view and Figure 4B is a top-plan view of an embodiment of a substrate at another stage of a method for forming an array of memory cells in accordance with the technology.
[0009] Figure 5A is a cross-sectional view and Figure 5B is a top-plan view of an embodiment of a substrate at another stage of a method for forming an array of memory cells in accordance with the technology.
[0010] Figure 6 A is a cross-sectional view and Figure 6B is a top-plan view of an embodiment of a substrate at another stage of a method for forming an array of memory cells in accordance with the technology.
[0011] Figure 7A is a cross-sectional view and Figure 7B is a top-plan view of an embodiment of a substrate at another stage of a method for forming an array of memory cells in accordance with the technology.
[0012] Figure 8A is a cross-sectional view and Figure 8B is a top-plan view of an embodiment of a substrate at another stage of a method for forming an array of memory cells in accordance with the technology.
[0013] Figures 9A and 9B are a cross-sectional views and Figure 9C is a top-plan view of an embodiment of a substrate at another stage of a method for forming an array of memory cells in accordance with the technology.
[0014] Figure 10 is a cross-sectional view of an embodiment of a substrate at another stage of a method for forming an array of memory cells in accordance with the technology.
[0015] Figure 11 is a cross-sectional view of an embodiment of a substrate at another stage of a method for forming an array of memory cells in accordance with the technology.
[0016] Figure 12 is a cross-sectional view of an embodiment of a substrate at another stage of a method for forming an array of memory cells in accordance with the technology.
[0017] Figure 13 is a cross-sectional view of an embodiment of a substrate at another stage of a method for forming an array of memory cells in accordance with the technology.
[0018] Figure 14 is a cross-sectional view of an embodiment of a substrate at another stage of a method for forming an array of memory cells in accordance with the technology.
[0019] Figure 15 is a cross-sectional view of an embodiment of a substrate at another stage of a method for forming an array of memory cells in accordance with the technology.
[0020] Figure 16 is a cross-sectional view of an embodiment of a substrate at another stage of a method for forming an array of memory cells in accordance with the technology.
[0021] Figure 17 is a cross-sectional view of an embodiment of a substrate at another stage of a method for forming an array of memory cells in accordance with the technology.
[0022] Figure 18 is a cross-sectional view of an embodiment of a substrate at another stage of a method for forming an array of memory cells in accordance with the technology.
[0023] Figure 19 is a cross-sectional view of an embodiment of a substrate at another stage of a method for forming an array of memory cells in accordance with the technology.
[0024] Figure 20 is a cross-sectional view of an embodiment of a substrate at another stage of a method for forming an array of memory cells in accordance with the technology.
[0025] Figure 21 is a cross-sectional view of an embodiment of a substrate at another stage of a method for forming an array of memory cells in accordance with the technology.
[0026] Figure 22 is a cross-sectional view of an embodiment of a substrate at another stage of a method for forming an array of memory cells in accordance with the technology.
[0027] Figure 23 is a flow chart of another embodiment of a method for forming vertical memory cells in accordance with the technology.
[0028] Specific details of several embodiments of the new technology are described below with reference to memory cell arrays and methods for manufacturing arrays of memory cells. Many embodiments, for example, are directed to cross-point memory arrays used in phase change memory or other types of memory. Memory cells and other semiconductor components are manufactured on and/or in semiconductor wafers that can include semiconductor substrates upon which and/or in which microelectronic devices, micromechanical devices, data storage elements, optics, read/write components, and other features can be fabricated. For example, SRAM, DRAM (e.g., DDR/SDRAM), flash memory (e.g., NAND flash-memory), phase change memory (PCRAM), processors, imagers, light emitting diodes (LEDs) and other types of devices can be constructed on semiconductor wafers. Although many of the embodiments are described below with respect to semiconductor devices that have integrated circuits, other types of devices manufactured on other types of substrates may be within the scope of the new technology. Moreover, several other embodiments of the new technology can have different configurations, components, or procedures than those described in this section. A person of ordinary skill in the art, therefore, will accordingly understand that the new technology may have other embodiments with additional elements, or the new technology may have other embodiments without several of the features shown and described below with reference to Figures 1-24.
[0029] Figure 1 is a flow chart of an embodiment of a method 100 of forming an array of memory cells in accordance with the technology. The method can include forming a plurality of pillars in an array of rows and columns (block 110). The pillars are formed from a substrate of a bulk semiconductor material, and individual pillars have a sacrificial cap structure. For example, individual pillars can have a semiconductor post formed of the bulk semiconductor material and the sacrificial cap structure can be on each of the semiconductor posts. The method further includes forming source regions between columns of the pillars (block 120), and forming conductive gate lines (block 130). Individual gate lines extend along a column of pillars and are spaced apart from corresponding source regions. Each gate line completely surrounds a portion of the semiconductor posts along a corresponding column of pillars. This embodiment of the method 100 further includes selectively removing the sacrificial cap structure and thereby forming self-aligned openings that expose a top portion of corresponding semiconductor posts (block 140), and forming individual drain contacts in the self-aligned openings that are electrically connected to corresponding semiconductor posts (block 150).
[0030] Figures 2A and 2B are cross-sectional and top plan views, respectively, of an embodiment of a substrate 200 (e.g., a wafer) at a stage of the method 100. At this stage, the substrate 200 has a bulk semiconductor material 210 (Figure 2A), a plurality of shallow trench isolation (STI) structures 220, and a sacrificial structure 230 (Figure 2A). The STI structures 220 can have array trenches 222, peripheral trenches 224, a dielectric liner 226 lining the array and peripheral trenches 222 and 224, and an oxide 228 filling the array and peripheral trenches. The array trenches 222 define the spacing between rows of pillars that form individual memory cells or memory units.
[0031] The sacrificial structure 230 can include a first sacrificial material 232 and an optional second sacrificial material 234. The first sacrificial material 232 can be selectively removable relative to the second sacrificial material 234 using a suitable solvent or other material, and the first and second sacrificial material 232 and 234 can also provide separate stop-on features for mechanical removal processes. For example, the first sacrificial material 232 can be a polymeric material and the second sacrificial material 234 can be a nitride. The sacrificial structure 230 can be separated from the bulk semiconductor material 210 by a dielectric layer 236. In one specific embodiment, the dielectric layer 236 can be a silicon oxide layer having a thickness of approximately 50 angstroms, the first sacrificial material 232 can be a polymeric material having a thickness of about 800 angstroms, and the second sacrificial material 234 can be a nitride having a thickness of approximately 400 angstroms.
[0032] Figures 3A and 3B are cross-sectional and top plan views, respectively, of an embodiment of the substrate 200 at a subsequent stage of the method 100 in which column trenches 240 are formed. The column trenches 240 can be perpendicular or at an oblique angle relative to the oxide 228 in the array trenches 222. The column trenches 240 can be formed by photo-patterning a resist or other material (not shown) on top of the sacrificial structure 230 using photolithography or other techniques known in the art. The array trenches 222 can have a first width Wi (Figure 3B), and the column trenches 240 have a second width W2greater than the first width Wi of the array trenches 222. The column trenches 240 are formed by etching through the sacrificial structure 230 and into the semiconductor material 210 to a desired trench depth. The etching process can be a dry etch or other method known in the art. In one embodiment, the target trench depth of the column trenches 240 is approximately equal to the depth of the array trenches 222 and peripheral trenches 224 of the STI structure 220.
[0033] The substrate 200 has an array of pillars 250 that provide vertical channels for forming individual memory cells. The oxide 228 in the array trenches 222 supports the pillars 250. Referring to Figure 3 A, individual pillars 250 can include a semiconductor post 252 of the bulk semiconductor material 210 and a sacrificial cap 254 formed from the remaining portions of the first and second sacrificial material 232 and 234. The individual semiconductor posts 252 can each include a proximal portion 256a, an intermediate section 256b, and a distal portion 256c relative to the base of the bulk semiconductor material 210 at the bottom of the column trenches 240.
[0034] The array of pillars 250 can be arranged in a plurality of rows (Ri, R2, etc.) and a plurality of columns (Ci, C2, C3, C4, etc.). The rows of pillars 250 are spaced apart from each other by the first width Wi of the array trenches 222, and the columns of pillars 250 are spaced apart from each other by the second width W2of the column trenches 240. As described in more detail below, the first width Wi and second width W2are selected based upon the thickness of a conductive gate material such that the resulting conductive gate lines completely surround a portion of each of the pillars 250. The first width Wi, for example, can be less than 200% of the thickness of the conductive gate material, and the second width W2of the column trenches 240 can be greater than 200% of the thickness of the conductive gate material. In more specific embodiments, the second width W2can be about 300% greater than the thickness of the conductive gate material.
[0035] Figures 4A-6B illustrate embodiments of the substrate 200 at subsequent stages of the method 100. Figures 4A and 4B are cross-sectional and top plan views, respectively, after forming a first dielectric liner 257 and a second dielectric liner 258 along the sidewalls of the pillars 250. The first dielectric liner 257 can be formed by growing an oxide via oxidation, and the second dielectric liner 258 can be formed by growing or otherwise depositing a thin blocking spacer material. For example, the first dielectric liner 257 can be an oxide having a thickness of approximately 20 angstroms, and the second dielectric liner 258 can be a deposited TEOS having a thickness of approximately 50-100 angstroms. The first and second dielectric liners 257 and 258 are then spacer etched to remove the portions of the liners on the top of the pillars 250 and in the bottom of the column trenches 240. The method can further include an activation procedure to re-crystallize the semiconductor material.
[0036] After spacer etching the first and second liners 257 and 258, source regions 260 are formed by implanting the desired implant species into the bulk semiconductor material 210 at the bottom of the column trenches 240. The source regions 260, for example, can be an N-type species. Figures 5A and 5B are cross-sectional and top plan views, respectively, of the substrate 200 at a subsequent stage in which a silicide 262 is formed at the source regions 260 by exposing the implanted material to a source, such as Ni, Co, or Ti, that selectively forms a metal silicide. During the silicide process, the sidewalls of the pillars 250 are protected by the second dielectric liner 258 and the second sacrificial material 234 of the cap structure 254. The un-reacted metal can be removed from the silicide 262 with a wet etch or other technique, and a thin nitride liner can be formed to cap the silicide 262
[0037] Figures 6A and 6B are cross-sectional and top plan views, respectively, of an embodiment of the substrate 200 at a later stage in which the column trenches 240 are filled with an oxide 248 and then planarized using a chemical-mechanical planarization process or other process that stops on the second sacrificial material 234 of the sacrificial cap 254. The oxide 248 that fills the column trenches 240 can be the same as the oxide 228 that fills the array trenches 222 of the STI structure 220. The thin nitride cap deposited on the silicide 262 protects the silicid 262 from subsequent gate oxidation.
[0038] Figures 7A-8B illustrate embodiments of additional stages of the method 100. Figures 7A and 7B are cross-sectional and top plan views, respectively, of the substrate 200 after removing the second sacrificial material 234 and a portion of the oxides 228 and 248. The second sacrificial material 234 can be selectively removed relative to the oxides 228 and 248 in a separate process, or the second sacrificial material 234 and the oxides 228 and 248 can be removed in the same process. The oxides 228 and 248 are accordingly recessed relative to the distal portion 256c of the semiconductor posts 252. In one embodiment, the thickness of the remaining portions of the oxides 228 and 248 is about 700 angstroms.
[0039] Figures 8A and 8B are cross-sectional and top plan views, respectively, illustrating the substrate 200 at a further stage in which more material is removed from the oxides 228 and 248 and the sidewalls of the pillars 250 are cleaned. The remaining portions of the oxides 228 and 248 provide a dielectric spacer between the source regions 260 and the intermediate sections 256b of the semiconductor posts 252 where the metal gates will be formed. In one embodiment, the thickness of the remaining portions of the oxide 228 and 248 is about 200 angstroms. The exposed sidewalls of the semiconductor posts 252 provide a clean semiconductor surface for forming a gate dielectric 265. The gate dielectric 265 can be formed of conventional Si02, nitride hardened Si02, or other suitable materials. The portions of the gate dielectric 265 at the intermediate sections 256b of the posts 252 define the gate dielectric for the memory cells.
[0040] Figures 9A-9C illustrate embodiments of the substrate 200 at a metallization stage of the method 100. Figures 9A and 9B are cross-sectional views taken along lines 9A- 9 A and 9B-9B of Figure 9C. The method further includes depositing a conductive gate material 270 over the pillars 250 and into the recessed portions of the array trenches 222 (Figure 9B) and the column trenches 240 (Figure 9A). The gate material 270 has a thickness T (Figure 9A) such that the smaller first width Wi of the array trenches 222 causes the gate material 270 to pinch off at intersections 271 (Figure 9C) over the portions of the oxide 228 between rows of pillars 250. The thickness T of the gate material 270, however, is not so thick that it spans the larger second width W2 of the column trenches 240. The gate material 270 can be tantalum nitride or other suitable materials.
[0041] Figure 10 is a cross-sectional view illustrating embodiments of the substrate 200 at a stage of the method 100 in which gate lines 272 are formed from the gate material 270. The gate lines 272 are formed by spacer etching the gate material 270 (Figures 9A-9C) until the remaining portions of the gate material 270 are about at or near the intermediate sections 256b (Figure 5A) of the semiconductor posts 252. The spacer etch can selectively stop on the oxide 248 at the bottom of the column channels 240. However, because the gate material 270 completely filled the array tranches 222 between pillars 250, a portion of the gate material 270 remains in the bottom of the array trenches 222 between the pillars 250. Each metal gate line 272 accordingly completely surrounds the corresponding intermediate sections 256b of the posts 252 along a column of pillars 250. After forming the gate lines 272, an optional step includes implanting an n-type implant or other species into the distal portions 256c of the semiconductor posts using an angle implant (e.g., an n-type lightly doped drain).
[0042] Figure 11 is a cross-sectional view of embodiments of the substrate 200 at another stage of the method 100. At this stage dielectric spacers 274 are formed above the gate lines 272, along the sidewalls of the pillars 250. The dielectric spacers 274 can be formed by depositing a dielectric material over the substrate and spacer etching the dielectric material to remove it from horizontal or other non- vertical surfaces. The dielectric spacers 274, for example, can be a nitride that is selectively etchable relative to the gate dielectric 265 and the oxide 248 in the bottom of the column channels 240.
[0043] Figure 12 is a cross-sectional view of embodiments of the substrate 200 at a subsequent stage that includes depositing an oxide 278 into the open portions of the array trenches 222 and the column trenches 240. The oxide 278 can be planarized to remove (a) an over burden of the oxide 278 and (b) the portions of the gate dielectric 265 on top of the remaining portions of the first sacrificial material 232. The planarization procedure accordingly exposes the remaining portions of the first sacrificial dielectric layer 232 without any additional photolithography procedures. As such, the exposed portions of the first sacrificial material 232 over the individual semiconductor posts 252 are "self-aligned" in that a separate photolithography process is not necessary to form a pattern corresponding to the exposed portions of the first sacrificial material 232.
[0044] Figure 13 is a cross-sectional view illustrating embodiments of subsequent stages in which the exposed portions of the first sacrificial material 232 are selectively etched relative to the oxide 278 to form self-aligned openings 280 directly over the distal portions 256c of corresponding semiconductor posts 252. The first sacrificial material 232 is formed from a material that is selectively removable relative to the oxide 278 and the dielectric spacer 274 such that the self-aligned openings 280 can be formed directly over the distal portions 256c of the semiconductor post 252 without having to align openings of a mask with the posts 252 (e.g., a mask photo-patterned on the wafer to have openings aligned with the posts). An n-type or other species can be implanted into the distal portions 256c of the semiconductor posts 252 to form drain regions 282. The drain regions 282 can accordingly be formed by directly implanting the implant species through the openings 280 at this stage of the process either in lieu of or in addition to forming the drain regions 282 earlier in the method using an angled implant process as described above with respect to in Figure 10.
[0045] Figure 14 is a cross-sectional view illustrating embodiments of an additional stage of the method 100 in which a plurality of drain contact plugs 284 are formed in the openings 280 (Figure 13). The drain contact plugs 284 can be formed by depositing a metal or other suitably conductive material into the openings 280 (Figure 13), and then removing an overburden portion of the metal from the top of the oxide 278 using a chemical- mechanical planarization or other process. The drain contact plugs 284, for example, can be tungsten or other suitable metals. The drain contact plugs 284 are accordingly mask-less, self-aligned features that are aligned with the semiconductor posts 252. At this point, the structure of each pillar 250 defines a memory cell, and the array of memory cells is ready for cell integration into a PCRAM or other type of memory device.
[0046] Several embodiments of the method 100 and the resulting substrate 200 can be used to form very small cross-point memory cells. Some of the smallest features of a cross- point cell array are the gate lines and the contact plugs, and current photolithographic processes may not be able to efficiently form these features at the smallest sizes. The specific embodiment of the method 100 shown and described above, however, enables the gate lines and contact plugs to be formed without having to form a pattern of either the gate lines or the contact plugs using photolithography. This not only eliminates the process errors that can be induced by photolithographically patterning very small features, but is also reduces the utilization of expensive photolithography equipment. Therefore, several embodiments of the method 100 and substrate 200 provide a cost effective process for fabricating cross-point memory cells.
[0047] Several embodiments of the method 100 and the substrate 200 also provide a structure that can address other concerns of cross-point memory cells. For example, because the gate lines 272 surround the intermediate sections 256b of the semiconductor posts 252 along a column of pillars 250, the issues of reversed leakage current, serial resistance along a column of pillars 250, and current-voltage control are expected to be mitigated.
[0048] Figures 15-22 illustrate stages of another embodiment of the method 100. Figure 15 is a cross-sectional view that illustrates a stage immediately after the stages described above with respect to Figures 2A-9C. Figure 15, more specifically, illustrates a stage of another embodiment of the process 100 in which the gate material 270 has been spacer etched to selectively stop on the gate dielectric 265 and the oxide 248. The process illustrated in Figure 15 differs from that illustrated in Figure 10 in that the gate material 270 shown in Figure 15 is not etched to the same extent as it is in Figure 10. The stage illustrated in Figure 15 accordingly forms an intermediate structure 302 for forming gate lines that surround the individual pillars 250. In several embodiments, the gate lines 272 completely surround the individual pillars 250.
[0049] Figure 16 is a cross-sectional view illustrating embodiments at a later stage in which an oxide 308 is deposited into the open portions of the column trenches 240. At this stage an overburdened portion of the oxide 308 is removed using a chemical-mechanical planarizing procedure or other process that stops on the first sacrificial material 232. The removal procedure accordingly removes portions of the gate dielectric 265 from the top surface of the remaining portions of the first sacrificial material 232 in alignment with the individual pillars 250.
[0050] Figure 17 is a cross-sectional view illustrating subsequent stages in which the remaining portions of the first sacrificial material 232 are removed from the regions over the pillars 250 to form self-aligned openings 310 aligned with corresponding pillars 250. The first sacrificial material 232 can be selectively removed such that the remaining portions of the gate dielectric 265 remain intact. Figure 18 is a cross-sectional view that shows a subsequent stage in which the remaining portions of the gate dielectric 265 are removed to expose the distal portions 256c of the semiconductor posts 252. At this point a desired implant species can be implanted into the distal portions 256 of the semiconductor posts 252 to form drain regions 282.
[0051] Figure 19 is a cross-sectional view illustrating a subsequent stage that includes removing a portion of the intermediate structure 302 to form the individual gate lines 272 at the intermediate sections 256b of corresponding semiconductor posts 252. The gate lines 272 are formed such that they are spaced apart from both the drain regions 282 and the source regions 260. The gate lines 272 also surround the intermediate sections 256b of the semiconductor posts 252 along a corresponding column of the pillars 250 as described above with respect to Figure 10.
[0052] Figures 20-22 are cross-sectional views illustrating additional stages of this embodiment of the method. Figure 20 illustrates a stage in which a dielectric spacer 311 is deposited or otherwise formed in the substrate 200. The dielectric spacer 311 can be a nitride, and the thickness of the dielectric spacer 311 can be selected to fill the gaps where the gate metal was recessed to form the gate lines 272. Figure 21 illustrates spacer etching the dielectric spacer 311 to expose the drain regions 282. More specifically, the dielectric spacer 311 can be spacer etched to form dielectric spacers 314 above the gate lines 272 and along the sidewalls of the oxide 308. The drain regions 282 are accordingly exposed. Figure 22 illustrates the substrate 200 at a subsequent stage in which contact plugs 284 are formed in the openings over the drain regions 282.
[0053] Figure 23 is a flow chart of a method 400 for forming an array of vertical memory cells in accordance with another embodiment of the technology. In one embodiment, the method 400 includes forming a plurality of pillars (block 410) in which each pillar has a semiconductor post and a sacrificial cap. The pillars are arranged in rows spaced apart by a row spacing and columns spaced apart by a column spacing larger than the row spacing. The method 400 can further include forming source regions at a proximal region of the semiconductor posts (block 420) and forming conductive gate lines that completely surround an intermediate section of the semiconductor posts in a corresponding column of pillars (block 430). After forming the gate lines, the sacrificial caps can be removed selectively without forming a photo-pattern corresponding to a pattern of the sacrificial caps and thereby forming self-aligned openings over a distal portion of each of the semiconductor posts (block 440). The method 400 can also include forming drain contacts in the self-aligned openings that are electrically connected to corresponding semiconductor posts (block 450).
[0054] From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the invention. Where the context permits, singular or plural terms may also include the plural or singular term, respectively. Moreover, unless the word "or" is expressly limited to mean only a single item exclusive from the other items in reference to a list of two or more items, then the use of "or" in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Additionally, the term "comprising" is used throughout to mean including at least the recited feature(s) such that any greater number of the same feature and/or additional types of features are not precluded Accordingly, the invention is not limited except as by the appended claims.

中文:
[0002]微电子工业处于以持续降低的成本生产小封装大小的高性能装置的巨大压力之下。智能电话、便携式计算机、数码相机、便携式音乐及媒体播放器以及许多其它电子产品需要具有较多容量的较快速存储器装置。如此,存储器装置制造商尤其寻求用于制作高性能装置的可靠低成本工艺。
[0003]存储器装置可具有大的存储器单元阵列,且减小个别存储器单元的大小提供所述存储器装置的位密度的伴随增加。交叉点存储器单元位于字线与位线之间的垂直重叠区域中。交叉点存储器单元包含在暴露于字线与对应位线之间的电流时经历稳定且可检测的改变的结构。由于交叉点存储器单元位于位线与字线之间的重叠区域中,因此这些存储器单元在理论上可形成为极小尺寸。
[0004]制造交叉点存储器单元的一个担忧问题是可难以使用光刻工艺来形成所述结构的最小特征。举例来说,难以图案化晶片以形成交叉点存储器单元的漏极结构,因为这些特征如此小以致无法使用现有光刻工艺可靠地形成所述特征。还难以光图案化完全环绕高密度交叉点存储器阵列中的个别柱的栅极结构。此外,使用光刻工艺来形成非常小的特征非常昂贵,因为这些工艺需要昂贵设备及材料。交叉点存储器阵列的额外担忧问题包含反向泄漏电流、串联电阻及对电流-电压均匀性的准确控制,此对于多电平单元配置来说是重要的。因此,期望开发用于形成高度集成的电路且特定来说形成交叉点存储器单元的经改进方法,及开发此些特征的经改进电路。
[0005]图1是根据本技术用于形成存储器单元阵列的方法的实施例的流程图。
[0006]图2A是根据本技术用于形成存储器单元阵列的方法的阶段处的衬底的实施例的横截面图且图2B是其俯视平面图。
[0007]图3A是根据本技术用于形成存储器单元阵列的方法的另一阶段处的衬底的实施例的横截面图且图3B是其俯视平面图。
[0008]图4A是根据本技术用于形成存储器单元阵列的方法的另一阶段处的衬底的实施例的横截面图且图4B是其俯视平面图。
[0009]图5A是根据本技术用于形成存储器单元阵列的方法的另一阶段处的衬底的实施例的横截面图且图5B是其俯视平面图。
[0010]图6A是根据本技术用于形成存储器单元阵列的方法的另一阶段处的衬底的实施例的横截面图且图6B是其俯视平面图。
[0011]图7A是根据本技术用于形成存储器单元阵列的方法的另一阶段处的衬底的实施例的横截面图且图7B是其俯视平面图。
[0012]图8A是根据本技术用于形成存储器单元阵列的方法的另一阶段处的衬底的实施例的横截面图且图8B是其俯视平面图。
[0013]图9A及9B是根据本技术用于形成存储器单元阵列的方法的另一阶段处的衬底的实施例的横截面图且图9C是其俯视平面图。
[0014]图10是根据本技术用于形成存储器单元阵列的方法的另一阶段处的衬底的实施例的横截面图。
[0015]图11是根据本技术用于形成存储器单元阵列的方法的另一阶段处的衬底的实施例的横截面图。
[0016]图12是根据本技术用于形成存储器单元阵列的方法的另一阶段处的衬底的实施例的横截面图。
[0017]图13是根据本技术用于形成存储器单元阵列的方法的另一阶段处的衬底的实施例的横截面图。
[0018]图14是根据本技术用于形成存储器单元阵列的方法的另一阶段处的衬底的实施例的横截面图。
[0019]图15是根据本技术用于形成存储器单元阵列的方法的另一阶段处的衬底的实施例的横截面图。
[0020]图16是根据本技术用于形成存储器单元阵列的方法的另一阶段处的衬底的实施例的横截面图。
[0021]图17是根据本技术用于形成存储器单元阵列的方法的另一阶段处的衬底的实施例的横截面图。
[0022]图18是根据本技术用于形成存储器单元阵列的方法的另一阶段处的衬底的实施例的横截面图。
[0023]图19是根据本技术用于形成存储器单元阵列的方法的另一阶段处的衬底的实施例的横截面图。
[0024]图20是根据本技术用于形成存储器单元阵列的方法的另一阶段处的衬底的实施例的横截面图。
[0025]图21是根据本技术用于形成存储器单元阵列的方法的另一阶段处的衬底的实施例的横截面图。
[0026]图22是根据本技术用于形成存储器单元阵列的方法的另一阶段处的衬底的实施例的横截面图。
[0027]图23是根据本技术用于形成垂直存储器单元的方法的另一实施例的流程图。
[0028]下文参考存储器单元阵列及用于制造存储器单元阵列的方法描述新技术的数个实施例的特定细节。举例来说,许多实施例针对在相变存储器或其它类型的存储器中使用的交叉点存储器阵列。可在半导体晶片上及/或中制造存储器单元及其它半导体组件,所述半导体晶片可包含其上及/或其中可制作微电子装置、微机械装置、数据存储元件、光学器件、读取/写入组件及其它特征的半导体衬底。举例来说,可在半导体晶片上构造SRAM、DRAM(例如,DDR/SDRAM)、快闪存储器(例如,NAND快闪存储器)、相变存储器(PCRAM)、处理器、成像器、发光二极管(LED)及其它类型的装置。虽然下文关于具有集成电路的半导体装置描述实施例中的许多实施例,但制造于其它类型的衬底上的其它类型的装置可在新技术的范围内。此外,新技术的数个其它实施例可具有不同于此部分中所描述的那些配置、组件或程序的配置、组件或程序。因此,所属领域的技术人员将相应地理解,新技术可具有带有额外元件的其它实施例,或者新技术可具有不具有下文参考图1到24所展示及所描述的特征中的数者的其它实施例。
[0029]图1是根据本技术用于形成存储器单元阵列的方法100的实施例的流程图。所述方法可包含将多个柱形成为若干行及若干列的阵列(框110)。所述柱由块体半导体材料的衬底形成,且个别柱具有牺牲帽结构。举例来说,个别柱可具有由所述块体半导体材料形成的半导体立柱且所述牺牲帽结构可在所述半导体立柱中的每一者上。所述方法进一步包含在所述柱的列之间形成源极区域(框120)并形成导电栅极线(框130)。个别栅极线沿柱列延伸且与对应源极区域间隔开。每一栅极线沿对应柱列完全环绕半导体立柱的一部分。方法100的此实施例进一步包含选择性地移除所述牺牲帽结构且借此形成暴露对应半导体立柱的顶部部分的自对准开口(框140),并在所述自对准开口中形成电连接到对应半导体立柱的个别漏极触点(框150)。
[0030]图2A及2B分别是方法100的一阶段处的衬底200(例如,晶片)的实施例的横截面图及俯视平面图。在此阶段处,衬底200具有块体半导体材料210(图2A)、多个浅沟槽隔离(STI)结构220及牺牲结构230(图2A)。STI结构220可具有阵列沟槽222、外围沟槽224、给阵列及外围沟槽222及224加衬的电介质衬里226以及填充所述阵列及外围沟槽的氧化物228。阵列沟槽222界定形成个别存储单元或存储器单元的柱行之间的间距。
[0031]牺牲结构230可包含第一牺牲材料232及任选第二牺牲材料234。第一牺牲材料232可使用适合溶剂或其它材料相对于第二牺牲材料234选择性移除,且第一牺牲材料232及第二牺牲材料234还可提供用于机械移除工艺的单独终止特征。举例来说,第一牺牲材料232可为聚合材料且第二牺牲材料234可为氮化物。牺牲结构230可通过电介质层236与块体半导体材料210分离。在一个特定实施例中,电介质层236可为具有约50埃的厚度的氧化硅层,第一牺牲材料232可为具有大约800埃的厚度的聚合材料,且第二牺牲材料234可为具有约400埃的厚度的氮化物。
[0032]图3A及3B分别是方法100的后续阶段处的衬底200的实施例的横截面图及俯视平面图,其中形成有列沟槽240。列沟槽240可相对于阵列沟槽222中的氧化物228垂直或成斜角。可通过使用光刻或此项技术中已知的其它技术在牺牲结构230的顶部上光图案化抗蚀剂或其它材料(未展示)来形成列沟槽240。阵列沟槽222可具有第一宽度W1(图3B),且列沟槽240具有大于阵列沟槽222的第一宽度W1的第二宽度W2。通过蚀刻穿过牺牲结构230且向半导体材料210中蚀刻到所期望沟槽深度来形成列沟槽240。蚀刻工艺可为干蚀刻或此项技术中已知的其它方法。在一个实施例中,列沟槽240的目标沟槽深度约等于STI结构220的阵列沟槽222及外围沟槽224的深度。
[0033]衬底200具有柱250阵列,所述柱提供用于形成个别存储器单元的垂直沟道。阵列沟槽222中的氧化物228支撑柱250。参考图3A,个别柱250可包含块体半导体材料210的半导体立柱252以及由第一牺牲材料232及第二牺牲材料234的剩余部分形成的牺牲帽254。个别半导体立柱252可各自包含相对于列沟槽240的底部处的块体半导体材料210的基底的近端部分256a、中间区段256b及远端部分256c。
[0034]柱250阵列可布置成多个行(R1、R2等)及多个列(C1、C2、C3、C4等)。柱250行彼此间隔开阵列沟槽222的第一宽度W1,且柱250列彼此间隔开列沟槽240的第二宽度W2。如下文更详细地描述,基于导电栅极材料的厚度选择第一宽度W1及第二宽度W2,使得所得导电栅极线完全环绕柱250中的每一者的一部分。举例来说,第一宽度W1可小于所述导电栅极材料的厚度的200%,且列沟槽240的第二宽度W2可大于所述导电栅极材料的厚度的200%。在更特定实施例中,第二宽度W2可比所述导电栅极材料的厚度大约300%。
[0035]图4A到6B图解说明方法100的后续阶段处的衬底200的实施例。图4A及4B分别是在沿柱250的侧壁形成第一电介质衬里257及第二电介质衬里258之后的横截面图及俯视平面图。可通过经由氧化生长氧化物来形成第一电介质衬里257,且通过生长或以其它方式沉积薄阻挡间隔件材料来形成第二电介质衬里258。举例来说,第一电介质衬里257可为具有约20埃的厚度的氧化物,且第二电介质衬里258可为具有约50到100埃的厚度的所沉积TEOS。接着,对第一电介质衬里257及第二电介质衬里258进行间隔件蚀刻以移除衬里的在柱250的顶部上及列沟槽240的底部中的部分。所述方法可进一步包含活化程序以使半导体材料再结晶。
[0036]在对第一衬里257及第二衬里258进行间隔件蚀刻之后,通过在列沟槽240的底部处将所期望的植入物质植入到块体半导体材料210中来形成源极区域260。举例来说,源极区域260可为N型物质。图5A及5B分别是后续阶段处的衬底200的横截面图及俯视平面图,其中通过将所植入材料暴露于选择性地形成金属硅化物的源(例如Ni、Co或Ti)而在源极区域260处形成硅化物262。在硅化物工艺期间,通过第二电介质衬里258及帽结构254的第二牺牲材料234来保护柱250的侧壁。可借助湿蚀刻或其它技术从硅化物262移除未反应的金属,且可形成薄氮化物衬里来帽盖硅化物262。
[0037]图6A及6B分别是稍后阶段处的衬底200的实施例的横截面图及俯视平面图,其中用氧化物248填充列沟槽240且接着使用化学机械平面化工艺或在牺牲帽254的第二牺牲材料234上终止的其它工艺对其进行平面化。填充列沟槽240的氧化物248可与填充STI结构220的阵列沟槽222的氧化物228相同。沉积于硅化物262上的薄氮化物帽保护硅化物262免受后续栅极氧化的影响。
[0038]图7A到8B图解说明方法100的额外阶段的实施例。图7A及7B分别是在移除第二牺牲材料234以及氧化物228及248的一部分之后的衬底200的横截面图及俯视平面图。可相对于氧化物228及248在单独工艺中选择性地移除第二牺牲材料234,或者可在同一工艺中移除第二牺牲材料234以及氧化物228及248。因此,氧化物228及248相对于半导体立柱252的远端部分256c凹入。在一个实施例中,氧化物228及248的剩余部分的厚度为约700埃。
[0039]图8A及8B分别是图解说明在另一阶段处的衬底200的横截面图及俯视平面图,其中从氧化物228及248移除更多材料且清洗柱250的侧壁。氧化物228及248的剩余部分在源极区域260与半导体立柱252的中间区段256b之间提供电介质间隔件,其中将形成金属栅极。在一个实施例中,氧化物228及248的剩余部分的厚度为约200埃。半导体立柱252的经暴露侧壁提供用于形成栅极电介质265的洁净半导体表面。栅极电介质265可由常规SiO2、氮化物硬化的SiO2或其它适合材料形成。在立柱252的中间区段256b处的栅极电介质265的部分界定存储器单元的栅极电介质。
[0040]图9A到9C图解说明方法100的金属化阶段处的衬底200的实施例。图9A及9B是沿图9C的线9A-9A及9B-9B截取的横截面图。所述方法进一步包含在柱250上方及向阵列沟槽222(图9B)及列沟槽240(图9A)的凹入部分中沉积导电栅极材料270。栅极材料270具有厚度T (图9A),使得阵列沟槽222的较小第一宽度W1致使栅极材料270夹止于氧化物228的在柱250行之间的部分上方的相交点271(图9C)处。然而,栅极材料270的厚度T并非如此厚以致其横跨列沟槽240的较大第二宽度W2。栅极材料270可为氮化钽或其它适合材料。
[0041]图10是图解说明方法100的阶段处的衬底200的实施例的横截面图,其中由栅极材料270形成栅极线272。通过对栅极材料270(图9A到9C)进行间隔件蚀刻直到栅极材料270的剩余部分约在半导体立柱252的中间区段256b (图5A)处或附近为止来形成栅极线272。所述间隔件蚀刻可选择性地终止于列沟道240的底部处的氧化物248上。然而,由于栅极材料270曾完全填充柱250之间的阵列沟槽222,因此栅极材料270的一部分保留于柱250之间的阵列沟槽222的底部中。因此,每一金属栅极线272沿柱250列完全环绕立柱252的对应中间区段256b。在形成栅极线272之后,任选步骤包含使用角度植入将n型植入物或其它物质植入到半导体立柱的远端部分256c中(例如,n型轻掺杂漏极)。
[0042]图11是方法100的另一阶段处的衬底200的实施例的横截面图。在此阶段处,沿柱250的侧壁在栅极线272上面形成电介质间隔件274。可通过在衬底上方沉积电介质材料并对所述电介质材料进行间隔件蚀刻以将其从水平或其它非垂直表面移除来形成电介质间隔件274。举例来说,电介质间隔件274可为可相对于栅极电介质265及列沟道240的底部中的氧化物248选择性蚀刻的氮化物。
[0043]图12是后续阶段处的衬底200的实施例的横截面图,所述后续阶段包含将氧化物278沉积到阵列沟槽222及列沟槽240的敞开部分中。可对氧化物278进行平面化以移除(a)氧化物278的超载部分及(b)栅极电介质265的在第一牺牲材料232的剩余部分的顶部上的部分。因此,平面化程序不借助任何额外光刻程序便暴露第一牺牲电介质层232的剩余部分。如此,个别半导体立柱252上方的第一牺牲材料232的经暴露部分为“自对准的”,因为不需要单独光刻工艺来形成对应于第一牺牲材料232的经暴露部分的图案。
[0044]图13是图解说明后续阶段的实施例的横截面图,其中相对于氧化物278选择性地蚀刻第一牺牲材料232的经暴露部分以在对应半导体立柱252的远端部分256c正上方形成自对准开口280。第一牺牲材料232由可相对于氧化物278及电介质间隔件274选择性移除的材料形成,使得自对准开口280可形成于半导体立柱252的远端部分256c正上方而不必使掩模的开口与立柱252对准(例如,在晶片上经光图案化以具有与立柱对准的开口的掩模)。可将n型或其它物质植入到半导体立柱252的远端部分256c中以形成漏极区域282。因此,代替较早在所述方法中使用上文关于图10中所描述的有角植入工艺形成漏极区域282或除此以外,还可在工艺的此阶段处经由开口280直接植入植入物质来形成漏极区域282。
[0045]图14是图解说明方法100的额外阶段的实施例的横截面图,其中在开口280(图13)中形成多个漏极接触柱塞284。可通过将金属或其它适合导电材料沉积到开口280(图13)中且接着使用化学机械平面化或其它工艺从氧化物278的顶部移除所述金属的超载部分来形成漏极接触柱塞284。举例来说,漏极接触柱塞284可为钨或其它适合金属。因此,漏极接触柱塞284为与半导体立柱252对准的无掩模自对准特征。此时,每一柱250的结构界定一存储器单元,且存储器单元阵列准备好单元集成到PCRAM或其它类型的存储器装置中。
[0046]可使用方法100及所得衬底200的数个实施例形成非常小的交叉点存储器单元。交叉点单元阵列的最小特征中的一些特征为栅极线及接触柱塞,且当前光刻工艺可能不能够以最小大小高效地形成这些特征。然而,上文展示并描述的方法100的特定实施例使得能够在不必使用光刻形成栅极线或接触柱塞的图案的情况下形成栅极线及接触柱塞。此不仅消除可能由以光刻方式图案化非常小的特征诱发的工艺误差,而且减少昂贵光刻设备的利用。因此,方法100及衬底200的数个实施例提供一种用于制作交叉点存储器单元的具成本效益的工艺。
[0047]方法100及衬底200的数个实施例还提供一种可解决交叉点存储器单元的其它担忧问题的结构。举例来说,由于栅极线272沿柱250列环绕半导体立柱252的中间区段256b,因此预期会减轻反向泄漏电流、沿柱250列的串联电阻及电流-电压控制的问题。
[0048]图15到22图解说明方法100的另一实施例的各阶段。图15是图解说明紧接在上文关于图2A到9C所描述的阶段之后的阶段的横截面图。更具体来说,图15图解说明工艺100的另一实施例的阶段,其中已对栅极材料270进行间隔件蚀刻以选择性地终止于栅极电介质265及氧化物248上。图15中所图解说明的工艺与图10中所图解说明的工艺的不同在于图15中所展示的栅极材料270未被蚀刻到与其在图10中相同的程度。因此,图15中所图解说明的阶段形成用于形成环绕个别柱250的栅极线的中间结构302。在数个实施例中,栅极线272完全环绕个别柱250。
[0049]图16是图解说明稍后阶段处的实施例的横截面图,其中将氧化物308沉积到列沟槽240的敞开部分中。在此阶段处,使用化学机械平面化程序或终止于第一牺牲材料232上的其它工艺移除氧化物308的超载部分。因此,所述移除程序与个别柱250对准地从第一牺牲材料232的剩余部分的顶部表面移除栅极电介质265的部分。
[0050]图17是图解说明后续阶段的横截面图,其中从柱250上方的区域移除第一牺牲材料232的剩余部分以形成与对应柱250对准的自对准开口310。可选择性地移除第一牺牲材料232,使得栅极电介质265的剩余部分保持完好无损。图18是展示后续阶段的横截面图,其中移除栅极电介质265的剩余部分以暴露半导体立柱252的远端部分256c。此时,可将所期望的植入物质植入到半导体立柱252的远端部分256中以形成漏极区域282。
[0051]图19是图解说明后续阶段的横截面图,所述后续阶段包含移除中间结构302的一部分以在对应半导体立柱252的中间区段256b处形成个别栅极线272。栅极线272经形成使得其与漏极区域282及源极区域260两者间隔开。栅极线272也沿对应柱250列环绕半导体立柱252的中间区段256b,如上文关于图10所描述。
[0052]图20到22是图解说明所述方法的此实施例的额外阶段的横截面图。图20图解说明其中在衬底200中沉积或以其它方式形成电介质间隔件311的阶段。电介质间隔件311可为氮化物,且电介质间隔件311的厚度可经选择以填充其中栅极金属曾凹入以形成栅极线272的间隙。图21图解说明对电介质间隔件311进行间隔件蚀刻以暴露漏极区域282。更具体来说,可对电介质间隔件311进行间隔件蚀刻以在栅极线272上面且沿氧化物308的侧壁形成电介质间隔件314。因此暴露漏极区域282。图22图解说明后续阶段处的衬底200,其中在接触漏极区域282上方的开口中形成接触柱塞284。
[0053]图23是根据本技术的另一实施例用于形成垂直存储器单元阵列的方法400的流程图。在一个实施例中,方法400包含形成多个柱(框410),其中每一柱具有一半导体立柱及一牺牲帽。所述柱布置成间隔开一行间距的若干行及间隔开大于所述行间距的列间距的若干列。方法400可进一步包含在所述半导体立柱的近端区域处形成源极区域(框420)并形成在对应柱列中完全环绕所述半导体立柱的中间区段的导电栅极线(框430)。在形成所述栅极线之后,可在不形成对应于所述牺牲帽的图案的光图案的情况下选择性地移除所述牺牲帽且借此在所述半导体立柱中的每一者的远端部分上方形成自对准开口(框440)。方法400还可包含在所述自对准开口中形成电连接到对应半导体立柱的漏极触点(框450)。
[0054]从前文将了解,在本文中已出于图解说明目的描述了本发明的特定实施例,但尚未详细展示或描述众所周知的结构及功能以避免不必要地使对本发明的实施例的说明模糊。在上下文准许的情况下,单数或复数术语还可分别包含复数或单数术语。此外,除非词语“或”在参考两个或两个以上物项的列表时明确地被限定于仅意指排斥其它物项的单个物项,否则在此列表中使用“或”将被理解为包含(a)所述列表中的任一单个项目,(b)所述列表中的所有项目或(c)所述列表中项目的任一组合。另外,在通篇中术语“包括”用于意指包含至少所述的特征使得不排除任何更大数目个相同特征及/或额外类型的特征。因此,本发明不受除所附权利要求书以外的限定。