English:
[0002] Gallium nitride (GaN) semiconductor devices are increasingly desirable for power semiconductor devices because of their ability to carry large current and support high voltages. Development of these devices has generally been aimed at high power/high frequency applications. Devices fabricated for these types of applications are based on general device structures that exhibit high electron mobility and are referred to variously as heteroj unction field effect transistors (HFET), high electron mobility transistors (HEMT), or modulation doped field effect transistors (MODFET). These types of devices can typically withstand high voltages, e.g., 100 Volts, while operating at high frequencies, e.g., 100 kHz- 10 GHz.
[0003] A GaN HEMT device includes a nitride semiconductor with at least two nitride layers. Different materials formed on the semiconductor or on a buffer layer causes the layers to have different band gaps. The different material in the adjacent nitride layers also causes polarization, which contributes to a conductive two dimensional electron gas (2DEG) region near the junction of the two layers, specifically in the layer with the narrower band gap.
[0004] The nitride layers that cause polarization typically include a barrier layer of AlGaN adjacent to a layer of GaN to include the 2DEG, which allows charge to flow through the device. This barrier layer may be doped or undoped. Because of the 2DEG region existing under the gate at zero gate bias, most nitride devices are normally on, or depletion mode devices. If the 2DEG region is depleted, i.e. removed, below the gate at zero applied gate bias, the device can be an enhancement mode device. Enhancement mode devices are normally off and are desirable because of the added safety they provide. An enhancement mode device requires a positive bias applied at the gate in order to conduct current.
[0005] FIG. 1 illustrates a conventional GaN transistor device 100. Device 100 includes substrate 11 composed of silicon (Si), silicon carbide (SiC), sapphire, or other material, transition layers 12 typically composed of aluminum nitride (AlN) and aluminum gallium nitride (AlGaN) that is about 0.1 to about 1.0 μm in thickness, Mg doped GaN layer 10, buffer layer 13 typically composed of GaN that is about 0.5 to about 3 μm in thickness, current conducting region 14 composed of GaN or indium gallium nitride (InGaN) typically about 0.01 to about 0.5 μm in thickness, contact region 15 typically composed of AlGaN, Al and titanium (Ti) that may have Si, typically about 0.01 to about 0.03 μm in thickness, barrier layer 16 typically composed of AlGaN where the Al to Ga ratio is about 0.1 to about 0.5 with a thickness of about 0.01 to about 0.03 μm, gate structure 17 composed of a nickel (Ni) and gold (Au) metal contact, and ohmic contact metals 18, 19 composed of Ti and Al with a capping metal such as Ni and Au.
[0006] During growth of Mg doped GaN material in a conventional GaN transistor device (e.g., FIG. 1), magnesium (Mg) is added to the growth environment. This Mg accumulates on the surface of the GaN and becomes part of the crystal. In addition, Mg coats the walls of the growth chamber during this part of the growth. Growth of undoped GaN, with the intention of having material without Mg present, following the growth of Mg doped material is difficult due to the presence of Mg still residing on the surface of the GaN and other Mg on the walls of the chamber. This residual Mg will continue to contaminate the crystal for extended lengths of time as Mg moves easily about the growth chamber.
[0007] Conventional GaN transistors have many disadvantages. The breakdown voltage is limited by the width of the gate 17 (as shown in FIG. 1). To reach high voltages, a wide gate and large separation between gate 17 and drain contact 18 is required due to residual n-type doping from oxygen contamination and nitrogen vacancies in the undoped GaN material 13. In addition, conventional GaN transistors using Mg doping in the buffer layer suffer from changes in the conductivity caused by Mg near the barrier layer.
[0009] FIG. 1 illustrates a cross-sectional view of a conventional GaN transistor device.
[0010] FIG. 2 illustrates a cross-sectional view of an enhancement mode GaN transistor device formed according to a first embodiment of the present invention.
[0011] FIG. 3 is a graph of Mg concentration in a buffer layer for single and multiple row interrupts in comparison to non-interrupted or standard growth.
[0013] In the following detailed description, reference is made to certain embodiments. These embodiments are described with sufficient detail to enable those skilled in the art to practice them. It is to be understood that other embodiments may be employed and that various structural, logical, and electrical changes may be made.
[0014] The present invention is a GaN transistor device with a Mg growth interruption layer to trap excess or residual dopants, and a method for making such a device. The invention is designed to force reaction of Mg with nitrogen, for example, to form a less volatile material, i.e., magnesium nitride. This material is then covered by a layer of either GaN or AlGaN. The coating step can be done at lower temperatures as well to assist the coating. By lowering the temperature, less reaction between the MgN and Al or Ga will occur. The reaction of Al and MgN is such that AlN is formed and MgN is reduced to Mg. This reaction is in competition with the desired coating and entrapment of MgN. Thus, Mg will more readily remain in the MgN form if the reaction can be suppressed by reducing the temperature.
[0015] Referring to FIG. 2, a first embodiment is now described with reference to the formation of an enhancement mode GaN transistor. FIG. 2 illustrates a cross-sectional view of the device 200. Device 200 includes, from bottom up, substrate 31 , transition layers 32, Mg doped layer 33, growth interrupt layers 39, buffer layer 34, barrier layer 35, ohmic contact metals 36, 37, and gate structure 38. The growth interrupt layers (Mg diffusion barrier) 39 may be composed of one or more layers of highly Mg doped GaN. They are formed by interruption of growth and exposing the surface to ammonia. Other suitable dopants beside Mg may be used, including iron (Fe), nickel (Ni), manganese (Mn), calcium (Ca), vanadium (V), or other transition metals.
[0016] Formation of the structure of FIG. 2 will now be described with reference to Mg as the dopant, as an example. The transition layers 32 are formed by nucleation and growth on the substrate 31. Substrate 31 may be composed of silicon (Si), silicon carbide (SiC), sapphire, lithium gallium oxide (LiGaO2), gallium nitride (GaN), or other suitable material. Transition layers 32 may be composed of AlN, AlGaN, InAlGaN, SiO2, SiN, MgO, Al2O3, or combinations of these, preferably about 0.1 to about 1.0 μm in thickness. The transition layers 32 are typically less than about 1000 A in thickness. Then, the Mg doped layer 33 is grown. The Mg doped layer 33 may be composed of GaN that is about 0.1 to about 1. 0 μm in thickness with a Mg concentration between 1016atoms per cm3and 1019atoms per cm3. Next, the Mg blocking growth interrupt layers 39 are grown. The formation of the growth interrupt layers 39 consists of growing GaN without Mg- containing material, stopping a supply of Ga-containing materials while maintaining a supply of ammonia or other activated nitrogen source (e.g., plasma N2) to form a layer of magnesium nitride, beginning a supply of Ga to seal in the magnesium nitride layer by growing a layer of GaN, and interrupting growth again and repeating the above sequence until a target level of Mg in the final layer is reached. Next, buffer layer 34, barrier layer 35 and gate structure 38 are grown and material processing occurs to form gate contacts. Buffer layer 34 may be composed of GaN, preferably with a thickness of about 0.5 to about 3.0 μm. Barrier layer 35 may be composed of AlGaN where the Al fraction is about 0.1 to about 0.5, preferably with a thickness between about 0.01 and about 0.03 μm. The Al fraction is the content of Al such that Al fraction plus Ga fraction equals 1. Gate structure 38 may be composed of p-type GaN with a refractory metal contact such as tantalum (Ta), titanium (Ti), titanium nitride (TiN), tungsten (W), or tungsten suicide (WSi2). The gate structure can be simple metal, such as Ni under Au, or a semiconductor with metal such as GaN under TiN, or a semiconductor under insulator under metal such as GaN under SiN under TiN. Other semiconductors could be Si, GaAs, or InAlGaN. Other insulators could be AlGaN, InAlGaN, SiO2, SiN, MgO, Al2O3. Other metals could be Al, Ni, Au, Pt, etc. Also, in place of a metal, polysilicon could be used. The metal and gate layer are each preferably about 0.01 to about 1.0 μm in thickness. Total thickness for the gate structure would preferably be under 1 μm. Next, gate structure 38 is etched in other regions of the device and ohmic contacts 36, 37 are produced. Ohmic contact metals 36, 37 may be composed of titanium (Ti) and aluminum (Al) with a capping metal such as nickel (Ni) and gold (Au) or titanium (Ti) and titanium nitride (TiN). There can also be an implanted highly doped region associate d with the contact region. The primary channel region can be n-type doped GaN, or undoped or intrinsic InAlGaN.
[0017] In accordance with the above-described method, the addition of a p-type GaN layer 33 below the gate and a series of growth interrupt layers 39 reduces the level of Mg in the GaN buffer layer 34. The Mg doping of layer 33, in FIG. 2, increases the breakdown voltage of the device. The gate length of the device can be greatly reduced without reducing the breakdown voltage of the device. Gate capacitance of the device is reduced due to smaller gate length. Switching speed of the device is improved due to smaller gate capacitance. Growth interrupt layers 39 reduce Mg concentration in layer 34 and near the barrier layer 35.
[0018] FIG. 3 is a graph comparing the Mg concentration in a buffer layer without growth interrupt layers, a buffer layer with a single growth interrupt layer, and a buffer layer with six growth interrupt layers. As can be seen from the multiple growth interrupt curve, each growth interrupt produces a higher level of Mg at the position of the interrupt, followed by a lower level of Mg in the following layer. Each growth interrupt layer decreases the Mg, and by application of multiple layers, a low level of Mg can be obtained in a smaller distance.
[0019] Reduced Mg in layer 34 increases device conductivity. Reduced Mg in layer 34 also allows placement of layer 33 in close proximity to layer 35 without reduction in device conductivity. In addition, close proximity of layer 33 to 35 results in improved device breakdown and lower gate leakage currents. The structure of FIG. 2, however, has some drawbacks. The time required to produce growth interrupt layers 39 can be large, leading to increased cost of fabrication. Additionally, some Mg is still present in layer 34 due to contamination from reactor parts.
[0020] Referring to FIG. 4, a second embodiment is now described with reference to the formation of an enhancement mode GaN transistor. FIG. 4 illustrates a cross-sectional view of the device 300 formed by the method described below. This embodiment of the invention differs from the first embodiment in that the growth interrupt layers 39 of FIG. 2 are now replaced by AlGaN layers 49. The AlGaN layers (doped diffusion barrier) 49 may be composed of one or more layers of AlGaN. They are formed by interruption of growth and exposing the GaN surface to ammonia, similar to the first embodiment, followed by deposition of AlGaN and then GaN. The Al fraction of the AlGaN layers is between about 0.3 and about 1. The thickness of the AlGaN layers is preferably about 0.005 to about 0.03 μm.
[0021] Formation of the structure of FIG. 4 is similar to that described above with respect to the first embodiment (FIG. 2), with Mg as the dopant, as an example. The dimensions and compositions of the various layers are similar to that of the first embodiment as well. However, instead of forming growth interrupt layers 39 (FIG. T), AlGaN layers 49 are formed. The formation of AlGaN layers 49 consists of growing GaN without Mg-containing material, stopping a supply of Ga-containing materials while maintaining a supply of ammonia or other activated nitrogen source (e.g., plasma N2) to form a layer of magnesium nitride, reducing growth temperature, beginning a supply of Al and/or Ga to seal in the magnesium nitride layer by growing a layer of GaN, returning growth temperature to the initial temperature to grow GaN3and interrupting growth again and repeating the above sequence until a target level of Mg in the final layer is reached. The step of reducing the growth temperature and returning to the initial growth temperature is optional.
[0022] In accordance with the above-described method, the addition of a p-type GaN layer 43 below the gate and a series of growth interrupt and AlGaN layers 49 reduce the level of Mg in the GaN buffer layer 44. The second embodiment shares the same advantages of the first embodiment. Furthermore, the addition of the AlGaN layers to the diffusion barrier 49 improves the efficiency of each growth interrupt step, reducing the number of steps to achieve a desired level of Mg doping in the buffer layer 44.

中文:
[0002]对于功率半导体器件,氮化镓(GaN)半导体器件的需求日益增加,这是由于它们能够承载大电流并且支持高电压的能力。这些器件的发展通常旨在进行高功率/高频应用。为这些应用类型而制造的器件基于展示高电子迁移率的通用器件结构,并且这些器件被称为异质结场效应晶体管(HFET)、高电子迁移率晶体管(HEMT)或者调制掺杂场效应晶体管(MODFET)等各种名称。这些类型的器件典型地可以经受高电压,例如100伏特,同时在高频下运行,例如100kHz-10GHz。
[0003]GaN HEMT器件包括具有至少两个氮化物层的氮化物半导体。形成在该半导体或缓冲层上的不同材料使得这些层具有不同的带隙。相邻氮化物层中的不同材料还引起极化,这有助于在两层接合处附近,尤其在具有较窄带隙的层中形成导电二维电子气(2DEG)区。
[0004]引起极化的这些氮化物层通常包括临近GaN层的AlGaN阻挡层,以包括2DEG,其允许电荷流经器件。该阻挡层可以是掺杂或无掺杂的。由于在零栅偏压下门极下方存在2DEG区,所以大部分氮化物器件是常开型或者是耗尽型器件。如果在施加零栅偏压时在门极下方2DEG区被耗尽,即被移除,则该器件可以是增强型器件。增强型器件是常关型,并且由于它们提供的附加安全性而符合需要。为了传导电流,增强型器件需要在门极施加正偏压。
[0005]图1示出了常规GaN晶体管器件100。器件100包括由硅(Si)、碳化硅(SiC)、蓝宝石或其他材料形成的基底11,通常由氮化铝(AlN)和氮化铝镓(AlGaN)形成的厚度为约0.1至约1.0μm的过渡层12,掺杂Mg的GaN层10,通常由GaN形成的厚度为约0.5至约3μm的缓冲层13,由GaN或氮化铟镓(InGaN)形成的厚度通常为约0.01至0.5μm的电流传导区14,通常由AlGaN、Al和钛(Ti)形成的可以具有Si的厚度通常为约0.01至约0.03μm的接触区15,通常由AlGaN形成的厚度为约0.01至约0.03μm的阻挡层16,其中Al和Ga比例为约0.1至约0.5,由镍(Ni)和金(Au)金属触点形成的门极结构17,以及由具有诸如Ni和Au的封盖金属的Ti和Al形成的欧姆触点金属18和19。
[0006]在常规GaN晶体管器件(例如图1)中生长掺杂Mg的GaN材料期间,将镁(Mg)添加至生长环境中。该Mg积聚在GaN的表面上,并且成为晶体的一部分。此外,在该部分生长期间,Mg覆盖了生长腔的壁。在生长掺杂Mg的材料之后,为了获得不具有Mg的材料而生长未掺杂的GaN是困难的,这是因为在GaN的表面仍然残留有Mg并且在室壁上也具有Mg。由于Mg容易在生长腔移动,所以这些残余的Mg将继续污染晶体更长时间。
[0007]常规GaN晶体管具有许多缺点。击穿电压受到门极17宽度的限制(如图1中所示)。为了实现高电压,需要宽的门极以及门极17和漏极触点18之间的大间隔,这是由于在未掺杂GaN材料13中由于氧污染和氮空位导致的残余n-型掺杂。此外,使用掺杂在缓冲层中的Mg的常规GaN晶体管受到由阻挡层附近的Mg所引起的导电性改变的不良影响。
[0009]图1示出了常规GaN晶体管器件的横截面视图。
[0010]图2示出了根据本发明第一实施例形成的增强型GaN晶体管器件的横截面视图。
[0011]图3是与非中断或标准生长相比的单行中断和多行中断的缓冲层中的Mg浓度的曲线图。
[0013]在下列详述中,参考特定实施例。充分详细地描述这些实施例,以使得本领域技术人员能够实施这些实施例。应当理解的是,可以采用其他实施例,并且可以进行各种结构、逻辑和电气改变。
[0014]本发明涉及具有Mg生长中断层以捕获多余或残余的掺杂剂的GaN晶体管器件,以及用于制造该器件的方法。本发明被设计成迫使Mg与氮进行反应,例如形成较低挥发性的材料,即氮化镁。随后,该材料被一层GaN或AlGaN所覆盖。覆层步骤可以在较低的温度下进行,以协助覆层。通过降低温度,MgN与Al或Ga之间将发生较少的反应。Al和MgN的反应使得形成AlN,而MgN还原成Mg。该反应与所需覆层和MgN的捕获相竞争。因而,如果可以通过降低温度而抑制该反应,Mg将更易于以MgN的形式存留。
[0015]参考图2,现在参考增强型GaN晶体管的形成来描述第一实施例。图2示出器件200的截面视图。器件200自底向上地包括基底31、过渡层32、Mg掺杂层33、生长中断层39、缓冲层34、阻挡层35、欧姆接触金属36、37以及门极结构38。生长中断层(Mg扩散阻挡)39可以由一层或多层高度Mg掺杂的GaN构成。它们可以通过中断生长并且将表面暴露至氨而形成。可以使用除了Mg之外的其他合适的掺杂剂,包括铁(Fe)、镍(Ni)、锰(Mn)、钙(Ca)、钒(V)或其他过渡金属。
[0016]现在将参考Mg作为掺杂剂的一个实例,描述图2的结构的形成。通过在基底31上成核和生长形成过渡层32。基底31可以包括硅(Si)、碳化硅(SiC)、蓝宝石、氧化锂镓(LiGaO2)、氮化镓(GaN)或其他合适的材料。过渡层32可以包括AlN、AlGaN、InAlGaN、SiO2、SiN、MgO、Al2O3或其组合物,优选其厚度为约0.1至约1.0μm。过渡层32通常厚度小于约1000埃。随后,生长Mg掺杂层33。Mg掺杂层33可以包括GaN,其厚度为约0.1至约1.0μm,其中Mg的浓度在每cm3具有1016个原子和每cm3具有1019个原子之间。接着,生长阻挡Mg的生长中断层39。生长中断层39的形成包括生长不具有含Mg材料的GaN,停止提供含镓材料、同时维持提供氨或其他活性氮源(例如,等离子体N2),以形成一层氮化镁,开始提供Ga以通过生长一层GaN而封盖该氮化镁层,再次中断生长并重复上述顺序,直到实现最终层中的Mg的目标含量。接着,生长缓冲层34、阻挡层35和门极结构38,并且进行材料处理以形成门极触点。缓冲层34可以包括GaN,优选厚度为约0.5至约3.0μm。阻挡层可以包括AlGaN,其中Al组分比例为约0.1至约0.5,优选厚度在约0.01和约0.03μm之间。Al组分比例是Al在AlGaN的含量,其中Al组分比例加上Ga组分比例等于1。门极结构38可以包括p型GaN,其具有高熔点金属触点,诸如钽(Ta)、钛(Ti)、氮化钛(TiN)、钨(W)或硅化钨(WSi2)。门极结构可以是简单金属,如Au下的Ni,或者具有金属的半导体,如TiN下的GaN,或者金属下的绝缘体下的半导体,如TiN下的SiN下的GaN。其他半导体可以是Si、GaAs或InAlGaN。其他绝缘体可以是AlGaN、InAlGaN、SiO2、SiN、MgO、Al2O3。其他金属可以是Al、Ni、Au、Pt等。也可以使用多晶硅代替金属。金属和门极层优选厚度均为约0.01至约1.0μm。门极结构的总厚度优选低于1μm。接着,在器件的其他区域蚀刻门极结构38,并且形成欧姆触点36、37。欧姆触点金属36、37可以由具有诸如镍(Ni)和金(Au)或者钛(Ti)和氮化钛(TiN)的封盖金属的钛(Ti)和铝(Al)形成。还可以存在与接触区相关的被注入的高掺杂区。主沟道区可以使n型掺杂GaN、或未掺杂或本征InAlGaN。
[0017]根据上述方法,在门极下添加p型GaN层33和一系列生长中断层39减小了GaN缓冲层34中Mg的水平。在图2中,层33的Mg掺杂增大了器件的击穿电压。器件的门极长度可以显著地减小,而不减小器件的击穿电压。由于较小的门极长度,器件的门极电容减小。由于较小的门极电容,提高了器件的开关速度。生长中断层39减少了层34中和阻挡层35附近的Mg浓度。
[0018]图3是比较在不具有生长中断层的缓冲层中、具有单一生长中断层的缓冲层中和具有六层生长中断层的缓冲层中Mg浓度的曲线图。从多个生长中断曲线可见,每个生长中断在中断位置处形成较高水平的Mg,而在随后层中具有较低水平的Mg。每个生长中断层降低了Mg,并且通过应用多层,可以在较短的距离内获得低水平的Mg。
[0019]降低层34中的Mg增加器件的导电性。降低层34中的Mg还允许将层33设置紧密接近层35,而不降低器件的导电性。此外,层33与层35的紧密接近导致提高了器件的击穿电压,并且减小了门极漏电流。然而,图2的结构具有一些缺点。生成生长中断层39所需的时间会很长,导致增加制造成本。此外,因为反应器部件的污染,在层34中仍然存在一些Mg。
[0020]参考图4,现在参考增强型GaN晶体管的形成而描述第二实施例。图4示出了由下文所述方法形成的器件300的横截面视图。本发明的该实施例与第一实施例不同之处在于,图2的生长中断层39现在替换为AlGaN层49。AlGaN层49(掺杂扩散阻挡)可以包括一层或多层AlGaN。类似于第一实施例,它们通过中断生长和暴露GaN表面至氨、随后沉积AlGaN以及再沉积GaN而形成。AlGaN层中的Al组分比例在约0.3和约1之间。AlGaN层的厚度优选为约0.005至约0.03μm。
[0021]图4结构的形成类似于上述参考第一实施例(图2)所述,其中使用Mg作为掺杂剂,作为实例。各层的尺寸和成分也类似于第一实施例。然而,不形成生长中断层39(图2),而是形成AlGaN层49。AlGaN层49的形成包括生长不具有含Mg材料的GaN,停止提供含镓材料、同时维持提供氨或其他活性氮源(例如,等离子体N2),以形成一层氮化镁,降低生长温度,开始提供Al和/或Ga以通过生长一层GaN而封盖该氮化镁层,返回生长温度至初始温度以生长GaN,再次中断生长并重复上述顺序,直到实现最终层中的Mg的目标量级。降低生长温度和返回初始生长温度的步骤是任选的。
[0022]根据上述方法,在门极下添加p型GaN层43和一系列生长中断和AlGaN层49减少了GaN缓冲层44中的Mg的水平。第二实施例共享与第一实施例相同的优势。而且,向扩散阻挡49添加多个AlGaN层,提高了每个生长中断步骤的效率,减少了实现缓冲层44中Mg掺杂的所需水平的步骤数量。