English:
[0001] This disclosure relates generally to semiconductor processing, and more specifically, to forming semiconductor devices having extended active regions.
[0002] Semiconductor processing technologies typically impose various dimensional constraints related to active spaces and active widths. For example, a representative 90 nm node CMOS technology may allow a minimum active space of 140 nm and a minimum active width of 1 10 nm. Typically, such dimensional constraints are imposed to allow manufacturing tolerances during semiconductor processing and to ensure adequate device isolation. In particular, imposing such dimensional constraints may result in easier patterning of active regions and the subsequent filling of the gaps created by shallow trenches.
[0003] Such dimensional constraints, however, reduce design flexibility. For example, in certain instances wider active regions are desired to increase drive current, but cannot be implemented because of the rigid dimensional constraints imposed by conventional design and process methodologies. As an example, in the SRAM cells wider active regions can only be achieved at the cost of an increase in the cell size. Accordingly, there is a need for forming semiconductor devices having extended active regions while substantially complying with the dimensional constraints imposed by design rules related to a particular semiconductor processing technology.
[0004] The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
[0005] FIG. 1 is a cross-sectional view of a semiconductor device during a processing step;
[0006] FIG. 2 is a cross-sectional view of a semiconductor device during a processing step;
[0007] FIG. 3 is a cross-sectional view of a semiconductor device during a processing step;
[0008] FIG. 4 is a cross-sectional view of a semiconductor device during a processing step;
[0009] FIG. 5 is a cross-sectional view of a semiconductor device during a processing step;
[0010] FIG. 6 is a cross-sectional view of a semiconductor device during a processing step;
[0011] FIG. 7 is a cross-sectional view of a semiconductor device during a processing step;
[0012] FIG. 8 is a cross-sectional view of a semiconductor device during a processing step;
[0013] FIG. 9 is a cross-sectional view of a semiconductor device during a processing step;
[0014] FIG. 10 is a cross-sectional view of a semiconductor device during a processing step; and
[0015] FIG. 11 is a top view of the semiconductor device of FIG. 10 during a processing step.
[0016] By way of an example, in the same integrated circuit, active areas with different widths can be formed, where both types of active areas are at the minimum allowed pitch. This allows increased design flexibility by allowing the option to have standard drive current devices and higher drive current devices in the same integrated circuit. In one aspect, a method of forming a semiconductor device is provided. The method includes forming a trench adjacent to a first active area. The method further includes filling the trench with insulating material. The method further includes forming a masking feature over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. The method further includes etching into the first side of the trench to leave a first recess in the trench. The method further includes growing a first epitaxial region in the first recess to extend the first active area to include the first recess and thereby form an extended first active region.
[0019] FIG. 1 is a cross-sectional view of a semiconductor device 10 during a processing step. Semiconductor device 10 may be formed using a semiconductor substrate 12 using conventional semiconductor processing equipment. Semiconductor substrate 12 described herein can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above. Although an embodiment of the present invention is described using a bulk silicon substrate, other types of substrate, including SOI could also be used consistent with the present invention. A layer of pad oxide 14 may be grown over a top surface of substrate 12. By way of example, the pad oxide layer may be 5 nm to 25 nm thick. Next, a nitride layer 16 may be deposited over the layer of pad oxide. By way of example, the nitride layer may be 50 nm to 200 nm thick. Next, using semiconductor processing techniques, active regions 24, 26, 28, and 30 may be formed, such that these active regions are separated by trenches 18, 20, and 22, respectively.
[0020] Referring now to FIG. 2, trenches 18, 20, and 22 may be filled using an insulating material to form shallow trench isolation regions 32, 34, and 36. Next, the top surface of the shallow trench isolation regions may be planarized using chemical-mechanical polishing, for example.
[0021] Referring now to FIG. 3, nitride layer 16 may be removed from active regions 24, 26, 28 and 30 using a wet phosphoric etch, for example. Next, pad oxide layer 14 may be removed using a hydrofluoric etch, for example. As shown in FIG. 3, trench divots, such as a trench divot 46 may be formed as a result of the removal of the pad oxide layer. Next, sacrificial oxide layers 38, 40, 42, and 44 may be grown. Next, as shown in FIG. 4, a patterned photoresist layer including photoresist sections 48, 50, and 52 may be formed. With reference to FIG. 5, photoresist sections 48, 50, and 52 (also referred to as masking features) may be trimmed prior to etching. By way of example, trimming may include ashing. As an example, masking feature 50, formed over shallow trench isolation region 34, may leave exposed regions on both sides. Each exposed region may be between the edge of masking feature 50 and the corresponding active region.
[0022] Referring now to FIG. 6, sacrificial oxide layers 38, 40, 42, and 44 and a portion of the oxide in trench isolation regions 32, 34, and 36 may be removed creating recesses 54, 56, 58, and 60. By way of example, an isotropic dry etch using hydrofluoric acid (HF) or an anisotropic oxide dry etch may be used as part of this step. In one embodiment, the depth of the recesses may be 30 nm to 100 nm. Next, as shown in FIG. 7, photoresist sections 48, 50, and 52 may be removed.
[0023] Referring now to FIG. 8, silicon may be epitaxially grown to form epitaxial regions 62 and 66. This step results in selective widening of active regions. Thus, for example, the original active regions 64 and 68 are widened as a result of the grown epitaxial regions. At the same time, however, unpatterned areas are protected by sacrificial oxide layers 38 and 44, for example. Because silicon is grown epitaxially, it has the same crystal orientation as the original active silicon. Thus, using this process, selective active regions can be widened to provide more drive current, as needed. Moreover, the same shallow trench isolation regions are used to provide isolation for both widened and not-widened active regions. In other words, along with complying with dimensional constraints imposed by a technology, such as 90 nm CMOS, widened active regions can be formed. Although FIG. 8 describes the step as epitaxial growth of silicon, silicon may be provided in the recesses using other methods, as long as the provided silicon has the same crystal structure and orientation as the original silicon in the active regions.
[0024] Next, as shown in FIG. 9, the top surface device 10 may be polished to remove grown epitaxial regions, except the epitaxial growth formed in extended active regions 82 and 84, for example. By way of example, this step may be performed using chemical- mechanical polishing techniques. As a result of this step, active regions 70 and 72 may have a width 76 as opposed to original width 74. Specifically, extensions 78 and 80 may add to original width 74, as shown in FIG. 9. Extended active regions 82 and 84 may provide additional surface area resulting in a higher transistor drive current. The extension of active regions, however, may narrow shallow trench isolation region 34, as indicated by reference numeral 81. Next, as shown in FIG. 10, gate dielectric layers 86 and 88 may be formed over active regions 70 and 72. Moreover, a gate electrode layer 90 may be formed, as shown in FIG. 10. Additional spacers (not shown) may be formed to form transistors.
[0025] Referring now to FIG. 11 , which shows a top view of the device 10 of FIG. 10, transistors 96 and 98 may be formed having channel widths corresponding to active regions 92 and 94, respectively, with extended width 76, as compared with original width 74. In one embodiment, semiconductor device 10 may include a semiconductor structure (substrate 12, for example) having a top surface. Isolation regions 32, 34, and 36 may extend from the top surface of substrate 12 to a certain depth. Active region 92 may have a central portion (representative of area covered by active region 74, for example) and an adjacent portion (representative of area covered by active region 84, for example). The central portion of the active region may extend at least to the same depth as the depth of isolation regions 32, 34, and 36, for example. The adjacent portion may have a top portion that has a top surface that is in the same plane as the top surface of the central portion and it may have a bottom portion at no more than a certain depth that is less than the depth to which the central portion extends. As evident from the combination of the various views, at least a portion of isolation region 32 (shown in Figure 2, but not shown in Figure 11 ) may be directly under the bottom portion of the adjacent portion.
[0026] Moreover, the terms "front," "back," "top," "bottom," "over," "under" and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
[0027] Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
[0029] Unless stated otherwise, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

中文:
[0001]本公开一般地涉及半导体加工,并且更特别地涉及形成具有扩展的有源区的半导体器件。
[0002]半导体加工技术通常强加与有源空间和有源宽度有关的各种维度限制。例如,代表性的90nm节点CMOS技术可以允许140nm的最小有源空间和110nm的最小有源宽度。典型地,此类维度限制被强加以允许半导体加工期间的制造容差以及保证充分的器件隔离。特别地,强加此类维度限制可以导致更容易的有源区的图案化以及随后的由浅沟槽产生的间隙的填充。
[0003]但是,此类维度限制降低了设计灵活性。例如在特定情况下较宽的有源区对于增加驱动电流是期望的,但是由于传统设计和工艺方法所强加的严格维度限制而不能实施。作为例子,在SRAM单元中,较宽的有源区只能以增加单元尺寸为代价来实现。因而,有在基本符合由与特定半导体加工技术有关的设计规则所强加的维度限制时形成具有扩展的有源区的半导体器件的需求。
[0004]由附图以实例的方式例示本发明,而非限制本发明,其中相似的附图标记表示相似的元件。附图中的元件基于简洁和清楚而例示,且不必定按比例绘制。
[0005]图1是在加工步骤期间的半导体器件的截面图;
[0006]图2是在加工步骤期间的半导体器件的截面图;
[0007]图3是在加工步骤期间的半导体器件的截面图;
[0008]图4是在加工步骤期间的半导体器件的截面图;
[0009]图5是在加工步骤期间的半导体器件的截面图;
[0010]图6是在加工步骤期间的半导体器件的截面图;
[0011]图7是在加工步骤期间的半导体器件的截面图;
[0012]图8是在加工步骤期间的半导体器件的截面图;
[0013]图9是在加工步骤期间的半导体器件的截面图;
[0014]图10是在加工步骤期间的半导体器件的截面图;以及
[0015]图11是在加工步骤期间的图10的半导体器件的顶视图。
[0016]以实例的方式,在相同的集成电路中,可以形成具有不同宽度的有源区,其中两种类型的有源区都处于最小允许节距(pitch)。这通过允许在相同的集成电路中具有标准驱动电流器件和较高驱动电流器件而允许增加的设计灵活性。在一个方面,提供形成半导体器件的方法。该方法包括形成与第一有源区相邻的沟槽。该方法还包括用绝缘材料填充该沟槽。该方法还包括在该沟槽的中心部分上形成掩蔽特征物以在该掩蔽特征物的第一侧与第一有源区之间暴露该沟槽的第一侧。该方法还包括蚀刻到该沟槽的第一侧内以在该沟槽中留下第一凹部。该方法还包括在第一凹部中生长第一外延区以将第一有源区扩展成包括第一凹部,并由此形成扩展的第一有源区。
[0019]图1是加工步骤期间的半导体器件10的截面图。半导体器件10可以利用传统半导体加工设备使用半导体衬底12形成。这里描述的半导体衬底12可以是任意半导体材料或材料组合,诸如砷化镓、硅锗、绝缘体上硅(SOI)、硅、单晶硅等,以及上述材料的组合。尽管本发明的实施例用体硅衬底来描述,但是也可以使用符合本发明的其它类型的衬底,包括SOI。可以在衬底12的顶表面上生长垫氧化物层14。以实例的方式,垫氧化物层可以是5nm至25nm厚。接着,可以在垫氧化物层上沉积氮化物层16。以实例的方式,氮化物层可以是50nm至200nm厚。接着,使用半导体加工技术,可以形成有源区24、26、28和30,使得这些有源区分别由沟槽18、20和22分离。
[0020]现在参照图2,可以使用绝缘材料填充沟槽18、20和22以形成浅沟槽隔离区32、34和36。接着,可以使用例如化学机械抛光来平坦化浅沟槽隔离区的顶表面。
[0021]现在参照图3,可以使用例如湿法磷蚀刻从有源区24、26、28和30去除氮化物层16。接着,可以使用例如氢氟酸蚀刻去除垫氧化物层14。如图3所示,作为去除垫氧化物层的结果,可以形成诸如沟槽凹陷区(trench divot)46的沟槽凹陷区。接着,可以生长牺牲氧化物层38、40、42和44。接着,如图4所示,可以形成图案化的光致抗蚀剂层,其包括光致抗蚀剂区段48、50和52。参照图5,可以在蚀刻之前修整光致抗蚀剂区段48、50和52(也称为掩蔽特征物)。以实例的方式,修整可以包括灰化。作为实例,形成于浅沟槽隔离区34上的掩蔽特征物50可以在两侧上留下暴露区域。每个暴露区域可以在掩蔽特征物50的边缘与相应的有源区之间。
[0022]现在参照图6,可以去除牺牲氧化物层38、40、42和44以及沟槽隔离区32、34和36中的氧化物的一部分,产生凹部54、56、58和60。以实例的方式,使用氢氟酸(HF)的各向同性干法蚀刻或各向异性氧化物干法蚀刻可以被用作该步骤的一部分。在一个实施例中,凹部的深度可以是30nm至100nm。接着,如图7所示,可以去除光致抗蚀剂区段48、50和52。
[0023]现在参照图8,可以外延生长硅以形成外延区62和66。该步骤导致有源区的选择性加宽。因此,例如,作为所生长的外延区的结果,原始的有源区64和68被加宽。但是,同时,未被图案化的区域受例如牺牲氧化物层38和44的保护。由于硅是外延生长的,其具有与原始的有源区相同的晶体取向。因此,使用该工艺,选择的有源区可以被加宽以提供所需的更多的驱动电流。并且,使用相同的浅沟槽隔离区提供对于加宽的有源区和未加宽的有源区二者的隔离。换言之,既符合由技术(诸如90nm CMOS)所强加的维度限制,又可以形成加宽的有源区。尽管图8将该步骤描述为硅的外延生长,但是可以使用其它方法在凹部中提供硅,只要所提供的硅具有与有源区中的原始的硅相同的晶体结构和取向即可。
[0024]接着,如图9所示,可以抛光顶表面器件10以去除生长的外延区,除了例如形成于扩展的有源区82和84中的外延生长区之外。以实例的方式,该步骤可以使用化学机械抛光技术进行。作为该步骤的结果,有源区70和72可以具有与原始的宽度74相对的宽度76。具体地,延长78和80可以添加到原始宽度74,如图9所示。扩展的有源区82和84可以提供附加的表面面积,导致更高的晶体管驱动电流。但是,有源区的扩展可以使浅沟槽隔离区34变窄,如附图标记81所示。接着,如图10所示,可以在有源区70和72上形成栅极电介质层86和88。并且,可以形成栅电极层90,如图10所示。可以形成附加的间隔件(未示出)以形成晶体管。
[0025]现在参照图11,其示出图10的器件10的顶视图。晶体管96和98可以被形成为分别具有与有源区92和94对应的沟道宽度,与原始宽度74相比具有扩展的宽度76。在一个实施例中,半导体器件10可以包括具有顶表面的半导体结构(例如,衬底12)。隔离区32、34和36可以从衬底12的顶表面延伸到一定深度。有源区92可以具有中心部分(例如,以由有源区74覆盖的区域为代表)和相邻部分(例如,以由有源区84覆盖的区域为代表)。有源区的中心部分可以至少延伸到例如与隔离区32、34和36的深度相同的深度。相邻部分可以具有顶部,该顶部具有与该中心部分的顶表面处于同一平面的顶表面,并且该相邻部分可以具有在不大于一定深度处的底部,该一定深度小于该中心部分所延伸到的深度。由各个视图的组合明显可见,隔离区32的至少一部分(在图2中示出,但在图11中未示出)可以直接位于该相邻部分的底部下。
[0026]并且,说明书和权利要求中的用语“前”、“后”、“底”、“上”、“下”等(如果有的话),被用于描述目的而非必定描述永久的相对位置。应该理解所使用的用语在适当情况下是可互换的,使得这里描述的本发明的实施例例如能够在不同于这里例示或描述的取向的其它取向下操作。
[0027]尽管这里参考具体实施例描述了本发明,但是可以做出各种修改和改变,而不脱离如以下权利要求中所提出的本发明的范围。因而,说明书和附图应该被视为示例性的而不是限制性的概念,并且所有这些修改预期被包括在本发明的范围内。这里针对具体实施例描述的任何益处、优点或对于技术问题的方案不预期被解释为任何或所有权利要求的关键、需要或必要特征或要素。
[0029]除非另有声明,诸如“第一”和“第二”的用语被用来在此类用语描述要素之间进行任意区分。因此,这些用语不必定预期表示此类要素的时间或其它优先权。