English:
[0001] The present invention relates generally to methods of forming semiconductor devices, and more particularly to semiconductor processes for forming nanoclusters or silicon dots.
[0002] When silicon dots, which are commonly called nanoclusters or nanocrystals, are formed in a non-volatile memory (NVM) of an integrated circuit, the nanocrystals that are deposited need to be preserved during subsequent processing. Typically, further processing required for various transistor types creates difficulties with preserving the nanocrystals. It is not unusual to have three different gate dielectric thicknesses for transistors of different purposes. The thinnest gate dielectrics are for the logic transistors that are normally for the fastest speeds. Another thickness is for the transistors used as the inputs and outputs of voltage signals to and from the integrated circuit. The largest thickness is for the high voltage transistors that are used for the highest voltages in the particular integrated circuit such as for programming and erasing the NVM transistors. The extra processing for one or more of these transistor types, especially the high voltage transistors, often includes exposure to highly oxidizing ambients that can degrade or consume the nanocrystals. This can also cause an increase in oxide growth from the substrate which increases the gate dielectric thickness. This increased thickness in gate dielectric is uneven because of the presence of the nanocrystals.
[0003] On the other hand a difficulty with making the regular (non-NVM) transistor gate dielectrics first is that these gate dielectrics are then subjected to etches during the formation of the gate dielectrics of the NVM devices. These etches adversely affect the gate dielectrics and result in reduced transistor performance. Thus the typical approach has been to form the NVM gate dielectrics followed by the regular transistor gate dielectrics.
[0004] Accordingly there is a need for a process that improves on one or more of the above described problems.
[0005] The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which:
[0006] In one aspect, a semiconductor device has at least three different types of transistors one of which is an NVM transistor that uses nanocrystals for charge storage. One of the transistor types is a high voltage transistor that has a relatively thick gate dielectric. This thick gate dielectric has a very thin nitrogen-rich oxide layer, preferably formed using decoupled plasma nithdation, that is sufficiently uniform to cover the thick gate dielectric. This nitrogen-rich oxide layer has minimal impact on the electrical characteristics of the gate dielectric because it is very thin but provides a good etch stop because it has substantially the etch characteristics of nitride and is uniform. Also because it is nitrogen-rich oxide it suffers minimal damage during subsequent formation of the gate dielectric of the NVM transistor. A gate dielectric, thinner than the gate dielectric of the high voltage transistor, of a regular transistor is formed after the gate dielectric of the NVM transistor. This thinner gate dielectric causes less problem with degradation of the nanocrystals than would the process for forming the gate dielectric of the high voltage transistor. This is better understood with reference to the drawings and the following description.
[0007] Shown in FIG. 1 is a semiconductor device 10 comprising a semiconductor substrate 12, an oxide layer 18 on substrate 12, a region 14 in substrate 12, a region 16 in substrate 12, and an isolation region 17 surrounding a portion of substrate 12. Substrate 12 is preferably silicon but could be another semiconductor material or combination of materials such as silicon germanium (SiGe). Region 14 is a well region for forming high voltage transistors. Region 16 is a well region for forming transistors used in providing inputs and outputs (I/O transistors) of semiconductor device 10. Oxide layer 18 is the principal portion of a gate dielectric for high voltage transistors formed in region 14. Oxide is a preferred material for gate dielectrics but another gate dielectric material that has high selectivity to an etch chemistry that is used to etch oxide and nanocrystals can be used. Region 14 is preferably doped for optimizing the high voltage transistors. Similarly Region 16 is doped for optimizing the I/O transistors. Isolation region 17 is of an oxide trench penetrating into substrate 12. The portion of substrate 12 surrounded by isolation region 17 is for forming non-volatile memory (NVM) transistors. Oxide layer 18 is preferably about 150 Angstroms thick. The thickness chosen is related to how high the voltage is that will be used by the high voltage transistors. Regions 14 and 16 are preferably about 3 to 5 thousand Angstroms deep. This depth may vary even further. Isolation 17 is about 2 to 4 thousand Angstroms in depth. Typically the isolation need not be as deep as the well, but there may be instances where isolation is as deep as the well. The lateral dimension of regions 14 and 16 and the distance across region 17 can vary greatly depending upon the number of transistors and the sizes of those transistors that are to be formed in those locations. A well may contain an entire memory array or just one transistor. Although not shown, regions 14 and 16 preferably have isolation regions similar to isolation 17 surrounding them.
[0008] Shown in FIG. 2 is semiconductor device 10 after performing decoupled plasma nitridation (DPN) on oxide layer 18 to form a nitrogen-rich oxide layer 20 on oxide layer 18. This nitrogen-rich oxide layer is preferably very thin, no more than 10 Angstroms, be sufficiently uniform to completely cover oxide layer 18, and have a nitrogen concentration not more than 10 atomic percent. DPN is capable of achieving this uniformity while achieving a thickness less than 10 Angstroms. Further typical nitride deposition processes are not capable of forming such a thin layer or of having the desired low concentration of nitrogen. Even atomic layer deposition (ALD) has been found to not be uniform for nitride until about 5 layers or more are deposited, which is much more than 10 Angstroms, or be able to achieve the desired low concentration of nitrogen. With DPN, even 5 Angstroms may be achievable. Alternately remote plasma nitridation may also be effective to form nitrogen-rich oxide layer 20. Nitrogen-rich oxide layer 20, although not stoichiometric silicon nitride, has many of the characteristics of nitride. In particular, it has high selectivity to certain etchants that are used for etching oxide. For example, hydrofluoric acid etches oxide very much faster than nitrogen-rich oxide such as layer 20. While it is desirable to have sufficient nitrogen concentration to achieve this desired etch characteristic, it is also desirable to have a low nitrogen concentration, less than 10 atomic percent, to more closely preserve the electrical characteristics of oxide. An effective DPN process or achieving this balance is to expose the wafer to a remote nitrogen plasma with plasma power between 200W and 600W, nitrogen partial pressure between 1 mTorr and 50mTorr and wafer temperature between 25C and 300C.
[0009] Shown in FIG. 3 is semiconductor device 10 after performing a patterned implant inside isolation 17. The result is a region 22 that is a well that is doped for the purpose of forming NVM transistors.
[0010] Shown in FIG. 4 is semiconductor device 10 after performing a patterned etch of nitrogen-rich oxide layer 20 and oxide layer 18 over region 22. The etch is aligned to isolation 17 so alignment is easily achieved.
[0011] Shown in FIG. 5 is semiconductor device 10 after forming a gate dielectric 24 on region 22 by growing oxide and forming a charge storage layer comprised of a plurality of nanocrystals 26 on gate dielectric 24 and over nitrogen-rich oxide layer 20 and an oxide layer 30 over and around plurality of nanocrystals 26. Oxide layer 30 is a deposited oxide, preferably what is commonly called high temperature oxide (HTO). Oxide layer 30 is about 150 Angstroms thick. Nanocrystal 28 is a nanocrystal of plurality of nanocrystals 26 that is over region 22 and on gate dielectric 24. Because oxide layer 30 is deposited, there is not very much free oxygen to react with nanocrystals 26 during the deposition of oxide layer 30.
[0012] Shown in FIG. 6 is semiconductor device 10 after etching the charge storage layer by etching oxide layer 30 and nanocrystals 26 to leave oxide layer 30 and nanocrystals 26 over gate dielectric 24. This etch is preferably a wet etch of hydrofluoric acid. This is very effective for etching oxide and highly selective to nitride. Thus, the etch removes oxide layer 30 and nanocrystals 26 and except over region 22 which is masked off during this patterned etch. Nitrogen-rich oxide layer 20 thus protects oxide layer 18 over region 14. If nitrogen-rich oxide layer 20 were not present, the etchant that removes oxide layer 30 would also necessarily etch into layer 18 which is oxide. Not only would that make it difficult to control the thickness of oxide layer 18 over region 14, where oxide layer 18 will be the gate dielectric, but it also would make the surface rough, adversely impacting transistor performance such as leakage.
[0013] Shown in FIG. 7 is semiconductor device 10 after performing a patterned etch over region 16 to expose region 16.
[0014] Shown in FIG. 8 is semiconductor device 10 after forming gate dielectric 32 by growing oxide on region 16. Gate dielectric 32 is preferably about 50 Angstroms thick.
[0015] Shown in FIG. 9 is a semiconductor device 10 after forming region 34 in substrate 12 by a patterned implant. Region 34 functions as a well for forming logic transistors. These transistors are for the fast logic circuits of an integrated circuit having thinner gate dielectrics than the I/O transistors have. Region 34 preferably has isolation, not shown, similar to isolation 17 around it.
[0016] Shown in FIG. 10 is semiconductor device 10 after performing a patterned etch over region 34 to expose region 34.
[0017] Shown in FIG. 11 is semiconductor device 10 after forming gate dielectric 36 by growing oxide on region 34. Gate dielectric 36 is preferably about 20 Angstroms thick.
[0018] Shown in FIG.12 is semiconductor device 10 after forming a transistor 38, which is a high voltage transistor, over and in region 14; a transistor 40, which is an NVM transistor, over and in region 22; transistor 42, which is an I/O transistor, over and in region 16; and a transistor 44, which is a logic transistor, over an in region 34. Thus the high voltage transistor has oxide layer 18 and nitrogen-rich oxide layer 20 as its gate dielectric. The NVM transistor has a gate dielectric of oxide layer 24 and a storage layer of oxide layer 30 over and around nanocrystals such as nanocrystal 28. The I/O transistor has oxide layer 32 as its gate dielectric. The logic transistor has oxide layer 36 as its gate dielectric.
[0019] Thus, it is seen that there is a benefit of having a nitrogen-rich oxide layer 20 to act as an etch stop in order to protect the gate dielectric of the high voltage transistor. Using DPN, the nitrogen-rich oxide layer can be made both thin so as to have minimal affect on transistor characteristics and sufficiently uniform to protect the gate dielectric. The formation of the NVM gate dielectric after formation of the thick grown gate dielectric of the high voltage transistor avoids the nanocrystals and NVM gate dielectric being subjected to oxygen during that relatively long oxide growth at high temperature. The shorter oxide growths for the I/O and logic transistors are performed after the removal of the nanocrystals so there is reduced negative impact by the oxide growth on the NVM gate dielectric and nanocrystals and the gate dielectrics for the I/O and logic transistors are not subjected to the etch that removes the charge storage layer that includes the nanocrystals.
[0020] In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.
[0021] Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms a or an, as used herein, are defined as one or more than one. The term plurality, as used herein, is defined as two or more than two. The term another, as used herein, is defined as at least a second or more. The terms including and/or having, as used herein, are defined as comprising (i.e., open language). The term coupled, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically.
[0022] In one view a semiconductor device is made on a semiconductor substrate. A first insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a high voltage transistor in a first region of the semiconductor substrate. After the first insulating layer is formed, a second insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a non-volatile memory transistor in a second region of the substrate. After the second insulating layer is formed, a third insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a logic transistor in a third region of the substrate. Further after the step of forming the second insulating layer, the method may form nanocrystals over the semiconductor substrate. Further the method may include forming a fourth insulating layer over the first insulating layer prior to the step of forming the second insulating layer and removing the nanocrystals over the first region and the third region prior to the step of forming the third insulating layer. Further the method may include removing the first and fourth insulating layer from over the second region prior to the step of forming the second insulating layer. Further the method include removing the first and fourth insulating layer from over the third region after the step of removing the first and fourth layer from over the second region and prior to the step of forming the third insulating layer. As an alternative the method may further be characterized by the step of forming the fourth insulating layer comprising performing a step of decoupled plasma nitridation on the first layer. In addition the method may be further characterized by the step of forming the fourth insulating layer being further characterized by the fourth insulating layer comprising nitrogen- rich oxide. Yet further the method may be characterized by the step of forming the fourth insulating layer being further characterized by the fourth insulating layer not exceeding 10 Angstroms in thickness. In addition the method may be further characterized by the step of forming the fourth insulating layer being further characterized by the fourth insulating layer having a nitrogen concentration not exceeding 10 atomic percent. Yet further the method may be further characterized by the step of removing the nanocrystals comprising performing a wet etch using hydrofluoric acid. In addition the method may be further characterized by the step of forming the first insulating layer comprising growing oxide on the semiconductor substrate. Additionally, in one aspect the method may further comprise forming a fifth insulating layer, after the step of forming the second insulating layer, on the semiconductor substrate for use as a gate dielectric for an I/O transistor.
[0023] In another view, there is a method of making a semiconductor device on a semiconductor substrate. A first oxide layer is grown on the semiconductor substrate. Plasma nithdation is performed on the first oxide layer to form a nitrogen- rich oxide layer on the first oxide layer. The first oxide layer and the nitrogen-rich layer are selectively removed to leave the first oxide layer and the nitrogen-rich oxide layer over a first region of the substrate and remove the first oxide layer and the nitrogen-rich oxide layer from over a second region of the substrate. A second oxide layer is grown over the second region. A nanocrystal layer is formed over the semiconductor substrate after the step of growing the second oxide layer. The nanocrystal layer is removed from over the first region and a third region of the substrate. After the step of removing the nanocrystal layer, selectively removing the first oxide layer and the nitrogen-rich oxide layer to leave the first oxide layer and the nitrogen-rich oxide layer over the first region of the substrate and remove the first oxide layer and the nitrogen-rich oxide layer from over the third region of the substrate. A third oxide layer is grown over the third region. A first transistor of a first type is formed in and over the first region using the first oxide layer and nitrogen- rich oxide layer as a gate dielectric of the first transistor. A second transistor of a second type is formed in and over the second region using the second oxide layer as a gate dielectric of the second transistor. A third transistor of a third type is formed in and over the third region using the third oxide layer as a gate dielectric of the third transistor. The method may be further characterized by the step of growing the first oxide layer being further characterized by the first oxide layer having a first thickness, the step of growing the second oxide layer being further characterized by the second oxide layer having a second thickness less than the first thickness, and the step of growing the third oxide layer being further characterized by the third oxide layer having a third thickness less than the second thickness. Also the method may be further characterized by the step of forming the first transistor being further characterized by the first transistor being a high voltage transistor, the step of forming the second transistor is further characterized by the second transistor being a non-volatile memory transistor, and the step of forming the third transistor is further characterized by the third transistor being a logic transistor. Also the method may be further characterized by the step of removing the nanocrystal layer further comprising removing the nanocrystal layer from over a fourth region of the substrate and the method may further comprise selectively removing, after the step of removing the nanocrystals, the first oxide layer and the nitrogen-rich oxide layer to leave the first oxide layer and the nitrogen-rich oxide layer over the first region of the substrate and remove the first oxide layer and the nitrogen-rich oxide layer from over the fourth region of the substrate, growing a fourth oxide layer over the fourth region, and forming a fourth transistor of a fourth type on and over the fourth region using the fourth oxide layer as a gate dielectric of the fourth transistor. Also the method may be further characterized by the step of performing decoupled plasma nitridation being further characterized by the nitrogen-rich oxide layer being not more than 10 Angstroms in thickness. Also the method may be further characterized by the step of performing decoupled plasma nitridation being further characterized by the nitrogen-rich oxide layer having a nitrogen concentration not exceeding 10 atomic percent
[0024] In a further view, a semiconductor device comprises a high voltage transistor, a non-volatile memory transistor; an a logic transistor. The high voltage transistor has a gate dielectric comprising an oxide layer and a nitrogen-rich oxide layer, wherein the nitrogen-rich oxide layer is not more than 10 Angstroms thick and has a concentration of nitrogen not in excess of 10 atomic percent; wherein the oxide layer has a first thickness. The non-volatile memory transistor has a gate dielectric of a second thickness less than the first thickness. The logic transistor has a gate dielectric of a third thickness less than the second thickness. Further the semiconductor device may further comprise an I/O transistor having a gate dielectric of a fourth thickness greater than the third thickness and less than the first thickness.

中文:
[0001]本发明一般地涉及形成半导体器件的方法,以及更特别地涉及形成纳米团簇或硅点的半导体工艺。
[0002]当通常被称作纳米团簇或纳米晶的硅点形成于集成电路的非易失性存储器(NVM)中的时候,被沉积的纳米晶需要在随后的处理过程中予以保留。典型地,为了各种晶体管类型而需要的进一步处理给保留纳米晶造成了困难。为了不同用途的晶体管而具有三种不同的栅极电介质厚度是不常见的。最薄的栅极电介质用于通常为了最快速度的逻辑晶体管。另一厚度用于被用作电压信号进出集成电路的输入端及输出端的晶体管。最大的厚度用于高压晶体管,该高压晶体管被用于特殊集成电路中的最高电压,例如用于编程以及擦除NVM晶体管的集成电路。用于一个或多个这些晶体管类型(尤其是高压晶体管)的额外处理通常包括暴露给能够使纳米晶退化或者消耗纳米晶的高氧化环境。这同样能够引起基板上的氧化物生长的增加,这增加了栅极电介质厚度。由于纳米晶的存在,栅极电介质这种增加的厚度是不均匀的。
[0003]另一方面,制造常规的(非NVM)晶体管栅极电介质的困难首先是在NVM器件的栅极电介质的形成过程中,这些栅极电介质另外受到了蚀刻。这些蚀刻对栅极电介质产生不利的影响并且导致晶体管性能降低。因而典型的方法是先形成NVM栅极电介质,随后是常规的晶体管栅极电介质。
[0004]因此,需要在上述问题中的一个或多个方面作出改进的工艺。
[0005]本发明在附图中以实例而非局限的方式来说明,在附图中相同的标记表示类似的元件,并且其中:
[0006]一方面,半导体器件至少具有三种不同类型的晶体管,其中之一是将纳米晶用于电荷存储的NVM晶体管。所述晶体管类型之一是具有相对厚的栅极电介质的高压晶体管。这种厚的栅极电介质具有很薄的富氮氧化物层,优选使用脱耦等离子体氮化来形成的,该富氮氧化物层充分均匀以覆盖厚的栅极电介质。该富氮氧化物层对栅极电介质的电特性的影响极小,因为虽然它很薄,但由于它基本上具有氮的蚀刻特性并且是均匀的,所以提供了良好的蚀刻终止。同样因为它是富氮氧化物,所以它在NVM晶体管的栅极电介质随后的形成过程中受到的损害最小。比高压晶体管的栅极电介质更薄的常规晶体管的栅极电介质在NVM晶体管的栅极电介质之后形成。该较薄的栅极电介质在纳米晶退化方面引起的问题比用于形成高压晶体管栅极电介质的工艺所引起的更小。这参照附图及以下的描述更容易理解。
[0007]图1显示了半导体器件10,该半导体器件10包括半导体基板12、基板12上的氧化物层18、基板12内的区域14、基板12内的区域16,以及包围着一部分基板12的隔离区17。基板12优选是硅,但也可以是别的半导体材料或材料组合,例如锗硅(SiGe)。区域14是用于形成高压晶体管的阱区。区域16是用于形成用来提供半导体器件10的输入端及输出端(I/O晶体管)的晶体管的阱区。氧化物层18是形成于区域14内的高压晶体管的栅极电介质的主要部分。氧化物是栅极电介质的优选材料,但也能够使用对用来蚀刻氧化物及纳米晶的蚀刻化学具有高选择性的别的栅极电介质材料。为了优化高压晶体管,优选掺杂区域14。同样,为了优化I/O晶体管,掺杂区域16。隔离区17是穿入基板12的氧化物沟槽。基板12由隔离区17包围的部分用于形成非易失性存储器(NVM)晶体管。氧化物层18优选约为150埃厚。所选的厚度与将由高压晶体管使用的电压为多高有关。区域14和16优选约为3~5千埃深。该深度可以更进一步改变。隔离17深度约为2~4千埃。典型地,隔离区不需要像阱那么深,但是可能存在隔离区像阱那么深的实例。区域14和16的横向尺寸以及跨区域17的距离能够依据将要在那些位置形成的晶体管数量及其尺寸而大大地改变。阱可以包含全部存储器阵列或者仅仅是一个晶体管。虽然没有显示,但是区域14和16优选具有与包围它们的隔离区17相似的隔离区。
[0008]图2显示了在氧化物层18上进行脱耦等离子体氮化(DPN)以在氧化物层18上形成富氮氧化物层20之后的半导体器件10。该富氮氧化物层优选很薄,不大于10埃,充分均匀以完全覆盖氧化物层18,以及具有不大于10原子百分比的氮浓度。DPN能够在获得小于10埃的厚度的同时获得这种均匀性。而且典型的氮化物沉积工艺无法形成这样的薄层或者具有氮的期望低浓度。甚至已经发现,对于氮化物,原子层沉积(ALD)直到沉积了大约5层或更多的层才会均匀,这远大于10埃,或者无法获得氮的期望低浓度。使用DPN,甚至连5埃也可以获得。作为选择,远距等离子体氮化同样可以有效形成富氮氧化物层20。虽然不是化学计量比氮化硅,但是富氮氧化物层20具有氮化物的许多特性。特别地,它对某些用来蚀刻氧化物的蚀刻剂具有高选择性。例如,氢氟酸蚀刻氧化物远快于蚀刻富氮氧化物,例如层20。虽然希望具有充足的氮浓度以获得这种期望的蚀刻特性,但同样希望具有低的氮浓度,小于10原子百分比,以尽量保留氧化物的电特性。有效的DPN工艺或者该平衡的获得是使晶片暴露于远距氮等离子体下,等离子体功率在200W~600W之间,氮分压在1mTorr~5mTorr之间以及晶片温度在25°C~300°C之间。
[0009]图3显示了在隔离区17内部进行图形化植入之后的半导体器件10。结果是区域22,该区域22是为了形成NVM晶体管而掺杂的阱。
[0010]图4显示了对区域22上方的富氮氧化物层20及氧化物层18进行图形化蚀刻之后的半导体器件10。使蚀刻与隔离区17对齐因而容易实现对准。
[0011]图5显示了通过生长氧化物以在区域22上形成栅极电介质24以及形成电荷存储层之后的半导体器件10,该电荷存储层包括栅极电介质24上及富氮氧化物层20上方的许多纳米晶26以及许多纳米晶26的上方及周围的氧化物层30。氧化物层30是沉积氧化物,优选是通常被称作高温氧化物(HTO)的沉积氧化物。氧化物层30约为150埃厚。纳米晶28是许多纳米晶26中在区域22上方并且在栅极电介质24上的纳米晶。因为氧化物层30被沉积,所以没有很多的自由氧在氧化物层30的沉积过程中与纳米晶26反应。
[0012]图6显示了通过蚀刻氧化物层30及纳米晶26以留下栅极电介质24上方的氧化物层30及纳米晶26的方式来蚀刻电荷存储层之后的半导体器件10。该蚀刻优选为氢氟酸的湿法蚀刻。这对于蚀刻氧化物是非常有效的并且对氮化物是高选择性的。因而,蚀刻去除了区域22上方之外的氧化物层30及纳米晶26,该区域22在该图形化蚀刻的过程中被屏蔽。从而富氮氧化物层20保护区域14上方的氧化物层18。如果富氮氧化物层20不存在,去除氧化物层30的蚀刻剂同样会不可避免地蚀刻到为氧化物的层18中。不仅将会难以控制区域14上方的氧化物层18的厚度(这里氧化物层18将是栅极电介质),而且将会使表面粗糙,对晶体管性能产生不利影响,例如泄漏。
[0013]图7显示了在区域16上方进行图形化蚀刻以使区域16暴露之后的半导体器件10。
[0014]图8显示了通过在区域16上生长氧化物来形成栅极电介质32之后的半导体器件10。栅极电介质32优选约为50埃厚。
[0015]图9显示了通过图形化植入而在基板12中形成区域34之后的半导体器件10。区域34起着形成逻辑晶体管的阱的作用。这些晶体管用于栅极电介质比I/O晶体管的更薄的集成电路的快速逻辑电路。区域34优选具有与隔离17相似的在其周围的隔离区(没有显示)。
[0016]图10显示了在区域34上方进行图形化蚀刻以使区域34暴露之后的半导体器件10。
[0017]图11显示了通过在区域34上生长氧化物来形成栅极电介质36之后的半导体器件10。栅极电介质36优选约为20埃厚。
[0018]图12显示了形成晶体管38、40、42及44之后的半导体器件10,其中晶体管38是在区域14之上及之中的高压晶体管;晶体管40是在区域22之上及之中的NVM晶体管;晶体管42是在区域16之上及之中的I/O晶体管;以及晶体管44是在区域34之上及之中的逻辑晶体管。因而高压晶体管具有氧化物层18及富氮氧化物层20作为它的栅极电介质。NVM晶体管具有氧化物层24构成的栅极电介质以及在例如纳米晶28的纳米晶上方及周围的氧化物层30构成的存储层。I/O晶体管具有氧化物层32作为它的栅极电介质。逻辑晶体管具有氧化物层36作为它的栅极电介质。
[0019]因而,可以看出为了保护高压晶体管的栅极电介质而使富氮氧化物层20作为蚀刻终止是有利的。使用DPN,能够使富氮氧化物层既是薄的使得对晶体管特性的影响极小,也是充分均匀的以保护栅极电介质。在高压晶体管的厚生长栅极电介质形成之后形成NVM栅极电介质避免了纳米晶及NVM栅极电介质在该相对较长的氧化物于高温下生长的过程中受到氧的影响。I/O及逻辑晶体管的较短氧化物生长在去除纳米晶之后进行,因而减少了氧化物生长对NVM栅极电介质及纳米晶的负面影响并且I/O及逻辑晶体管的栅极电介质没有受到去除包含纳米晶的电荷存储层的蚀刻的影响。
[0020]在上述说明中,本发明已经参照具体的实施方案进行了描述。但是,本领域技术人员会意识到能够在不背离本发明如下文中的权利要求所阐明的范围的情况下进行不同的修改和更改。因此,说明书及附图应被看作是说明性的而不是限制性的,以及所有此类修改都意欲包括在本发明的范围之内。
[0021]益处、其他优点,以及问题的解决方案已经在上文针对具体的实施方案进行了描述。但是,益处、优点、问题的解决方案,以及可以促使任何益处、优点或解决方案产生或者变得更显著的任何要素不应被看作是关键的、必需的或本质的特征或者是任何或所有权利要求的要素。如在此所使用的,术语“包含”、“包括”,或其任何其他形式变形均意指涵盖非排它的包含,使得包含列示的要素的过程、方法、物品,或装置不只是包括那些要素而且还可以包括没有明确列出的或者非此类过程、方法、物品或装置所固有的其他要素。术语一或一个,如在此所使用的,被定义为一个或一个以上。术语多个,如在此所使用的,被定义为两个或两个以上。术语另一个,如在此所使用的,被定义为至少第二个或更多。术语包括和/或具有,如在此所使用的,被定义为包含(即,开放的语言)。术语耦合的,如在此所使用的,被定义为连接的,虽然不一定直接连接,也不一定机械上连接。
[0022]从一个角度来看,半导体器件被制造在半导体基板上。第一绝缘层被形成于半导体基板上以用作半导体基板第一区域内的高压晶体管的栅极电介质。在第一绝缘层形成之后,第二绝缘层被形成于半导体基板上以用作在基板的第二区域内的非易失性存储器晶体管的栅极电介质。在第二绝缘层形成之后,第三绝缘层被形成于半导体基板上以用作在基板的第三区域内的逻辑晶体管的栅极电介质。此外,在形成第二绝缘层的步骤之后,方法可以在半导体基板的上方形成纳米晶。此外,方法还可以包括在形成第二绝缘层的步骤之前于第一绝缘层上方形成第四绝缘层以及在形成第三绝缘层的步骤之前去除第一区域及第三区域上方的纳米晶。此外,方法还可以包括在形成第二绝缘层的步骤之前去除第二区域上方的第一及第四绝缘层。此外,方法还包括在去除第二区域上方的第一及第四层的步骤之后以及在形成第三绝缘层的步骤之前去除第三区域上方的第一及第四绝缘层。作为选择,方法的特征还可以在于形成第四绝缘层的步骤包括对第一层进行脱耦等离子体氮化的步骤。另外,方法的特征还可以在于形成第四绝缘层的步骤,其特征还在于第四绝缘层包含富氮氧化物。另外,方法的特征还可以在于形成第四绝缘层的步骤,其特征还在于第四绝缘层的厚度不超过10埃。另外,方法的特征还可以在于形成第四绝缘层的步骤,其特征还在于第四绝缘层具有不超过10原子百分比的氮浓度。另外,方法的特征还可以在于去除纳米晶的步骤包含使用氢氟酸进行湿法蚀刻。另外,方法的特征还可以在于形成第一绝缘层的步骤包含在半导体基板上生长氧化物。另外,一方面,方法还可以包括在形成第二绝缘层的步骤之后于半导体基板上形成用作I/O晶体管的栅极电介质的第五绝缘层。
[0023]从另一个角度来看,有在半导体基板上制造半导体器件的方法。第一氧化物层生长在半导体基板上。在第一氧化物层上进行等离子体氮化以在第一氧化物层上形成富氮氧化物层。第一氧化物层及富氮层被选择性地去除以留下在基板的第一氧化区域上方的第一氧化物层及富氮氧化物层以及去除基板的第二区域上方的第一氧化物层及富氮氧化物层。第二氧化物层生长在第二区域上。纳米晶层在生长第二氧化物层的步骤之后被形成于半导体基板的上方。去除基板的第一区域及第三区域上方的纳米晶层。在去除纳米晶层的步骤之后,选择性地去除第一氧化物层及富氮氧化物层以留下基板的第一区域上方的第一氧化物层及富氮氧化物层以及去除基板的第三区域上方的第一氧化物层及富氮氧化物层。第三氧化物层生长在第三区域上。第一种类型的第一晶体管被形成于第一区域之中及之上,使用第一氧化物层及富氮氧化物层作为该第一晶体管的栅极电介质。第二种类型的第二晶体管被形成于第二区域之中及之上,使用第二氧化物层作为该第二晶体管的栅极电介质。第三种类型的第三晶体管被形成于第三区域之中及之上,使用第三氧化物层作为该第三晶体管的栅极电介质。方法的特征还可以在于生长第一氧化物层的步骤,其特征还在于第一氧化物层具有第一厚度,生长第二氧化物层的步骤,其特征还在于第二氧化物层具有小于第一厚度的第二厚度,以及生长第三氧化物层的步骤,其特征还在于第三氧化物层具有小于第二厚度的第三厚度。同样,方法的特征还可以在于形成第一晶体管的步骤,其特征还在于第一晶体管是高压晶体管,形成第二晶体管的步骤,其特征还在于第二晶体管是非易失性存储器晶体管,以及形成第三晶体管的步骤,其特征还在于第三晶体管是逻辑晶体管。同样,方法的特征还可以在于去除纳米晶层的步骤还包括去除基板的第四区域上方的纳米晶层,以及方法还可以包含在去除纳米晶的步骤之后选择性地去除第一氧化物层及富氮氧化物层,以留下基板的第一区域上方的第一氧化物层及富氮氧化物层以及去除基板的第四区域上方的第一氧化物层及富氮氧化物层,在第四区域上方生长第四氧化物层,以及在第四区域之中及之上形成第四种类型的第四晶体管,使用第四氧化物层作为该第四晶体管的栅极电介质。同样,方法的特征还可以在于进行脱耦等离子体氮化的步骤,其特征还在于富氮氧化物层的厚度不大于10埃。同样,方法的特征还可以在于进行脱耦等离子体氮化的步骤,其特征还在于富氮氧化物层具有不超过10原子百分比的氮浓度。
[0024]从另一个角度来看,半导体器件包括高压晶体管、非易失性存储器晶体管、逻辑晶体管。高压晶体管具有包含氧化物层及富氮氧化物层的栅极电介质,其中富氮氧化物层不大于10埃厚并且具有没有超过10原子百分百的氮浓度;其中氧化物层具有第一厚度。非易失性存储器晶体管具有小于第一厚度的第二厚度的栅极电介质。逻辑晶体管具有小于第二厚度的第三厚度的栅极电介质。此外,半导体器件可以还包括具有大于第三厚度且小于第一厚度的第四厚度的栅极电介质的I/O晶体管。