English:
[0002] A digital-to-analog converter (DAC) is a device for converting a digital (usually binary) code to an analog signal such as a current, voltage or an electric charge. DACs are widely used components of various electronic systems, such as telephone and other communications systems, radio transceiver systems, audio systems, image processing systems, and the like.
[0003] Many DACs are fabricated in an integrated circuit, where variations in semiconductor manufacturing processes can affect the performance of the DAC. For example, over the entire range of digital codes that can be input into the DAC, a step from one code to the next code in one portion or region of the input codes can produce a different output step size in the analog signal due to nonlinearities introduced in the manufacturing process, or due to differences in circuit architecture used to produce an output signal in one code region compared to another. Some DACs may use some circuits to output a signal with a smaller amplitude, and may use other circuits to output signals with larger amplitudes.
[0004] Because nonlinearities or other anomolies can be present in DACs, and because such issues can cause problems in the application and use of the analog outputs signals, there is a need for calibration systems and techniques that can improve upon the accuracy and linearity of the output signals of the DAC.
[0005] The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
[0006] FIG. 1 is a high-level block diagram of a digital-to-analog converter having a calibration system in accordance with one or more embodiments;
[0008] FIG. 3 is a flowchart of a process of calibrating a digital-to-analog converter in accordance with one or more embodiments.
[0009] Referring to FIG. 1 , a high-level diagram of portions of a digital-to-analog converter (DAC) having a calibration system in accordance with one or more embodiments will be briefly discussed and described. As shown, digital-to-analog converter 100 includes main DAC 102, which receives a digital value or digital code at DAC input 104, and outputs an analog signal (e.g., a current, a voltage, or an electric charge) at DAC output 106 in response to the digital code at the input. Main DAC 102 is the primary digital-to-analog converter.
[0010] CAL DAC (calibration digital-to-analog converter) 108 is a secondary or auxiliary DAC that provides an output signal at CAL DAC output 1 10 that can be used to correct, adjust, or calibrate the output of main DAC 102 in response to a digital value or digital code at CAL DAC input 1 12. Thus, CAL DAC output 110 is coupled to DAC output 106 so that it can adjust the DAC output 106 to compensate for errors, including any nonlinearities in step size, in the operation of main DAC 102.
[0011] CAL DAC input 112 is coupled to look up table 1 14. Look up table 1 14 outputs a compensation value (e.g., a digital code) at look up table output 1 16. The compensation value is selected by the digital code received at look up table input 1 18, which can be the same digital code that is input into DAC input 104. Thus, the value at look up table input 118 acts as an index (i.e., a value corresponding to an address of a memory location in the lookup table that contains a corresponding value) pointing to a compensation value, which is recalled and output at look up table output 1 16.
[0012] As illustrated in the embodiment of FIG. 1 , DAC input 104 and look up table input 118 receive a digital code having 14 bits. Look up table output 112 outputs a compensation value having 9 bits. This means that there can be 512 compensation values stored in 16 locations in look up table 1 14, which corresponds to one compensation value for every group of 1024 14-bit input codes. These groups of input codes can be referred to as code regions.
[0013] Look up table 114 can also receive compensation values for storing in look up table memory from calibration input 120. Calibration input 120 is coupled to calibration system 122. Calibration system 122 calibrates DAC 100 (wherein the output of DAC 100 is the combined outputs of main DAC 102 and CAL DAC 108) by selectively providing a waveform sequence of digital codes to DAC input 104 and analyzing the output of main DAC 102 as it is adjusted by the output of CAL DAC 108, and determining calibration values that will be stored in lookup table 1 14 for use in normal operation of DAC 100.
[0014] Calibration system 122 can be implemented together with the main DAC 102 and CAL DAC 108 or as a separate system or integrated circuit. The calibration performed by the calibration system 122 could be performed during the manufacturing process for the DAC or upon system initialization, etc. Calibration system 122 in various embodiments includes a calibration controller 124 for performing and controlling the calibration process. Calibration controller 124 can be implemented using hardware, or software, or combination of both. Calibration controller 124 can be a separate processing system, or it can be a function or a functional module implemented as part of a larger system or control module. Calibration controller 124 can execute steps and control processes that provide signals and take measurements that are needed to calibrate DAC 100.
[0015] Calibration controller 124 can be coupled to memory 126, which provides storage for data 128 and program code 130 (e.g., software, microcode, firmware, or the like) that is used in the process of calibrating DAC 100.
[0016] Calibration controller 124 can also be coupled to and configured to control waveform generator 132. Various approaches for providing waveform generators are generally known in the art. For example, in one embodiment, a pre-calculated waveform sequence can be repeatedly recalled from memory. In another embodiment, the waveform sequence can be mathematically produced. In the particular embodiment, waveform generator 132 can be used for outputting a waveform sequence having a particular zero offset and peak amplitude. In one embodiment, the waveform is a periodic sequence of digital codes that represents a sine wave. The zero offset of the waveform can be defined as the average value of the waveform. The peak amplitude of the waveform can be defined as the highest value above the zero offset.
[0017] The output of waveform generator 132 can be selectively coupled to DAC input 104 by switch 134, which can be switched by calibration enable signal 136. When calibration enable signal 136 is active, switch 134 switches from data input 138 to the output of waveform generator 132 to prepare for calibration. Calibration enable signal 136 can also be coupled to calibration controller 124 for controlling or initiating the calibration process. Calibration of the DAC can be initiated on an as needed basis (e.g., upon power up, or periodically, or from time to time) by a control function within the equipment using DAC 100.
[0018] Calibration controller 124 can also receive feedback data from filter output 140 of filter 142. Filter input 144 of filter 142 can be coupled to ADC (analog-to-digital converter) output 146 of ADC 148 for receiving digital codes or values that represent the output of the combination of main DAC 102 and CAL DAC 108. ADC input 150 is coupled to the combined outputs of main DAC 102 (i.e., main DAC output 106) and CAL DAC 108 (i.e., CAL DAC output 1 10). In the illustrated embodiment, ADC output 146 includes sixteen bits of digital information that represents the analog signal input at ADC input 150. As shown in FIG. 1 , ADC output 146 can include sixteen bits of digital information that represents the analog signal input at ADC input 150. This sixteen-bit resolution exceeds the fourteen bits of information input into main DAC 102. This increased resolution allows more precise measurement of the output of DAC 100 such that the CAL DAC performance can be measured by the ADC.
[0019] In one embodiment, filter 142 can be implemented with a filter that passes a harmonic of the waveform sequence output by waveform generator 132. More particularly, filter 142 can be a digital filter that measures the amplitude of a third harmonic of a waveform sequence from waveform generator 132. Filter 142 can be implemented using digital signal processing techniques and algorithms for filtering and analyzing spectral components of a waveform. Such techniques can include fast Fourier transform (FFT) signal processing techniques, which can be used to selectively isolate signal levels of harmonic components of an input signal.
[0020] Referring to FIG. 2, there is depicted a schematic representation of code regions of a DAC, such as DAC 102 in FIG. 1 , in accordance with one or more embodiments. A DAC is designed to receive a range of digital codes (e.g., such as binary values "0000, 0001 , ... 11 10, 1 11 1") that will be converted into an analog signal. The entire range of digital codes that can be input into main DAC 102 is represented by 200. For example, if 14 digital bits of information comprise the digital input code, the input range is from 0 to 16,383 (represented as fourteen-bit binary numbers).
[0021] For the purpose of more accurately calibrating the output of main DAC 102 a plurality of calibration values can be assigned or mapped to a plurality of code regions (e.g., a plurality of ranges of code values selected from the entire range of digital code input values). As shown in FIG. 2, the entire range of digital input codes 200 has been separated or divided into, for example, 8 code regions, which are shown by "code region 1 " through "code region 8." If the range of 16,384 input codes (e.g., a fourteen-bit input code) is divided into eight equally spaced regions, each region would include 2048 input codes. Regions do not need to be equally spaced, and different sized regions can be used if appropriate, e.g., if finer accuracy is desired in a particular area of the DAC range.
[0022] FIG. 2 shows that code regions 1 through 8 are separated by code boundaries, which are represented at 202, 204, 206, 208, 210, 212, and 214. Thus, for eight code regions there are seven code boundaries, wherein each code boundary separates two adjacent code regions.
[0023] FIG. 2 also shows graphical representations of waveform sequences (e.g., provided by waveform generator 132) that can be used in calibrating DAC 100. In one embodiment, such waveform sequences represent sine waves having selected zero offsets and amplitudes. For example, one waveform sequence used during calibration can be a sequence of digital codes selected to produce sine wave 216, which has a zero offset 218 located at boundary 202 between code region 1 and code region 2. The waveform sequence represented by sine wave 216 is comprised of digital codes having a range from the higher value shown at 220 to the lower value at 222.
[0024] The waveform sequence associated with sine wave 216 can be used to determine relative compensation values associated with boundary 202 between code region 1 and code region 2. The relative compensation value indicates a difference between the compensation values of adjacent code regions, which code regions can be referred to as a first code region and a second code region that are separated by a boundary. Additional waveform sequences can be used to determine relative compensation values associated with other code regions. For example, waveform sequences associated with sign waves 226 and 228 can be used to determine relative compensation values associated with code region boundary 204 and code region boundary 206, respectively.
[0025] Referring to FIG. 3, there is depicted a high-level flowchart of processes that can be executed by DAC 100 for calibrating the DAC in accordance with the one or more embodiments. As shown, process 300 begins at 302, and thereafter passes to 304 wherein the process initializes system parameters. System parameters that can be initialized include: e.g., setting the DAC resolution, determining the number of code regions and corresponding boundaries, initializing counters, and the like. In the embodiment shown in FIG. 1 , DAC 100 has a fourteen bit resolution. In one embodiment, sixteen code regions can be used in DAC 100. Other embodiments can use a different number of code regions, such as, for example, the eight code regions that are shown in FIG. 2.
[0026] Next, the process selects a boundary between a first and a second code region, as shown at 306. In one embodiment, the first and second code regions can be any two of the plurality of code regions that are adjacent and separated by a single boundary. For example, in FIG. 2, code regions 1 and 2 can be initially selected as the first and second code regions, wherein boundary 202 separates the two selected regions.
[0027] After selecting the boundary between the first and second code regions, the process determines a compensation value for the first code region, as illustrated at 308. In a first pass through the flowchart, the first code region can be assumed to have a compensation value of zero. In a second and subsequent passes through the flowchart, the first code region can be set to have a compensation value determined in a previous pass.
[0028] Next, the process inputs a waveform sequence having a zero offset at the selected boundary (i.e., the waveform has an average or DC value substantially equal to the value corresponding to the selected boundary), as shown at 310. The waveform sequence can be a sequence of digital codes that represent a periodic waveform having a zero offset at a digital code substantially equal to a code closest to the selected boundary. The zero offset can be substantially equal to an average value of the waveform sequence averaged over one or more periods of the waveform sequence. In one embodiment, the waveform sequence can represent a sine wave, such as sine wave 216 in FIG. 2, which has a zero offset 218 at boundary 202. Other embodiments can use other periodic waveforms that have a fundamental frequency.
[0029] In one embodiment, the peak amplitude of the waveform sequence (see 230 in FIG. 2) is substantially equal to a range of values in the smaller of the selected first or second code regions. Thus, the waveform sequence includes code values that remain within the values encompassed by the selected first and second code regions, which means that, in one embodiment, the waveform sequence crosses only one boundary, remaining between the two boundaries on either side of the selected boundary. For example, if the selected boundary is 204, the waveform sequence 226 remains within boundaries 202 and 206.
[0030] After inputting the waveform sequence and the compensation value for the first code region, the process determines a compensation value for the second code region that reduces the output distortion of the DAC, as depicted at 312. To minimize the output distortion, the process can vary or adjust the compensation value of the second code region (e.g., the corresponding compensation value stored in look up table 114) relative to the first code region and search for a minimum level of output distortion. Calibration controller 124 can write various compensation values into memory locations corresponding to code regions in look up table 114 by writing data to calibration input 120. In one embodiment, the search for a minimum level of output distortion can use a sweep of a range of compensation values that are temporarily stored in look up table 114, wherein following the sweep a compensation value corresponding to a minimum distortion is selected. In other embodiments, another suitable algorithm can be used, such as a least mean square (LMS) search algorithm. Note that at 312 the process determines a relative compensation value (e.g., a difference in the compensation values) between the first and second code regions. The compensation value for a code region (e.g., the second code region) is not determined independently of the value of another code region (e.g., the first code region). The distortion in the output is a function of the difference in the compensation values of code regions on either side of the boundary.
[0031] In one embodiment, the output distortion reduced at 312 is a magnitude of a third harmonic of the waveform sequence input at 310. In other embodiments, other distortion metrics can be measured and minimized. For example, some embodiments may examine a second harmonic of the input waveform sequence.
[0032] In one embodiment, the output distortion is measured by converting the output signal (e.g., DAC output 106) back to a digital signal using ADC 148. ADC output 146 can then be filtered by filter 142 in order to isolate any distortion in the signal. In one embodiment, filter 142 can include an FFT, which can efficiently separate the output signal into its frequency components for further analysis. For example, a magnitude of a third harmonic can be determined from the output of such an FFT.
[0033] After finding the compensation value for the second code region (and finding the relative compensation value between the first and second code regions), the process determines whether there are additional boundaries to be analyzed, as illustrated at 314. For example, in a first pass through the adjustments at 312 a relative compensation between code region 1 and code region 2 is determined using a waveform sequence having a zero offset at boundary 202. At 314, the process determines whether code regions on either side of all boundaries 202, 204, 206, 208, 210, 212, and 214 have been analyzed. If there are additional code boundaries that have not been analyzed, the process selects a new code boundary, as shown at 316, and iteratively returns to 308 to set a compensation value for the first code region and input a new waveform sequence having a zero offset at the newly selected boundary. If the second pass selects boundary 204, the first code region can be code region 2, and the compensation value for the first code region (e.g., now set to code region 2) can be set to the value previously determined in the first pass at 312.
[0034] If all boundaries have been analyzed, the process calculates compensation values for each code region, wherein the compensation values maintain the differences or relative compensation values across each boundary, where such relative compensation values were determined at 312 for each boundary. For example, in one embodiment, code region 1 may have a compensation value of "0" and code region 2 may have a compensation value of "4," which makes the relative compensation value between these two regions equal to "4." In an analysis (312) at boundary 204 it may be determined that the relative compensation value is "6". In this case, the compensation value of code region 3 can be set to "10," which is a value calculated (e.g. 4 + 6) to maintain the relative compensation values across boundaries 202 and 204. The compensation values stored in look up tablei 14 for each code region will include a base value, e.g., a DC compensation value or the like, with the relative compensation values added thereto. For instance, if the base value is 100, in this example, respective regions 1-3 would have compensation values of 100, 104, 110 stored in the look up table.
[0035] The process illustrated in FIG. 3 can be implemented in the DAC of FIG. 1 or other suitably configured DAC systems with appropriate capabilities. The process can be repeated as needed or desired.
[0036] Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, while the techniques and apparatus for calibrating a DAC may vary widely, one or more embodiments can be used in a wireless communications system having a digital baseband signal processor and an analog transmitter. The inventive concepts and principles taught herein can also be applied to other wireline or wireless communications systems, and other systems that process digital and analog signals. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
[0037] Unless stated otherwise, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

中文:
[0002]数字模拟转换器(DAC)是用于将数字(通常是二进制)码转换成诸如电流、电压或电荷这样的模拟信号的一种设备。DAC是各种电子系统中广泛使用的组件,例如电话和其他通信系统、无线电收发信机系统、音频系统、图像处理系统等等。
[0003]许多DAC被制作在集成电路中,其中半导体制造工艺的变化可能影响DAC的性能。例如,在可以被输入到DAC中的数字码的整个范围内,在输入码的一个部分或区域中从一个码到下一个码的量化阶(step)可能由于在制造过程中引入的非线性或者由于相比另一个码区域在一个码区域中用来产生输出信号的电路结构的不同,而在模拟信号中产生不同的输出量化阶大小。某些DAC可以使用一些电路来输出具有较小振幅的信号,并且可以使用其他电路来输出具有较大振幅的信号。
[0004]因为在DAC中可能存在非线性和其他异常,并且由于这些问题会在模拟输出信号的应用和使用中产生问题,因此,需要可以提高DAC输出信号的准确性和线性的校准系统和技术。
[0005]本发明是通过示例的方式来描述的,并且被附图所限制,在附图中,相同的附图标记表示相同的元件。出于简单和清楚的目的描述图中的元件,并且不必按照比例来绘制这些元件。
[0006]图1是根据一个或多个实施例的具有校准系统的数字模拟转换器的高层框图;
[0008]图3是根据一个或多个实施例的校准数字模拟转换器的过程的流程图。
[0009]参考图1,将简要讨论和描述根据一个或多个实施例的具有校准系统的数字模拟转换器(DAC)的部分的高层示图。如图所示,数字模拟转换器100包括主DAC102,其在DAC输入104处接收数字值或数字码,并且响应于输入处的数字码而在DAC输出106处输出模拟信号(例如,电流、电压或电荷)。主DAC102是主要的数字模拟转换器。
[0010]CAL DAC(校准数字模拟转换器)108是次级或辅助DAC,其响应于CAL DAC输入112处的数字值或数字码在CAL DAC输出110处提供输出信号,该输出信号可以被用来校正、调整或校准主DAC102的输出。因此,CAL DAC输出110耦合到DAC输出106,以便其能够调整DAC的输出106来补偿主DAC102的操作中的错误,包括量化阶大小中的任何非线性。
[0011]CAL DAC输入112耦合到查找表114。查找表114在查找表输出116处输出补偿值(例如,数字码)。由在查找表输入118处接收到的数字码来选择该补偿值,该数字码可以与输入到DAC输入104中的数字码相同。因此,在查找表输入118处的值用作指向补偿值的索引(即,与包含对应值的查找表中的存储器位置的地址对应的值),该补偿值在查找表输出116处被取回和输出。
[0012]如图1的实施例所说明的,DAC输入104和查找表输入118接收具有14比特的数字码。查找表输出112输出具有9比特的补偿值。这意味着可以有512个补偿值存储在查找表114的16个位置中,这与针对具有1024个14比特输入码的每个组的一个补偿值对应。输入码的这些组可以被称为码区域。
[0013]查找表114也可以从校准输入120接收补偿值,用于存储在查找表存储器中。校准输入120耦合到校准系统122。校准系统122通过以下方式对DAC100进行校准(其中DAC100的输出是主DAC102和CAL DAC108的组合输出):通过选择性地向DAC输入104提供数字码的波形序列并且在主DAC102被CAL DAC108的输出调整时,分析主DAC102的输出以及确定将存储于查找表114中用于DAC100正常操作的校准值。
[0014]校准系统122可以与主DAC102和CAL DAC108实现在一起,或者可以被实现为单独的系统或集成电路。可以在DAC的制造过程中或者可以在系统初始化时等,执行由校准系统122执行的校准。各种实施例中的校准系统122包括用于执行和控制校准过程的校准控制器124。可以使用硬件、或软件或者两者的组合来实现校准控制器124。校准控制器124可以是单独的处理系统,或者其可以是被实现为较大系统或控制模块的一部分的功能或功能模块。校准控制器124能够执行提供信号并且进行校准DAC100所需要的测量的步骤和控制过程。
[0015]校准控制器124可以耦合到存储器126,存储器126为数据128和程序代码130(例如,软件、微码、固件等)提供存储,在校准DAC100的过程中使用该数据128和程序代码130。
[0016]校准控制器124也可以耦合到波形生成器132并且被配置用于控制波形生成器132。用于提供波形生成器的各种方法在现有技术中是公知的。例如,在一个实施例中,预计算的波形序列可以从存储器中重复地被调用。在另一个实施例中,可以算术地产生波形序列。在特定实施例中,波形生成器132可以被用来输出具有特定零偏移和峰值振幅的波形序列。在一个实施例中,波形是呈现正弦波的数字码的周期序列。波形的零偏移可以被定义为波形的平均值。波形的峰值振幅可以被定义为高于零偏移的最高值。
[0017]可以通过开关134将波形生成器132的输出选择性地耦合到DAC输入104,开关134可以由校准启用信号136来切换。当校准启用信号136激活时,开关134从数据输入138切换到波形生成器132的输出以准备校准。校准启用信号136也可以耦合到校准控制器124用于控制或初始化校准过程。使用DAC100的设备内部的控制功能可以在需要的基础上(例如,在接通电源时、周期性地或者是间或)来开始DAC的校准。
[0018]校准控制器124也可以接收来自滤波器142的滤波器输出140的反馈数据。滤波器142的滤波器输入144可以耦合到ADC148的ADC(模拟数字转换器)输出146,用于接收表示主DAC102和CALDAC108的组合的输出的数字码或值。ADC输入150耦合到主DAC102(即,主DAC输出106)和CAL DAC108(即,CAL DAC输出110)的组合输出。在所说明的实施例中,ADC输出146包括16比特的数字信息,其表示在ADC输入150处的模拟信号输入。如图1所示,ADC输出146可以包括16比特的数字信息,其表示在ADC输入150处的模拟信号输入。该16比特的分辨率超过了输入到主DAC102的14比特的信息。该增加的分辨率允许对DAC100的输出更精确的测量以便ADC可以测量CAL DAC性能。
[0019]在一个实施例中,可以利用使波形生成器132输出的波形序列的谐波通过的滤波器来实现滤波器142。更具体地,滤波器142可以是测量来自波形生成器132的波形序列的第三谐波的振幅的数字滤波器。可以使用用于对波形的频谱分量进行滤波和分析的数字信号处理技术和算法来实现滤波器142。这些技术可以包括快速傅立叶变换(FFT)信号处理技术,该技术可以被用于选择性地隔离输入信号的谐波分量的信号电平。
[0020]参考图2,描述了根据一个或多个实施例的诸如图1中的DAC102的DAC的码区域的示意性表示。DAC被设计用来接收将被转换成模拟信号的某一范围的数字码(例如,诸如二进制值“0000、0001、...1110、1111”)。可被输入到主DAC102中的整个范围的数字码由200表示。例如,如果14个数字比特的信息包括数字输入码,那么输入范围是从0到16,383(被表示为14比特的二进制数)。
[0021]出于对主DAC102的输出进行更精确的校准的目的,可以将多个校准值指配或映射到多个码区域(例如,从数字码输入值的整个范围中选择的多个码值范围)。如图2所示,数字输入码200的整个范围已被分隔或划分成,例如,8个码区域,其由“码区域1”至“码区域8”来示出。如果16,384个输入码的范围(例如,14比特输入码)被划分成8个等间隔的区域,则每个区域将包括2048个输入码。区域并不需要是等间隔的,并且如果合适,可以使用不同大小的区域,例如,如果在DAC范围的特定区域内需要更精细的精确度。
[0022]图2示出了码区域1到8是由码边界分隔的,这些码边界被表示为202、204、206、208、210、212和214。因此,对于8个码区域,存在7个码边界,其中每个码边界分隔两个相邻的码区域。
[0023]图2也示出了可用于校准DAC100的波形序列(例如,由波形生成器132所提供)的图形表示。在一个实施例中,该波形序列表示具有选定的零偏移和振幅的正弦波。例如,在校准期间所使用的一个波形序列可以是被选择用于产生正弦波216的数字码序列,其在位于码区域1和码区域2之间的边界202处具有零偏移218。由正弦波216所表示的波形序列由具有从220处所示的较高值到222处所示的较低值的范围的数字码组成。
[0024]与正弦波216相关联的波形序列可以被用来确定与码区域1和码区域2之间的边界202相关联的相对补偿值。相对补偿值指示相邻码区域的补偿值之间的差,该码区域可以被称为由边界分隔的第一码区域和第二码区域。附加的波形序列可以被用来确定与其他码区域相关联的相对补偿值。例如,与正弦波226和228相关联的波形序列可以被用来确定分别与码区域边界204和码区域边界206相关联的相对补偿值。
[0025]参考图3,描述了根据一个或多个实施例的可以由DAC100执行的用于校准DAC的过程的高层流程图。如图所示,过程300开始于302,并且其后进行到304,在304中该过程初始化系统参数。可以被初始化的系统参数包括:例如,设置DAC分辨率、确定码区域和对应边界的数目、初始化计数器等等。在如图1所示的实施例中,DAC100具有14比特的分辨率。在一个实施例中,16个码区域可以被用在DAC100中。其他实施例可以使用不同数目的码区域,诸如,例如图2中所示的8个码区域。
[0026]接下来,如306所示的,该过程选择第一和第二码区域之间的边界。在一个实施例中,第一和第二码区域可以是相邻的并且由单个边界分隔的多个码区域中的任意两个。例如,在图2中,码区域1和2最初可被选择为第一和第二码区域,其中边界202将这两个选定的区域分隔。
[0027]在选择了第一和第二码区域之间的边界后,如308所示,该过程确定第一码区域的补偿值。在第一次通过流程图时,第一码区域可以被假定具有为零的补偿值。在第二次以及接下来通过流程图时,第一码区域可以被设定为具有在前一次通过中确定的补偿值。
[0028]接下来,如310所示,该过程输入在选定边界处具有零偏移的波形序列(即,该波形具有与对应于选定边界的值基本相等的平均或DC值)。该波形序列可以是表示周期波形的数字码序列,其在与选定边界最接近的码基本相等的数字码处具有零偏移。该零偏移可以与在波形序列的一个或多个周期内平均的波形序列的平均值基本相等。在一个实施例中,波形序列可以表示正弦波,诸如图2中所示的正弦波216,其在边界202处具有零偏移218。其它实施例可以使用具有基本频率的其他周期波形。
[0029]在一个实施例中,波形序列的峰值振幅(参见图2中的230)与选定的第一或第二码区域中较小的那个的值的范围基本相等。因此,该波形序列包括保持在由选定的第一和第二码区域所包括的值之内的码值,这意味着,在一个实施例中,波形序列只穿过一个边界,保持在选定边界两侧的两个边界之间。例如,如果选定边界为204,则波形序列226保持在边界202和206之间。
[0030]在输入波形序列和第一码区域的补偿值后,如312所示,该过程为第二码区域确定补偿值,其减少DAC的输出失真。为了最小化输出失真,该过程可以相对于第一码区域改变或调整第二码区域的补偿值(例如,存储在查找表114中的对应的补偿值),并且搜索输出失真的最小水平。通过向校正输入120写数据,校正控制器124可以将不同的补偿值写入与查找表114中的码区域对应的存储器位置中。在一个实施例中,搜索输出失真的最小水平可以使用对暂时存储在查找表114中的某一范围的补偿值的扫描,其中,在扫描后,选择对应于最小失真的补偿值。在其他实施例中,可以使用其它合适的算法,例如最小均方(LMS)搜索算法。注意到在312,该过程确定了在第一和第二码区域之间的相对补偿值(例如,补偿值中的差)。码区域(例如,第二码区域)的补偿值并不独立于另一个码区域(例如,第一码区域)的值而被确定。输出中的失真是边界两侧的码区域的补偿值中的差的函数。
[0031]在一个实施例中,在312减少的输出失真是在310输入的波形序列的第三谐波幅度。在其它实施例中,其它失真度量可以被测量和最小化。例如,一些实施例可以检查输入波形序列的第二谐波。
[0032]在一个实施例中,可以通过使用ADC 148将输出信号(例如,DAC输出106)转换回数字信号来测量输出失真。为了隔离信号中的任何失真,可以由滤波器142来对ADC输出146进行滤波。在一个实施例中,滤波器142可以包括FFT,其可以有效地将输出信号分隔成其频率分量用于进一步的分析。例如,可以通过这种FFT的输出来确定第三谐波的幅度。
[0033]在找到第二码区域的补偿值(并且找到第一和第二码区域之间的相对补偿值)之后,该过程确定是否存在要被分析的其它边界,如314所示。例如,在第一次通过调整时在312,使用在边界202处具有零偏移的波形序列来确定码区域1和码区域2之间的相对补偿。在314,该过程确定所有边界202、204、206、208、210、212和214两侧的码区域是否已被分析。如果存在还未被分析的其它码边界,则该过程选择新的码边界,如316所示,并且迭代地返回308来为第一码区域设置补偿值,并且输入新的波形序列,该波形序列在新选定的边界处具有零偏移。如果第二次通过选择边界204,则第一码区域可以是码区域2,并且第一码区域的补偿值(例如,现在被设置为码区域2)可以被设置为先前在312中在第一次通过中确定的值。
[0034]如果已分析了所有边界,则该过程计算每个码区域的补偿值,其中该补偿值维持跨每个边界的差或相对补偿值,其中该相对补偿值是在312针对每个边界确定的。例如,在一个实施例中,码区域1可以具有补偿值“0”,并且码区域2可以具有补偿值“4”,这使得这两个码区域之间的相对补偿值等于“4”。在边界204处的分析(312)中,可以确定相对补偿值是“6”。在这种情况下,码区域3的补偿值可以被设置为“10”,这个值是被计算用来维持跨边界202和204的相对补偿值(例如4+6)的值。每个码区域的查找表114中所存储的补偿值将包括基础值,例如DC补偿值等,具有添加于其上的相对补偿值。例如,如果基础值是100,在这个示例中,相应区域1-3会具有存储在查找表中的补偿值100、104、110。
[0035]可以在图1的DAC或具有适当能力的其它适当配置的DAC系统中实现图3中所描述的过程。该过程可以根据需要或期望重复。
[0036]尽管参照特定的实施例对本发明进行了描述,但是在不脱离所附权利要求所阐述的本发明的范围的前提下可以进行各种修改和改变。例如,虽然用于校正DAC的技术和装置可能变化很大,但一个或多个实施例可以用于具有数字基带信号处理器和模拟发射机的无线通信系统中。在这里教导的发明概念和原理也可以被应用于其他有线或无线通信系统,以及处理数字和模拟信号的其他系统。因此,本说明书和附图被看作是说明性的而不是限制性的,并且所有这样的修改都将被包括在本发明的范围之内。这里参考特定的实施例所描述的任何益处、优点以及对问题的解决方案不被解释为任何或者所有权利要求的关键的、必要的或者本质的特征或要素。
[0037]除非另行声明,诸如“第一”和“第二”的术语被用来在其所描述的元件之间进行任意区分。因此,这些术语不必一定意指这些元件的时间或其他优先顺序。