English:
[0001] This disclosure relates generally to memories, and more specifically, to memories having a low voltage data path.
[0002] As feature sizes continue to shrink, the requirement for lower voltage operation also continues. The lower voltage is beneficial in requiring less power but it is also necessary because the transistors with reduced feature sizes can only withstand a limited voltage. This is a problem with regard to all portions of a device. Other things generally beneficial are speed of operation and power consumption. Thus, any changes needed for one constraint, such as power supply voltage, should not adversely impact speed and power consumption. Transistors with reduced feature sizes often have both of the those benefits which also makes the lower feature sizes more desirable. The circuits that implement them though should still not adversely impact the inherent improvement in speed and power consumption. This includes the output data path in a memory.
[0003] Thus, there is a need for a memory data path that is operable at a lower voltage while taking into account speed and power consumption.
[0004] The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
[0005] FIG. 1 is a block diagram of an integrated circuit having a memory using an embodiment of the invention; and
[0006] FIG. 2 is a combination block and circuit diagram showing a portion of a data path of FIG. 1 in more detail.
[0007] A data path of a memory is from an array of the memory, through a sense amplifier, through NOR gates, through N channel transistors, and through a latch that provides an output. The sense amplifier provides complementary data to the NOR gates which provide an output to the N channel transistors. The NOR gates provide outputs to the latch. This has the affect of providing outputs to gates of one inverter and drains of another inverter. Additional P channel transistors are in series with the inverters of the latch. The P channel transistor that is in series with the inverters whose drains are receiving the signal is made to be nonconductive by the output of the NOR gate to block current flow to the N channel transistor that is providing the input to the latch. The blocking of the current reduces the amount of current that the N channel transistor has to sink. This enables the N channel transistor, even at a reduced voltage, to be sufficiently conductive to flip the state of the latch. This is better understood by reference to the drawings and the specification.
[0008] Shown in FIG. 1 is a circuit 2 comprising a processor 4, other blocks 6, and a memory 8. Processor 4 further comprises an Ll cache 10 and an L2 cache 12. In this case caches 10 and 12 are memories useful in increasing the efficiency of processor 4. Processor 4 attempts to fetch from the Ll cache first then the L2 cache then memory 8. Processor 4 performs operations using these three memories as well as other blocks 6.
[0009] L2 cache 12 is shown in more detail in FIG. 2 as memory 12 which comprises an array portion 13, a special inverter 14, a special inverter 16, a NOR gate 18, an N channel transistor 20, a NOR gate 22, an N channel transistor 24, a NOR gate 26, an N channel transistor 28, a NOR gate 30, and an N channel transistor 32. Array portion 13 comprises an array 34, a sense amplifier 36, a memory array 38, and a sense amplifier 40. Array portion comprises additional memory arrays and sense amplifiers that are not individually identified. Special inverter 14 comprises an P channel transistor 46, an N channel transistor 48, a P channel transistor 42, and a P channel transistor 44. Special inverter 16 comprises an P channel transistor 56, an N channel transistor 58, a P channel transistor 52, and a P channel transistor 54. Special inverters 14 and 16 operate together as a latch. Sense amplifier 36 has a pair of complementary outputs Dl and DlB representative of a selected memory cell from memory array 34. Sense amplifier 36 may have other outputs representative of other memory cells going to other circuits. Sense amplifier 40 has a pair of complementary outputs D2 and
[0010] NOR gate 18 has a first input for receiving output DlB, a second input for receiving an enable signal ENBl, and an output. Signal ENBl is a signal that, when it is a logic low, allows NOR gate 18 to provide an output inverted from output DlB. NOR gate 22 has a first input for receiving output D2B, a second input for receiving an enable signal ENB2, and an output. Signal ENB2 is a signal that, when it is a logic low, allows NOR gate 22 to provide an output inverted from output D2B. NOR gate 26 has a first input for receiving output Dl, a second input for receiving enable signal ENBl, and an output. Signal ENBl is a signal that, when it is a logic low, allows NOR gate 26 to provide an output inverted from output Dl . NOR gate 30 has a first input for receiving output D2, a second input for receiving enable signal ENB2, and an output. Signal ENB2 is a signal that, when it is a logic low, allows NOR gate 30 to provide an output inverted from output D2. Transistor 20 has a gate connected to the output of NOR gate 18, a source connected to ground, and a drain. Transistor 24 has a gate connected to the output of NOR gate 22, a source connected to ground, and a drain. Transistor 28 has a gate connected to the output of NOR gate 26, a source connected to ground, and a drain. Transistor 32 has a gate connected to the output of NOR gate 30, a source connected to ground, and a drain. Transistor 42 has a source connected to a positive power supply terminal VDD, a gate connected to the output of NOR gate 26, and drain. Transistor 44 has a source connected to the drain of transistor 42, a gate connected to the output of NOR gate 30 and a drain. Transistor 46 has a source connected to the drain of transistor 44, a gate connected to the drains of transistors 20 and 24, and a drain. Transistor 48 has a drain connected to the drain of transistor 46, a gate connected to the gate of transistor 46, and a source connected to ground. Transistor 52 has a source connected to a positive power supply terminal VDD, a gate connected to the output of NOR gate 18, and drain. Transistor 54 has a source connected to the drain of transistor 52, a gate connected to the output of NOR gate 22 and a drain. Transistor 56 has a source connected to the drain of transistor 54, a gate connected to the drains of transistors 28, 32, 46, and 48, and a drain connected to the gates of transistors 46 and 48 and the drains of transistors 20 and 24. Transistor 58 has a drain connected to the drain of transistor 56, a gate connected to the gate of transistor 56, and a source connected to ground. The drains of transistors 46 and 48 provide an output OUT. The drains of transistors 56 and 58 provide an output OUTB which is complementary to output OUT. The order of transistors 42 and 44 can be reversed.
[0011] In operation, array portion 13 provides data from memory arrays 34 and 38 through sense amplifiers 36 and 40 as complementary signals when these signals are representing the logic state of a selected memory cell. This is often called the active cycle of the memory, in this case memory 12. When not in the active cycle, often called the precharge cycle, signals Dl, DlB, D2, and D2B are held to a logic high. Enable signal signals ENBl and ENB2 are also held to a logic high. This causes NOR gates 18, 22, 26, and 30 to provide logic low signals as outputs which causes transistors 42, 44, 52, and 54 to be conductive. With transistors 42, 44, 52, and 54 conductive, inverters 14 and 16 function as a latch to hold the last logic state provided as outputs OUT and OUTB. During an active cycle, one pair of NOR gates, either NOR gates 18 and 26 or NOR gates 22 and 30 will be enabled by enable signal ENBl or ENB2, respectively, by switching to a logic low. The logic low then allows the pair of NOR gates receiving the logic low to be responsive to their other input. For the example of sense amplifier 36 providing the data that is to be output, NOR gates 18 and 26 receive sensed data from sense amplifier 36. When there has been sufficient time for sense amplifier 36 to have performed its sensing function and provided valid data to NOR gates 18 and 26, enable signal ENBl is enabled to a logic low state so that NOR gates 18 and 26 respond to output signals Dl and DlB. For the example of output Dl being a logic high and thus DlB being a logic low, P channel transistor 52 is made to be non-conductive and transistor 20 is made to be conductive. The drain of transistor 20 is connected to the gates of transistors 46 and 48 to cause transistor 48 to be non-conductive and transistor 46 to be conductive. The drain of transistor 20, however, is also coupled to the drains of transistors 56 and 58 as a consequence of inverters 14 and 16 being connected to form a latch. Previously, for the case where the latch was providing a logic high for OUTB, transistor 56 would have been conductive and coupling VDD to the OUTB node. N channel transistor 20 becoming conductive would have been thus drawing current through transistor 56, making it more difficult to cause transistor 46 to become conductive. With a lower power supply voltage and thus a lower voltage as the logic high on the gate of transistor 20, transistor 20 would not have enough drive strength to overcome the current being supplied through transistor 56 to cause transistor 46 to flip states from non-conductive to sufficiently conductive to cause transistor 58 to become conductive. With output of NOR gate 18 coupled to transistor 52 causing transistor 52 to become non-conductive, the current path from VDD to transistor 56 is blocked, preventing current being supplied through transistor 56 to transistor 20. Without the extra current load through transistor 56, transistor 46 can be made conductive by transistor 20 even with reduced voltage drive on the gate of transistor 20. By ensuring the current path from VDD to transistor 56 is blocked, transistor 20 causes transistor 46 to be conductive more quickly thus increasing speed. Also, current is saved. Thus, there are benefits of speed, power consumption, and operability at reduced voltage.
[0012] In this example of output DlB being a logic low, output Dl is a logic high which keeps NOR gate 26 providing a logic low output so that transistor 28 is retained in a non- conductive state. Transistor 42 remains conductive with the output of NOR gate 26 remaining at a logic low. Similarly for NOR gates 22 and 30, enable signal ENB2 is a kept at a logic high as are outputs D2 and D2B which keep NOR gates 22 and 30 providing a logic low output. This keeps transistors 54 and 44 conductive. Analogous operation is provided for output signal Dl being a logic low and signal DlB being a logic high. In such case transistor 42 becomes non-conductive while P channel transistors 44, 52, and 54 remain conductive. Transistor 42 blocks the current path from VDD to transistor 46 and thus prevents transistor 46 from providing additional current that conductive transistor 28 has to sink. Thus transistor 28 can cause transistor 56 to become conductive which can in turn causes transistor 48 to become conductive. The same type of operation occurs for the case in which enable signal ENB2 is enabled. In such case NOR gates 22 and 30 are responsive to their inputs that receive signals D2 and D2B so that one of transistors 44 or 54 is made non- conductive. This allows the N channel pull down transistor, either transistor 24 or 32, to efficiently and reliably cause the corresponding P channel transistor 46 or 56, respectively, to become conductive.
[0013] By now it should be appreciated that a circuit useful for a data path in a memory has been described. The circuit includes a first sense amplifier providing a set of outputs, wherein the set includes a first true output and a first complementary output. The circuit further includes a first input coupled to the first true output. The circuit further includes a second input coupled to the first complementary output. The circuit further includes a first N-channel transistor including a gate connected to the first input. The circuit further includes a second N-channel transistor including a gate connected to the second input. The circuit further includes a pair of cross coupled inverters, wherein the pair includes a first inverter and a second inverter. The first inverter includes a first P-channel transistor and a third N- channel transistor, a gate of the first P-channel transistor and a gate of the third N-channel transistor are connected to a first node, a first current terminal of the first P-channel transistor and a first current terminal of the third N-channel transistor are connected to a second node. The second inverter includes a second P-channel transistor and a fourth N-channel transistor, a gate of the second P-channel transistor and a gate of the fourth N-channel transistor are connected to the second node, a first current terminal of the second P-channel transistor and a first current terminal of the fourth N-channel transistor are connected to the first node. The circuit further includes a third P-channel transistor including a gate connected to the first input. The circuit further includes a fourth P-channel transistor including a gate connected to the second input. The third P-channel transistor and the first P-channel transistor are stacked in series. The fourth P-channel transistor and the second P-channel transistor are stacked in series. The circuit may further comprise a second sense amplifier, third and fourth inputs, and fifth and sixth N and P channel transistors. The second sense amplifier provides a second set of outputs, wherein the second set includes a second true output and a second complementary output. The third input is coupled to the second true output. The fourth input is coupled to the second complementary output. The fifth N-channel transistor includes a gate connected to the third input. The sixth N-channel transistor includes a gate connected to the fourth input. The fifth P-channel transistor includes a gate connected to the third input. The sixth P-channel transistor includes a gate connected to the fourth input. The third P- channel transistor, the fifth P-channel transistor, and the first P-channel transistor are stacked in series. The fourth P-channel transistor, the sixth P-channel transistor, and the second P- channel transistor are stacked in series. The circuit may further comprise a first NOR gate and a second NOR gate. The first NOR gate including an output connected to the first input, the first NOR gate including an input coupled to the first true output. The second NOR gate including an output connected to the second input, the second NOR gate including an input coupled to the first complementary output. The first NOR gate may include an input connected to an enable signal line. The second NOR gate may include an input connected to the enable signal line. The first N-channel transistor may include a first current terminal connected to the second node. The second N-channel transistor includes a first current terminal connected to the first node. The circuit may further include a power supply terminal. The third P-channel transistor may be located in a transistor stack and be between the first P-channel transistor and the power supply terminal. The fourth P-channel transistor may be located in a transistor stack and be between the second P-channel transistor and the power supply terminal. The first P-channel transistor may include a second current terminal, the third P-channel transistor may include a first current terminal and a second current terminal; and the second current terminal of the first P-channel transistor may be connected to the first current terminal of the third P-channel transistor. The circuit may further comprise a memory array and the sense amplifier may be operably coupled the memory array for providing values at the first true output and the first complementary output that are indicative of a value stored in the memory array. The circuit may further comprise a cache in which the cache includes the memory array, the first sense amplifier, the first input, the second input, the first N-channel transistor, the second N-channel transistor, the pair of cross coupled inverters, the third P-channel transistor, and the fourth P-channel transistor. The circuit may further include a processor that includes the cache.
[0014] A circuit useful for a data path in a memory has also been described as follows. The circuit includes a first sense amplifier providing a first set of outputs, wherein the first set includes a first true output and a first complementary output. The circuit further includes a second sense amplifier providing a second set of outputs, wherein the second set includes a second true output and a second complementary output. The circuit further includes a latch circuit including a first input coupled to the first true output, a second input coupled to the first complementary output, a third input coupled to the second true output, and a fourth input coupled to the second complementary data. The latch includes a first N-channel transistor including a gate connected to the first input, a second N-channel transistor including a gate connected to the second input, a third N-channel transistor including a gate connected to the third input, a fourth N-channel transistor including a gate connected to the fourth input, and a pair of cross coupled inverters. The pair includes a first inverter and a second inverter. The first inverter includes a first P-channel transistor and a fifth N-channel transistor, a gate of the first P-channel transistor and a gate of the fifth N-channel transistor are connected to a first node, a first current terminal of the first P-channel transistor and a first current terminal of the fifth N-channel transistor are connected to a second node. The second inverter includes a second P-channel transistor and a sixth N-channel transistor, a gate of the second P-channel transistor and a gate of the sixth N-channel transistor are connected to the second node, a first current terminal of the second P-channel transistor and a first current terminal of the sixth N- channel transistor are connected to the first node. The circuit further includes a third P- channel transistor including a gate connected to the first input. The circuit further includes a fourth P-channel transistor including a gate connected to the third input. The circuit further includes a fifth P-channel transistor including a gate connected to the second input. The circuit further includes a sixth P-channel transistor including a gate connected to the fourth input. The third P-channel transistor, the fourth P-channel transistor, and the first P-channel transistor are stacked in series. The fifth P-channel transistor, the sixth P-channel transistor, and the second P-channel transistor are stacked in series. The circuit may further comprise first, second, third, and fourth NOR gates. The first NOR gate includes an output connected to the first input and an input coupled to the first true output. The second NOR gate includes an output connected to the second input and an input coupled to the first complementary output. The third NOR gate includes an output connected to the third input and an input coupled to the second true output. The fourth NOR gate includes an output connected to the fourth input and input coupled to the second complementary output. The first NOR gate may include an input connected to a first enable signal line, the second NOR gate may include an input connected to the first enable signal line, the third NOR gate may include an input connected to a second enable signal line, and the fourth NOR gate may include an input connected to the second enable signal line. The first N-channel transistor may include a first current terminal connected to the second node, the third N-channel transistor may include a first current terminal connected to the second node, the second N-channel transistor may include a first current terminal connected to the first node, and the fourth N-channel transistor may include a first current terminal connected to the first node. The circuit may further include a power supply in which the third P-channel transistor and the fourth P-channel transistor are located in a transistor stack and are between the first P-channel transistor and the power supply terminal and the fifth P-channel transistor and sixth P-channel transistor are located in a transistor stack and are between the second P-channel transistor and the power supply terminal. The circuit may be further characterized in that the first P-channel transistor includes a second current terminal, the third P-channel transistor includes a first current terminal and a second current terminal, the fourth P-channel transistor includes a first current terminal and a second current terminal, the second current terminal of the first P-channel transistor is connected to the first current terminal of the fourth P-channel transistor, and the second current terminal of the fourth P-channel transistor is connected to the first current terminal of the third P-channel transistor. The circuit may be further characterized in that the first sense amplifier is operably coupled a memory array for providing values at the first true output and the first complementary output that are indicative of values stored in the memory array, and the second sense amplifier is operably coupled to a second memory array for providing values at the second true output and the second complementary output that are indicative of values stored in the memory array. The circuit may further comprise a cache, wherein the first sense amplifier, the second sense amplifier, and the latch circuit are implemented in the cache. The circuit may further comprise a processor in which the processor includes the cache.
[0016] Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, only two pairs of complementary output signals are being received by the latch but more than two may be supplied. This could be implemented with additional pairs of NOR gates, pairs of N channel pull-down transistors, and pairs of P channel blocking transistors for each additional pair of complementary output signals. Also instead of a plurality of pairs of complementary signals there may be only one pair. This could then be implemented with just one pair of NOR gates, one pair of N channel pull-downs, and one pair of P channel blocking transistors. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
[0019] Unless stated otherwise, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

中文:
[0001]本公开总体上涉及存储器,并且更具体地,涉及具有低电压数据路径的存储器。
[0002]随着特征尺寸持续缩小,对较低电压操作的需求也在继续。在要求较少功率方面,较低电压是有利的,而且由于具有减小的特征尺寸的晶体管仅能承受有限的电压,因此较低电压也是必要的。这是关于器件的所有部分的一个问题。通常有利的其他因素是操作速度和功耗。因此,对于诸如电源电压的一个约束所需的任何改变,均不应不利地影响速度和功耗。具有减小的特征尺寸的晶体管常常具有这两个优点,这也使得更加期望较低的特征尺寸。将其实现的电路仍然不应不利地影响速度和功耗的固有改进。这包括存储器中的输出数据路径。
[0003]因此,需要一种可操作于较低电压同时兼顾速度和功耗的存储器数据路径。
[0004]本发明借助于示例进行说明且不限于附图,在附图中相同的附图标记表示相似的元素。图中的元素是为了简化和清楚的目的而示出的且没有必要依比例绘制。
[0005]图1是具有使用本发明的实施例的存储器的集成电路的框图;并且
[0006]图2是更加详细地示出图1的一部分数据路径的组合框图和电路图。
[0007]存储器的数据路径从存储器阵列开始,通过读出放大器,通过NOR门,通过N沟道晶体管并且通过提供输出的锁存器。读出放大器向NOR门提供互补数据,该NOR门向N沟道晶体管提供输出。该NOR门向锁存器提供输出。这具有向一个反相器的栅极和另一反相器的漏极提供输出的效果。额外的P沟道晶体管与锁存器的反相器串联。由于NOR门的输出,与漏极接收信号的反相器串联的P沟道晶体管是不导通的,以阻挡电流流向为锁存器提供输入的N沟道晶体管。电流阻挡减少了N沟道晶体管须吸收的电流的量。这使得N沟道晶体管即使在减小的电压下,仍是充分导通的,以使锁存器的状态翻转。通过参考附图和说明书可以更好地理解这一点。
[0008]图1中示出了包括处理器4、其他模块6和存储器8的电路2。处理器4进一步包括L1高速缓存10和L2高速缓存12。在该情况中高速缓存10和12是用于提高处理器4的效率的存储器。处理器4首先尝试从L1高速缓存取数据,随后是L2高速缓存,再随后是存储器8。处理器4使用这三个存储器以及其他模块6执行操作。
[0009]在图2中更加详细地将L2高速缓存12示出为存储器12,该存储器12包括阵列部分13、专用反相器14、专用反相器16、NOR门18、N沟道晶体管20、NOR门22、N沟道晶体管24、NOR门26、N沟道晶体管28、NOR门30和N沟道晶体管32。阵列部分13包括阵列34、读出放大器36、存储器阵列38和读出放大器40。阵列部分包括未单独标识的额外的存储器阵列和读出放大器。专用反相器14包括P沟道晶体管46、N沟道晶体管48、P沟道晶体管42和P沟道晶体管44。专用反相器16包括P沟道晶体管56、N沟道晶体管58、P沟道晶体管52和P沟道晶体管54。专用反相器14和16一起作为锁存器操作。读出放大器36具有一对互补输出D1和D1B来表示从存储器阵列34中选择的存储器单元。读出放大器36可以具有其他输出来表示到达其他电路的其他存储器单元。读出放大器40具有一对互补输出D2和D2B来表示从存储器阵列38中选择的存储器单元。读出放大器40具有其他输出来表示到达其他电路的其他存储器单元。
[0010]NOR门18具有用于接收输出D1B的第一输入、用于接收启用信号ENB1的第二输入、和输出。当信号ENB1是逻辑低时,信号ENB 1允许NOR门18提供与输出D1B反相的输出。NOR门22具有用于接收输出D2B的第一输入、用于接收启用信号ENB2的第二输入、和输出。当信号ENB2是逻辑低时,信号ENB2允许NOR门22提供与输出D2B反相的输出。NOR门26具有用于接收输出D1的第一输入、用于接收启用信号ENB1的第二输入、和输出。当信号ENB1是逻辑低时,信号ENB1允许NOR门26提供与输出D1反相的输出。NOR门30具有用于接收输出D2的第一输入、用于接收启用信号ENB2的第二输入、和输出。当信号ENB2是逻辑低时,信号ENB2允许NOR门30提供与输出D2反相的输出。晶体管20具有连接至NOR门18的输出的栅极、连接至地的源极、和漏极。晶体管24具有连接至NOR门22的输出的栅极、连接至地的源极、和漏极。晶体管28具有连接至NOR门26的输出的栅极、连接至地的源极、和漏极。晶体管32具有连接至NOR门30的输出的栅极、连接至地的源极、和漏极。晶体管42具有连接至正电源端子VDD的源极、连接至NOR门26的输出的栅极、和漏极。晶体管44具有连接至晶体管42的漏极的源极、连接至NOR门30的输出的栅极、和漏极。晶体管46具有连接至晶体管44的漏极的源极、连接至晶体管20和24的漏极的栅极、和漏极。晶体管48具有连接至晶体管46的漏极的漏极、连接至晶体管46的栅极的栅极、和连接至地的源极。晶体管52具有连接至正电源端子VDD的源极、连接至NOR门18的输出的栅极、和漏极。晶体管54具有连接至晶体管52的漏极的源极、连接至NOR门22的输出的栅极、和漏极。晶体管56具有连接至晶体管54的漏极的源极、连接至晶体管28、32、46和48的漏极的栅极、以及连接至晶体管46和48的栅极和晶体管20和24的漏极的漏极。晶体管58具有连接至晶体管56的漏极的漏极、连接至晶体管56的栅极的栅极、和连接至地的源极。晶体管46和48的漏极提供输出OUT。晶体管56和58的漏极提供与输出OUT互补的输出OUTB。晶体管42和44的顺序可以反转。晶体管42和44相互串联并且与包括晶体管46和48的反相器串联。对于晶体管52和54情况亦是如此。
[0011]在操作中,阵列部分13通过读出放大器36和40自存储器阵列34和38提供数据作为互补信号,此时这些信号表示所选择的存储器单元的逻辑状态。这常常被称为存储器的活跃周期,在该情况中该存储器是存储器12。在未处于活跃周期时,这常常被称为预充电周期,信号D1、D1B、D2和D2B保持于逻辑高。启用信号ENB1和ENB2也保持于逻辑高。这使NOR门18、22、26和30提供逻辑低信号作为使晶体管42、44、52和54导通的输出。当晶体管42、44、52和54导通时,反相器14和16用作锁存器以保持被提供为输出OUT和OUTB的最后的逻辑状态。在活跃周期中,一对NOR门,即NOR门18和26或者NOR门22和30将分别由启用信号ENB 1或ENB2通过切换到逻辑低而被启用。该逻辑低随后允许接收该逻辑低的一对NOR门响应该NOR门的另一个输入。对于提供要被输出的数据的读出放大器36的示例,NOR门18和26接收来自读出放大器36的读出数据。当存在足够的时间使读出放大器36执行其读出功能并且向NOR门18和26提供有效数据时,启用信号ENB1被启用到逻辑低状态,由此NOR门18和26响应输出信号D1和D1B。对于输出D1是逻辑高并且因此D1B是逻辑低的示例,使P沟道晶体管52不导通并且使晶体管20导通。晶体管20的漏极连接至晶体管46和48的栅极,使晶体管48不导通并且使晶体管46导通。然而,由于反相器14和16被连接为形成锁存器,因此晶体管20的漏极还耦合至晶体管56和58的漏极。先前,对于锁存器提供逻辑高用于OUTB的情况,晶体管56将导通并且将VDD耦合至OUTB节点。变得导通的N沟道晶体管20将因此通过晶体管56抽取电流,使得更加难于使晶体管46导通。由于晶体管20的栅极上的逻辑高,较低的电源电压并且因此的较低的电压,晶体管20将不具有足以克服通过晶体管56提供的电流的驱动强度,使晶体管46的状态从不导通翻转到充分导通,使晶体管58变得导通。耦合至晶体管52的NOR门18的输出使晶体管52变得不导通,因此从VDD到晶体管56的电流路径被阻挡,防止通过晶体管56将电流提供给晶体管20。在没有通过晶体管56的额外电流负载的情况下,即使在晶体管20的栅极上的驱动电压减小时,晶体管20仍可以使晶体管46导通。通过确保阻挡从VDD到晶体管56的电流路径,晶体管20使晶体管46更加快速地导通,因此提高了速度。而且,节约了电流。因此,存在减小的电压下的速度、功耗和可操作性的益处。
[0012]在输出D1B是逻辑低的该示例中,输出D1是逻辑高,这使NOR门26保持提供逻辑低输出,由此晶体管28保持于不导通状态。由于NOR门26的输出保持于逻辑低,因此晶体管42保持导通。相似地,对于NOR门22和30,启用信号ENB2保持于逻辑高,输出D2和D2B使NOR门22和30保持提供逻辑低输出。这使晶体管54和44保持导通。提供关于输出信号D1是逻辑低并且信号D1B是逻辑高的情况的类似操作。在该情况中,晶体管42变得不导通而P沟道晶体管44、52和54保持导通。晶体管42阻挡从VDD到晶体管46的电流路径并且因此防止晶体管46提供导通晶体管28须吸收的额外电流。因此晶体管28可以使晶体管56变得导通,这又可以使晶体管48变得导通。对于启用信号ENB2被启用的情况,发生相同类型的操作。在该情况中,NOR门22和30响应接收信号D2和D2B的该NOR门的输入,由此使晶体管44或54之一变得不导通。这允许N沟道下拉晶体管,即晶体管24或32,高效地和可靠地使对应的P沟道晶体管46或56分别变得导通。
[0013]到目前为止应认识到,描述了一种用于存储器中的数据路径的电路。该电路包括提供一组输出的第一读出放大器,其中该组包括第一真实输出和第一互补输出。该电路进一步包括耦合至第一真实输出的第一输入。该电路进一步包括耦合至第一互补输出的第二输入。该电路进一步包括第一N沟道晶体管,该第一N沟道晶体管包括连接至该第一输入的栅极。该电路进一步包括第二N沟道晶体管,该第二N沟道晶体管包括连接至该第二输入的栅极。该电路进一步包括一对交叉耦合反相器,其中该对包括第一反相器和第二反相器。该第一反相器包括第一P沟道晶体管和第三N沟道晶体管,该第一P沟道晶体管的栅极和该第三N沟道晶体管的栅极连接至第一节点,该第一P沟道晶体管的第一电流端子和该第三N沟道晶体管的第一电流端子连接至第二节点。该第二反相器包括第二P沟道晶体管和第四N沟道晶体管,该第二P沟道晶体管的栅极和该第四N沟道晶体管的栅极连接至该第二节点,该第二P沟道晶体管的第一电流端子和该第四N沟道晶体管的第一电流端子连接至该第一节点。该电路进一步包括第三P沟道晶体管,该第三P沟道晶体管包括连接至该第一输入的栅极。该电路进一步包括第四P沟道晶体管,该第四P沟道晶体管包括连接至该第二输入的栅极。该第三P沟道晶体管和该第一P沟道晶体管串联堆叠。该第四P沟道晶体管和该第二P沟道晶体管串联堆叠。该电路可以进一步包括第二读出放大器、第三和第四输入、以及第五和第六N和P沟道晶体管。该第二读出放大器提供第二组输出,其中该第二组包括第二真实输出和第二互补输出。该第三输入耦合至该第二真实输出。该第四输入耦合至该第二互补输出。该第五N沟道晶体管包括连接至该第三输入的栅极。该第六N沟道晶体管包括连接至该第四输入的栅极。该第五P沟道晶体管包括连接至该第三输入的栅极。该第六P沟道晶体管包括连接至该第四输入的栅极。该第三P沟道晶体管、第五P沟道晶体管和第一P沟道晶体管串联堆叠。该第四P沟道晶体管、第六P沟道晶体管和第二P沟道晶体管串联堆叠。该电路可以进一步包括第一NOR门和第二NOR门。该第一NOR门包括连接至该第一输入的输出,该第一NOR门包括耦合至第一真实输出的输入。该第二NOR门包括连接至该第二输入的输出,该第二NOR门包括耦合至第一互补输出的输入。该第一NOR门可以包括连接至启用信号线的输入。该第二NOR门可以包括连接至启用信号线的输入。该第一N沟道晶体管可以包括连接至该第二节点的第一电流端子。该第二N沟道晶体管包括连接至该第一节点的第一电流端子。该电路可以进一步包括电源端子。该第三P沟道晶体管可以位于晶体管堆叠中并且位于该第一P沟道晶体管和该电源端子之间。该第四P沟道晶体管可以位于晶体管堆叠中并且位于该第二P沟道晶体管和该电源端子之间。该第一P沟道晶体管可以包括第二电流端子,该第三P沟道晶体管可以包括第一电流端子和第二电流端子;并且该第一P沟道晶体管的第二电流端子可以连接至第三P沟道晶体管的第一电流端子。该电路可以进一步包括存储器阵列并且该读出放大器可操作地耦合该存储器阵列,用于在第一真实输出和第一互补输出处提供值来表示该存储器阵列中存储的值。该电路可以进一步包括高速缓存,其中该高速缓存包括存储器阵列、第一读出放大器、第一输入、第二输入、第一N沟道晶体管、第二N沟道晶体管、一对交叉耦合反相器、第三P沟道晶体管和第四P沟道晶体管。该电路可以进一步包括处理器,该处理器包括该高速缓存。
[0014]还如下描述了一种用于存储器中的数据路径的电路。该电路包括提供第一组输出的第一读出放大器,其中该第一组包括第一真实输出和第一互补输出。该电路进一步包括提供第二组输出的第二读出放大器,其中该第二组包括第二真实输出和第二互补输出。该电路进一步包括锁存器电路,该锁存器电路包括耦合至该第一真实输出的第一输入、耦合至该第一互补输出的第二输入、耦合至该第二真实输出的第三输入和耦合至该第二互补输出的第四输入。该锁存器包括:第一N沟道晶体管,其包括连接至该第一输入的栅极;第二N沟道晶体管,其包括连接至该第二输入的栅极;第三N沟道晶体管,其包括连接至该第三输入的栅极;第四N沟道晶体管,其包括连接至该第四输入的栅极;和一对交叉耦合反相器。该对包括第一反相器和第二反相器。该第一反相器包括第一P沟道晶体管和第五N沟道晶体管,该第一P沟道晶体管的栅极和该第五N沟道晶体管的栅极连接至第一节点,该第一P沟道晶体管的第一电流端子和该第五N沟道晶体管的第一电流端子连接至第二节点。该第二反相器包括第二P沟道晶体管和第六N沟道晶体管,该第二P沟道晶体管的栅极和该第六N沟道晶体管的栅极连接至该第二节点,该第二P沟道晶体管的第一电流端子和该第六N沟道晶体管的第一电流端子连接至该第一节点。该电路进一步包括第三P沟道晶体管,其包括连接至该第一输入的栅极。该电路进一步包括第四P沟道晶体管,其包括连接至该第三输入的栅极。该电路进一步包括第五P沟道晶体管,其包括连接至该第二输入的栅极。该电路进一步包括第六P沟道晶体管,其包括连接至该第四输入的栅极。该第三P沟道晶体管、第四P沟道晶体管和第一P沟道晶体管串联堆叠。该第五P沟道晶体管、第六P沟道晶体管和第二P沟道晶体管串联堆叠。该电路可以进一步包括第一、第二、第三和第四NOR门。该第一NOR门包括连接至该第一输入的输出和耦合至该第一真实输出的输入。该第二NOR门包括连接至该第二输入的输出和耦合至该第一互补输出的输入。该第三NOR门包括连接至该第三输入的输出和耦合至该第二真实输出的输入。该第四NOR门包括连接至该第四输入的输出和耦合至该第二互补输出的输入。该第一NOR门可以包括连接至第一启用信号线的输入,该第二NOR门可以包括连接至该第一启用信号线的输入,该第三NOR门可以包括连接至第二启用信号线的输入,并且该第四NOR门可以包括连接至该第二启用信号线的输入。该第一N沟道晶体管可以包括连接至该第二节点的第一电流端子,该第三N沟道晶体管可以包括连接至该第二节点的第一电流端子,该第二N沟道晶体管可以包括连接至该第一节点的第一电流端子,并且该第四N沟道晶体管可以包括连接至该第一节点的第一电流端子。该电路可以进一步包括电源,其中该第三P沟道晶体管和第四P沟道晶体管位于晶体管堆叠中并且位于该第一P沟道晶体管和电源端子之间,并且该第五P沟道晶体管和第六P沟道晶体管位于晶体管堆叠中并且位于该第二P沟道晶体管和电源端子之间。该电路的进一步的特征可以在于,该第一P沟道晶体管包括第二电流端子,该第三P沟道晶体管包括第一电流端子和第二电流端子,该第四P沟道晶体管包括第一电流端子和第二电流端子,该第一P沟道晶体管的第二电流端子连接至该第四P沟道晶体管的第一电流端子,并且该第四P沟道晶体管的第二电流端子连接至该第三P沟道晶体管的第一电流端子。该电路的进一步的特征可以在于,该第一读出放大器可操作地耦合存储器阵列,用于在该第一真实输出和第一互补输出处提供值来表示该存储器阵列中存储的值,并且该第二读出放大器可操作地耦合第二存储器阵列,用于在该第二真实输出和第二互补输出处提供值来表示该存储器阵列中存储的值。该电路可以进一步包括高速缓存,其中该第一读出放大器、第二读出放大器和锁存器电路在该高速缓存中实现。该电路可以进一步包括处理器,其中该处理器包括该高速缓存。
[0016]尽管此处参考特定实施例描述了本发明,但是在不偏离如附属权利要求中阐述的本发明的范围的前提下可以进行多种修改和改变。例如,虽然锁存器仅接收两对互补输出信号,但是可以提供多于两对的信号。对于每个额外的互补输出信号对,这可以通过额外的NOR门对、N沟道下拉晶体管对和P沟道阻挡晶体管对实现。而且,作为对多个互补信号对的替代,可以仅存在一个对。这于是可以通过仅一对NOR门、一对N沟道下拉晶体管和一对P沟道阻挡晶体管实现。因此,说明书和附图应被视为说明性的而非限制性的,并且所有该修改应涵盖于本发明的范围内。此处针对特定实施例描述的任何益处、优点或者对问题的解决方案不应被解释为任何或所有权利要求的关键的、必须的或基本的特征或元素。
[0019]除非另外说明,否则诸如“第一”和“第二”的术语用于任意区分由该术语描述的元素。因此,这些术语没有必要指出这些元素的时间上或其他的优先顺序。