English:
[0002] Serial communication is common in industrial control applications. For example, serial half-duplex communication in accordance with RS-485 is widely used in automation systems. Applications such as factory automation systems often employ programmable logic controllers that use RS-485 for communication. Some systems are moving to Ethernet-based communication, but still require support for prevalent legacy systems. For example, RS-485 does not specify speed, format and protocol of the serial communication. Interoperability of devices from different manufacturers, even if similar, is not assured by merely complying with the signal level specifications.
[0003] An example of a conventional communication system using serial half-duplex communication is shown diagrammatically in FIG. 1, in which an integrated circuit 10 (e.g., a RISC microprocessor), including a host processor 11 and a universal asynchronous receiver/transmitter (UART) 12, cooperates with an external transceiver (XCVR) 13, such as a further integrated circuit. The UART 12 outputs to the transceiver 13 data TXD, which has been received from the host processor 11 and is transmitted by the transceiver onto a devices bus that has one or more connected devices, as shown diagrammatically at 14. Similarly, the UART 12 receives from the transceiver 13 data RXD, which has been received by the transceiver 13 from the devices bus 14. The UART 12 provides this received data to the host processor 11. The host processor 11 provides to the transceiver 13 control signaling TX RX, which appropriately enables and disables transmit operation and receive operation of the transceiver 13.
[0004] A turn-around operation occurs when the host processor 11 (using the TX RX signal) switches the transceiver 13 from a transmit (TX) mode to a receive (RX) mode, or vice versa. For example, for transition from TX mode to RX mode, turn-around time is the time required to transition the transceiver 13 from the TX mode (where transmit and receive operations of the transceiver 13 are respectively enabled and disabled) to the RX mode (where transmit and receive operations of the transceiver 13 are respectively disabled and enabled). This turn-around time begins when the last transmitted bit has completely traversed the transceiver 13.
[0005] For communication in many automation system applications, low latency (e.g., aggressively low latency) is important. For example, the turn-around from TX mode to RX mode should happen as soon as possible after the last transmitted bit has traversed the external transceiver (e.g., 13 in FIG. 1). Accordingly, the turn-around time from TX mode to RX mode should be as short as possible.
[0006] In described examples, an integrated circuit apparatus includes a host processor and a UART. The UART is coupled for communication with the host processor and configured for serial half-duplex communication with a transceiver that is external to the apparatus. The transceiver assumes a transmit mode of operation and a receive mode of operation during the serial half-duplex communication. Also, the apparatus includes logic that is separate from the host processor, coupled to the UART, and responsive to operation of the UART for signaling to the transceiver respective indications of when to assume the transmit mode and when to assume the receive mode.
[0007] FIG. 1 diagrammatically shows a conventional communication system using serial half-duplex communication.
[0008] FIG. 2 diagrammatically shows a communication system according to example embodiments.
[0009] FIG. 3 shows operations that may be performed by the system of FIG. 2.
[0010] FIG. 4 diagrammatically shows a communication system according to further example embodiments.
[0011] FIG. 5 shows operations that may be performed by the system of FIG. 4.
[0012] Depending on the software used in the host processor (such as shown at 11 in FIG. 1), the turn-around time associated with a transition from the TX mode to the RX mode of an external serial half-duplex transceiver (such as shown at 13 in FIG. 1) could have a negative impact on the receive capability of the communication link. If the turn-around time is too long, some of the incoming RX data will be missed. Some link protocols require the turn-around operation to occur within two bit times. In at least one example, for communication at 115.2k baud, a turn-around time of two bit times would be well within the commonly requested 130us.
[0013] Example embodiments control TX/RX mode transitions of the external transceiver separately from the host processor, thereby avoiding slow turn-around times that may be associated with host processor control of the TX RX mode transitions. Some embodiments provide, on the same integrated circuit as the host processor, logic that is separate from the host processor and controls the TX RX mode transitions.
[0014] FIG. 2 diagrammatically shows a communication system according to example embodiments. In the system of FIG. 2, a serial half-duplex UART 12 within an integrated circuit 20 interfaces communications between a host processor 23 of the integrated circuit 20 and an external transceiver 13 (an integrated circuit in some embodiments) that is coupled in turn to a devices bus (not explicitly shown in FIG. 2). However, in the system of FIG. 2, a coprocessor 21 (in integrated circuits such as 10 and 20 of FIGS. 1 and 2) is used for controlling transitions between the TX and RX modes of the transceiver 13. Thus, the host processor 23 of FIG. 2 does not control the TX/RX mode transitions, whereas the host processor 11 of FIG. 1 does control those transitions.
[0015] The coprocessor 21 controls the TX/RX mode transitions by exploiting knowledge of the timing and structure of serial data frames (also referred to as characters) transmitted at TXD by the UART 12. For example, frames transmitted at TXD usually begin with a start bit that is followed by a predetermined number of data bits (and one or more parity bits in some embodiments), which are in turn followed by one or more stop bits (usually one stop bit). In some embodiments, the frame contains eight data bits. The coprocessor 21 is coupled to the TXD output of the UART 12, and monitors the transmitted frame. Based on this monitoring of the transmitted frame, the coprocessor 21 outputs to the transceiver 13 signaling at TX/RX to indicate selection of the TX mode of the transceiver 13.
[0016] In the aforementioned frame monitoring, the coprocessor 21 monitors the TXD output of the UART 12 to detect occurrence of a start bit. Detection of the start bit triggers the coprocessor 21 to signal (at TX/RX) immediately for the TX mode of the transceiver 13 (e.g., TX enabled and RX disabled). In some embodiments, the TX or RX mode is selected by simply toggling a single digital signal that, depending on its logic level, enables TX while disabling RX, or vice versa. Detection of the start bit also triggers operation of a timer function at 22 in coprocessor 21. The total amount of time required to transmit a frame, which includes a start bit, multiple data (and optional parity) bits, and a stop bit, is known to the coprocessor 21. When triggered by start bit detection, the timer function 22 begins timing the frame transmission. When the timer function 22 indicates that the frame transmission time has elapsed, the coprocessor 21 signals the transceiver 13 for selection of the RX mode.
[0017] In some embodiments, the timer function 22 implements a delay time immediately after the frame transmission time has elapsed. The coprocessor 21 waits until the delay time expires, and then signals for the RX mode. The delay time helps ensure that the stop bit has completely traversed the transceiver 13 before the switch to RX mode occurs. Also, the coprocessor 21 continues to monitor the TXD output of the UART 12 during the delay time, thereby avoiding unnecessary toggling of the TX/RX select signal between frames in the event that a burst of consecutive frames is transmitted. Accordingly, the start bit of a second (or other subsequent) frame in a burst may be detected during the delay time, causing TX mode to remain selected. This operation can avoid a situation in which (a) a switch to RX mode occurs after completion of a frame in a burst, followed by (b) a switch right back to TX mode when the start bit of the next frame of the burst is detected. In various embodiments, the delay has various time durations, such as at least one bit transmission time (bit time), some fraction of a bit time, and combinations of at least one bit time and some fraction of a bit time.
[0019] The above-described use of the coprocessor 21 frees the host processor 23 from the task of switching the TX RX mode of the transceiver 13. This is in contrast with conventional arrangements such as described above relative to FIG. 1 , wherein the host processor performs the task of switching the TX/RX mode. The mode control by coprocessor 21 helps to avoid occurrences of excessive turn-around times that may be associated with host processor control.
[0021] FIG. 4 diagrammatically shows a communication system according to further example embodiments. The system of FIG. 4 is generally similar to that of FIG. 2, except a coprocessor 41 within the integrated circuit 40 uses a line status register (LSR) 42 (conventionally available in the UART 12) to track progress of frame transmission on the TXD output of the UART 12. The LSR 42 conventionally indicates when transmit hold and shift registers of the UART 12 are empty, which is an indication that transmission of the frame is complete.
[0022] FIG. 5 shows further operations that may be performed according to example embodiments. In some embodiments, the system of FIG. 4 is capable of performing the operations of FIG. 5. At 51, monitoring for a start bit is shown. If a start bit is detected at 51, the TX mode is selected at 52, and the LSR is monitored starting at 53. When the LSR indicates at 54 that transmission is complete, the RX mode is selected at 55, after which the next start bit is awaited at 51.
[0023] The techniques described above relative to FIGS. 2-5 are easily scalable to accommodate multiple UARTs 12 in each of the integrated circuits 20 and 40, with multiple external transceivers 13 respectively coupled to the multiple UARTs. Such multiple UART/XCVR combinations are usually the case, such as in factory automation applications. The firmware for the coprocessor 21 or 41 provides configuration parameters to identify, for each of the multiple UART/XCVR combinations, which terminals of the integrated circuit are to be used by the coprocessor for monitoring the TXD output of the associated UART 12, and for outputting the TX RX signal to the associated XCVR 13.
[0024] No interrupt processing is required on the host processor for TX RX mode control in the above-described embodiments, so no impact exists on the host UART driver software operation. The firmware for the coprocessor may be loaded in conventional fashion by the host processor (e.g., a Linux or RTOS host processor driver) written for the operating system used on the host processor.
[0025] In some embodiments, the transceivers 13 are provided as RS-485 transceivers, such as the commercially available SN65HVD82 RS-485 transceiver. In some embodiments, the integrated circuits 20 and 40 are provided as RISC microprocessors, such as the commercially available AM335x/AM437x/AM57xx or similarly enabled microprocessors.
[0026] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

中文:
[0002]串行通信在工业控制应用中是常见的。举例来说,根据RS-485的串行半双工通信在自动化系统中广泛使用。例如工厂自动化系统的应用通常采用使用RS-485进行通信的可编程逻辑控制器。一些系统正朝基于以太网通信发展,但是仍然需要支持普遍的旧系统。举例来说,RS-485并未规定串行通信的速度、格式及协议。仅仅符合信号电平规范并不保证来自不同制造商(即使类似)的装置的互操作性。
[0003]图1中以图表形式展示使用串行半双工通信的常规通信系统的实例,其中包含主机处理器11及通用异步接收器/发射器(UART)12的集成电路10(例如,RISC微处理器)与外部收发器(XCVR)13(例如另一集成电路)协作。UART 12将数据TXD输出到收发器13,所述数据TXD已从主机处理器11接收并由收发器发射到具有一或多个连接装置的装置总线(如以图表形式示出为14)上。类似地,UART 12从收发器13接收数据RXD,所述数据RXD已由收发器13从装置总线14接收。UART 12将此接收的数据提供到主机处理器11。主机处理器11将控制信令TX/RX提供到收发器13,所述控制信令TX/RX适当地启用及停用收发器13的发射操作及接收操作。
[0004]当主机处理器11(使用TX/RX信号)将收发器13从发射(TX)模式切换为接收(RX)模式时发生周转操作,或反之亦然。举例来说,对于从TX模式到RX模式的转变,周转时间是将收发器13从TX模式(其中收发器13的发射及接收操作分别被启用及停用)转变为RX模式(其中收发器13的发射及接收操作分别被停用及启用)所需要的时间。当最后发射的位已完全越过收发器13时开始此周转时间。
[0005]对于许多自动化系统应用中的通信,低延时(例如,逐渐变低延时)是重要的。举例来说,从TX模式到RX模式的周转应在最后发射的位已越过外部收发器(例如,图1中的13)之后尽快发生。因此,从TX模式到RX模式的周转时间应尽可能短。
[0006]在所描述的实例中,集成电路设备包含主机处理器及UART。UART经耦合用于与主机处理器通信且经配置用于与在所述设备外部的收发器进行串行半双工通信。收发器在串行半双工通信期间采用发射操作模式及接收操作模式。此外,所述设备包含逻辑,所述逻辑与主机处理器分离、耦合到UART且响应于UART的操作用于向收发器发信号通知何时采用发射模式及何时采用接收模式的相应指示。
[0007]图1以图表形式展示使用串行半双工通信的常规通信系统。
[0008]图2以图表形式展示根据实例实施例的通信系统。
[0009]图3展示可由图2的系统执行的操作。
[0010]图4以图表形式展示根据其它实例实施例的通信系统。
[0011]图5展示可由图4的系统执行的操作。
[0012]取决于主机处理器(例如图1中示为11)中所使用的软件,与从外部串行半双工收发器(例如图1中示为13)的TX模式到RX模式的转变相关联的周转时间可对通信链路的接收能力具有负面影响。如果周转时间太长,那么将错失一些传入的RX数据。一些链路协议要求周转操作发生在两个位时间内。在至少一个实例中,对于115.2k波特下的通信,两个位时间的周转时间将完全在通常请求的130us内。
[0013]实例实施例控制与主机处理器分离的外部收发器的TX/RX模式转变,借此避免减缓可与TX/RX模式转变的主机处理器控制相关联的周转时间。一些实施例在与主机处理器相同的集成电路上提供与主机处理器分离并控制TX/RX模式转变的逻辑。
[0014]图2以图表形式展示根据实例实施例的通信系统。在图2的系统中,集成电路20内的串行半双工UART 12介接集成电路20的主机处理器23与继而耦合到装置总线(图2中未明确展示)的外部收发器13(一些实施例中的集成电路)之间的通信。然而,在图2的系统中,协同处理器21(在集成电路中,例如图1及2的10及20)用于控制收发器13的TX模式与RX模式之间的转变。因此,图2的主机处理器23并不控制TX/RX模式转变,而图1的主机处理器11确实控制所述转变。
[0015]协同处理器21通过利用对在TXD处由UART 12发射的串行数据帧(又称为字符)的时序及结构的了解来控制TX/RX模式转变。举例来说,在TXD处发射的帧通常开始于起始位,接着是预定数目个数据位(及一些实施例中的一或多个奇偶校验位),所述数据位后继而接着一或多个终止位(通常一个终止位)。在一些实施例中,帧含有八个数据位。协同处理器21耦合到UART 12的TXD输出并监测所发射帧。基于所发射帧的此监测,协同处理器21将TX/RX处的信令输出到收发器13以指示收发器13的TX模式的选择。
[0016]在前文提及的帧监测中,协同处理器21监测UART 12的TXD输出以检测起始位的发生。起始位的检测触发协同处理器21(在TX/RX处)立即发信号通知收发器13的TX模式(例如,启用TX且停用RX)。在一些实施例中,TX或RX模式是通过仅仅切换单个数字信号而选择,所述数字信号取决于其逻辑电平而启用TX同时停用RX,或反之亦然。起始位的检测还触发协同处理器21中的22处的计时器功能的操作。协同处理器21已知发射帧(包含起始位、多个数据(及任选奇偶校验)位及终止位)所需要的总时间量。当由起始位检测触发时,计时器功能22开始对帧发射计时。当计时器功能22指示已经过帧发射时间时,协同处理器21向收发器13发信号通信RX模式的选择。
[0017]在一些实施例中,计时器功能22在已经过帧发射时间之后立即实施延迟时间。协同处理器21等待直到延迟时间期满,且接着发信号通知RX模式。延迟时间帮助确保终止位在发生到RX模式的切换之前已完全越过收发器13。此外,协同处理器21继续在延迟时间期间监测UART 12的TXD输出,借此在发射连续帧的脉冲串的情况下避免不必要地在帧之间切换TX/RX选择信号。因此,可在延迟时间期间检测到脉冲串中的第二(或其它后续)帧的起始位,从而导致保持选择TX模式。此操作可避免以下情形:(a)在脉冲串中的帧完成之后发生到RX模式的切换,接着(b)当检测到脉冲串的下一帧的起始位时马上返回切换到TX模式。在各个实施例中,延迟具有各种持续时间,例如至少一个位发射时间(位时间)、位时间的某个部分及至少一个位时间与位时间的某个部分的组合。
[0019]协同处理器21的上述使用使主机处理器23免于执行切换收发器13的TX/RX模式的任务。这与例如上文相对于图1描述的常规配置相反,其中主机处理器执行切换TX/RX模式的任务。由协同处理器21进行的模式控制帮助避免发生可与主机处理器控制相关联的过量周转时间。
[0021]图4以图表形式展示根据其它实例实施例的通信系统。图4的系统大致上类似于图2的系统,除集成电路40内的协同处理器41使用线路状态寄存器(LSR)42(常规上可在UART12中使用)以跟踪UART 12的TXD输出上的帧发射的进程之外。LSR 42常规上指示UART 12的发射保持及移位寄存器何时为空,这是完成帧的发射的指示。
[0022]图5展示可根据实例实施例执行的其它操作。在一些实施例中,图4的系统能够执行图5的操作。在51处,展示了对起始位的监测。如果在51处检测到起始位,那么在52处选择TX模式,且在53处监测LSR的起始。当LSR在54处指示完成发射时,在55处选择RX模式,此后在51处等待下一起始位。
[0023]上述相对于图2到5描述的技术可易于扩展到适应集成电路20及40中的每一者中的多个UART 12,其中多个外部收发器13分别耦合到多个UART。此类多个UART/XCVR组合例如在工厂自动化应用中通常如此。用于协同处理器21或41的固件提供配置参数以针对多个UART/XCVR组合中的每一者识别集成电路的哪些终端是由协同处理器用来监测相关联的UART 12的TXD输出且将TX/RX信号输出到相关联的XCVR 13。
[0024]在上述实施例中,主机处理器上TX/RX模式控制并不需要中断处理,因此不存在对主机UART驱动器软件操作的影响。用于协同处理器的固件可以常规方式由主机处理器(例如,Linux或RTOS主机处理器驱动器)加载、经写入用于主机处理器上使用的操作系统。
[0025]在一些实施例中,收发器13被提供作为RS-485收发器,例如商用SN65HVD82RS-485收发器。在一些实施例中,集成电路20及40被提供作为RISC微处理器,例如商用AM335x/AM437x/AM57xx或经类似启用的微处理器。
[0026]所描述实施例中可进行修改且其它实施例可在权利要求书的范围内。