English:
[0001] Embodiments of the invention relate to the field of semiconductor devices. In particular, the embodiments relate to a method of using gas cluster ion beams (GCIB) to fabricate memory cells.
[0003] One such phase-change memory cell 110 may have the structure illustrated in FIGS. IA and IB, which includes a layer of phase-change material 116 between first and second electrodes 112, 118, which are supported by a dielectric material 114 that has an opening containing the first electrode 112. The phase-change material 116 is set to a particular resistance state according to the amount of current applied by the first and second electrodes 112, 118. To obtain an amorphous state (FIG. IB), an initial write current pulse (i.e., a reset pulse) is applied for a first period of time through the conventional phase-change memory cell 110 to alter at least a portion 126 of the phase-change material 116 adjacent to the first electrode 112. The current is removed and the phase-change material 116 cools to a temperature below the crystallization temperature, which results in the portion 126 of the phase-change material 116 covering the first electrode 112 having the amorphous state. To obtain a crystalline state (FIG. IA), a write current pulse (i.e., a set pulse) lower than the initial write current pulse is applied to the phase-change memory cell 110 for a second period of time, which is typically longer in duration than the crystallization time of amorphous phase-change material, resulting in the heating of the amorphous portion 126 of the phase-change material 116 to a temperature below its melting point, but above its crystallization temperature. This causes the amorphous portion 126 of the phase-change material 116 to re- crystallize. The amorphous portion 126 recrystallizes to a state that is maintained once the current is removed and the phase-change memory cell 110 is cooled. The phase-change memory cell 110 is read by applying a read voltage to the electrodes 112, 118, which does not change the state of the phase-change material 116, but which permits reading of the resistance of the phase-change material 116.
[0004] One potential drawback of the above described phase-change memory device 110 is the large programming current needed to achieve the phase change. This need for the large current is a limitation when attempting to reduce the size of the memory cell and when large memory cell arrays are fabricated. Another problem associated with the above described phase- change memory cell 110 is heat loss. Since the phase-change material 116 is in direct contact with a large area of the first electrode 112, there may be a significant amount of heat loss resulting in a large reset current requirement, Additionally, since the programmable volume (i.e., portion 126) of the phase-change material 116 is not confined and has the freedom to extend sideways during phase change, switching stability may be reduced.
[0006] Referring to FIG. 2B, it is known that due to arrival angle distribution and poor step coverage, a conventional physical vapor deposition (PVD) process cannot always accurately control the thickness of the phase-change material 216 deposited along the sidewall 230 of a via 222. The thick layer of phase-change material deposited on a field region 231 surrounding the via 222 poses a problem for the subsequent CMP process, as it introduces large film stress and phase-change material adhesion issues during the CMP process. An excessive overhang of material at the top of the via 222 may cause a "necking in" of the opening which may restrict or prohibit subsequent thin film depositions and/or filling of the structure. This problem may result in voids in the phase-change memory cell and failed memory devices.
[0007] It is therefore desirable to use a fabrication process that provides the level of anisotropy needed at the interface between heater and phase-change material without introducing problems in the overall process flow. It is also desirable to reduce voids and provide a method of fabricating a semiconductor device that allows for the recovery of failed devices due to an excessive overhang of material at the opening of phase-change memory vias.
[0009] FIGS. 2A-2B are schematic views of another conventional phase-change memory cell and its intermediate stages of fabrication.
[0010] FIGS. 3A-3I schematically illustrate the formation of a variable resistance memory cell in accordance with an embodiment described therein.
[0011] FIGS. 4A-4C schematically illustrate the formation of a variable resistance memory cell in accordance with some of the steps of another embodiment described therein.
[0012] In the following detailed description, reference is made to certain embodiments. These embodiments are described with sufficient detail to enable those skilled in the art to practice them. It is to be understood that other embodiments may be employed, and that various structural, logical, and electrical changes may be made.
[0013] The term "substrate" used in the following description may include any supporting structure including, but not limited to, a semiconductor substrate that has an exposed substrate surface. A semiconductor substrate should be understood to include silicon, silicon-on- insulator (SOI), silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures, including those made of semiconductors other than silicon. When reference is made to a semiconductor substrate in the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor or foundation. The substrate also . need not be semiconductor-based, but may be any support structure suitable for supporting an integrated circuit, including, but not limited to, metals, alloys, glasses, polymers, ceramics, and any other supportive materials as is known in the art.
[0014] Embodiments described herein provide a method of forming a material on the bottom of a via that provides the level of anisotropy needed at the interface between heater and variable resistance material. That is, the method provides for uniform coverage at the bottom of a high aspect ratio via without significant deposition on the sidewalls of the via. The method uses gas cluster ion beams (GCIB) to deposit material that exists only in the bottom of the via of a variable resistance memory cell. The method includes forming a first electrode, forming an insulating material over the first electrode, forming a via in the insulating material to expose a surface of the first electrode, forming a heater material on the surface of the first electrode using gas cluster ion beams, removing a portion of the heater material over the insulating material, forming a variable resistance material over the heater material, and forming a second electrode over the variable resistance material.
[0015] Referring to FIGS. 3A-3I, one embodiment is now described with reference to the formation of a variable resistance memory cell, wherein like reference numbers are used consistently for like features throughout the drawings. The embodiments described herein can be utilized for an array of memory cells, which can be formed simultaneously, or in parts of an integrated circuit not used as memory cells.
[0016] FIG. 3 A illustrates a memory device 310 which includes a plurality of variable resistance material memory cells 302 formed by the method described below with respect to FIGS. 3B-3I. Memory device 310 includes a substrate 300, first electrodes 312, heater material 316, variable resistance material 318, and second electrode 320. The memory cells 302 are formed within insulating layers 314, 324.
[0017] FIG. 3B depicts an intermediate variable resistance memory device structure 31 Oa formed by, for example, depositing a first insulating layer 314 over a support substrate 300. The first insulating layer 314 can be formed by any suitable method and can be any insulating material such as e.g., nitrides, oxides, high temperature polymers, low dielectric constant materials, insulating glass, and insulating polymers, among others.
[0018] As shown in FIG. 3 C, the first insulating layer 314 is etched by any suitable method to create vias 301. A first electrode 312 is formed within the vias 301, as depicted in FIG. 3D. The first electrode 312 can be formed by any suitable method and can be any conductive material such as e.g., titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium aluminum nitride (TiAlN), titanium tungsten (TiW) or platinum (Pt), among others.
[0019] Subsequently, as shown in FIG 3E, a second insulating layer 324 is formed over the first insulating layer 314 and the first electrode 312. The second insulating layer 324 can be formed by any suitable method and can be any insulating material such as e.g., nitrides, oxides, high temperature polymers, low dielectric constant materials, insulating glass, or insulating polymers, and may be formed by any method known in the art.
[0020] Referring now to FIG. 3 F, vias 322 are formed in the second insulating layer 324 using methods known in the art, such as photolithographic and etching techniques, to expose a portion of a respective first electrode 312. Optionally, the vias 322 can extend partially through respective first electrodes 312. The vias 322 have a bottom surface 330 and the second insulating layer 324 has a top surface 331, Preferably, the bottom surface 330 is a substantially planar surface. The via 322 can be of any suitable shape, including a substantially cylindrical shape. Although the embodiment is described in terms of forming a via, it can be appreciated that any type of opening including, but not limited to, other apertures, trenches, and contact holes may be formed, as appropriate for the application.
[0021] Referring now to FIG. 3 G, once via 322 is formed, a GCIB deposited heater material 316 is formed over the bottom surfaces 330 of the vias 322 and the top surface 331 of the second insulating layer 324. The heater material 316 is formed such that there is no sidewall deposition except for that portion in contact with a sidewall due to the thickness of the heater material 316. In addition to or instead, the heater material 316 can act as a barrier and/or adhesion material.
[0022] Heater material 316 can be formed of a GeN material, which may have other atoms included, as follows. Gas is injected at high pressure into an ionization chamber of the GCIB tool, which can be the nFusion product made by TEL Epion, for example. Pressures are in a range from about 1500 to about 3000 PSI at the point of gas injection into the ionization chamber, which may be under vacuum. To deposit heater material 316, the GCIB process can use GeH4, N2, He and Ar gases. The percentage of each is used to control material thickness, nitrogen incorporation and anisotropy of the GeN material. Ionized molecular clusters are then directed towards the surface 330, 331 of the memory device 310a, which includes the exposed first electrodes 312 and the second insulating layer 324 . The cluster is accelerated from a potential to ground of about 3 to about 50 keV. The clusters dissociate immediately upon impact with the surface of memory device 310a. The temperature and pressure of the surface increase rapidly for a time (e.g., a spike) on the order of from about 5 to about 15 psec as the beam is scanned across the surface of the memory device. The energy release of the gases creates the new GeN material on the surface or partially within the near surface of the memory device. The location of the new GeN material depends on the voltage potential, species and surface. Gas clusters can be on the order of 30 angstroms in diameter and may be formed of thousands of gas molecules.
[0023] During the fabrication process, when a GCIB is scanned across the surface of the memory device, the scan can include a combination of passes which may be a mix OfGeH4, Ge, N2, Ar, He, methoxide, ethoxide, O2, F2, or N2O gases. The GCIB deposition process may include transitions in the amount of germane (GeH4), nitrogen (N2), argon (Ar), helium (He), methoxide, ethoxide, oxygen (O2), fluorine (F2), nitrous (N2O) gases, or any combination thereof. Scans of pure N2may also be used to control the most beneficial concentration profile of nitrogen. The nitrogen level may be a top down or bottom up gradient within the thickness of the material. The gradient can be high to low, low to high, low to high to low, or high to low to high, depending on the adjacent materials.
[0024] As shown in FIG. 3H, the portion of the GCIB deposited heater material 316 formed on the top surface 331 of the second insulating layer 324 is removed by any suitable technique, e.g. etch according to known techniques. The heater material 316 can include germanium (Ge) as the primary atom and other impurity atoms that can be from about 0.5 to about 15 atomic percent. The impurity atoms can include nitrogen (N), antimony (Sb), fluorine (F), oxygen (O), and tellurium (Te). In one embodiment, the impurity atoms are from 5-10 atomic percent.
[0025] As depicted in FIG. 31, a layer of variable resistance material 318 may be formed over the GCIB deposited heater material 316 by any suitable technique. Suitable techniques include physical vapor deposition, atomic layer deposition, chemical vapor deposition and wet immersion, among others. The variable resistance material 318 can be formed of any phase-change chalcogenide alloy, such as GeχTey, GaSb, SbxTe5,, InSb, InSe, InxSbyTez, SnxSDyTe2, GaxSeyTez, InSbGe, AgInSbTe, GeSnSbTe, TexGeySbzSkand GeSbSeTe, for example. Those variable resistance materials can also have impurities of oxygen (O), fluorine (F), nitrogen (N) and carbon (C). The variable resistance material 318 can also be formed of any other resistive cell material that does not require phase change to change resistance, including NiO, TiO, CuS and SrTiO.
[0026] A top electrode 320 may then be formed over the surface to obtain the resulting variable resistance memory device as shown in FIG. 3 A.
[0027] In an alternative embodiment, the steps shown in FIGS. 3B-3D are performed. Subsequently, as shown in FIG. 4A, a GCIB deposited heater material 316 is blanket deposited over the electrodes 312 and the first insulating layers 314. Then, a portion of the heater material 316 is removed using methods known in the art, such as photolithographic and etching techniques, to expose the insulating layers 314 (FIG. 4B). Referring to FIG. 4C, the second insulating layer 324 is then blanket deposited over the heater materials 316 and the first insulating layers 314. Then, a portion of the second insulating layer 324 is removed using methods known in the art, such as photolithographic and etching techniques, to expose the heater material 316 as shown in FIG. 3H. Subsequently, the method follows the process as outlined with respect to FIG. 31 to achieve the resulting structure shown in FIG. 3A.

中文:
[0001]本发明的实施例涉及半导体装置领域。明确地说,所述实施例涉及一种使用气体团簇离子束(GCIB)来制作存储器单元的方法。
[0003]此一个相变存储器单元110可具有图1A及图1B中所图解说明的结构,其包含介于第一与第二电极112、118之间的一层相变材料116,所述第一及第二电极由具有含纳第一电极112的开口的电介质材料114支撑。根据由第一及第二电极112、118施加的电流的量将相变材料116设定为特定电阻状态。为获得非晶态(图1B),在第一时间周期施加初始写入电流脉冲(即,复位脉冲)穿过常规相变存储器单元110以变更相变材料116的邻近第一电极112的至少一部分126。移除电流且相变材料116冷却到低于结晶温度的温度,此导致相变材料116的覆盖第一电极112的部分126具有非晶态。为获得结晶态(图1A),在第二时间周期将低于初始写入电流脉冲的写入电流脉冲(即,设定脉冲)施加到相变存储器单元110,所述第二时间周期通常在持续时间上比非晶相变材料的结晶时间长,从而导致将相变材料116的非晶部分126加热到低于其熔点但高于其结晶温度的温度。此致使相变材料116的非晶部分126再结晶。非晶部分126再结晶到一旦移除电流且相变存储器单元110经冷却便得以维持的状态。通过将读取电压施加到电极112、118来读取相变存储器单元110,此并不改变相变材料116的状态,但此准许读取相变材料116的电阻。
[0004]上文所描述的相变存储器装置110的一个可能缺点是实现相变需要大的编程电流。在尝试减小存储器单元的大小时及在制作大的存储器单元阵列时,对大电流的此需要为一限制。与上文所描述的相变存储器单元110相关联的另一问题是热损耗。由于相变材料116与第一电极112的大面积直接接触,因此可存在显著的热损耗量,从而导致大的复位电流要求。另外,由于相变材料116的可编程体积(即,部分126)不受局限且具有在相变期间向侧面延伸的自由,因此可减小切换稳定性。
[0006]参考图2B,已知,由于到达角分布及不良阶梯覆盖,常规物理气相沉积(PVD)工艺无法始终准确地控制沿通孔222的侧壁230沉积的相变材料216的厚度。在围绕通孔222的场区域231上沉积厚的相变材料层对后续CMP工艺造成问题,因为其在CMP工艺期间引入大的膜应力及相变材料粘附问题。材料在通孔222的顶部处过度伸出可致使开口“缩颈(necking in)”,此可限制或禁止结构的后续薄膜沉积及/或填充。此问题可导致相变存储器单元中的空隙及有故障的存储器装置。
[0007]因此,期望使用一种在不在整个工艺流程中引入问题的情况下在加热器与相变材料之间的界面处提供所需各向异性水平的制作工艺。还期望减小空隙且提供一种制作半导体装置的方法,所述方法允许恢复由于材料在相变存储器通孔的开口处的过度伸出所致的有故障装置。
[0009]图2A到图2B是另一常规相变存储器单元及其中间制作阶段的示意图。
[0010]图3A到图3I根据本文中所描述的实施例示意性图解说明可变电阻存储器单元的形成。
[0011]图4A到图4C根据本文中所描述的另一实施例的步骤中的某些步骤示意性图解说明可变电阻存储器单元的形成。
[0012]在以下详细描述中,参考某些实施例。充分详细地描述这些实施例以使得所属领域的技术人员能够实践所述实施例。应理解,可采用其它实施例且可做出各种结构、逻辑及电改变。
[0013]以下描述中所使用的术语“衬底”可包含任何支撑结构,包含但不限于具有经暴露衬底表面的半导体衬底。半导体衬底应理解为包含硅、绝缘体上硅(SOI)、蓝宝石上硅(SOS)、经掺杂及未经掺杂半导体、由基底半导体基础支撑的外延硅层及其它半导体结构,包含由除硅以外的半导体制成的那些半导体结构。当在以下描述中参考半导体衬底时,可已利用先前工艺步骤在基底半导体或基础中或其上方形成区域或结。所述衬底也无需是基于半导体的,但可以是适于支撑集成电路的任何支撑结构,包括但不限于金属、合金、玻璃、聚合物、陶瓷及此项技术中已知的任何其它支撑性材料。
[0014]本文中所描述的实施例提供一种在通孔的底部上形成材料的方法,所述方法在加热器与可变电阻材料之间的界面处提供所需的各向异性水平。即,所述方法在通孔的侧壁上没有显著沉积的情况下在高纵横比通孔的底部处提供均匀覆盖。所述方法使用气体团簇离子束(GCIB)来沉积仅存在于可变电阻存储器单元的通孔的底部中的材料。所述方法包含:形成第一电极、在第一电极上方形成绝缘材料、在绝缘材料中形成通孔以暴露第一电极的表面、使用气体团簇离子束在第一电极的表面上形成加热器材料、移除加热器材料的在绝缘材料上方的一部分、在加热器材料上方形成可变电阻材料且在可变电阻材料上方形成第二电极。
[0015]参考图3A到图3I,现在参考可变电阻存储器单元的形成描述一个实施例,其中在所有所述图式中针对相同特征一致地使用相同参考编号。本文中所描述的实施例可用于存储器单元阵列,所述存储器单元阵列可由未用作存储器单元的集成电路同时或部分地形成。
[0016]图3A图解说明存储器装置310,其包含通过下文参考图3B到图3I所描述的方法形成的多个可变电阻材料存储器单元302。存储器装置310包含衬底300、第一电极312、加热器材料316、可变电阻材料318及第二电极320。存储器单元302形成于绝缘层314、324内。
[0017]图3B描绘通过(例如)在支撑衬底300上方沉积第一绝缘层314形成的中间可变电阻存储器装置结构310a。第一绝缘层314可通过任何适合的方法形成且可以是任何绝缘材料,例如,氮化物、氧化物、高温聚合物、低介电常数材料、绝缘玻璃及绝缘聚合物等等。
[0018]如图3C中所示,通过任何适合的方法蚀刻第一绝缘层314以形成通孔301。如图3D中所描绘,在通孔301内形成第一电极312。第一电极312可通过任何适合的方法形成且可以是任何导电材料,例如,氮化钛(TiN)、氮化钽(TaN)、钨(W)、氮化钨(WN)、氮化钛铝(TiAlN)、钛钨(TiW)或铂(Pt)等等。
[0019]随后,如图3E中所示,在第一绝缘层314及第一电极312上方形成第二绝缘层324。第二绝缘层324可通过任何适合的方法形成且可以是任何绝缘材料(例如,氮化物、氧化物、高温聚合物、低介电常数材料、绝缘玻璃或绝缘聚合物)且可通过此项技术中已知的任何方法形成。
[0020]现在参考图3F,使用此项技术中已知的方法(例如,光刻及蚀刻技术)在第二绝缘层324中形成通孔322以暴露相应第一电极312的一部分。任选地,通孔322可部分地延伸穿过相应第一电极312。通孔322具有底表面330且第二绝缘层324具有顶表面331。优选地,底表面330为大致平面表面。通孔322可具有任何适合的形状,包含大致圆柱形形状。虽然就形成通孔描述了所述实施例,但可了解,如适合于本应用,可形成任何类型的开口,包含但不限于其它孔口、沟槽及接触孔。
[0021]现在参考图3G,一旦形成通孔322,便在通孔322的底表面330及第二绝缘层324的顶表面331上方形成经GCIB沉积的加热器材料316。加热器材料316经形成以使得不存在侧壁沉积,由于加热器材料316的厚度而与侧壁接触的部分除外。另外或替代地,加热器材料316可充当阻挡层及/或粘附材料。
[0022]加热器材料316可由GeN材料形成,所述GeN材料可包含有如下其它原子。将气体以高压注入到GCIB工具的离子化室中,所述GCIB工具可以是(例如)由东京威力科创艾派恩股份有限公司(TELEpion)制作的nFusion产品。在气体将注入到所述离子化室(可在真空下)中时,压力是在介于从约1500PSI到约3000PSI的范围内。为沉积加热器材料316,GCIB工艺可使用GeH4、N2、He及Ar气体。使用每一气体的百分比来控制GeN材料的材料厚度、氮并入及各向异性。接着朝向存储器装置310a的表面330、331引导经离子化的分子团簇,所述存储器装置包含经暴露的第一电极312及第二绝缘层324。所述团簇从约3keV的对地电位加速到约50keV。所述团簇在与存储器装置310a的表面碰撞之后立即解离。当所述束扫描跨越存储器装置的表面时,所述表面的温度及压力在大约为从约5微微秒到约15微微秒的时间(例如,尖峰)内迅速增加。气体的能量释放在存储器装置的表面上或部分地在其近表面内形成新的GeN材料。新GeN材料的位置取决于电压电位、种类及表面。气体团簇直径可大约为30埃且可由数以千计的气体分子形成。
[0023]在制作工艺期间,当GCIB扫描跨越存储器装置的表面时,所述扫描可包含通过组合,所述通过组合可以是GeH4、Ge、N2、Ar、He、甲醇盐、乙醇盐、O2、F2或N2O气体的混合。GCIB沉积工艺可包含锗烷(GeH4)、氮(N2)、氩(Ar)、氦(He)、甲醇盐、乙醇盐、氧(O2)、氟(F2)、亚硝(N2O)气体或其任一组合的量的转变。还可使用纯N2的扫描来控制氮的最有益浓度分布。氮水平可以是材料厚度内的从上向下或从下向上梯度。取决于邻近材料,所述梯度可以是高到低、低到高、低到高到低或高到低到高。
[0024]如图3H中所示,通过任何适合的技术(例如,根据已知技术的蚀刻)移除经GCIB沉积的加热器材料316的形成于第二绝缘层324的顶表面331上的部分。加热器材料316可包含锗(Ge)作为初级原子且包含可从约0.5原子百分比到约15原子百分比的其它杂质原子。所述杂质原子可包含氮(N)、锑(Sb)、氟(F)、氧(O)及碲(Te)。在一个实施例中,所述杂质原子为从5原子百分比到10原子百分比。
[0025]如图3I中所描绘,可通过任何适合的技术在经GCIB沉积的加热器材料316上方形成一层可变电阻材料318。适合的技术包含物理气相沉积、原子层沉积、化学气相沉积及湿式浸渍等等。可变电阻材料318可由任何相变硫属化合物合金(例如,GexTey、GaSb、SbxTey、InSb、InSe、InxSbyTez、SnxSbyTez、GaxSeyTez、InSbGe、AgInSbTe、GeSnSbTe、TexGeySbzSk及GeSbSeTe)形成。所述可变电阻材料还可具有氧(O)、氟(F)、氮(N)及碳(C)的杂质。可变电阻材料318还可由不需要相变来改变电阻的任何其它电阻性单元材料(包含NiO、TiO、CuS及SrTiO)形成。
[0026]可接着在表面上方形成顶部电极320以获得如图3A中所示的所得可变电阻存储器装置。
[0027]在替代实施例中,执行图3B到图3D中所示的步骤。随后,如图4A中所示,在电极312及第一绝缘层314上方毯覆沉积经GCIB沉积的加热器材料316。接着使用此项技术中已知的方法(例如,光刻及蚀刻技术)移除加热器材料316的一部分以暴露绝缘层314(图4B)。参考图4C,接着在加热器材料316及第一绝缘层314上方毯覆沉积第二绝缘层324。接着,使用此项技术中已知的方法(例如,光刻及蚀刻技术)移除第二绝缘层324的一部分以暴露加热器材料316,如图3H中所示。随后,所述方法遵循参考图3I所概述的工艺以实现图3A中所示的所得结构。