English:
[0001] The present invention relates generally to electronics, and more specifically to multi chip modules.
[0002] Multi-chip computer systems are generally known to include a plurality of Integrated Circuits (IC) dies that are commonly packaged to support high performance processing systems. In some multi-chip modules, a plurality of ICs is mounted in an array with supporting interconnections and cooling systems. The structure of such multi-chip modules may include a plurality of components laminated into a number of layers with an Integrated Fan Out (InFO) substrate that provides signal connectivity between the plurality of ICs mounted thereto. While the InFO substrate provides efficiency for signal connectivity for the plurality of IC dies mounted thereon, it also has downsides for the Multi-Chip computer system that it services. Because the InFO substrate may have different temperature-based expansion characteristics than other components of the multi-chip module, when the temperature of the multi-chip module changes over time, the InFO substrate may warp, stretch, shrink or be damaged by the changing expansion of the sustrate. Further, a large amount of heat removal from multi-chip modules using an InFO substrate can be difficult in some circumstances.
[0003] One embodiment is a multi-chip module that includes: a Redistribution Layer (RDL) substrate; a first plurality of Integrated Circuit (IC) dies mounted to a first surface of the RDL substrate; a second plurality of IC dies mounted to an opposite second surface; a plurality of sockets mounted upon the second plurality of IC dies; a cold plate mounted to the first plurality of IC dies; and a mounting structure. In this embodiment, the mounting structure may include: a plurality of socket frames coupled to the plurality of sockets; a plurality of holes formed through the RDL substrate; and a plurality of screws extending from the plurality of socket frames through the plurality of holes formed through the RDL substrate and screwed into the cold plate.
[0004] Another embodiment is a method of mounting a multi-chip module to a substrate. The method may include mounting a plurality of integrated circuit dies onto a first surface of a redistribution layer; encapsulating the mounted integrated circuit dies; attaching a floating frames or molded socket, or both onto the integreated circuit on the redistribution layer; mounting a thermal interface module onto the encapsulated IC dies; and installing a cold plate onto the thermal interface module.
[0005] FIG. 1 is a sectional side view block diagram illustrating one embodiment of a multi chip module constructed according to the present disclosure.
[0006] FIG. 2 is a perspective view of the multi-chip module of FIG. 1 according to an embodiment of the present disclosure.
[0007] FIG. 3 is a partial perspective view of a magnified portion of the multi-chip module of FIG. 2.
[0008] FIG. 4 is a sectional side view of the portion of the multi-chip module of FIG. 3.
[0009] FIG. 5 is a sectional side view of the portion of the multi-chip module of FIG. 3 showing details of a load frame.
[0010] FIG. 6 is a top view of a socket of a multi-IC load frame of a multi-chip module according to an embodiment of the present disclosure.
[0011] FIG. 7 is a sectional side view of the socket of the multi-IC load frame of FIG. 6.
[0012] FIG. 8 is a top view of a Voltage Regulator Module (VRM) mounted into the socket structure of the multi-IC load frame of FIG. 6.
[0013] FIG. 9 is a partial sectional side view of the VRM and multi-IC load frame of FIG. 8.
[0014] FIG. 10 is a flow chart illustrating a method for constructing a multi-chip module according to an embodiment of the present disclosure.
[0015] FIG. 11 is a partial sectional side view illustrating a multi-chip module according to another embodiment of the present disclosure.
[0018] FIG. 1 is a sectional side view illustrating a multi-chip module 100 constructed according to the present disclosure. The multi-chip module 100 of FIG. 1 includes a plurality of high power Voltage Regulator Modules (VRMs) 102 A, 102B, 102C, and 102D that mount on a substrate structure 104. The plurality of high power VRMs 102A, 102B, 102C, and 102D are fed by a DC supply voltage 108, e.g., 40 volts, 48 volts, or another relatively voltage, and respectively service a respective plurality of Integrated Circuits (IC) dies 106 A, 106B, 106C, and 106D. In some embodiments, each of the plurality of high power VRMs 102A, 102B, 102C, and 102D produces an output of approximately 0.8 volts and provides 600 watts of power or more to the respective plurality of IC dies 106 A, 106B, 106C, and 106D. Thus, each of the plurality of multiple circuit board high power VRMs 102A, 102B, 102C, and 102D produces in excess of 100 amperes of current to the plurality of IC dies 106 A, 106B, 106C, and 106D.
[0019] FIG. 2 is a perspective view of a portion 200 of the multi-chip module of FIG. 1 according to an embodiment of the present disclosure. Illustrated is an Integrated Fan Out (InFO) substrate 202 upon which a plurality of embedded capacitor structures (embedded CAPs) 204 are mounted. The InFO substrate 202 may be formed in an integrated circuit manufacturing process and have a thickness of approximately 0.1 mm, although other thicknesses of InFO substrates are within the scope of the present disclosure. The InFO substrate 202 may be formed of silicon and include, for each of the embedded caps 204, signal routing connections between the embedded CAPs 204 and corresponding IC dies mounted on an opposite surface of the InFO substrate 202. As will be show in FIG. 3, according to one embodiment of the invention a modular direct-clamp structure 206 is shown for mounting a plurality of sockets 208 onto the embedded CAPs 204 such that the plurality of sockets 208 mechanically couple to a cold plate mounted on an opposite side of the InFO substrate 202.
[0020] FIG. 3 is a partial perspective view of a portion of the multi-chip module of FIG. 2. Shown in detail is one of the modular direct-clamp structures 206 that services the multi-chip module 100. The modular direct-clamp structure 206 includes a socket frame 302 that provides mechanical mounting for four sockets 208 mounted therein, corner clamps 304, and screws 306. The screws extend through the InFO substrate 202 and are secured within a cooling structure for the multi-chip module.
[0021] FIG. 4 is a sectional side view of the portion of the multi-chip module of FIG. 3. The sectional side view of FIG. 4 shows in detail the modular clamp structure 206 and details of its mounting to the cooling structure. The cooling structure includes a cold plate 406 that mounts upon a global manifold structure 408. An IC die 412 mounts upon the InFO substrate 202. The screws 306 engage threads formed in the global manifold structure 408. Shown are plugs 402 that mount to the socket 208 and cases 404 mounted there upon. The cases 404 may house VRMs in some embodiments.
[0022] FIG. 5 is a sectional side view of the portion of the multi-chip module of FIG. 3 showing details of a load frame taken along section 410 of FIG. 4. FIG. 5 illustrates the components previously illustrated in FIG. 4 but with more detail. Note that the InFO substrate 202 provides one or more Redistribution Layers (RDLs) that service the interconnection between the IC dies 412 and the embedded CAPs 204. With the structure of FIG. 5, holes drilled through the InFO substrate 202 are shown. These holes may be formed mechanically or via lasering. The cold plate 406 (and the global manifold structure 408) serve as a structural back plate and provide sufficient stiffness for the InFO substrate 202 to ensure that the InFO substrate 202 will not be damaged due to uneven mechanical loads. The clamping structure provides the components mounted sufficient mobility to prevent cracking during thermal expansion and/or contraction.
[0023] FIG. 6 is a top view of a socket structure 600 of a multi-IC load frame of a multi-chip module according to an embodiment of the present disclosure. The socket structure 600 includes a load frame 602 having a plurality of sockets 604 formed/mounted therein. Screws/washers 606 secure the socket structure 600 to a cold plate. While four sockets 604 are shown in a 2x2 array any array of NxM of socket structures may be provided therewith, with N and M being integers.
[0024] FIG. 7 is a sectional side view of the socket of the multi-IC load frame of FIG. 6. Shown are insert molded LCP sockets 604 surrounded by a metal load frame 604, both of which couple to embedded caps 204.
[0025] FIG. 8 is a top view Voltage Regulator Module (VRMs) mounted into the socket structure of the multi-IC load frame of FIG. 6. The VRMs 802 mount into the sockets 604 via appropriate electrical connections 804.
[0026] FIG. 9 is a partial sectional side view of the VRM and multi-IC load frame of FIG. 8. The VRMs 802 mount upon the sockets 604 via the appropriate electrical connections 604. VRM screws and VRM washers couple to the cold plate via socket screws and a VRM nut/socket. Note that the complete structure is held vertically in place to the cold plate via this mounting structure.
[0027] FIG. 10 is a flow chart illustrating a method for constructing a multi-chip module according to an embodiment of the present disclosure. The method 1000 begins with mounting a plurality of IC dies onto a first surface of an InFO substrate (step 1004). Then, the IC dies are encapsulated (step 1006). Then, two differing steps may be taken based upon an embodiment chosen. With a first embodiment, floating frames are attached to the InFO substrate (step 1008). With a second embodiment, frame over molded sockets are attached to the second surface of the InFO substrate (step 1010). Then, a back plate is installed (step 1012). Next, a thermal interface module is installed onto the encapsulated IC dies (step 1014). Then, a cold plate is installed onto the thermal interface module (step 1016). Finally, the VRM modules are installed into the sockets (step 1018). Drilling of holes into the laminated structure, tapping the holes, securing the sockets with screws, and securing the VRM modules may be performed at various points during the method 1000.
[0028] FIG. 11 is a partial sectional side view illustrating a multi-chip module according to another embodiment of the present disclosure. The structure of FIG. 11 may be accomplished using the method 1000 of FIG. 10.
[0029] The system and methods above has been described in general terms as an aid to understanding details of preferred embodiments of the present invention. Other preferred embodiments of the present include the described application for electric vehicles. In the description herein, numerous specific details are provided, such as examples of components and/or methods, to provide a thorough understanding of embodiments of the present invention. One skilled in the relevant art will recognize, however, that an embodiment of the invention can be practiced without one or more of the specific details, or with other apparatus, systems, assemblies, methods, components, materials, parts, and/or the like. In other instances, well- known structures, materials, or operations are not specifically shown or described in detail to avoid obscuring aspects of embodiments of the present invention.
[0030] Reference throughout this specification to "one embodiment", "an embodiment", or "a specific embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention and not necessarily in all embodiments. Thus, respective appearances of the phrases "in one embodiment", "in an embodiment", or "in a specific embodiment" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics of any specific embodiment of the present invention may be combined in any suitable manner with one or more other embodiments. It is to be understood that other variations and modifications of the embodiments of the present invention described and illustrated herein are possible in light of the teachings herein and are to be considered as part of the spirit and scope of the present invention.
[0031] It will also be appreciated that one or more of the elements depicted in the drawings/figures can also be implemented in a more separated or integrated manner, or even removed or rendered as inoperable in certain cases, as is useful in accordance with a particular application.
[0032] Additionally, any signal arrows in the drawings/Figures should be considered only as exemplary, and not limiting, unless otherwise specifically noted. Furthermore, the term "or" as used herein is generally intended to mean "and/or" unless otherwise indicated. Combinations of components or steps will also be considered as being noted, where terminology is foreseen as rendering the ability to separate or combine is unclear.
[0034] The foregoing description of illustrated embodiments of the present invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention, as those skilled in the relevant art will recognize and appreciate. As indicated, these modifications may be made to the present invention in light of the foregoing description of illustrated embodiments of the present invention and are to be included within the spirit and scope of the present invention.
[0035] Thus, while the present invention has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes and substitutions are intended in the foregoing disclosures, and it will be appreciated that in some instances some features of embodiments of the invention will be employed without a corresponding use of other features without departing from the scope and spirit of the invention as set forth. Therefore, many modifications may be made to adapt a particular situation or material to the essential scope and spirit of the present invention. It is intended that the invention not be limited to the particular terms used in following claims and/or to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include any and all embodiments and equivalents falling within the scope of the appended claims. Thus, the scope of the invention is to be determined solely by the appended claims.

中文:
[0001]本发明总体上涉及电子装置,并且更具体地涉及多芯片模块。
[0002]多芯片计算机系统通常已知包括多个集成电路(IC)裸片,这些集成电路裸片通常被封装以支持高性能处理系统。在一些多芯片模块中,多个IC被安装在具有支持互连和冷却系统的阵列中。这种多芯片模块的结构可以包括多个部件,多个部件被层压到多个具有集成扇出(InFO)基底的层中,该集成扇出基底提供安装到其上的多个IC之间的信号连接。虽然InFO基底为安装在其上的多个IC裸片的信号连通性提供了效率,但是对于它所服务的多芯片计算机系统来说也有缺点。因为InFO基底可以具有与多芯片模块的其它部件不同的基于温度的膨胀特性,当多芯片模块的温度随时间变化时,InFO基底可以因基底的变化的膨胀而翘曲、拉伸、收缩或损坏。此外,在某些情况下,从使用InFo基底的多芯片模块中排除大量的热可以是困难的。
[0003]一个实施例是多芯片模块,其包括:重布线层(RDL)基底;第一多个集成电路(IC)裸片,被安装至RDL基底的第一表面;第二多个IC裸片,被安装至相背的第二表面;多个插座,被安装到第二多个IC裸片上;冷板,被安装至第一多个IC裸片;以及安装结构。在该实施例中,安装结构可以包括:多个插座框架,耦接至多个插座;多个孔,穿过RDL基底被形成;多个螺丝钉,从多个插座框架延伸穿过多个孔并且被旋拧至冷板中,多个孔穿过RDL基底被形成。
[0004]另一个实施例是将多芯片模块安装至基底的方法。方法可以包括:将多个集成电路裸片安装到重布线层的第一表面;封装经安装的集成电路裸片;在重布线层上,将浮动框架或模制插座、或将浮动框架和模制插座两者附接到集成电路上;将热接口模块安装到封装的IC裸片上;并且将冷板安置到热接口模块上。
[0005]图1是示出根据本公开而构造的多芯片模块的一个实施例的截面侧视图框架图。
[0006]图2是根据本公开的一个实施例的图1的多芯片模块的立体图。
[0007]图3是图2的多芯片模块的放大部分的局部立体图。
[0008]图4是图3的多芯片模块的部分的截面侧视图。
[0009]图5是图3的示出了负载框架的细节的多芯片模块的部分的截面侧视图。
[0010]图6是根据本公开的一个实施例的多芯片模块的多IC负载框架的插座的俯视图。
[0011]图7是图6的多IC负载框架的插座的截面侧视图。
[0012]图8是安装至图6的多IC负载框架的插座结构中的电压调节器模块(VRM)的俯视图。
[0013]图9是图8的VRM和多IC负载框架的局部截面侧视图。
[0014]图10是示出根据本公开的一个实施例的用于构建多芯片模块的方法的流程图。
[0015]图11是示出根据本公开的另一实施例的多芯片模块的局部截面侧视图。
[0018]图1是示出了根据本公开构建的多芯片模块100的截面侧视图。图1的多芯片模块包括安装在基底结构104上的多个高功率电压调节模块(VRM)102A、102B、102C、102D。多个高功率VRM 102A、102B、102C、102D由DC电源供应电压108,例如40伏、48伏或另外的相关电压,并且相应地服务于相应的多个集成电路(IC)裸片106A、106B、106C和106D。在一些实施例中,多个高功率VRM 102A、102B、102C、102D中的每个高功率VRM产生大约0.8伏的输出,并且将600瓦或更多的功率提供给相应的IC裸片106A、106B、106C和106D。因此,多个电路板高功率VRM 102A、102B、102C、102D中的每个电路板高功率VRM产生超过100安培的到多个IC裸片106A、106B、106C和106D的电流。
[0019]图2是根据本公开的一个实施例的图1的多芯片模块的一部分200的立体图。所示出的是集成扇出(InFO)基底202,在集成扇出基底上安装有多个嵌入式电容器结构(嵌入式CAP)204。虽然InFO基底的其他厚度也在本公开的范围内,InFO基底202可以在集成电路制造过程中被形成并且具有大约0.1mm的厚度。InFO基底202可以由硅形成并且针对嵌入式cap 204中的每个嵌入式cap,包括在嵌入式CAP 204与安装在InFO基底202的相背的表面的对应IC裸片之间的信号路由连接。如将在图3中示出的,根据本发明的一个实施例,示出了模块化的直接钳位结构206,用于将多个插座208安装至嵌入式CAP 204上,使得多个插座208机械地耦接到安装在InFO基底202的相背侧上的冷板。
[0020]图3是图2的多芯片模块的放大部分的局部立体图。详细示出的是服务于多芯片模块100的模块化的直接钳位结构206中的一个直接钳位结构。模块化的直接钳位结构206包括插座框架302,插座框架为安装在其中的四个插座208、角钳位304和螺丝钉306提供了机械安装结构。螺丝钉延伸穿过InFO基底202并且被固定在针对多芯片模块的冷却结构内。
[0021]图4是图3的多芯片模块的部分的截面侧视图。图4的截面侧视图详细地示出了模块化的钳位结构206及其安装至冷却结构的细节。冷却装置包括冷板406,其安装在全局歧管结构408上。IC裸片412安装在InFO基底202上。螺丝钉306与成型在全局歧管结构408上的螺纹接合。示出了安装至插座208的插头402以及安装在插头上的壳体404。在一些实施例中,壳体404可以容纳VRM。
[0022]图5是图3的多芯片模块的部分的截面侧视图,示出了沿着图4的区段410截取的负载框架的细节。图5示出了之前在图4中示出的部件,并且具有更多的细节。应注意的是,InFO基底202提供了服务于在IC裸片412与嵌入式CAP 204之间的互连的一个或多个重布线层(RDL)。利用图5的结构,示出了钻透InFO基底202的孔。这些孔可以被机械地形成或经由激光成型。冷板406(以及全局歧管结构408)用作结构性的背板并且为InFO基底202提供了充分的刚度,以确保InFO基底202不会因不平衡的机械负载而受损。钳位机构为构件提供了足够的移动性,以防止在热膨胀和/或收缩期间的开裂。
[0023]图6是根据本公开的一个实施例的多IC负载框架的插座结构600的俯视图。插座结构600包括负载框架602,负载框架具有被形成/安装在其中的多个插座604。螺丝钉/垫圈606将插座结构600固定至冷板。尽管示出了以2x2阵列形式的四个插座604,但是都可以插座提供NxM的任何阵列的插座结构,其中N和M为整数。
[0024]图7是图6的多IC负载框架的插座的截面侧视图。示出了被金属负载框架604包围的嵌件模制LCP插座604,它们两者都耦接至嵌入式cap 204。
[0025]图8是安装至图6的多IC负载框架的插座结构中的电压调节器模块(VRM)的俯视图。VRM 802经由合适的电气连接804安装到插座604中。
[0026]图9是图8的VRM和多IC负载框架的局部截面侧视图。VRM 802经由合适的电连接604安装至插座604中。VRM螺丝钉和VRM垫圈经由插座螺丝钉和VRM螺母/插座耦接至冷板。应注意的是,整个结构经由该安装结构垂直地保持在冷板上。
[0027]图10是示出根据本公开的一个实施例的用于构建多芯片模块的方法的流程图。方法1000以将多个IC裸片安装至InFO基底的第一表面上(步骤1004)开始。然后封装IC裸片(步骤1006)。然后,基于所选择的实施例,可以执行两个不同的步骤。在第一实施例中,将浮动框架附接至InFO基底(步骤1008)。在第二实施例中,在模制插座上方,将框架附接至InFO基底的第二表面(步骤1010)。然后,安置背板(步骤1012)。接着,将热接口模块安置到经封装的IC裸片上(步骤1014)。然后,将冷板安置到热接口模块上(步骤1016)。最后,将VRM模块安置到插座中(步骤1018)。在方法1000期间在多个点处可以执行:在层压的结构中钻孔、为孔攻丝、利用螺丝钉固定插座以及固定VRM模块。
[0028]图11是示出根据本公开的另一实施例的多芯片模块的局部截面侧视图。图11的结构可以使用图10的方法1000来实现。
[0029]以上的系统和方法已经以一般术语进行了描述,以作为对理解本发明的优选实施例的细节的帮助。本发明的其它优选实施例包括针对电动车辆描述的应用。在本文的描述中,提供了许多具体细节,例如部件和/或方法的示例,以提供对本发明实施例的透彻理解。然而,相关领域的技术人员将认识到,本发明的实施例可以在没有一个或多个具体细节的情况下实施,或者可以使用其他装置、系统、组装件、方法、部件、材料、零件和/或等等来实施。在其它实例中,未具体示出或详细描述公知的结构、材料或操作,以避免使本发明实施例的方面模糊。
[0030]在本说明书中对“一个实施例”、“实施例”或“特定实施例”的引用意指,结合该实施例描述的特定特征、结构或特性包括在本发明的至少一个实施例中,而不一定包括在所有实施例中。因此,在本说明书的各个地方出现的短语“在一个实施例中”、“在实施例中”或“在一个特定实施例中”不一定是指同一实施例。此外,本发明的任何特定实施例的特定特征、结构或特性可以以任何合适的方式与一个或多个其它实施例组合。应当理解,根据这里的教导,这里描述和图示的本发明的实施例的其它变化和修改是可能的,并且将被认为是本发明的精神和范围的一部分。
[0031]还将理解,附图/图中描绘的元件中的一个或多个元件也可以以更分离或集成的方式实现,或者甚至在某些情况下移除或使其不可操作,这根据特定应用是有用的。
[0032]此外,除非另有特别说明,附图/图中的任何信号箭头应被认为仅是示例性的,而不是限制性的。此外,除非另有指示,本文所使用的术语“或”一般意在表示“和/或”。部件或步骤的组合也将被认为已被说明,其中术语被预见为使分离或组合的能力不清楚。
[0034]对本发明的图示实施例的前述描述,包括在摘要中描述的内容,并不意在穷尽或将本发明限制于本文公开的精确形式。虽然在此描述本发明的具体实施例和示例仅出于说明目的,但是如相关领域的技术人员将认识到和理解的,在本发明的精神和范围内,各种等同的修改是可行的。如所指示的,可以根据对本发明的图示实施例的前述描述对本发明进行这些修改,并且这些修改将被包括在本发明的精神和范围内。
[0035]因此,虽然在此已经参照本发明的特定实施例描述了本发明,但是在前述公开内容中意图有修改的范围、各种变化和替换,并且应理解,在一些情况下,将采用本发明实施例的一些特征,而不相应地使用其他特征,而不脱离所阐述的本发明的范围和精神。因此,可以进行许多修改以使特定情况或材料适应本发明的基本范围和精神。希望本发明不限于随附的权利要求书中使用的特定术语和/或公开为实施本发明的最佳模式的特定实施例,而是本发明将包括落在所附权利要求书范围内的任何和所有实施例和等同物。因此,本发明的范围仅由所附权利要求书确定。