English:
[0001] NPN transistors have two N type regions surrounding a P type region. One of the N type regions is the collector, the P type region is the base, and the second one of the N type regions is the emitter. Depending upon how the NPN transistor is voltage biased, the NPN transistor will have a different mode of operation. When the emitter-base junction is reverse biased and the collector-base junction is reverse biased, the NPN transistor operates in a cutoff mode. When the emitter-base junction is forward biased and the collector-base junction is reverse biased, the NPN transistor operates in an active mode, and when the emitter-base junction is forward biased and the collector-base junction is forward biased, the NPN transistor operates in the saturation mode. The active mode is used when the transistor is to be used as an amplifier, and the cutoff mode and the saturation mode are used when the transistor is to be used as a switch.
[0002] One parameter of an NPN transistor is the common-emitter current gain, which is often known as β or HFE- When in the active mode, the common-emitter current gain is the ratio of the collector current over the base current. For an example NPN transistor, the common-emitter current gain may be in the range of 50 to 200. For an example super-beta NPN (SBNPN) transistor, the common-emitter current gain may be 1,000 or more.
[0003] Described examples include a method for making an SBNPN transistor that comprises depositing a tetraethyl orthosilicate (TEOS) layer on a P type epitaxial layer, and depositing a nitride layer on the TEOS layer. An emitter region of the SBNPN transistor is patterned by selectively etching away portions of the nitride layer and the TEOS layer. A second TEOS layer is deposited on top of the nitride layer, along sides of the nitride layer and the TEOS layer, and on top of the P type epitaxial layer. The P type epitaxial layer is implanted through the second TEOS layer with N type ions to form the emitter region of the SBNPN transistor.
[0005] Yet another example includes an SBNPN transistor that comprises a base, an emitter, and a collector. The emitter comprises a nitride layer and a first TEOS layer on top of a P type epitaxial layer. The second TEOS layer is deposited on the nitride layer and the first TEOS layer. The second TEOS layer fills in undercut regions of the nitride layer and the first TEOS layer, and the second TEOS layer comprises a homogenous screen oxide for an emitter implant step.
[0006] FIG. 1 shows a cross-sectional view of an SBNPN transistor in accordance with various examples.
[0007] FIG. 2 shows a top-down view of an SBNPN transistor in accordance with various examples.
[0008] FIGS. 3-10 show cross-sectional views of an SBNPN transistor being manufactured in accordance with various examples.
[0009] FIG. 11 shows a process flowchart of a method of manufacturing an emitter region of an SBNPN transistor in accordance with various examples.
[0010] In this description, the term "couple" or "couples" means either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections.
[0011] When manufacturing SBNPN transistors, the common-emitter current gain can vary within a wafer, can vary from wafer-to-wafer, and can vary from lot-to-lot. Ideally, this variation would be reduced to a minimum, such that SBNPN transistors with consistent and predictable common-emitter current gains could be produced. Example embodiments include SBNPN transistors and methods of making SBNPN transistors that produce SBNPN transistors with more consistent and predictable common-emitter current gains. In one example, an existing oxide layer is removed, and a new oxide layer is deposited that provides better uniformity in the subsequent emitter ion implant step than at least some conventional SBNPN transistors. The better uniformity in the subsequent emitter ion implant step results in reduced variation of the common-emitter current gain variation within a wafer, from wafer-to-wafer, and from lot-to-lot.
[0012] FIG. 1 shows a cross-sectional view of one embodiment of an SBNPN transistor 100 in accordance with the described embodiments. Although examples herein include SBNPN transistors and associated methods, the embodiments are not limited to any particular type of transistor and may be practiced in other types of transistors. SBNPN transistor 100 in FIG. 1 has one or more base terminals 102, one or more collector terminals 104, and one or more emitter terminals 106. The one or more base terminals 102, the one or more collector terminals 104, and the one or more emitter terminals 106 may be used as connections for electrical signals for the SBNPN transistor 100. The SBNPN transistor 100 is supported by a buried oxide layer 108. The buried oxide layer 108 works along with one or more isolation trenches 110 to electrically isolate the SBNPN transistor 100. For example, the buried oxide layer 108 electrically isolates the SBNPN transistor 100 from adjacent SBNPN transistors and other devices which may be formed on the same wafer as SBNPN 100.
[0013] In some embodiments, the base portion of the SBNPN transistor comprises the base terminal 102 and a P type epitaxial layer 111. The collector portion of the SBNPN transistor may comprise the collector terminal 104 and a plurality of N type regions. The plurality of N type regions of the collector portion includes a vertical N type channel 112, a horizontal N type channel 114, and an N type epitaxial layer 118. Thus, in the example of FIG. 1, the plurality of N type regions forming part of the collector portion includes three N type regions. The emitter portion of the SBNPN transistor comprises the emitter terminal 106, a polysilicon structure 120, and an N type emitter region 122.
[0014] FIG. 2 shows a top-down view of the SBNPN transistor 100 of FIG. 1. In the example shown in FIG. 2, SBNPN transistor 100 has sixteen base terminals 102, seven collector terminals 104, and one elongated emitter terminal 106. However, embodiments are not limited to any particular number of terminals, shape of terminals, or size of terminals. Also, embodiments may have a different number of terminals, different shapes of terminals, and different sizes of terminals from what is shown in FIG. 2.
[0016] In FIG. 4, a layer of photoresist 402 is applied to the top of the nitride layer 306, and the layer of photoresist 402 is patterned to form the area that will become the emitter of the SBNPN transistor. For example, the entire surface of the nitride layer 306 is applied with photoresist. A photomask is then used to selectively shine light on areas of the photoresist, and a developing solution is used to remove the unwanted photoresist. The openings in the photoresist will be used to etch away material to form the emitter.
[0017] In FIG. 5, the nitride layer 306 and a portion of the TEOS layer 304 that are not covered by the photoresist layer 402 are etched away. The TEOS layer 304 is etched away such that about
[0018] In FIG. 6, the photoresist layer 402 from FIGS. 4-5 is first removed. In one embodiment, the photoresist layer 402 is removed by first performing a plasma ashing step and then performing a wet etch (e.g., an H2SO4and H202wet etch) to remove any remaining photoresist. After the photoresist layer 402 is removed, another wet etch is performed to remove the exposed TEOS layer 304 in the emitter region. For example, a hydrofluoric acid (HF) wet etch may be performed. However, embodiments are not limited to any particular type of etch to remove the exposed TEOS layer 304.
[0019] In the example of FIG. 7, a second TEOS layer 702 is deposited over the top of the nitride layer 306, along the sides of nitride layer 306, TEOS layer 304, and screen oxide layer 302, and over the top of the exposed P type epitaxial layer 308. In an embodiment, the second TEOS layer 702 is about 2-8 nm and may be deposited using a low temperature (e.g., 640 degrees Celsius), low deposition rate process. The second TEOS layer 702 illustratively performs two functions. First, the second TEOS layer 702 acts as a homogenous screen oxide for the subsequent emitter implant step. Second, the second TEOS layer 702 acts to refill any undercut of the nitride layer 306, TEOS layer 304, and screen oxide layer 302 that occurs due to the above-described wet etch that removes the exposed TEOS layer 304.
[0020] In FIG. 8, a second layer of photoresist 802 is applied to the top of the second TEOS layer 702. The layer of photoresist 802 is patterned to expose the portions of SBNPN transistor that will receive the emitter implant step and to protect the portions of the SBNPN transistor that will be blocked from receiving the emitter implant step.
[0021] In FIG. 9, the emitter implant step is performed. N type ions 902 (e.g., arsenic ions) are projected onto the SBNPN transistor. The exposed areas that include the areas where the second TEOS layer 702 covers the P type epitaxial layer 308 receive the implant. The second TEOS layer 702 acts as a screen oxide layer allowing the N type ions 902 to pass through and penetrate the P type epitaxial layer 308. This forms an N type region 904 that acts as the emitter.
[0022] In FIG. 10, the layer of photoresist 802 from FIGS. 8-9 is removed. In one embodiment, the layer of photoresist 802 is removed by performing a plasma ashing step and then performing a wet etch (e.g., an H2S04and H202wet etch) to remove any remaining photoresist. After the layer of photoresist 802 is removed, another wet etch may be performed to remove the exposed TEOS layer 702 in the emitter region. Embodiments are not limited to any particular type of etch to remove the exposed TEOS layer 304 and include any etch that removes the exposed TEOS layer 304.
[0023] FIG. 11 shows a process flowchart of a method of manufacturing an emitter region of an SBNPN transistor according to one embodiment. At block 1102, a screen oxide layer, a TEOS layer, and a nitride layer are deposited on a P type epitaxial layer. At block 1104, a layer of photoresist is deposited on the nitride layer and is patterned for the emitter region. At block 1106, the areas of the nitride layer that are not covered by photoresist are etched away and a thin film of oxide (e.g., 50 - 105 A) is left covering the P type epitaxial layer. At block 1108, the layer of photoresist is removed and the thin film of oxide is etched away. At block 1110, a second TEOS layer is deposited. The second TEOS layer acts as a homogenous screen oxide for the subsequent emitter implant step, and the second TEOS layer acts to refill any undercut of the nitride layer, the first TEOS layer, and the screen oxide layer. At block 1112, a second layer of photoresist is deposited on the second TEOS layer and is patterned for the emitter implant. At block 1114, the emitter implant is performed to form the emitter N type region. At block 1116, the second layer of photoresist is removed and the thin film of oxide in the emitter region is etched away. At block
[0024] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

中文:
[0001]NPN晶体管具有围绕P型区域的两个N型区域。N型区域中的一个是集电极,P型区域是基极以及N型区域中的第二个是发射极。根据NPN晶体管的电压偏置方式,NPN晶体管将具有不同的操作模式。当发射极-基极结被反向偏置并且集电极-基极结被反向偏置时,NPN晶体管以截止模式操作。当发射极-基极结被正向偏置且集电极-基极结被反向偏置时,NPN晶体管以有源模式操作,以及当发射极-基极结被正向偏置且集电极-基极结被正向偏置时,NPN晶体管以饱和模式操作。当晶体管用作放大器时使用有源模式,以及当晶体管用作开关时使用截止模式和饱和模式。
[0002]NPN晶体管的一个参数是共发射极电流增益,其通常被称为β或HFE。当处于有源模式时,共发射极电流增益是集电极电流与基极电流的比率。对于示例NPN晶体管,共发射极电流增益可以在50到200的范围内。对于示例超βNPN(SBNPN)晶体管,共发射极电流增益可以是1,000或更大。
[0003]所描述的示例包括一种用于制造SBNPN晶体管的方法,该方法包括在P型外延层上沉积正硅酸乙酯(TEOS)层,以及在TEOS层上沉积氮化物层。通过选择性地蚀刻掉部分氮化物层和TEOS层来图案化SBNPN晶体管的发射极区域。在氮化物层的顶部、沿着氮化物层和TEOS层的侧面以及在P型外延层的顶部上沉积第二TEOS层。通过第二TEOS层利用N型离子注入P型外延层,以形成SBNPN晶体管的发射极区域。
[0005]又一示例包括一种SBNPN晶体管,其包括基极、发射极和集电极。发射极包括在P型外延层顶部上的氮化物层和第一TEOS层。第二TEOS层沉积在氮化物层和第一TEOS层上。第二TEOS层在氮化物层和第一TEOS层的底切(undercut)区域中填充,并且第二TEOS层包括用于发射极注入步骤的同质屏蔽氧化物。
[0006]图1示出了根据各种示例的SBNPN晶体管的横截面图。
[0007]图2示出了根据各种示例的SBNPN晶体管的俯视图。
[0008]图3-图10示出了根据各种示例制造的SBNPN晶体管的横截面图。
[0009]图11示出了根据各种示例的一种制造SBNPN晶体管的发射极区域的方法的工艺流程图。
[0010]在本说明书中,术语“耦合(couple或couples)”表示间接或直接有线或无线连接。因此,如果第一设备耦合到第二设备,则该连接可以通过直接连接或通过经由其他设备和连接的间接连接。
[0011]当制造SBNPN晶体管时,共发射极电流增益可以在晶片内变化,可以从晶片到晶片变化,并且可以从批次到批次变化。理想地,这种变化将被减小到最小,使得可以产生具有一致且可预测的共发射极电流增益的SBNPN晶体管。示例实施例包括SBNPN晶体管和制造SBNPN晶体管的方法,所述方法产生具有更一致且可预测的共发射极电流增益的SBNPN晶体管。在一个示例中,去除现有的氧化物层,并且沉积新的氧化物层,其在随后的发射极离子注入步骤中提供比至少一些传统的SBNPN晶体管更好的均匀性。随后的发射极离子注入步骤中的更好的均匀性导致晶片内、晶片到晶片以及批次到批次的共发射极电流增益变化的变化减小。
[0012]图1示出了根据所描述实施例的SBNPN晶体管100的一个实施例的横截面图。尽管本文中的示例包括SBNPN晶体管和相关联方法,但是实施例不限于任何特定类型的晶体管,并且可以在其他类型的晶体管中实施。图1中的SBNPN晶体管100具有一个或更多个基极端子102、一个或更多个集电极端子104以及一个或更多个发射极端子106。一个或更多个基极端子102、一个或更多个集电极端子104以及一个或更多个发射极端子106可以用作针对SBNPN晶体管100的电信号的连接。SBNPN晶体管100由掩埋氧化物层108支撑。掩埋氧化物层108与一个或更多个隔离沟槽110一起工作以电隔离SBNPN晶体管100。例如,掩埋氧化物层108将SBNPN晶体管100与相邻的SBNPN晶体管和可以与SBNPN 100形成在同一晶片上的其他器件电隔离。
[0013]在一些实施例中,SBNPN晶体管的基极部分包括基极端子102和P型外延层111。SBNPN晶体管的集电极部分可以包括集电极端子104和多个N型区域。集电极部分的多个N型区域包括垂直N型沟道112、水平N型沟道114和N型外延层118。因此,在图1的示例中,形成部分的集电极部分的多个N型区域包括三个N型区域。SBNPN晶体管的发射极部分包括发射极端子106、多晶硅结构120和N型发射极区域122。
[0014]图2示出了图1的SBNPN晶体管100的俯视图。在图2所示的示例中,SBNPN晶体管100具有十六个基极端子102、七个集电极端子104和一个细长的发射极端子106。然而,实施例不限于任何特定数量的端子、端子的形状或端子的尺寸。而且,实施例可以具有与图2中所示的不同数量的端子、不同形状的端子以及不同尺寸的端子。
[0016]在图4中,将光刻胶层402施加到氮化物层306的顶部,并且图案化光刻胶层402以形成将成为SBNPN晶体管的发射极的区。例如,氮化物层306的整个表面涂有光刻胶。然后使用光掩模选择性地将光照射在光刻胶的区上,并使用显影溶液去除不需要的光刻胶。光刻胶中的开口将用于蚀刻掉材料以形成发射极。
[0017]在图5中,蚀刻掉未被光刻胶层402覆盖的氮化物层306和TEOS层304的一部分。TEOS层304被蚀刻掉,使得留下大约3-12nm的TEOS层304。
[0018]在图6中,来自图4-图5的光刻胶层402首先被去除。在一个实施例中,通过首先执行等离子体灰化步骤然后执行湿法蚀刻(例如,H2SO4和H2O2湿法蚀刻)以去除任何剩余的光刻胶来去除光刻胶层402。在去除光刻胶层402之后,执行另一次湿法蚀刻以去除发射极区域中的暴露的TEOS层304。例如,可以执行氢氟酸(HF)湿法蚀刻。然而,实施例不限于任何特定类型的蚀刻以去除暴露的TEOS层304。
[0019]在图7的示例中,在氮化物层306的顶部上方,沿着氮化物层306、TEOS层304和屏蔽氧化物层302的侧面,以及在暴露的P型外延层308的顶部上方沉积第二TEOS层702。在一个实施例中,第二TEOS层702为约2-8nm并且可以使用低温(例如,640摄氏度)、低沉积速率工艺来沉积。第二TEOS层702说明性地执行两个功能。第一,第二TEOS层702用作随后的发射极注入步骤的同质屏蔽氧化物。第二,第二TEOS层702用于重新填充由于上述用于去除暴露的TEOS层304的湿法蚀刻而发生的氮化物层306、TEOS层304和屏蔽氧化物层302的任何底切。
[0020]在图8中,第二光刻胶层802被施加到第二TEOS层702的顶部。光刻胶层802被图案化以暴露将接收发射极注入步骤的SBNPN晶体管的部分并且保护将被阻止接收发射极注入步骤的SBNPN晶体管的部分。
[0021]在图9中,执行发射极注入步骤。N型离子902(例如,砷离子)被投射到SBNPN晶体管上。包括第二TEOS层702覆盖P型外延层308的区的暴露区接收注入。第二TEOS层702用作屏蔽氧化物层,允许N型离子902穿过并穿透P型外延层308。这形成用作发射极的N型区域904。
[0022]在图10中,来自图8-图9的光刻胶层802被去除。在一个实施例中,通过执行等离子体灰化步骤然后执行湿法蚀刻(例如,H2SO4和H2O2湿法蚀刻)以去除任何剩余的光刻胶来去除光刻胶层802。在去除光刻胶层802之后,可以执行另一次湿法蚀刻以去除发射极区域中的暴露的TEOS层702。实施例不限于任何特定类型的蚀刻以去除暴露的TEOS层304,并且包括去除暴露的TEOS层304的任何蚀刻。
[0023]图11示出了根据一个实施例的一种制造SBNPN晶体管的发射极区域的方法的工艺流程图。在框1102处,在P型外延层上沉积屏蔽氧化物层、TEOS层和氮化物层。在框1104处,在氮化物层上沉积光刻胶层,并将该光刻胶层图案化以用于发射极区域。在框1106处,蚀刻掉未被光刻胶覆盖的氮化物层的区,并留下覆盖P型外延层的氧化物薄膜(例如,50-105A)。在框1108处,去除光刻胶层并蚀刻掉氧化物薄膜。在框1110处,沉积第二TEOS层。第二TEOS层用作随后的发射极注入步骤的同质屏蔽氧化物,以及第二TEOS层用于重新填充氮化物层、第一TEOS层和屏蔽氧化物层的任何底切。在框1112处,在第二TEOS层上沉积第二光刻胶层并且将该第二光刻胶层图案化以用于发射极注入。在框1114处,执行发射极注入以形成发射极N型区域。在框1116处,去除第二光刻胶层并蚀刻掉发射极区域中的氧化物薄膜。在框1118处,沉积发射极多晶硅以形成多晶硅结构(例如,图1中的多晶硅结构120)。
[0024]在所描述的实施例中,修改是可能的,并且在权利要求的范围内,其他实施例也是可能的。