English:
[0001] Aspects of this disclosure pertain to operations involving two or more vectors where data elements of at least one vector are of a different bit-width than data elements of at least one other vector. Such operations are referred to as mixed- width operations. More specifically, some aspects relate to mixed-width single instruction multiple data (SIMD) operations involving at least a first vector operand and a second vector operand where at least one of the first or second vector operands have data elements which may be stored in even or odd register pairs.
[0002] Single instruction multiple data (SIMD) instructions may be used in processing systems for exploiting data parallelism. Data parallelism exists when a same or common task needs to be performed on two or more data elements of a data vector, for example. Rather than use multiple instructions, the common task may be performed on the two or more data elements in parallel by using a single SIMD instruction which defines the same instruction to be performed on multiple data elements in corresponding multiple SIMD lanes.
[0003] SIMD instructions may include one or more vector operands such as source and destination vector operands. Each vector operand would include two or more data elements. For SIMD instructions, all data elements belonging to the same vector operand may generally be of the same bit-width. However, some SIMD instructions may specify mixed-width operands where data elements of a first vector operand may be of a first bit-width and data elements of a second vector operand may be of a second bit-width, where the first and second bit-widths differ from each other. Execution of SIMD instructions with mixed-width operands may involve several challenges.
[0004] FIGS. 1A-C illustrate examples of challenges involved in conventional implementations for executing SIMD instructions with mixed-width operands. With reference to FIG. 1A, a first conventional implementation for executing SIMD instruction 100 is illustrated. It is assumed that SIMD instruction 100 may be executed by a conventional processor (not shown) which supports a 64-bit instruction set architecture (ISA). This means that instructions such as SIMD instruction 100 may specify operands with bit- widths up to 64-bits. The 64-bit operands may be specified in terms of 64-bit registers or a pair of 32-bit registers.
[0005] The object of SIMD instruction 100 is to execute the same instruction on each data element of source operand 102. Source operand 102 is a 64-bit vector comprising eight 8-bit data elements labeled 0-7. Source operand 102 may be stored in a single 64-bit register or a pair of 32-bit registers. The same instruction or common operation to be executed on each of the eight data elements 0-7 may be, for example, multiplication, square function, left-shit function, increment function, addition (e.g., with a constant value or immediate fields in the instruction or with values provided by another vector operand), etc., the result of which may consume more than 8-bits, and up to 16-bits of storage for each of the eight resulting data elements. This means that the result of SIMD instruction 100 may consume twice the storage space that source operand 102 may consume, i.e., two 64-bit registers or two pairs of 32-bit registers.
[0006] Since the conventional processor configured to implement SIMD instruction 100 does not include instructions which specify operands of bit-widths greater than 64-bits, SIMD instruction 100 may be divided into two component SIMD instructions 100X and 100Y. SIMD instruction 100X specifies the common operation to be performed on data elements labeled with even-numbers (or "even-numbered data elements") 0, 2, 4, and 6 of source operand 102. SIMD instruction 100X specifies destination operand 104x which is 64-bits wide and includes 16-bit data elements labeled A, C, E, and G, each of which i composed of high (H) 8-bits and low (L) 8-bits. The results of the common operation on even-numbered 8-bit data elements 0, 2, 4, and 6 of source operand 102 are correspondingly written to 16-bit data elements A, C, E, and G of destination operand 104x. SIMD instruction 100Y is similar to SIMD instruction 100X with the difference that SIMD instruction 100Y specifies the common operation on data elements labeled with odd-numbers (or "odd-numbered data elements") 1, 3, 5, and 7 of source operand 102 with the results to be written to 16-bit data elements B, D, F, H of destination operand 104y which is also a 64-bit operand similar to destination operand 104x of SIMD instruction 100X. In this manner, each of the SIMD instructions 100X and 100Y can specify one 64-bit destination operand, and together, SIMD instructions 100X and 100Y can accomplish the execution of the common operation on each of the data elements 0-7 of source operand 102. However, due to the two separate instructions needed to implement SIMD instruction 100 increases code space.
[0007] FIG. IB illustrates a second conventional implementation of SIMD instruction 100 using a different set of component SIMD instructions 120X and 120Y. SIMD instructions 120X and 120Y each specify the common operation on each of the 8-bit data elements 0-7 of source operand 102. SIMD instruction 120X specifies destination operand 124x into which the low (L) 8-bits of the results are to be written, to corresponding 8-bit result data elements A-H of destination operand 124x (while the high (H) 8-bits of the results are discarded). Similarly, instruction 120Y specifies destination operand 124y into which the high (H) 8-bits of the results are to be written, to corresponding 8-bit data elements A-H of destination operand 124y (while the low (L) 8-bits of the results are discarded). This second conventional implementation of SIMD instruction 100 also suffers from increased code space for the two component SIMD instructions 120X and 120Y. Moreover, as can be appreciated, the second conventional implementation also incurs wastage of power in calculating and discarding either the high (H) 8-bits (e.g., in executing instruction 120X) or the low (L) 8-bits (e.g., in executing instruction 120Y) for each of the data elements 0-7 of source operand 102.
[0008] FIG. 1C illustrates a third conventional implementation of SIMD instruction 100 using yet another set of component SIMD instructions 140X and 140Y, which are similar in some ways to SIMD instructions 100X and 100Y of FIG. 1A. The difference lies in which ones of the data elements of source operand 102 are operated on by each SIMD instruction. In more detail, rather than even-numbered 8-bit data elements, SIMD instruction 140X specifies the common operation to be performed on the lower four data elements 0-3 of source operand 102. The results are written to 16-bit data elements A, B, C, D of destination operand 144x. However, execution of SIMD instruction 140X involves the spreading out of the results of the operation on the lower four 8-bit data elements (spanning 32 bits) across all 64-bits of destination operand 140X. SIMD instruction 144y is similar and specifies the spreading out of the results of operation on the upper four 8-bit data elements 4-7 of source operand 102 across 16-bit data elements E, F, G, H of 64-bit destination operand 144y. Apart from increased code size as in the first and second conventional implementations, these spreading out data movements as seen in the third conventional implementation may need additional hardware such as a crossbar.
[0009] Accordingly, there is a need for improved implementations of mixed-width SIMD instructions which avoid the aforementioned drawbacks of the conventional implementations.
[0010] Exemplary aspects include systems and methods related to a mixed-width single instruction multiple data (SIMD) instruction which has at least a source vector operand comprising data elements of a first bit-width and a destination vector operand comprising data elements of a second bit-width, wherein the second bit-width is either half of or twice the first bit-width. Correspondingly, one of the source or destination vector operands is expressed as a pair of registers, a first register and a second register. The other vector operand is expressed as a single register. Data elements of the first register correspond to even-numbered data elements of the other vector operand expressed as a single register, and data elements of the second register correspond to data elements of the other vector operand expressed as a single register.
[0011] For example, an exemplary aspect relates to a method of performing a mixed-width single instruction multiple data (SIMD) operation, the method comprising: receiving, by a processor, a SIMD instruction comprising at least a first source vector operand comprising a first set of source data elements of a first bit-width, and at least a destination vector operand comprising destination data elements of a second bit-width, wherein the second bit-width is twice the first bit-width. The destination vector operand comprises a pair of registers including a first register comprising a first subset of the destination data elements and a second register comprising a second subset of the destination data elements. Based on a sequential order of the first set of source data elements, the method includes executing the SIMD instruction in the processor, comprising generating the first subset of destination data elements in the first register from even-numbered source data elements of the first set, and generating the second subset of destination data elements in the second register from odd-numbered source data elements of the first set.
[0012] Another exemplary aspect relates to a method of performing a mixed-width single instruction multiple data (SIMD) operation, the method comprising receiving, by a processor, a SIMD instruction comprising at least a source vector operand comprising source data elements of a first bit-width, and at least a destination vector operand comprising destination data elements of a second bit-width, wherein the second bit- width is half of the first bit-width. The source vector operand comprises a pair of registers including a first register comprising a first subset of the source data elements and a second register comprising a second subset of the source data elements. Based on a sequential order of the destination data elements, the method includes executing the SIMD instruction in the processor, comprising generating even-numbered destination data elements from corresponding first subset of source data elements in the first register, and generating odd-numbered destination data elements from corresponding second subset of source data elements in the second register.
[0013] Another exemplary aspect relates to a non-transitory computer-readable storage medium comprising instructions executable by a processor, which when executed by the processor cause the processor to perform mixed-width single instruction multiple data (SIMD) operation. The non-transitory computer-readable storage medium, comprises a SIMD instruction, which comprises at least a first source vector operand comprising a first set of source data elements of a first bit-width, and at least a destination vector operand comprising destination data elements of a second bit-width, wherein the second bit-width is twice the first bit-width. The destination vector operand comprises a pair of registers including a first register comprising a first subset of the destination data elements and a second register comprising a second subset of the destination data elements. Based on a sequential order of the first set of source data elements, the non- transitory computer-readable storage medium includes code for generating the first subset of destination data elements in the first register from even-numbered source data elements of the first set, and code for generating the second subset of destination data elements in the second register from odd-numbered source data elements of the first set.
[0014] Yet another exemplary aspect relates to a non-transitory computer-readable storage medium comprising instructions executable by a processor, which when executed by the processor cause the processor to perform mixed-width single instruction multiple data (SIMD) operation, the non-transitory computer-readable storage medium comprising a SIMD instruction. The SIMD instruction comprises at least a source vector operand comprising source data elements of a first bit-width, and at least a destination vector operand comprising destination data elements of a second bit-width, wherein the second bit-width is half of the first bit-width. The source vector operand comprises a pair of registers including a first register comprising a first subset of the source data elements and a second register comprising a second subset of the source data elements. Based on a sequential order of the destination data elements, the non-transitory computer-readable storage medium includes code for generating even-numbered destination data elements from corresponding first subset of source data elements in the first register, and code for generating odd-numbered destination data elements from corresponding second subset of source data elements in the second register.
[0016] FIGS. 1A-C illustrate conventional implementations of mixed-width SIMD instructions.
[0017] FIGS. 2A-C illustrate exemplary implementations of mixed-width SIMD instructions according to aspects of this disclosure.
[0018] FIGS. 3A-B illustrate methods of performing mixed-width single instruction multiple data (SIMD) operations.
[0019] FIG. 4 illustrates an exemplary wireless device 400 in which an aspect of the disclosure may be advantageously employed.
[0020] Aspects of the invention are disclosed in the following description and related drawings directed to specific aspects of the invention. Alternate aspects may be devised without departing from the scope of the invention. Additionally, well-known elements of the invention will not be described in detail or will be omitted so as not to obscure the relevant details of the invention.
[0022] The terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting of aspects of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising,", "includes" and/or "including", when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
[0023] Further, many aspects are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be recognized that various actions described herein can be performed by specific circuits (e.g., application specific integrated circuits (ASICs)), by program instructions being executed by one or more processors, or by a combination of both. Additionally, these sequence of actions described herein can be considered to be embodied entirely within any form of computer readable storage medium having stored therein a corresponding set of computer instructions that upon execution would cause an associated processor to perform the functionality described herein. Thus, the various aspects of the invention may be embodied in a number of different forms, all of which have been contemplated to be within the scope of the claimed subject matter. In addition, for each of the aspects described herein, the corresponding form of any such aspects may be described herein as, for example, "logic configured to" perform the described action.
[0024] Exemplary aspects of this disclosure relate to implementation of mixed-width SIMD operations which avoid data movement across SIMD lanes and reduce code size. For example, rather than decompose a SIMD operation into two or more component SIMD instructions (e.g., conventional execution of SIMD instruction 100 in FIGS. 1A-C), exemplary aspects include a single SIMD instruction which specifies one or more vector operands as a pair of operands, which may be expressed in terms of a pair of registers. By specifying at least one vector operand (either a source or a destination operand) as a pair of registers or a register pair, the single exemplary SIMD instruction can be used in place of two or more component conventional SIMD instructions. Therefore, code size is reduced for mixed- width SIMD operations.
[0025] It is noted that in this disclosure, reference is made to expressing operands in terms of registers, in order to follow the customary instruction formats where an instruction specifies an operation to be performed on one or more registers. Thus, a SIMD instruction may be of a format where a common operation is specified for one or more operands which are expressed in terms of registers. Thus, an exemplary mixed-width SIMD instruction according to this disclosure includes at least one vector operand expressed in terms of a single register and at least one other vector operand expressed in terms of a pair of registers. These references to registers may pertain to logical or architectural registers used by a program comprising exemplary SIMD instructions. They may also pertain to physical registers of a physical register file, without restriction. In general, the references to registers are meant to convey storage elements of a certain size.
[0026] Accordingly, an exemplary method of executing a mixed-width single instruction multiple data (SIMD) operation in a processor coupled to a register file may involve specifying a SIMD instruction with at least a first vector operand comprising data elements of a first bit-width and at least a second vector operand data elements of a second bit-width. The first vector operand can be a source vector operand and the second vector operand can be a destination vector operand. Correspondingly, the data elements of the source vector operand may be referred to as source data elements and data elements of the destination vector operand may be referred to as destination data elements.
[0027] A one-to-one correspondence exists between the source data elements and the destination data elements in an exemplary mixed-width SIMD instruction. In general, when the operation specified in the mixed-width SIMD instruction is performed on a source data element, a specific corresponding destination data element is generated. For example, consider a mixed-width SIMD operation for left-shifting the source vector operand to form a destination vector operand. In this example, each source data element generates a specific destination data element when a left-shift of the source data element is performed.
[0028] In one exemplary aspect of this disclosure, the second bit-width of the destination data elements can be less than, and specifically, half the size of the first bit-width of the source data elements. In this aspect, the destination vector operand can be expressed as a pair of registers and the source vector operand can be expressed as a single register.
[0029] In another exemplary aspect of this disclosure, the second bit-width of the destination data elements can be greater than, and specifically, twice the size of the first bit-width of the source data elements. In this aspect, the source vector operand can be expressed as a single register and the destination vector operand can be expressed as a pair of registers.
[0030] In order to illustrate the specific mapping between source and vector data elements of the source and destination vector operands, respectively, a sequential order is assigned to the data elements of the vector operand whose data elements have a smaller bit width. For example, a sequential order is assigned to data elements of the vector operand which is expressed as a single register. Based on the sequential order, even-numbered data elements (e.g., corresponding to numbers 0, 2, 4, 6, etc.) and odd-numbered data elements (e.g., corresponding to numbers 1, 3, 5, 7, etc.) are identified for the vector operand expressed as a single register. The pair of registers of the other vector operand are referred to as a first register and a second register, which comprise a first subset and a second subset of data elements respectively. Accordingly, the even-numbered data elements of the vector operand expressed as a single register are then assigned a correspondence with data elements of the first subset or first register, and the odd- numbered data elements are assigned a correspondence with data elements of the second subset or second register. In this manner, large data movements across SIMD lanes are avoided for source data elements during execution of the specified SIMD operation to generate corresponding destination data elements.
[0031] Exemplary aspects may also relate to SIMD operations which specify more than two vector operands, such as, include a third operand of a third bit-width, and beyond. One example is disclosed where two source vector operands, each expressed as a single register are specified for a mixed-width SIMD instruction to generate a destination vector operand expressed as a pair of register. Numerous other such instruction formats are possible within the scope of this disclosure. For the sake of simplicity, exemplary aspects for implementing mixed-width SIMD operations will be discussed with relation to some example SIMD instructions and bit-widths of operands, while keeping in mind that these are merely for the sake of explanation. As such, the features discussed herein can be extended to any number of operands and bit-widths of data elements for mixed- width vector operations.
[0032] In FIGS. 2A-C, exemplary aspects pertaining to SIMD instructions 200, 220, and 240 are shown. Each of these SIMD instructions 200, 220, and 240 can be executed by a processor (e.g., processor 402 shown in FIGS. 4-5) configured to execute SIMD instructions. More specifically, each of these SIMD instructions 200, 220, and 240 may specify one or more source vector operands and one or more destination vector operands, where the source and destination vector operands may be expressed in terms of registers (e.g., 64-bit registers). The source and destination vector operands of SIMD instructions 200, 220, and 240 include corresponding source and destination data elements, each of which fall under one or more SIMD lanes. The number of SIMD lanes in the execution of a SIMD instruction corresponds to the number of parallel operations which are performed in the execution of the SIMD instruction. A processor or execution logic configured to implement the example SIMD instructions 200, 220, and 240, can accordingly include hardware (e.g., an arithmetic and logic unit (ALU) comprising a number of left/right shifters, adders, multipliers, etc.,) required to implement the parallel operations specified by the SIMD instructions 200, 220, and 240.
[0033] Accordingly, with reference to FIG. 2A, a first exemplary aspect is illustrated for execution of SIMD instruction 200. In one example, the processor is assumed to be capable of supporting a 64-bit instruction set architecture (ISA). SIMD instruction 200 may specify the same operation or common instruction to be performed on source data elements of source vector operands expressed in terms of a single 64-bit register.
[0034] The same operation or common instruction specified in SIMD instruction 200 may be, for example, a square function, a left-shift function, an increment function, an addition by a constant value, etc., on eight 8-bit source data elements (which can be implemented with logic elements such as eight 8-bit left-shifters, eight 8-bit adders, etc.) which produces corresponding eight resulting destination data elements which can consume up to 16-bits of storage. As shown, SIMD instruction 200 may specify source vector operand 202 comprising eight 8-bit data elements. A numerical order may be assigned to these eight 8-bit data elements of source vector operand 202, which is shown by the reference numerals 0-7. The result of SIMD instruction 200 can be expressed using eight 16-bit destination data elements or 128-bits altogether, which cannot be stored in a single 64-bit register. Rather than decompose SIMD instruction 200 into two or more instructions to handle this problem (e.g., as in conventional implementations of SIMD instruction 100 shown in FIGS. 1A-C), a destination vector operand is specified as a pair of component vector operands. The pair of component destination vector operands can be expressed as a corresponding pair of registers 204x, 204y. Note that the pair of registers need not be stored in consecutive physical locations in a register file or even have consecutive logical register numbers. As such, SIMD instruction 200 specifies destination vector operand expressed in terms of a pair of component vector operands or registers 204x, 204y (e.g., a pair of 64-bit registers), and source vector operand 202, which is expressed as a single register 202.
[0036] Considering eight 8-bit SIMD lanes, e.g., referred to as SIMD lanes 0-7, with each lane comprising a respective source data element 0-7, it is seen that the amount of movement involved to generate a corresponding destination data element A-H is contained within the same SIMD lane or an adjacent SIMD lane. In other words, a first set of source data elements (e.g., source data element 0-7) are in respective SIMD lanes, and from each one of the source data elements, a destination data element (e.g., a corresponding destination data element A-H) is generated in the respective SIMD lane or a SIMD lane adjacent to the respective SIMD lane. For example, even-numbered source data elements 0, 2, 4, and 6 in SIMD lanes 0, 2, 4, and 6, respectively, generate destination data elements A, C, E, and G, which are respectively contained within SIMD lanes 0-1, 2-3, 4-5, and 6-7. Similarly, odd-numbered source data elements 1, 3, 5, and 7 in SIMD lanes 0, 2, 4, and 6, respectively, generate destination data elements B, D, F, and H, which are respectively also contained within SIMD lanes 0-1, 2-3, 4-5, and 6-7.
[0037] Accordingly, in the first exemplary aspect of FIG. 2A, mixed-width SIMD instruction 200 involves efficient use of instruction space or code space (since only one SIMD instruction is used, rather than two or more component SIMD instructions), whose implementation or execution avoids large data movements across SIMD lanes.
[0038] With reference now to FIG. 2B, another exemplary aspect is illustrated with relation to mixed-width SIMD instruction 220. SIMD instruction 220 involves two source vector operands: first source vector operand expressed as a single register 222 and second source vector operand expressed as a single register 223, which have a first set and second set, respectively, of four 16-bit source data elements. SIMD instruction 220 may specify a same or common operation such as a multiplication (e.g., with rounding) on the two source vector operands, wherein four 16-bit source data elements of the first set (in register 222) are multiplied by corresponding four 16-bit source data elements of the second set (in register 223) to produce four 32-bit results (where implementation of SIMD instruction 220 can involve logic elements such as four 16x16 multipliers). Since 128-bits are needed to be able to store these four 32-bit results, a destination vector operand is specified in terms of a pair of component vector operands: first component destination vector operand and second component destination vector operand (these may be expressed as a first 64-bit register 224x and a second 64-bit register 224y correspondingly). It is noted that SIMD instruction 220 may also be applicable to addition of source data elements of the first set with corresponding source data elements of the second set, where the corresponding results may consume more than 16-bits (even if not all 32-bits) for each destination data element.
[0039] In FIG. 2B, source data elements of the first and second sets are assigned a sequential order, representatively shown as 0, 1, 2, 3 and Ο', , 2', 3', respectively. First component destination vector operand in first register 224x holds a first subset of the results of SIMD instruction 220 (shown as 32-bit destination data elements A and C) corresponding to even-numbered source data elements of the source operands 222 and 223; and similarly, second component destination vector operand in second register 224y holds a second subset of the results of SIMD instruction 220 (shown as 32-bit data elements B and D) corresponding to odd-numbered source data elements of the source operands 222 and 223. In this case, it is seen that even-numbered source data elements (0, 0') and (2, 2') of first source vector operand 222 and second source vector operand 223, respectively, generate data elements A and C of first destination vector operand 224x; and odd-numbered data elements (1, ) and (3, 3') of first source vector operand 222 and second source vector operand 223, respectively, generate data elements B and D of second destination vector operand 224y.
[0040] Once again, it is seen in the second exemplary aspect of FIG. 2B, mixed-width SIMD instruction 220 accomplishes code space efficiency by utilizing a single mixed-width SIMD instruction rather than two or more component SIMD instructions. Moreover, it is also seen that movements across SIMD lanes is minimized in this aspect as well. In general, the first set of source data elements and second set of source data elements are in respective SIMD lanes, and generate from each one of the source data elements of the first set and corresponding one of the source data elements of the second set, a destination data element in the respective SIMD lane or a SIMD lane adjacent to the respective SIMD lane. For example, considering four 16-bit SIMD lanes 0-3 which comprise the first set of source data elements 0-3 (or second set of source data elements 0'-3'), respectively, data movement for a source data element of the first and second to generate a corresponding destination data elements A-D is contained within the same SIMD lane and at most an adjacent SIMD lane (e.g., even-numbered source data elements (0, 0') and (2, 2') in SIMD lanes 0 and 2, respectively, generate destination data elements A and C in SIMD lanes 0-1 and 2-4; and similarly, odd-numbered source data elements (1, ) and (3, 3') in SIMD lanes 1 and 3, respectively, generate destination data elements B and D in SIMD lanes 0-1 and 2-4).
[0041] FIG. 2C represents a third exemplary aspect related to mixed-width SIMD instruction 240. Unlike mixed-width SIMD instructions 200 and 220, a source vector operand of mixed-width SIMD instruction 240 is specified as a pair of component vector operands or expressed as a register pair. It is noted that mixed-width SIMD instruction 240 is different from mixed-width SIMD instruction 220 because mixed-width SIMD instruction 220 included two separate source vector operands, where data elements of one source vector operand were specified to interact (e.g., get multiplied with) data elements of another source vector operand. On the other hand, in mixed-width SIMD instruction 240, a pair of component source vector operands is specified because not doing so would have consumed two separate instructions. For example, SIMD instruction 240 may involve a common operation of a right-shift function from 16-bits to 8-bits to be performed on eight 16-bit source data elements in order to obtain a result of eight 8-bit destination data elements (where implementation of SIMD instruction 240 can involve logic elements such as eight 8-bit right-shifters). However, since eight 16- bit source data elements consume 128-bits, conventional implementations would have split up this operation to be performed using two component SIMD instructions. On the other hand, in the exemplary aspect of FIG. 2C, a source vector operand pair comprising first component source vector operand in first register 242x and a second component source vector operand in second register 242y are specified by SIMD instruction 240. Accordingly, code space is efficiently used.
[0042] The destination vector operand is expressed as a single 64-bit register 244 in this case and comprises eight 8-bit destination data elements which are results of SIMD instruction 240. Accordingly, a sequential order is assigned to the destination data elements of the destination vector operand in register 244, which are shown with reference numerals 0-7. The source data elements of the pair of component source vector operands (expressed as a pair of registers 242x, 242y) are arranged such that first register 242x comprising a first subset of source data elements A, C, E, and G, will generate the results corresponding to even-numbered destination data elements 0, 2, 4, and 6 of the destination vector operand in register 244, respectively; and second register 242y comprising a second subset of source data elements B, D, F, and H, will generate the results corresponding to odd-numbered destination data elements 1, 3, 5, and 7, respectively, of destination vector operand in register 244.
[0043] Thus code space can be effectively utilized and data movement across SIMD lanes can be minimized even in cases where the source vector operands are wider than the destination vector operands, by specifying a pair of component source vector operands or expressing the source vector operand as a pair of registers. Movement across SIMD lanes in execution of SIMD instruction 240 is also minimized. In general, it is seen that the destination data elements are in respective SIMD lanes, and each one of the destination data elements is generated from a source data element in the respective SIMD lane or a SIMD lane adjacent to the respective SIMD lane. For example, considering eight 8-bit SIMD lanes corresponding to the eight destination data elements 0-7, it is seen that source data elements A, C, E, and G, will move from SIMD lanes 0-1, 2-3, 4-5, and 6-7 respectively to generate the results corresponding to even-numbered destination data elements in SIMD lanes 0, 2, 4, and 6; and source data elements B, D, F, and H, will move from SIMD lanes 0-1, 2-3, 4-5, and 6-7 respectively to generate the results corresponding to even-numbered destination data elements in SIMD lanes 1, 3, 5, and 7. In either case, the movement is contained within two SIMD lanes.
[0044] Accordingly, it will be appreciated that aspects include various methods for performing the processes, functions and/or algorithms disclosed herein. For example, as illustrated in FIG. 3A, an aspect can include a method 300 of performing a mixed-width single instruction multiple data (SIMD) operation, in accordance with FIGS. 2A-B, for example.
[0045] In Block 302, method 300 includes receiving, by a processor (e.g., processor 402 of FIG. 4, which will be explained below), and with reference, for example, to FIG. 2A, a SIMD instruction (e.g., SIMD instruction 200) comprising at least a first source vector operand (e.g., in register 202) comprising a first set of source data elements (e.g., source data elements 0-7) of a first bit-width (e.g., 8-bits); and at least a destination vector operand (e.g., in register pair 204x, 204y) comprising destination data elements (e.g., destination data elements A-H) of a second bit-width (e.g., 16-bits), wherein the second bit-width is twice the first bit-width, wherein the destination vector operand comprises a pair of registers including a first register (e.g., 204x) comprising a first subset of the destination data elements (e.g., destination data elements A, C, E, G) and a second register comprising a second subset of the destination data elements (e.g., destination data elements B, D, F, H).
[0046] In Block 303 (which is shown to include Blocks 304 and 306), method 300 further includes executing the mixed-width SIMD instruction in the processor. Specifically, considering a sequential order (e.g., 0-7) assigned to the source data elements in Block 304, Block 306 includes executing the SIMD instruction in the processor. In further detail, Block 306 is made of the components Blocks 306a and 306b which may be performed in parallel.
[0047] Block 306a includes generating the first subset of destination data elements (e.g., destination data elements A, C, E, G) in the first register (e.g., first register 204x) from even-numbered source data elements (e.g., source data elements 0, 2, 4, 6) of the first set.
[0048] Block 306b includes generating the second subset of destination data elements (e.g., destination data elements B, D, F, H) in the second register (e.g., second register 204y) from odd-numbered source data elements (e.g., source data elements 1, 3, 5, 7) of the first set.
[0049] In general, the SIMD instruction of method 300 can be one of a square function, left- shift function, increment, or addition by a constant value, of the source data elements of the first set. Code space efficiency is achieved by utilizing a single SIMD instruction in method 300. Movement across SIMD lanes is also minimized in method 300, where the first set of source data elements are in respective SIMD lanes, and method 300 includes generating from each one of the source data elements (e.g., source data element 0 in SIMD lane 0), a destination data element (e.g., destination data element A) in the respective SIMD lane (e.g., SIMD lane 0) or a SIMD lane adjacent (e.g., SIMD lane 1) to the respective SIMD lane.
[0050] It will also be noted that although not shown separately, method 300 can also include a method for implementing SIMD instruction 220 of FIG. 2B, which further comprises, for example, receiving in Block 302, a second source vector operand, comprising a second set of source data elements of the first bit-width (e.g., first and second source vector operands in registers 222 and 223), and the sequential order of the first set of source data elements corresponds to a sequential order of the second set of source data elements. In this case, based on the sequential order assigned in Block 304, Block 306 includes executing the SIMD instruction in the processor, comprising Block 306a for generating the first subset of destination data elements in the first register from even- numbered source data elements of the first set and even-numbered source data elements of the second set; and Block 306b for generating the second subset of destination data elements in the second register from odd-numbered source data elements of the first set and even-numbered source data elements of the second set. In this case, the SIMD instruction can be a multiplication or addition of the source data elements of the first set with corresponding source data elements of the second set, wherein the first set of source data elements and second set of source data elements are in respective SIMD lanes, and generating from each one of the source data elements of the first set and corresponding one of the source data elements of the second set, a destination data element in the respective SIMD lane or a SIMD lane adjacent to the respective SIMD lane.
[0051] With reference to FIG. 3B, another method for performing the processes, functions and/or algorithms disclosed herein is illustrated. For example, as illustrated in FIG. 3B, method 300 includes another method of performing a mixed-width single instruction multiple data (SIMD) operation, in accordance with FIG. 2C, for example.
[0052] In Block 352, method 350 includes receiving, by a processor (e.g., processor 402), a SIMD instruction (e.g., SIMD instruction 240) comprising: at least a source vector operand (e.g., in registers 242x, 242y) comprising source data elements (e.g., source data elements A-H) of a first bit-width (e.g., 16-bits); and at least a destination vector operand (e.g., in register 244) comprising destination data elements (e.g., destination data elements 0-7) of a second bit-width (e.g., 8-bits), wherein the second bit-width is half of the first bit-width, wherein the source vector operand comprises a pair of registers including a first register (e.g., first register 242x) comprising a first subset of the source data elements (e.g., destination data elements 0, 2, 4, 6) and a second register (e.g., second register 242y) comprising a second subset of the source data elements (e.g., destination data elements 1, 3, 5, 7).
[0053] In Block 354, a sequential order is assigned to the destination data elements, and in Block 356, the SIMD instruction is executed. Block 356 includes sub blocks 356a and 356b, which can also be performed in parallel.
[0054] Block 356a includes generating even-numbered destination data elements (e.g., destination data elements 0, 2, 4, 6) from corresponding first subset of source data elements in the first register (e.g., source data elements A, C, E, G).
[0055] Block 356b includes generating odd-numbered destination data elements (e.g., destination data elements 1, 3, 5, 7) from corresponding second subset of source data elements in the second register (e.g., source data elements B, D, F, H).
[0056] In exemplary aspects, the SIMD instruction of method 350 may be a right-shift function of the source data elements, wherein the destination data elements are in respective SIMD lanes (e.g., SIMD lanes 0-7), and generating each one of the destination data elements (e.g., destination data element 0) from a source data element (e.g., source data element A) in the respective SIMD lane (e.g., SIMD lane 0) or a SIMD lane adjacent (e.g., SIMD lane 1) to the respective SIMD lane.
[0057] Referring to FIG. 4, a block diagram of a particular illustrative aspect of wireless device 400 according to exemplary aspects. Wireless device 400 includes processor 402 which may be configured (e.g., include execution logic) to support and implement the execution of exemplary mixed-width SIMD instructions, for example, according to methods 300 and 350 of FIG. 3A and FIG. 3B, respectively. As shown in FIG. 4, processor 402 may be in communication with memory 432. Processor 402 may include a register file (not shown) which holds physical registers corresponding to the registers (e.g., logical registers) in terms of which operands of the exemplary SIMD instructions are expressed. The register file may be supplied with data from memory 432 in some aspects. Although not shown, one or more caches or other memory structures may also be included in wireless device 400.
[0058] FIG. 4 also shows display controller 426 that is coupled to processor 402 and to display 428. Coder/decoder (CODEC) 434 (e.g., an audio and/or voice CODEC) can be coupled to processor 402. Other components, such as wireless controller 440 (which may include a modem) are also illustrated. Speaker 436 and microphone 438 can be coupled to CODEC 434. FIG. 4 also indicates that wireless controller 440 can be coupled to wireless antenna 442. In a particular aspect, processor 402, display controller 426, memory 432, CODEC 434, and wireless controller 440 are included in a system-in-package or system-on-chip device 422.
[0059] In a particular aspect, input device 430 and power supply 444 are coupled to the system- on-chip device 422. Moreover, in a particular aspect, as illustrated in FIG. 4, display 428, input device 430, speaker 436, microphone 438, wireless antenna 442, and power supply 444 are external to the system-on-chip device 422. However, each of display 428, input device 430, speaker 436, microphone 438, wireless antenna 442, and power supply 444 can be coupled to a component of the system-on-chip device 422, such as an interface or a controller.
[0060] It should be noted that although FIG. 4 depicts a wireless communications device, processor 402 and memory 432 may also be integrated into a set top box, a music player, a video player, an entertainment unit, a navigation device, a personal digital assistant (PDA), a fixed location data unit, a communications device, or a computer. Further, at least one or more exemplary aspects of wireless device 400 may be integrated in at least one semiconductor die.
[0061] Those of skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
[0062] Further, those of skill in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
[0063] The methods, sequences and/or algorithms described in connection with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
[0064] Accordingly, an aspect of the invention can include computer readable media (e.g., a non-transitory computer readable storage medium) embodying a method for implementing mixed-width SIMD instructions (e.g., according to methods 300 and 350 described above, for implementing SIMD instructions of FIGS. 2A-C). Accordingly, the invention is not limited to illustrated examples and any means for performing the functionality described herein are included in aspects of the invention.
[0065] While the foregoing disclosure shows illustrative aspects of the invention, it should be noted that various changes and modifications could be made herein without departing from the scope of the invention as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the aspects of the invention described herein need not be performed in any particular order. Furthermore, although elements of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

中文:
[0001]本揭示的各方面涉及包括两个或多于两个向量的运算,其中至少一个向量的数据元素与至少另一向量的数据元素具有不同位宽。此类运算被称为混合宽度运算。更具体地说,一些方面涉及包括至少第一向量操作数和第二向量操作数的混合宽度单指令多数据(SIMD)运算,其中第一或第二向量操作数中的至少一个具有可存储在偶数或奇数个寄存器对中的数据元素。
[0002]单指令多数据(SIMD)指令可用于处理系统以采用数据并行性。当需要在例如数据向量的两个或多于两个数据元素上进行相同或共同任务时存在数据并行性。可通过使用单条SIMD指令而不是使用多条指令对两个或多于两个数据元素并行地进行共同任务,所述单条SIMD指令限定有待对对应多个SIMD通道中的多个数据元素进行的相同指令。
[0003]SIMD指令可包含一或多个向量操作数,例如源向量操作数和目的地向量操作数。每个向量操作数将包含两个或多于两个数据元素。对于SIMD指令,属于相同向量操作数的所有数据元素可大体上具有相同位宽。然而,一些SIMD指令可指定混合宽度操作数,其中第一向量操作数的数据元素可具有第一位宽且第二向量操作数的数据元素可具有第二位宽,其中第一和第二位宽彼此不同。具有混合宽度操作数的SIMD指令的执行可包括若干挑战。
[0004]图1A到C示出包括在用于执行具有混合宽度操作数的SIMD指令的常规实施方案中的挑战的实例。参考图1A,示出用于执行SIMD指令100的第一常规实施方案。假定SIMD指令100可由支持64位指令集体系结构(ISA)的常规处理器(未示出)执行。这意味着例如SIMD指令100等指令可指定具有高达64位位宽的操作数。可就64位寄存器或32位寄存器对来指定64位操作数。
[0005]SIMD指令100的目标是对源操作数102的每个数据元素执行相同指令。源操作数102是包括标记为0到7的八个8位数据元素的64位向量。源操作数102可存储在单个64位寄存器或32位寄存器对中。有待对八个数据元素0到7中的每一个执行的相同指令或共同运算可例如是乘法、平方函数、左移位函数、增量函数、加法(例如,根据指令中的一常数值或立即数字段或根据由另一向量操作数提供的值)等,所述相同指令或共同运算的结果针对八个所得数据元素中的每一个可消耗多于8位且高达16位存储容量。这意味着SIMD指令100的结果可消耗源操作数102可消耗的存储空间两倍的存储空间,即,两个64位寄存器或两个32位寄存器对。
[0006]由于被配置成实施SIMD指令100的常规处理器并不包含指定大于64位位宽的操作数的指令,因此SIMD指令100可分成两个分量SIMD指令:100X和100Y。SIMD指令100X指定有待对标记有源操作数102的偶数(或“偶数编号的数据元素”)0、2、4和6的数据元素进行的共同运算。SIMD指令100X指定目的地操作数104x,所述目的地操作数104x的宽度是64位且包含标记为A、C、E和G的16位数据元素,其中的每一个包括高(H)8位和低(L)8位。对源操作数102的偶数编号的8位数据元素0、2、4和6的共同运算的结果对应地写入目到的地操作数104x的16位数据元素A、C、E和G。SIMD指令100Y类似于SIMD指令100X,其中的区别在于,SIMD指令100Y指定对标记有源操作数102的奇数(或“奇数编号的数据元素”)1、3、5和7的数据元素的共同运算,同时结果有待写入到目的地操作数104y的16位数据元素B、D、F、H,所述目的地操作数104y还是类似于SIMD指令100X的目的地操作数104x的64位操作数。以此方式,SIMD指令100X和100Y中的每一个可指定一个64位目的地操作数,且SIMD指令100X和100Y可一起实现对源操作数102的数据元素0到7中的每一个的共同运算的执行。然而,由于需要实施的两条单独指令,因此SIMD指令100增加了代码空间。
[0007]图1B示出使用分量SIMD指令120X和120Y的不同集合的SIMD指令100的第二常规实施方案。SIMD指令120X和120Y各自指定对源操作数102的8位数据元素0到7中的每一个的共同运算。SIMD指令120X将目的地操作数124x(低(L)8位结果有待写入到所述目的地操作数124x)指定为目的地操作数124x的对应8位结果数据元素A到H(同时丢弃结果的高(H)8位)。类似地,指令120Y将目的地操作数124y(高(H)8位结果有待写入到所述目的地操作数124y)指定为目的地操作数124y的对应8位数据元素A到H(同时丢弃结果的低(L)8位)。SIMD指令100的此第二常规实施方案的不足之处还在于针对两个分量SIMD指令120X和120Y增加的代码空间。此外,如可理解的,第二常规实施方案还引发针对源操作数102的数据元素0到7中的每一个计算和丢弃高(H)8位(例如,在执行指令120X时)或低(L)8位(例如,在执行指令120Y时)时的功率损耗。
[0008]图1C示出使用分量SIMD指令140X和140Y的又一集合的SIMD指令100的第三常规实施方案,所述分量SIMD指令140X和140Y在某些方面类似于图1A的SIMD指令100X和100Y。区别在于每条SIMD指令对源操作数102的数据元素中的哪些数据元素进行运算。更详细地,SIMD指令140X指定有待对源操作数102的下游四个数据元素0到3而不是偶数编号的8位数据元素进行的共同运算。结果写入到目的地操作数144x的16位数据元素A、B、C、D。然而,SIMD指令140X的执行包括将对下游四个8位数据元素(生成32位)的运算结果跨目的地操作数140X的所有64位扩散出去。SIMD指令144y是类似的且指定将对源操作数102的上游四个8位数据元素4到7的运算结果跨64位目的地操作数144y的16位数据元素E、F、G、H扩散出去。除了如第一和第二常规实施方案中增加的代码大小外,如第三常规实施方案中所见的这些扩散出去的数据移动可能需要例如交叉开关等额外硬件。
[0009]因此,需要一种避开常规实施方案的以上提及的缺点的混合宽度SIMD指令的改进的实施方案。
[0010]示范性方面包含关于混合宽度单指令多数据(SIMD)指令的系统和方法,所述混合宽度单指令多数据指令具有包括第一位宽数据元素的至少源向量操作数以及包括第二位宽数据元素的目的地向量操作数,其中所述第二位宽是所述第一位宽的一半或两倍。对应地,源向量操作数或目的地向量操作数中的一个表达为寄存器对:第一寄存器和第二寄存器。另一向量操作数表达为单个寄存器。第一寄存器的数据元素对应于表达为单个寄存器的另一向量操作数的偶数编号的数据元素,且第二寄存器的数据元素对应于表达为单个寄存器的另一向量操作数的数据元素。
[0011]举例来说,示范性方面涉及进行混合宽度单指令多数据(SIMD)运算的方法,所述方法包括:由处理器接收SIMD指令,所述SIMD指令包括:包括第一位宽源数据元素的第一集合的至少第一源向量操作数以及包括第二位宽目的地数据元素的至少目的地向量操作数,其中所述第二位宽是所述第一位宽的两倍。目的地向量操作数包括寄存器对,所述寄存器对包含:包括目的地数据元素的第一子集的第一寄存器以及包括目的地数据元素的第二子集的第二寄存器。基于源数据元素的第一集合的顺序次序,所述方法包含在处理器中执行SIMD指令,包括:从第一集合的偶数编号的源数据元素生成第一寄存器中的目的地数据元素的第一子集,以及从第一集合的奇数编号的源数据元素生成第二寄存器中的目的地数据元素的第二子集。
[0012]另一示范性方面涉及进行混合宽度单指令多数据(SIMD)运算的方法,所述方法包括:由处理器接收SIMD指令,所述SIMD指令包括:包括第一位宽源数据元素的至少源向量操作数以及包括第二位宽目的地数据元素的至少目的地向量操作数,其中所述第二位宽是所述第一位宽的一半。源向量操作数包括寄存器对,所述寄存器对包含:包括源数据元素的第一子集的第一寄存器以及包括源数据元素的第二子集的第二寄存器。基于目的地数据元素的顺序次序,所述方法包含在处理器中执行SIMD指令,包括:从第一寄存器中的源数据元素的对应第一子集生成偶数编号的目的地数据元素,以及从第二寄存器中的源数据元素的对应第二子集生成奇数编号的目的地数据元素。
[0013]另一示范性方面涉及包括可由处理器执行的指令的非暂时性计算机可读存储媒体,所述指令在由所述处理器执行时致使处理器进行混合宽度单指令多数据(SIMD)运算。所述非暂时性计算机可读存储媒体包括SIMD指令,所述SIMD指令包括:包括第一位宽源数据元素的第一集合的至少第一源向量操作数以及包括第二位宽目的地数据元素的至少目的地向量操作数,其中所述第二位宽是所述第一位宽的两倍。目的地向量操作数包括寄存器对,所述寄存器对包含:包括目的地数据元素的第一子集的第一寄存器以及包括目的地数据元素的第二子集的第二寄存器。基于源数据元素的第一集合的顺序次序,所述非暂时性计算机可读存储媒体包含:用于从第一集合的偶数编号的源数据元素生成第一寄存器中的目的地数据元素的第一子集的代码,以及从第一集合的奇数编号的源数据元素生成第二寄存器中的目的地数据元素的第二子集的代码。
[0014]又一示范性方面涉及包括可由处理器执行的指令的非暂时性计算机可读存储媒体,所述指令在由所述处理器执行时致使处理器进行混合宽度单指令多数据(SIMD)运算,所述非暂时性计算机可读存储媒体包括SIMD指令。所述SIMD指令包括:包括第一位宽源数据元素的至少源向量操作数以及包括第二位宽目的地数据元素的至少目的地向量操作数,其中所述第二位宽是所述第一位宽的一半。源向量操作数包括寄存器对,所述寄存器对包含:包括源数据元素的第一子集的第一寄存器以及包括源数据元素的第二子集的第二寄存器。基于目的地数据元素的顺序次序,所述非暂时性计算机可读存储媒体包含:用于从第一寄存器中的源数据元素的对应第一子集生成偶数编号的目的地数据元素的代码,以及从在第二寄存器中的源数据元素的对应第二子集生成奇数编号的目的地数据元素的代码。
[0016]图1A到C示出混合宽度SIMD指令的常规实施方案。
[0017]图2A到C示出根据本揭示的各方面的混合宽度SIMD指令的示范性实施方案。
[0018]图3A到B示出进行混合宽度单指令多数据(SIMD)运算的方法。
[0019]图4示出本揭示的一方面可有利地用于其中的示范性无线装置400。
[0020]在以下针对本发明的具体方面的描述和相关图式中揭示本发明的各方面。可在不脱离本发明的范围的情况下设计替代方面。另外,将不会详细描述或将省略本发明的众所周知的元件以免混淆本发明的相关细节。
[0022]本文中所使用的术语仅出于描述特定方面的目的,且并不打算限制本发明的各方面。如本文中所使用,单数形式“一(a/an)”和“所述”打算还包含复数形式,除非上下文另外清楚地指示。将进一步理解,术语“包括”和/或“包含”当在本文中使用时指定所叙述的特征、整数、步骤、操作、元件和/或组件的存在,但并不排除一或多个其它特征、整数、步骤、操作、元件、组件和/或其群组的存在或添加。
[0023]此外,就待由例如计算装置的元件进行的动作序列来描述许多方面。将认识到,本文中所描述的各种动作可由特定电路(例如,专用集成电路(ASIC))、由正由一或多个处理器执行的程序指令或由所述两者的组合来进行。另外,本文中所描述的这些动作序列可被视为全部在任何形式的计算机可读存储媒体内体现,在所述计算机可读存储媒体中存储有对应计算机指令集,所述计算机指令集在执行时将致使相关联的处理器进行本文中所描述的功能性。因此,本发明的各种方面可以数个不同形式来体现,预期所有形式属于所要求的主题的范围内。另外,对于本文中所描述的各方面中的每一个,任何此类方面的对应形式可在本文中描述为例如“逻辑被配置成”进行所描述动作。
[0024]本揭示的示范性方面涉及混合宽度SIMD运算的实施方案,其避免跨SIMD通道的数据移动且减小代码大小。举例来说,示范性方面包含将一或多个向量操作数指定为操作数对(其可就寄存器对来表达)的单条SIMD指令,而不是将SIMD操作分解成两条或多于两条分量SIMD指令(例如,图1A到C中的SIMD指令100的常规执行)。通过将至少一个向量操作数(源操作数或目的地操作数中的任一个)指定为寄存器对或一寄存器对,所述单条示范性SIMD指令可用于代替两条或多于两条分量常规SIMD指令。因此,代码大小减小以实现混合宽度SIMD运算。
[0025]应指出,在本揭示中,对就寄存器来表达的操作数进行引用以便遵循惯例的指令格式,其中指令指定有待在一或多个寄存器上进行的运算。因此,SIMD指令可具有一定格式,其中对就寄存器来表达的一或多个操作数指定共同运算。因此,根据本揭示的示范性混合宽度SIMD指令包含就单个寄存器来表达的至少一个向量操作数和就寄存器对来表达的至少另一向量操作数。对寄存器的这些引用可涉及由包括示范性SIMD指令的程序使用的逻辑或体系结构寄存器。对寄存器的这些引用还可非限制地涉及物理寄存器堆的物理寄存器。大体上,对寄存器的引用意指传达某一大小的存储元件。
[0026]因此,在耦合到寄存器堆的处理器中执行混合宽度单指令多数据(SIMD)运算的示范性方法可包括指定具有包括第一位宽数据元素的至少第一向量操作数以及包括第二位宽数据元素的至少第二向量操作数的SIMD指令。第一向量操作数可以是源向量操作数且第二向量操作数可以是目的地向量操作数。对应地,源向量操作数的数据元素可被称为源数据元素且目的地向量操作数的数据元素可被称为目的地数据元素。
[0027]一一对应存在于示范性混合宽度SIMD指令中的源数据元素与目的地数据元素之间。大体上,当对源数据元素进行混合宽度SIMD指令中指定的运算时,生成具体的对应目的地数据元素。举例来说,考虑到混合宽度SIMD运算以使源向量操作数左移位,从而形成目的地向量操作数。在此实例中,当进行源数据元素的左移位时,每个源数据元素生成具体目的地数据元素。
[0028]在本揭示的一个示范性方面中,目的地数据元素的第二位宽可小于源数据元素的第一位宽的大小,且具体地说是后者的一半。在此方面中,目的地向量操作数可表达为一对寄存器且源向量操作数可表示为单个寄存器。
[0029]在本揭示的另一示范性方面中,目的地数据元素的第二位宽可大于源数据元素的第一位宽的大小,且具体地说是后者的两倍。在此方面中,源向量操作数可表达为单个寄存器且目的地向量操作数可表达为寄存器对。
[0030]为了示出源向量操作数和目的地向量操作数各自的源向量数据元素与向量数据元素之间的具体映射,对向量操作数的数据元素(其数据源数据具有更小位宽)分配顺序次序。举例来说,对表达为单个寄存器的向量操作数的数据元素分配顺序次序。基于顺序次序,对表达为单个寄存器的向量操作数标识偶数编号的数据元素(例如,对应于编号0、2、4、6等)和奇数编号的数据元素(例如,对应于编号1、3、5、7等)。另一向量操作数的寄存器对被称为第一寄存器和第二寄存器,所述第一寄存器和第二寄存器各自包括数据元素的第一子集和第二子集。因此,表达为单个寄存器的向量操作数的偶数编号的数据元素接着分配有与第一子集或第一寄存器的数据元素的对应关系,且奇数编号的数据元素分配有与第二子集或第二寄存器的数据元素的对应关系。以此方式,避免了源数据元素在执行指定SIMD运算以生成对应目的地数据元素期间跨SIMD通道的大的数据移动。
[0031]示范性方面还可涉及指定多于两个向量操作数(例如包含第三位宽的第三操作数及超过)的SIMD运算。揭示其中两个源向量操作数的一个实例,对混合宽度SIMD指令指定表达为单个寄存器的每个源向量操作数以生成表达为寄存器对的目的地向量操作数。众多其它此类指令格式在本揭示的范围内是可能的。为简单起见,将关于操作数的一些实例SIMD指令和位宽描述用于实施混合宽度SIMD运算的示范性方面,同时记住这些仅仅是为了解释起见。由此,本文中所论述的特征可扩展到数据元素的任何数目的操作数和位宽以实现混合宽度向量运算。
[0032]在图2A到C中,示出关于SIMD指令200、220和240的示范性方面。这些SIMD指令200、220和240中的每一个可由被配置成执行SIMD指令的处理器(例如,图4到5中所示出的处理器402)执行。更具体地说,这些SIMD指令200、220和240中的每一个可指定一或多个源向量操作数和一或多个目的地向量操作数,其中所述源向量操作数和目的地向量操作数可就寄存器(例如,64位寄存器)来表达。SIMD指令200、220和240的源向量操作数和目的地向量操作数包含对应源数据元素和目的地数据元素,其中的每一个落在一或多个SIMD通道下。执行SIMD指令时SIMD通道的数目对应于执行SIMD指令时进行的并行运算的数目。被配置成实施实例SIMD指令200、220和240的处理器或执行逻辑可因此包含实施由SIMD指令200、220和240指定的并行运算所需的硬件(例如,包括多个左/右移位器、加法器、乘法器等的算术和逻辑单元(ALU))。
[0033]因此,参考图2A,示出SIMD指令200的执行的第一示范性方面。在一个实例中,采用处理器以能够支持64位指令集体系结构(ISA)。SIMD指令200可指定有待对就单个64位寄存器来表达的源向量操作数的源数据元素进行的相同运算或共同指令。
[0034]SIMD指令200中指定的相同运算或共同指令可以是例如根据一常数值等对八个8位源数据元素的平方函数、左移位函数、增量函数、加法(其可运用例如八个8位左移位器、八个8位加法器等逻辑元件实施),所述相同运算或共同指令产生可消耗高达16位存储容量的对应八个所得目的地数据元素。如所示出,SIMD指令200可指定包括八个8位数据元素的源向量操作数202。可对源向量操作数202的这八个8位数据元素分配数字次序,所述八个8位数据元素由附图标记0到7示出。可使用八个16位目的地数据元素或总共128位来表达SIMD指令200的无法存储在单个64位寄存器中的结果。将目的地向量操作数指定为分量向量操作数对,而不是将SIMD指令200分解成两条或多于两条指令以处置此问题(例如,如图1A到C中所示出的SIMD指令100的常规实施方案中那样)。分量目的地向量操作数对可表达为对应寄存器204x、204y对。应指出,寄存器对无需存储在寄存器堆中的连续物理位置中或甚至具有连续逻辑寄存器编号。由此,SIMD指令200指定就分量向量操作数或寄存器204x、204y对(例如,64位寄存器对)来表达的目的地向量操作数,以及表达为单个寄存器202的源向量操作数202。
[0036]考虑到八个8位SIMD通道(例如,被称为SIMD通道0到7),其中每个通道包括相应源数据元素0到7,看出生成对应目的地数据元素A到H所包括的移动量包含在相同SIMD通道或邻近SIMD通道内。换句话说,源数据元素的第一集合(例如,源数据元素0到7)是在相应SIMD通道中,且从源数据元素中的每一个在相应SIMD通道或邻近于相应SIMD通道的SIMD通道中生成目的地数据元素(例如,对应目的地数据元素A到H)。举例来说,各自在SIMD通道0、2、4和6中的偶数编号的源数据元素0、2、4和6生成目的地数据元素A、C、E、和G,所述目的地数据元素A、C、E、和G各自包含在SIMD通道0到1、2到3、4到5和6到7内。类似地,各自在SIMD通道0、2、4和6中的奇数编号的源数据元素1、3、5和7生成目的地数据元素B、D、F和H,所述目的地数据元素B、D、F和H也各自包含在SIMD通道0到1、2到3、4到5和6到7内。
[0037]因此,在图2A的第一示范性方面中,混合宽度SIMD指令200包括指令空间或代码空间的有效使用(由于仅使用一条SIMD指令而不是两条或多于两条分量SIMD指令),其实施或执行避免了跨SIMD通道的大的数据移动。
[0038]现在参考图2B,关于混合宽度SIMD指令220示出另一示范性方面。SIMD指令220包括两个源向量操作数:表达为单个寄存器222的第一源向量操作数和表达为单个寄存器223的第二源向量操作数,其各自具有四个16位源数据元素的第一集合和第二集合。SIMD指令220可指定对两个源向量操作数的例如乘法等相同或共同运算(例如,运用四舍五入),其中第一集合的四个16位源数据元素(在寄存器222中)乘以第二集合的对应四个16位源数据元素(在寄存器223中)以产生四个32位结果(其中SIMD指令220的实施方案可包括例如四个16×16乘法器等逻辑元件)。由于需要128位能够存储这四个32位结果,因此就分量向量操作数对来指定目的地向量操作数:第一分量目的地向量操作数和第二分量目的地向量操作数(这些可对应地表达为第一64位寄存器224x和第二64位寄存器224y)。应指出,SIMD指令220还可适用于第一集合的源数据元素与第二集合的对应源数据元素的相加,其中对应结果可消耗每个目的地数据元素的多于16位(即使并非全是32位)。
[0039]在图2B中,第一和第二集合的源数据元素分配有顺序次序,代表性地各自示出为0、1、2、3和0'、1'、2'、3'。第一寄存器224x中的第一分量目的地向量操作数保留SIMD指令220的对应于源操作数222和223的偶数编号的源数据元素的结果的第一子集(示出为32位目的地数据元素A和C);且类似地,第二寄存器224y中的第二分量目的地向量操作数保留SIMD指令220的对应于源操作数222和223的奇数编号的源数据元素的结果的第二子集(示出为32位数据元素B和D)。在此情况下,看出第一源向量操作数222和第二源向量操作数223各自的偶数编号的源数据元素(0、0')和(2、2')生成第一目的地向量操作数224x的数据元素A和C;且第一源向量操作数222和第二源向量操作数223各自的奇数编号的数据元素(1、1')和(3、3')生成第二目的地向量操作数224y的数据元素B和D。
[0040]同样,在图2B的第二示范性方面中看出,混合宽度SIMD指令220通过利用单条混合宽度SIMD指令而不是两条或多于两条分量SIMD指令来实现代码空间效率。此外,还看出在此方面中也最小化了跨SIMD通道的移动。大体上,源数据元素的第一集合和源数据元素的第二集合在相应SIMD通道中,且从第一集合的源数据元素中的每一个和第二集合的源数据元素中的对应一个在相应SIMD通道或邻近于相应SIMD通道的SIMD通道中生成目的地数据元素。举例来说,考虑到各自包括源数据元素的第一集合0到3(或源数据元素的第二集合0'到3')的四个16位SIMD通道0到3,第一和第二的源数据元素的用以生成对应目的地数据元素A到D的数据移动包含在相同SIMD通道且最多邻近SIMD通道内(例如,各自在SIMD通道0和2中的偶数编号的源数据元素(0、0')和(2、2')在SIMD通道0到1和2到4中生成目的地数据元素A和C;且类似地,各自在SIMD通道1和3中的奇数编号的源数据元素(1、1')和(3、3')在SIMD通道0到1和2到4中生成目的地数据元素B和D)。
[0041]图2C表示关于混合宽度SIMD指令240的第三示范性方面。不同于混合宽度SIMD指令200和220,混合宽度SIMD指令240的源向量操作数被指定为分量向量操作数对或表达为一寄存器对。应指出,混合宽度SIMD指令240不同于混合宽度SIMD指令220,原因是混合宽度SIMD指令220包含两个单独源向量操作数,其中一个源向量操作数的数据元素被指定为与另一源向量操作数的数据元素交互(例如,相乘)。另一方面,在混合宽度SIMD指令240中,指定分量源向量操作数对,原因是如果不这样做将会消耗两条单独指令。举例来说,SIMD指令240可包括有待对八个16位源数据元素进行的从16位到8位的右移位函数的共同运算以便获得八个8位目的地数据元素的结果(其中SIMD指令240的实施方案可包括例如八个8位右移位器等逻辑元件)。然而,由于八个16位源数据元素消耗128位,因此常规实施方案将使用两条分量SIMD指令分离有待进行的此运算。另一方面,在图2C的示范性方面中,包括第一寄存器242x中的第一分量源向量操作数和第二寄存器242y中的第二分量源向量操作数的源向量操作数对由SIMD指令240指定。因此,代码空间得以有效地使用。
[0042]目的地向量操作数在此情况下表达为单个64位寄存器244且包括是SIMD指令240的结果的八个8位目的地数据元素。因此,对寄存器244中的目的地向量操作数的目的地数据元素分配顺序次序,所述目的地数据元素由附图标记0到7示出。分量源向量操作数对(表达为寄存器对242x、242y)的源数据元素被布置成使得包括源数据元素的第一子集A、C、E和G的第一寄存器242x将生成各自对应于寄存器244中的目的地向量操作数的偶数编号的目的地数据元素0、2、4和6的结果;且包括源数据元素的第二子集B、D、F和H的第二寄存器242y将生成各自对应于寄存器244中的目的地向量操作数的奇数编号的目的地数据元素1、3、5和7的结果。
[0043]因此,通过指定分量源向量操作数对或将源向量操作数表达为寄存器对,可有效地利用代码空间且可最小化跨SIMD通道的数据移动,即使在源向量操作数比目的地向量操作数更宽的情况下也同样如此。还最小化了在执行SIMD指令240时跨SIMD通道的移动。大体上,看出目的地数据元素是在相应SIMD通道中,且从源数据元素在相应SIMD通道或邻近于相应SIMD通道的SIMD通道中生成目的地数据元素中的每一个。举例来说,考虑到八个8位SIMD通道对应于八个目的地数据元素0到7,看出源数据元素A、C、E和G将各自从通道0到1、2到3、4到5和6到7移动以生成对应于SIMD通道中的偶数编号的目的地数据元素0、2、4和6的结果;且源数据元素B、D、F和H将各自从SIMD通道0到1、2到3、4到5和6到7移动以生成对应于SIMD通道中的偶数编号的目的地数据元素1、3、5和7的结果。在任一情况下,移动包含在两个SIMD通道内。
[0044]因此,应了解,各方面包含用于进行本文中所揭示的过程、功能和/或算法的各种方法。举例来说,如图3A中所示出,一方面可包含例如根据图2A到B的进行混合宽度单指令多数据(SIMD)运算的方法300。
[0045]在块302中,方法300包含由处理器(例如,图4的处理器402,其将在下文解释)且例如参考图2A接收SIMD指令(例如,SIMD指令200),所述SIMD指令包括:包括第一位宽(例如,8位)源数据元素的第一集合(例如,源数据元素0到7)的至少第一源向量操作数(在寄存器202中);以及包括第二位宽(例如,16位)目的地数据元素(例如,目的地数据元素A到H)的至少目的地向量操作数(例如,在寄存器对204x、204y中),其中所述第二位宽是所述第一位宽的两倍,其中所述目的地向量操作数包括寄存器对,所述寄存器对包含:包括目的地数据元素的第一子集(例如,目的地数据元素A、C、E、G)的第一寄存器(例如,204x)以及包括目的地数据元素的第二子集(例如,目的地数据元素B、D、F、H)的第二寄存器。
[0046]在块303(其示出包含块304和306)中,方法300进一步包含在处理器中执行混合宽度SIMD指令。具体地说,考虑到在块304中对源数据元素分配的顺序次序(例如,0到7),块306包含在处理器中执行SIMD指令。进一步详细地,块306由可并行进行的分量块306a和306b组成。
[0047]块306a包含从第一集合的偶数编号的源数据元素(例如,源数据元素0、2、4、6)生成第一寄存器(例如,第一寄存器204x)中的目的地数据元素的第一子集(例如,目的地数据元素A、C、E、G)。
[0048]块306b包含从第一集合的奇数编号的源数据元素(例如,源数据元素1、3、5、7)生成第二寄存器(例如,第二寄存器204y)中的目的地数据元素的第二子集(例如,目的地数据元素B、D、F、H)。
[0049]大体上,方法300的SIMD指令可以是第一集合的源数据元素根据一常数值的平方函数、左移位函数、递增或加法中的一个。在方法300中通过利用单条SIMD指令来实现代码空间效率。在方法300中还最小化了跨SIMD通道的移动,其中源数据元素的第一集合是在相应SIMD通道中,且方法300包含从源数据元素中的每一个(例如,SIMD通道0中的源数据元素0)在相应SIMD通道(例如,SIMD通道0)或邻近于相应SIMD通道的SIMD通道(例如,SIMD通道1)中生成目的地数据元素(例如,目的地数据元素A)。
[0050]还将指出,尽管未单独示出,但方法300还可包含用于实施图2B的SIMD指令220的方法,所述方法进一步包括例如在块302中接收第二源向量操作数,所述第二源向量操作数包括第一位宽源数据元素的第二集合(例如,寄存器222和223中的第一和第二源向量操作数),且源数据元素的第一集合的顺序次序对应于源数据元素的第二集合的顺序次序。在此情况下,基于块304中所分配的顺序次序,块306包含在处理器中执行SIMD指令,所述块306包括:块306a,其用于从第一集合的偶数编号的源数据元素和第二集合的偶数编号的源数据元素生成第一寄存器中的目的地数据元素的第一子集;以及块306b,其用于从第一集合的奇数编号的源数据元素和第二集合的偶数编号的源数据元素生成第二寄存器中的目的地数据元素的第二子集。在此情况下,SIMD指令可以是第一集合的源数据元素与第二集合的对应源数据元素的相乘或相加,其中所述源数据元素的第一集合和源数据元素的第二集合是在相应SIMD通道中,且从第一集合的源数据元素中的每一个和第二集合的源数据元素中的对应一个在相应SIMD通道或邻近于相应SIMD通道的SIMD通道中生成目的地数据元素。
[0051]参考图3B,示出用于进行本文中所揭示的过程、功能和/或算法的另一方法。举例来说,如图3B中所示出,方法300包含例如根据图2C的进行混合宽度单指令多数据(SIMD)运算的另一方法。
[0052]在块352中,方法350包含由处理器(例如,处理器402)接收SIMD指令(例如,SIMD指令240),所述SIMD指令包括:包括第一位宽(例如,16位)源数据元素(例如,源数据元素A到H)的至少源向量操作数(例如,在寄存器242x、242y中);以及包括第二位宽(例如,8位)目的地数据元素(例如,目的地数据元素0到7)的至少目的地向量操作数(例如,在寄存器244中),其中所述第二位宽是所述第一位宽的一半,其中所述源向量操作数包括寄存器对,所述寄存器对包含:包括源数据元素的第一子集(例如,目的地数据元素0、2、4、6)的第一寄存器(例如,第一寄存器242x)以及包括源数据元素的第二子集(例如,目的地数据元素1、3、5、7)的第二寄存器(例如,第二寄存器242y)。
[0053]在块354中,对目的地数据元素分配顺序次序,且在块356中执行SIMD指令。块356包含也可并行进行的子块356a和356b。
[0054]块356a包含从第一寄存器中的源数据元素的对应第一子集(例如,源数据元素A、C、E、G)生成偶数编号的目的地数据元素(例如,目的地数据元素0、2、4、6)。
[0055]块356b包含从第二寄存器中的源数据元素的对应第二子集(例如,源数据元素B、D、F、H)生成奇数编号的目的地数据元素(例如,目的地数据元素1、3、5、7)。
[0056]在示范性方面中,方法350的SIMD指令可以是源数据元素的右移位函数,其中目的地数据元素是在相应SIMD通道(例如,SIMD通道0到7)中,且从源数据元素(例如,源数据元素A)在相应SIMD(例如,SIMD通道0)或邻近于相应SIMD通道的SIMD通道(例如,SIMD通道1)中生成目的地数据元素中的每一个(例如,目的地数据元素0)。
[0057]参考图4,根据示范性方面的无线装置400的特定说明性方面的块图。无线装置400包含处理器402,所述处理器402可被配置成(例如,包含执行逻辑)例如各自根据图3A的方法300和图3B方法350支持和实施示范性混合宽度SIMD指令的执行。如图4中所示出,处理器402可与存储器432通信。处理器402可包含寄存器堆(未示出),所述寄存器堆保持对应于寄存器(例如,逻辑寄存器)的物理寄存器,就所述物理寄存器来表达示范性SIMD指令的操作数。在一些方面中,寄存器堆可供应有来自存储器432的数据。尽管未示出,但一或多个高速缓存或其它存储器结构还可包含在无线装置400中。
[0058]图4还示出耦合到处理器402和显示器428的显示控制器426。编解码器(DODEC)434(例如,音频和/或语音CODEC)可耦合到处理器402。还示出例如无线控制器440(其可包含调制解调器)等其它组件。扬声器436和麦克风438可耦合到编解码器434。图4还指示无线控制器440可耦合到无线天线442。在特定方面中,处理器402、显示控制器426、存储器432、编解码器434和无线控制器440包含在封装内系统或芯片上系统装置422中。
[0059]在特定方面中,输入装置430和电力供应器444耦合到芯片上系统装置422。此外,在特定方面中,如图4中所示出,显示器428、输入装置430、扬声器436、麦克风438、无线天线442和电力供应器444在芯片上系统装置422的外部。然而,显示器428、输入装置430、扬声器436、麦克风438、无线天线442和电力供应器444中的每一个可耦合到芯片上系统装置422的组件(例如接口或控制器)。
[0060]应指出,尽管图4描绘无线通信装置,但处理器402和存储器432还可集成到机顶盒、音乐播放器、视频播放器、娱乐单元、导航装置、个人数字助理(PDA)、固定位置数据单元、通信装置或计算机中。此外,无线装置400的至少一或多个示范性方面可集成在至少一个半导体裸片中。
[0061]所属领域的技术人员将了解,可使用多种不同技术和技艺中的任一种来表示信息和信号。举例来说,可通过电压、电流、电磁波、磁场或磁粒子、光场或光粒子或其任何组合来表示在整个上文描述中可能参考的数据、指令、命令、信息、信号、位、码元和芯片。
[0062]此外,所属领域的技术人员将了解,结合本文中所揭示的各方面而描述的各种说明性逻辑块、模块、电路和算法步骤可实施为电子硬件、计算机软件或两者的组合。为清晰地说明硬件与软件的此可互换性,上文已大体上就其功能性来描述了各种说明性组件、块、模块、电路和步骤。此类功能性是实施为硬件还是软件取决于特定应用和强加于整个系统的设计约束。熟练的技术人员可针对每个特定应用以不同方式来实施所描述的功能性,但这样的实施决策不应被解释为会引起脱离本发明的范围。
[0063]结合本文中所揭示的方面描述的方法、序列和/或算法可直接以硬件、以由处理器执行的软件模块或以硬件和软件模块的组合来体现。软件模块可驻留在RAM存储器、快闪存储器、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、可移动磁盘、CD-ROM,或所属领域中已知的任何其它形式的存储媒体中。示范性存储媒体耦合到处理器,使得处理器可从存储媒体读取信息并将信息写入到存储媒体。在替代方案中,存储媒体可与处理器成整体。
[0064]因此,本发明的一方面可包含电脑可读媒体(例如,非暂时性计算机可读存储媒体),其体现用于实施混合宽度SIMD指令的方法(例如,根据上文所描述的方法300和350,用于实施图2A到C的SIMD指令)。因此,本发明不限于所说明的实例,且任何用于执行本文中所描述的功能性的装置包含在本发明的各方面中。
[0065]虽然前述揭示内容示出本发明的说明性方面,但应指出,在不脱离如所附权利要求书界定的本发明的范围的情况下,可在其中做出各种改变和修改。无需以任何特定次序来进行根据本文中所描述的本发明的各方面的方法权利要求的功能、步骤和/或动作。此外,尽管可以单数形式描述或主张本发明的元件,但除非明确陈述限于单数,否则也涵盖复数形式。