English:
[0001] Embodiments of the present disclosure relate to an isolated semiconductor controlled rectifier (SCR) circuit for electrostatic discharge (ESD) protection. A preferred embodiment of the circuit is intended for use at input, output, or input-output terminals having a negative operating voltage with respect to GND or VSS, but the circuit may also be used between power supply terminals such as VDD and GND or VSS terminals of an integrated circuit.
[0002] Referring to FIGS. 1-3, there is an ESD protection circuit of the prior art that is similar to those disclosed by Ker et al. in U.S. Pat. No. 6,765,771. The plan view of FIG. 1 illustrates a dual semiconductor controlled rectifier formed on p-type substrate (PSUB) 102 and surrounded by n-type well (NWELL) 100. The PSUB layer 102 is electrically connected to P+ region 112. The dual SCRs are formed symmetrically above and below P+ region 112, so only the lower SCR will be described in detail. Here and in the following discussion the same reference numerals are used to identify the same or similar circuit elements in the various drawing FIGS.. N+ region 114 is the cathode of the lower SCR and is formed adjacent P+ region 112 within p-type well region 104. P+ region 108 is formed within NWELL 100 and serves as an anode for the lower SCR. N+ region 106 is electrically connected to NWELL 100. Gate region 110 is formed over a boundary between NWELL 100 and PSUB 102. Gate region 110, P+ anode 108, and N+ region 106 are electrically connected to reference terminal 122, which is preferably GND or VSS. P+ region 112 and N+ region 114 are electrically connected to terminal 120, which is preferably an input, output, or input-output terminal to be protected.
[0003] Referring next to FIG. 2, there is a cross sectional diagram of the lower SCR along the plane A - A' as indicated by the line in FIG. 1. The SCR is formed on P-type substrate (PSUB) 200. N-type buried layer (NBL) 101 is formed in PSUB 200 below the surface by ion implantation. Taken together n-type well (NWELL) 100 and NBL 101 form an isolated P-type region (PSUB) 102. The lower SCR includes P+ anode 108 formed in NWELL 100 and N+ cathode 114 formed in p-type well region 104. Active P+ regions 112 and 108, N+ regions 114 and 106, and the channel region below gate 110 are separated by shallow trench isolation (STI) regions 124.
[0004] Turning now to FIG. 3, there is a simplified diagram of the SCR of FIG. 2 showing individual bipolar transistors. Shallow trench isolation (STI) regions are omitted for clarity. The lower SCR of FIG. 2 comprises a vertical SCR and a horizontal SCR. The vertical SCR includes PNP transistor 304 and NPN transistor 306 and forms a vertical current path from P+ anode 108 to NBL 101 via NWELL 100 and back to N+ cathode 114 via PSUB 102. The horizontal SCR includes PNP transistor 300 and NPN transistor 302 and forms a horizontal current path directly from P+ anode 108 to N+ cathode 114. Parasitic resistor 301 is a base-emitter shunt resistor for PNP transistor 300. Parasitic resistor 303 is a base-emitter shunt resistor for NPN transistors 302 and 306.
[0005] Several problems arise with operation of the SCR of FIGS. 1-3 that limit operating voltage, gain of the SCR, and introduce reliability problems as will become apparent in the following discussions. Various embodiments of the invention are directed to solving these problems and improving operation of the SCR without increasing process complexity.
[0007] FIG. 1 (Prior Art) is a plan view of a known enclosed semiconductor controlled rectifier (SCR) of an electrostatic discharge (ESD) protection circuit;
[0008] FIG. 2 (Prior Art) is a cross section view taken along the line A - A' of FIG. 1;
[0009] FIG. 3 (Prior Art) is a schematic diagram showing individual transistors of the SCR of FIG. 2;
[0010] FIG. 4A is a cross section view of a first example embodiment implementing principles of the invention;
[0011] FIG. 4B is a current-voltage diagram of the SCR of FIG. 4A;
[0012] FIG. 5A is a cross section view of a second example embodiment;
[0013] FIG. 5B is a doping profile of p-type well 104 of FIG. 5 A;
[0014] FIGS. 6A-6C are cross section views of a third example embodiment;
[0015] FIG. 7 is a cross section view of a fourth example embodiment; and
[0016] FIG. 8 is a cross section view of a fifth example embodiment.
[0017] Example embodiments implementing principles of the invention provide significant advantages over conventional electrostatic discharge (ESD) protection circuits.
[0018] FIG. 4A illsutrates a first example embodiment of a semiconductor controlled rectifier (SCR) of the invention. Here, SCR refers to a semiconductor controlled rectifier of which a silicon controlled rectifier is a special case. In general, heavily doped means a semiconductor region having a concentration of lei 8 Acm-3or greater. Likewise, lightly doped means a semiconductor region having a concentration of less than lei 8 Acm"3. In both cases, the doped regions may be formed by ion implantation or other methods as are well known to those having ordinary skill in the art.
[0020] A problem with the SCR of FIGS. 1-3 is the limited operating voltage at terminal 120 with respect to reference terminal 122. Present analog circuits may require an operating voltage of -10 V or more at terminal 120 with respect to reference terminal 122. For small feature sizes, however, it was discovered that -6 V applied to terminal 120 with respect to reference terminal 122 would fully deplete lightly doped PSUB region 102 and cause collector-emitter punch through of NPN transistor 306. This problem is solved by a first embodiment of the invention in which p-type region (PBL) 400 is preferably formed by ion implantation between p-type region 104 and NBL 101. PBL 400 is preferably formed with an impurity concentration between that of p-type region 104 and PSUB 102. If the PBL concentration is too low, collector-emitter punch through of NPN transistor 306 may still occur within the operating voltage range of terminal 120. Alternatively, if the concentration of PBL 400 is too high, lateral collector-base avalanche conduction of NPN transistor 302 will occur.
[0021] FIG. 4B illustrates a current-voltage diagram of the SCR of FIG. 4A. The absolute voltage at terminal 120 with respect to terminal 122 is shown along the horizontal axis. The absolute current between terminal 120 and 122 is shown along the vertical axis. It is important to note that the trigger voltage of the SCR is now 16 V, rather than 6 V, with no evidence of collector-emitter punch through. Moreover, the holding voltage of the SCR is less than 1 V to provide effective protection against electrostatic discharge (ESD).
[0022] FIG. 5 A illustrates a second embodiment. Here, p-type well layer 104 is modified according the impurity concentration diagram of FIG. 5B. The original doping profile is produced by a Boron implant dose of 4el2 Acm"2and energy of 15 keV. In addition, a second Boron implant dose of 1.8el2 Acm"2and energy of 47 keV and a third Boron implant dose of 2el2 Acm"2and energy of 115 keV are performed. The three implants produce three respective overlapping Gaussian distributions of FIG. 5A. The first and original implant produces a maximum concentration of 1.8el6 Acm-3 at 0.5 um. The second implant produces a maximum concentration of 1.5el6 Acm-3 at 1.6 um. The third implant produces a maximum concentration of 1.0el6 Acm-3 at 3.4 um. The resulting doping profile of FIG. 5 A advantageously prevents collector-emitter punch through of NPN transistor 306 to -20 V at terminal 120 with respect to reference terminal 122. The progressively decreasing concentration of Boron with increasing implant depth advantageously prevents collector- base avalanche conduction of NPN transistor 306. Since the maximum Boron concentration of the second and third implants is no greater than the original implant, no lateral collector- base avalanche of NPN transistor 302 will occur. Finally, no additional masks are required for the second and third Boron implants.
[0023] FIG. 6A illustrates a third embodiment of the invention. The operating voltage of the SCR of FIGS. 1-3 is limited by the electric field between gate 110 and p-type well region 104. This limitation becomes increasingly significant as the dielectric thickness under gate 110 decreases. In the embodiment of FIG. 6A, gate 110 may be necessary when a metal silicide layer is formed over active regions 106, 108, 112, 114, and gate 110. The gate 110 prevents metal silicide formation that might otherwise short p-type well region 104 to NWELL 100. In the embodiment of FIG. 6A, a lightly doped p-type well region 600 is formed by ion implantation between p-type well region 104 and NWELL 100. P-type well region 600 is electrically connected to p-type well region 104 and extends NWELL 100. Region 600 is preferably more lightly doped than either of p-type well region 104 or NWELL 100 to avoid avalanche conduction with NWELL 100. During normal circuit operation, when terminal 120 is negative with respect to terminal 122, an inversion layer connected to NWELL 100 forms at the surface of p-type well region 600. This advantageously avoids any high electric field across the dielectric layer under gate 110 during normal circuit operation as well as during ESD events.
[0024] FIG. 6B further illustrates the third embodiment. Here, when the space between SCR anode 108 and cathode 114 is sufficiently large it is possible to omit implant region 600 so that region 602 is an extension of PSUB 102. Isolation region 604 may also be optionally omitted to improve the gain of the horizontal SCR. As with FIG. 6A, an inversion layer connected to NWELL 100 forms at the surface of p-type region 602. This advantageously avoids any high electric field across the dielectric layer under gate 110 during normal circuit operation as well as during ESD events.
[0025] FIG. 6C further illustrates the third embodiment. In the embodiment of FIG. 6C, a lightly doped n-type well region 606 is formed by ion implantation between p-type well region 104 and NWELL 100. N-type well region 606 is electrically connected to NWELL 100 and extends to p-type well region 104. Region 606 is preferably more lightly doped than either of p-type well region 104 or NWELL 100 to avoid avalanche conduction with p-type well region 104. During normal circuit operation, when terminal 120 is negative with respect to terminal 122, region 606 under gate 110 remains in accumulation and connected to NWELL 100. This advantageously avoids any high electric field across the dielectric layer under gate 110 during normal circuit operation as well as during ESD events. Alternatively, when not limited by punch through and avalanche conduction, NWELL 100 may be extended to the left to underlie gate 110.
[0026] FIG. 7 illustrates a fourth embodiment. Here, gate 110 and STI 404 (FIG. 6) are removed. Silicide blocking layer 710 is formed over portions of p-type well region 104 and NWELL 100 between N+ cathode 114 and P+ anode 108. The silicide blocking layer is preferably a thin deposited dielectric layer such as Si02or a composite dielectric of Si02and SiN. The silicide blocking layer 710 advantageously prevents formation of metal silicide that would otherwise short p-type well 104 to NWELL 100. Moreover, gate 110 is removed so there is no high electric field across the dielectric layer 710 during normal circuit operation as well as during ESD events. Removal of STI region 404 advantageously improves the gain of the lateral SCR (FIG. 3) by creating a more direct collector-emitter current path for NPN transistor 302.
[0027] FIG. 8 illustrates a fifth embodiment. Recall from the discussion of FIG. 3 that resistor 301 is a base-emitter shunt resistor for lateral PNP transistor 300. The present inventors have determined that the gain, trigger voltage, and holding voltage of the lateral SCR formed by PNP transistor 300 and NPN transistor 302 are significantly affected by the value of shunt resistor 301. In order to improve these characteristics of the SCR, p-type (PWELL) region 800 is formed by ion implantation below and electrically connected to P+ anode 108. PWELL region 800 has a slightly higher impurity concentration than NWELL 100 and preferably extends to NBL 101. However, one of ordinary skill in the art having access to the instant specification will understand that SCR characteristics are improved even when PWELL 800 extends any distance below P+ anode 108. This improvement is due to an increase in the value of resistor 301, since the current path through resistor 301 must flow through NWELL 100, below PWELL 800, and up to N+ well contact 106. Therefore, the maximum increase in the value of resistor 301 is advantageously achieved when PWELL 800 extends to NBL 101.
[0028] Although the foregoing discussion is directed to an SCR having a negative operating voltage at terminal 120 with respect to reference terminal 122, principles of the invention are equally applicable to an SCR having a positive operating voltage at an input, input-output, or output terminal such as terminal 122 with respect to a reference terminal such as terminal 120.
[0029] Those skilled in the art will appreciate that modifications may be made to the described embodiments, and also that many other embodiments are possible, within the scope of the claimed invention.

中文:
[0001]本发明的实施例涉及一种用于静电放电(ESD)保护的隔离式半导体控制整流器(SCR)电路。所述电路的优选实施例既定供在相对于GND或VSS具有负操作电压的输入、输出或输入-输出端子处使用,但所述电路也可在电力供应端子(例如集成电路的VDD及GND或VSS端子)之间使用。
[0002]参考图1-3,其为现有技术的ESD保护电路,所述ESD保护电路类似于科尔(Ker)等人在第6,765,771号美国专利中所揭示的ESD保护电路。图1的平面图图解说明形成于p型衬底(PSUB)102上且由n型阱(NWELL)100环绕的双重半导体控制整流器。PSUB层102电连接到P+区112。所述双重SCR在P+区112上方及下方对称地形成,因此将详细地描述下部SCR。此处及在以下论述中,使用相同参考编号来识别各图式图中相同或类似的电路元件。N+区114是下部SCR的阴极且在p型阱区104内邻近于P+区112而形成。P+区108形成于NWELL 100内且充当下部SCR的阳极。N+区106电连接到NWELL 100。栅极区110形成于NWELL 100与PSUB 102之间的边界上方。栅极区110、P+阳极108及N+区106电连接到参考端子122,参考端子122优选地为GND或VSS。P+区112及N+区114电连接到端子120,端子120优选地为待受保护的输入、输出或输入-输出端子。
[0003]接下来参看图2,其为下部SCR沿着如图1中的线所指示的平面A-A’的横截面图。所述SCR形成于P型衬底(PSUB)200上。N型掩埋层(NBL)101是通过离子植入而形成于PSUB 200中位于表面下方。总的来说,n型阱(NWELL)100与NBL 101形成隔离式P型区(PSUB)102。下部SCR包含形成于NWELL 100中的P+阳极108及形成于p型阱区104中的N+阴极114。作用P+区112及108、N+区114及106以及栅极110下方的沟道区由浅沟槽隔离(STI)区124分离。
[0004]现在转到图3,其为图2的SCR的简化图,其展示个别双极晶体管。为清晰起见省略了浅沟槽隔离(STI)区。图2的下部SCR包括垂直SCR及水平SCR。垂直SCR包含PNP晶体管304及NPN晶体管306且形成从P+阳极108经由NWELL 100到NBL 101并经由PSUB 102返回到N+阴极114的垂直电流路径。水平SCR包含PNP晶体管300及NPN晶体管302且形成直接从P+阳极108到N+阴极114的水平电流路径。寄生电阻器301为PNP晶体管300的基极-射极分流电阻器。寄生电阻器303为NPN晶体管302及306的基极-射极分流电阻器。
[0005]关于图1-3的SCR的操作会出现数个问题,其限制操作电压、SCR的增益,并引入可靠性问题,如在以下论述中将变得显而易见。本发明的各种实施例针对于解决这些问题且改善SCR的操作,而不会增加工艺复杂度。
[0007]图1(现有技术)是静电放电(ESD)保护电路的已知包封式半导体控制整流器(SCR)的平面图;
[0008]图2(现有技术)是沿着图1的线A-A’截取的横截面图;
[0009]图3(现有技术)是展示图2的SCR的个别晶体管的示意图;
[0010]图4A是实施本发明的原理的第一实例性实施例的横截面图;
[0011]图4B是图4A的SCR的电流-电压图;
[0012]图5A是第二实例性实施例的横截面图;
[0013]图5B是图5A的p型阱104的掺杂分布曲线;
[0014]图6A-6C是第三实例性实施例的横截面图;
[0015]图7是第四实例性实施例的横截面图;及
[0016]图8是第五实例性实施例的横截面图。
[0017]实施本发明的原理的实例性实施例提供胜过常规静电放电(ESD)保护电路的显著优点。
[0018]图4A图解说明本发明的半导体控制整流器(SCR)的第一实例性实施例。本文中,SCR指代半导体控制整流器,硅控制整流器是其特例。一般来说,经重掺杂意指半导体区具有1e18Acm-3或更大的浓度。同样地,经轻掺杂意指半导体区具有小于1e18Acm-3的浓度。在两种情况中,均可通过离子植入或如所属领域的普通技术人员所熟知的其它方法来形成经掺杂区。
[0020]关于图1-3的SCR的问题是端子120处相对于参考端子122的有限操作电压。目前的模拟电路可需要端子120处相对于参考端子122为-10V或更大的操作电压。然而,对于小特征大小,已发现相对于参考端子122施加到端子120的-6V电压将使经轻掺杂PSUB区102完全耗尽且引起NPN晶体管306的集极-射极穿通。此问题通过其中优选地通过在p型区104与NBL 101之间进行离子植入来形成p型区(PBL)400的本发明第一实施例来解决。PBL 400优选地以介于p型区104的杂质浓度与PSUB 102的杂质浓度之间的杂质浓度来形成。如果PBL浓度过低,那么在端子120的操作电压范围内仍可发生NPN晶体管306的集极-射极穿通。或者,如果PBL 400的浓度过高,那么将发生NPN晶体管302的横向集极-基极雪崩导通。
[0021]图4B图解说明图4A的SCR的电流-电压图。沿着水平轴来展示端子120处相对于端子122的绝对电压。沿着垂直轴来展示端子120与122之间的绝对电流。重要的是应注意,SCR的触发电压现在是16V而非6V,并无证据表明发生集极-射极穿通。此外,SCR的保持电压小于1V以提供防御静电放电(ESD)的有效保护。
[0022]图5A图解说明第二实施例。此处,根据图5B的杂质浓度图来对p型阱层104进行改质。原始掺杂分布曲线是由4e12Acm-2的硼植入剂量及15keV的能量产生的。另外,执行1.8e12Acm-2的第二硼植入剂量及47keV的能量以及2e12Acm-2的第三硼植入剂量及115keV的能量。三次植入产生图5A的三个相应重叠高斯分布。第一及原始植入在0.5μm处产生1.8e16Acm-3的最大浓度。第二植入在1.6μm处产生1.5e16Acm-3的最大浓度。第三植入在3.4μm处产生1.0e16Acm-3的最大浓度。在端子120处相对于参考端子122达-20V的范围内,图5A的所得掺杂分布曲线均有利地防止NPN晶体管306的集极-射极穿通。随着植入深度的增加逐渐减小的硼浓度有利地防止NPN晶体管306的集极-基极雪崩导通。由于第二及第三植入的最大硼浓度也大于原始植入,因此将不会发生NPN晶体管302的横向集极-基极雪崩。最后,第二及第三硼植入不需要额外掩模。
[0023]图6A图解说明本发明的第三实施例。图1-3的SCR的操作电压受栅极110与p型阱区104之间的电场限制。随着栅极110下方的电介质厚度减小,此限制变得越来越显著。在图6A的实施例中,当在作用区106、108、112、114及栅极110上方形成金属硅化物层时,栅极110可为必要的。栅极110防止形成原本可将p型阱区104短接到NWELL 100的金属硅化物。在图6A的实施例中,通过在p型阱区104与NWELL 100之间进行离子植入来形成经轻掺杂p型阱区600。P型阱区600电连接到p型阱区104且使NWELL 100延伸。区600的掺杂优选地比p型阱区104或NWELL 100的掺杂轻以避免由于NWELL 100而发生雪崩导通。在正常电路操作期间,当端子120相对于端子122为负时,在p型阱区600的表面处形成连接到NWELL 100的反转层。这在正常电路操作期间以及在ESD事件期间有利地避免跨越栅极110下方的电介质层出现任何高电场。
[0024]图6B进一步图解说明第三实施例。此处,当SCR阳极108与阴极114之间的空间足够大时,可省略植入区600使得区602是PSUB 102的延伸部。也可任选地省略隔离区604以改善水平SCR的增益。与图6A一样,在p型区602的表面处形成连接到NWELL 100的反转层。这在正常电路操作期间以及在ESD事件期间有利地避免跨越栅极110下方的电介质层出现任何高电场。
[0025]图6C进一步图解说明第三实施例。在图6C的实施例中,通过在p型阱区104与NWELL 100之间进行离子植入来形成经轻掺杂n型阱区606。N型阱区606电连接到NWELL 100且延伸到p型阱区104。区606的掺杂优选地比p型阱区104或NWELL 100中的任一者轻以避免由于p型阱区104而发生雪崩导通。在正常电路操作期间,当端子120相对于端子122为负时,栅极110下方的区606保持处于积累状态且连接到NWELL 100。这在正常电路操作期间以及在ESD事件期间有利地避免跨越栅极110下方的电介质层出现任何高电场。或者,当不受穿通及雪崩导通限制时,NWELL 100可向左延伸以位于栅极110下方。
[0026]图7图解说明第四实施例。此处,栅极110及STI 404(图6)被移除。硅化物阻挡层710形成于p型阱区104及NWELL 100的介于N+阴极114与P+阳极108之间的部分上方。所述硅化物阻挡层优选地为薄的经沉积电介质层,例如SiO2或SiO2与SiN的复合电介质。硅化物阻挡层710有利地防止形成原本将p型阱104短接到NWELL 100的金属硅化物。此外,栅极110被移除,因此在正常电路操作期间以及在ESD事件期间跨越电介质层710不存在高电场。STI区404的移除通过为NPN晶体管302形成更直接的集极-射极电流路径而有利地改善横向SCR(图3)的增益。
[0027]图8图解说明第五实施例。根据对图3的论述回想起,电阻器301是横向PNP晶体管300的基极-射极分流电阻器。本发明人已确定,由PNP晶体管300及NPN晶体管302形成的横向SCR的增益、触发电压及保持电压受分流电阻器301的值的显著影响。为了改善SCR的这些特性,通过在P+阳极108下方进行离子植入来形成p型(PWELL)区800并将其电连接到P+阳极108。PWELL区800具有比NWELL 100稍高的杂质浓度且优选地延伸到NBL 101。然而,可以获知本说明书的所属领域的普通技术人员将理解,甚至当PWELL 800在P+阳极108下方延伸达任何距离时,SCR特性也得以改善。此改善归因于电阻器301的值的增加,因为穿过电阻器301的电流路径必须流动穿过NWELL 100、穿过PWELL 800下方且向上到达N+阱触点106。因此,在PWELL 800延伸到NBL 101时,有利地实现电阻器301的值的最大增加。
[0028]虽然前述论述是针对于在端子120处相对于参考端子122具有负操作电压的SCR,但本发明的原理同等适用于在输入、输入-输出或输出端子(例如端子122)处相对于参考端子(例如端子120)具有正操作电压的SCR。
[0029]所属领域的技术人员将了解,在所主张发明的范围内,可对所描述实施例做出修改,并且许多其它实施例为可能的。