English:
[0001] The present disclosure relates to circuitry for memory devices, and more specifically, to circuitry to adjust delays in input processing for received instructions that may be used in a memory device.
[0002] Random access memory (RAM) devices, such as the ones that may be employed in electrical devices to provide data processing and/or storage, may provide direct availability to addressable data stored in memory circuitry of the device. Certain RAM devices, such as dynamic RAM (DRAM) devices may, for example, have multiple memory banks having many addressable memory elements. RAM devices may also have a command interface that may receive addresses and instructions (e.g., read, write, etc.) for operations that may be associated with those addresses and decoding circuitry that may process the instructions and the addresses to access the corresponding memory banks.
[0003] The instructions and addresses to a RAM device may be provided by processing circuitry of an electrical device external to the RAM device. The electrical device may also provide clocking signals that may be synchronous with the instructions and addresses. For example, an edge of a clocking signal may occur in a moment in which an address signal is stable and, thus, should be read by the RAM device. Accordingly, the RAM device may include circuitry that monitors received clocking signals, and reads the address and/or instructions when the clocking signals are received. Due to unknown latencies, such circuitry may include delays to the processing of the received instructions and addresses. Such delays may increase the overall latency of the RAM device and increase power consumption during operation of the RAM device.
[0005] FIG. 1 is a block diagram illustrating an organization of a memory device that may benefit from a faster access time (tAA), in accordance with an embodiment;
[0006] FIG. 2 illustrates a block diagram of circuitry that may be used to latch a chip select (CS) signal and/or the command/address (CA) signal based on a received clock signal and includes delay elements that may lead to faster tAA, in accordance with an embodiment;
[0007] FIG. 3 A illustrates a block diagram for a memory device coupled to a memory driver to perform read training, in accordance with an embodiment;
[0008] FIG. 3B illustrates a timing diagram illustrating the effect of an increased delay in a CS signal during a read training process, in accordance with an embodiment; and
[0009] FIG. 4 illustrates a method for adjustments of delays during read training to reduce tAA, in accordance with an embodiment.
[0010] One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation- specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.
[0011] Many electrical devices may include random access memory (RAM) devices that are coupled to processing circuitry, and may provide storage of data for processing. Examples of RAM devices include dynamic RAM (DRAM) devices and synchronous DRAM (SDRAM) devices, which may store individual bits electronically. The stored bits may be organized into addressable memory elements (e.g., words), which may be directly accessed by the processing circuitry. Memory devices may also include command circuitry to receive instructions and/or addresses from the processing circuitry. For example, in double data rate type five (DDR5) SDRAM devices, instructions and addresses may be provided by using a 14 bit command/address (CA) signal. Processing circuitry may also provide clocking signals to the memory device along with instructions and/or addresses. In DDR5 SDRAM devices, such a clocking signal Clk may be provided by a differential signal pair Clk t and Clk s. The clocking signal may provide information to the memory device about when an instruction and/or an address signal is ready to be processed. For example, processing circuitry may provide a clocking signal and instructions to a DDR5 SDRAM device such that the CA signal may be available (e.g., stable, ready) for processing during a transition (e.g., edge) of the Clk signal. A DDR5 SDRAM device, as well as other memory devices configured to share instruction buses, may also receive a chip select (CS) signal, which may inform the memory device that it is the intended destination of the CA signal available on the instruction bus. Moreover, in some standards, such as in the DDR5 standard, commands may be provided using a two-cycle (e.g., two-step) CA signal. In such cases, the CS signal may be used to indicate to the memory device that the current CA signal, the first part or the second instruction in a two-cycle cycle CA signal.
[0012] The delay between the data request with CS or CA signals, and the reception of data in a memory device, may be referred to as access time (tAA). Generally, the tAA may depend on the processing times of the received CS and/or CA signals. Processing of CS and CA signals may be performed in accordance with a received clocking signal Clk, and may be susceptible to lags and delays in the input circuitry of the memory devices and delays that may compensate for any unknown latencies. Embodiments described herein discuss memory devices that may have adjustable delays, which may be used to reduce an overall latency in the initial processing of CS and/or CA signals. For example, input circuitry in the memory device may have latches that store the received CA and CS signals as clocked by the Clk signal. Input delays in the Clk, CA, and CS signals may be added and/or adjusted to decrease the tAA by, for example, increasing CS delays and decreasing CA delays. The delays may be adjusted during and/or following a training process, during which a memory device may determine latencies and may adjust skew between CS, CA, and Clk signals. This adjustment of delays may lead to reduced tAA, leading to a decrease in power consumption and/or other resources of the memory device.
[0013] As an example, consider a memory device in which a CA signal may be latched based on a received CS signal, which itself may be latched. Delays in the processing of the CS signal to instruct latching of the CA signal may lead to a skew (e.g., time difference) between the latching of the CA signal and a latching of the CS signal. As detailed below, an increase in the delay of the latching of the CS signal may be accompanied by a decrease in the delay of the latching of the CA signal, which may reduce the skew and the tAA (e.g., an access time between receiving the CA signals and providing the requested data). Moreover, as further detailed below, a training mode during the coupling between a user circuitry (e.g., a processor) may cause an anticipation of the CS signal, further reducing the tAA. Note that, while the description of the embodiments relate to DDR5 SDRAM devices and chip select and command and address signals, these systems may be adapted to input stages of other synchronous digital circuitry that may benefit from a reduced latency in the input by means of addition of specific delays and/or presence of training processes.
[0014] Turning now to the figures, FIG. 1 is a simplified block diagram illustrating certain features of a memory device 10. Specifically, the block diagram of FIG. 1 is a functional block diagram illustrating certain functionality of the memory device 10. In accordance with one embodiment, the memory device 10 may be a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM) device. Various features of DDR5 SDRAM allow for reduced power consumption, more bandwidth and more storage capacity compared to prior generations of DDR SDRAM.
[0015] The memory device 10, may include a number of memory banks 12. The memory banks 12 may be DDR5 SDRAM memory banks, for instance. The memory banks 12 may be provided on one or more chips (e.g., SDRAM chips) that are arranged on dual inline memory modules (DFMMS). Each DFMM may include a number of SDRAM memory chips (e.g., x8 or xl6 memory chips), as will be appreciated. Each SDRAM memory chip may include one or more memory banks 12. The memory device 10 represents a portion of a single memory chip (e.g., SDRAM chip) having a number of memory banks 12. For DDR5, the memory banks 12 may be further arranged to form bank groups. For instance, for an 8 gigabyte (GB) DDR5 SDRAM, the memory chip may include 16 memory banks 12, arranged into 8 bank groups, each bank group including 2 memory banks. For a 16GB DDR5 SDRAM, the memory chip may include 32 memory banks 12, arranged into 8 bank groups, each bank group including 4 memory banks, for instance. Various other configurations, organization and sizes of the memory banks 12 on the memory device 10 may be utilized depending on the application and design of the overall system.
[0017] As will be appreciated, the command interface 14 may include a number of circuits, such as a clock input circuit 18, command address input circuit 20, and chip select input circuit 21, for instance, to ensure proper handling of the signals 15. Input circuits 18, 20, and 21 may, for example, perform synchronous latching to provide stable signals 15 for further processing by the memory device 10. The command interface 14 may receive one or more clock signals from an external device. Generally, double data rate (DDR) memory utilizes a clock signal referred to herein as Clk signal 52, which may be provided as a differential pair formed by true clock signal (Clk t) and the complementary clock signal (Clk c). The positive clock edge for Clk signal 52 in DDR refers to the point where the rising true clock signal Clk t crosses the falling complementary clock signal Clk c, while the negative clock edge indicates that transition of the falling true clock signal Clk t and the rising of the complementary clock signal Clk c.
[0018] The clock input circuit 18 receives the true clock signal (Clk t) and the complementary clock signal (Clk c) and generates an internal clock signal CLK 54. The internal clock signal CLK 54 may be supplied to an internal clock generator, such as a delay locked loop (DLL) circuit 30. The DLL circuit 30 generates a phase controlled internal clock signal LCLK based on the received internal clock signal CLK 54. The phase controlled internal clock signal LCLK is supplied to the I/O interface 16, for instance, and is used as a timing signal for determining an output timing of read data. The internal clock signal CLK 54 may also be provided to various other components within the memory device 10 and may be used to generate various additional internal clock signals. For instance, the internal clock signal CLK 54 may be provided to a command decoder 32. The command decoder 32 may receive command signals from the command bus 34 and may decode the command signals to provide various internal commands. The received command signals may be provided to the command bus 34 from latched inputs in input circuits 18, 20, and 21.
[0019] Further, the command decoder 32 may decode commands, such as read commands, write commands, mode-register set commands, activate commands, etc., and provide access to a particular memory bank 12 corresponding to the command, via the bus path 40. As will be appreciated, the memory device 10 may include various other decoders, such as row decoders and column decoders, to facilitate access to the memory banks 12. In one embodiment, each memory bank 12 includes a bank control block 22 which provides the necessary decoding (e.g., row decoder and column decoder), as well as other features, such as timing control and data control, to facilitate the execution of commands to and from the memory banks 12.
[0020] The memory device 10 executes operations, such as read commands and write commands, based on the command/address signals received from an external device, such as a processor. In one embodiment, the command/address (CA) bus may be a 14-bit bus to accommodate the command/address signals 58 (CA). The command/address signals are clocked to the command interface 14 using the clock 52 (Clk t and Clk c), as discussed above. The command interface 14 may include a command address input circuit 20 which is configured to receive and transmit the commands to provide access to the memory banks 12, through the command decoder 32, for instance. In addition, the command interface 14 may receive a chip select signal (CS). The CS signal 56 enables the memory device 10 to process commands on the incoming CA bus. Access to specific banks 12 within the memory device 10 is encoded on the CA bus with the commands. As an example, a processor requesting data from memory device 10 may provide a CS enable signal 56 via an input pin to inform the memory device 10 that it should operate on the CA signal 58 available in the bus. To this end, the command interface 14 may gate the CA signal 58 based on the received chip select signal 56 and provide the gated CA signal to the memory banks 12 via the bus 40. Based on the CA signal 58, the memory banks 12 may provide the requested data via data path 46 and I/O interface 16. The tAA may be measured as the time between receiving the CA signal 58 and providing the requested data. For example, an access time tAA may be in a range between about 14 and about 18ns. As detailed below, delay circuitry may be placed in a CS input circuit 21 to reduce tAA by increasing a delay in the CS signal processing path. The CS input circuit 21 in command interface 15 may further perform a CS training routine to determine and/or cause an advancement of the CS signal in view of the latency in of the CS signal 56 with respect to the Clk signal 52. As briefly discussed above, and detailed below, the CS training routine may be used to further decrease the tAA in the memory device 10.
[0021] In addition, the command interface 14 may be configured to receive a number of other command signals. For instance, a command/address on die termination (CA ODT) signal may be provided to facilitate proper impedance matching within the memory device 10. A reset command (RESET) may be used to reset the command interface 14, status registers, state machines and the like, during power-up for instance. The command interface 14 may also receive a command/address invert (CAI) signal which may be provided to invert the state of command/address signals CA on the command/address bus, for instance, depending on the command/address routing for the particular memory device 10. A mirror (MIR) signal may also be provided to facilitate a mirror function. The MIR signal may be used to multiplex signals so that they can be swapped for enabling certain routing of signals to the memory device 10, based on the configuration of multiple memory devices in a particular application. Various signals to facilitate testing of the memory device 10, such as the test enable (TEN) signal, may be provided, as well. For instance, the TEN signal may be used to place the memory device 10 into a test mode for connectivity testing.
[0022] The command interface 14 may also be used to provide an alert signal (ALERT) to the system processor or controller for certain errors that may be detected. For instance, an alert signal (ALERT) may be transmitted from the memory device 10 if a cyclic redundancy check (CRC) error is detected. Other alert signals may also be generated. Further, the bus and pin for transmitting the alert signal (ALERT) from the memory device 10 may be used as an input pin during certain operations, such as the connectivity test mode executed using the TEN signal, as described above.
[0023] Data may be sent to and from the memory device 10, utilizing the command and clocking signals discussed above, by transmitting and receiving data signals 44 through the IO interface 16. More specifically, the data may be sent to or retrieved from the memory banks 12 over the data path 46, which includes a plurality of bi-directional data buses. Data IO signals, generally referred to as DQ signals, are generally transmitted and received in one or more bidirectional data busses. For certain memory devices, such as a DDR5 SDRAM memory device, the IO signals may be divided into upper and lower bytes. For instance, for a xl6 memory device, the IO signals may be divided into upper and lower IO signals (e.g., DQ and DQ) corresponding to upper and lower bytes of the data signals, for instance.
[0025] An impedance (ZQ) calibration signal may also be provided to the memory device 10 through the IO interface 16. The ZQ calibration signal may be provided to a reference pin and used to tune output drivers and ODT values by adjusting pull-up and pull-down resistors of the memory device 10 across changes in process, voltage and temperature (PVT) values. Because PVT characteristics may impact the ZQ resistor values, the ZQ calibration signal may be provided to the ZQ reference pin to be used to adjust the resistance to calibrate the input impedance to known values. As will be appreciated, a precision resistor is generally coupled between the ZQ pin on the memory device 10 and G D/VSS external to the memory device 10. This resistor acts as a reference for adjusting internal ODT and drive strength of the IO pins.
[0026] In addition, a loopback signal (LOOPBACK) may be provided to the memory device 10 through the IO interface 16. The loopback signal may be used during a test or debugging phase to set the memory device 10 into a mode wherein signals are looped back through the memory device 10 through the same pin. For instance, the loopback signal may be used to set the memory device 10 to test the data output (DQ) of the memory device 10. Loopback may include both a data and a strobe or possibly just a data pin. This is generally intended to be used to monitor the data captured by the memory device 10 at the IO interface 16.
[0027] As will be appreciated, various other components such as power supply circuits (for receiving external VDD and VSS signals), mode registers (to define various modes of programmable operations and configurations), read/write amplifiers (to amplify signals during read/write operations), temperature sensors (for sensing temperatures of the memory device 10), etc., may also be incorporated into the memory system 10. Accordingly, it should be understood that the block diagram of FIG. 1 is only provided to highlight certain functional features of the memory device 10 to aid in the subsequent detailed description.
[0028] With the foregoing in mind, the electrical circuit 100 in FIG. 2 illustrates a portion of the clock input circuit 18, the command address input circuit 20, and chip select input circuit 21. Electrical circuit 100 illustrates processing circuitry 102 that receive the Clk signal 52 as the differential pair Clk t and Clk c, and provides a digital clock signal CLK 54. Processing circuitry 102 may include a differential amplifier that converts the differential pair Clk t and Clk c into a digital signal. Processing circuitry 102 may also include a buffer that may stabilize the digital clock signal CLK 54. Electrical circuit 100 also illustrates an input buffer 106 that stabilizes the received CS signal 56, for utilization by the circuity. Similarly, electrical circuit 100 illustrates a buffer 108 that stabilizes the CA signal 58, for utilization by the circuitry. CS signal 56 and CA signal 58 may be further stabilized by the use of CS latch 116 and CA latch 118. CS latch 116 may be used to provide a latched CS signal 117, and CA latch 118 may be used to provide a latched signal 119. As detailed above, the latches 116 and 118 may store signals that were intended to be captured during an edge of CLK 54, and thus, are stable signals that may be properly used by the SDRAM device 10.
[0029] To obtain the latched CS signal 117, CS signal 107 from buffer 106 may be available to a data input of CS latch 116. The data may be delayed by a CS delay 126. The CS delay 126 may be a fixed or a programmable delay circuit. CS latch 116 may latch the received CS signal according to CLK 54. The CS delay 126 may be adjusted such that CS latch 116 may latch CS signal 56 when appropriately latched by CLK 54, as determined during a CS training process. Further, the CS delay 126 may be adjusted to cause a device coupled with the memory to advance the CS signal 56 during the training process, as detailed below. Also, the delays 122, 126, and 128 may be adjusted dynamically or pre adjusted such that the latencies in the pipeline are matched. For example, a latency between the CS input buffer 106 and gate 150 may be matched to a latency between the processing circuitry 102 and the gate 150. Moreover, a latency between processing circuitry 102 and latch 118 may match the latency between CA buffer 108 and latch 118. Further, the latched CS signal 117 and latched CA signal 119 may be made available with a clock skew, based on the configuration of the delay elements.
[0030] CS signal 107 from buffer 106 may also be used to gate off the CLK 54 from other circuitry, such as the CA input circuitry 20. Such gating may be used to prevent the memory device 10 from processing a CA signal 58. The CS signal 107 from the CS input circuitry 106 may travel through a first half-latch circuitry 132 and a second half-latch circuitry 134 coupled via an inverting buffer 136. The first half-latch circuitry 132 may latch CS signal using a CLK signal 54. The second half-latch circuitry 134 may latch the CS signal from inverter 136 using a delayed version of CLK signal 54, provided by CLK delay 122. CLK delay 122 may be fixed or programmable circuitry, and may be adjusted such that the CLK signal received in node 142 may correspond to the CS signal received in node 140. The CS signal latched in second half-latch circuitry 134, illustrated in node 146, may gate the delay clock signal in node 144 to produce a gated clock signal 148.
[0031] Gated clock signal 148 may be used to latch the CA signal 58. The gated clock signal 148 may be transmitted to CA latch 118 by a transmission line 152 which may have buffers 154. The transmission line 152 and buffers 154 may generate a latency between the gated clock signal 148 at the gate and the gated clock signal 156 at the CA latch 118. As discussed above, CA latch 118 may latch the CA signal 58. In order to latch the data properly, a CA delay 128 circuitry may add a delay to the CA signal 58 to allow the data at CA signal at node 158 to correspond to the gated clock signal 118. Advantageously, the presence of CS delay circuitry 126 and the adjustment in CA delay circuitry 128 may lead to a reduced skew between latched CS signal 117 and latched CA signal 119, which may be significantly smaller than a clock cycle (e.g., <10% of a clock cycle). As detailed below, this skew may be reduced further to decrease the tAA by causing an anticipation of the CS signal 56 during a training mode with CS delay circuitry 126.
[0032] As discussed above, circuitry 100 may provide latched CS signal 117 and latched CA signal 119 when the CS signal 56 informs that the memory device 10 should process the CA signal 58. Latching of the CA signal may be performed by gating the clock signal 54 using the CS signal 56. As this system is operating synchronously, CLK delay 122, CS delay 126 and CA delay 128 may be adjusted to improve the performance. For example, in some systems, an increase in the delay in CS delay 126 may be accompanied by a decrease in CLK delay 122 and CA delay 128 without substantial change in the logic performance of system 100. Such change may provide an improved performance with respect to power and/or latency of the overall system, as the overall time for providing latched CA signal 119 is reduced. In some implementations, CS delay circuitry 126 may be adjusted to provide a CS latency that is similar (i.e., similar up to 10% of the value) to a gating latency of the clock signal between processing circuitry 102 and latch 118.
[0033] Moreover, in some situations, a training process that includes the memory device and a memory driver system (e.g., a user device) may be employed. The training process may be performed during initialization of operations or during refreshes. As an example, a CS training process may be performed, as illustrated in FIGS. 3 A and 3B. FIG. 3 A illustrates a block diagram 200 of a memory driver 202 that may be coupled to a memory device 10 having circuitry 100. Memory device 10 may receive (data 210) from memory driver 202 a differential clock signal 56 and a CS signal 56, as discussed. During the CS training process, the memory driver may adjust the timing of the CS based on a response 220 of the memory device 10 to the training CS signal. For example, the memory driver system may provide a clock signal 52 and a CS signal 56, and may monitor the response 220 (e.g., latched CS signal 117) during training. Upon noticing an excessive lag in the response 220, the memory driver may advance the CS signal 56 relative to the clock signal 52. FIG. 3B illustrates this advance behavior through chart 250. Chart 250 shows clock signal 252 and an initial CS signal 256A. After the training process, memory driver 202 may advance (arrow 258) the CS signal 256A to provide CS signal 256B. The advancement of CS signal may allow a reduction in the latencies introduced by CLK delay 122 and CA delay 128. As discussed above, such reduction may further decrease the power consumption in memory device 10 and reduce the overall latency for CA latching.
[0034] The above-discussed process may be performed dynamically if the delay circuits employed are programmable. Method 300 in FIG. 4 illustrates a technique that may be implemented by circuitry, such as circuitry 100, to readjust the delays during CS training. In a process 310, the system may enter in CS training mode. During CS training mode, the device using the memory may make requests to the memory device 10 using CS signals and differential CLK signals, and monitors the return of the request. Based on the return latency, the user device may adjust the timing of its CS signals relative to the CLK signal sent. In a process 320, delay circuitry in the CS line, such as the delay circuitry discussed above, may be adjusted to increase the latency of the return of the request. This adjustment may cause the user device to advance the CS signal relative to the CLK signal. As a result, the CS signal may reach device 10 earlier than the CA signal and, thus, delays due to gating the CLK to a CA latch may be compensated without need of excessive delays in the CA line. In a process 322, CLK delay may also be adjusted accordingly, and the circuitry may leave the CS training mode (process 324). Note that adjustments of the CS delay (process 320) and/or clock delay (process 322) may take place prior to entering the CS training (process 310). It should also be noted the CA delay may also be programmable and, thus, a process for increasing and/or decreasing its delay may take place in method 300. It will be appreciated that in circuits employing non-adjustable delay circuitries, the delay may be adjusted during the configuration of the communication between the processor and the memory device in view of the CS training process.
[0035] While the embodiments described herein may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the techniques and system described in the disclosure as defined by the following appended claims.

中文:
[0001]本发明涉及用于存储器装置的电路,且更明确来说,涉及可在存储器装置中使用的用以调整输入处理经接收指令时的延迟的电路。
[0002]随机存取存储器(RAM)装置(例如可在电装置中采用以提供数据处理及/或存储的装置)可提供对存储于装置的存储器电路中的可寻址数据的直接可用性。某些RAM装置(例如动态RAM(DRAM)装置)可例如具有具许多可寻址存储器元件的多个存储器库。RAM装置还可具有可接收地址及指令(例如,读取、写入等)用于可与所述地址相关联的操作的命令接口,及可处理指令及地址以存取对应存储器库的解码电路。
[0003]到RAM装置的指令及地址可由所述RAM装置外部的电装置的处理电路提供。电装置还可提供可与指令及地址同步的时控信号(clocking signal)。例如,时控信号的边缘可出现在其中地址信号稳定且因此应由RAM装置读取的时刻。因此,RAM装置可包含监测经接收时控信号且在接收到时控信号时读取地址及/或指令的电路。归因于未知延时,此电路可包含处理经接收指令及地址的延迟。此类延迟可增大RAM装置的总延时且增大RAM装置操作期间的功率消耗。
[0005]图1是说明根据实施例的可受益于较快存取时间(tAA)的存储器装置的组织的框图;
[0006]图2说明根据实施例的可用以基于经接收时钟信号锁存芯片选择(CS)信号及/或命令/地址(CA)信号且包含可导致较快tAA的延迟元件的电路的框图;
[0007]图3A说明根据实施例的耦合到存储器驱动器以执行读取训练的存储器装置的框图;
[0008]图3B说明根据实施例的说明在读取训练过程期间CS信号中的增大的延迟的影响的时序图;及
[0009]图4说明根据实施例的用于在读取训练期间调整延迟以减小tAA的方法。
[0010]下文将描述一或多个特定实施例。为提供这些实施例的简洁描述,本说明书中并未描述实际实施方案的全部特征。应明白,如在任何工程或设计项目中,在任何此实际实施方案的开发中,必须作出许多实施方案特定决策以实现可能随实施方案变化的开发者的特定目标,例如符合系统相关及业务相关约束。此外,应明白,此开发工作可为复杂的且耗时的,但对于受益于本发明的所属领域的一般技术人员来说,仍将为常规设计、制作及制造任务。
[0011]许多电装置可包含耦合到处理电路且可提供数据存储以进行处理的随机存取存储器(RAM)装置。RAM装置的实例包含可电子地存储个别位的动态RAM(DRAM)装置及同步DRAM(SDRAM)装置。可将经存储位组织成可由处理电路直接存取的可寻址存储器元件(例如,字)。存储器装置还可包含用以从处理电路接收指令及/或地址的命令电路。例如,在第五代双倍数据率(DDR5)SDRAM装置中,可通过使用14位命令/地址(CA)信号而提供指令及地址。处理电路还可将时控信号连同指令及/或地址一起提供到存储器装置。在DDR5 SDRAM装置中,此时控信号Clk可由差分信号对Clk_t及Clk_s提供。时控信号可将关于何时准备好处理指令及/或地址信号的信息提供到存储器装置。例如,处理电路可将时控信号及指令提供到DDR5 SDRAM装置,使得CA信号可在Clk信号的转变(例如,边缘)期间可用(例如,稳定、准备好)以进行处理。DDR5 SDRAM装置以及经配置以共享指令总线的其它存储器装置还可接收芯片选择(CS)信号,所述CS信号可通知存储器装置其是指令总线上可用的CA信号的预期目的地。此外,在一些标准中(例如在DDR5标准中),可使用双循环(例如,二阶)CA信号来提供命令。在此类情况中,CS信号可用以向存储器装置指示当前CA信号、双循环循环CA信号中的第一部分或第二指令。
[0012]运用CS或CA信号的数据请求与存储器装置中的数据接收之间的延迟可称为存取时间(tAA)。一般来说,tAA可取决于经接收CS及/或CA信号的处理时间。CS及CA信号的处理可根据经接收时控信号Clk执行,且可能易受存储器装置的输入电路中的滞后及延迟以及可补偿任何未知延时的延迟的影响。本文中描述的实施例论述可具有可调整延迟而可用以减小CS及/或CA信号的初始处理中的总延时的存储器装置。例如,存储器装置中的输入电路可具有存储如由Clk信号时控的经接收CA及CS信号的锁存器。可添加及/或调整Clk、CA及CS信号中的输入延迟以通过例如增大CS延迟及减少CA延迟而减少tAA。可在训练过程期间及/或之后调整延迟,在所述训练过程期间,存储器装置可确定延时且可调整CS、CA及Clk信号之间的偏斜。此延迟调整可导致减小的tAA,而导致存储器装置的功率消耗及/或其它资源的减少。
[0013]作为实例,考虑其中可基于经接收CS信号(其自身可经锁存)锁存CA信号的存储器装置。处理CS信号以指示锁存CA信号时的延迟可导致CA信号的锁存与CS信号的锁存之间的偏斜(例如,时间差)。如下文详述,CS信号的锁存的延迟的增大可伴随着CA信号的锁存的延迟的减少,此可减小偏斜及tAA(例如,接收CA信号与提供所请求数据之间的存取时间)。此外,如下文进一步详述,在与用户电路(例如,处理器)之间耦合期间的训练模式可引起CS信号提前出现,从而进一步减小tAA。应注意,虽然实施例的描述涉及DDR5 SDRAM装置以及芯片选择信号以及命令及地址信号,但这些系统可适于可通过添加特定延迟及/或存在训练过程而受益于减小的输入延时的其它同步数字电路的输入级。
[0014]现转向图,图1是说明存储器装置10的某些特征的简化框图。明确来说,图1的框图是说明存储器装置10的特定功能性的功能框图。根据一个实施例,存储器装置10可为第五代双倍数据率同步动态随机存取存储器(DDR5 SDRAM)装置。与前几代DDR SDRAM相比,DDR5SDRAM的各种特征允许降低的功率消耗、较大的带宽及较大的存储容量。
[0015]存储器装置10可包含若干存储器库12。存储器库12例如可为DDR5 SDRAM存储器库。存储器库12可提供于布置于双列直插式存储器模块(DIMM)上的一或多个芯片(例如,SDRAM芯片)上。如将明白,每一DIMM可包含若干SDRAM存储器芯片(例如,x8或x16存储器芯片)。每一SDRAM存储器芯片可包含一或多个存储器库12。存储器装置10表示具有若干存储器库12的单个存储器芯片(例如,SDRAM芯片)的部分。对于DDR5,存储器库12可进一步经布置以形成库群组。例如,对于8千兆字节(GB)DDR5SDRAM,存储器芯片可包含布置成8个库群组的16个存储器库12,每一库群组包含2个存储器库。对于16GB DDR5 SDRAM,存储器芯片可包含例如布置成8个库群组的32个存储器库12,每一库群组包含4个存储器库。可取决于总体系统的应用及设计而利用存储器装置10上的存储器库12的各种其它配置、组织及大小。
[0017]如将明白,命令接口14可包含若干电路(例如时钟输入电路18、命令地址输入电路20及芯片选择输入电路21)以例如确保对信号15的适当处置。例如,输入电路18、20及21可执行同步锁存以提供稳定的信号15供存储器装置10进一步处理。命令接口14可从外部装置接收一或多个时钟信号。一般来说,双倍数据率(DDR)存储器利用可提供为由真实时钟信号(Clk_t)及互补时钟信号(Clk_c)形成的差分对的时钟信号(在本文中称为Clk信号52)。DDR中的Clk信号52的正时钟边缘指上升的真实时钟信号Clk_t与下降的互补时钟信号Clk_c交叉的点,而负时钟边缘指示下降的真实时钟信号Clk_t与互补时钟信号Clk_c的上升的转变。通常在时钟信号的正边缘上键入命令(例如,读取命令、写入命令等),且在正时钟边缘及负时钟边缘两者上传输或接收数据。
[0018]时钟输入电路18接收真实时钟信号(Clk_t)及互补时钟信号(Clk_c)且产生内部时钟信号CLK 54。可将内部时钟信号CLK 54供应到内部时钟产生器,例如延迟锁定环路(DLL)电路30。DLL电路30基于经接收内部时钟信号CLK 54产生相控内部时钟信号LCLK。例如,相控内部时钟信号LCLK经供应到I/O接口16且用作用于确定读取数据的输出时序的时序信号。内部时钟信号CLK 54还可提供到存储器装置10内的各种其它组件且可用以产生各种额外内部时钟信号。例如,可将内部时钟信号CLK 54提供到命令解码器32。命令解码器32可从命令总线34接收命令信号且可解码命令信号以提供各种内部命令。经接收命令信号可从输入电路18、20及21中的锁存输入提供到命令总线34。
[0019]此外,命令解码器32可解码命令(例如读取命令、写入命令、模式寄存器设置命令、激活命令等),且经由总线路径40提供对与命令对应的特定存储器库12的存取。如将明白,存储器装置10可包含各种其它解码器(例如行解码器及列解码器)以有利于存取存储器库12。在一个实施例中,每一存储器库12包含库控制块22,其提供必要解码(例如,行解码器及列解码器)以及其它特征(例如时序控制及数据控制)以有利于执行到及来自存储器库12的命令。
[0020]存储器装置10基于从外部装置(例如处理器)接收的命令/地址信号执行操作,例如读取命令及写入命令。在一个实施例中,命令/地址(CA)总线可为用以容纳命令/地址信号58(CA)的14位总线。如上文论述,使用时钟52(Clk_t及Clk_c)时控到命令接口14的命令/地址信号。命令接口14可包含命令地址输入电路20,其经配置以例如通过命令解码器32接收及传输命令以提供对存储器库12的存取。另外,命令接口14可接收芯片选择信号(CS)。CS信号56使存储器装置10能够处理传入CA总线上的命令。在CA总线上用命令编码对存储器装置10内的特定库12的存取。作为实例,请求来自存储器装置10的数据的处理器可经由输入引脚提供CS启用信号56以通知存储器装置10其应对总线中可用的CA信号58操作。为此,命令接口14可基于经接收芯片选择信号56门控CA信号58,且经由总线40将门控CA信号提供到存储器库12。基于CA信号58,存储器库12可经由数据路径46及I/O接口16提供所请求数据。tAA可量测为在接收CA信号58与提供所请求数据之间的时间。例如,存取时间tAA可在介于约14ns与约18ns之间的范围内。如下文详述,可将延迟电路放置于CS输入电路21中以通过增大CS信号处理路径中的延迟而减小tAA。鉴于CS信号56中相对于Clk信号52的延时,命令接口15中的CS输入电路21可进一步执行CS训练例程以确定及/或引起CS信号的提前。如上文简要论述及下文详述,CS训练例程可用以进一步减少存储器装置10中的tAA。
[0021]另外,命令接口14可经配置以接收若干其它命令信号。例如,可提供片内终结(ondie termination)命令/地址(CA_ODT)信号以有利于存储器装置10内的适当阻抗匹配。可例如在通电期间使用复位命令(RESET)来复位命令接口14、状态寄存器、状态机及类似者。命令接口14还可接收命令/地址反转(CAI)信号,所述CAI信号可经提供以例如取决于用于特定存储器装置10的命令/地址路由而使命令/地址总线上的命令/地址信号CA反转。还可提供镜像(MIR)信号(mirror signal)以有利于镜像功能。基于特定应用中的多个存储器装置的配置,可使用MIR信号来多路复用信号使得可将其交换以启用信号到存储器装置10的特定路由。还可提供有利于测试存储器装置10的各种信号,例如测试启用(TEN)信号。例如,可使用TEN信号来将存储器装置10置于用于连接性测试的测试模式中。
[0022]命令接口14还可用以针对可检测的特定错误将警报信号(ALERT)提供到系统处理器或控制器。例如,如果检测到循环冗余校验(CRC)错误,那么可从存储器装置10传输警报信号(ALERT)。还可产生其它警报信号。此外,在特定操作(例如使用TEN信号执行的连接性测试模式,如上文描述)期间,用于传输来自存储器装置10的警报信号(ALERT)的总线及引脚可用作输入引脚。
[0023]利用上文论述的命令及时控信号,可借助于通过I/O接口16传输及接收数据信号44而将数据发送到存储器装置10及从存储器装置10发送数据。更明确来说,可经由数据路径46将数据发送到存储器库12或从存储器库12检索数据,数据路径46包含多个双向数据总线。通常在一或多个双向数据总线中传输及接收数据IO信号(通常称为DQ信号)。对于某些存储器装置(例如DDR5 SDRAM存储器装置),可将IO信号划分为高字节及低字节。例如,对于x16存储器装置,可将IO信号划分为例如对应于数据信号的高字节及低字节的高IO信号及低IO信号(例如,DQ及DQ)。
[0025]还可通过IO接口16将阻抗(ZQ)校准信号提供到存储器装置10。ZQ校准信号可提供到参考引脚且用以通过跨工艺、电压及温度(PVT)值的变化调整存储器装置10的上拉及下拉电阻器而调谐输出驱动器及ODT值。因为PVT特性可影响ZQ电阻器值,所以可将ZQ校准信号提供到ZQ参考引脚以用于调整电阻而将输入阻抗校准为已知值。如将明白,精密电阻器通常耦合于存储器装置10上的ZQ引脚与存储器装置10外部的GND/VSS之间。此电阻器充当用于调整IO引脚的内部ODT及驱动强度的参考。
[0026]另外,可通过IO接口16将回送信号(LOOPBACK)提供到存储器装置10。可在测试或除错阶段期间使用回送信号来将存储器装置10设置为其中通过存储器装置10通过相同引脚回送信号的模式。例如,可使用回送信号来设置存储器装置10以测试存储器装置10的数据输出(DQ)。回送可包含数据及选通两者或可能仅为数据引脚。此通常希望用于监测由存储器装置10在IO接口16处捕获的数据。
[0027]如将明白,各种其它组件(例如电源供应电路(用于接收外部VDD及VSS信号)、模式寄存器(用以定义各种可编程操作模式及配置)、读取/写入放大器(用以在读取/写入操作期间放大信号)、温度传感器(用于感测存储器装置10的温度)等)还可并入到存储器系统10中。因此,应了解,图1中的框图仅经提供用于突出存储器装置10的某些功能特征以辅助后续详细描述。
[0028]鉴于前述内容,图2中的电路100说明时钟输入电路18、命令地址输入电路20及芯片选择输入电路21的部分。电路100说明处理电路102,处理电路102接收作为差分对Clk_t及Clk_c的Clk信号52且提供数字时钟信号CLK 54。处理电路102可包含将差分对Clk_t及Clk_c转换成数字信号的差分放大器。处理电路102还可包含可稳定数字时钟信号CLK 54的缓冲器。电路100还说明输入缓冲器106,输入缓冲器106稳定经接收CS信号56以供电路利用。类似地,电路100说明缓冲器108,缓冲器108稳定CA信号58以供电路利用。可通过使用CS锁存器116及CA锁存器118而进一步稳定CS信号56及CA信号58。CS锁存器116可用以提供锁存CS信号117,且CA锁存器118可用以提供锁存信号119。如上文详述,锁存器116及118可存储希望在CLK 54的边缘期间捕获且因此为可由SDRAM装置10适当使用的稳定信号的信号。
[0029]为获得锁存CS信号117,来自缓冲器106的CS信号107可用于CS锁存器116的数据输入。可通过CS延迟126延迟数据。CS延迟126可为固定或可编程延迟电路。CS锁存器116可根据CLK 54锁存经接收CS信号。可调整CS延迟126使得CS锁存器116可在由CLK 54适当锁存时锁存CS信号56,如在CS训练过程期间确定。此外,可调整CS延迟126以引起与存储器耦合的装置在训练过程期间将CS信号56提前,如下文详述。此外,可动态地调整或预先调整延迟122、126及128,使得匹配管线中的延时。例如,CS输入缓冲器106与门150之间的延时可匹配处理电路102与门150之间的延时。此外,处理电路102与锁存器118之间的延时可匹配CA缓冲器108与锁存器118之间的延时。此外,基于延迟元件的配置,可在具有时钟偏斜的情况下获得锁存CS信号117及锁存CA信号119。
[0030]来自缓冲器106的CS信号107还可用以从其它电路(例如CA输入电路20)断开CLK54。此门控可用以防止存储器装置10处理CA信号58。来自CS输入电路106的CS信号107可行进通过经由反相缓冲器136耦合的第一半锁存电路132及第二半锁存电路134。第一半锁存电路132可使用CLK信号54锁存CS信号。第二半锁存器电路134可使用由CLK延迟122提供的CLK信号54的延迟版本锁存来自反相器136的CS信号。CLK延迟122可为固定或可编程电路,且可经调整使得在节点142中接收的CS信号可对应于在节点140中接收的CS信号。锁存于第二半锁存电路134中的CS信号(在节点146中说明)可门控节点144中的延迟时钟信号以产生门控时钟信号148。
[0031]门控时钟信号148可用以锁存CA信号58。可通过可具有缓冲器154的传输线152将门控时钟信号148传输到CA锁存器118。传输线152及缓冲器154可产生门处的门控时钟信号148与CA锁存器118处的门控时钟信号156之间的延时。如上文论述,CA锁存器118可锁存CA信号58。为适当锁存数据,CA延迟128电路可将延迟添加到CA信号58以允许节点158处的CA信号处的数据对应于门控时钟信号118。有利地,CS延迟电路126的存在及CA延迟电路128中的调整可导致锁存CS信号117与锁存CA信号119之间的减小的偏斜,所述偏斜可显著小于时钟循环(例如,小于时钟循环的10%)。如下文详述,可通过在训练模式期间用CS延迟电路126引起CS信号56提前出现而进一步减小此偏斜以减少tAA。
[0032]如上文论述,当CS信号56通知存储器装置10应处理CA信号58时,电路100可提供锁存CS信号117及锁存CA信号119。CA信号的锁存可通过使用CS信号56门控时钟信号54而执行。在此系统同步操作时,可调整CLK延迟122、CS延迟126及CA延迟128以改进性能。例如,在一些系统中,CS延迟126中的延迟的增大可伴随着CLK延迟122及CA延迟128的减少,而系统100的逻辑性能无大体变化。此变化可提供关于总体系统的功率及/或延时的改进性能,这是因为用于提供锁存CA信号119的总时间减小。在一些实施方案中,可调整CS延迟电路126以提供类似于处理电路102与锁存器118之间的时钟信号的门控延时(即,值类似高达10%)的CS延时。
[0033]此外,在一些情境中,可采用包含存储器装置及存储器驱动器系统(例如,用户装置)的训练过程。所述训练过程可在初始化操作期间或在刷新期间执行。作为实例,可执行CS训练过程,如图3A及3B中说明。图3A说明可耦合到具有电路100的存储器装置10的存储器驱动器202的框图200。存储器装置10可从存储器驱动器202接收差分时钟信号56及CS信号56(数据210),如所论述。在CS训练过程期间,存储器驱动器可基于存储器装置10对训练CS信号的响应220调整CS的时序。例如,存储器驱动器系统可提供时钟信号52及CS信号56,且可在训练期间监测响应220(例如,锁存CS信号117)。在注意到响应220中的过度滞后之后,存储器驱动器可将CS信号56相对于时钟信号52提前。图3B通过图表250说明此提前行为。图表250展示时钟信号252及初始CS信号256A。在训练过程之后,存储器驱动器202可将CS信号256A提前(箭头258)以提供CS信号256B。CS信号的提前可允许由CLK延迟122及CA延迟128引入的延时的减小。如上文论述,此减小可进一步降低存储器装置10中的功率消耗且减小CA锁存的总延时。
[0034]如果所采用的延迟电路是可编程的,那么可动态地执行上文论述的过程。图4中的方法300说明可由电路(例如电路100)实施以在CS训练期间重新调整延迟的技术。在过程310中,系统可进入CS训练模式。在CS训练模式期间,使用存储器的装置可使用CS信号及差分CLK信号对存储器装置10提出请求,且监测请求的返回。基于返回延时,用户装置可相对于所发送的CLK信号调整其CS信号的时序。在过程320中,可调整CS线中的延迟电路(例如上文论述的延迟电路)以增大请求返回的延时。此调整可引起用户装置将CS信号相对于CLK信号提前。因此,CS信号可比CA信号更早到达装置10,且因此可补偿归因于门控到CA锁存器的CLK的延迟,而无需CA线中的过度延迟。在过程322中,还可相应地调整CLK延迟,且电路可离开CS训练模式(过程324)。应注意,可在进入CS训练(过程310)之前调整CS延迟(过程320)及/或时钟延迟(过程322)。还应注意,CA延迟还可为可编程的,且因此方法300中可发生用于增大及/或减少其延迟的过程。将明白,在采用不可调整延迟电路的电路中,鉴于CS训练过程,可在配置处理器与存储器装置之间的通信期间调整延迟。
[0035]虽然本文中描述的实施例可具有各种修改及替代形式,但已在图式中以实例方式展示且已在本文中详细描述特定实施例。然而,应了解,本发明并不希望限于所揭示的特定形式。而是,本发明希望涵盖落入本发明中描述的如由以下所附权利要求书定义的技术及系统的精神及范围内的全部修改、等效物及替代物。