English:
[0001] With increasing speed of clocking circuits (such as clock buffers, phase-lock loops, and clock generators), the performance of input stages within integrated circuits has become a factor in the overall performance of the integrated circuit.
[0003] In another example, a circuit includes a first common mode amplifier including a first input, a second input, and a first output. The first common mode amplifier comprises a first plurality of self-based differential amplifiers. The circuit also includes a second common mode amplifier including a third input, a fourth input, and a second output, The third input is connected to the second input and the fourth input is connected to the first input. The second common amplifier comprises a second plurality of self-based differential amplifiers. The circuit further includes a first gain amplifier including a fifth input and a sixth input and a second gain amplifier including a seventh input and an eighth input. The first output is connected to the fifth and eight inputs and the second output is connected to the sixth and seventh inputs.
[0004] In yet another example, a circuit includes a first transistor comprising a first control input and first and second current terminals and a second transistor including a second control input and third and fourth current terminals, wherein the third current terminal is connected to the first current terminal. A first current source transistor is included that comprises a third control input and fifth and sixth current terminals, wherein the sixth current terminal is connected to the first and third current terminals. A first resistor is connected to the second current terminal. A second resistor is connected to the first resistor and, at an output node, to the fourth current terminal. A second current source transistor includes a fourth control input and seventh and eighth current terminals. The seventh current terminal is connected to the first and second resistors. The third and fourth control inputs are connected together and to the second terminal.
[0005] FIG. 1 illustrates an example of an amplifier circuit.
[0006] FIG. 2 illustrates another example of an amplifier circuit.
[0007] FIG. 3 illustrates a system that includes multiple wide input common mode amplifiers.
[0008] FIG. 4 shows an example of a wide input common mode amplifier.
[0009] Various circuits are described that are usable as input stages for integrated circuits. The circuits comprise amplifiers. The input signals to the illustrative amplifiers comprise differential time-varying inputs that include a common mode (CM) signal component. The input signals fluctuate over time with respect to the CM signal level. The CM signal level is between the voltages supplying power to the amplifiers (e.g., ground and VDD). One of the illustrative amplifiers operates when the input common mode (ICM) voltage level is at a lower level closer to the lower power supply voltage (e.g., ground). Another illustrative amplifier operates when the ICM voltage level is at a higher level closer to the higher power supply voltage (e.g., VDD). Yet another amplifier is designed for operation across a wide range of ICM voltage levels from close to the lower supply voltage (e.g., ground) to close to the higher power supply voltage (VDD). This latter amplifier is referred to herein as a wide input common mode amplifier (WICMA). The power supply voltages are referred to herein as ground and VDD.
[0010] FIG. 1 illustrates an amplifier circuit that operates particularly well for ICM voltage levels that are closer to ground than the VDD. The illustrative amplifier circuit of FIG. 1 includes transistors Ml, M2, MCS1, MCS2, and resistors Rl and R2. In this example, Ml, M2, and MCS2 are p-type metal oxide semiconductor field effect (PMOS) transistors and MCS1 is an n-type metal oxide semiconductor field effect (NMOS) transistor. Each transistor has a control input (a gate in the example of NMOS or PMOS transistors) and a pair of current terminals (source and drain in the example of NMOS or PMOS transistors). The input signal to the amplifier of FIG. 1 is represented as VIN+ and VIN-, and the output from the amplifier is represented as OUTP, which is a single-ended signal (referenced to ground) in this example. VTN+ and VIN- are complementary voltages, that is, as VIN+ increases, VIN- decreases, and vice versa.
[0011] The gate of Ml is coupled to one input node 101 to thereby receive VIN+ and the gate of M2 is coupled to another input node 102 to thereby receive VIN-. The drain of Ml is connected to one terminal of Rl. Similarly, the drain of M2 is connected to one terminal of R2. The other terminals of Rl and R2 are connected together and to the drain of MCS1. The source of MCS1 is connected to the ground node 109. The gates of MCS1 and MCS2 are connected together and to the node 105 between the drain of Ml and resistor Rl. The drain of MCS2 is connected to the sources of both Ml and M2. The source of MCS2 is connected to a VDD node 110. The output OUTP from the amplifier is the voltage at node 107 between the drain of M2 and resistor R2.
[0012] The combination of M2 and R2 forms a common source amplifier whose current is supported (generated) by MCS2 and MCS1. At relatively low ICM voltages (close to ground), VIN+ and VIN- will swing complementarily between voltages that are close to ground (e.g., between 100 mV and 300 mV for an ICM voltage level of 200 mV, and thus a 100 mV swing). As VIN+ increases within that range, the voltage on node 105 decreases due to lower current flowing through Rl from MCS2 and Ml . The voltage on node 105 enhances either PMOS current source MCS2 (when node 105 voltage decreases) or NMOS MCS1 (when node 105 voltage increases). Also the voltage on node 105 causes a change in the resistances of MCS1 and MCS2. As VTN+ increases, the voltage on node 105 decreases thereby enhancing MCS2 to deliver more current and the resistance of MCS2 reduces while the resistance of MCS1 increases. At the same time, the resistance of M2 decreases due to the decrease in VIN- to the gate of M2. Due to the decrease in the resistance of M2, the OUTP voltage increases. Conversely, as VIN+ decreases and VTN- increases, Ml is enhanced and thus voltage on node 105 increases, which in turn enhances MCS1 to deliver more current. Further, with a higher node 105 voltage the resistance of MCS1 decreases, the resistance of MCS2 increases, and the resistance of M2 increases (due to a decrease in VTN-). As a result, the OUTP voltage decreases.
[0013] FIG. 2 illustrates an example of another common source amplifier circuit that operates particularly well for ICM voltage levels that are closer to VDD than to ground. The illustrative amplifier circuit of FIG. 2 includes transistors M3, M4, MCS3, MCS4, and resistors R3 and R4. In this example, M3, M4, and MCS3 are NMOS transistors and MCS4 is a PMOS transistor. As in the example of FIG. 2, the input signal to the amplifier of FIG. 1 is represented as VIN+ and VTN-, and the output from the amplifier is represented as OUTP.
[0014] The gate of M3 is coupled to one input node 201 to thereby receive VIN+ and the gate of M4 is coupled to another input node 202 to thereby receive VIN-. The drain of M3 is connected to one terminal of R3. Similarly, the drain of M4 is connected to one terminal of R4. The other terminals of R3 and R4 are connected together and to the drain of MCS4. The source of MCS3 is connected to the ground node 109. The gates of MCS3 and MCS4 are connected together and to the node 205 between the drain of M3 and resistor R3. The drain of MCS3 is connected to the sources of both M3 and M4. The source of MCS4 is connected to VDD node 110. The output OUTP from the amplifier of the example of FIG. 2 is the voltage at node 207 between the drain of M4 and resistor R4.
[0015] The example of FIG. 2 operates similarly to the example of FIG. 1 but at ICM voltages that are closer to VDD rather than ground. The combination of M4 and R4 forms an amplifier whose current is supported (generated) by MCS4 and MCS3. At relatively high ICM voltages (close to VDD), VIN+ will swing between voltages that are close to VDD (e.g., between 800 mV and 1 V for an ICM voltage level of 900 mV and a 100 mV swing relative to the ICM voltage). As VIN+ increases within that range, the resistance of NMOS M3 decreases and thus the voltage on node 205 decreases. The decreasing voltage on node 205 enhances PMOS current source transistor MCS4 to deliver more current. At the same time the resistance of M4 increases due to the decrease in VIN-. An increase in resistance of M4 results in an increase in OUTP. Conversely, if MCS3 is enhanced to deliver more current more current (due to VIN+ decreasing causing node 205 voltage to increase), the resistance of MCS3 decreases while the resistance of MCS4 increases. As a result, OUTP decreases.
[0017] The gain factor of the WICMAs 310 and 315 may not be as much as is desired in many applications. Accordingly, a second stage comprising gain amplifiers 320 and 325 are included in the example of FIG. 3. Each GA 320, 325 includes a positive input and a negative input, as was the case for the WICMAs 310, 315. The output node 313 from WICMA 310 is coupled to the positive input node 321 of GA 320 and to the negative input node 327 of GA 325. The output node 318 from WICMA 315 is coupled to the negative input node 322 of GA 320 and to the positive input node 326 of GA 325. The gain factors of GAs 320 and 325 may be application specific. In one example, the gain factor is 2, but can be other than 2 in other examples. The output from circuit 300 is taken as the voltage on the output nodes 323 and 328 of GA 320 and GA 325, respectively, as shown as OUT+ and OUT-.
[0018] Each of the WICMAs 310 and 315 may be implemented with a circuit such as that shown in the example of FIG. 4. The example WICMA implementation of FIG. 4 effectively combines three amplifiers together— one that operates with ICM voltage levels in the lower range closer to ground, one that operates with ICM voltage levels at the upper range closer to VDD, and one that operates with ICM voltages approximately half-way between ground and VDD. The three amplifiers share input voltage nodes 301 (VIN+) and 302 (VTN-) and an output voltage node 308 (OUTP).
[0019] The example WICMA of FIG. 4 includes transistors M5, M6, M7, M8, M9, and M10, current source transistors MCS5, MCS6, MCS7, MCS8, MCS9, and MCS10, and resistors R5, R6, R7, and R8. Transistors M7, M8, and M9 are PMOS transistors and transistors M5, M6, and M10 are NMOS transistors. Current source transistors MCS6, MCS8, and MCS10 are PMOS transistors and current source transistors MCS5, MCS7, and MCS9 are NMOS transistors. The transistors can be implemented with different dopings in other examples, and bipolar junction transistors can be used instead of MOS transistors.
[0020] The drain 406 of M7 is connected to the drain 401 of M5 at node 420. The gates of M7 and M5 are connected together at the VIN+ input voltage node 398. On the right side of the circuit, the drain 408 of M8 is connected to the drain 403 of M6 at the output voltage node (OUTP) 395. The gates of M8 and M6 are connected together at the VIN- input voltage node 399.
[0021] The gates of current source transistors MCS6 and MCS5 are connected together and also to node 420 to connect to the drains 401 and 406 of M5 and M7, respectively. The source of MCS6 is connected to the positive power node 415 (VDD) and the source of MCS5 is connected to ground node 417 (also termed a power node). The drain of MCS5 is connected to the sources 402 and 404 of M5 and M6, respectively. The drain of MCS6 is connected to the sources 405 and 407 of M7 and M8, respectively.
[0022] The combination of M5, M6, M7, M8, MCS5, and MCS6 represents one of the three amplifiers noted above subsumed within the architecture of the WICMA 310, 315. This particular amplifier operates when the ICM voltage level is in the mid-range between ground and VDD (e.g., approximately one-half of VDD). M6 and M8 function as an inverter between VIN- and OUTP. That is, as the VIN- voltage falls, OUTP rises, and vice versa. The inverter comprising M8 and M6 receives current via current source transistors MCS6 and MCS5. M5 and M7 also form an inverter to invert VIN+ on to node 420 (as VIN+ increases, the voltage on node 420 decreases, and vice versa).
[0023] The input to the amplifier is defined by VTN+ and VTN-, which has a particular ICM voltage (approximately mid-range between ground and VDD and which has a voltage swing relative to the ICM voltage level). In one example, the suitable ICM voltage level for the amplifier defined above is 600 mV for a VDD of IV and may have a voltage swing of 200 mV relative to the ICM voltage level. Thus, VIN+ ranges from 500 mV to 700 mV, while at the same time VIN- ranges in the opposite direction from 700 mV to 500 mV. If VIN+ increases towards its upper voltage level (700 mV in this example), the voltage on node 420 decreases thereby biasing PMOS transistor MCS6 more strongly than NMOS transistor MCS5. While VIN+ increases, VTN- decreases. Due to the inverter formed by M8 and M6, the voltage on the output node 395 (OUTP) increases because M6 will be turned off as VIN- may be less than the switching threshold voltage of M6. With MCS6 being driven more strongly due the decrease in voltage on node 420 (which drives the gate of MCS6), current from MCS2 helps to increase the OUTP voltage even faster. By contrast, if VIN+ decreases and VIN- increases, the voltage on node 420 will increase thereby turning on M6 and MCS5 to a stronger state thereby providing a good conducting path from OUTP to ground thereby pulling OUTP down even faster than if the inverter formed by M7 and M5 was not present.
[0024] However, the amplifier formed by M5, M6, M7, M8, MCS5 and MCS6 may not function correctly at ICM voltage levels closer to ground or closer to VDD. At those higher or lower voltage levels, one of M6 or M8 may be stuck on or off thereby preventing the satisfactory operation. For example, if the ICM voltage level is 900 mV (with VDD equal to IV and a 200 mV swing relative to the 900 mV ICM voltage level), M8 will permanently in the triode or even the sub-threshold region as VIN- swings between 800 mV and 1 V and thus also remains above the threshold voltage of M8. As such, M8 cannot operate as an amplifier. Similarly, if the input voltage is close to ground (e.g., ICM voltage of 200 mV with a 100 mV swing), then Vin- will be too low ever to turn on M6.
[0025] Another amplifier embedded in the architecture of each WICMA 310, 315 includes transistors M8 and M9, current source transistors MCS10 and MCS9, and resistors R5 and R6. The architecture of this amplifier is similar to that shown in the example of FIG. 1 and is operative for ICM voltage levels closer to ground. The drain 410 of M9 is connected to R5 (at node 422), which also connects to the gates of MCS10 and MCS9. The drain 408 of M8 is connected to R6, and R6 also connects to MCS9. The sources 409 and 407 of M9 and M8, respectively connect to MCS10 as shown. As such, transistor M8 is a component both of the amplifier which is operative for ICM voltage levels in the mid-range between ground and VDD and of the amplifier which is operative for ICM voltage levels closer to ground. Resistors R5 and R6 are used for this latter amplifier to advantageously permit current to flow even at lower ICM voltage levels.
[0026] The operation of the amplifier formed by transistors M8 and M9, current source transistors MCS10 and MCS9, and resistors R5 and R6 functions similar to that described above regarding FIG. 1. When ICM is low (close to ground), the transistors M8, M9, MCS9 and MCS10 and the resistors R5 and R6 will operate as an amplifier because all NMOS transistors will be off (not conduct current). Also the PMOS transistors M7, MCS6 and MSC8 will not conduct current because the current path is interrupted with M5, MCS5 and MCS9 being off). R8 can be neglected because R8 is of a much lower resistance than M8. In the case in which VTN+ increases (albeit close to ground), the voltage on node 422 will decline because M9 will provide less current to the node 410. At the same time M8 becomes more open meaning it is capable of delivering more current to the OUTP node 395 due to the lower gate-to-source voltage on M8. As the voltage on node 422 decreases, MCS10 will be more open i.e. provide more current to the circuit. Since M8 provides a better conducting path for current than M9, the current from MCS10 will flow to OUTP rather than to node 422 thereby causing a voltage rise for OUTP. At the same time, when the node 422 node voltage decreases, the MCS9 will be less open (because MCS9 gate-to-source voltage is lower). Since less current is pulled from OUTP (through R6) the voltage at the node OUTP will rise quickly. The voltage OUTP is not clamped to VDD due to limited gain of the amplifier formed by M8, M9, MCS9 and MCS10 and the resistors R5 and R6. As long as VIN+ is greater than VIN- , the OUTP voltage will be high (high compared to the case when VIN+ = VIN-). In the opposite case, when VIN+ declines and VIN- increases, M9 is enhanced to form a better conducting path for current than M8. The node 422 voltage declines, MCS10 provides less current to M8 and a majority of current flows through M9. At the same time MCS9 becomes more open (because its gate-to-source voltage is higher) which will pull down the OUTP voltage and the voltage OUTP is lower than in case when VIN+ equals VTN-. Also, in this case, the voltage OUTP is not clamped to ground.
[0027] A third amplifier embedded in the architecture of each WICMA 310, 315 includes transistors M6 and M10, current source transistors MCS8 and MCS7, and resistors R7 and R8. The architecture of this amplifier is similar to that shown in the example of FIG. 2 and is operative for ICM voltage levels closer to VDD. The drain 411 of M10 is connected to R7 (at node 421) and to the gates of MCS7 and MCS8. The drain 403 of M6 is connected to R8, and R8 also connects to MCS8. The sources 412 and 404 of M10 and M6, respectively, connect to MCS7 as shown. As such, transistor M6 is a component both of the amplifier which is operative for ICM voltage levels in the mid-range between ground and VDD and of the amplifier which is operative for ICM voltage levels closer to ground. Resistors R7 and R8 are used for this latter amplifier to advantageously permit current to flow even at lower ICM voltage levels.
[0028] The operation of the amplifier formed by transistors M6 and M10, current source transistors MCS8 and MCS7, and resistors R7 and R8 functions similar to that described above regarding FIG. 2. When ICM is high i.e. close to VDD the transistors M6, M10, MCS7 and MCS8 and the resistors R7 and R8 will operate as amplifier because all PMOS transistors will be off and thus not conduct current. Also the NMOS transistors M5, MCS5 and MSC9 will not conduct current because the current path is interrupted due to M7, MCS6 and MCS10 being off. In this case R6 can be neglected because the resistance of R6 is high compared to the resistance of M6. When the differential voltage VIN+ increases and thus VIN- decreases, M10 becomes a better conductive path for current than M6 because the M10 gate-to- source voltage raises while M6 gate-to- source decreases. At the same time the node 421 voltage decreases and MCS8 is more open and delivers more current. Since M10 is a better path for current, and thus less current will flow through R8. The voltage drop across R8 will be lower and the voltage OUTP increases. At the same time MCS7 is more closed and delivers less current which prevents the discharging of OUTP through R6 (i.e., the voltage at OUTP will raise faster due to small discharging current). In the opposite case when VIN+ decreases and VIN- increases, M6 is a better conducting path for current than M10. The node 421 voltage increases and MCS8 is less open i.e. delivers less current while MCS7 deliver more current. As a result, the node OUTP will discharge faster (much less current is injected into this node than is pulled from the node) and the voltage OUTP will decreases faster.
[0029] The pairs of current source transistors— MCS5/MCS6, MCS7/MCS8, and MCS9/MCS10— operate as described above based on the change in voltages of their corresponding nodes 420, 421, and 422.
[0030] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

中文:
[0001]随着时钟电路(诸如时钟缓冲器、锁相环和时钟发生器)的速度提高,集成电路内的输入级的性能已成为集成电路的整体性能的一个因素。
[0003]在另一示例中,一种电路包括第一共模放大器,该第一共模放大器包括第一输入端、第二输入端和第一输出端。第一共模放大器包括第一多个基于自身的差分放大器。该电路还包括第二共模放大器,该第二共模放大器包括第三输入端、第四输入端和第二输出端。第三输入端连接到第二输入端,并且第四输入端连接到第一输入端。第二共模放大器包括第二多个基于自身的差分放大器。该电路还包括第一增益放大器和第二增益放大器,该第一增益放大器包括第五输入端和第六输入端,该第二增益放大器包括第七输入端和第八输入端。第一输出端连接到第五输入端和第八输入端,并且第二输出端连接到第六输入端和第七输入端。
[0004]在又一示例中,一种电路包括:第一晶体管,其包括第一控制输入端以及第一电流端子和第二电流端子;以及第二晶体管,其包括第二控制输入端以及第三电流端子和第四电流端子,其中第三电流端子连接到第一电流端子。包括第一电流源晶体管,其包括第三控制输入端以及第五电流端子和第六电流端子,其中第六电流端子连接到第一电流端子和第三电流端子。第一电阻器连接到第二电流端子。第二电阻器连接到第一电阻器,并且第二电阻器在输出节点处连接到第四电流端子。第二电流源晶体管包括第四控制输入端以及第七电流端子和第八电流端子。第七电流端子连接到第一电阻器和第二电阻器。第三控制输入端和第四控制输入端连接在一起并且连接到第二端子。
[0005]图1示出了放大器电路的示例。
[0006]图2示出了放大器电路的另一示例。
[0007]图3示出了包括多个宽输入共模放大器的系统。
[0008]图4示出了宽输入共模放大器的示例。
[0009]描述了可用作集成电路的输入级的各种电路。电路包括放大器。说明性放大器的输入信号包括差分时变输入,该差分时变输入包括共模(CM)信号分量。输入信号相对于CM信号电平随时间波动。CM信号电平介于向放大器供电的电压(例如,地和VDD)之间。当输入共模(ICM)电压电平处于更接近较低电源电压(例如,地)的较低电平时,说明性放大器中的一个操作。当ICM电压电平处于更接近较高电源电压(例如,VDD)的较高电平时,另一说明性放大器操作。还设计了另一种放大器,以在从接近较低电源电压(例如,地)到接近较高电源电压(VDD)的宽范围的ICM电压电平内操作。后一种放大器在本文中称为宽输入共模放大器(WICMA)。电源电压在本文中称为地和VDD。
[0010]图1示出了放大器电路,该放大器电路对于与VDD相比更接近地的ICM电压电平操作得尤其好。图1的说明性放大器电路包括:晶体管M1、M2、MCS1、MCS2以及电阻器R1和R2。在此示例中,M1、M2和MCS2是p型金属氧化物半导体场效应(PMOS)晶体管,并且MCS1是n型金属氧化物半导体场效应(NMOS)晶体管。每个晶体管具有控制输入端(在NMOS或PMOS晶体管的示例中为栅极)和一对电流端子(在NMOS或PMOS晶体管的示例中为源极和漏极)。图1的放大器的输入信号被表示为VIN+和VIN-,并且放大器的输出被表示为OUTP,其在此示例中为单端信号(参考地)。VIN+和VIN-是互补电压,也就是说,随着VIN+增加,VIN-降低,反之亦然。
[0011]M1的栅极耦合到一个输入节点101,由此接收VIN+,并且M2的栅极耦合到另一输入节点102,由此接收VIN-。M1的漏极连接到R1的一个端子。类似地,M2的漏极连接到R2的一个端子。R1和R2的另一端子连接在一起并且连接到MCS1的漏极。MCS1的源极连接到接地节点109。MCS1和MCS2的栅极连接在一起并且连接到M1的漏极和电阻器R1之间的节点105。MCS2的漏极连接到M1和M2的源极。MCS2的源极连接到VDD节点110。放大器的输出OUTP是M2的漏极和电阻器R2之间的节点107处的电压。
[0012]M2和R2的组合形成共源放大器,其电流由MCS2和MCS1支持(产生)。在相对低的ICM电压(接近地)下,VIN+和VIN-将在接近地的电压之间互补摆动(例如,对于200mV的ICM电压电平,在100mV和300mV之间互补摆动,并且因此摆动100mV)。当VIN+在该范围内增加时,由于从MCS2和M1流经R1的电流较低,因此节点105上的电压降低。节点105上的电压增强PMOS电流源MCS2(当节点105电压降低时)或NMOS MCS1(当节点105电压增加时)。而且,节点105上的电压引起MCS1和MCS2的电阻变化。随着VIN+的增加,节点105上的电压降低,从而增强MCS2以递送更多电流,并且MCS2的电阻减小而MCS1的电阻增加。同时,由于到M2的栅极的VIN-降低,因此M2的电阻降低。由于M2的电阻降低,OUTP电压增加。相反,随着VIN+降低和VIN-增加,M1增强,并且因此节点105上的电压增加,这进而增强MCS1以递送更多的电流。此外,随着节点105电压的升高,MCS1的电阻降低,MCS2的电阻增加,并且M2的电阻增加(由于VIN-的降低)。结果,OUTP电压降低。
[0013]图2示出了另一共源放大器电路的示例,该共源放大器电路在与地相比更接近VDD的ICM电压电平下操作得尤其好。图2的说明性放大器电路包括晶体管M3、M4、MCS3、MCS4以及电阻器R3和R4。在此示例中,M3、M4和MCS3是NMOS晶体管,并且MCS4是PMOS晶体管。如在图2的示例中,图1的放大器的输入信号被表示为VIN+和VIN-,并且放大器的输出被表示为OUTP。
[0014]M3的栅极耦合到一个输入节点201,由此接收VIN+,并且M4的栅极耦合到另一输入节点202,由此接收VIN-。M3的漏极连接到R3的一个端子。类似地,M4的漏极连接到R4的一个端子。R3和R4的其他端子连接在一起并连接到MCS4的漏极。MCS3的源极连接到接地节点109。MCS3和MCS4的栅极连接在一起并且连接到M3的漏极和电阻器R3之间的节点205。MCS3的漏极连接到M3和M4的源极。MCS4的源极连接到VDD节点110。图2的示例的放大器的输出OUTP是M4的漏极和电阻器R4之间的节点207处的电压。
[0015]图2的示例与图1的示例类似地操作,但是ICM电压更接近VDD而非地。M4和R4的组合形成放大器,其电流由MCS4和MCS3支持(生成)。在相对高的ICM电压(接近VDD)下,VIN+将在接近VDD的电压之间摆动(例如,对于900mV的ICM电压电平,在800mV至1V之间摆动,并且相对于ICM电压的摆动为100mV)。随着VIN+在该范围内增加,NMOS M3的电阻降低,并且因此节点205上的电压降低。节点205上的电压降低增强PMOS电流源晶体管MCS4以递送更多电流。与此同时,由于VIN-的降低,导致M4的电阻增加。M4的电阻的增加导致OUTP的增加。相反,如果MCS3被增强以递送更多电流(由于VIN+降低导致节点205电压增加),则MCS3的电阻降低而MCS4的电阻增加。结果,OUTP降低。
[0017]WICMA 310和315的增益因子在许多应用中可能没有期望的那么大。因此,在图3的示例中包括包含增益放大器320和325的第二级。每个GA 320、325包括正输入端和负输入端,与WICMA 310、315的情况一样。WICMA 310的输出节点313耦合到GA 320的正输入节点321和GA 325的负输入节点327。WICMA 315的输出节点318耦合到GA 320的负输入节点322和GA 325的正输入节点326。GA 320和325的增益因子可以是特定于应用的。在一个示例中,增益因子是2,但是在其他示例中增益因子可以不是2。电路300的输出分别取为GA 320和GA325的输出节点323和328上的电压,如OUT+和OUT-所示。
[0018]WICMA 310和315中的每个可以利用诸如图4的示例中所示的电路来实现。图4的示例WICMA实施方式将三个放大器有效地组合在一起:一个放大器以接近地的较低范围内的ICM电压电平操作,一个放大器以接近VDD的较高范围的ICM电压电平操作,并且一个放大器以大约在地和VDD之间的中值的ICM电压操作。这三个放大器共享输入电压节点301(VIN+)和302(VIN-)以及输出电压节点308(OUTP)。
[0019]图4的示例WICMA包括晶体管M5、M6、M7、M8、M9和M10、电流源晶体管MCS5、MCS6、MCS7、MCS8、MCS9和MCS10以及电阻器R5、R6、R7和R8。晶体管M7、M8和M9是PMOS晶体管,并且晶体管M5、M6和M10是NMOS晶体管。电流源晶体管MCS6、MCS8和MCS10是PMOS晶体管,并且电流源晶体管MCS5、MCS7和MCS9是NMOS晶体管。在其他示例中,可以用不同的掺杂实现晶体管,并且可以使用双极结型晶体管代替MOS晶体管。
[0020]M7的漏极406在节点420处连接到M5的漏极401。M7和M5的栅极在VIN+输入电压节点398处连接在一起。在电路的右侧,M8的漏极408在输出电压节点(OUTP)395处连接到M6的漏极403。M8和M6的栅极在VIN-输入电压节点399处连接在一起。
[0021]电流源晶体管MCS6和MCS5的栅极连接在一起并且还连接到节点420,以分别连接到M5和M7的漏极401和406。MCS6的源极连接到正电源节点415(VDD),并且MCS5的源极连接到接地节点417(也称为电源节点)。MCS5的漏极分别连接到M5和M6的源极402和404。MCS6的漏极分别连接到M7和M8的源极405和407。
[0022]M5、M6、M7、M8、MCS5和MCS6的组合表示WICMA 310、315的架构内包含的上述三个放大器中的一个放大器。该特定放大器在ICM电压电平处于接地和VDD之间的中间范围(例如约为VDD的一半)时操作。M6和M8用作VIN-和OUTP之间的反相器。也就是说,随着VIN-电压下降,OUTP上升,反之亦然。包括M8和M6的反相器经由电流源晶体管MCS6和MCS5接收电流。M5和M7还形成反相器以将VIN+反相到节点420上(随着VIN+增加,节点420上的电压降低,反之亦然)。
[0023]放大器的输入端由VIN+和VIN-定义,该输入端具有特定的ICM电压(大约在地和VDD之间的中间范围并且具有相对于ICM电压电平的电压摆动)。在一个示例中,对于1V的VDD,上面定义的放大器的合适的ICM电压电平是600mV并且相对于ICM电压电平可以具有200mV的电压摆动。因此,VIN+的范围为500mV至700mV,同时VIN-在相反的方向上的范围为700mV至500mV。如果VIN+朝着其较高电压电平(在该示例中为700mV)增加,则节点420上的电压降低,从而与NMOS晶体管MCS5相比更强地偏置PMOS晶体管MCS6。当VIN+增加时,VIN-降低。由于由M8和M6形成的反相器,输出节点395(OUTP)上的电压增加,这是因为当VIN-可能小于M6的开关阈值电压时,M6将被关断。通过MCS6由于节点420上的电压(其驱动MCS6的栅极)的降低而被更强地驱动,来自MCS2的电流帮助更快地增加OUTP电压。相反,如果VIN+降低并且VIN-增加,则节点420上的电压将增加,从而将M6和MCS5导通至更强的状态,由此提供从OUTP到地的良好的传导路径,从而与不存在由M7和M5形成的反相器的情况相比更快地下拉OUTP。
[0024]然而,由M5、M6、M7、M8、MCS5和MCS6形成的放大器在ICM电压电平更接近地或更接近VDD时可能无法正常操作。在那些较高或较低的电压电平下,M6或M8之一可能会卡在开或关上,从而妨碍令人满意的操作。例如,如果ICM电压电平为900mV(其中VDD等于1V,并且相对于900mV的ICM电压电平具有200mV的摆动),则随着VIN-在800mV和1V之间摆动,M8将永久位于三极管(triode)区域或甚至亚阈值区域,并且因此也保持高于M8的阈值电压。因此,M8无法操作为放大器。类似地,如果输入电压接近于地(例如,ICM电压为200mV,摆动为100mV),则Vin-将太低而无法导通M6。
[0025]嵌入在每个WICMA 310、315的架构中的另一个放大器包括晶体管M8和M9、电流源晶体管MCS10和MCS9以及电阻器R5和R6。该放大器的架构类似于图1的示例中所示,并且可用于更接近地的ICM电压电平。M9的漏极410(在节点422处)连接到R5,R5还连接到MCS10和MCS9的栅极。M8的漏极408连接到R6,并且R6也连接到MCS9。如图所示,M9和M8的源极409和407分别连接到MCS10。这样,晶体管M8既是可操作用于在地和VDD之间的中间范围中的ICM电压电平的放大器的部件,也是可操作用于更接近地的ICM电压电平的放大器的部件。电阻器R5和R6用于后一个放大器,以便即使在较低的ICM电压电平下也有利地允许电流流动。
[0026]由晶体管M8和M9、电流源晶体管MCS10和MCS9以及电阻器R5和R6形成的放大器的操作类似于以上关于图1所述的发挥作用。当ICM为低(接近地)时,晶体管M8、M9、MCS9和MCS10以及电阻器R5和R6将操作为放大器,因为所有NMOS晶体管都将截止(不传导电流)。而且,因为电流路径在M5、MCS5和MCS9截止的情况下被中断,所以PMOS晶体管M7、MCS6和MSC8将不传导电流。R8可以忽略不计,因为R8的电阻远低于M8的电阻。在VIN+增加(尽管接近于地)的情况下,节点422上的电压将下降,因为M9将为节点410提供更少的电流。同时,M8变得断开得更多,这意味着由于M8上的较低的栅极至源极电压使得M8能够向OUTP节点395递送更多电流。随着节点422上电压的降低,MCS10将打开得更多,即为电路提供更多电流。由于M8与M9相比提供了更好的电流传导路径,因此来自MCS10的电流将流向OUTP而不是节点422,从而导致OUTP的电压上升。同时,当节点422的节点电压降低时,MCS9将打开得更少(因为MCS9的栅极至源极电压较低)。由于从OUTP(通过R6)汲取的电流较小,因此节点OUTP处的电压将快速上升。由于由M8、M9、MCS9和MCS10以及电阻器R5和R6形成的放大器的增益有限,因此电压OUTP未钳位到VDD。只要VIN+大于VIN-,OUTP电压就将为高(与VIN+=VIN-的情况相比为高)。在相反的情况下,当VIN+下降并且VIN-增加时,M9被增强,从而与M8相比提供了更好的电流传导路径。节点422电压下降,MCS10向M8提供更少的电流,并且大部分电流流过M9。同时,MCS9变得打开得更多(因为其栅极至源极电压更高),这将拉低OUTP电压,并且电压OUTP比VIN+等于VIN-的情况下更低。同样,在这种情况下,电压OUTP没有被钳位到地。
[0027]嵌入在每个WICMA 310、315的架构中的第三放大器包括晶体管M6和M10、电流源晶体管MCS8和MCS7以及电阻器R7和R8。这种放大器的架构类似于图2的示例中所示的架构并且可操作用于更接近VDD的ICM电压电平。M10的漏极411(在节点421处)连接到R7以及MCS7和MCS8的栅极。M6的漏极403连接到R8,并且R8也连接到MCS8。如图所示,M10和M6的源极412和404分别连接到MCS7。这样,晶体管M6既是可操作用于在地和VDD之间的中间范围内的ICM电压电平的放大器的部件,也是可操作用于更接近地的ICM电压电平的放大器的部件。电阻器R7和R8用于后一种放大器,从而即使在较低的ICM电压电平下也有利地允许电流流动。
[0028]由晶体管M6和M10、电流源晶体管MCS8和MCS7以及电阻器R7和R8形成的放大器的操作类似于以上关于图2所描述的发挥作用。当ICM为高时,即接近VDD时,晶体管M6、M10、MCS7和MCS8以及电阻器R7和R8将操作为放大器,因为所有PMOS晶体管都将截止,并且因此不传导电流。而且,因为由于M7、MCS6和MCS10截止而使电流路径中断,因此NMOS晶体管M5、MCS5和MSC9将不传导电流。在这种情况下,由于R6的电阻比M6的电阻高,因此可以忽略R6。当差分电压VIN+增加并且由此VIN-降低时,由于M10的栅极至源极电压升高而M6的栅极至源极电压降低,因此M10与M6相比变为了更好的电流传导路径。同时,节点421的电压降低,并且MCS8打开得更多并且递送更多电流。由于M10是更好的电流路径,并且因此流过R8的电流将较少。R8两端的电压降将降低,并且电压OUTP增加。同时,MCS7关闭得更多并且递送更少的电流,这阻止了OUTP通过R6放电(即,由于放电电流小,OUTP处的电压将更快地上升)。相反,当VIN+降低并且VIN-增加时,M6是比M10更好的电流传导路径。节点421的电压增加并且MCS8打开得更少,即,递送更少的电流,同时MCS7递送更多电流。结果,节点OUTP将更快地放电(注入该节点的电流比从节点汲取的电流少得多),并且电压OUTP将更快地降低。
[0029]成对的电流源晶体管(MCS5/MCS6、MCS7/MCS8和MCS9/MCS10)基于其对应的节点420、421和422的电压变化如上所述地操作。
[0030]在权利要求的范围内,在所描述的实施例中可以进行修改,并且其他实施例也是可能的。