English:
[0001] Switching converters are used to convert electrical power from one form to another by operation of a switching circuit. Examples include DC-DC switching converters with switch circuits to convert DC input power into a controlled DC output to drive a load. Single-phase systems include a single switching converter to drive the load. Multiphase systems include two or more switching converters connected in parallel with one another to provide a regulated output voltage, with the ability to activate or deactivate certain switching converters depending on load current requirements. In single or multiphase switching converter systems, it is desirable to react to transient conditions, such as line or load variations. For example, changes in load current requirements may allow one or more phases to be turned off or disabled to enhance overall system energy efficiency. Other changing conditions may require activation of one or more phases to accommodate increased load current requirements. Changing input power conditions, such as variations in input voltage levels can likewise be accommodated by selectively activating or deactivating phases of a multiphase system. Using parallel inductors at the outputs of individual switching converter phases can improve transient response, but this might lead to energy inefficiencies in steady state operation. It is then a great advantage to detect as fast as possible the transient event and to know when the system went back to steady state. Transient events are typically short and detecting certain events requires very high-speed circuitry, leading to cost and energy efficiency challenges in switching converter design. Enhanced efficiency and intelligent phase management can be facilitated by fast detection of transient events and also fast notification that the system has returned to steady state operation. SUMMARY
[0002] Described examples include power conversion systems, integrated circuits and transient event detector circuits to detect transient events in switching converters. The transient event detector circuit in certain examples includes a delay lock loop (DLL) circuit to detect changes in a duty cycle of a pulse width modulation (PWM) signal used to operate a switching converter. The detector circuit provides a status output signal in a first state when no transient event is detected. The detector circuit provides the status output signal in a second state indicating a transient event in the switching converter in response to a detected change in the duty cycle of the PWM signal. The DLL circuit in one example includes a monostable multivibrator to generate a pulse output signal triggered by a first edge of the PWM signal, and a phase detector to provide first and second output signals according to a phase difference between the second edge of the PWM signal and a controlled edge of the multivibrator pulse output signal. A charge pump selectively sources or sinks current to or from a capacitor according to the phase detector outputs to establish a voltage control signal. The capacitor provides the voltage control signal as a control input to the multivibrator to align the second edges of the multivibrator pulse output and PWM signals. In certain examples, the DLL circuit has a bandwidth equal to the bandwidth of a control circuit operating the switching converter so that both systems are over-slewed for the same type of transient events. This facilitates detection that a previous steady state duty cycle has changed within the PWM cycle in which the change occurs. Fast transient detection, in turn, facilitates timely intelligent adjustments in single and/or multiphase switching converter systems, such as selectively activating or deactivating one or more phases in a multiphase system. In certain examples, the transient event detector circuit filters the phase detector output signals, and generates the status output signal according to the filtered phase detector signals. The first and second filtered phase detector signals can also be provided as output signals to distinguish between positive and negative transient events. The transient event detector circuit in certain examples is provided in a switching controller integrated circuit (IC) along with a control circuit to operate the switching converter. In other examples, the transient event detector circuit is integrated with a multiphase converter master controller that receives PWM signals from one or more individual switching converter control circuits to identify a load and/or line transient event based on changes in PWM signal duty cycle.
[0003] FIG. 1 is a schematic diagram of a transient event detector circuit with a DLL to detect changes in a PWM signal duty cycle.
[0004] FIG. 2 is a schematic diagram of a monostable multivibrator in the DLL of FIG. 1.
[0005] FIG. 3 is a schematic diagram of a switching converter controller IC with a transient event detector circuit in a multiphase power conversion system.
[0006] FIG. 4 is a waveform diagram showing various signals in the circuits of FIGS. 1-3.
[0007] FIG. 5 is a system diagram of a multiphase power conversion system with a transient event detector providing signals to a master controller.
[0008] FIG. 6 is a system diagram of a multiphase power conversion system with a master controller including a transient event detector circuit.
[0009] In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. In this description, the terms "couple," "couples" or "coupled" include indirect or direct electrical or mechanical connection or combinations thereof. For example, if a first device couples to or is coupled with a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via one or more intervening devices and connections.
[0010] FIG. 1 shows a transient event detector circuit 100 including an input 102 that receives a first signal PWM from a switching converter control circuit, referred to herein as a pulse width modulation signal PWM. The transient event detector circuit 100 also includes signal outputs 142, 144 and 146 that provide a status output signal SS, a positive transient signal TR+ and a negative transient signal TR-, respectively. The circuit 100 can be used in any form of power conversion system that includes one or more switching converter stages to convert power from one form to another. Examples are illustrated and described hereinbelow in connection with DC-DC switching converters, although techniques of this description are not limited to the illustrated examples. In operation, the switching converter operates according to the PWM signal, and the circuit 100 quickly detects that a previous steady state duty cycle of the PWM signal has changed within the cycle in which the change occurs. The circuit 100 provides a solution to quickly identify transient events at the input and/or output of a switching converter, allowing timely intelligent responsive measures. For example, one or more of the outputs SS, TR+ and TR- can be used by converter control circuitry for intelligent load management for enabling or disabling individual switching converter phases in a multiphase power conversion system in response to a line or load transient event.
[0012] The phase detector circuit 120 includes a first input inverter 116 that receives the TIMER signal and provides an inverted signal TIMER' at an output 118. A second inverter 117 is provided at a second input of the phase detector 120. The inverter 117 receives the PWM signal and provides an inverted signal PWM' at an output 119. The phase detector 120 includes first and second outputs 128A and 128B to provide first and second output signals UP and DOWN according to a phase difference between the second edge of the PWM signal and the controlled second edge of the multivibrator pulse output signal TIMER. The output 118 of the inverter 116 provides the inverted signal TIMER' to a clock input of a first data (D) flip-flop 122. A second D flip-flop 124 has a clock input that receives the inverted first signal PWM' . The data inputs "D" of the flip-flops 122 and 124 are connected to a supply voltage VDD (logic high in this example). The output 128A of the first flip-flop 122 ("Q" flip-flop output) provides a first phase detector output signal UP in a first state (e.g., high) in response to the falling edge of the output pulse signal TIMER. The "Q" output of the second flip-flop 124 is connected to a second output 128B of the phase detector 120. The output 128B provides a second phase detector output signal DOWN in a first state (e.g., high) in response to the falling edge of the first signal PWM. The flip-flops 122 and 124 in FIG. 1 are reset by the active low output of a NAND gate 126, whose inputs are connected to the flip-flop outputs 128 A and 128B.
[0013] In this configuration, the phase detector 120 provides an UP signal in an active first state (high) in response to the falling edge (second edge) of the PWM signal lagging the falling edge of the TIMER signal. The UP signal in this example has a rising edge triggered by the falling edge of the TIMER signal, and a falling edge triggered by the receipt of a lagging PWM signal falling edge. The phase detector 120 provides the DOWN signal in this example in an active (high) first state in response to the falling edge of the PWM signal leading the falling edge of the TIMER signal. The resulting DOWN signal has a rising edge triggered by the falling edge of the PWM signal, and a falling edge triggered by receipt of a lagging TIMER signal falling edge. In steady state operation, the second edges of the TIMER and PWM signals will be aligned, and the UP and DOWN signals will both be generally inactive (low) apart from intermittent glitches. However, any change in the duty cycle of the PWM signal will be detected by the circuit 100, in which case the first and second phase detector output signals UP and DOWN are generated according to any phase difference between the falling edges of the PWM and TIMER signals.
[0014] The charge pump circuit 130 selectively sources or sinks current to or from a capacitor CI according to the UP and DOWN signals to establish the voltage control signal VCTRL at the multivibrator control input 112. The multivibrator 110 provides a feedback path according to the voltage control signal VCTRL to adjust the duration of the TIMER pulses in order to align the second edges of the TIMER and PWM signals. The charge pump circuit 130 includes a first switching circuit 134 that operates when the UP signal is high to connect a first current source 131 to the control input 112 to source a first current II to the capacitor CI . The current source 131 is connected between a first analog supply reference voltage VDDA and the switching circuit 134. A second switching circuit 136 selectively connects a second current source 132 to the control input 112 to sink a second current (e.g., also II in this example) from the capacitor CI when the second phase detector output signal DOWN is high. The second current source 132 is connected between the switching circuit 136 and a second analog supply reference voltage VSSA. The first and second currents are equal in one example, both having a value labeled II in FIG. 1.
[0015] An output circuit 140 provides the status output signal SS at the output 142 in a first state (high) when neither of the first and second phase detector output signals UP, DOWN is in the first state (high). When one of the first and second phase detector output signals UP or DOWN is active (high), the output circuit 140 provides the status output signal SS in a second state (low) indicating a transient event in the associated switching converter. The output circuit 140 in FIG. 1 filters the UP and DOWN signals to generate the status output signal SS. A first low pass filter circuit is formed by a resistor RFl and a capacitor CF1 chosen to have a time constant of a few nanoseconds in one example. The first filter circuit RFl, CF1 receives the UP signal from the phase detector output 128 A and includes an output 144 to provide a first filtered output signal TR+ having a first state (high) when the first phase detector output signal UP is high for a sufficient amount of time. The output circuit 140 also includes a second low pass filter circuit RF2, CF2, including an input coupled with the phase detector output 128B to receive the second phase detector output signal DOWN. An output 146 of the second filter circuit provides a second filtered output signal TR- having a first state (high) when the second phase detector output signal DOWN is high for a sufficient amount of time according to the time constant of the filter circuit RF2, CF2. The output circuit 140 in this example also includes a NOR gate 141 with a first input coupled with the output 144 of the first low pass filter circuit RFl, CFl and a second input coupled with the output 146 of the second low pass filter circuit RF2, CF2. The output 142 of the NOR gate provides the status output signal SS in the first state (high) when neither of the signals TR+, TR- is high to indicate steady state operation of the associated switching converter. The NOR gate 141 provides the status output signal SS in a second state (low) indicating a transient event in the switching converter when one of the first and second filtered output signals TR+, TR- is high.
[0016] FIG. 2 shows an example monostable multivibrator circuit 110 which can be used in the transient event detector circuit 100 of FIG. 1. The multivibrator circuit 110 includes a D flip-flop 200 with a clock input 202 that receives the PWM signal from the transient detector input 102. The flip-flop 200 provides a normal data output signal "Q" at an output 204, and an inverted output "Q"' at a second output 206. A reset input (RST) of the flip-flop 200 is driven by the TEVIER signal on line 208 from the output 114 of the monostable multivibrator circuit 110. The circuit 110 also includes a comparator circuit 210 connected between the analog supply voltage node VDDA at line 212 and the second analog supply VSSA at line 214. The control voltage signal VCTRL is provided to a first comparator input 216. A CMOS input stage including transistors M2 and M3 receives the voltage control signal VCTRL, and the corresponding CMOS circuit output node 218 is connected to gate terminals of PMOS transistors M4 and M5 and to the gates of NMOS transistors M6 and M7. A first switch 221 is connected between the node 218 and VSSA and operates according to the Q' signal to reset the control input side of the comparator circuit 210. The comparator circuit 210 includes a second input node 220 connected to VDDA through a switch 223 and a resistor R. The switch 223 operates according to the Q signal from the flip-flop 200 to selectively deliver charging current to the second input node 220. A multivibrator capacitor C2 is connected between the second input node 220 and VSSA to control the voltage at the node 220. A switch 222 is connected between the node 220 and VSSA in parallel with the capacitor C2. The switch 222 operates according to the Q' signal to discharge the capacitor C2 to reset the voltage at the second input node 220. The voltage across C2 is provided as a gate control signal to a CMOS output formed by a PMOS transistor M8 and an NMOS transistor M9 connected between M5 and M7. The output transistor pair M8 and M9 have drains connected to an output node 224 that provides an input signal to a NOR gate 226. The Q' signal is provided to the other input of the gate 226, and the output of the gate 226 provides the TIMER signal at the multivibrator output 114.
[0017] After the comparator circuit 210 is reset by the switches 221 and 222, the next rising edge of the signal PWM causes the flip-flop Q signal to go high, and the Q' signal to go low. In this state, the switch 223 allows current flow through the resistor R to charge the capacitor C2 until the voltage at the node 220 turns on M9 to bring the voltage at the NOR gate input 224 low. The output of the NOR gate 226 goes high, causing a rising edge in the TIMER signal at the multivibrator output 114. The high state of the TIMER signal resets the flip-flop 200, causing the Q signal to again go low, and the Q' signal to go high. This resets the comparator circuit 210 by closing the switches 221 and 222, and opening the switch 223. The multivibrator circuit 110 controls the pulse width of the TIMER output signal according to the level of the voltage control signal VCTRL. In closed loop operation of the DLL circuit of FIG. 1, reducing the voltage control signal VCTRL reduces the TIMER signal pulse width or pulse duration because less time is required to charge the capacitor C2 to the corresponding level set by VCTRL in the multivibrator circuit 110. Conversely, increasing VCTRL allows the capacitor C2 to charge for a longer time, and thus increases the duration of the TIMER signal pulses.
[0018] The example circuit 100 of FIGS. 1 and 2 compares falling edges of the TIMER and PWM signals. In other examples, rising edge comparisons can be used by a corresponding phase detector circuit 120. In other examples, a phase comparator can compare a rising edge of one of the signals TIMER, PWM with a falling edge of the other signal to selectively provide an output signal based on a phase difference between the compared edges. The circuit 100 in FIG. 1 uses a voltage controlled monostable multivibrator circuit 110 and a feedback loop to implement a DLL in which the output of the variable monostable circuit 110 tracks the duty cycle of the PWM signal. The status signal SS can be used by a host circuit to identify changes in the PWM signal duty cycle, and thereby detect load or line transient events in a corresponding switching converter. In this example, if the switching converter reacts to a transient event through normal close loop PWM regulation of its output signal, the duty cycle of the corresponding PWM signal will change, and this duty cycle change is reflected by either the UP or the DOWN signal within the same PWM control cycle during which the transient event occurred. In certain implementations, the DLL circuit 110, 120, 130 has a bandwidth equal to the bandwidth of a control circuit operating the corresponding switching converter. This enhances transient event detection by ensuring that the controlled switching converter and the DLL become similarly over-slewed for the same type of detectable transient events.
[0019] FIG. 3 shows an example power conversion system 300 in which the transient event detector circuit 100 can be used in combination with a controlled DC-DC switching converter 320 and an associated converter control circuit 302. As described hereinabove, a host system can use the status signal SS to create a transient event flag to initiate appropriate responsive action in the system 300. Also, the TR+ and TR- signals provided at the circuit outputs 144 and 146 can also be used to distinguish between positive and negative transient events. In the example of FIG. 3, an integer number N DC-DC switching converters 320 are used to drive a single load 330 with a regulated output voltage VO, where N is greater than 1. A multiphase converter master controller circuit 340 uses the SS, TR+ and TR- signals to selectively enable or disable certain of the switching converters 320 using corresponding slave control signals SCL1, SCL2,... , SCLN. In this example, the control circuit 302 that operates one of the DC-DC switching converters 320 is included along with the transient event detector circuit 100 in a single integrated circuit (IC) 301. The circuit 100 of FIG. 1 can be used in combination with a variety of different DC-DC converter systems. FIG. 3 shows an example multiphase buck DC-DC converter system 300 with a DC-DC converter circuit 320, and the system 300 includes one or more additional converter circuits 320 (not shown in FIG. 3).
[0020] The system 300 includes a PWM controller integrated circuit (IC) 301 with a transient event detector circuit 100 as described hereinabove that receives a PWM signal at an input 102 from the control circuit 302, and provides the signals SS, TR+ and TR- to the master controller 340. The control circuit 302 implements closed loop voltage control of the output voltage VO to deliver current IO to a load 330. The control circuit 302 in this example includes a modulator circuit 304 that generates the pulse width modulation signal PWM according to one or more feedback signals IFB, VFB to regulate the output voltage signal VO by generating switching control signal SCI and SC2 according to the signal PWM. In the illustrated buck converter example, the modulator 304 generates the first switching control signal SCI by providing a signal to a first driver circuit 306 generally according to the PWM signal, and generates the low side switching control signal SC2 via a second driver circuit 308 according to the inverse of the PWM signal. The drivers 306 and 308 respectively provide first and second switching control signals SCI and SC2 at IC outputs 314 and 316 to operate high and low side switches SI and S2 of the DC-DC switching converter 320. The modulator circuit 304 includes an output 305 that provides the PWM signal to the input 102 of the transient detector circuit 100 as described hereinabove. The control circuit 302 includes a first comparator 310 that compares a voltage reference signal VR to a feedback voltage signal VFB from an IC input 319 for regulating the output voltage VO of the DC-DC converter 320. Also, a second comparator 312 compares a current threshold ITH with a current feedback signal IFB received at an IC input 318 from the DC-DC converter circuit 320. The DC-DC converter switching devices SI and S2 operate according to the switching control signals SCI and SC2 to convert DC input voltage VIN to provide a controlled DC output voltage VO to drive the load 330.
[0021] The first or high side converter switching device SI is coupled between an input voltage node 322 and a switching node 326. The second switching device S2 is connected between the switching node 326 and an output reference voltage node 324 (labeled G D in the drawing). An output inductor L is connected between the switching node 326 and an output node 328. An output capacitor CO is connected between the output node 328 and the reference voltage node 324. A resistive divider network provides the voltage feedback signal VFB to the comparator 310 as a voltage in a node joining resistors Rl and R2 connected in series with one another in parallel with the output capacitor CO. In operation, the control circuit 302 provides alternating pulse width modulated switching control signals SCI and SC2 in order to turn on SI to magnetize the inductor L, and then to turn SI off while turning on S2 in CCM operation for relatively high output current requirements. The inductor L conducts current IL from the switching node 326 to charge the output capacitor CO. Turning on S2 allows current to flow through the inductor L and the output capacitor CO, with the alternate operation of SI and S2 maintaining a regulating the output voltage VO across the capacitor CO. A current sensor senses the inductor current IL to provide the current feedback signal IFB to the IC input 318 for comparison with a threshold ITH via the comparator 312. Controlled operation of the converter circuit 320 drives the load 330 with output current IO.
[0022] Referring also to FIG. 4, a waveform diagram 400 illustrates various signals in the DC-DC converter system 300 of FIG. 3 and the transient event detector circuit 100 of FIG. 1. The PWM signal is shown as curve 410 including a first (e.g., rising) edge 410a and a second (falling) edge 410b. In this example, the PWM signal begins with a rising edge in each of a series of PWM cycles having a cycle period TPWM. The monostable multivibrator output pulse signal TIMER is shown as curve 420 including a first (e.g., rising) edge 420a triggered by the first edge 410a of the pulse with modulation signal PWM, and a second (falling) edge 420b controlled by the multivibrator circuit 110 to set the pulse duration TMS of the pulse output signal TFMER according to the voltage control signal VCTRL. Curves 430 and 440 respectively show the first and second switching control signals SCI and SC2 in the switching converter 320. In this example, an output load current requirement of the switching converter 320 is shown as a curve 450 that varies as a function of time t. A curve 460 shows the status output signal SS remaining in the first state (high) and providing low going pulses at times Tl, T2, T3, T4 and T5 based on the circuit 100 detecting transient events according to duty cycle changes in the PWM signal. The positive transient event signal TR+ is shown as curve 470 and the negative transient event signal TR- is shown as curve 480.
[0023] Between the illustrated times TO and Tl, the output current IO requirement curve 450 is generally constant, and the PWM signal curve 410 accordingly provides a generally constant duty cycle (e.g., approximately 50% in this example). The TFMER signal curve 420 generally tracks the PWM signal curve 410 in the steady state operation between TO and Tl, and the switching control signal curves 430 and 440 generally track the PWM signal 410 by operation of the control circuit 302. Just prior to Tl, the output current requirement curve 450 increases, causing the control circuit 302 to extend the duty cycle of the PWM signal. At Tl, the circuit 100 detects that the falling edge of the PWM signal lags the falling edge of the TFMER signal, causing assertion of the UP signal at the phase detector output 128 A (FIG. 1). The output circuit 140 filters the UP signal, and the resulting filtered signal is provided as a high-going pulse in the TR+ signal curve 470. This TR+ signal pulse switches the output of the NOR gate 141, which provides a low-going pulse in the status output signal SS in curve 460. The output current requirement curve 450 remains generally high between Tl and T2, and the closed loop operation of the switching converter control circuit 302 controls the on-time TON1 of the first switching device SI and the on-time TON2 of S2 according to the PWM signal curve 410.
[0024] At time T2, the output current requirement 10 decreases, causing a corresponding decrease in the PWM signal duty cycle by operation of the control circuit 302. The phase detector circuit 120 asserts the DOWN signal in response to detection of the falling edge 410b of the PWM signal leading the falling edge 420b of the TIMER signal. This creates a high-going pulse in the DOWN signal, which is filtered and provided as a high-going pulse in the TR- curve 480. The TR- pulse switches the NOR gate output 142 which provides another low-going pulse in the SS signal curve 460 to indicate detection of a transient condition in the power converter 320. A further decrease in the output current requirement at T3 causes the transient event detector circuit 100 to generate another low-going pulse in the SS curve 460 and a corresponding high-going pulse in the TR- curve 480. In this example, the current requirement undergoes a further decrease at T4, leading to further pulses in the SS and TR- curves 460 and 480, respectively. Prior to time T5 in FIG. 4, the output load current requirement increases, which causes a further phase difference between the PWM and TIMER signals. In this increasing load current instance, the falling edge of the TIMER signal leads the corresponding falling edge of the PWM signal, and the transient detector circuit 100 generates a low-going pulse in the SS signal curve 460 along with a corresponding high-going pulse in the TR+ curve 470.
[0025] As described hereinabove, the transient event detector circuit 100 advantageously provides one or more signals SS, TR+, TR- to indicate to a host system the occurrence of a transient event associated with a switching converter 320. Also, the circuit 100 provides fast detection of transient events, and provides the signals SS, TR+, TR- in the same PWM switching cycle during which the transient event occur. This is a significant advance over other solutions that used comparators and differentiators created using op amp circuits to differentiate the output voltage to detect the transient event. The examples described herein provide significant transient detection speed improvement, and certain implementations can detect transient events within a few nanoseconds representing gate delays of a few gates in the phase detector circuit 120. Also, the described circuits 100 provide a low power detection solution which cannot be achieved using high-speed differentiating op amp circuitry to achieve the detection speed while using a reasonable amount of current.
[0026] Referring also to FIGS. 5 and 6, the transient event detector circuit 100 can be employed in any form of switching converter system, and can advantageously be incorporated into a master controller and/or a PWM control chip or IC. As described hereinabove in connection with FIG. 3, one possible implementation includes a switching converter control chip 301 having a control circuit 302 for operating an associated switching converter circuit 320, and an on-board transient event detector that consumes the PWM signal from the control circuit 302 and generates one or more of the signals SS, TR+, TR-for internal use or for use by an external multiphase converter master controller 340. The master controller 340, in turn, can selectively control activation states (e.g., enabled or disabled) of one or more converter circuits 320 in a multiphase power conversion system. FIG. 5 shows another example of a multiphase DC-DC power conversion system 500, including an integer number N DC-DC switching converter circuits 320, each connected by a corresponding output inductor LOl, L02, ... , LON to provide (when enabled) a corresponding output current IOl, 102,... , ION to drive a shared load 330. In this example, the individual switching converter circuits 320 receive switching control signals SCI and SC2 from a corresponding control circuit 302. The individual converter systems, referred to herein as "phases" are individually enabled by a corresponding slave control signal SCL1, SCL2,... , SCLN from a multiphase converter master controller circuit 340. The master controller 340 in this case includes an integer number N outputs 148 to provide the slave control signals SCL to the individual control circuits 302. In one example, the slave control signals SCL are 2-state signals causing the corresponding controller 302 to enable or disable operation of the corresponding switching converter 320. The individual control circuits 302 in this case provide their corresponding PWM signals PWM1, PWM2,... PWMN to a transient event detector circuit 100 as described hereinabove. In one example, the transient event detector circuit 100, the control circuits 302 are stand-alone converter control ICs, and the master controller 340 is a separate IC. In this case, the transient event detector circuit IC 100 is connected in a given implementation to the control circuits 302 and to the master controller 340 by appropriate circuit board connections (not shown). FIG. 6 shows another system 600 in which the transient event detector circuit 100 and the master controller 340 are included in a single integrated circuit implementation. In another alternative implementation, the master controller circuitry 340, the transient event detector circuit 100 and the single or multiple converter control circuits 302 can be provided in a single multiphase controller IC.
[0027] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

中文:
[0001]开关转换器用于通过开关电路的操作将电力从一种形式转换成另一形式。实例包含DC-DC开关转换器,其具有开关电路以将DC输入电力转换成可控DC输出以驱动负载。单相系统包含单个开关转换器以驱动负载。多相系统包含彼此并联连接以提供经调节输出电压的两个或两个以上开关转换器,其具有取决于负载电流要求激活或取消激活某些开关转换器的能力。在单相或多相开关转换器系统中,希望对瞬态条件作出反应,所述瞬态条件例如线或负载变化。举例来说,负载电流要求的变化可允许断开或停用一或多个相位以增强整体系统能量效率。其它变化条件可能需要激活一或多个相位以适应增加的负载电流要求。变化的输入电力条件,例如输入电压电平的变化,同样可通过选择性地激活或取消激活多相系统的相位来适应。在个别开关转换器相位的输出处使用并联电感器可改进瞬态响应,但此可在稳态操作中导致能量低效。接着,尽可能快地检测瞬态事件及获知系统何时返回到稳态是极其有利的。瞬态事件通常较短且检测某些事件需要非常高速的电路,从而导致开关转换器设计中的成本及能量效率挑战。增强型效率及智能相位管理可通过快速检测瞬态事件以及系统已返回到稳态操作的快速通知来促成。
[0002]描述的实例包含电力转换系统、集成电路及瞬态事件检测器电路以检测开关转换器中的瞬态事件。在某些实例中,所述瞬态事件检测器电路包含:延迟锁定环路(DLL)电路,其检测用于操作开关转换器的脉冲宽度调制(PWM)信号的工作循环的变化。所述检测器电路在未检测到瞬态事件时在第一状态中提供状态输出信号。所述检测器电路响应于所述PWM信号的所述工作循环的检测到的变化在指示所述开关转换器中的瞬态事件的第二状态中提供所述状态输出信号。在一个实例中,所述DLL电路包含:单稳态多谐振荡器,其生成由所述PWM信号的第一边缘触发的脉冲输出信号;及相位检测器,其根据所述PWM信号的所述第二边缘与所述多谐振荡器脉冲输出信号的受控边缘之间的相位差提供第一及第二输出信号。电荷泵根据相位检测器输出选择性地向电容器供给电流或汲取来自电容器的电流以建立电压控制信号。所述电容器将所述电压控制信号作为控制输入提供到所述多谐振荡器以对准所述多谐振荡器脉冲输出的第二边缘与PWM信号的第二边缘。在某些实例中,所述DLL电路具有等于操作所述开关转换器的控制电路的带宽的带宽使得两个系统针对相同类型的瞬态事件过度扭转。此有利于检测:前一稳态工作循环在于其中发生变化的PWM循环内已改变。快速瞬态检测又有利于单相及/或多相开关转换器系统中的及时智能调整,例如选择性地激活或取消激活多相系统中的一或多个相位。在某些实例中,瞬态事件检测器电路对相位检测器输出信号进行滤波,且根据经滤波相位检测器信号生成状态输出信号。第一及第二经滤波相位检测器信号还可被提供为输出信号以区分正瞬态事件与负瞬态事件。在某些实例中,瞬态事件检测器电路以及控制电路一起被提供于开关控制器集成电路(IC)中以操作开关转换器。在其它实例中,瞬态事件检测器电路与多相转换器主控制器集成,所述多相转换器主控制器从一或多个个别开关转换器控制电路接收PWM信号以基于PWM信号工作循环的变化识别负载及/或线瞬态事件。
[0003]图1是检测PWM信号工作循环中的变化的具有DLL的瞬态事件检测器电路的示意图。
[0004]图2是图1的DLL中的单稳态多谐振荡器的示意图。
[0005]图3是在多相电力转换系统中具有瞬态事件检测器电路的开关转换器控制器IC的示意图。
[0006]图4是展示图1到3的电路中的各种信号的波形图。
[0007]图5是具有将信号提供到主控制器的瞬态事件检测器的多相电力转换系统的系统图。
[0008]图6是具有包含瞬态事件检测器电路的主控制器的多相电力转换系统的系统图。
[0009]在图中,相似的元件符号指代全文的相似元件,且各种特征不一定是按比例绘制。在此描述中,术语“耦合(couple/couples/coupled)”包含间接或直接电或机械连接或其组合。举例来说,如果第一装置耦合到第二装置或与第二装置耦合,那么所述连接可为通过直接电连接或通过经由一或多个中介装置及连接的间接电连接。
[0010]图1展示瞬态事件检测器电路100,其包含从开关转换器控制电路接收第一信号PWM的输入102,第一信号PWM在本文中称为脉冲宽度调制信号PWM。瞬态事件检测器电路100还包含信号输出142、144及146,其分别提供状态输出信号SS、正瞬态信号TR+及负瞬态信号TR-。电路100可用于包含一或多个开关转换器级以将电力从一种形式转换成另一形式的任何形式的电力转换系统中。下文关于DC-DC开关转换器说明且描述实例,但此描述的技术不限于说明的实例。在操作中,开关转换器根据PWM信号操作,且电路100迅速检测到:PWM信号的前一稳态工作循环在于其中发生变化的循环内已改变。电路100提供解决方案以迅速识别开关转换器的输入及/或输出处的瞬态事件,从而允许及时智能响应措施。举例来说,输出SS、TR+及TR-中的一或多者可由转换器控制电路用于智能负载管理以响应于线或负载瞬态事件启用或停用多相电力转换系统中的个别开关转换器相位。
[0012]相位检测器电路120包含第一输入反相器116,其接收TIMER信号且在输出118处提供经反相信号TIMER'。第二反相器117被提供在相位检测器120的第二输入处。反相器117接收PWM信号且在输出119处提供经反相信号PWM'。相位检测器120包含第一输出128A及第二输出128B以根据PWM信号的第二边缘与多谐振荡器脉冲输出信号TIMER的受控第二边缘之间的相位差提供第一输出信号UP及第二输出信号DOWN。反相器116的输出118将经反相信号TIMER'提供到第一数据(D)触发器122的时钟输入。第二D触发器124具有接收经反相第一信号PWM'的时钟输入。触发器122及124的数据输入“D”连接到供应电压VDD(在此实例中为逻辑高)。第一触发器122的输出128A(“Q”触发器输出)响应于输出脉冲信号TIMER的下降边缘在第一状态(例如,高)中提供第一相位检测器输出信号UP。第二触发器124的“Q”输出连接到相位检测器120的第二输出128B。输出128B响应于第一信号PWM的下降边缘在第一状态(例如,高)中提供第二相位检测器输出信号DOWN。图1中的触发器122及124通过NAND门126的低电平有效输出复位,NAND门126的输入连接到触发器输出128A及128B。
[0013]在此配置中,相位检测器120响应于PWM信号的下降边缘(第二边缘)滞后于TIMER信号的下降边缘在第一有效状态(高)中提供UP信号。在此实例中,UP信号具有由TIMER信号的下降边缘触发的上升边缘及通过接收滞后PWM信号下降边缘触发的下降边缘。在此实例中,相位检测器120响应于PWM信号的下降边缘超前于TIMER信号的下降边缘在第一有效(高)状态中提供DOWN信号。所得DOWN信号具有由PWM信号的下降边缘触发的上升边缘及通过接收滞后TIMER信号下降边缘触发的下降边缘。在稳态操作中,TIMER及PWM信号的第二边缘将被对准,且除了间歇性毛刺外,UP及DOWN信号两者都将是大体上无效的(低)。然而,PWM信号的工作循环中的任何变化将由电路100检测,在此情况中,第一相位检测器输出信号UP及第二相位检测器输出信号DOWN根据PWM信号及TIMER信号的下降边缘之间的任何相位差生成。
[0014]电荷泵电路130根据UP及DOWN信号选择性地向电容器C1供给电流或汲取来自电容器C1的电流以在多谐振荡器控制输入112处建立电压控制信号VCTRL。多谐振荡器110根据电压控制信号VCTRL提供反馈路径以调整TIMER脉冲的持续时间以便对准TIMER信号及PWM信号的第二边缘。电荷泵电路130包含第一开关电路134,其在UP信号是高时操作以将第一电流源131连接到控制输入112以向电容器C1源送第一电流I1。电流源131连接于第一模拟供应参考电压VDDA与开关电路134之间。第二开关电路136选择性地将第二电流源132连接到控制输入112以在第二相位检测器输出信号DOWN是高时汲取来自电容器C1的第二电流(例如,在此实例中,也为I1)。第二电流源132连接于开关电路136与第二模拟供应参考电压VSSA之间。在一个实例中,第一及第二电流相等,两者都具有在图1中标记为I1的值。
[0015]输出电路140在第一相位检测器输出信号UP及第二相位检测器输出信号DOWN两者都不处于第一状态(高)中时在输出142处在第一状态(高)中提供状态输出信号SS。当第一相位检测器输出信号UP及第二相位检测器输出信号DOWN中的一者是有效(高)时,输出电路140在指示相关联的开关转换器中的瞬态事件的第二状态(低)中提供状态输出信号SS。图1中的输出电路140对UP及DOWN信号进行滤波以生成状态输出信号SS。在一个实例中,第一低通滤波器电路由经选取以具有几纳秒的时间常数的电阻器RF1及电容器CF1形成。第一滤波器电路RF1、CF1从相位检测器输出128A接收UP信号且包含输出144以在第一相位检测器输出信号UP在充足时间量内是高时提供具有第一状态(高)的第一经滤波输出信号TR+。输出电路140还包含第二低通滤波器电路RF2、CF2,其包含与相位检测器输出128B耦合的输入以接收第二相位检测器输出信号DOWN。第二滤波器电路的输出146在第二相位检测器输出信号DOWN根据滤波器电路RF2、CF2的时间常数在充足的时间量内是高时提供具有第一状态(高)的第二经滤波输出信号TR-。在此实例中,输出电路140还包含NOR门141,其具有与第一低通滤波器电路RF1、CF1的输出144耦合的第一输入及与第二低通滤波器电路RF2、CF2的输出146耦合的第二输入。NOR门的输出142在信号TR+、TR-两者都不是高时在第一状态(高)中提供状态输出信号SS以指示相关联的开关转换器的稳态操作。NOR门141在第一经滤波输出信号TR+及第二经滤波输出信号TR-中的一者是高时在指示开关转换器中的瞬态事件的第二状态(低)中提供状态输出信号SS。
[0016]图2展示可用于图1的瞬态事件检测器电路100中的实例单稳态多谐振荡器电路110。多谐振荡器电路110包含D触发器200,其具有从瞬态检测器输入102接收PWM信号的时钟输入202。触发器200在输出204处提供正常数据输出信号“Q”且在第二输出206处提供经反相输出“Q”。触发器200的复位输入(RST)由线208上的来自单稳态多谐振荡器电路110的输出114的TIMER信号驱动。电路110还包含连接于线212处的模拟供应电压节点VDDA与线214处的第二模拟供应VSSA之间的比较器电路210。控制电压信号VCTRL被提供到第一比较器输入216。包含晶体管M2及M3的CMOS输入级接收电压控制信号VCTRL,且对应CMOS电路输出节点218连接到PMOS晶体管M4及M5的栅极端子及NMOS晶体管M6及M7的栅极。第一开关221连接于节点218与VSSA之间且根据Q'信号操作以复位比较器电路210的控制输入侧。比较器电路210包含通过开关223及电阻器R连接到VDDA的第二输入节点220。开关223根据来自触发器200的Q信号操作以选择性地将充电电流递送到第二输入节点220。多谐振荡器电容器C2连接于第二输入节点220与VSSA之间以控制节点220处的电压。开关222与电容器C2并联连接于节点220与VSSA之间。开关222根据Q'信号操作以使电容器C2放电以复位第二输入节点220处的电压。跨C2的电压作为栅极控制信号被提供到由连接于M5与M7之间的PMOS晶体管M8及NMOS晶体管M9形成的CMOS输出。输出晶体管对M8及M9具有连接到输出节点224的漏极,输出节点224将输入信号提供到NOR门226。Q'信号被提供到门226的其它输入,且门226的输出在多谐振荡器输出114处提供TIMER信号。
[0017]在比较器电路210由开关221及222复位时,信号PWM的下一上升边缘导致触发器Q信号转高且Q'信号转低。在此状态中,开关223允许电流流过电阻器R以给电容器C2充电直到节点220处的电压接通M9以使NOR门输入224处的电压变低。NOR门226的输出转高,从而导致多谐振荡器输出114处的TIMER信号中的上升边缘。TIMER信号的高态使触发器200复位,从而导致Q信号再次转低,且Q'信号转高。此通过闭合开关221及222且断开开关223使比较器电路210复位。多谐振荡器电路110根据电压控制信号VCTRL的电平控制TIMER输出信号的脉冲宽度。在图1的DLL电路的闭合环路操作中,减小电压控制信号VCTRL减小TIMER信号脉冲宽度或脉冲持续时间,这是因为需要较少时间来将电容器C2充电到由多谐振荡器电路110中的VCTRL设置的对应电平。相反地,增加VCTRL允许电容器C2在较长时间内充电,且因此增加TIMER信号脉冲的持续时间。
[0018]图1及2的实例电路100比较TIMER信号及PWM信号的下降边缘。在其它实例中,上升边缘比较可由对应相位检测器电路120使用。在其它实例中,相位比较器可比较信号TIMER、PWM的一者的上升边缘与其它信号的下降边缘以基于所比较的边缘之间的相位差选择性地提供输出信号。图1中的电路100使用电压控制的单稳态多谐振荡器电路110及反馈环路实施DLL,其中可变单稳态电路110的输出跟踪PWM信号的工作循环。状态信号SS可由主机电路使用以识别PWM信号工作循环中的变化,且借此检测对应开关转换器中的负载或线瞬态事件。在此实例中,如果开关转换器通过其输出信号的正常闭合环路PWM调节对瞬态事件作出反应,那么对应PWM信号的工作循环将改变,且此工作循环变化通过瞬态事件在其期间发生的相同PWM控制循环内的UP或DOWN信号得到反映。在某些实施方案中,DLL电路110、120、130具有等于操作对应开关转换器的控制电路的带宽的带宽。此通过确保受控开关转换器及DLL针对相同类型的可检测瞬态事件变为类似地过度扭转增强瞬态事件检测。
[0019]图3展示实例电力转换系统300,其中瞬态事件检测器电路100可与受控DC-DC开关转换器320及相关联的转换器控制电路302组合地使用。如上文描述,主机系统可使用状态信号SS创建瞬态事件旗标以在系统300中起始适当的响应动作。而且,电路输出144及146处提供的TR+及TR-信号还可用于区分正瞬态事件与负瞬态事件。在图3的实例中,整数数目N个DC-DC开关转换器320用于用经调节输出电压VO驱动单个负载330,其中N大于1。多相转换器主控制器电路340使用SS、TR+及TR-信号使用对应从控信号SCL1、SCL2、...、SCLN选择性地启用或停用某些开关转换器320。在此实例中,操作DC-DC开关转换器320中的一者的控制电路302与瞬态事件检测器电路100一起包含于单个集成电路(IC)301中。图1的电路100可与多种不同DC-DC转换器系统组合地使用。图3展示具有DC-DC转换器电路320的实例多相降压DC-DC转换器系统300,且系统300包含一或多个额外转换器电路320(图3中未展示)。
[0020]系统300包含PWM控制器集成电路(IC)301,其具有上文所描述的瞬态事件检测器电路100,其在输入102处从控制电路302接收PWM信号且将信号SS、TR+及TR-提供到主控制器340。控制电路302实施输出电压VO的闭合环路电压控制以将电流IO递送到负载330。在此实例中,控制电路302包含调制器电路304,其根据一或多个反馈信号IFB、VFB生成脉冲宽度调制信号PWM以通过根据信号PWM生成开关控制信号SC1及SC2调节输出电压信号VO。在说明的降压转换器实例中,调制器304通过大体上根据PWM信号将信号提供到第一驱动器电路306生成第一开关控制信号SC1,且根据PWM信号的反转经由第二驱动器电路308生成低侧开关控制信号SC2。驱动器306及308相应地在IC输出314及316处提供第一开关控制信号SC1及第二开关控制信号SC2以操作DC-DC开关转换器320的高侧开关S1及低侧开关S2。调制器电路304包含输出305,其将PWM信号提供到瞬态检测器电路100的输入102,如上文描述。控制电路302包含第一比较器310,其比较电压参考信号VR与来自IC输入319的反馈电压信号VFB以调节DC-DC转换器320的输出电压VO。而且,第二比较器312比较电流阈值ITH与在IC输入318处从DC-DC转换器电路320接收到的电流反馈信号IFB。DC-DC转换器开关装置S1及S2根据开关控制信号SC1及SC2操作以转换DC输入电压VIN以提供受控DC输出电压VO以驱动负载330。
[0021]第一或高侧转换器开关装置S1耦合于输入电压节点322与开关节点326之间。第二开关装置S2连接于开关节点326与输出参考电压节点324(在图中标记为GND)之间。输出电感器L连接于开关节点326与输出节点328之间。输出电容器CO连接于输出节点328与参考电压节点324之间。电阻分压器网络将电压反馈信号VFB提供到比较器310作为接合与彼此串联且与输出电容器CO并联连接的电阻器R1及R2的节点中的电压。在操作中,控制电路302提供交变脉冲宽度调制开关控制信号SC1及SC2以便接通S1以使电感器L磁化,且接着断开S1同时针对相对较高的输出电流要求在CCM操作中接通S2。电感器L传导来自开关节点326的电流IL以给输出电容器CO充电。接通S2允许电流流过电感器L及输出电容器CO,其中S1与S2的交替操作维持调节跨电容器CO的输出电压VO。电流传感器感测电感器电流IL以将电流反馈信号IFB提供到IC输入318以经由比较器312与阈值ITH比较。转换器电路320的受控操作用输出电流IO驱动负载330。
[0022]还参考图4,波形图400说明图3的DC-DC转换器系统300及图1的瞬态事件检测器电路100中的各种信号。PWM信号被展示为曲线410,其包含第一(例如,上升)边缘410a及第二(下降)边缘410b。在此实例中,PWM信号在具有循环周期TPWM的一系列PWM循环中的每一者中以上升边缘开始。单稳态多谐振荡器输出脉冲信号TIMER被展示为曲线420,其包含由脉冲宽度调制信号PWM的第一边缘410a触发的第一(例如,上升)边缘420a及由多谐振荡器电路110控制的第二(下降)边缘420b以根据电压控制信号VCTRL设置脉冲输出信号TIMER的脉冲持续时间TMS。曲线430及440分别展示开关转换器320中的第一开关控制信号SC1及第二开关控制信号SC2。在此实例中,开关转换器320的输出负载电流要求被展示为依据时间t改变的曲线450。曲线460展示保持在第一状态(高)中且基于电路100根据PWM信号中的工作循环变化检测到瞬态事件在时间T1、T2、T3、T4及T5处提供转低的脉冲的状态输出信号SS。正瞬态事件信号TR+被展示为曲线470,且负瞬态事件信号TR-被展示为曲线480。
[0023]在说明的时间T0与T1之间,输出电流IO要求曲线450大体上是恒定的,且PWM信号曲线410因此提供大体上恒定工作循环(例如,在此实例中,是大约50%)。TIMER信号曲线420在T0与T1之间的稳态操作中大体上跟踪PWM信号曲线410,且开关控制信号曲线430及440通过控制电路302的操作大体上跟踪PWM信号410。就在T1之前,输出电流要求曲线450增加,从而导致控制电路302延长PWM信号的工作循环。在T1处,电路100检测到PWM信号的下降边缘滞后于TIMER信号的下降边缘,从而导致在相位检测器输出128A处断言UP信号(图1)。输出电路140对UP信号进行滤波,且所得经滤波信号被提供作为TR+信号曲线470中的转高脉冲。此TR+信号脉冲切换NOR门141的输出,这在曲线460中的状态输出信号SS中提供转低脉冲。输出电流要求曲线450在T1与T2之间大体上保持为高,且开关转换器控制电路302的闭合环路操作根据PWM信号曲线410控制第一开关装置S1的接通时间TON1及S2的接通时间TON2。
[0024]在时间T2处,输出电流要求IO减小,从而通过控制电路302的操作导致PWM信号工作循环中的对应减小。相位检测器电路120响应于检测到PWM信号的下降边缘410b超前于TIMER信号的下降边缘420b断言DOWN信号。此在DOWN信号中创建转高脉冲,所述DOWN信号经滤波且被提供作为TR-曲线480中的转高脉冲。TR-脉冲切换NOR门输出142,NOR门输出142在SS信号曲线460中提供另一转低脉冲以指示检测到电力转换器320中的瞬态条件。T3处的输出电流要求的进一步减小导致瞬态事件检测器电路100在SS曲线460中生成另一转低脉冲且在TR-曲线480中生成对应转高脉冲。在此实例中,电流要求在T4处经受进一步减小,从而在SS曲线460及TR-曲线480中分别导致另外脉冲。在图4的时间T5之前,输出负载电流要求增加,这导致PWM与TIMER信号之间的另一相位差。在此增加负载电流例子中,TIMER信号的下降边缘超前于PWM信号的对应下降边缘,且瞬态检测器电路100在SS信号曲线460中生成转低脉冲,以及在TR+曲线470中生成对应转高脉冲。
[0025]如上文描述,瞬态事件检测器电路100有利地提供一或多个信号SS、TR+、TR-以向主机系统指示发生了与开关转换器320相关联的瞬态事件。而且,电路100提供瞬态事件的快速检测且在瞬态事件在其期间发生的相同PWM开关循环中提供信号SS、TR+、TR-。此显著优于使用了比较器及微分器的其它解决方案,所述比较器及微分器使用运算放大器电路创建以区别输出电压以检测瞬态事件。本文描述的实例提供显著瞬态检测速度改进,且某些实施方案可在几纳秒内检测到表示相位检测器电路120的几个门的门延迟的瞬态事件。而且,描述的电路100提供使用高速微分运算放大器电路不能实现的低电力检测解决方案以在使用合理的电流量时实现检测速度。
[0026]还参考图5及6,瞬态事件检测器电路100可用于任何形式的开关转换器系统中,且可有利地被并入到主控制器及/或PWM控制芯片或IC中。如上文关于图3描述,一个可能实施方案包含:开关转换器控制芯片301,其具有用于操作相关联的开关转换器电路320的控制电路302;及板上瞬态事件检测器,其消耗来自控制电路302的PWM信号且生成信号SS、TR+、TR-中的一或多者以供内部使用或由外部多相转换器主控制器340使用。主控制器340又可选择性地控制多相电力转换系统中的一或多个转换器电路320的激活状态(例如,启用或停用)。图5展示多相DC-DC电力转换系统500的另一实例,其包含整数数目N个DC-DC开关转换器电路320,每一者通过对应输出电感器LO1、LO2、...、LON连接以提供(在启用时)对应输出电流IO1、IO2、...、ION以驱动共享负载330。在此实例中,个别开关转换器电路320从对应控制电路302接收开关控制信号SC1及SC2。个别转换器系统,在本文中称为“相位”,通过来自多相转换器主控制器电路340的对应从控信号SCL1、SCL2、...、SCLN个别地启用。在此情况中,主控制器340包含整数数目个输出148以将从控信号SCL提供到个别控制电路302。在一个实例中,从控信号SCL是2状态信号,从而导致对应控制器302启用或停用对应开关转换器320的操作。在此情况中,个别控制电路302将其对应PWM信号PWM1、PWM2、...、PWMN提供到瞬态事件检测器电路100,如上文描述。在一个实例中,瞬态事件检测器电路100、控制电路302是独立转换器控制IC,且主控制器340是单独IC。在此情况中,瞬态事件检测器电路IC 100在给定实施方案中通过适当的电路板连接(未展示)连接到控制电路302及主控制器340。图6展示其中瞬态事件检测器电路100及主控制器340被包含于单个集成电路实施方案中的另一系统600。在另一替代实施方案中,主控制器电路340、瞬态事件检测器电路100及单相或多相转换器控制电路302可被提供于单个多相控制器IC中。
[0027]在描述的实施例中,修改是可能的,且权利要求书的范围内的其它实施例是可能的。