English:
[0001] Generally, for reliable circuit design, various transient protection circuits are implemented to protect electronic devices from high voltage surges. For example, certain protection circuits protect electronic devices from electrostatic discharge (ESD). ESD can cause serious damage to electronic devices and most reliable designs include some form of ESD protection. Typically, ESD protection circuits are implemented in parallel with various electronic device circuits and provide least resistive paths to a ground or other nodes for transient currents, thus bypassing and protecting electronic devices. The size of ESD protection circuits increases with voltage levels of the components in which they are implemented and can use up significant semiconductor area in electronic devices.
[0003] FIG. 1 is a schematic diagram of conventional ESD protection circuitry.
[0005] FIG 3A is a cross sectional view of a semiconductor device that includes the diode and the resistance of FIG. 2 located in a substrate.
[0006] FIG. 3B is a top plan view of the semiconductor device of FIG. 3 A.
[0008] FIG. 4B is a top plan view of the semiconductor device of FIG. 4A.
[0009] FIG. 5 is a schematic diagram of an ESD circuit that provides isolation of the ESD components.
[0010] FIG. 6 is a cross-sectional view of an example of a semiconductor device implementing the ESD circuit of FIG. 5.
[0011] FIG. 7 is a schematic diagram of an ESD circuit.
[0012] The following description provides many different embodiments, or examples, for implementing different features of semiconductor devices implemented as electrostatic discharge (ESD) protection devices and/or circuits. These descriptions are merely for illustrative purposes and do not limit the scope of the invention.
[0013] ESD protection circuits, devices, and methods are disclosed herein. Some examples described herein are implemented for bidirectional ESD protection, which has been troublesome to implement in the past. Some of the ESD protection circuits disclosed herein may be fabricated into semiconductor devices using various existing technologies without any dedicated mask/process steps. The characteristics of the ESD protection circuits can be tuned according to a particular bidirectional pin specific application by adjusting layout parameters as described herein.
[0014] FIG. 1 is a schematic diagram of conventional ESD protection circuitry 100, which may be implemented in another circuit (not shown). For example, the circuitry 100 may be coupled to each pin or contact of an integrated circuit that has a plurality of contacts. The circuitry 100 is coupled to a voltage source or power supply 104 that generates a voltage VI 1 and to a second voltage potential, which in the example of FIG. 1 is ground. A first diode 110 is coupled between the power supply 104 and a node Ni l . A second diode 112 is coupled between the node Nl 1 and ground. The node Nl 1 is coupled to a pin or other conductor 120 that is coupled to or a part of the other circuit described above. In some examples, the conductor 120 is a conductor or an input/output (I/O) node in the other circuit. An ESD clamp 128 is coupled between the power supply 104 and ground. In case of an ESD event occurring at the conductor 120, either of the diodes 110 or 112 will conduct a resulting transient current to ground or to the power supply 104. In other situations, the transient current may conduct through the ESD clamp 128. The circuitry 100 conducts the transient current to the power supply 104 or ground, which protects components coupled to the contact 120 from being damaged or temporarily malfunctioning as a result of the transient current.
[0015] The circuitry 100 has many limitations. As noted in FIG. 1, the circuitry 100 requires two diodes 110, 112, and an ESD clamp 128. These components require space on the larger circuit, which defeats the purpose of reducing the size of many circuits. When the circuitry 100 is implemented with input/output (I/O) pins or contacts, each pin has a dedicated ESD protection circuitry 100 coupled to the ground bus or ESD diodes coupled to the power supply bus and ground bus, which may be relatively complex. In addition, pins having different voltages require different ESD protection circuitry 100 with components selected for the specific voltage requirements. Other conventional ESD protection circuits are similar to the circuitry 100, but include transistors coupled in series between the power supply 104 and ground. A resistor that couples the node Nl 1 to the junction of the transistors may be needed to protect them during an ESD event. To compensate the loss across the additional resistor, these transistors are large and use excessive space on an integrated circuit or other device.
[0016] Bidirectional ESD protection applications are particularly challenging because the voltage on the contact 120 can swing to both positive and negative during normal operation. These types of pins require special ESD protection circuits and full electrical isolation, which is complex and usually leads to additional process masks and thus higher cost.
[0017] FIG. 2 is a schematic diagram of ESD protection circuitry 200 that overcomes limitations in the circuitry 100 of FIG. 1. The circuitry 200 may be implemented in another circuit (not shown). The circuitry 200 may be coupled to a voltage source or power supply 204 at a node N21, wherein the power supply 204 generates a voltage V21. The circuitry 200 may also be coupled to a second voltage potential at a node N22, which in the example of FIG. 2 is ground. The node N21 is sometimes referred to as a first node and the node N22 is sometimes referred to as second node. A diode 210 is coupled between the power supply 204 (node N21) and a node N23. A resistor 220 is coupled between the node N23 and ground (node N22). The resistor 220 is shown as being a variable resistor, wherein the value of the resistor 220 is dependent on the voltage applied to the diode 210 as described below. For example, the resistance of the resistor 220 may vary depending on the voltage potential at node N21. Node N23 is coupled to a terminal or other conductor 230 that is coupled to another circuit (not shown) that is protected by the circuitry 200. In some examples, the conductor 230 is a conductor or an input/output (I/O) terminal or pad in the other circuit. Both the diode 210 and the resistor 220 may be integrally formed in a substrate as a single semiconductor device or unit as described below. The circuitry 200 further includes an ESD clamp 240 coupled between the nodes N21 and N22. As noted in FIG. 2, the circuitry 200 only requires one diode instead of two diodes.
[0018] When an ESD event occurs at the conductor 230, either the diode 210 or the resistor 220 conducts the resulting transient current to ground or the power supply 204 depending on the polarity of the ESD event. More specifically, current resulting from positive ESD events between the conductor 230 and the power supply 204 flows to the power supply 204 through the diode 210. Current resulting from positive or negative ESD events between the contact 230 and ground flows through the resistor 220 to ground. The ESD clamp 128 may still be included in the circuitry 200 for the ESD strike protection with a negative voltage on the contact 230 relative to the voltage V21.
[0019] FIG 3A is a cross sectional view of a semiconductor device 300 that includes the diode 210 and the resistor 220 of FIG. 2 fabricated into or located within a substrate 302. FIG. 3B is a top plan view of the semiconductor device 300 of FIG. 3A. The semiconductor device 300 is described herein as having certain p-type and n-type layers or regions, which may be switched in some examples. As shown in FIG. 3 A, the resistor 220 is integral to the diode 210 as described herein and the two are not necessarily separate components.
[0020] The substrate 302 in the example of FIGS. 3A and 3B is a p-type material that is sometimes referred as a p-type material or region, meaning a p-type material has been diffused into the substrate 302. The semiconductor device 300 includes an n-type buried layer (NBL) 304 fabricated into the substrate 302. The layer 304 is sometimes referred to as a doped semiconductive region that is disposed in the substrate 302. The NBL 304 is situated substantially parallel to a substrate surface 322 of the substrate 302. The NBL 304 has an opening 310 that couples the interior 312 of the semiconductor device 300 with the substrate 302. As described in greater detail below, the opening 310 provides a current path during an ESD event. An Nwell 320 extends between the NBL 304 and the surface 322 of the substrate
[0021] The semiconductor device 300 further includes a P+ layer 340 formed therein, which is sometimes referred to herein as a doped semiconductive region in the substrate 302. The P+ layer 340 is coupled to a node or terminal, such as the ground node (node N22) shown in FIG. 2 and serves as a path for current during an ESD event. More specifically, the anode of the diode 210 is coupled to the P+ layer 340 by way of the resistor 220 created by the opening 310 in the NBL 304. The value of the resistor 220 is a function of the voltage potential at the anode of the diode 210 during an ESD event. The resistor 220 is described as being in the opening 310. In practice, the opening 310 forms a resistive path noted as the resistor 220.
[0022] The value of the resistor 220 is dependent on the voltage potential of the cathode of the diode 210. The resistance increases with the voltage potential of the cathode. Eventually, a certain potential is reached, which is determined by the layout of the semiconductor device 300 and the opening 310, and causes the resistance to become very high or infinite. The high resistance isolates the interior 312 from the substrate 302. Accordingly, during normal operation, the voltage potential on the cathode is high, resulting in a very high or infinite resistance. The high resistance prevents the circuitry 200, FIG. 2, from interfering with signals transmitted to other circuitry (not shown) by way of the contact 230. The high resistance also enables the voltage on the contact 230 to swing positive or negative with respect to the substrate 302 since the interior 312 is completely isolated from the substrate 302. During an ESD event between the contact 230 and ground, the resistance of the resistor 220 is small because node N21 is not biased, creating a low resistance path from the anode of the diode 210, which is coupled to the contact 230, to ground. With reference to FIG. 3 A, the resistance path is between the Pwell 330 and the P+ layer 340 through the opening 310, which constitutes the resistor 220. This low resistance path prevents transients generated during the ESD event from causing problems with the circuitry or damaging components.
[0023] During positive ESD events between the contact 230 and the power supply 204, the diode 210 is forward biased, so the current generated by the transients during the ESD event are conducted to the power supply 204. With reference to FIG. 3 A, the transient currents flow from the Pwell 330 to the Nwell 320, which is coupled to the power supply 204. During a negative ESD event, the cathode voltage floats, so the resistance of the resistor 220 is small, creating a low resistance path to ground. Currents generated by the transients during the ESD event pass through the resistor 220, which has low resistance, to ground, so they do not interfere with circuits coupled to the contact 230.
[0024] The voltage on the cathode that causes a significant increase in the resistance of the resistor 220 is referred to as the punch-through voltage and is at least partially dependent on the size of the opening 310 in the NBL 304. A smaller opening 310 results in a smaller punch- through voltage. During fabrication of the semiconductor device 300, the size of the opening 310 is set to a specific punch-through voltage depending on the application of the semiconductor device 300.
[0025] FIG. 4A is a cross-sectional view of an example of a semiconductor device 400 implementing the circuitry 200 of FIG. 2, which includes the diode 210 and the resistor 220. FIG. 4B is a top plan view of the semiconductor device 400 of FIG. 4A. The semiconductor device 400 includes the diode 210 and the resistor 220 fabricated into a substrate 408. The semiconductor device 400 is similar to the semiconductor device 300 of FIG. 3 with the exception of an opening in the Nwell rather than the NBL. The substrate 408 in the example of FIGS. 4A and 4B is a p-type material and includes an NBL 410 fabricated into or located within the substrate 408 and situated substantially parallel to the surface 422 of the substrate 408. The NBL 410 is sometimes referred to as a doped semiconductive region in the substrate 408. An Nwell 420 extends between the NBL 410 and the surface 422 of the substrate 408 and is substantially perpendicular to the surface 422. The Nwell 420 at least partially contacts the NBL 410. The NBL 410 and the Nwell 420 form an isolation tank 424 having an interior 426. The Nwell 420 serves as the cathode of the diode 210. A Pwell 430 is located within the interior 426 of the isolation tank 424 so as to be at least partially surrounded by the Nwell 420. The Pwell 430 serves as the anode of the diode 210. The Nwell 420 and the Pwell 430 are sometimes referred to as doped semiconductive regions.
[0026] The Nwell 420 has an opening 434 formed therein that serves as the resistor 220 described in FIG. 2. As described above, the resistance of the resistor 220 is a function of the cathode voltage, which is the voltage applied to the Nwell 420. The punch-through voltage associated with the opening 434 is proportional to the size of the opening 434 as described above. The substrate 408 includes a P+ layer 440 formed therein, which is sometimes referred to as the fourth layer or fourth doped semiconductor region. The P+ layer 440 is coupled to a terminal or a node, such as the ground node (node N22) shown in FIG. 2 and serves as a path for current during an ESD event. More specifically, the anode of the diode 210 is coupled to the P+ layer 440 by way of the resistor 220 created by the opening 434 in the Nwell 420. The value of resistance is a function of the voltage potential at the anode of the diode 210 during an ESD event and during normal operation.
[0027] The opening 434 fabricated in the Nwell 420 creates a shorter current path between the anode and the ground, which is coupled to the P+ layer 440, relative to an opening fabricated in the NBL 410 as described with reference to FIG. 3. The semiconductor device 400 is more effective than the semiconductor device 300 of FIG. 3 at ESD protection, but its fabrication may be more difficult.
[0028] FIG. 5 is a schematic diagram of an ESD circuit 500 that provides isolation of the ESD components. The circuit 500 includes a first diode 504 and a second diode 506 that have their cathodes coupled to a node N51. In the example of FIG. 5, node N51 is coupled to a power supply 510, which may be a voltage source. The anodes of the diodes 504 and 506 are coupled together by way of a resistor 520, which is substantially similar to the resistor 220 of FIG. 2. The anode of the first diode 504 is coupled to a terminal or contact 522 that may be coupled to another circuit (not shown) that is being protected from ESD events. The anode of the second diode 506 is coupled to a reference node 524 that is coupled to a potential that is different than the voltage of the power supply 510. As shown in FIG. 5, the circuit 500 provides complete isolation.
[0029] FIG. 6 is a cross sectional view of an example of a semiconductor device 600 that implements the circuit 500 of FIG. 5. The semiconductor device 600 includes a first P+ layer 602 and a second P+ layer 604 located in the interior 608 of an isolation tank 610. The contact 522 is coupled to the first P+ layer 602 and the reference node REF is coupled to the second P+ layer 604. An Nwell 616 is located in the interior of the isolation tank 610 and forms the cathodes of the diodes 504 and 506, FIG. 5. The anode of the first diode 504 is coupled to the first P+ layer 602 and the anode of the second diode 506 is coupled to the second P+ layer 604. An Nwell 618 and an NBL 620 form the isolation tank 610. The layer 602, layer 604, Nwell 616, Nwell 618, and the NBL 620 are sometimes referred to as doped semiconductor regions.
[0030] The resistor 520 is formed between the Nwell 616 and the NBL 620. The electrical path between the P+ layer 602 and the P+ layer 604 is referred to as a resistive path having a variable resistor. The resistance of the resistor 520 is a function of the voltage potential on the cathode of the diodes 504 and 506. One benefit of the semiconductor device 600 is that the resistor 520 is completely electrically isolated within the isolation tank 610.
[0031] FIG. 7 is a schematic diagram of another ESD circuit 700. The circuit 700 includes a diode 702 having an anode and a cathode that are coupled together at a node N71. The node N71 is coupled to a contact 706 that is coupled to a power supply 710. A variable resistor 720 is coupled between the node N71 and ground. The circuit 700 is implemented to protect the power supply 710 from ESD events. Referring to FIG. 3B, the circuit 700 may be implemented in the semiconductor device 300 by coupling the anode and cathode of the diode 230 together. Accordingly, the power supply 710 may be coupled to either node of the diode 230.
[0032] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

中文:
[0001]通常,为实现可靠的电路设计,实施各种瞬变保护电路以保护电子装置免受高压浪涌的影响。举例来说,某些保护电路保护电子装置免受静电放电(ESD)的影响。ESD可对电子装置造成严重损害且大部分可靠设计都包含某种形式的ESD保护。通常,ESD保护电路与各种电子装置电路并联地实施,且为瞬变电流提供到接地或其它节点的最小电阻路径,从而因此旁路并保护电子装置。ESD保护电路的大小随其中实施ESD保护电路的组件的电压电平而增大,且可在电子装置中使用较大半导体区域。
[0003]图1为常规ESD保护电路的示意图。
[0005]图3A为半导体装置的横截面图,所述半导体装置包含位于衬底中的图2的二极管及电阻。
[0006]图3B为图3A的半导体装置的顶部平面图。
[0008]图4B为图4A的半导体装置的顶部平面图。
[0009]图5为提供ESD组件隔离的ESD电路的示意图。
[0010]图6为实施图5的ESD电路的半导体装置的实例的横截面图。
[0011]图7为ESD电路的示意图。
[0012]以下描述提供用于实施被实施为静电放电(ESD)保护装置及/或电路的半导体装置的不同特征的许多不同实施例或实例。这些描述仅仅是出于说明的目的且并不限制本发明的范围。
[0013]本文中公开ESD保护电路、装置及方法。本文中所描述的一些实例用于双向ESD保护,这在过去是难以实施的。本文中所公开的ESD保护电路中的一些可使用各种现有技术制造到半导体装置中,而无需任何专用掩模/工艺步骤。可通过调整布局参数来根据特定双向引脚特殊应用调谐ESD保护电路的特性,如本文中所描述。
[0014]图1为可实施于另一电路(未示出)中的常规ESD保护电路100的示意图。举例来说,电路100可耦合到具有多个接点的集成电路的每一引脚或接点。电路100耦合到生成电压V11的电压源或电力供应器104,且耦合到第二电压电势(在图1的实例中为接地)。第一二极管110耦合在电力供应器104与节点N11之间。第二二极管112耦合在节点N11与接地之间。节点N11耦合到引脚或其它导体120,所述引脚或导体耦合到上文所描述的其它电路或为其部分。在一些实例中,导体120为其它电路中的导体或输入/输出(I/O)节点。ESD箝位电路128耦合在电力供应器104与接地之间。在导体120处发生ESD事件的状况下,二极管110或112中的任一个将所得瞬变电流传导到接地或电力供应器104。在其它情况下,瞬变电流可传导通过ESD箝位电路128。电路100将瞬变电流传导到电力供应器104或接地,此情况保护耦合到接点120的组件不因瞬变电流而受损或暂时发生故障。
[0015]电路100具有许多限制。如图1中所提到,电路100需要两个二极管110、112及ESD箝位电路128。这些组件需要较大电路上的空间,这就违背了降低许多电路的大小的目的。当电路100与输入/输出(I/O)引脚或接点一起实施时,每一引脚都具有耦合到接地总线的专用ESD保护电路100,或耦合到电力供应总线及接地总线的ESD二极管,这可能相对复杂。另外,具有不同电压的引脚需要具有选定用于特殊电压要求的组件的不同ESD保护电路100。其它常规ESD保护电路类似于电路100,但包含串联耦合在电力供应器104与接地之间的晶体管。可能需要将节点N11耦合到晶体管的结的电阻器以在ESD事件期间对其进行保护。为补偿跨越额外电阻器的损耗,这些晶体管较大且在集成电路或其它装置上使用过多空间。
[0016]双向ESD保护应用特别具有挑战性,这是因为在正常操作期间,接点120上的电压可摆动为正及负两者。这些类型的引脚需要特殊ESD保护电路及完全电隔离,这是复杂的且通常产生额外工艺掩模且因此导致成本较高。
[0017]图2为克服图1电路100中的限制的ESD保护电路200的示意图。电路200可实施于另一电路(未示出)中。电路200可在节点N21处耦合到电压源或电力供应器204,其中电力供应器204生成电压V21。电路200还可在节点N22处耦合到第二电压电势,其在图2的实例中为接地。节点N21有时被称为第一节点且节点N22有时被称为第二节点。二极管210耦合在电力供应器204(节点N21)与节点N23之间。电阻器220耦合在节点N23与接地(节点N22)之间。电阻器220示出为可变电阻器,其中电阻器220的值取决于施加到二极管210的电压,如下文所描述。举例来说,电阻器220的电阻可取决于节点N21处的电压电势而变化。节点N23耦合到端子或其它导体230,所述端子或导体耦合到由电路200保护的另一电路(未示出)。在一些实例中,导体230为其它电路中的导体或输入/输出(I/O)端子或垫片。二极管210及电阻器220两者可在衬底中一体成型为单个半导体装置或单元,如下文所描述。电路200进一步包含耦合在节点N21与N22之间的ESD箝位电路240。如图2中所提到,电路200仅需要一个二极管而非两个二极管。
[0018]当导体230处发生ESD事件时,二极管210或电阻器220取决于ESD事件的极性,将所得瞬变电流传导到接地或电力供应器204。更具体地说,由导体230与电力供应器204之间的正ESD事件引起的电流通过二极管210流到电力供应器204。由接点230与接地之间的正或负ESD事件引起的电流通过电阻器220流到接地。ESD箝位电路128可仍包含在电路200中,以用于接点230上相对于电压V21具有负电压情况下的ESD冲击保护。
[0019]图3A为半导体装置300的横截面图,所述半导体装置包含制造到或位于衬底302内的图2的二极管210及电阻器220。图3B为图3A的半导体装置300的顶部平面图。半导体装置300在本文中描述为具有某些p型及n型层或区域,所述层或区域在一些实例中可交换。如图3A中所示出,电阻器220如本文中所描述般与二极管210成一体式,且所述两组件未必为分离组件。
[0020]图3A及3B的实例中的衬底302为有时被称作p型材料或区域的p型材料,这意味着p型材料已扩散到衬底302中。半导体装置300包含制造到衬底302中的n型埋层(NBL)304。层304有时被称为安置于衬底302中的掺杂半导电区域。NBL 304定位成大体上平行于衬底302的衬底表面322。NBL 304具有将半导体装置300的内部312与衬底302耦合的开口310。如下文更详细地描述,开口310在ESD事件期间提供电流路径。N阱320在NBL 304与衬底302的表面322之间延伸。N阱320及NBL 304界定隔离槽324,其中内部312处于隔离槽324内。N阱320在本文中有时被称作衬底302中的掺杂半导电区域,且大体上垂直于表面322延伸。N阱320充当二极管210(图2)的阴极。P阱330形成于内部312内,以便由N阱320部分环绕且在隔离槽324内。P阱330充当二极管210的阳极,且在本文中有时被称作衬底302中的掺杂半导电区域。
[0021]半导体装置300进一步包含形成于其中的P+层340,所述层在本文中有时被称作衬底302中的掺杂半导电区域。P+层340耦合到节点或端子且在ESD事件期间充当电流路径,所述节点或端子例如图2中示出的接地节点(节点N22)。更具体地说,二极管210的阳极借助于由NBL 304中的开口310产生的电阻器220耦合到P+层340。在ESD事件期间,电阻器220的值随二极管210的阳极处的电压电势而变。电阻器220被描述为在开口310中。在实践中,开口310形成提到为电阻器220的电阻性路径。
[0022]电阻器220的值取决于二极管210的阴极的电压电势。电阻随阴极的电压电势而增大。最终,达到由半导体装置300及开口310的布局确定的某一电势,且导致电阻变得极高或无穷大。高电阻会隔离内部312与衬底302。因此,在正常操作期间,阴极上的电压电势较高,从而带来极高或无穷大的电阻。高电阻防止电路200(图2)干扰借助于接点230发射到其它电路(未示出)的信号。高电阻也使得接点230上的电压能够相对于衬底302摆动为正或负,这是因为内部312与衬底302完全隔离。在接点230与接地之间发生ESD事件期间,因为节点N21未被偏压,所以电阻器220的电阻较小,从而产生从耦合到接点230的二极管210的阳极到接地的低电阻路径。参考图3A,电阻路径在P阱330与P+层340之间,所述路径通过构成电阻器220的开口310。此低电阻路径防止ESD事件期间生成的瞬变造成电路问题或损害组件。
[0023]在接点230与电力供应器204之间发生正ESD事件期间,二极管210被正向偏压,因此由ESD事件期间的瞬变生成的电流被传导到电力供应器204。参考图3A,瞬变电流从P阱330流动到耦合到电力供应器204的N阱320。在负ESD事件期间,阴极电压浮动,因此电阻器220的电阻较小,从而产生到接地的低电阻路径。由ESD事件期间的瞬变生成的电流穿过具有低电阻的电阻器220到接地,因此其并不干扰耦合到接点230的电路。
[0024]阴极上导致电阻器220的电阻显著增大的电压被称为穿通电压,且其至少部分地取决于NBL 304中的开口310的大小。较小开口310带来较小穿通电压。在半导体装置300的制造期间,取决于半导体装置300的应用,将开口310的大小设定成特殊穿通电压。
[0025]图4A为实施图2的电路200的半导体装置400的实例的横截面图,所述电路包含二极管210及电阻器220。图4B为图4A的半导体装置400的顶部平面图。半导体装置400包含制造到衬底408中的二极管210及电阻器220。除开口在N阱中而非NBL中之外,半导体装置400类似于图3的半导体装置300。图4A及4B的实例中的衬底408为p型材料,且包含制造到或位于衬底408内且定位成大体上平行于衬底408的表面422的NBL 410。NBL 410有时被称为衬底408中的掺杂半导电区域。N阱420在NBL 410与衬底408的表面422之间延伸,且大体上垂直于表面422。N阱420至少部分地接触NBL 410。NBL 410及N阱420形成具有内部426的隔离槽424。N阱420充当二极管210的阴极。P阱430位于隔离槽424的内部426内,以便由N阱420至少部分地环绕。P阱430充当二极管210的阳极。N阱420及P阱430有时被称为掺杂半导电区域。
[0026]N阱420具有充当图2中所描述的电阻器220的形成于其中的开口434。如上文所描述,电阻器220的电阻随阴极电压(其为施加到N阱420的电压)而变。与开口434相关联的穿通电压与开口434的大小成比例,如上文所描述。衬底408包含形成于其中的P+层440,所述层有时被称为第四层或第四掺杂半导体区域。P+层440耦合到端子或节点且在ESD事件期间充当电流路径,所述端子或节点例如图2中示出的接地节点(节点N22)。更具体地说,二极管210的阳极借助于由N阱420中的开口434产生的电阻器220耦合到P+层440。在ESD事件期间及正常操作期间,电阻值随二极管210的阳极处的电压电势而变。
[0027]相对于如参考图3所描述的制造于NBL 410中的开口,制造于N阱420中的开口434在阳极与耦合到P+层440的接地之间产生较短电流路径。半导体装置400在ESD保护方面比图3的半导体装置300更有效,但其制造可能较困难。
[0028]图5为提供ESD组件隔离的ESD电路500的示意图。电路500包含其阴极耦合到节点N51的第一二极管504及第二二极管506。在图5的实例中,节点N51耦合到可为电压源的电力供应器510。二极管504及506的阳极借助于电阻器520耦合在一起,所述电阻器大体上类似于图2的电阻器220。第一二极管504的阳极耦合到端子或接点522,所述端子或接点可耦合到被保护以免受ESD事件影响的另一电路(未示出)。第二二极管506的阳极耦合到参考节点524,所述参考节点耦合到不同于电力供应器510的电压的电势。如图5中所示出,电路500提供完全隔离。
[0029]图6为实施图5的电路500的半导体装置600的实例的横截面图。半导体装置600包含位于隔离槽610的内部608中的第一P+层602及第二P+层604。接点522耦合到第一P+层602,且参考节点REF耦合到第二P+层604。N阱616位于隔离槽610的内部中且形成二极管504及506(图5)的阴极。第一二极管504的阳极耦合到第一P+层602,且第二二极管506的阳极耦合到第二P+层604。N阱618及NBL 620形成隔离槽610。层602、层604、N阱616、N阱618及NBL620有时被称为掺杂半导体区域。
[0030]电阻器520形成于N阱616与NBL 620之间。P+层602与P+层604之间的电路径被称为具有可变电阻器的电阻性路径。电阻器520的电阻随二极管504及506的阴极上的电压电势而变。半导体装置600的一个益处在于电阻器520在隔离槽610内被完全电隔离。
[0031]图7为另一ESD电路700的示意图。电路700包含二极管702,其具有在节点N71处耦合在一起的阳极及阴极。节点N71耦合到接点706,所述接点耦合到电力供应器710。可变电阻器720耦合在节点N71与接地之间。电路700用以保护电力供应器710免受ESD事件的影响。参考图3B,可通过将二极管230的阳极及阴极耦合在一起而将电路700实施于半导体装置300中。因此,电力供应器710可耦合到二极管230的任一节点。
[0032]在权利要求书的范围内,对所描述实施例的修改是可能的,且其它实施例是可能的。