English:
[0001] This disclosure relates generally to semiconductors, and more specifically, to voltage circuits used in semiconductors.
[0002] Integrated circuits typically use charge pump circuits to boost a supply voltage to a value that is greater than the actual supply voltage value. Charge pumps are advantageous for creating a boost supply because they can be implemented in an integrated circuit. Many different types of charge pump circuits have been described to accomplish this function. In memory circuits, such as FLASH memory, a circuit node is charged to an elevated voltage. The circuit node is subsequently discharged. To discharge the circuit node a transistor or current source is connected to the circuit node to couple the circuit node to a ground voltage potential. The charge movement results in a current flow to discharge the boosted potential through the transistor or current source. The current flow is discharged to the ground terminal and all of the charge is lost as dissipated power. When integrated circuits include high capacitance nodes, the resulting power loss is substantial.
[0003] The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
[0005] FIG. 2 illustrates in schematic form one embodiment of a charge and discharge voltage generator used in the circuit of FIG. 1 ;
[0006] FIG. 3 illustrates in timing diagram form exemplary voltage variation of a circuit node during charge use and charge reuse operations;
[0007] FIG. 4 illustrates in timing diagram form a known voltage variation of a circuit node during charge and discharge operations;
[0008] FIG. 5 illustrates in timing diagram form exemplary voltage variation of a circuit node during partial discharge and subsequent discharge phases; and
[0009] FIG. 6 illustrates in block diagram form a first embodiment of a voltage circuit for discharging a circuit node in two distinct discharge phases.
[0010] Illustrated in FIG. 1 is a circuit 10 for charging and discharging a circuit node 14 in a power efficient manner. Circuit 10 accomplishes the charging and discharging of circuit node 14 by reusing the charge of circuit node 14 by conserving a portion of the charge existing on circuit node 14. A clock oscillator 18 has an enable input for receiving an On/Off' signal. The clock oscillator 18 has an output connected to an input of a clock generator 20. The clock oscillator 18 and clock generator 20 may be collectively considered as clock circuitry and implemented in a single circuit portion or as separate circuits as illustrated. A first output of clock generator 20 provides a first clock signal labeled "CIk 1" to a first input of a charge and discharge voltage generator 12, and a second output of clock generator 20 provides a second clock signal labeled "CIk 2" to a second input of the charge and discharge voltage generator 12. The charge and discharge voltage generator 12 functions as a charge pump circuit. An input/output terminal of the charge and discharge voltage generator 12 is connected to an input/output terminal of a charge source 21. In one form the charge source provides a supply voltage labeled VDD. An output of the charge and discharge voltage generator 12 is connected to the circuit node 14. Circuit node 14 is a predetermined node within an integrated circuit or within a circuit system, such as a node of a printed circuit board or card. A first input of a voltage detector 16 is connected to the circuit node 14. A second input of voltage detector 16 receives a first voltage, such as the supply voltage VDD. A third input of voltage detector 16 receives a second voltage, such as (-V), which is a negative voltage referenced to VDD. An output of the voltage detector 16 provides an "On/Off" signal and is connected to an Enable input of the clock oscillator 18. A control circuit 22 has an output for providing an "Up/Down" signal. The output of control circuit 22 is connected to a third input of the charge and discharge voltage generator 12 and to a fourth input of voltage detector 16.
[0011] In operation, the charge source 21 bidirectionally sources charge to and sinks charge from the charge and discharge voltage generator 12 as the charge and discharge voltage generator 12 respectively charges circuit node 14 to a predetermined voltage and discharges circuit node 14 from the predetermined voltage returning charge to the charge source 21. As used herein the term "charge" is understood to mean the placing of a desired voltage, either positive or negative, on a circuit node or storage device. The term "discharge" is understood to mean the removing of a desired voltage, either positive or negative, on a circuit node or storage device. The voltage detector 16 that is coupled to circuit node 14 monitors the voltage potential at circuit node 14. Circuitry that is not shown determines when the circuit node 14 should be charged or discharged. Also, circuitry that is not shown is connected to the circuit node 14 to utilize the applied voltage to be maintained on the circuit node 14. In one form the circuit node 14 is a programming node of a FLASH memory. However, other applications of charge stored on a circuit node may be readily implemented. When circuit 10 is in a mode of operation wherein circuit node 14 is being charged to a predetermined voltage, such as -V, the control circuit 22 provides the up/down signal in a form that indicates that the voltage on circuit node 14 is to go down to the predetermined voltage. The voltage detector 16 is comparing the actual voltage at circuit node 14 with the -V that voltage detector 16 receives. When voltage detector 16 detects that the voltage on circuit node 14 is more than -V, voltage detector 16 provides an "on/off' signal to the enable input of the clock oscillator 18. The clock oscillator 18 provides a clock signal to the clock generator 20. The clock generator 20 uses the clock signal of the clock oscillator 18 and provides two clock signals, CLK1 and CLK2, in a phase relationship which is used as described below by the charge and discharge voltage generator 12 to enable the circuit node 14 to be charged by the charge source 21 to the beginning voltage (VDD). The charge source 21 (VDD) supplies charge from charge source 21 (VDD) to the charge and discharge voltage generator 12 to charge circuit node 14 to -V and selectively permits charge from circuit node 14 to be returned to charge source 21 through the charge and discharge voltage generator 12 when the circuit node 14 is being charged back to VDD. When circuit 10 is in a mode of operation required to discharge the circuit node 14 to a predetermined voltage such as (-V), control circuit 22 provides an encoded value of the up/down signal that indicates that the voltage on circuit node 14 is to go down. In response to the up/down signal, the voltage detector 16 provides an encoded value of the on/off signal that enables the clock oscillator 18. When voltage detector 16 determines that the circuit node 14 has achieved the target voltage (-V), it turns the clock oscillator 18 off which disables the charge and discharge voltage generator 12 by not providing the CLK1 and
[0012] Illustrated in FIG. 2 is an exemplary embodiment of the charge and discharge voltage generator 12 of FIG. 1 that is connected to the circuit node 14 and charge source 21. The charge source 21 is bidirectionally connected to a node 41. A diode-configurable P- channel transistor 42 has a source connected to the charge source 21 at node 41 , a gate, and a drain connected to a node 68. A diode-configurable P-channel transistor 43 has a source connected to node 68, a gate, and a drain connected to a node 83. A diode- configurable P-channel transistor 44 has a source connected to node 83, a gate, and a drain connected to the circuit node 14. A diode-configurable P-channel transistor 45 has a source connected to the charge source 21 at node 41 , a gate, and a drain connected to node 68. A diode-configurable P-channel transistor 46 has a source connected to node 68, a gate, and a drain connected to node 83. A diode-configurable P-channel transistor 47 has a source connected to node 83, a gate, and a drain connected to circuit node 14. The gates of diode- configurable transistors 42-47 are connected to a charge/discharge circuit 40. The charge/discharge circuit 40 has an N-channel transistor 50 having a drain connected to node 41 , a gate, and a source connected to the gate of transistor 42 at a node 85. A P-channel transistor 51 has a source connected to the gate of transistor 42 at node 85, a gate, and a drain connected to node 68. An N-channel transistor 52 has a drain connected to node 68, a gate, and a source connected to the gate of transistor 43 at a node 69. A P-channel transistor 53 has a source connected to the gate of transistor 43 and the source of transistor 52, a gate, and a drain connected to node 83. An N-channel transistor 54 has a drain connected to node 83, a gate, and a source connected to the gate of transistor 44 at a node 71. A P-channel transistor 55 has a source connected to the source of transistor 54 and to the gate of transistor 44. Transistor 55 has a gate. A drain of transistor 55 is connected to the circuit node 14. An N-channel transistor 56 has a drain connected to node 41 , a gate, and a source connected to the gate of transistor 45 at a node 63. A P-channel transistor 57 has a source connected to the gate of transistor 45 at node 63, a gate, and a drain connected to node 68. An N-channel transistor 58 has a drain connected to node 68, a gate, and a source connected to the gate of transistor 46 at a node 65. A P-channel transistor 59 has a source connected to the gate of transistor 46 and the source of transistor 58, a gate, and a drain connected to node 83. An N-channel transistor 60 has a drain connected to node 83, a gate, and a source connected to the gate of transistor 47 at a node 67. A P- channel transistor 61 has a source connected to the source of transistor 60 and to the gate of transistor 47. Transistor 61 has a gate. A drain of transistor 61 is connected to the circuit node 14. The gates of each of transistors 50-61 within the charge/discharge circuit 40 are connected together at a node 66. A first electrode of a capacitor 70 is connected to the first clock signal, CLK 1 , provided by the clock generator 20. A second electrode of capacitor 70 is connected to node 68. A first electrode of a capacitor 72 is connected to the second clock signal, CLK 2, provided by the clock generator 20. A second electrode of capacitor 72 is connected to node 83. A first electrode of a capacitor 74 is connected to the second clock signal CLK 2. A second electrode of capacitor 74 is connected to node 68. A first electrode of capacitor 76 is connected to the first clock signal, CLK 1. A second electrode of capacitor 76 is connected to node 83.
[0013] Connected between the charge source 21 and the circuit node 14 is a voltage level shifter circuit 78. The voltage level shifter circuit 78 has a P-channel transistor 80 having a source connected to node 41 , a gate, and a drain connected to node 66 of the charge/discharge circuit 40. An input of an inverter 82 is connected to receive the "Up/Down" signal provided by the control circuit 22 of FIG. 1. An output of inverter 82 is connected to the gate of transistor 80. A P-channel transistor 84 has a source connected to the source of transistor 80 at node 41 , a gate for receiving the "Up/Down" signal, and a drain. An N-channel transistor 86 has a drain connected to the drain of transistor 80, a gate connected to the drain of transistor 84 and the drain of transistor 88, and a source connected to the circuit node 14. An N-channel transistor 88 has a drain connected to the drain of transistor 84, a gate connected to the drain of transistor 80 and the drain of transistor 86, and a source connected to the circuit node 14.
[0014] In operation, the charge/discharge circuit 40 selectively connects each of diode- configurable transistors 42-47 as a diode-configured transistor in response to the voltage at node 66 which is provided by the voltage level-shifter circuit 78. Depending upon whether the voltage at node 66 is a logic high or a logic low value determines whether the gate of each of diode-configurable transistors 42-47 is connected to its source or to its drain. For example, when the voltage level-shifter circuit 78 provides a logic high value at node 66, transistor 50 is conductive and transistor 51 is nonconductive to connect the source and gate of diode configurable transistor 42 together. Each of the remaining transistors 43-47 is similarly configured. In this configuration, charge is permitted to move only from circuit node 14 to charge source 21 through diode configurable transistors 44, 43 and 42 and through diode configurable transistors 47, 46 and 45. Any charge movement from charge source 21 to circuit node 14 is therefore blocked by the diode action of the diode configurable transistors 42-47. Similarly, when the voltage level-shifter circuit 78 provides a logic low value at node 66, transistor 50 is nonconductive and transistor 51 is conductive to connect the drain and gate of diode configurable transistor 42 together. Each of the remaining diode configurable transistors 43-47 is similarly configured. In this configuration, charge is permitted to move only from the charge source 21 to the circuit node 14 through diode configurable transistors 42, 43 and 44 and through diode configurable transistor 45, 46 and 47. Any charge flow from the circuit node 14 to the charge source 21 is blocked by the diode action of the diode configurable transistors 42-47.
[0015] The logic value of the voltage at node 66 is determined by the voltage level- shifter 78 in response to the value of the Up/Down signal that is provided by control circuit 22 of FIG. 1. When the circuit node 14 is determined to need to be charged toward VDD, the effective logic value of the Up/Down signal is a logic low signal which makes transistor 80 nonconductive and transistor 84 conductive. When transistor 84 is conductive, the transistor 86 is conductive and transistor 88 is nonconductive. This biasing condition makes node 66 assume a logic low value which configures the diode-configurable transistors 42-47 to be able to only conduct current from the charge source 21 to the circuit node 14. The CIkI and Clk2 signals are complementary phase clock signals. As noted above, when circuit node 41 is to be discharged toward VDD, node 66 is low. During a clock phase when CIkI is a logic low and Clk2 is a logic high, the capacitors 70 and 76 are initialized with charge from the diode-configurable transistors 42 and 47, respectively. During this phase the charge from capacitor 72 and capacitor 74 respectively moves through the diode-configurable transistors
[0016] When the circuit node 14 is determined to need to be charged toward a negative voltage, the effective logic value of the Up/Down signal is a logic high signal which makes transistor 80 conductive and transistor 84 nonconductive. When transistor 84 is nonconductive, the transistor 86 is nonconductive and transistor 88 is conductive. This biasing condition makes node 66 assume a logic high value which configures the diode- configurable transistors 42-47 to be able to only conduct current from the circuit node 14 to the charge source 21. As the CLK1 and CLK2 clock signals cycle (i.e. oscillate), capacitors 70, 72, 74 and 76 charge and discharge in a similar fashion as described above wherein the charge on circuit node 41 moves through the charge and discharge voltage generator 12 toward VDDcausing the voltage on node 41 to decrease.
[0017] Illustrated in FIG. 3 is an exemplary graph of the circuit node 14 voltage plotted as a function of time as the operation of circuit 10 occurs. In general, the graph illustrates both a charge use portion and a charge reuse portion in which power is significantly saved. Assume that circuit node 14 is initially charged to the VDDvoltage potential from time to to time ti . The state of circuit node 14 is a quiescent state at this voltage potential. Within the system that uses circuit 10 a decision is made by circuitry (not shown) to discharge circuit node 14 to the voltage of (-V). As stated above, the (-V) voltage may be any predetermined voltage, either positive or negative or an isolated ground. Voltage node 14 is discharged to (-V) during the time interval from t1 to t2 during which charge transfer occurs with minimal power loss. The discharging occurs by returning charge from circuit node 14 to charge source 21. From time t2 to t3 the voltage (-V) at circuit node 14 is used by circuitry (not shown) in a use phase. From time t3 to t4 the circuit node 14 is returned to VDDin a charge return phase. At time t4 through time t5 the circuit node 14 is in a quiescent state. At time t5 the quiescent state ends and a charge transfer phase of circuit node 14 occurs by the charging of circuit node 14 to (-V) until time t6. During the time between t5 and t6 a substantial portion of the charge from the cycle embodied from t1 through t4 is reused. Between time t6 and time t7 a use phase occurs during which the (-V) voltage of circuit node 14 is used by circuitry (not shown). From time t7 to time t8 the charge from circuit node 14 is returned to the charge source 21 (VDD) with minimal power loss for reuse in future cycles. The circuit node 14 is thereby discharged to VDD. At time t8 the voltage of circuit node 14 is
[0018] For comparison with FIG. 3, illustrated in FIG. 4 is a graphical timeline of the charging and discharging of a circuit node to a boosted voltage as commonly implemented. Assume the circuit node is at a ground zero voltage from time to through t1. The circuit node is in a quiescent state. At time t1 the voltage of the circuit node is boosted during a charge phase to a potential of V600St until that voltage is reached at time t2. The V600St voltage is used during a use phase from time t2 until time t3. Between time t3 and time t4 the circuit node is discharged through a power consuming resistive circuit element. At time t4 the voltage of the circuit node returns to zero volts. The conventional charging and discharging of a circuit node is wasteful of power. The discharged charge is not reused.
[0019] Illustrated in FIG. 5 is a graph of another embodiment of the charging and discharging of a circuit node wherein a portion of the discharged potential is reused. In this form assume that between time to and t1 the circuit node is at zero volts potential and is in a quiescent state. Between time t1 and time t2 a charge phase occurs. The voltage of the circuit node is charged from zero volts to a predetermined voltage potential of VBθost- The boosted voltage on the circuit node is used in a charge use phase between time t2 and time t3. Between time t3 and time t4 a partial discharge of the circuit node to an intermediate voltage, Vmtermediate, is made wherein the charge representing the voltage differential between V60OSt and Vintermediate is transferred to another circuit node for reuse by circuit 108. The time period from time t4 to time t5 is a charge reuse phase wherein the charge transferred to support the Vmtermediate voltage is reused. After the charge transfer from VBθost to Vmtermediate, a discharge phase is completed between time t5 and time t6 wherein the circuit node VBoOst is discharged to ground or zero volts.
[0020] Illustrated in FIG. 6 is a first embodiment of a voltage circuit for implementing the voltage functionality represented in FIG. 5. A voltage circuit 100 is provided for discharging a node and reusing the charge by discharging in two phases. A charge pump 102 has an output terminal for providing a boosted voltage, VBoost, which is elevated above a predetermined voltage such as a supply voltage. The output of the charge pump 102 is connected to a circuit node 104. A three-terminal switch 106 is connected to the circuit node 104. A first terminal of switch 106 is connected to a circuit 108 and transfers an amount of charge from the circuit node 104 to a node within circuit 108. A second terminal of switch 106 is not connected. A third terminal of switch 106 is connected to a ground reference voltage terminal or other voltage terminal which represents a voltage potential to which it is desired to discharge the circuit node 104. When switch 106 is connected to the second terminal the circuit node 104 is not connected to either circuit 108 or to the ground reference voltage terminal.
[0021] In operation, voltage circuit 100 uses the charge pump 102 to charge the circuit node 104 to the boosted voltage, VBoOst- During the charging of circuit node 104 the switch 106 is connected to the second position which is electrically floating in potential. The circuit node 104 may, for example, be a node of a memory circuit which is at a high voltage for programming a memory cell. At some point in time the circuit node 104 must be discharged. Rather than discharging the circuit node 104 to ground and losing the stored power, a portion of the charge associated with the potential difference VBoOst- V|ntΘrmΘdιatΘas described in FIG. 5 is coupled to the circuit 108 by switching the switch 106 to the first position. The portion of the charge is thereby available for reuse by circuit 108. The circuit 108 is implemented as one of any of numerous types of circuits. For example, circuit 108 may be a logic circuit which has a static node for storing the V|ntΘrmΘdιatΘvoltage. After a charge associated with the VBθost- Vmtermediate voltage has been transferred from the circuit node 104 to the circuit 108, the remaining charge on circuit node 104 is discharged by switching the switch 106 to the third switch position. The third switch position of switch 106 connects the circuit node 104 to a ground potential which completes the discharge of the circuit node 104. The voltage circuit 100 has thus reused a significant portion of the charge which has been placed onto circuit node 104. It should be understood that charge pump 102 may be implemented using any of a variety of known charge pump circuit configurations.
[0022] By now it should be appreciated that there has been provided a voltage circuit for charging a circuit node and discharging at least a portion of the charge for subsequent reuse to thereby save power. In one form a charge pump is used which is power efficient as the charge pump transfers charge rather than discharging the charge to ground through a resistive circuit element. In one form the reused charge is transferred back into a charge source, such as a power supply. In that form substantially all of the reused charge is transferred back to the charge source. In another form the reused charge is transferred to another circuit node of a separate circuit. In that form less than all of the original charge is reused by the separate circuit. In one form a charge pump is used to transfer charge to a circuit node and again transfer the charge for subsequent reuse. The polarity of the charge pump is bidirectional and may be reversed by using transistor switches to reconfigure series- connected transistors as diodes which conduct current in only one direction. Depending upon the direction of charge flow, the charge/ discharge circuit 40 determines what diode configuration the series-connected transistors will assume. Capacitors within the charge pump are clocked by two complementary phase clock signals to efficiently move charge through the charge pump without incurring any significant power loss. Thus the voltage circuits described herein are very power efficient.
[0024] In another form there is provided a voltage circuit having a circuit node and a charge source for providing charge to be stored onto the circuit node. A voltage generator is coupled between the circuit node and the charge source. The voltage generator conducts current in a first direction to charge a first predetermined voltage onto the circuit node for use in a first predetermined function during a first time period. The voltage generator removes a portion of the charge from the circuit node by conducting current in a second direction opposite the first direction and couples the portion to the charge source for reuse by the charge source during a second time period subsequent to the first time period with minimal power loss from not discharging the portion of the charge to ground. In one form a control circuit is coupled to the voltage generator for providing a control signal indicating whether the circuit node should be charged or discharged. A voltage detector is coupled to the circuit node and the control circuit for comparing voltage at the circuit node with either the first predetermined voltage or a second predetermined voltage in response to the control signal, the voltage detector providing a clock enable signal. Clock circuitry is coupled to the voltage generator and the voltage detector for providing one or more clock signals in response to the clock enable signal. The one or more clock signals transfer charge through the voltage generator between the charge source and the circuit node. In another form the voltage generator switches diode-configurable transistors in response to the control signal to enable current to flow in only one direction through the voltage generator. In another form the voltage generator has a plurality of series-coupled transistors coupled between the charge source and the circuit node, each having a source, a drain and a control electrode. A charge/discharge switch is coupled to the control electrode of each of the plurality of series- coupled transistors. The charge/discharge switch selectively connects the control electrode to a corresponding drain or a corresponding source of each of the plurality of series-coupled transistors in response to the control signal. In another form the voltage generator has a voltage level shifting circuit coupled to the circuit node. The voltage level shifting circuit has an input for receiving the control signal and has an output coupled to the charge/discharge circuit for configuring the charge/discharge circuit to either charge the circuit node or discharge the circuit node. In one form the charge/discharge circuit has a plurality of pairs of complementary conductivity transistors, each pair being coupled in series and coupled to a source and a drain of a respective one of the plurality of series-coupled transistors and to a control electrode thereof at a common connection between the each pair, wherein only one transistor of each pair is conductive to place the respective one of the plurality of series- coupled transistors in a diode configuration. In another form a control circuit is coupled to the voltage generator for providing a control signal indicating whether the circuit node should be charged or discharged. A voltage detector is coupled to the circuit node and the control circuit for comparing voltage at the circuit node with either the first predetermined voltage or a second predetermined voltage in response to the control signal. The voltage detector provides a clock enable signal. A clock oscillator has an input coupled to the voltage detector for receiving the clock enable signal and has an output for providing an oscillating clock in response to the clock enable signal. A clock generator has an input coupled to the output of the clock oscillator, a first output coupled to the voltage generator for providing a first clock signal, and a second output coupled to the voltage detector for providing a second clock signal. The first clock signal and the second clock signal transfer charge through the voltage generator between the charge source and the circuit node. In another form the voltage generator has a plurality of series-coupled transistors coupled between the charge source and the circuit node, each having a source, a drain and a control electrode. A charge/discharge circuit is coupled to the control electrode of each of the plurality of series- coupled transistors. The charge/discharge circuit selectively connects each control electrode of the series-coupled transistors to a corresponding drain or a corresponding source in response to the control signal to determine a current flow direction through the voltage generator.
[0026] Although the invention has been described with respect to specific conductivity types or polarity of potentials, skilled artisans appreciated that conductivity types and polarities of potentials may be reversed. Moreover, terms such as "front," "back," "top," "bottom," "over," "under" and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
[0027] Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, the circuit node for storing charge may be implemented in various types of transistor memory storage cell circuits and various types of memory, such as Flash, DRAM, SRAM and MRAM (magnetoresistive random access memory). Various logic circuits or logic gates that implement digital logic functions may be implemented to perform the described functionality of circuit 108 and circuit 1 16. Switch 106 and switch 1 13 may be implemented with any of a variety of differing switch circuits including, but not limited to, any type of switch using transistors. In the voltage circuit 109 all or some of the illustrated charge pumps may be implemented with the same charge pump circuitry which is time shared. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
[0028] The terms "a" or "an," as used herein, are defined as one or more than one. Also, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an." The same holds true for the use of definite articles.
[0029] Unless stated otherwise, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

中文:
[0001]本公开内容一般地涉及半导体,并且更特别地涉及用于半导体中的电压电路。
[0002]集成电路典型地使用电荷泵电路将电源电压提升到大于实际电源电压值的值。电荷泵有利于产生升压电源,因为它们可以在集成电路中实现。已经描述了用于实现这种功能的许多不同类型的电荷泵电路。在存储器电路中,例如闪速存储器(FLASH memory),电路节点被充电至升高的电压。该电路节点随后被放电。为了使电路节点放电,将晶体管或电流源连接至该电路节点以使该电路节点耦接至地电压电位。电荷运动引起电流以使升压电位通过晶体管或电流源放电。电流被排入地端子,并且全部电荷作为耗散功率而丢失。当集成电路包括高电容节点时,所引起的功率损耗是相当大的。
[0003]本发明通过举例的方式来说明并且不受附图所限制,在附图中类似的参考符号指示相似的元件。附图中的元件处于简单和清晰起见而示出,而并不一定按比例绘制。
[0005]图2以示意图的形式示出了图1的电路所使用的充电和放电电压发生器的一种实施例;
[0006]图3以时序图的形式示出了电路节点在电荷使用和电荷重用操作期间的示例性电压变化;
[0007]图4以时序图的形式示出了电路节点在充电和放电操作期间的已知的电压变化;
[0008]图5以时序图的形式示出了电路节点在部分放电和后续放电阶段期间的示例性电压变化;以及
[0009]图6以框图的形式示出了用于在两个不同的放电阶段内对电路节点放电的电压电路的第一实施例。
[0010]图1所示的是用于以功率高效的方式对电路节点充电和放电的电路10。电路10通过存储存在于电路节点14上的一部分电荷而重用电路节点14的电荷来实现电路节点14的充电和放电。时钟振荡器18具有用于接收“开/关”信号的使能输入。时钟振荡器18具有与时钟发生器20的输入连接的输出。时钟振荡器18和时钟发生器20可以被共同看作时钟电路并且实现于单个电路部分内或者作为如图所示那样的独立电路。时钟发生器20的第一输出给充电和放电电压发生器12的第一输入提供记为“Clk1”的第一时钟信号,并且时钟发生器20的第二输出给充电和放电电压发生器12的第二输入提供记为“Clk2”的第二时钟信号。充电和放电电压发生器12起着电荷泵电路的作用。充电和放电电压发生器12的输入/输出端与电荷源21的输入/输出端连接。在一种形式中,电荷源提供了记为VDD的电源电压。充电和放电电压发生器12的输出与电路节点14连接。电路节点14是在集成电路内的或者在电路系统内的预定的节点,例如,印制电路板或卡的节点。电压检测器16的第一输入与电路节点14连接。电压检测器16的第二输入接收第一电压,例如电源电压VDD。电压检测器16的第三输入接收第二电压,例如(-V),该第二电压是以VDD为基准的负电压。电压检测器16的输出提供了“开/关”信号并且与时钟振荡器18的使能输入连接。控制电路22具有用于提供“上/下(Up/Down)”信号的输出。控制电路22的输出与充电和放电电压发生器12的第三输入以及电压检测器16的第四输入连接。
[0011]在操作中,当充电和放电电压发生器12分别对电路节点14充电到预定的电压以及使电路节点14自该预定电压起放电,使电荷返回电荷源21时,电荷源21双向地从充电和放电电压发生器12源出(source)电荷以及汇入(sink)电荷。如同在此所使用的,术语“充电”应理解为意指在电路节点或存储器件上设置所期望的电压(正的或负的)。术语“放电”应理解为意指移除电路节点或存储器件上的期望电压(正的或负的)。与电路节点14耦接的电压检测器16监控在电路节点14处的电压电位。没有示出的电路确定电路节点14应当何时充电或放电。此外,没有示出的电路与电路节点14连接以使用将要维持于电路节点14上的施加电压。在一种形式中,电路节点14是闪速存储器的编程节点。但是,存储于电路节点上的电荷的其他应用可以轻易地实现。当电路10处于其中电路节点14正被充电至预定的电压(例如,-V)的操作模式时,控制电路22提供以指示电路节点14上的电压将下降到预定电压的形式的上/下信号。电压检测器16将电路节点14处的实际电压与电压检测器16所收到的-V进行比较。当电压检测器16检测到在电路节点14处的电压大于-V时,电压检测器16提供“开/关”信号给时钟振荡器18的使能输入。时钟振荡器18提供时钟信号给时钟发生器20。时钟发生器20使用时钟振荡器18的时钟信号并且提供有某相位关系的两种时钟信号,CLK1和CLK2,它们由充电和放电电压发生器12如同以下所描述的那样使用以使电路节点14能够由电荷源21充电至起始电压(VDD)。电荷源21(VDD)将来自电荷源21(VDD)的电荷供应给充电和放电电压发生器12以将电路节点14充电至-V,并且在电路节点14正被充电回到VDD时选择性地允许来自电路节点14的电荷通过充电和放电电压发生器12返回电荷源21。当电路10处于需要将电路节点14放电至预定电压(例如,(-V))的操作模式中时,控制电路22提供指示在电路节点14上的电压将下降的上/下信号的编码值。响应于该上/下信号,电压检测器16提供启用(enable)时钟振荡器18的开/关信号的编码值。当电压检测器16确定电路节点14已经达到目标电压(-V)时,它关闭时钟振荡器18,该时钟振荡器18通过不提供CLK1和CLK2信号来禁用(disable)充电和放电电压发生器12。缺少CLK1和CLK2信号的生成具有对电路节点14既不充电也不放电的效果。当充电电路节点14使其回到起始电压(VDD)时,电路10以相似的方式来操作,但是使上/下信号被编码以指示在节点14上的电压将上升,并且电压检测器16提供启用时钟振荡器18的开/关信号。当节点14的电压达到起始电压(VDD)时,电压检测器16对开/关信号进行编码以禁用时钟振荡器18。充电和放电电压发生器12关于如何重用电路节点14上的电荷以节省功率的操作可以结合图2来进一步理解。
[0012]在图2中示出的是与电路节点14及电荷源21连接的图1的充电和放电电压发生器12的一种示例性实施例。电荷源21与节点41双向连接。可配置二极管型(diode-configurable)P沟道晶体管42具有与电荷源21连接于节点41的源极、栅极以及与节点68连接的漏极。可配置二极管型P沟道晶体管43具有与节点68连接的源极、栅极以及与节点83连接的漏极。可配置二极管型P沟道晶体管44具有与节点83连接的源极、栅极以及与电路节点14连接的漏极。可配置二极管型P沟道晶体管45具有与电荷源21连接于节点41的源极、栅极以及与节点68连接的漏极。可配置二极管型P沟道晶体管46具有与节点68连接的源极、栅极以及与节点83连接的漏极。可配置二极管型P沟道晶体管47具有与节点83连接的源极、栅极以及与电路节点14连接的漏极。可配置二极管型晶体管42-47的栅极与充电/放电电路40连接。充电/放电电路40具有N沟道晶体管50,该N沟道晶体管50具有与节点41连接的漏极、栅极以及与晶体管42的栅极连接于节点85的源极。P沟道晶体管51具有与晶体管42的栅极连接于节点85的源极、栅极以及与节点68连接的漏极。N沟道晶体管52具有与节点68连接的漏极、栅极以及与晶体管43的栅极连接于节点69的源极。P沟道晶体管53具有与晶体管43的栅极和晶体管52的源极连接的源极、栅极以及与节点83连接的漏极。N沟道晶体管54具有与节点83连接的漏极、栅极以及与晶体管44的栅极连接于节点71的源极。P沟道晶体管55具有与晶体管54的源极和晶体管44的栅极连接的源极。晶体管55具有栅极。晶体管55的漏极与电路节点14连接。N沟道晶体管56具有与节点41连接的漏极、栅极以及与晶体管45的栅极连接于节点63的源极。P沟道晶体管57具有与晶体管45的栅极连接于节点63的源极、栅极以及与节点68连接的漏极。N沟道晶体管58具有与节点68连接的漏极、栅极以及与晶体管46的栅极连接于节点65的源极。P沟道晶体管59具有与晶体管46的栅极和晶体管58的源极连接的源极、栅极以及与节点83连接的漏极。N沟道晶体管60具有与节点83连接的漏极、栅极以及与晶体管47的栅极连接于节点67的源极。P沟道晶体管61具有与晶体管60的源极和晶体管47的栅极连接的源极。晶体管61具有栅极。晶体管61的漏极与电路节点14连接。在充电/放电电路40之内的晶体管50-61各自的栅极共同连接于节点66。电容器70的第一电极与由时钟发生器20提供的第一时钟信号CLK1连接。电容器70的第二电极与节点68连接。电容器72的第一电极与由时钟发生器20提供的第二时钟信号CLK2连接。电容器72的第二电极与节点83连接。电容器74的第一电极与第二时钟信号CLK2连接。电容器74的第二电极与节点68连接。电容器76的第一电极与第一时钟信号CLK1连接。电容器76的第二电极与节点83连接。
[0013]连接于电荷源21与电路节点14之间的是电压电平移位电路78。电压电平移位电路78具有P沟道晶体管80,该P沟道晶体管80具有与节点41连接的源极、栅极以及与充电/放电电路40的节点66连接的漏极。反相器82的输入被连接用于接收由图1的控制电路22提供的“上/下”信号。反相器82的输出与晶体管80的栅极连接。P沟道晶体管84具有与晶体管80的源极连接于节点41的源极、用于接收“上/下”信号的栅极,以及漏极。N沟道晶体管86具有与晶体管80的漏极连接的漏极、与晶体管84的漏极和晶体管88的漏极连接的栅极,以及与电路节点14连接的源极。N沟道晶体管88具有与晶体管84的漏极连接的漏极、与晶体管80的漏极和晶体管86的漏极连接的栅极,以及与电路节点14连接的源极。
[0014]在操作中,充电/放电电路40响应于由电压电平移位电路78提供的在节点66处的电压而选择性地将每个可配置二极管型晶体管42-47连接为二极管配置型的晶体管。根据在节点66出的电压为究竟是逻辑高值还是逻辑低值来确定可配置二极管型晶体管42-47各自的栅极究竟是连接到其源极还是其漏极。例如,当电压电平移位电路78在节点66处提供逻辑高值时,晶体管50是导通的并且晶体管51是非导通的,以将可配置二极管型晶体管42的源极和栅极连接在一起。剩余的各个晶体管43-47类似地配置。在这种结构中,仅允许电荷通过可配置二极管型晶体管44、43和42以及通过可配置二极管型晶体管47、46和45从电路节点14移动到电荷源21。因此,从电荷源21到电路节点14的任何电荷运动均由可配置二极管型晶体管42-47的二极管作用所阻挡。类似地,当电压电平移位寄存器78在节点66提供逻辑低值时,晶体管50是非导通的并且晶体管51是导通的,以将可配置二极管型晶体管42的漏极和栅极连接在一起。剩余的各个可配置二极管型晶体管43-47类似地配置。在这种结构中,仅允许电荷通过可配置二极管型晶体管42、43和44以及通过可配置二极管型晶体管45、46和47从电荷源21移动到电路节点14。从电路节点14到电荷源21的任何电荷流动均由可配置二极管型晶体管42-47的二极管作用所阻挡。
[0015]在节点66处的电压的逻辑值由电压电平移位器78响应于由图1的控制电路22提供的上/下信号的值来确定。当确定电路节点14需要朝VDD方向充电时,上/下信号的有效逻辑值是使晶体管80导通并且晶体管84不导通的逻辑低信号。当晶体管84导通时,晶体管86导通并且晶体管88不导通。该偏压状态使得节点66呈现出逻辑低值,该逻辑低值配置可配置二极管型晶体管42-47使其仅能够传导从电荷源21到电路节点14的电流。Clk1和Clk2信号是相位互补的时钟信号。如以上所指出的,当电路节点41将要放电至VDD时,节点66为低。在Clk1为逻辑低并且Clk2为逻辑高的时钟相位期间,电容器70和76分别以来自可配置二极管型晶体管42和47的电荷来初始化。在该相位期间,来自电容器72和74的电荷分别朝电路节点41的方向运动通过可配置二极管型晶体管43和45。随着时钟信号改变相位,电容器72和74分别通过可配置二极管型晶体管44和46来充电,并且电容器70和76分别通过可配置二极管型及鞥通过42和46来放电。随着时钟继续循环,在电路节点41上的电荷沿VDD的方向运动通过可配置二极管型晶体管42-47。
[0016]当确定电路节点14需要朝负电压方向充电时,上/下信号的有效逻辑值是使晶体管80导通并且晶体管84不导通的逻辑高信号。当晶体管84不导通时,晶体管86不导通并且晶体管88导通。该偏压状态使得节点66呈现出逻辑高值,该逻辑高值配置可配置二极管型晶体管42-47使其仅能够传导从电路节点14到电荷源21的电流。随着Clk1和Clk2时钟信号的循环(即,振荡),电容器72、72、74和76如上所述以相似的方式来充电和放电,其中在电路节点41上的电荷朝VDD的方向运动通过充电和放电电压发生器12,促使在节点41上的电压降低。
[0017]在图3中示出的是在电路10操作发生时标绘为时间的函数的电路节点14的电压的示例性图表。一般而言,图表示出了电荷使用部分以及其中显著地节省了功耗的电荷重用部分两者。假定电路节点14在开始时从时间t0到时间t1被充电至VDD电压电位。电路节点14的状态在该电压电位为静止状态。在使用电路10的系统之内,由电路(没有示出)作出将电路节点14放电至(-V)电压的决定。如上所述,(-V)电压可以是任何预定的电压(正的或负的)或者隔离接地(isolated ground)。电压节点14在从t1到t2的时间间隔内被放电至(-V),在该时间间隔期间电荷转移在最小功率损耗的情况下发生。放电通过将电荷从电压节点14返回电荷源21而发生。从时间t2到t3,在电路节点14处的电压在使用阶段由电路(没有示出)使用。从时间t3到t4,电路节点14在电荷返回阶段返回至VDD。在时间t4到时间t5,电路节点14处于静止状态。在时间t5,静止状态结束并且电路节点14的电荷转移阶段在将电路节点14充电至(-V)期间发生直到时间t6。在t5和t6时间内,来自包含从t1到t4的循环的大部分电荷被重用。在时间t6和时间t7之间,出现使用阶段,在其间电路节点14的(-V)电压由电路(没有示出)使用。从时间t7到时间t8,来自电路节点14的电荷以最小的功率损耗返回至21(VDD),以便在将来的循环中重用。电路节点14由此被放电至VDD。在时间t8,电路节点14的电压是VDD,并且电路10的静止状态重新开始。充电和放电电压发生器12能够以不同于图2所示的形式来实现。例如,在某些应用中可能所希望的是在没有二极管电压降(例如,存在于每个晶体管42-47两端的电压降)的无效率的情况下运行的充电和放电发生器。在这种可另选的实现方式中能够使用需要更多定时钟(clocking)电路。但是,另加的定时钟电路使用更多的电路面积,因此在另加面积的使用相对功率使用之间存在着设计权衡。在图2所示的实施例中,在本文所描述的重用电荷的电路操作中实现了显著的功耗节省,即使存在着与二极管电压降有关的某些功率损耗。
[0018]与图3相比,在图4中示出的是电路节点充电和放电到通常所实现的升高电压的图形时间线。假定电路节点从时间t0到t1处于接地零电压。电路节点处于静止状态。在时间t1,电路节点的电压在充电阶段期间被升压至VBoost电位,直到在时间t2达到该电压。VBoost电压在从时间t2直到时间t3的使用阶段内被使用。在时间t3与时间t4之间,电路节点通过功率消耗电阻电路元件来放电。在时间t4,电路节点的电压返回至零电压。电路节点常规的充电和放电是浪费功率的。所释放的电荷没有被重用。
[0019]在图5中示出的是其中一部分放电电位被重用的电路节点的充电和放电的另一种实施例的图表。在这种形式中,假定在时间t0和t1之间,电路节点处于零伏特电位并且处于静止状态。在时间t1与时间t2之间,充电阶段出现。电路节点的电压从零伏特充电至预定的电压电位VBoost。在电路节点上的升高电压在时间t2与时间t3之间的电荷使用阶段内被使用。在时间t3与时间t4之间,进行电路节点的部分放电至中间电压VIntermediate,其中代表VBoost和VIntermediate之间的电压差的电荷被转移至另一个电路节点,以由电路108重用。从时间t4到时间t5的时间段是电荷重用阶段,其中为支持VIntermediate电压而转移的电荷被重用。在从VBoost到VIntermediate的电荷转移之后,在时间t5和时间t6之间完成放电阶段,其中电路节点VBoost被放电至地电位或零伏特。
[0020]在图6中示出的是用于实现图5所表示的电压功能的电压电路的第一实施例。电压电路100被提供用于使节点放电并且在两个阶段内通过放电重用电荷。电荷泵102具有用于提供升高电压VBoost的输出端,该升高电压VBoost被升高至诸如电源电压的预定电压以上。电荷泵102的输出与电路节点104连接。三端开关106与电路节点104连接。开关106的第一端与电路108连接并将一定量的电荷从电路节点104转移至在电路108之内的节点。开关106的第二端不连接。开关106的第三端与地参考电压端子或者代表电路节点104所希望放电到的电压电位的其他电压端子连接。当开关106与第二端连接时,电路节点104既没有与电路108连接也没有与地参考电压端子连接。
[0021]在操作中,电压电路100使用电荷泵102来将电路节点104充电至升高电压VBoost。在电路节点104的充电期间,开关106与电位电浮置(electrically float)的第二位置连接。例如,电路节点104可以是处于用于对存储单元编程的高电压的存储电路的节点。在某一时间点,电路节点104必须被放电。不是将电路节点104放电至地电位并且损失所存储的功率,而是通过将开关106切换至第一位置来使与结合图5所描述的电位差VBoost-VIntermediate相关的一部分电荷耦合至电路108。这部分电荷由此可由电路108来使用。电路108被实现为众多类型的电路中的任一种。例如,电路108可以是具有用于存储VIntermediate电压的静态节点的逻辑电路。在与VBoost-VIntermediate电压相关的电荷已经从电路节点104转移到电路108之后,在电路节点104上的剩余电荷通过将开关106切换至第三开关位置来释放。开关106的第三开关位置将电路节点104连接至使电路节点104完成放电的地电位。因而,电压电路100重用了已经布置于电路节点104之上的大部分电荷。应当理解,电荷泵102可以使用各种已知的电荷泵电路结构中的任一种来实现。
[0022]应当意识到,至此已经提供了用于对电路节点充电以及释放至少一部分电荷用于后续的重用以由此节省功耗的电压电路。在一种形式中,使用了功率高效的电荷泵,因为该电荷泵转移电荷而不是通过电阻电路元件将电荷释放到地线。在一种形式中,所重用的电荷被转移回到电荷源,例如电源。在该形式中,基本上全部所重用的电荷都转移回到电荷源。在另一种形式中,所重用的电荷被转移到分离电路的另一电路节点。在该形式中,少于全部(less than all)的原始电荷由分离电路所重用。在一种形式中,电荷泵被用来将电荷转移至电路节点并再次转移该电荷用于后续的重用。电荷泵的极性是双向的并且可以通过使用晶体管开关来将串联连接的晶体管重配置为仅沿一个方向来传导电流的二极管而反转。根据电荷流动的方向,充电/放电电路40确定串联连接的晶体管将擦用什么样的二极管结构。在电荷泵之内的电容器由两种相位互补的时钟信号来定时钟,以有效地通过电荷泵来移动电荷,没有招致任何重大的功率损耗。因而,在此所描述的电压电路是功率很高效的。
[0024]在另一种形式中,本发明提供了具有电路节点以及用于提供待存储于电路节点上的电荷的电荷源的电压电路。电压发生器被耦接于电路节点与电荷源之间。电压发生器沿第一方向传导电流以将第一预定电压充电于电路节点之上,以在第一时间段期间用于第一预定功能中。电压发生器通过沿与第一方向相反的第二方向传导电流来将一部分电荷从电路节点中移除,并且将该部分电荷耦合至电荷源以由电荷源在第一时间段之后的第二时间段期间重用,而不是将这部分电荷释放到地线,以达最小的功率损耗。在一种形式中,控制电路与电压发生器耦接,用于提供指示电路节点应当充电还是放电的控制信号。电压检测器与电路节点和控制电路耦接,以便响应于该控制信号而将电路节点处的电压与第一预定电压或第二预定电压进行比较,该电压检测器提供时钟使能信号。时钟电路与电压发生器和电压检测器耦接,以响应于时钟使能信号而提供一个或多个时钟信号。该一个或多个时钟信号使电荷通过电压发生器在电荷源与电路节点之间转移。在另一种形式中,电压发生器响应于控制信号而开关可配置二极管型晶体管,以使电流仅沿一个方向流过电压发生器。在另一种形式中,电压发生器具有耦接于电荷源与电路节点之间的多个串联耦接的晶体管,每个晶体管具有源极、漏极和控制电极。充电/放电开关与该多个串联耦接的晶体管各自的控制电极耦接。充电/放电开关响应于控制信号选择性地将控制电极连接至该多个串联耦接的晶体管各自的对应漏极或对应漏极。在另一种形式中,电压发生器具有与电路节点耦接的电压电平移位电路。电压电平移位电路具有用于接收控制信号的输入,并且具有与充电/放电开关耦接的输出,用于配置该充电/放电开关以对电路节点充电或者使电路节点放电。在一种形式中,充电/放电电路具有多对互补导电性的晶体管,每对晶体管串联耦接并且与该多个串联耦接的晶体管中相应的一个晶体管的源极和漏极耦接以及与其控制电极耦接于每对晶体管之间的公共连接处,其中每对晶体管中只有一个晶体管导通以使该多个串联耦接的晶体管中对应的一个晶体管置为二极管结构。在另一种形式中,控制电路与电压发生器耦接,用于提供指示电路节点究竟应当充电还是放电的控制信号。电压检测器与电路节点和控制电路耦接,以响应于控制信号而将电路节点处的电压与第一预定电压或第二预定电压进行比较。电压检测器提供时钟使能信号。时钟振荡器具有与电压检测器耦接的用于接收时钟使能信号的输入,以及具有用于响应于时钟使能信号而提供振荡时钟的输出。时钟发生器具有与时钟振荡器的输出耦接的输入,与电压发生器耦接的用于提供第一时钟信号的第一输出,以及与电压检测器耦接的用于提供第二时钟信号的第二输出。第一时钟信号和第二时钟信号使电荷通过电压发生器在电荷源与电路节点之间转移。在另一种形式中,电压发生器具有耦接于电荷源与电路节点之间的多个串联耦接的晶体管,每个晶体管具有源极、漏极和控制电极。充电/放电电路与该多个串联耦接的晶体管各自的控制电极耦接。充电/放电电路响应于控制信号而选择性地将该多个串联耦接的晶体管的每个控制电极连接至对应的漏极或对应的源极,用于确定通过电压发生器的电流流向。
[0026]虽然本发明针对具体导电类型或电位极性来描述,但是本领域技术人员应当意识到,导电类型和电位极性可以反转。而且,在说明书和权利要求书中的诸如“前面”、“后面”、“顶部”、“底部”、“上方”、“下方”之类的词语,如果有,仅出于说明性的目的而使用,而并不一定用于描述永久的相对位置。应当理解,这样使用的词语在适当的情况下是可互换的,使得在此所描述的本发明的实施例,例如,能够以与在此所示出的或另外描述的那些取向不同的取向来操作。
[0027]虽然本发明在此针对具体的实施例来描述,但是在不脱离权利要求书所阐明的本发明的范围的情况下能够进行各种修改和变更。例如,用于存储电荷的电路节点可以用不同类型的晶体管存储器存储单元电路以及各种类型的存储器,例如闪存(Flash)、DRAM、SRAM和MRAM(磁阻随机存取存储器)来实现。实现数字逻辑功能的各种逻辑电路或逻辑门可以被实现以执行电路108和电路116的所述功能。开关106和开关113可以用各种不同的开关电路(包括但不限于任何类型的使用晶体管的开关)来实现。在电压电路109中,所示出的电荷泵中的全部或某些可以用相同的分时的电荷泵电路来实现。因此,本说明书和附图应当看作是说明性的,而不是限制性的,并且所有此类修改意欲包含于本发明的范围之内。在此针对具体实施例所描述的任何好处、优点或问题的解决方案不应看作是任一或全部权利要求的关键的、必要的或必不可少的特征或元素。
[0028]在此所使用的词语“一(a)”或“一个(an)”被限定为一个或多个。此外,在权利要求书中的诸如“至少一个”和“一个或多个”之类的引入性短语不应视为暗示另一要求权利的元素由不定冠词“一(a)”或“一个(an)”的引入将含有该引入的要求权利的元素的任何特定权利要求限制于仅含有一个这样的元素的发明,即使在同一权利要求包括引入性短语“一个或多个”或“至少一个”以及诸如“一(a)”或“一个(an)”的不定冠词时。这对于定冠词的使用同样如此。
[0029]除非另外说明,否则诸如“第一”和“第二”之类的词语用来任意区分此类词语所描述的元素。因而,这些词语并不一定旨在指示此类元素的时间先后或其他优先次序。