English:
[0001] Static random access memory (SRAM) utilizes latching to store each bit. Because SRAM is static, periodic refreshing of the memory is unnecessary, and therefore SRAM is typically faster, less dense and more expensive than dynamic random-access memory (DRAM). Due to SRAM's speed, SRAM is typically used in computer applications that require a fast memory, such as cache memory for the central processing unit (CPU), external burst mode SRAM caches, hard disk buffers, router buffers and CPU register files. Although SRAM is fast, it also consumes a significant portion of system's level dynamic power. In some cases, SRAM may consume as much as 90% of the system level dynamic power.
[0002] In described examples of systems and methods for reducing power consumption and increasing speed in static random access memory (SRAM), the SRAM includes an array of storage cells and a first sense amplifier. The array of storage cells is arranged as rows and columns. The rows correspond to word lines, and the columns correspond to bit lines. The first sense amplifier includes a first transistor and a second transistor. The first sense amplifier is configured to provide a first read of a first storage cell of the array of storage cells. Based on the first read of the first storage cell failing to correctly read data stored in the first storage cell, the first sense amplifier is configured to increment a body bias of the first transistor a first time. In response to the body bias of the first transistor being incremented, the first sense amplifier is configured to provide a second read of the first storage cell.
[0003] In an example method for reducing power consumption and increasing speed in SRAM, the method includes writing known data into a plurality of storage cells of an array of storage cells arranged as rows and columns; reading a first storage cell of the plurality of storage cells a first time; based on the reading the first storage cell the first time failing to correctly read the known data from the first storage cell, incrementing a body bias of a first transistor of a first sense amplifier of the SRAM; and in response to the body bias of the first transistor being incremented, reading the first storage cell a second time.
[0004] An example SRAM sense amplifier includes a first transistor and a second transistor. The second transistor is cross coupled with the first transistor. The first transistor is configured to receive a body bias, such that a voltage threshold of the first transistor is approximately equal to a voltage threshold of the second transistor.
[0006] FIG. 2 shows a block diagram of a static random access memory (SRAM) in accordance with various embodiments.
[0007] FIG. 3 shows a block diagram of storage cell array in accordance with various embodiments.
[0008] FIG. 4 shows a circuit diagram of a sense amplifier in accordance with various embodiments.
[0009] FIG. 5 shows a flow diagram of a method for reducing power consumption and increasing speed in SRAM in accordance with various embodiments.
[0010] The term "couple" or "couples" means either an indirect or direct connection. For example, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections. The recitation "based on" means "based at least in part on." For example, if X is based on Y, then X may be based on Y and any number of other factors.
[0011] Static random access memory (SRAM) is memory that utilizes latching to store each bit. Because SRAM is static, periodic refreshing of the memory is unnecessary, and therefore SRAM is typically faster, less dense and more expensive than dynamic random-access memory (DRAM). Due to SRAM's speed, SRAM is typically used in computer applications that require a fast memory, such as cache memory for the central processing unit (CPU), external burst mode SRAM caches, hard disk buffers, router buffers and CPU register files. Therefore, SRAM is a fundamental building block of many systems. While SRAM is fast, it also consumes a significant portion of system's level dynamic power. In some cases SRAM may consume as much as 90% of the system level dynamic power. Therefore, it is desirable to reduce the power consumption of SRAM while increasing speed.
[0012] Whenever a storage cell in a storage cell array of a memory is to be read, a precharge of the bit lines is initiated. After the bit lines are precharged in the conventional SRAM, the word line corresponding to the row in which the storage cell to be read is activated. This creates a differential voltage in a differential pair of bit lines corresponding to the columns containing the storage cell being read. A sense amplifier to then may be utilized to read the contents of the storage cell by sensing the differential voltage. The sense amplifier compares the differential pair of bit lines to determine which of the bit lines is HIGH and which is LOW. Based on this comparison, the sense amplifier makes a determination as to what is stored in the storage cell. However, in real operations, the differential voltage inputs into the sense amplifier may be skewed, which may cause an imbalance or offset in the sense amplifier. More particularly, many conventional sense amplifiers contain two sensing transistors. Due to many factors, the two sensing transistors may have slightly different voltage thresholds. For example the voltage threshold of one of the sense transistors may be a few mV higher or lower than the other sense transistor. This imbalance, or offset, may cause the sense amplifier to provide an incorrect determination as to what data is stored in the storage cell, especially whenever the difference in voltage in the differential pair is very small. Conventional techniques utilized to cancel the offset of the transistors in a sense amplifier include turning on and/or off transistors within the sense amplifier to balance the offset or adding a separate voltage on the input of sense amplifier to cancel the offset effect. However, these techniques either require additional power and/or slow the access time of the memory. Therefore, it is desirable to create a sense amplifier in memory that reduces power consumption and increases speed (i.e., reduces access times).
[0013] In accordance with the disclosed principles, a sense amplifier may include two transistors. The voltage threshold of the two transistors may be controlled by providing adaptive body bias to the transistors (i.e., a voltage to the back of the gate of the transistors). For example, if the transistors are n-channel metal oxide semiconductor field effect (NMOS) transistors, applying a positive body bias voltage to the transistor decreases the voltage threshold of the transistor while applying a negative body bias voltage to the transistor increases the voltage threshold of the transistor. Therefore, by applying the adaptive body bias to the sense transistors of the sense amplifier in the SRAM, the offset may be reduced or removed. Because the swing required to be produced by the sense amplifier is related to the offset (i.e., the larger the offset, the larger the swing required to read the storage cell), power may be reduced by lowering the offset. Additionally, by reducing offset, the sense amplifier is capable of making an accurate determination of the difference between the voltages of the differential pair of bit lines with smaller voltage differentials. Therefore, a reduced offset sense amplifier may sense the voltage differential at an earlier time during the bit cell discharge than an offset sense amplifier. Thus, by providing adaptive body bias to the sense transistors of the sense amplifier, power and access times may be reduced.
[0014] FIG. 1 shows a block diagram of an integrated circuit 100 in accordance with various embodiments. Integrated circuit 100 may include processor 102 and SRAM 104, which may, in some embodiments, be coupled to processor 102. Integrated circuit 100 may also include various additional components, such as transceivers, clock generators and ports. However, these components have been omitted for clarity. Processor 102 may be a control processor, a signal processor, a central processor, or any other type of processor. For example, processor 102 may be a general-purpose microprocessor, a digital signal processor, a microcontroller, or other suitable device configured to execute instructions for performing operations. Processor architectures generally include execution units (e.g., fixed point, floating point, integer), instruction decoding, peripherals (e.g., interrupt controllers, timers, direct memory access controllers), input/output systems (e.g., serial ports, parallel ports) and various other components and sub-systems.
[0015] SRAM 104 is static random access memory which may provide storage of data and/or instructions that are capable of being processed by processor 102. SRAM 104 is designed such that it exhibits data remanence and utilizes latching circuitry to store each bit of data. SRAM 104 is coupled to processor 102 such that processor 102 may read from and/or write data and/or instructions to SRAM 104 for storage. In some embodiments, SRAM 104 is a part of processor 102 while in alternative embodiments, SRAM 104 is distinct from processor 102. Furthermore, multiple SRAMs 104 may be included in integrated circuit 100.
[0016] FIG. 2 shows a block diagram of a SRAM 104 in accordance with various embodiments. SRAM 104 may include storage cell array 202, read controller 204, column decoder 206, and sense amplifiers 208-210. Storage cell array 202 may be arranged as rows and columns of storage cells, sometimes referred to as bit cells, each storage cell storing one bit of data.
[0017] FIG. 3 shows a block diagram of storage cell array 202 in accordance with various embodiments. Storage cell array 202 may include word lines 302-312 which correspond to the rows of storage cell array 202 and columns 322-328. Each of columns 322-328 may include a differential pair of bit lines. For example, column 322 may include bit lines 332-334; column 324 may include bit lines 336-338; column 326 may include bit lines 340-342; and column 328 may include bit lines 344-346. At the intersection of each of the word lines 302-312 and the columns 322-328, are the storage cells, such as storage cells 352, 354 and 356, that make up storage cell array 202.
[0018] Each of the storage cells in storage array 202, such as storage cells 352, 354, and 356 may be arranged to store a single bit of data. In some embodiments, each of the storage cells comprises a six-transistor ("6T") SRAM cell that is formed with a pair of cross-coupled inverters. Each inverter includes a p-channel transistor and an n-channel transistor. The source of a first pass gate transistor is connected to the gate nodes of the first inverter and the drain nodes of the second inverter. Similarly, the source of a second pass gate transistor, is connected to the gate nodes of the second inverter and the drain nodes of the first inverter. The gates of the pass gate transistors are connected to a common word line, such as word line 302 for storage cells 352 and 354 and word line 308 for storage cell 356, while the drains of the pass gate transistors are connected to a differential pair of bit lines, such as bit lines 332 and 334 for storage cells 352 and 356 and bit lines 336 and 338 for storage cell 354. In alternative embodiments, the storage cells of storage array 202 may be any type of SRAM bit cell, such as a four-transistor ("4T") SRAM cell, an eight- transistor ("8T") SRAM cell, a ten-transistor ("lOT") SRAM cell, or any other SRAM storage cell.
[0019] Referring again to FIG. 2, read controller 204 is coupled to storage cell array 202 and is configured to manage the reading of the storage cells contained in storage cell array 202. Read controller 204 may be any type of memory controller that manages the flow of data going from and to storage cell array 202. At the beginning of a read cycle, read controller 204 is configured to cause each of the differential pairs of bit lines (both positive and negative signals) to precharge to a common voltage. To read any of the storage cells, the word line corresponding to the storage cell to be read is activated. For example, if storage cell 352 is to be read, then word line 302 is activated. In some embodiments, a row controller (not shown) may cause the word line to activate. After the word line is activated, each of the pass gate transistors from each of the storage cells on the activated word line is enabled. For example, if word line 302 is activated, then pass gate transistors in storage cells 352 and 354 are enabled, and the pass gate transistors for any other storage cell connected to word line 302 are enabled. This causes the bit line voltage for one of the two differential pairs of bit lines connected to each of the storage cells to drop based on whether the storage cell connected to the differential pair stores a 0 or a 1. For example, after word line 302 is activated, the voltage along bit line 332 or 334 will drop based on whether storage cell 352 stores a 0 or a 1. Similarly, the voltage along bit line 336 or 338 will drop based on whether storage cell 354 contains a 0 or a 1.
[0020] Column decoder 206 determines which of the columns 322-328 from FIG. 3 contains the storage cell that is to be read. More specifically, column decoder 206 is configured to receive an output signal from each of the columns 322-328 and select the output signal form the column corresponding to the storage cell being read. Each of the output signals corresponds to the differential voltage carried in the differential pair of bit lines. For example, if storage cell 352 is to be read, column decoder 206 selects column 322 and its differential pair of bit lines 332-334. Sense amplifier 208 then may sense which of the selected differential pair of bit lines has the higher voltage through amplification, thus determining whether the storage cell stores a 0 or a 1. Accordingly, the sense amplifier 208 is configured to determine the state of the selected column by sensing the column voltage differential. Continuing the previous example, after column decoder 206 selects column 322, the sense amplifier 208 will sense, or determine, which of bit lines 332 and 334 has a higher voltage. After this is determined, the state of storage cell 352 is able to be determined. In some embodiments, multiple sense amplifiers 208-210 may exist. The ellipsis between the sense amplifiers 208-210 indicates that any number of sense amplifiers may exist, although only two are shown for clarity. For example, each column 322-328 may have its own sense amplifier. In other examples, a single sense amplifier may be utilized to sense the differential for 4 columns, 8 columns, 16 columns, 32 columns, etc. of the storage cell array 202.
[0021] FIG. 4 shows an example circuit diagram of sense amplifier 208 in accordance with various embodiments. Sense amplifier 208 may comprise switches 402 and 404 and cross coupled transistors 406-412. In some embodiments, switches 402 and 404 act to turn on and off the sense amplifier 208. Accordingly, after column decoder 206 selects the column that is to be sensed, switches 402-404 may be switched open and/or closed in such a way, that sense amplifier 208 is turned on and begins to sense the voltage differential between the bit lines. For example, after column decoder 206 selects column 322 to be sensed, in order to read storage cell 352, switches
[0022] Sense transistors 410-412 are configured to read the data stored in at least one storage cell. In some embodiments, sense transistors 410-412 are MOS transistors. While shown as MOS transistors in FIG. 4, in some embodiments, sense transistors 410-412 may be p-channel metal-oxide-semiconductor field-effect (PMOS) transistors, p-type junction gate field-effect transistors (PJFET), n-type junction gate field-effect transistors (NJFET), and/or bipolar junction transistors (BJT) (including PNP and NPN transistors). Because of the manufacturing process (and many other potential reasons), sense transistors 410-412 may not have the same voltage threshold even though the sense amplifier 208 is designed such that the sense transistors 410-412 have the same voltage threshold. Therefore, an offset may exist between the two sense transistors 410-412. Accordingly, sense transistor 410, in an embodiment, is configured to receive a body bias such that its voltage threshold is approximately equal (i.e., plus or minus 50mV) to the voltage threshold of sense transistor 412. In alternative embodiments, sense transistor 412 is configured to receive a body bias such that its voltage threshold is approximately equal (i.e., plus or minus 50m V) to the voltage threshold of sense transistor 410.
[0024] If the read fails (i.e., if the sense amplifier 208 fails to correctly read the known data stored in bit cell 352), then the forward body bias of sense transistor 410 may be incremented by a predetermined voltage and the process repeats with reading storage cell 352 to determine whether sense amplifier 208 correctly reads the data stored in storage cell 352. Accordingly, the read of storage cell 352 then may be repeated with the forward body bias of sense transistor 410 being incremented after each read fail. However, if the maximum allowable forward body bias for sense transistor 410 has been reached, then the forward body bias of sense transistor 410 may be reset to zero. Additionally, the forward body bias of sense transistor 412 may be incremented by a predetermined voltage. The read of storage cell 352 then may be repeated with the forward body bias of sense transistor 412 being incremented after each read fail.
[0025] After the read passes (i.e., if the sense amplifier 208 correctly reads the known data stored in bit cell 352), then the forward body bias calibration may end and the forward body bias settings (i.e., the forward body bias applied to each of sense transistors 410-412 at the time the read passes) may be stored or saved in a memory of the integrated circuit 100 (not shown) and the same process may be utilized to calibrate sense amplifier 210 by reading storage cell 354. In some embodiments, multiple reads of storage cell 352 may be performed to verify that the sense amplifier 208 is correctly reading the storage cell 352.
[0026] FIG. 5 shows a flow diagram of method 500 for reducing power consumption and increasing speed in SRAM 104 in accordance with various embodiments. Though depicted sequentially as a matter of convenience, at least some of the actions shown in method 500 can be performed in a different order and/or performed in parallel. Additionally, some embodiments may perform only some of the actions shown or may perform additional actions. In some embodiments, at least some of the operations of the method 500, and other operations described herein, can be performed by SRAM 104 and/or sense amplifiers 208-210 implemented by a processor executing instructions stored in a non-transitory computer readable storage medium or a state machine.
[0027] Method 500 begins in block 502 with writing data into a SRAM array, such as storage array 202. The data that is written into the SRAM array may be known data. Accordingly, the contents of the storage cells of the SRAM array are known before being read from the array. In block 504, the method 500 continues with initializing the body bias of first and second transistors, such as sense transistors 410-412, of a sense amplifier, such as sense amplifier 208, to zero. Accordingly, no forward body bias is applied to the first and second transistors when initialized. The method 500 continues with setting the margin mode of the sense amplifier to the fastest setting. Thus, the sense amplifier is set to trigger at the earliest possible time and least amount of bit cell discharge.
[0028] In block 508, the method 500 continues with reading a storage cell, such as storage cell 352, of the SRAM array. The method 500 continues in block 510 with determining whether the read from block 508 has passed. Accordingly, a determination is made as to whether the sense amplifier correctly read the known data stored in the storage cell. If, in block 510, a determination is made that the read from block 508 has passed (i.e., a determination is made that the sense amplifier has correctly read the known data stored in the storage cell), then in block 512, the method 500 continues with saving the body bias settings (i.e., the body bias applied to the first and second transistors) at the time of the reading in block 508. In block 514, the method 500 continues with determining whether any other sense amplifiers, such as sense amplifier 210, remain to be calibrated in the SRAM. If, in block 514, a determination is made that this is the last sense amplifier in the SRAM to be calibrated, then the method 500 ends in block 516. However, if, in block 514, a determination is made that this is not the last sense amplifier in the SRAM to be calibrated (e.g., sense amplifier 210 needs to be calibrated), then the method continues in block 504 with initializing the body bias of a first and second transistor of the new sense amplifier, such as sense amplifier 210, to zero.
[0029] If, in block 510, a determination is made that the read from block 508 has not passed (i.e., a determination is made that the sense amplifier has failed to correctly read the known data stored in the storage cell), then in block 518, the method 500 continues with determining whether the body bias of the first transistor is at a maximum level, which may be predetermined. If, in block 518, a determination is made that the body bias of the first transistor is not at the maximum level, then the method 500 continues in block 520 with incrementing the body bias of the first transistor. In some embodiments, the amount that the body bias of the first transistor is incremented is predetermined. The method 500 then may continue in block 508 with reading the storage cell of the array.
[0030] If, in block 518, a determination is made that the body bias of the first transistor is at the maximum level, then the method 500 continues in block 522 with setting the body bias of first transistor to zero. In block 524, the method 500 continues with incrementing the body bias of the second transistor, such as transistor 412. In some embodiments, the amount that the body bias of the second transistor is incremented is predetermined. In block 526, the method 500 continues with reading the storage cell of the array again. The method 500 continues in block 528 with determining whether the read from block 528 has passed (i.e., whether the sense amplifier correctly read the known data stored in the storage cell). If, in block 528, a determination is made that the read from block 526 has passed (i.e., a determination is made that the sense amplifier has correctly read the known data stored in the storage cell), then in block 530, the method 500 continues with saving the body bias settings (i.e., the body bias applied to the first and second transistors) at the time of the reading in block 526. In block 532, the method 500 continues with determining whether any other sense amplifiers, such as sense amplifier 210, remain to be calibrated in the SRAM. If, in block 532, a determination is made that this is the last sense amplifier in the SRAM to be calibrated, then the method 500 ends in block 534. However, if, in block 532, a determination is made that this is not the last sense amplifier in the SRAM to be calibrated (e.g., sense amplifier 210 needs to be calibrated), then the method continues in block 504 with initializing the body bias of a first and second transistor of the new sense amplifier, such as sense amplifier 210, to zero.
[0031] If, in block 528, a determination is made that the read from block 526 has not passed (i.e., a determination is made that the sense amplifier has failed to correctly read the known data stored in the storage cell), then in block 536, the method 500 continues with determining whether the body bias of the second transistor is at a maximum level, which may be predetermined. If, in block 536, a determination is made that the body bias of the second transistor is not at the maximum level, then the method 500 continues in block 524 with incrementing the body bias of the second transistor. In some embodiments, the amount that the body bias of the second transistor is incremented is predetermined. However, if in block 536, a determination is made that the body bias of the second transistor is at the maximum level, then the method 500 continues in block 538 with setting the body bias of the second transistor to zero.
[0032] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

中文:
[0001]静态随机存取存储器(SRAM)利用锁存来存储每一位。因为SRAM是静态的,所以存储器的周期性刷新是不必要的,且因此,SRAM通常比动态随机存取存储器(DRAM)更快、密度更低且更昂贵。由于SRAM的速度,SRAM通常用于需要快速存储器(例如用于中央处理单元(CPU)的高速缓冲存储器、外部突发模式SRAM高速缓冲存储器、硬盘缓冲器、路由器缓冲器及CPU寄存器文件)的计算机应用中。尽管SRAM较快,但其也消耗很大一部分的系统级动态功率。在一些情况中,SRAM可消耗高达90%的系统级动态功率。
[0002]在所描述的用于降低静态随机存取存储器(SRAM)中的功率消耗并增加其中的速度的系统及方法的实例中,所述SRAM包含存储单元阵列及第一感测放大器。所述存储单元阵列布置为行及列。所述行对应于字线,且所述列对应于位线。所述第一感测放大器包含第一晶体管及第二晶体管。所述第一感测放大器经配置以提供对所述存储单元阵列的第一存储单元的第一读取。基于对所述第一存储单元的所述第一读取不能正确地读取存储于所述第一存储单元中的数据,所述第一感测放大器经配置以第一次递增所述第一晶体管的体偏置。响应于所述第一晶体管的所述体偏置被递增,所述第一感测放大器经配置以提供对所述第一存储单元的第二读取。
[0003]在用于降低SRAM中的功率消耗并增加其中的速度的实例方法中,所述方法包含:将已知数据写入到布置为行及列的存储单元阵列的多个存储单元中;第一次读取所述多个存储单元中的第一存储单元;基于第一次读取所述第一存储单元不能正确地从所述第一存储单元读取所述已知数据,递增所述SRAM的第一感测放大器的第一晶体管的体偏置;及响应于所述第一晶体管的所述体偏置被递增,第二次读取所述第一存储单元。
[0004]实例SRAM感测放大器包含第一晶体管及第二晶体管。所述第二晶体管与所述第一晶体管交叉耦合。所述第一晶体管经配置以接收体偏置使得所述第一晶体管的电压阈值近似等于所述第二晶体管的电压阈值。
[0006]图2展示根据各种实施例的静态随机存取存储器(SRAM)的框图。
[0007]图3展示根据各种实施例的存储单元阵列的框图。
[0008]图4展示根据各种实施例的感测放大器的电路图。
[0009]图5展示根据各种实施例的用于降低SRAM中的功率消耗并增加其中的速度的方法的流程图。
[0010]术语“耦合”意味着间接或直接连接。举例来说,如果第一装置耦合到第二装置,那么那个连接可为通过直接连接或通过经由其它装置及连接的间接连接。叙述“基于”意味着“至少部分基于”。举例来说,如果X是基于Y,那么X可为基于Y及任何数目个其它因素。
[0011]静态随机存取存储器(SRAM)是利用锁存存储每一位的存储器。因为SRAM是静态的,所以存储器的周期性刷新是不必要的,且因此SRAM通常比动态随机存取存储器(DRAM)更快、密度更低且更昂贵。由于SRAM的速度,SRAM通常用于需要快速存储器(例如用于中央处理单元(CPU)的高速缓冲存储器、外部突发模式SRAM高速缓冲存储器、硬盘缓冲器、路由器缓冲器及CPU寄存器文件)的计算机应用中。因此,SRAM是许多系统的基本构建块。尽管SRAM较快,但其也消耗很大一部分的系统级动态功率。在一些情况中,SRAM可消耗高达90%的系统级动态功率。因此,需要在增加速度的同时降低SRAM的功率消耗。
[0012]每当读取存储器的存储单元阵列中的存储单元时,起始位线的预充电。在预充电常规SRAM中的位线之后,激活对应于待读取其中的存储单元的行的字线。此在对应于含有被读取的存储单元的列的差分位线对中产生差分电压。接着,可利用感测放大器通过感测差分电压来读取存储单元的内容。感测放大器比较差分位线对以确定位线中的哪一者高及哪一者低。基于此比较,感测放大器做出关于存储在存储单元中的内容的确定。然而,在实际操作中,到感测放大器的差分电压输入可能偏斜,这可致使感测放大器中的不平衡或偏移。更特定来说,许多常规感测放大器含有两个感测晶体管。由于许多因素,两个感测晶体管可能具有稍微不同的电压阈值。举例来说,感测晶体管中的一者的电压阈值可比另一感测晶体管高或低几mV。此不平衡或偏移可能致使感测放大器提供关于存储在存储单元中的数据的不正确确定,尤其是每当差分对中的电压的差十分小时。用于消除感测放大器中的晶体管的偏移的常规技术包含接通及/或关断感测放大器内的晶体管以使偏移平衡或在感测放大器输入上添加单独电压来消除偏移效应。然而,这些技术需要额外功率及/或减慢存储器的存取时间。因此,可能需要在存储器中创建降低功率消耗并增加速度(即,减少存取时间)的感测放大器。
[0013]根据所揭示的原理,感测放大器可包含两个晶体管。可通过将自适应体偏置提供到晶体管(即,到晶体管的栅极的后部的电压)来控制两个晶体管的电压阈值。举例来说,如果晶体管是n通道金属氧化物半导体场效应(NMOS)晶体管,那么将正体偏置电压施加到晶体管会减少晶体管的电压阈值,而将负体偏置电压施加到晶体管会增加晶体管的电压阈值。因此,通过将自适应体偏置施加到SRAM中的感测放大器的感测晶体管,可减小或去除偏移。因为需要由感测放大器产生的摆动与偏移相关(即,偏移越大,读取存储单元所需的摆动越大),所以可通过降低偏移来降低功率。另外,通过减少偏移,感测放大器能够以更小电压差分做出位线差分对的电压之间的差的准确确定。因此,偏移经减小的感测放大器可在位单元放电期间比偏移感测放大器更早地感测到电压差。因此,通过将自适应体偏置提供到感测放大器的感测晶体管,可减少功率及存取时间。
[0014]图1展示根据各种实施例的集成电路100的框图。集成电路100可包含处理器102及SRAM 104,在一些实施例中,SRAM 104可耦合到处理器102。集成电路100还可包含各种额外组件,例如收发器、时钟发生器及端口。然而,为了清楚起见,省略了这些组件。处理器102可为控制处理器、信号处理器、中央处理器或任何其它类型的处理器。举例来说,处理器102可为通用微处理器、数字信号处理器、微控制器或经配置以执行用于执行操作的指令的其它合适的装置。处理器架构通常包含执行单元(例如,定点、浮点、整数)、指令解码、外围设备(例如,中断控制器、定时器、直接存储器存取控制器)、输入/输出系统(例如,串行端口、并行端口)及各种其它组件及子系统。
[0015]SRAM 104是静态随机存取存储器,其可提供能够由处理器102处理的数据及/或指令的存储。SRAM 104经设计使得其展现数据残留,且利用锁存电路来存储每一位数据。SRAM104耦合到处理器102使得处理器102可从SRAM 104读取数据及/或指令及/或将数据及/或指令写入到SRAM 104以供存储。在一些实施例中,SRAM 104是处理器102的一部分,而在替代实施例中,SRAM 104与处理器102不同。此外,多个SRAM 104可包含于集成电路100中。
[0016]图2展示根据各种实施例的SRAM 104的框图。SRAM 104可包含存储单元阵列202、读取控制器204、列解码器206及感测放大器208到210。存储单元阵列202可布置为存储单元的行及列,有时称之为位单元,每一存储单元存储一位数据。
[0017]图3展示根据各种实施例的存储单元阵列202的框图。存储单元阵列202可包含字线302到312,其对应于存储单元阵列202的行及列322到328。列322到328中的每一者可包含差分位线对。举例来说,列322可包含位线332到334;列324可包含位线336到338;列326可包含位线340到342;且列328可包含位线344到346。在字线302到312中的每一者与列322到328的相交处是组成存储单元阵列202的存储单元,例如存储单元352、354及356。
[0018]存储阵列202中的存储单元中的每一者(例如,存储单元352、354及356)可经布置以存储单个数据位。在一些实施例中,存储单元中的每一者包括六晶体管(“6T”)SRAM单元,其由一对交叉耦合反相器形成。每一反相器包含p通道晶体管及n通道晶体管。第一导通门晶体管的源极连接到第一反相器的栅极节点及第二反相器的漏极节点。类似地,第二导通门晶体管的源极连接到第二反相器的栅极节点及第一反相器的漏极节点。导通门晶体管的栅极连接到共同字线,例如用于存储单元352及354的字线302及用于存储单元356的字线308,而导通门晶体管的漏极连接到差分位线对,例如用于存储单元352及356的位线332及334及用于存储单元354的位线336及338。在替代实施例中,存储阵列202的存储单元可为任何类型的SRAM位单元,例如四晶体管(“4T”)SRAM单元、八晶体管(“8T”)SRAM单元、十晶体管(“10T”)SRAM单元或任何其它SRAM存储单元。
[0019]再次参考图2,读取控制器204耦合到存储单元阵列202且经配置以管理含于存储单元阵列202中的存储单元的读取。读取控制器204可为管理数据从存储单元阵列202的流动及数据到存储单元阵列202的流动的任何类型的存储器控制器。在读取循环的开始处,读取控制器204经配置以致使差分位线对中的每一者(正信号及负信号两者)预充电到共同电压。为了读取存储单元中的任何者,激活对应于待读取的存储单元的字线。举例来说,如果将读取存储单元352,那么激活字线302。在一些实施例中,行控制器(未展示)可致使激活字线。在激活字线之后,启用来自经激活字线上的存储单元中的每一者的导通门晶体管中的每一者。举例来说,如果激活字线302,那么启用存储单元352及354中的导通门晶体管,且启用连接到字线302的任何其它存储单元的导通门晶体管。这致使用于连接到存储单元中的每一者的两个差分位线对中的一者的位线电压基于连接到差分对的存储单元是存储0还是1而下降。举例来说,在激活字线302之后,沿着位线332或334的电压将基于存储单元352是存储0还是1而下降。类似地,沿着位线336或338的电压将基于存储单元354是含有0还是1而下降。
[0020]列解码器206确定来自图3的列322到328中的哪一者含有待读取的存储单元。更具体来说,列解码器206经配置以从列322到328中的每一者接收输出信号且从对应于被读取的存储单元的列选择输出信号。输出信号中的每一者对应于载送于差分位线对中的差分电压。举例来说,如果将读取存储单元352,那么解码器206选择列322及其差分位线对332到334。接着,感测放大器208可通过放大来感测所选择的差分位线对中的哪一者具有更高电压,从而确定存储单元是存储0还是1。因此,感测放大器208经配置以通过感测列电压差分来确定所选择的列的状态。继续前一实例,在列解码器206选择列322之后,感测放大器208将感测或确定位线332及334中的哪一者具有更高电压。在确定此之后,能够确定存储单元352的状态。在一些实施例中,可存在多个感测放大器208到210。感测放大器208到210之间的省略号指示可存在任何数目个感测放大器,但为了清楚起见仅展示两个感测放大器。举例来说,每一列322到328可具有其自身的感测放大器。在其它实例中,可利用单个感测放大器感测存储单元阵列202的4个列、8个列、16个列、32个列等的差分。
[0021]图4展示根据各种实施例的感测放大器208的实例电路图。感测放大器208可包括开关402及404以及交叉耦合的晶体管406到412。在一些实施例中,开关402及404用于接通及关断感测放大器208。因此,在列解码器206选择将感测的列之后,开关402到404可以使得感测放大器208被接通且开始感测位线之间的电压差分的方式被切换为断开及/或闭合。举例来说,在列解码器206选择列322进行感测之后,为了读取存储单元352,开关402到404被切换为断开及/或闭合,以使得感测放大器208的其余组件(例如晶体管406到412)可感测位线332到334之间的电压差分。
[0022]感测晶体管410到412经配置以读取存储于至少一个存储单元中的数据。在一些实施例中,感测晶体管410到412是NMOS晶体管。虽然在图4中被展示为NMOS晶体管,但在一些实施例中,感测晶体管410到412可为p通道金属氧化物半导体场效应(PMOS)晶体管、p型结栅场效应晶体管(PJFET)、n型结栅场效应晶体管(NJFET)及/或双极结晶体管(BJT)(包含PNP及NPN晶体管)。因为制造工艺(及许多其它潜在原因),感测晶体管410到412可能不具有相同电压阈值,即使感测放大器208经设计使得感测晶体管410到412具有相同电压阈值。因此,两个感测晶体管410到412之间可存在偏移。因此,在实施例中,感测晶体管410经配置以接收体偏置使得其电压阈值近似等于(即,加或减50mV)感测晶体管412的电压阈值。在替代实施例中,感测晶体管412经配置以接收体偏置使得其电压阈值近似等于(即,加或减50mV)感测晶体管410的电压阈值。
[0024]如果读取失败(即,如果感测放大器208不能正确地读取存储于位单元352中的已知数据),那么可使感测晶体管410的正体偏置递增达经预先确定的电压,且所述过程重复读取存储单元352以确定感测放大器208是否正确地读取存储于存储单元352中的数据。因此,接着,在感测晶体管410的正体偏置在每一读取失败之后递增的情况下,可重复存储单元352的读取。然而,如果达到了感测晶体管410的最大可允许正体偏置,那么感测晶体管410的正体偏置可复位到零。另外,感测晶体管412的正体偏置可递增达经预先确定的电压。接着,在感测晶体管412的正体偏置在每一读取失败之后递增的情况下,可重复存储单元352的读取。
[0025]在读取通过之后(即,如果感测放大器208正确地读取存储于位单元352中的已知数据),那么正体偏置校准可结束且正体偏置设置(即,在读取通过时施加到感测晶体管410到412中的每一者的正体偏置)可被存储或保存在集成电路100的存储器(未展示)中,且可利用相同过程通过读取存储单元354校准感测放大器210。在一些实施例中,可执行存储单元352的多次读取以验证感测放大器208正确地读取存储单元352。
[0026]图5展示根据各种实施例的用于降低SRAM 104中的功率消耗并增加其中的速度的方法500的流程图。尽管为了方便起见循序地描绘,但可以不同顺序执行方法500中展示的至少部分动作及/或并行执行所述动作。另外,一些实施例可执行所展示动作中的仅部分或可执行额外动作。在一些实施例中,方法500的至少部分操作及本文描述的其它操作可由SRAM 104及/或感测放大器208到210执行,其由执行存储于非暂时性计算机可读存储媒体或状态机中的指令的处理器实施。
[0027]方法500在框502中以将数据写入到SRAM阵列中开始,例如存储阵列202。被写入到SRAM阵列中的数据可为已知数据。因此,SRAM阵列的存储单元的内容在被从阵列读取之前是已知的。在框504中,方法500以将第一晶体管及第二晶体管的体偏置初始化为零而继续,所述晶体管例如感测放大器(例如感测放大器208)的感测晶体管410到412。因此,当初始化时,无正体偏置被施加到第一晶体管及第二晶体管。方法500以将感测放大器的容限模式设置到最快设置而继续。因此,设置感测放大器以在最早可能时间及以最小位单元放电量触发。
[0028]在框508中,方法500以读取SRAM阵列的存储单元(例如存储单元352)而继续。方法500在框510中以确定来自框508的读取是否已通过而继续。因此,做出关于感测放大器是否正确地读取存储于存储单元中的已知数据的确定。如果在框510中,做出来自框508的读取已通过的确定(即,做出感测放大器已正确地读取存储于存储单元中的已知数据的确定),那么在框512中,方法500以保存框508中的读取时间处的体偏置设置(即,施加到第一晶体管及第二晶体管的体偏置)而继续。在框514中,方法500以确定SRAM中的任何其它感测放大器(例如感测放大器210)是否有待被校准而继续。如果在框514中,做出此是SRAM中待校准的最后感测放大器的确定,那么方法500在框516中结束。然而,如果在框514中做出此并非SRAM中待校准的最后感测放大器的确定(例如,感测放大器210需要被校准),那么方法在框504中以将新感测放大器(例如感测放大器210)的第一晶体管及第二晶体管的体偏置初始化为零而继续。
[0029]如果在框510中做出来自框508的读取尚未通过的确定(即,做出感测放大器不能正确地读取存储于存储单元中的已知数据的确定),那么在框518中,方法500以确定第一晶体管的体偏置是否处于可为经预先确定的最大电平而继续。如果在框518中,做出第一晶体管的体偏置并非处于最大电平的确定,那么方法500在框520中以递增第一晶体管的体偏置而继续。在一些实施例中,第一晶体管的体偏置递增的量是经预先确定的。接着,方法500可在框508中以读取阵列的存储单元而继续。
[0030]如果在框518中做出第一晶体管的体偏置处于最大电平的确定,那么方法500在框522中以将第一晶体管的体偏置设置为零而继续。在框524中,方法500以递增第二晶体管(例如晶体管412)的体偏置而继续。在一些实施例中,第二晶体管的体偏置递增的量是经预先确定的。在框526中,方法500以再次读取阵列的存储单元而继续。方法500在框528中以确定来自框528的读取是否已通过(即,感测放大器是否正确地读取存储于存储单元中的已知数据)而继续。如果在框528中做出来自框526的读取已通过的确定(即,做出感测放大器已正确地读取存储于存储单元中的已知数据的确定),那么在框530中,方法500以保存在框526中的读取时间处的体偏置设置(即,施加到第一晶体管及第二晶体管的体偏置)而继续。在框532中,方法500以确定SRAM中的任何其它感测放大器(例如感测放大器210)是否有待被校准而继续。如果在框532中做出此是SRAM中待校准的最后感测放大器的确定,那么方法500在框534中结束。然而,如果在框532中,做出此并非SRAM中待校准的最后感测放大器的确定(例如,感测放大器210需要被校准),那么方法在框504中以将新感测放大器(例如感测放大器210)的第一晶体管及第二晶体管的体偏置初始化为零而继续。
[0031]如果在框528中做出来自框526的读取尚未通过的确定(即,做出感测放大器不能正确地读取存储于存储单元中的已知数据的确定),那么在框536中,方法500以确定第二晶体管的体偏置是否处于可为经预先确定的最大电平而继续。如果在框536中做出第二晶体管的体偏置并非处于最大电平的确定,那么方法500在框524中以递增第二晶体管的体偏置而继续。在一些实施例中,第二晶体管的体偏置递增的量是经预先确定的。然而,如果在框536中做出第二晶体管的体偏置处于最大电平的确定,那么方法500在框538中以将第二晶体管的体偏置设置为零而继续。
[0032]修改在所描述的实施例中是可能的,且在权利要求书的范围内其它实施例是可能的。