English:
[0001] This application claims the benefit of provisional U.S. Application Serial No. 60/642,934, entitled "A Multi-Threshold MOS Flip-Flop Circuit," filed January 10, 2005.
[0002] The present invention relates generally to electronic circuits, and more specifically to metal oxide semiconductor (MOS) circuits.
[0003] Integrated circuit (IC) fabrication technology continually improves and, as a result, the size of transistors continues to shrink. This enables more transistors and more complicated circuits to be fabricated on an IC die or, alternatively, a smaller IC die to be used for a given circuit. Smaller transistor size also supports faster operating speed and provides other benefits.
[0004] For complementary metal oxide semiconductor (CMOS), which is widely used for digital circuits and some analog circuits, a major issue with shrinking transistor size is leakage current. Smaller geometry for a transistor results in higher electric field, which stresses the transistor and causes oxide breakdown. To decrease the electric field, a lower power supply voltage may be used for the smaller geometry transistor. Unfortunately, the lower power supply voltage also increases the delay of the transistor, which is undesirable for a high-speed circuit. To reduce the delay and improve operating speed, the threshold voltage (Vt) of the transistor may be reduced. The threshold voltage is the voltage at which the transistor turn on. However, the lower threshold voltage and smaller geometry result in higher leakage current, which is the current passing through the transistor when it is turned off.
[0005] Leakage current is more problematic as CMOS technology scales smaller. This is because leakage current increases at a high rate with respect to the decrease in transistor size. Leakage current is also more problematic for certain applications such as portable devices, e.g., cellular phones and laptop computers. Leakage current consumes battery power and reduces standby time for portable devices that use internal batteries.
[0007] There is therefore a need in the art for CMOS circuits having good performance and low leakage current.
[0010] Various aspects and embodiments of the invention are described in further detail below.

中文:
[0001]本申请请求于2005年1月10日提交的标题为“A Multi-ThresholdMOS Flip-Flop Circuit”的美国临时申请号60/642,934的优先权。
[0002]本发明一般涉及电子电路,并且更具体地,涉及金属氧化物半导体(MOS)电路。
[0003]集成电路(IC)制造技术不断进步,从而使晶体管的尺寸不断缩小。这使得能将更多晶体管和更复杂电路制造在IC芯片上,或可选地,可对给定电路使用更小的IC芯片上。更小的晶体管尺寸还支持更快的操作速度并能提供其它好处。
[0004]对于广泛用于数字电路和一些模拟电路的互补型金属氧化物半导体,晶体管尺寸缩小带来的主要问题是泄漏电流。晶体管的几何尺寸越小就会导致电场越高,而该电场会压迫(stress)晶体管并且导致氧化物被击穿。为了减小电场,对于几何尺寸较小的晶体管可以使用较低的电源电压。但,较低的电源电压还增加了晶体管的延迟,为高速电路所不希望。为了减小延迟并提高操作速度,可减小晶体管的阈值电压(Vt)。阈值电压为晶体管开启时的电压。然而,较低的阈值电压和较小的几何尺寸导致较高的泄漏电流,泄漏电流是在晶体管关闭时流过晶体管的电流。
[0005]泄漏电流在CMOS技术尺寸减小时更加成为问题。这是因为泄漏电流以与晶体管尺寸缩小相关的较高比率增加。泄漏电流对于诸如便携式装置(例如蜂窝电话和膝上型计算机)之类的某些应用更加成为问题。对于使用内部电池的便携式装置,泄漏电流消耗电池电量并且减少待机时间。
[0007]因此在本领域中希望能出现性能好且泄漏电流低的CMOS电路。
[0010]本发明的各方面和各个实施例将在以下进行更详细的说明。