English:
[0001] Aspects of the present disclosure may relate to the design and fabrication of structured integrated circuits (ICs) that may also have a high degree of configurability. Various aspects may related to structured application-specific ICs (ASICs).
[0002] A structured ASIC, or IC in general, may have a combination of pre-made elements that may be manufactured in an initial manufacturing process and kept in inventory. The elements may later be interconnected to form a circuit or may be customized by means, e.g., of masks. In one or more further manufacturing processes. Such interconnections and customizations may result in greater flexibility in that the resulting IC may be customized for a particular customer application or to have particular characteristics, such as high speed, low power, etc. The result of such an approach to IC production may be an ability to amortize non-recurring engineering (NRE) costs over a wide range of devices and/or multiple customer applications. This approach may also result in improved yields and/or reduced manufacturing time, from tape-out to packaged chip.
[0003] While there may exist some methods for designing and manufacturing structured, configurable ICs, it may desirable, to improve upon existing techniques, in order to obtain even greater flexibility and/or to further improve characteristics of the resulting ICs for the purposes to which they are tailored.
[0004] Various aspects of the disclosure may be directed to techniques that may be used to increase flexibility and/or efficiency of customizable IC design. Such techniques may include, for example, but are not limited to, the use of multiple customizable via layers and/or customization of voltage thresholds in devices and/or customization of one or more metal layers. Such latter customization may include removal of unused metal and/or rerouting of metal within one or more metal layers.
[0006] FIG. 1 shows an example of a device including multiple metal and via layers, according to various aspects of the disclosure;
[0007] FIG. 2 shows a further example of a device including multiple metal and customizable via layers, according to various aspects of the disclosure;
[0008] FIG. 3 shows an example of an integrated circuit that may be designed using the example structure of FIG. 2, according to an aspect of the disclosure;
[0009] FIG. 4 shows a further example of portion of an integrated circuit that may be designed using the example structure of FIG. 2, according to an aspect of the disclosure;
[0010] FIG. 5 shows an example of a logic array structure according to an aspect of the disclosure;
[0011] FIGs. 6A and 6B show a schematic and M2/M3 layout of an example of a logic cell, according to an aspect of the disclosure;
[0012] FIG. 7 shows an example of a V4-programmable M4/M5 routing fabric, according to an aspect of this disclosure; and
[0013] FIG. 8 shows an example of a further customization, according to a further aspect of this disclosure.
[0014] A structured IC may have the form of a series of superimposed layers, a non-limiting example of which is shown in FIG. 1. In the example of FIG. 1, the lowest layer is labeled, "Transistor layers." This layer may not only contain transistors, per se, but may also include other electronic components, such as, but not limited to, resistors, capacitors, inductors, diodes, et al. Furthermore, the components of the transistor layers may be designed to form various types of functional blocks and sub-blocks, which may include non-programmable and/or programmable blocks. For example, in addition, or alternatively, to individual basic components, such as transistors, various components may be organized into functional blocks/sub-blocks, such as memory, logic devices, buffers, amplifiers, look-up tables, processor units (e.g., but not limited to, arithmetic logic units (ALUs)), high-speed serializers/deserializers (SERDES), etc. (i.e., the complexity of the components of the "transistor layers" may range from very simple to highly complex, as determined by the designer). Some components of the transistor layers may include highly-specialized devices, as well, rather than only generic components. Hence, while referred to herein as "transistor layers," this may also be referred to by other terms, such as "component layer(s)," "IP core," et al. Additionally, although labeled "transistor layers," this may comprise one or more structural layers (e.g., but not limited to, variously-doped different layers of silicon or other semiconductor materials, insulating materials, etc.). Furthermore, components of the transistor layers may be further customizable, for example, various components of the transistor layers may be interconnected to form functional blocks and/or blocks that may be useful for further interconnection into further functional blocks by interconnection layers of various types that may be superimposed on the transistor layers.
[0016] A contact layer CO may be superimposed directly on the transistor layers. Contact layer CO may include metal or other conductive substances. The contact layer CO may provide contact points, which may include contact points to at least one further superimposed layer (e.g., one or more metal interconnection layers) for further interconnection/connectivity. The transistor layers or the combination of the transistor layers with the contact layer CO may be a standard device that may be manufactured in large quantities, if desired, to provide an inventory that may be used to create further-customized devices. It is noted that, according to some aspects of the disclosure, the contact layer CO may be customizable.
[0017] Above the contact layer CO, there may be superimposed a series of alternating metallization and via layers. In the example of FIG. 1 , layers M1-M10 are metal layers, and layers VI -V9 are via layers. While ten metal and nine via layers are shown, the invention is not thus limited, and the numbers of such layers may be arbitrary. The metal layers may provide horizontal connectivity among or between components of lower layers, while the via layers may provide vertical connectivity between or among interconnections of various metal layers, where "horizontal" and "vertical" are being used in the sense of the orientation and structures shown in FIG. 1. Note that within a "horizontal" metal layer, it is also common usage to refer to metal strips directed in one direction as "horizontal" and metal strips directed in a perpendicular direction as "vertical." Unless otherwise specified in this disclosure, "horizontal" and "vertical" are being used in the first sense, i.e., the orientation of the overall structure of a device, rather than in the second sense, i.e., the orientation of structures within a layer of such a structure.
[0018] For example, Ml may contain a pattern of metal strips that may interconnect various devices/blocks formed by the transistor layers, and which may be connected to the transistor layers by contact layer CO. M2 may contain another pattern of metal strips for interconnection, for which VI may determine which interconnected components formed by Ml may be further interconnected by M2 layer. In the example of FIG. 1, this pattern of horizontal (Mn, where "Mn" represents the nthmetal layer) connectivity and vertical (Vm, where "Vm" represents the mthvia layer) connectivity may continue throughout the device, up to layer M10. These metal and via layers may enable the connection of the various components in/formed by the transistor layers and CO layer to form highly-complex and/or highly-customized devices.
[0019] A method of fabricating an integrated circuit may involve forming the transistor layers, forming the contact layer CO, and superimposing the metal and via layers. Customization, as will be further described below, may be performed during the forming of the superimposed metal and via layers.
[0020] Note that even though the descriptions provided herein may be with respect to the structure as shown, e.g., in FIGs. 1 and 2, and the terms "vertical," "horizontal,1' "upper" and "lower" are used with respect to the orientations shown in these drawings, the invention is not limited to this orientation. Any physical orientation of such a structure is contemplated, and the orientation is not limited to what is shown in FIGs. 1 and 2. For example, the transistor layers may be located on the top, with the metal and via layers progressing downward, a "sideways" implementation may be used, etc.
[0021] While the metal layers and via layers may be fixed, to form a standard ASIC, recent technologies may permit the use of customizable via layers that may enable the construction of custom ICs from a "standard" or "common" base device layer (i.e., the transistor layers and connection layer) by customizing the interconnections. For example, eASIC®Corporation has developed such technologies that may use patterned metal layers and/or a customizable via layer to obtain multiple ICs from a standard device layer. See, e.g., U.S. Patent Nos. 6,331,733, 6,331 ,790, 6,476,493, 6,642,744, 6,756,81 1, 6,953,956, 7,098,691 , 7, 157,937, 7,463,062, 7,514,959, and 7,550,996, which are incorporated by reference herein. However, the techniques disclosed in such patents may generally permit a single customizable via layer; also, such a single via layer may be customized without resorting to mask-based optical lithography and, instead, may be customized using a maskless e-beam process, e.g., as described in U.S. Patent No. 6,953,956.
[0023] The above techniques may be generalized by permitting any or all of via layers VI -V9, using the example of FIG. 1 (to which the invention is not limited; there may be more or fewer metal layers and/or via layers than as shown), to be customizable, which may thus permit greater flexibility of customization. Additionally, any or all of metal layers M1-M10 may be customized, which may provide even further design flexibility.
[0024] In a particular variation, a structured, flexible ASIC (SFASIC) may be provided in which each of the layers of the layout shown in FIG. 1 has a default state, and the resulting chip may have a default functionality defined by the default state of all of the layers; however, this is not necessarily the case. However, a manufacturer may benefit from having a default state/functionality that may correspond to a device that may be frequently sold, which may eliminate the need for specific customization when such a device is to be produced, which may, in turn, reduce the cost of manufacturing the device. The SFASIC may be customized, and in particular, one or more particular layers may be changed from their default states to custom states. A hardware design language, such as, but not limited to, register transfer language (RTL), may be used to specify the changes; this may be provided by a particular customer. In some aspects of this, only an arbitrary subset of layout layers may be changed from their default states to custom states. This may involve, for example, translation of the RTL or other language into specific via layer or other layer configurations.
[0025] FIG. 2 shows an example in which two of the via layers, V2 and V4, are shown as being customizable; however, the invention is not thus limited, and any subset of via layers (and/or metal layers) may be chosen for customization. This specific example of FIG. 2 may enable customizable vertical interconnectivity between M2 and M3 and between M4 and M5. As shown in this example, to which the invention is not limited, the remaining metal and via layers may be fixed.
[0026] FIG. 3 shows an example of an IC 30 that may be designed using the generic structure example of FIG. 2. FIG. 3 shows a number of different functional blocks of the IC 30. IC 30 may, for example, contain a design-for-test (DFT) microcontroller 31, which may be used to manage memory built-in self-test (BIST) functionality, repair and initialization. This block may be created by means of V2-programmable cells and V2/V4-prograrnmable routing fabric, and its functionality may thus be changed based on customer needs. The V2-programmable cells may be logic cells, which may be used to implement different logic functionality, depending upon how they are programmed. These cells may originally be part of a logic fabric, like logic fabric 36, which may contain such V2-programmable cells that may be interconnected using a V2 and/or V4-programmable routing. The IC may further contain a scrializer/deserializer delay generators 34 may also be provided; such delay generators 34 may be based on double data rate delay-lock loop (DDRDLL) technology and may, e.g., support strobe shifting for DDR-like interfaces. V4 programmability may be used to create a power-down option for delay generators 34. High-speed logic fabric 35 may be provided, which may support high-speed interfaces; this may be created using V2/V4 programming. The IC 30 of FIG. 3 may also have a memory block 37 that may contain random-access memory (RAM) and/or other memory and/or registers, which may be core memory for the device; V2 may be used to customize user interface variations, such as numbers of words and/or bits and/or double-pumping, which V4 may be used to create a power-down option. One or more clock generators 38 may be provided, which may used phase- locked loop (PLL) technology, and which may combine V2/V4 and/or Joint Test Action Group (JTAG) programmability for changing user clock parameters. Finally, the IC 30 may include V2/V4-programmable input/output (I/O) blocks 39. Such I/O blocks 39 may be programmed by vias to provide, e.g., single differential I/O, pairs of single-ended I/Os, or both. V2/V4- programmability may be used to support different standards and/or voltages.
[0027] FIG . 4 shows a further example of a portion of a core structure 40 that may be created using V2/V4-programmability, according to an aspect of this disclosure. The structure 40 may include a digitally-controlled delay line (DCDL) 41, which may be used, e.g., for support of high-speed interfaces. V4-programmability may be used to create a power-down option for DCDL 41. The structure 40 may include one or more cells (e.g., eCellTM logic cells by eASIC®Corporation), which may form a cell matrix 42, D-flip flops (DFFs) (e.g., eDFFTM DFFs by eASIC®Corporation), which may form a DFF column 43, block RAM 44, register files 45, etc. The structure 40 may further include one or more clock distribution cells 46, which may be V2- programmable and may utilize a V2/V4 programmable routing fabric that may implement cells and/or high-level layer clock track connections. The structure may further incorporate a highspeed logic fabric 47 (e.g., the eiomotifIMby eASIC* Corporation). This may be a block of V2- programmable cells, which are sequential and/or combinatorial, that may be optimized for highspeed operation, and this may include a V2/V 4-programmable routing fabric. Finally, the structure 40 may include a high-speed balancing fabric 48, which may be V2/V4-programmable and may enable one to create highly balanced connections between I/O and core logic.
[0028] In a generalization, demonstrated by, but not limited to the above examples, different functional blocks may be obtained by means of the same or different customized layers, even in the same IC. In the examples described above, some functional blocks involve customization of V2, only, some involve customization of V4, only, and some involve customization of both V2 and V4. Additionally, portions of the same functional block may involve customization of different layers or sets of layers (including the possibility that some portion of a given functional block may use no customized layers). In general, a single IC may include multiple functional blocks, and each of the multiple functional blocks may obtained or programmed using different combinations of customized via layers or customized metal layers or both customized via layers and customized metal layers.
[0029] FIG. 5 shows an example of a logic array structure that may, for example, be incorporated into a structure such as structure 40 of FIG. 4. In FIG. 5, logic cells (e.g., eCell1Mlogic cells) 51 may form a chess board-like pattern, which may be based on variation of V2/V4- based routing between neighboring cells. DFFs (e.g., eDFFTM DFFs) 52 may, e.g., simply be arranged in columns.
[0030] FIGs. 6A and 6B show a schematic and corresponding M2/M3 layout of a logic cell, according to an aspect of this disclosure. This is merely one variant of a logic cell and is merely provided as an illustrative example. Many other variations are possible.
[0031] FIG. 7 shows an example of a V4-programmable M4/M5 routing fabric, according to an aspect of this disclosure. In this particular example, the M4/M5 routing fabric is shown for a 2x2 array of logic cells (e.g., eCellsI M). V4-layer vias may be used to interconnect the wires of M4 and M5 to create customized routing patterns.
[0032] As previously noted, the non-limiting examples of FIGs. 3-7 utilize the non-limiting example of FIG. 2, in which V2 and V4 are the only customizable via layers. It is noted that the fabrication of some functional blocks may utilize customization in the V2 layer or the V4 layer or both the V2 and V4 layers. That is, even if multiple customizable via layers are used, some functional blocks may be created using the same subset or different subsets of the customizable via layers; it is also possible that some functional blocks or portions of functional blocks may not require customization of any customizable via layer and may, instead, use a default layout of a respective portion of one or more of the customizable via layers.
[0033] It is also stressed that the set of customizable via layers is not limited to V2 and V4, as shown in FIG. 2 and as used in the above examples. In general, any subset of two or more via layers may be customizable, and customization to obtain particular functionality may be obtained through customization of any subset of one or more of the customizable via layers, including a single via layer of the customizable via layers, and as noted above, functional blocks of a single IC may use customization of different layers or different combinations of layers of the subset of customizable via layers.
[0034] A structure such as that shown in FIG. 2, having multiple customizable via layers, may be achieved by a number of means. While direct- write e-beam, for example, may be effective for customizing a single customizable via layer, it may be more cost-effective, e.g., for mass production of ICs, to use mask-based techniques. As discussed, for example, in U.S. Patent No. 6,823,499, incorporated herein by reference, it is possible to create an IC having fixed and custom design parts using mask-based techniques. Custom layers may be sandwiched between fixed, non-customizable layers, and this technique may be used multiple times to create combinations of multiple customizable via layers, e.g., as in FIG. 2. As noted above, such techniques may be used to customize any subset of via layers in a layered structure, such as that shown in FIGs. 1 and 2.
[0035] In addition to having customizable via layers, an IC may also be customized using voltage threshold (VT) and/or gate-length variation of the devices in the transistor layers, as shown in FIGs. 1 and 2. VT may affect such factors as speed, power consumption, and/or cost. One may use low-VT (LVT), regular- VT (RVT), or high-VT (HVT) devices, or combinations thereof, in a given design. LVT, RVT and HVT may be relative terms or fixed. However, relative to an RVT device, an LVT device may exhibit higher speed but increased leakage current (and thus greater power consumption), while an HVT device may exhibit lower speed but decreased leakage current. Transistor gate length may similarly affect speed and power within a class of VT devices (LVT, RVT or HVT). VT and/or gate length may be customized by means of VT implant and/or gate fabrication masks used in fabricating the transistor layers.
[0036] According to an aspect of this disclosure, VT and gate length variations may be selected based on timing/speed and/or power requirements. Such selection may be performed using a static timing analysis based on the timing and power requirements.
[0037] According to another aspect of this disclosure, based on a cost perspective, the variations may be limited to VT variations, in order to reduce costs, in contrast with the customization of gate length.
[0038] In a further variation, according to aspects of this disclosure, one or more of the metal layers, e.g., as shown in FIGs. 1 and 2, may also be varied/customized. In one particular case, alluded to above, any subset of the metal layers may be customizable so that particular functionality may be obtained; this may be in combination with customization of a subset of the via layers.
[0039] In another particular case, portions of various metal layers may not actually be used in a particular IC design. Nonetheless, such portions may continue to conduct signals, resulting in unnecessary power consumption. Therefore, according to a further aspect of this disclosure, one or more metal layers may be customized, e.g., by removing unused metal, which may then limit interconnect capacity to only that needed for a particular IC design and may result in reduced power consumption. FIG. 8 shows an example of such metal layer customization by removal of unneeded metal. In the example of FIG. 8, metal strips 81, 82, and 83 provide examples in which the lengths of the strips have been shortened, compared with parallel metal strips shown, to eliminate unused portions of metal strips 81, 82 and 83. This may be done by customization of the metal layer prior to fabrication and fabrication of the customized metal layer, or by removal of the unused portions of metal after fabrication of the layer but prior to fabrication of any subsequent (higher) via and/or metal layers. This may be performed on multiple metal layers, if desired, to minimize interconnect capacity to that necessary and reduce dynamic power consumption.
[0040] In a further variation, one or more metal layers may be rerouted, which may optimize width and spacing of interconnects, e.g., by redistributing resource(s) of the layer(s) that are not utilized based on the custom design. For example, in FIG. 8, two examples of rerouting, in two metal layers shown in FIG. 8, are indicated by reference numeral 84.
[0041] The combination of rerouting and/or elimination of unneeded metal may, in addition to reducing dynamic power consumption, or in conjunction therewith, have additional benefits. For example, removal of metal may pemiit increased spacing 85 between adjacent metal strips. As a result, capacitance between the adjacent metal strips may be reduced, which may lead to a reduction in cross-talk and/or allow for increased signaling speed. Furthermore, this may enable some increase in widths of one or more metal strips (not shown), which may also reduce resistance in the respective metal strip(s) and may allow for increased signaling speed along the respective metal strip(s).
[0042] The above discussion has presented various aspects of this disclosure. It is contemplated that these various aspects may be used in any or all different combinations. For example, all of the different aspects of the disclosure may be used together, in a single device, or any subset of these aspects may be used in a single device. This disclosure is not limited to the use of these different aspects in isolation. For example, a single IC may use a stacked structure, as in FIGs. 1 and 2, which may have two or more customizable via layers and/or at least one customizable metal layer that may be customized for power consumption or speed or functionality and/or customized voltage thresholds and/or gate lengths and/or having a default functionality. The presence or lack of any particular one of these aspects of the disclosure in a given IC is not viewed as essential to the function of the IC.
[0043] Various embodiments of the invention have been presented above. However, the invention is not intended to be limited to the specific embodiments presented, which have been presented for purposes of illustration. Rather, the invention extends to functional equivalents as would be within the scope of the appended claims. Those skilled in the art, having the benefit of the teachings of this specification, may make numerous modifications without departing from the scope and spirit of the invention in its various aspects.

中文:
[0001]本发明的各方面可以涉及结构化集成电路(ICs)的设计和制造,所述结构化集成电路的设计和制造还可以具有高度可配置性。各个方面可以涉及结构化专用集成电路(ASICs)。
[0002]结构化ASIC,或一般而言的IC,可以具有可以在初始制造过程中制造并保存在库存中的预制元件的组合。然后,在一个或更多个进一步的制造过程中,元件可以互连以形成电路或者可以通过例如掩膜来进行定制。这样的互连和定制可以产生更大的灵活性,其体现在所产生的IC可以针对具体的客户应用而进行定制,或者可以被定制为具有例如高速、低功率等的特性。这种IC生产方法可以获得在广泛的器件和/或多种客户应用上摊销非经常性工程(NRE)成本的能力。该方法也可以使从流片到封装芯片的产量提高和/或制造时间减少。
[0003]虽然可能存在设计和制造结构化、可配置IC的一些方法,但是改进现有技术,以便获得更大的灵活性并且/或者进一步改进(针对其所要实现的目标而言的)产生的IC的特性是可取的。
[0004]本发明的各个方面可以涉及可用于增加可定制IC设计的灵活性和/或效率的技术。这样的技术可以包括(例如,但不限于)使用多个可定制的通孔层和/或定制器件中的电压阈值和/或定制一个或更多个金属层。这样的对一个或更多个金属层的定制可以包括在一个或更多个金属层内去除不使用的金属并且/或者重新对金属布线。
[0006]图1示出了根据本发明的各个方面的,包括多个金属层和通孔层的器件的示例;
[0007]图2示出了根据本发明的各个方面的,包括多个金属层和可定制通孔层的器件的进一步的示例;
[0008]图3示出了根据本发明的一个方面的,可以使用图2的示例结构来设计的集成电路的示例;
[0009]图4示出了根据本发明的一个方面的,可以使用图2的示例结构来设计的集成电路的一部分的进一步的示例;
[0010]图5示出了根据本发明的一个方面的逻辑阵列结构的示例;
[0011]图6A和6B示出了根据本发明的一个方面的,逻辑单元的示例的示意图和M2/M3布局;
[0012]图7示出了根据本发明的一个方面的,V4可编程M4/M5布线结构的示例;以及
[0013]图8示出了根据本发明的另一方面的,进一步定制的示例。
[0014]结构化IC可以具有一系列叠加层的形式,在图1中示出了其非限制性示例。在图1的示例中,最低层称为“晶体管层”。该层可以不仅包含晶体管本身,而是还可以包括其它电子元件,例如但不限于电阻器、电容器、电感器、二极管等。此外,晶体管层的元件可以被设计成形成各种类型的功能块和子块,其可以包括不可编程和/或可编程块。例如,额外地或替选地,对于单个基本元件而言,例如晶体管,各种元件可以被组织成功能块/子块,诸如存储器、逻辑器件、缓冲器、放大器、查找表、处理器单元(例如但不限于算术逻辑单元(ALU))、高速串行器/解串器(串行解串器)等(即,“晶体管层”的元件的复杂性可以(由设计者决定)从非常简单改变为高度复杂的)。晶体管层的一些元件也可以包括高度专业化的器件,而不是仅包括通用组件。因此,虽然在本文中被称为“晶体管层”,但是其也可以由其他术语来表示,例如“元件层”、“IP核”等。另外,虽然被称为“晶体管层”,但是其可以包括一个或更多个结构层(例如但不限于硅或其它半导体材料、绝缘材料等的进行各种掺杂的不同层)。此外,晶体管层的元件可以为可进一步定制的,例如,晶体管层的各种元件可以互连以形成功能块和/或这样的模块:其可用于通过可叠加在晶体管层上的各种类型的互连层而进一步互连为另外的功能块。
[0016]接触层CO可以直接叠加在晶体管层上。接触层CO可以包括金属或其他导电物质。接触层CO可以提供接触点,所述接触点可以包括到至少一个进一步的叠加层(例如,一个或更多个金属互连层)的接触点,以用于进一步的互连/连接。晶体管层或晶体管层与接触层CO的组合可以为标准器件,所述标准器件可以大量制造(如果需要的话)以提供可用于形成进一步定制的器件的存货。应当注意,根据本发明的一些方面,接触层CO可以是可定制的。
[0017]在接触层CO之上,可以叠加有一系列交替的金属化层和通孔层。在图1的示例中,层M1-M10是金属层,而层V1-V9是通孔层。虽然示出了十个金属层和九个通孔层,但是本发明不限于此,并且这些层的数量可以是任意的。金属层可以在低层的元件之间提供水平连接,而通孔层可以在各种金属层的互连之间或之中提供垂直连接,其中,“水平”和“垂直”是在图1所示的定向和结构的意义上使用的。注意,在“水平”金属层中,将指向一个方向的金属条称为“水平”,并且将指向垂直方向的金属条称为“垂直”也是常见的用法。除非在本发明中另有规定,否则都应在第一意义(即器件的整体结构的定向)上,而不是在第二意义(即这样的结构的层内结构的定向)上使用“水平”和“垂直”。
[0018]例如,M1可以包含可以互连由晶体管层形成的各种器件/块的金属条的图案,并且所述金属条的图案可以通过接触层CO而连接到晶体管层。M2可以包含用于互连的金属条的另一个图案,为此,V1可以决定由M1形成的哪些互连元件可以通过M2层而进一步互连。在图1的示例中,这种水平(Mn,其中“Mn”表示第n个金属层)连接和垂直(Vm,其中“Vm”表示第m个通孔层)连接的图案可以在整个器件上连续形成,直到层M10。这些金属层和通孔层可以实现晶体管层中或者由晶体管层形成的各种元件与CO层的连接,以形成高度复杂和/或高度定制的器件。
[0019]制造集成电路的方法可以包括形成晶体管层、形成接触层CO以及叠加的金属层和通孔层。如下面将进一步描述的,可以在叠加的金属层和通孔层的形成期间执行定制。
[0020]注意,即使本文所提供的描述可以是针对例如图1和图2所示的结构,并且,术语“垂直”、“水平”、“上”和“下”是针对在这些图中所示的定向而使用的,但是本发明不限于该定向。这样的结构的任何物理定向都是设想中的,并且所述定向不限于图1和图2所示的定向。例如,晶体管层可以位于顶部,金属层和通孔层向下延伸,可以使用“侧向”实施方式等。
[0021]虽然金属层和通孔层可以是固定的,以形成标准的ASIC,但是最近的技术可以允许使用可定制的通孔层,这可以使得能够通过定制互连而从“标准的”或“通用的”基本器件层(即,晶体管层和连接层)来构建定制IC。例如,公司已开发了这样的技术,其可以使用图案化金属层和/或可定制通孔层以从标准器件层获得多种IC。参见例如美国专利第6331733、6331790、6476493、6642744、6756811、6953956、7098691、7157937、7463062、7514959和7550996号,这些专利通过引用并入本文。然而,在这些专利中所公开的技术通常可以允许单个可定制的通孔层;另外,也可以定制这样的单个通孔层,而不需要采用基于掩膜的光学光刻技术,而是可以使用例如美国专利第6953956号中所述的无掩膜电子束工艺而进行定制。
[0023]可以通过使用图1的示例(本发明不限于此;可以有比如图所示的示例更多或更少的金属层和/或通孔层)而允许通孔层V1-V9中的任意或所有的通孔层为可定制的来一般化上述技术,这因此可以允许更大的定制灵活性。此外,金属层M1-M10中的任意或所有的金属层可以是可定制的,这可以提供更进一步的设计灵活性。
[0024]在一个具体的变体中,可以提供一种结构化的、灵活的ASIC(SFASIC),其中图1所示的布局的每个层具有默认状态,并且所产生的芯片可以具有由所有层的默认状态而定义的默认功能;然而,并不一定是这样。然而,制造商可能受益于具有对应于可以频繁售出的器件的默认状态/功能,这可以消除在要生产这样的器件时的对专用定制的需要,这可以反过来减小制造器件的成本。SFASIC可以被定制,并且具体地,一个或更多个特定层可以从其默认状态变化为定制状态。可以使用例如但不限于寄存器传输语言(RTL)的硬件设计语言来指定这种变化;该变化可以由具体的客户来提供。在就此而言的某些方面,仅布局层的任意子集可以从其默认状态变化为定制状态。这可以涉及,例如,将RTL或其他语言翻译(translation)为具体的通孔层或其他的层配置。
[0025]图2示出了其中通孔层中的两个通孔层V2和V4显示为可定制的示例;然而,本发明不限于此,并且可以选择通孔层(和/或金属层)的任意子集以用于定制。图2的该具体示例可以获得M2和M3之间以及M4和M5之间的可定制垂直互连。如该示例所示(本发明不限于此),其余的金属层和通孔层可以是固定的。
[0026]图3示出了IC30的示例,其可以使用图2的通用结构示例来设计。图3示出了IC30的多个不同的功能块。例如,IC30可以包括可测试性设计(DFT)微控制器31,其可以用于管理存储器内建自测(BIST)功能、修复和初始化。该块可以通过V2可编程单元和V2/V4可编程布线结构来创建,其功能因此可以根据客户需求而改变。V2可编程单元可以是逻辑单元,其可以根据其自身是如何被编程的而用于实现不同的逻辑功能。这些单元最初可以为逻辑结构的一部分,如逻辑结构36,其可以包含这样的V2可编程单元,该V2可编程单元可以使用V2和/或V4可编程布线来互连。该IC可以进一步包含串行器/解串器(串行解串器)32,其可以配置用于数千兆位输入/输出(MGIO)。也可以在IC30上配备静态数据存储器33;可以使用可以由微控制器31编程的V2可编程只读存储器(ROM)和/或一次性可编程(OTP)存储器来创建静态数据存储器33。互连可以允许微控制器31访问内容,并允许将内容加载至IC30的核心存储器中。也可以设置一个或更多个延迟发生器34;这样的延迟发生器34可以基于双倍数据速率延迟锁定环(DDRDLL)技术,并且可以例如支持对于类似DDR(DDR-like)接口的频闪移位(strobe shifting)。V4可编程性可用于为延迟发生器34创建掉电选项(power-downoption)。可以设置高速逻辑结构35,其可以支持高速接口;可以使用V2/V4编程来创建该高速逻辑结构。图3的IC30还可以具有存储器块37,其可以包含随机存取存储器(RAM)和/或其他存储器和/或寄存器,其可以是该器件的核心存储器;V2可以用于定制用户界面变量,例如字数和/或位数和/或双抽(double-pumping),其中V4可用于创建掉电选项。可以设置一个或更多个时钟发生器38,其可以使用锁相环(PLL)技术,并且其可以结合V2/V4和/或联合测试行为组织(JTAG)可编程性,以用于改变用户时钟参数。最后,IC30可以包括V2/V4可编程输入/输出(I/O)块39。这样的I/O块39可以通过通孔来编程,以提供例如单个差分I/O,单端I/O对,或同时提供两者。V2/V4可编程性可用于支持不同的标准和/或电压。
[0027]图4示出了根据本发明的一个方面的,可以使用V2/V4可编程性来创建的核心结构40的一部分的进一步的示例。结构40可以包括数控的延迟线(digitally-controlleddelay line,DCDL)41,其可以用于例如支持高速接口。V4可编程性可用于为DCDL41创建掉电选项。结构40可以包括一个或更多个单元(例如,公司的eCellTM逻辑单元。其可以形成单元矩阵42)、D触发器(DFF)(例如,公司的eDFFTM DFF。其可以形成DFF列43)、块RAM44、寄存器文件45等。结构40还可以包括一个或更多个时钟分配单元46,其可以是V2可编程的,并且可以利用可以实现单元和/或高级层时钟脉冲道连接(clock trackconnection)的V2/V4可编程布线结构。该结构可以进一步包括高速逻辑结构47(例如,公司的eiomotifTM)。该高速逻辑结构47可以是可以对高速操作进行优化的顺序和/或组合的V2可编程单元的块,并且其可以包括V2/V4可编程布线结构。最后,结构40可以包括高速平衡结构48,其可以是V2/V4可编程的,并且可以使得能够在I/O和核心逻辑之间创建高度平衡的连接。
[0028]在通过(但不限于)上述示例所示的概括中,即使在相同的IC中,也可以通过相同或不同的定制层来获得不同的功能块。在上述示例中,一些功能块仅涉及V2的定制,一些仅涉及V4的定制,并且一些涉及V2和V4的定制两者。此外,相同功能块的部分可以涉及不同层或层的集合的定制(包括给定功能块的某些部分可以使用非定制层的可能性)。通常,单个IC可以包括多个功能块,并且可以利用定制的通孔层、定制的金属层或者定制的通孔层和定制的金属层两者的不同组合来获得或编程多个功能块中的每个。
[0029]图5示出了逻辑阵列结构的示例,例如,其可以并入例如图4的结构40的结构。在图5中,逻辑单元(例如eCellTM逻辑单元)51可以形成棋板状图案,其可以基于相邻单元之间的基于V2/V4的布线的变体。例如,DFFs(例如eDFFTM DFF)52可以简单地设置在列中。
[0030]图6A和6B示出了根据本发明的一个方面的,逻辑单元的示意图和相应的M2/M3布局。这仅是逻辑单元的一个变体,并且仅提供作为说明性的示例。许多其他的变体也是可能的。
[0031]图7示出了根据本发明的一个方面的,V4可编程M4/M5布线结构的示例。在该具体示例中,M4/M5布线结构显示为逻辑单元(例如eCellsTM)的2×2阵列。V4层通孔可用于将M4和M5的线互连,以创建定制的布线图案。
[0032]如前所述,图3至图7的非限制性示例利用了图2的非限制性示例,其中,V2和V4是仅有的可定制的通孔层。应注意,一些功能块的制造可以利用V2层、V4层或V2层和V4层两者中进行的定制。也就是说,即使使用多个可定制的通孔层,也可以使用可定制通孔层的相同子集或不同子集来创建一些功能块;同样可能的是,一些功能块或功能块的一部分可以不需要定制任何可定制的通孔层,而是可以使用一个或更多个可定制的通孔层的各自部分的默认布局。
[0033]还应强调,可定制通孔层的集合不限于V2和V4(如图2所示,以及如上述示例中所使用的)。通常,两个或更多个通孔层的任何子集都可以是可定制的,并且可以通过对一个或更多个可定制的通孔层的任何子集(包括可定制通孔层的单个通孔层)进行定制来获得用于得到特定功能的定制,并且如上所述,单个IC的功能块可以使用对于可定制通孔层的子集的不同层或层的不同组合的定制。
[0034]例如图2所示的结构具有多个可定制通孔层,所述结构可以通过多种手段来实现。虽然,例如,直接写入(direct-write)电子束对于定制单个可定制通孔层可能是有效的,但是,例如,对于IC的批量生产来说,使用基于掩膜的技术可能更具成本效益。例如,如在美国专利第6,823,499号(其通过引用并入本文)中所讨论的,可以使用基于掩膜的技术来创建具有固定和定制设计组件的IC。定制层可以夹在固定的不可定制层之间,并且该技术可以使用多次以创建例如如图2所示的多个可定制通孔层的组合。如上所述,这样的技术可以用于对分层结构中的通孔层的任何子集进行定制,例如图1和图2所示。
[0035]除了具有可定制通孔层以外,还可以使用晶体管层中的器件的电压阈值(VT)和/或栅极长度变化来定制IC,如图1和图2所示。VT可以影响这样的因素,如速度、功耗和/或成本。在给定的设计中,可以使用低VT(LVT)、常规VT(RVT)或高VT(HVT)器件或其组合。LVT、RVT和HVT可以是相对术语或固定术语。然而,相对于RVT器件,LVT器件可以表现出更高的速度,但是增加了漏电流(并因此增加了功耗),而HVT器件可以表现出较低的速度,但是减小了漏电流。晶体管栅极长度可以类似地影响一类VT器件(LVT,RVT或HVT)内的速度和功率。VT和/或栅极长度可以通过用于制造晶体管层的VT植入(implant)和/或栅极制造掩膜而进行定制。
[0036]根据本发明的一个方面,可以基于时序/速度和/或功率要求来选择VT和栅极长度变化。可以使用基于时序和功率要求的静态时序分析来执行这样的选择。
[0037]根据本发明的另一方面,基于成本的观点,可以将变化限制为VT变化,以便降低成本(与对栅极长度的定制相反)。
[0038]在另一个变体中,根据本发明的多个方面,一个或更多个金属层(例如,如图1和图2所示)也可以是变化的/定制的。在一种特殊情况下,如上文所提及的,金属层的任意子集可以是可定制的,从而可以获得特定的功能;这可以与对通孔层的子集的定制相结合。
[0039]在另一种特殊情况下,各个金属层中的部分可能不会在特定的IC设计中实际使用。尽管如此,这样的部分可以继续传导信号,导致不必要的功耗。因此,根据本发明的另一方面,可以例如通过去除不使用的金属来定制一个或更多个金属层,这可以将互连容量(capacity)仅限制于特定IC设计所需的互连容量,并且可以实现功耗的降低。图8示出了通过去除不需要的金属来进行的这种对金属层的定制的示例。在图8的示例中,与所示的平行金属条相比,金属条81、82和83提供了其中条的长度缩短的示例,以消除金属条81、82和83的不使用的部分。这可以通过在制造定制的金属层之前定制金属层来进行,或者在制造该层之后、但在制造任何随后的(较高的)通孔层和/或金属层之前去除不使用的金属的部分来进行。如果需要,这可以在多个金属层上执行,以将互连容量减至必需的互连容量,并减小动态功耗。
[0040]在进一步的变体中,例如,通过基于定制设计重新分配未使用的层的资源,一个或更多个金属层可以重新布线,这可以优化互连的宽度和间隔。例如,在图8中,附图标记84指示了在图8所示的两个金属层中的两个重新布线的示例。
[0041]除了减小动态功耗之外,或者与减小动态功耗相结合,重新布线和/或消除不需要的金属的结合可以具有额外的益处。例如,去除金属可以使得相邻的金属条之间的间隔85增大。因此,相邻金属条之间的电容可以减少,这可以导致串扰减小并且/或者使得信号传递速度增加。此外,这可以允许一个或更多个金属条的宽度进行一定程度的增大(未示出),这也可以降低相应金属条中的电阻,并且可以使得沿相应金属条的信号传递速度增大。
[0042]上述讨论已呈现了本发明的各个方面。可以设想这些不同的方面可以以任意或所有不同的组合使用。例如,可以在单个器件中一起使用本发明的所有不同方面,或者可以在单个器件中使用这些方面的任意子集。本发明不限于孤立地使用这些不同的方面。例如,单个IC可以使用堆叠结构,如图1和图2所示,其可以具有可以针对功耗、速度或功能和/或定制的电压阈值和/或栅极长度进行定制的、并且/或者具有默认功能的两个或更多个可定制的通孔层和/或至少一个可定制的金属层。在给定的IC中存在或缺失本发明的这些方面中的任何一个特定方面并不应被认为对于IC的功能是关键的。
[0043]上文示出了本发明的各种实施方案。然而,本发明不旨在限制于所示出的具体实施方案,这些具体实施方案是出于说明的目的而示出的。相反,本发明延伸到如应在所附权利要求的范围内的功能等同物。受益于本说明书的指导的本领域技术人员可以在不偏离本发明在其各个方面的范围和精神的情况下进行许多修改。