English:
[0001] In optical communications, an input optical pulse from an optical fiber may be received and converted into an electrical current through an optical module. The optical module may have a high output impedance. A Trans- impedance amplifier (TIA) may be used to convert input current into voltage output, and may generate heat. Because the photo-current from the optical module is very small, and the output impedance of the optical module is very high, the TIA is typically placed right next to the optical module. However, the optical module may be thermally sensitive and suffer drawbacks due to the proximity to the TIA.
[0002] FIG. 1 is a block diagram of a system including a Trans-Impedance Amplifier (TIA) according to an example.
[0003] FIG. 2 is a block diagram of a system including a TIA according to an example.
[0004] FIG. 3A is a block diagram of a TIA according to an example.
[0005] FIG. 3B is a block diagram of a TIA according to an example.
[0006] FIG. 4A is a block diagram of a Continuous-Time Linear Equalizer (CTLE) according to an example.
[0007] FIG. 4B is a block diagram of a CTLE according to an example.
[0008] FIG. 5 is a flow chart based on amplifying an input signal according to an example.
[0009] Example systems provided herein may address heat generation of components in communication with each other, by thermally isolating components. Furthermore, it is possible to avoid transmission line effects for component communication, even when communication involves low current, high impedance components such as photo diodes or other optical components to be amplified. To reduce the reflection from transmission line effects, an amplifier such as an exemplary Trans-Impedance Amplifier (TIA) may include impedance matching to match the transmission line impedance. In addition, example systems may address the very low current pulse from the optical source by exemplary techniques of routing a reference ground next to a signal transmission line, to be delivered into the TIA as a ground reference. Such exemplary interconnect techniques can minimize any noise coupling to the interconnect.
[0010] Thus, the examples described herein enable the integration of a TIA chip into other components, e.g., based on a single application-specific integrated circuit (ASIC) or other solution. Therefore, overall system cost, latency, and power consumption may be reduced. Furthermore, a thermal solution for the TIA (e.g., an ASIC or other chip/package including the TIA) may be addressed separately from a thermal solution for the optical module (which is extremely sensitive to temperatures), thus additional design flexibility and relaxed thermal constraints are enabled for a TIA and its related ASIC/chip implementations. For example a first solution may involve an active heatsink to dissipate heat from the TIA, and a second solution may involve a minimal passive heatsink to dissipate heat from the optical module 130 (or vice versa, depending on a particular optimization for a particular component considered independently).
[0011] FIG. 1 is a block diagram of a system 100 including a Trans- Impedance Amplifier (TIA) 1 10 according to an example. The system 100 also includes an optical module 130 thermally isolated from the TIE 1 10 by transmission line 122 and reference ground 124. The optical module 130 is to receive an input signal 132 that is to be amplied by the TIA 1 10. The TIA 1 10 includes an impedance adjuster 1 12 that is adjustable based on the impedance control 1 14.
[0012] The optical module 130 may be built and packaged in a process separately from the TIA 1 10. For example, the optical; module 130 may include discrete optical components assembled together using a non-silicon assembly process, separately from other electrical components (such as an ASIC to contain the TIA 1 10) through a Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process. The optical components and other features of the optical module 130 may be sensitive to thermal issues. By physically separating the optical module 130, a thermal solution for the optical components may be separately designed and optimized specifically for the optical module 130. In other words, thermal isolation between the optical module 130 and the TIA 1 10 prevents heat from the TIA 1 10 from negatively affecting performance of the optical module 130; the optical module 130 is thermally decoupled from the TIA 1 10. Thermally isolating the optical module 130 avoids a liability of diminishing an operational lifetime and performance of optical elements (e.g., a photodiode or other detector) that are sensitive to heat. For example, an operational lifetime of thermally isolated optical components at 25 degrees Centigrade (25 C) is far longer than operating them at 70 C without thermal isolation.
[0013] The TIA 1 10 is to convert and/or amplify the input signal 132, which may be a small photo-current, to a high-swing voltage, for example. Such amplification may discourage separation between the optical module 130 and TIA 1 10 due to transmission effects, and examples provided herein address such issues to enable separation and thermal isolation. The TIA 1 10 may be built and packaged based on CMOS processes, such as Bipolar junction transistor Complementary Metal-Oxide-Semiconductor (BiCMOS) technology. Thus the TIA 1 10 is compatible with technology used on other components for system 100, such as a main functional ASIC based on CMOS processing. Thus, there is no need to place the TIA 1 10 chip next to the optical module 130 in examples provided herein. However, in an example, the TIA 1 10 may be a separate component from an ASIC that is placed further away from the TIA 1 10 based on a package interconnect and/or a board-level interconnect. Integrating the TIA 1 10 chip into the main ASIC can reduce overall cost, power, and latency by avoiding a need for an additional/separate chip. Even with such integration, examples provided herein can address reflection issues with transmission line effects, avoid coupling noise issues that may arise due to the very small input signal 132 (e.g., a photo-current), and provide thermal isolation for the optical module 130 while integrating the TIA 1 10 design with other components (e.g., integration of the TIA 1 10 on a main ASIC).
[0014] The TIA 1 10 is to receive the input signal 132, which may be a single-ended signal (e.g., based on a light sensor diode that turns on and off). The TIA 1 10 may convert the input signal 132 to a differential signal, so that a differential linear amplifier or other stage downstream of the TIA 1 10 can amplify the output of the TIA 1 10 based on a common mode. Furthermore, a differential signal may be used to mute power supply noise.
[0015] The optical module 130 and TIA1 10 may be based on various packaging solutions. The optical module 130 and TIA 1 10 may be separately packaged, co-packaged, or packaged based on other designs. A co-packaged design may provide the optical module 130 on one package substrate, the TIA 1 10 (e.g., integrated with an ASIC, for example) on another package substrate, and a third package substrate to interconnect the TIA 1 10 and optical module 130. Packaging solutions may provide enough distance between the TIA 1 10 and optical module 130 for thermal isolation, even though a solution may not necessarily involve different packages, and components may be on the same substrate. Package substrate material may include organic package substrates, ceramic package substrates, and other substrates. Various integrated circuit package techniques also may be used to package components together or separately. The packaging solution is to thermally isolate the optical module 130 and TIA 1 10, and that can be achieved based on a common package, by having the TIA 1 10 and optical module 130 on two different packages/substrates that are both on the same board, and other combinations/arrangements. Thus, there is no need for components to be bonded to or otherwise part of the same chip that would tie thermal issues among all those components. Thus, solutions provide a high level of integration
[0016] Separating the TIA 1 10 from the optical module 130 may raise the issue of "transmission line effect," which may depend on the data rate used. In an example, 10 gigabit or 25 gigabit data rates may be used. Conductor losses, dielectric losses, and other characteristics may further be affected by the data rate, and exacerbated by a length of the transmission line. Thus, the reference ground 124 may be routed next to the transmission line 122, for the interconnect between the optical module 130 and the TIA 1 10. Such routing of the reference ground 124 next to the transmission line 122 may avoid inductive coupling between wires.
[0017] A photodetector or other component of the optical module 130 may have a relatively high impedance. To maintain high bandwidth across the transmission line 122, a relatively low impedance may be used for the transmission line 122. Similarly, it is not desirable to match components of the optical module 130 with very high impedance input to avoid negatively affecting bandwidth capability. In an example, a typical photodiode impedance is on the order of K-Ohms of impedance, and typical trace impedance associated with the transmission line 122 (for bandwidth) may be chosen on the order of approximately 50-70 Ohms. Thus, additional techniques may be used for impedance matching.
[0018] Another exemplary technique for mitigating transmission line effects is based on the impedance control 1 14 to control the impedance adjuster 1 12, to adjust an input impedance of the TIA 1 10. The impedance control 1 14 may be, for example, an impedance programmable control logic to control the impedance adjuster 1 12 of the TIA 1 10. The impedance adjuster 1 12 may be formed in the TIA 1 10 package, and may be based on post-silicon trimming or other dynamic adjustment. The impedance control 1 14 and/or impedance adjuster 1 12 may be adjusted based on output of the system 100 (e.g., based on an eye diagram) and controlling the impedance based on the output. In an example, the impedance adjuster 1 12 may be a termination resistor (e.g., a passive feedback resistor that is trimmable). Impedance control and tuning may be used to mitigate any interconnect mismatch, by calibrating the termination resistor. For calibration, an output eye diagram may be examined during testing while adjusting various current to look at voltage changes, or other various techniques (including those that can be implemented post-silicon such as fixed- fused programming).
[0019] The input impedance of the TIA 1 10 may depend on the structure of the TIA 1 10, such as a gain and/or bias of the TIA 1 10 that may be controllable in various examples, whether the TIA 1 10 relies on feedback or not, and other factors that are represented by the impedance adjuster 1 12. The impedance control 1 14 is to be compatible with and interact with the structure and functionality of the impedance adjuster 1 12 and other related aspects of the TIA 1 10. The impedance control 1 14 is shown as separate from the TIA 1 10, although in alternate examples the impedance control 1 14 may be integrated into the TIA 1 10. Thus, the impedance adjuster 1 12 and/or the impedance control 1 14 may provide impedance calibration for the system 100.
[0020] FIG. 2 is a block diagram of a system 200 including a TIA 210 according to an example. The system 200 may be an optical receiver system that includes an optical module 230, interconnect 220, and receiver chip 240. The optical module 230 includes a first capacitor 236 and an optical component 234. The interconnect 220 includes transmission line 222 and reference ground 224. The reference ground 224 may be routed next to the transmission line 222. The receiver chip 240 includes TIA 210, impedance control 214, differential amplifier 242, second capacitor 243, voltage regulator 244, voltage reference 246, and filter 248.
[0021] The interconnect 220 is to separate the optical module 230 from the receiver chip 240 (e.g., an ASIC including the TIA 210) by a distance to provide thermal isolation, e.g., based on a package or board arrangement. An input impedance of the TIA 210 is to match a transmission line impedance (e.g., Z0). In an example, impedance values may include an transmission impedance value of around 50-70 Ohms, for transmitting an input signal from the optical component 234 (photo-detector) on the order of 100 microamps. An output impedance around of the optical component 234 may on the order of 100 KOhms, and may be scaled to avoid noise.
[0022] The optical module 230 may be a purely optical arrangement, such as an optical device having its own packaging. The receiver chip 240 may be part of ASIC, host device, central processing unit (CPU), or other component. The optical module 230 and receiver chip 240 are to connect through the interconnect 220 (transmission line 220), which may be a package. Thus, the interconnect 220 is to provide a distance between the optical module 230 and the receiver chip 240, enabling thermal isolation. The receiver chip 240, such as an ASIC, may be fabricated based on normal silicon processes. Examples enable multiple different processes to be put on the same package, enabling separation of real optical components in the optical module 230 from the electrical/silicon components of the receiver chip 240. Any mismatch between the optical module 230 and receiver chip 240 may be addressed by tuning the termination to match the interconnect 220, to reduce reflection. At the same time, it is possible to avoid heat transfer from the electrical components of the receiver chip 240 to the real optical components of the optical module 230.
[0023] In an example optical module 230, optical component 234 may be a photo-diode reverse-biased with high voltage, shown as VDDH, and reference ground 224. A relatively large first capacitor 236 may be used to form an alternating current (AC) path from VDDH to ground. A second capacitor 243 may be used to provide a complete AC return-loop to avoid any capacitive and inductive noise. The photo-current and reference ground associated with the optical module 230 may be connected to the interconnect 220 package, which has a signal trace for transmission line 222 and a trace for reference ground 224 routed next to the transmission line 222, to minimize any capacitive and inductive noise. The trace impedance may be designed to be as high as possible to optimize signal-to-noise ratio.
[0024] On the receiver chip 240, the transmission line 222 and reference ground 224 are connected to the TIA 210, which may be integrated into and/or isolated from the rest of the receiver chip 240 (e.g., an ASIC). A voltage regulator 244 and voltage reference 246 (e.g., bandgap reference) may be used to provide clean supply voltage (VDD) for the TIA 210. Second capacitor 243 may be connected between the supply voltage VDD for the TIA, and reference ground 224, to provide an AC path to minimize capacitive and inductive coupling noises. The TIA 210 may include impedance control 214 (and an impedance adjuster in the TIA 210, not shown) to trim an input impedance of the TIA 210 to match an impedance of the interconnect 220, to minimize reflection noise. A low-pass filter 248 may be used to extract a direct current (DC) common mode. A differential amplifier 242, such as a continuous-time linear equalizer (CTLE) may be used to convert output of the TIA 210, and DC common mode from the filter 248, if applicable, into a differential output that can be processed by components further downstream, such as other ASICs.
[0025] The voltage regulator 244 is to provide clean voltage, independent of outside voltage variations, to supply the TIA 210. In alternate examples, the voltage reference 246 may be integrated with the voltage regulator 244. A bandgap reference, or other type of reference, may be used to provide the desired voltage. The voltage reference 246 may be a temperature independent reference to provide true and consistent voltage across all environmental conditions.
[0026] The filter 248 (e.g., a low-pass filter (LPF)) may be used to extract a common mode from the output signal of the TIA 210, to be used by the differential amplifier 242 (e.g., linear differential amplifier). Thus, the receiver chip 240 is to convert a single-ended signal to a differential signal. The signal may be DC balanced/averaged, such as by using a LPF to extract the average signal value, for use with the linear differential amplifier 242.
[0027] The differential amplifier 242 may be associated with a high quality common mode noise rejection. In an example, a continuous-time linear equalizer (CTLE) may be used to convert the TIA output and DC common mode into differential output, though other implementations may be used. A linear differential amplifier 242 with a high-pass filter may be used to compensate, for example, high frequency losses due to package routes and any bandwidth limitations of the TIA 210. Thus, the package routing and TIA 210 may be designed to be low bandwidth to have a better signal-to-noise ratio (SNR). The single-end to differential conversion through common mode can further ensure that the signals may be amplified differentially at downstream stages in the system 200.
[0028] The first capacitor 236 and second capacitor 243 may be placed adjacent to the device(s)/component(s) that the capacitors are concerned with, to reduce a distance from the capacitor and the component(s) on which they act. Capacitors may be chosen to have compatible values that are as high as possible, to provide good references for the very low signals involved (e.g., the low-current signals produced by the optical module 230 and transmitted by the interconnect 220. In an example, the first capacitor 236 may be on the order of micro farads, and the second capacitor 243 (which may be located on the voltage regulator 244 itself), may be on the order of 200 pico farads. Thus, the second capacitor 243 may be provided on-chip (e.g., based on silicon fabrication with the receiver chip 240). The optical module 230 may be assembled from discrete components, thus the first capacitor 236 may be chosen as a larger discrete capacitor element that is provided separately.
[0029] FIG. 3A is a block diagram of a TIA 310a according to an example. TIA 310a is to interface with impedance control 314a and interconnect 320a, including transmission line 322a and reference ground 324a, to provide a common mode reference and output "out" based on a high supply reference. TIA 310a includes feedback resistor 350a, first capacitor 336a, second capacitor 343a, transistors M1 -M4, and resistors R1 -R5.
[0030] The TIA 310a may be a feedback-based TIA with input impedance programmability, based on the feedback resistor (Rfb) 350a and the impedance control 314a. In an example, an input impedance Rtia= Rfb/(A+1 ), where A is an open gain associated with the TIA 310a. Rfb is trimmabale by Rtrim_cntl, which may be based on logic or other form of control. Impedance control 314a is to trim Rfb, and may trim Rfb so that Rtia= Z0, where Z0 is associated with a transmission line (not shown) to interface with TIA 310a.
[0032] Impedance control 314a may be used to adjust the impedance adjuster. For example, the input impedance of the TIA 310a may be unknown at assembly prior to activation, so it may be unknown whether the input impedance meets requirements. An output of the TIA 310a may be examined, e.g., by examining an output eye diagram margin and so on as a way to test the TIA 310a performance. In response, a logic control outside the TIA 310a may provide the Rtrim_cntl signal used for impedance control 314a going to the adjustable feedback resistor 350a.
[0033] FIG. 3B is a block diagram of a TIA 310b according to an example. TIA 310b is to interface with impedance control 314b and interconnect 320b, including transmission line 322b and reference ground 324b, to provide a common mode reference and output "out" based on a high supply reference. TIA 310b includes feedback resistor 350b, first capacitor 336b, second capacitor 343b, transistors M1 -M5, and resistors R1 -R5 and Rfb.
[0034] The TIA 310b is an example open-gain TIA with input impedance programmability. An input impedance Rtia= Rtermll(1/gm1 ), and 1/gm1 > 20xRterm. Therefore, Rtia= Rterm, which is trimmable based on impedance control 314b (Rtrim_cntl) so that Rtia= Z0 (impedance of a transmission line). Thus, the TIA 310b may match an impedance of the transmission line, based on impedance control 314a and an impedance adjuster of the TIA 310b, such as termination resistor 350b and other aspects of the TIA 310b. By matching M4 = M5 and R4 = R5, level shifting and common mode output are provided.
[0035] FIG. 4A is a block diagram of a passive Continuous-Time Linear Equalizer (CTLE) 442a according to an example, and FIG. 4B is a block diagram of an active CTLE 442b according to an example. The exemplary CTLEs of FIGS. 4A and 4B may be associated with the differential amplifier described with respect to examples provided above.
[0037] FIG. 5 is a flow chart based on amplifying an input signal according to an example. In block 510, an input signal from an optical module is transmitted to a Trans-Impedance Amplifier (TIA) via a transmission line and a reference ground routed next to the transmission line. The TIA is thermally isolated from the optical module based on the transmission line. In block 520, an input impedance of the TIA is matched to a transmission line impedance, based on an impedance control to control an impedance adjuster. In block 530, the input signal is amplified by the TIA. In block 540, the impedance adjuster is adjusted based on the impedance control using an impedance program control logic.

中文:
[0001]在光通信中,可接收来自光纤的输入光脉冲并通过光模块将其转换成电流。光模块可具有高输出阻抗。跨阻抗放大器(TIA)可用于将输入电流转换成电压输出,并且可产生热量。由于来自光模块的光电流非常小,并且光模块的输出阻抗非常高,因此TIA通常紧邻光模块放置。然而,光模块可能是热敏的,并且由于接近TIA而受到不利影响。
[0002]图1是根据示例的包括跨阻抗放大器(TIA)的系统的框图。
[0003]图2是根据示例的包括TIA的系统的框图。
[0004]图3A是根据示例的TIA的框图。
[0005]图3B是根据示例的TIA的框图。
[0006]图4A是根据示例的连续时间线性均衡器(CTLE)的框图。
[0007]图4B是根据示例的CTLE的框图。
[0008]图5是根据示例基于放大输入信号的流程图。
[0009]本文提供的示例性系统可以通过热隔离彼此通信的各部件,而解决各部件的发热问题。而且,即使当通信涉及被放大的低电流、高阻抗部件(例如光电二极管或其它光学部件)时,也可以避免部件通信的传输线效应。为了降低来自传输线效应的反射,放大器(例如示例性跨阻抗放大器(TIA))可包括用于匹配传输线阻抗的匹配阻抗。另外,通过靠近信号传输线布线参考接地的示例性技术,示例性系统可解决来自光源的非常低的电流脉冲,以将电流脉冲作为接地参考传送到TIA中。这种示例性互连技术能够最小化耦合到互连的任何噪声。
[0010]因此,本文描述的示例使TIA芯片能够集成到其它部件中,例如,基于单一的专用集成电路(ASIC)或其它解决方案。所以,可降低整个系统的成本、延迟以及功耗。而且,可独立于光模块(其对温度非常敏感)的散热解决方案,提供TIA(例如,ASIC或包括TIA的其它芯片/组件)的散热解决方案,从而,针对TIA和与之有关的ASIC/芯片的实施,能够实现额外的设计灵活性和放宽的散热约束。例如,第一解决方案可包含用于驱散来自TIA的热量的主动散热器,第二解决方案可包括用于驱散来自光模块130的最小被动散热器(或者反之亦然,取决于独立的特定部件的特定优化)。
[0011]图1是根据示例的包括跨阻抗放大器(TIA)110的系统100的框图。系统100还包括通过传输线122和参考接地124与TIE 110热隔离的光模块130。光模块130接收将被TIA 110放大的输入信号132。TIA 110包括基于阻抗控制件114可调节的阻抗调节器112。
[0012]可以独立于TIA 110的工艺构造和封装光模块130。例如,光模块130可包括使用非硅装配工艺装配在一起的分散光学部件,这些分散光学部件通过互补金属氧化物半导体(CMOS)制造工艺独立于其它电气部件(例如包含TIA 110的ASIC)。光模块130的光学部件和其它特征对散热问题可能是敏感的。通过物理分离光模块130,可具体针对光模块130分别设计和优化这些光学部件的散热解决方案。换言之,光模块130与TIA 110之间的热隔离防止来自TIA 110的热量对光模块130的性能产生负面影响;光模块130与TIA 110热解耦。热隔离光模块130避免了对热敏感的光学元件(例如光电二极管或其它探测器)运行寿命缩短以及性能降低的可能性。例如,在25摄氏度(25C)热隔离的光学部件的运行寿命比在70C未热隔离的运行的光学部件长的多。
[0013]TIA 110将输入信号132转换和/或放大为例如高摆幅电压,其中输入信号132可以是小的光电流。由于传输效应,这种放大可阻碍光模块130与TIA 110之间的分离,而本文提供的示例解决了这种问题,以实现分离和热隔离。TIA 110可基于CMOS工艺(例如双极结型晶体管互补金属氧化物半导体(BiCMOS)技术)构造和封装。因此,TIA 110与系统100的其它部件(例如基于CMOS工艺的主要功能ASIC)上使用的技术兼容。因此,在本文提供的示例中,没有必要靠近光模块130放置TIA 110芯片。然而,在示例中,基于封装互连和/或板级互连,TIA 110可以是独立于ASIC的部件,其中ASIC远离TIA 110放置。将TIA 110芯片集成到主ASIC中,通过避免需要额外的/分离的芯片,能够降低整个成本、功耗以及延迟。甚至在这种集成的情况下,本文提供的示例能够解决具有传输线效应的反射问题,避免由于非常小的输入信号132(例如,光电流)而可能产生的耦合噪声,以及在将TIA 110设计与其它部件集成(例如,TIA 110集成到主ASIC上)的同时提供光模块130的热隔离。
[0014]TIA 110接收输入信号132,输入信号132可以是单端信号(例如,基于打开和关闭的光传感器二极管)。TIA 110可将输入信号132转换成差分信号,使得差分线性放大器或TIA 110下游的其它级能够基于共模,放大TIA 110的输出。而且,差分信号可用于静音电源噪声。
[0015]光模块130和TIA 110可基于各种封装解决方案。光模块130和TIA 110可分别封装、共同封装或基于其它设计封装。共同封装设计可在一个封装基板上提供光模块130,在另一个封装基板上提供TIA 110(例如,与ASIC集成),以及提供用于使TIA 110和光模块130互连的第三封装基板。即使解决方案不必包括不同的封装,并且部件可位于相同的基板上,但封装解决方案也可在TIA 110与光模块130之间提供足够的距离用于热隔离。封装基板材料可包括有机封装基板、陶瓷封装基板以及其它基板。还可使用各种集成电路封装技术来共同封装部件或者分别封装部件。封装解决方案使光模块130和TIA 110热隔离,并且能够基于普通的封装,通过使TIA 110和光模块130在两个不同封装/基板上(两个不同封装/基板在相同的板上)以及其它组合/布置来实现。因此,部件没有必要被束缚在相同芯片上或者相同芯片的部分上,这会限制所有那些部件之间的散热问题。因此,解决方案提供高等级的集成(例如,使TIA 110能够与其它部件集成),同时由于光模块130和/或其它热敏感部件的热隔离而实现散热解决方案的粒度。
[0016]将TIA 110与光模块130分离可产生“传输线效应”问题,“传输线效应”可取决于使用的数据速率。在示例中,可使用10千兆或25千兆数据速率。导体损耗、介电损耗以及其它特性可进一步受数据速率影响,并且由于传输线的长度而加剧。因此,对于光模块130与TIA 110之间的互连,可靠近传输线122布线参考接地124。这种靠近传输线122布线参考接地124可避免导线之间的电感耦合。
[0017]光模块130的光电探测器或其它部件可具有相对高的阻抗。为了维持传输线122上的高带宽,对于传输线122可使用相对低的阻抗。相似地,用非常高的阻抗输入来匹配光模块130的部件是不可取的,以避免对带宽能力产生负面影响。在示例中,典型的光电二极管阻抗大约是K-欧姆阻抗,并且与传输线122(对于带宽)相关联的典型的走线阻抗可被选择为大约50-70欧姆左右。因此,对于阻抗匹配可使用其它技术。
[0018]用于减轻传输线效应的另一个示例性技术基于用于控制阻抗调节器112的阻抗控制件114,以调节TIA 110的输入阻抗。阻抗控制件114例如可以是用于控制TIA 110的阻抗调节器112的阻抗可编程控制逻辑。阻抗调节器112可形成在TIA 110封装中,并且可基于后硅调整或其它动态调节。可基于系统100的输出(例如,基于眼图)以及基于输出控制阻抗,来调节阻抗控制件114和/或阻抗调节器112。在示例中,阻抗调节器112可以是终端电阻器(例如,可调整的被动反馈电阻器)。通过校准终端电阻器,阻抗控制和谐调可用于缓和任何互连不匹配。针对校准,可在测试期间同时调节不同电流以观察电压变化,或其它不同技术(包括那些能够后硅执行的技术,例如固定融合编程),检测输出眼图。
[0019]TIA 110的输入阻抗可取决于TIA 110的结构,例如在各种示例中可控制的TIA 110的增益和/或偏置、TIA 110是否依赖反馈以及由阻抗调节器112代表的其它因素。阻抗控制件114与阻抗调节器112的结构和功能以及TIA 110的其它相关的方面兼容且交互。阻抗控制件114被示出为与TIA 110分离,不过在可替代的示例中,阻抗控制件114可集成到TIA 110中。因此,阻抗调节器112和/或阻抗控制件114可提供系统100的阻抗校准。
[0020]图2是根据示例的包括TIA 210的系统200的框图。系统200可以是包括光模块230、互连体220和接收器芯片240的光接收器系统。光模块230包括第一电容器236和光学部件234。互连体220包括传输线222和参考接地224。参考接地224可靠近传输线222布线。接收器芯片240包括TIA 210、阻抗控制件214、差分放大器242、第二电容器243、稳压器244、电压参考246和滤波器248。
[0021]互连体220例如基于封装或板布置,将光模块230和接收器芯片240(例如,包括TIA 210的ASIC)分开一距离,以提供热隔离。TIA 210的输入阻抗匹配传输线阻抗(例如,Z0)。在示例中,阻抗值可包括大约50-70欧姆的传输阻抗值,以传输来自光学部件234(光电探测器)的大约100微安的输入信号。光学部件234周围的输出阻抗可大约是100K欧姆,并且可缩放以避免噪声。
[0022]光模块230可以是纯粹的光学布置,例如具有自身封装的光学装置。接收器芯片240可以是ASIC的部分、主设备、中央处理单元(CPU)或其它部件。光模块230和接收器芯片240通过互连体220(传输线222)连接,其可以是一个封装件。因此,互连体220提供光模块230与接收器芯片240之间的距离,实现热隔离。可基于正常的硅工艺制造接收器芯片240(例如ASIC)。示例使能够对相同的封装执行多个不同的工艺,实现光模块230中实际的光学部件与接收器芯片240的电气/硅部件的分离。通过谐调终端以匹配互连体220,可解决光模块230与接收器芯片240之间的任何不匹配,以降低反射。同时,可以避免从接收器芯片240的电气部件到光模块230的实际的光学部件的热传送。
[0023]在示例性光模块230中,光学部件234可以是具有高电压(如示出的VDDH)和参考接地224的反向偏置光电二极管。相对大的第一电容器236可用于形成从VDDH到地的交流(AC)路径。第二电容器243可用于提供完整的AC回路,以避免任何电容噪声和电感噪声。光电流以及与光模块230相关联的参考接地可被连接到互连体220的封装,其具有传输线222的信号走线和靠近传输线222布线的参考接地224的走线,以最小化任何电容噪声和电感噪声。可将走线阻抗设计得尽可能的高,以优化信噪比。
[0024]在接收器芯片240上,传输线222和参考接地224被连接到TIA 210,TIA 210可集成到接收器芯片240(例如,ASIC)剩余的部分中和/或与接收器芯片240剩余的部分隔离。稳压器244和电压参考246(例如,带隙基准)可用于为TIA 210提供净化供给电压(VDD)。第二电容器243可连接在TIA的供给电压VDD与参考接地224之间,以提供AC路径,从而最小化电容耦合噪声和电感耦合噪声。TIA 210可包括阻抗控制件214(以及TIA 210中的阻抗调节器,未示出),用于调整TIA 210的输入阻抗,来匹配互连体220的阻抗,从而最小化反射噪声。低通滤波器248可用于提取直流(DC)共模。如果适合,差分放大器242(例如连续时间线性均衡器(CTLE))可用于将TIA 210的输出以及来自滤波器248的DC共模转换成能够进一步被下游部件(例如其它ASIC)处理的差分输出。
[0025]稳压器244提供净化电压(独立于外部电压变化)以供给TIA 210。在可替代的示例中,电压参考246可与稳压器244集成。带隙基准,或其它类型的基准可用于提供期望的电压。电压参考246可以是与温度无关的参考,以在所有环境条件下提供真实且一致的电压。
[0026]滤波器248(例如,低通滤波器(LPF))可用于从TIA 210的输出信号提取将由差分放大器242(例如,线性差分放大器)使用的共模。因此,接收器芯片240将单端信号转换成差分信号。可以对该信号进行DC平衡/求平均(例如通过使用LPF提取平均信号值),以与线性差分放大器242一起使用。
[0027]差分放大器242可与高质量共模噪声抑制相关联。在示例中,可利用连续时间线性均衡器(CTLE)将TIA输出和DC共模转换成差分输出,不过也可利用其它实现方式。具有高通滤波器的线性差分放大器242可用于例如补偿由于封装布线和TIA 210的任意带宽限制而导致的高频损耗。因此,封装布线和TIA 210可被设计为低带宽,以具有更好的信噪比(SNR)。通过共模的单端到差分转换能够进一步确保信号在系统200中的下游级可被差分放大。
[0028]第一电容器236和第二电容器243可邻近与电容器有关的设备/部件放置,以减小电容器与电容器对其起作用的部件之间的距离。电容器可被选择为具有尽可能高的兼容值,以为所涉及的非常低的信号(例如由光模块230产生且由互连体220传输的低电流信号)提供良好参考。在示例中,第一电容器236可以是大约几个微法拉,并且第二电容器243(其可位于稳压器244自身上)可以是大约200皮法拉。因此,第二电容器243可片上提供(例如,基于接收器芯片240的硅制造)。光模块230可由分散的部件组装而成,因此,第一电容器236可被选择为单独提供的较大的分散电容器元件。
[0029]图3A是根据示例的TIA 310a的框图。TIA 310a与阻抗控制件314a以及包括传输线322a和参考接地324a的互连体320a相连接,以提供共模参考并基于高电源参考输出“out”。TIA 310a包括反馈电阻器350a、第一电容器336a、第二电容器343a、晶体管M1-M4以及电阻器R1-R5。
[0030]基于反馈电阻器(Rfb)350a和阻抗控制件314a,TIA 310a可以是具有输入阻抗可编程性的基于反馈的TIA。在示例中,输入阻抗Rtia=Rfb/(A+1),其中A是与TIA 310a相关联的开放增益(open gain)。Rfb通过Rtrim_cntl是可调整的,Rtrim_cntl可以是基于逻辑或者其它形式的控制。阻抗控制件314a用于调整Rfb,并且可调整Rfb使得Rtia=Z0,其中Z0与连接到TIA 310a的传输线(未示出)相关联。
[0032]阻抗控制件314a可用于调节阻抗调节器。例如,在激活之前的装配期间,TIA310a的输入阻抗可能是未知的,因此输入阻抗是否满足需要可能是未知的。可检测TIA 310a的输出,例如,通过检测输出眼图幅度等作为测试TIA 310a性能的方式。作为回应,TIA 310a外部的逻辑控制可提供用于阻抗控制件314a的、至可调节反馈电阻器350a的Rtrim_cntl信号。
[0033]图3B是根据示例的TIA 310b的框图。TIA 310b与阻抗控制件314b以及包括传输线322b和参考接地324b的互连体320b相连,以提供共模参考,并基于高电源参考输出“out”。TIA 310b包括反馈电阻器350b、第一电容器336b、第二电容器343b、晶体管M1-M5以及电阻器R1-R5和Rfb。
[0034]TIA 310b是具有输入阻抗可编程性的示例性开放增益TIA。输入阻抗Rtia=Rterm||(1/gm1),并且1/gm1>20×Rterm。因此,Rtia=Rterm,Rterm基于阻抗控制件314b(Rtrim_cntl)可调整,使得Rtia=Z0(传输线的阻抗)。因此,基于阻抗控制件314a和TIA 310b的阻抗调节器,例如终端电阻器350b和TIA 310b的其它方面,TIA 310b可匹配传输线的阻抗。通过匹配M4=M5以及R4=R5,提供电平位移和共模输出。
[0035]图4A是根据示例的无源连续时间线性均衡器(CTLE)442a的框图,图4B是根据示例的有源CTLE 442b的框图。图4A和图4B的示例性CTLE可与相对于上面提供的示例描述的差分放大器相关联。
[0037]图5是根据示例的基于放大输入信号的流程图。在框510,经由传输线和靠近传输线布线的参考接地,将来自光模块的输入信号发送到跨阻抗放大器(TIA)。TIA基于传输线与光模块热隔离。在框520,基于用于控制阻抗调节器的阻抗控制件,使TIA的输入阻抗与传输线的阻抗匹配。在框530,通过TIA放大输入信号。在框540,基于使用阻抗程序控制逻辑的阻抗控制件,调节阻抗调节器。