English:
[0001] The present invention relates to the field of enhancement mode gallium nitride (GaN) transistors. More particularly, the invention relates to an enhancement mode GaN transistor with a compensated GaN layer or a semi-insulating GaN layer below the gate contact and above the barrier layer.
[0002] Gallium nitride (GaN) semiconductor devices are increasingly desirable for power semiconductor devices because of their ability to carry large current and support high voltages. Development of these devices has generally been aimed at high power/high frequency applications. Devices fabricated for these types of applications are based on general device structures that exhibit high electron mobility and are referred to variously as heteroj unction field effect transistors (HFET), high electron mobility transistors (HEMT), or modulation doped field effect transistors (MODFET). These types of devices can typically withstand high voltages, e.g., 100 Volts, while operating at high frequencies, e.g., 100 kHz- 10 GHz.
[0003] A GaN HEMT device includes a nitride semiconductor with at least two nitride layers. Different materials formed on the semiconductor or on a buffer layer causes the layers to have different band gaps. The different material in the adjacent nitride layers also causes polarization, which contributes to a conductive two dimensional electron gas (2DEG) region near the junction of the two layers, specifically in the layer with the narrower band gap.
[0004] The nitride layers that cause polarization typically include a barrier layer of AlGaN adjacent to a layer of GaN to include the 2DEG, which allows charge to flow through the device. This barrier layer may be doped or undoped. Because the 2DEG region exists under the gate at zero gate bias, most nitride devices are normally on, or depletion mode devices. If the 2DEG region is depleted, i.e. removed, below the gate at zero applied gate bias, the device can be an enhancement mode device. Enhancement mode devices are normally off and are desirable because of the added safety they provide and because they are easier to control with simple, low cost drive circuits. An enhancement mode device requires a positive bias applied at the gate in order to conduct current.
[0005] FIG. 1 illustrates a conventional enhancement mode GaN transistor device 100. Device 100 includes substrate 101 that can be composed of silicon (Si), silicon carbide (SiC), sapphire, or other material, transition layers 102 typically composed of AlN and AlGaN that is about 0.1 to about 1.0 μm in thickness, buffer material 103 typically composed of GaN that is about 0.5 to about 10 μm in thickness, barrier material 104 typically composed of AlGaN where the Al to Ga ratio is about 0.1 to about 0.5 with thickness from about 0.005 to about 0.03 μm, p-type AlGaN 105, heavily doped p-type GaN 106, isolation region 107, passivation region 108, ohmic contact metals 109 and 110 for the source and drain, typically composed of Ti and Al with a capping metal such as Ni and Au, and gate metal 111 typically composed of a nickel (Ni) and gold (Au) metal contact over a p-type GaN gate.
[0006] There are several disadvantages of the conventional GaN transistors shown in FIG. 1. One problem is that the leakage current of the gate contact during device conduction is very high due to gate charge injection.
[0007] It therefore would be desirable to provide a MISFET, particularly a GaN transistor, that does not leak current during device conduction and that is easier to manufacture.
[0008] The present invention is directed to a MISFET, such as a GaN transistor, with low gate leakage. In one embodiment, the gate leakage is reduced with a compensated GaN layer below the gate contact and above the barrier layer. In another embodiment, the gate leakage is reduced by employing a semi-insulating layer below the gate contact and above the barrier layer.
[0009] FIG. 1 is a cross-section of a prior art transistor.
[0010] FIG. 2 is a transistor according to an embodiment described herein.
[0011] FIG. 3 is a cross-sectional view at a stage of processing.
[0012] FIG. 4 is a cross-sectional view at a stage of processing subsequent to that shown in FIG. 3.
[0013] FIG. 5 is a cross-sectional view at a stage of processing subsequent to that shown in FIG. 4.
[0014] FIG. 6 is a cross-sectional view at a stage of processing subsequent to that shown in FIG. 5.
[0015] FIG. 7 is a cross-sectional view at a stage of processing subsequent to that shown in FIG. 6.
[0016] FIG. 8 is a cross-sectional view at a stage of processing subsequent to that shown in FIG. 7.
[0017] FIG. 9 is a cross-sectional view at a stage of processing subsequent to that shown in FIG. 8.
[0018] FIG. 10 is a transistor according to an embodiment described herein.
[0019] FIG. 11 is a cross-sectional view at a stage of processing subsequent to that shown in FIG. 6.
[0020] FIG. 12 is a cross-sectional view at a stage of processing subsequent to that shown in FIG. 11.
[0021] FIG. 13 is a cross-sectional view at a stage of processing subsequent to that shown in FIG. 12.
[0022] FIG. 14 is a transistor according to an embodiment described herein.
[0023] FIG. 15 is a cross-sectional view at a stage of processing subsequent to that shown in FIG. 11.
[0024] FIG. 16 is a transistor according to an embodiment described herein.
[0025] FIG. 2 shows a MISFET in the form of GaN transistor 1 according to an embodiment of the present invention. GaN transistor 1 is formed on a substrate 31 that may comprise, for example, silicon Si, silicon carbide SiC or sapphire. Over and in contact with the substrate 31 are transition layers 32. Transition layers 32 may comprise, for example, AlN or AlGaN, with a thickness of between 0.1 to l.Oμm. A buffer layer 33 separates the transition layers 32 from a barrier layer 34. The buffer layer 33 is preferably formed of InAlGaN with any concentration of In and Al (including 0% In and/or Al) and has a thickness between 0.5 and 3μm. The barrier layer 34 is formed of AlGaN and has a thickness between 0.005 and 0.03μm and an Al percentage of about 10% to 50%. Source and drain contacts 35, 36 are disposed over the barrier layer. Source and drain contacts are formed of Ti or Al with a capping metal such as Ni and Au or Ti and TiN. A gate contact 37, formed of for example, Ta, Ti, TiN, W, or WSi2, and having a thickness of between 0.05 and l.Oμm, is provided between the source and drain contacts. In accordance with the present invention, a compensated semiconductor layer 38 is formed over the barrier layer 34 and under the gate contact 37. Compensated semiconductor layer 38 preferably comprises AlGaN or GaN with a deep level passivated p-type impurity such as, for example, Mg, Zn, Be, Cd, or Ca. Buffer layer 33 and barrier layer 34 are made of a III Nitride material. A III Nitride material can be composed of InxAIyGa^ _x_yN where x + y < 1.
[0026] Advantageously, the high doping level of compensated layer 38 leads to enhancement mode devices. In addition, using a compensated semiconductor layer 38 leads to low gate leakage during device operation. Finally, the insulating nature of compensated layer 38 reduces the gate capacitance of the device.
[0027] Figures 3-9 describe an example method of manufacturing the GaN transistor 1 shown in FIG. 2. Referring to FIG. 3, the first step is to provide a substrate 31. Referring to FIG. 4, the next step is to nucleate and grow transition layers 32 on top of the substrate 31. Referring to FIG. 5, the next step is to grow a buffer layer 33 over the transistor layer 32. Referring to FIG. 6, the next step is to grow a barrier layer 34 over the buffer layer 33.
[0028] Referring to FIG. 7, the next step is to grow a compensated semiconductor layer 38 over the barrier layer 34. Referring to FIG. 8, the next step is to deposit a gate contact 37 on the compensated semiconductor layer 38. Referring to FIG. 9, the next step is to apply a gate photo mask to etch away the gate contact layer 37, and to etch away the compensated semiconductor layer 38, except the portion beneath gate contact layer 37. The gate photo resist mask is then removed. An additional hydrogen passivation can be performed by exposing the device to ammonia or hydrogen plasma at a high temperature. The final step is to provide the source and drain ohmic contacts 35, 36 over the barrier layer 34, which results in the finished GaN transistor 1 shown in FIG. 2.
[0029] The critical step in the above process that differentiates the device of the present invention from the prior art device (FIG. 1) is the passivation of a p-type impurity using hydrogen. The passivation leads to two differences. First, in GaN transistor 1, the compensated semiconductor layer 38 is a highly compensated semi -insulating material, while in GaN transistor 100 of the prior art, layer 105 is a conductive p-type material. Second, the capacitance of the gate electrode to channel layer is reduced in the present invention as compared to the prior art.
[0030] FIG. 10 shows a GaN transistor 2 according to a second embodiment of the present invention. GaN transistor 2 is similar to GaN transistor 1 (FIG. 2), except that GaN transistor 2 has a semi-insulating layer 39 in place of the compensated semiconductor layer 38 (FIG. 2). Semi-insulating layer 39 may comprise, for example, AlGaN or GaN, with deep level impurity atoms, for example, C, Fe, Mn, Cr, V, or Ni. Additionally, a GaN transistor may have both a semi- insulating layer and a compensated semiconductor layer.
[0031] The second embodiment of the invention has the same advantages as the first embodiment. The high doping of semi-insulating layer 39 leads to enhancement mode devices, the semi-insulating layer 39 leads to low gate leakage during device operation, and the insulating nature of semi-insulating 39 reduces the gate capacitance of the device. In addition, the performance of the device of the second embodiment is not as sensitive to future processing steps involving hydrogen and/or high temperatures.
[0032] The method of manufacturing GaN transistor 2 is the same as the method of manufacturing GaN transistor 1 for the steps shown in FIGS. 3-6. Referring to FIG. 11, the next step in the production of the second embodiment, after the step shown in FIG.6, is the growth of semi-insulating layer 39 incorporating impurity atoms.
[0033] Referring to FIG 12, the next step is to deposit a gate contact layer 37 on the semi-insulating layer 39. Referring to FIG. 13, the next step is to apply a photo mask to etch away the gate contact layer 37, and to etch away the semi-insulating layer 39, except the portion under gate contact layer 37. The photo resist mask is then removed. The next step is to provide the source and drain ohmic contacts 35, 36 over the barrier layer 34 which results in the finished device 2 shown in FIG. 10.
[0035] Figure 14 shows a GaN transistor 3 according to the third embodiment of the present invention. GaN transistor 3 is similar to GaN transistor 2, except that a confinement layer is placed above the semi-insulating layer and below the gate contact layer. This confinement layer can be composed of AlGaN, SiN, SiO2, or other insulating material.
[0036] The method of manufacturing GaN transistor 3 is the same as the method of manufacturing GaN transistor 1 for steps shown in FIGS. 3-6 and GaN transistor 2 for the step shown in FIG. 11. Referring to FIG. 15, the next step is the deposition of an insulating confinement layer 40.
[0037] The third embodiment has the advantage of further reduced gate leakage compared to embodiment 1 or embodiment 2. The disadvantage is a further reduction in conductivity when the device is turned on by applying a positive voltage to the gate contact. A unique advantage of the third embodiment is the creation of a variable threshold voltage device. The confinement layer thickness can be adjusted such that very little leakage occurs under normal operating voltages, such as when the device is turned on and off, usually at 5V applied to the gate for on and OV applied to the gate to turn the device off. However, at higher biases, current can penetrate through the confinement layer and charge the semi-insulating GaN layer. This charge is then trapped between the barrier layer and the confinement layer. This trapped charge leads to a shift in the voltage at which the device turns on and off. By appropriate application of gate voltage, the device can be changed to a depletion mode device, such that it is on at OV on the gate. Alternatively, the device can be changed to an enhancement mode device that requires more than the gate drive to turn on, effectively making an open circuit. These two types of devices can be useful when programming an integrated circuit that controls a GaN FET with integrated gate drive.
[0038] FIG. 16 shows a GaN transistor 4 according to a fourth embodiment of the present invention. GaN transistor 4 is similar to GaN transistor 2, except that it has a spacer layer 49 beneath semi-insulating layer 48 and above barrier layer 44. Associated with spacer layer 49, which is a low Mg region, is a doping offset thickness. The low Mg concentration near the barrier layer reduces the back diffusion into the barrier layer.

中文:
[0001]本发明涉及增强型氮化镓(GaN)晶体管的领域。尤其,本发明涉及一种具有在门触点下方且在阻挡层上方的补偿GaN层或者半绝缘GaN层的增强型GaN晶体管。
[0002]对于功率半导体器件,氮化镓(GaN)半导体器件的需求日益增加,这是由于它们能够承载大电流并且支持高电压的能力。这些器件的发展通常旨在进行高功率/高频应用。为这些应用类型而制造的器件基于展示高电子迁移率的通用器件结构,并且这些器件被称为异质结场效应晶体管(HFET)、高电子迁移率晶体管(HEMT)或者调制掺杂场效应晶体管(MODFET)等各种名称。这些类型的器件通常可以经受高电压,例如100伏特,同时在高频下运行,例如100kHz-10GHz。
[0003]GaN HEMT器件包括具有至少两个氮化物层的氮化物半导体。形成在该半导体或缓冲层上的不同材料使得这些层具有不同的带隙。相邻氮化物层中的不同材料还引起极化,这有助于在两层接合处附近,尤其在具有较窄带隙的层中形成导电二维电子气(2DEG)区。
[0004]引起极化的这些氮化物层通常包括临近GaN层的AlGaN阻挡层,以包括2DEG,其允许电荷流经器件。该阻挡层可以是掺杂或无掺杂的。由于在零栅偏压下门极下方存在2DEG区,所以大部分氮化物器件是常开型或者是耗尽型器件。如果在施加零栅偏压时在门极下方2DEG区被耗尽,即被移除,则该器件可以是增强型器件。增强型器件是常关型,并且由于它们提供的附加安全性以及它们更易于使用简单低成本的驱动电路进行控制,因而符合需要。为了传导电流,增强型器件需要在门极施加正偏压。
[0005]图1示出了常规增强型GaN晶体管器件100。器件100包括由硅(Si)、碳化硅(SiC)、蓝宝石或其他材料形成的基底11,通常由AlN和AlGaN形成的厚度为约0.1至约1.0μm的过渡层102,通常由GaN形成的厚度为约0.5至约10μm的缓冲材料103,通常由AlGaN形成的厚度从约0.005至约0.03μm的阻挡材料104,其中Al和Ga比例为约0.1至约0.5,p型AlGaN 105,高度掺杂的p型GaN 106,绝缘区107,钝化区108,用于源极和漏极、通常由具有诸如Ni和Au的封盖金属的Ti和Al形成的欧姆触点金属109和110,以及通常由位于p型GaN门极上方的镍(Ni)和金(Au)金属触点形成的门金属111。
[0006]图1中所示的常规GaN晶体管存在多个缺点。一个问题是由于门极电荷输入,在器件导电期间门极触点的电流泄漏非常高。
[0007]因而需要提供一种在器件导电期间不泄漏电流并且更易于制造的金属绝缘半导体场效应晶体管(MISFET),尤其是GaN晶体管。
[0008]本发明涉及一种具有低门极泄漏的MISFET,如GaN晶体管。在一个实施例中,利用在门触点下方且在阻挡层上方的补偿GaN层减少门泄漏。在另一实施例中,通过采用在门触点下方且在阻挡层上方的半绝缘层减少门泄漏。
[0009]图1是现有技术晶体管的横截面图。
[0010]图2是根据本文所述的一个实施例的晶体管。
[0011]图3是一个处理阶段时的横截面视图。
[0012]图4是在图3中所示处理阶段之后的处理阶段时的横截面视图。
[0013]图5是在图4中所示处理阶段之后的处理阶段时的横截面视图。
[0014]图6是在图5中所示处理阶段之后的处理阶段时的横截面视图。
[0015]图7是在图6中所示处理阶段之后的处理阶段时的横截面视图。
[0016]图8是在图7中所示处理阶段之后的处理阶段时的横截面视图。
[0017]图9是在图8中所示处理阶段之后的处理阶段时的横截面视图。
[0018]图10是根据本文所述的一个实施例的晶体管。
[0019]图11是在图6中所示处理阶段之后的处理阶段时的横截面视图。
[0020]图12是在图11中所示处理阶段之后的处理阶段时的横截面视图。
[0021]图13是在图12中所示处理阶段之后的处理阶段时的横截面视图。
[0022]图14是根据本文所述的一个实施例的晶体管。
[0023]图15是在图11中所示处理阶段之后的处理阶段时的横截面视图。
[0024]图16是根据本文所述的一个实施例的晶体管。
[0025]图2示出了根据本发明一个实施例的采取GaN晶体管1形式的MISFET。GaN晶体管1形成在基底31上,基底31例如可以包括硅Si、碳化硅SiC或蓝宝石。在基底31上并与其接触的是过渡层32。过渡层32例如可以包括AlN或AlGaN,厚度在0.1至1.0μm之间。缓冲层33使得过渡层32与阻挡层34分离。缓冲层33优选由InAlGaN形成,具有任意浓度的In和Al(包括0%In和/或Al),并且厚度在0.5至3μm之间。阻挡层34由AlGaN形成,厚度在0.005至0.03μm之间,并且Al的百分比为约10%至50%。源极和漏极触点35、36设置在阻挡层上。源极和漏极触点由具有诸如Ni和Au或Ti和TiN的封盖金属形成。门极触点37例如由Ta、Ti、TiN、W或WSi2形成,厚度在0.05至1.0μm之间。根据本发明,补偿半导体层38形成在阻挡层34之上且在门极触点37之下。补偿半导体层38优选包括具有深层钝化的p型杂质的AlGaN或GaN,所述杂质诸如Mg、Zn、Be、Cd或Ca。缓冲层33和阻挡层34由III族氮化物材料制成。III族氮化物材料可以包括InxAlyGa1-x-yN,其中x+y≤1。
[0026]有利的是,补偿层38的高度掺杂水平导致形成增强型器件。另外,使用补偿半导体层38导致在器件工作期间的低门极泄漏。最终,补偿层38的绝缘性减小了器件的门极电容。
[0027]图3-图9描述了制造图2中所示的GaN晶体管1的实例方法。参考图3,第一步是提供基底31。参考图4,下一步是使过渡层32在基底31顶部成核和生长。参考图5,下一步是在过渡层32上生长缓冲层33。参考图6,下一步是在缓冲层33上生长阻挡层34。
[0028]参考图7,下一步是在阻挡层34上生长补偿半导体层38。参考图8,下一步是在补偿半导体层38上沉积门极触点层37。参考图9,下一步是施加门极光掩模以蚀刻门极触点层37,并且蚀刻掉除了门极触点层37下方的那部分补偿半导体层38之外的补偿半导体层38。随后移除门极遮光掩模。通过在高温下将器件暴露至氨或氢等离子体,可以执行附加的氢钝化。最后一步是在阻挡层34上提供源极和漏极欧姆触点35、36,这形成了图2中所示的最终GaN晶体管1。
[0029]上述处理中,使得本发明的器件与现有技术器件(图1)不同的关键步骤在于,使用氢对p型杂质的钝化。钝化导致了两个区别。第一,在GaN晶体管1中,补偿半导体层38是高度补偿半绝缘材料,而在现有技术的GaN晶体管100中,层105是导电p型材料。第二,与现有技术相比,在本发明中,门极与沟道层的电容减小。
[0030]图10示出根据本发明第二实施例的GaN晶体管2。GaN晶体管2类似于GaN晶体管1(图2),区别在于GaN晶体管2具有半绝缘层39,代替补偿半导体层38(图2)。半绝缘层39可以包括例如AlGaN或GaN,其具有深度杂质原子,例如,C、Fe、Mn、Cr、V或Ni。此外,GaN晶体管可以具有半绝缘层和补偿半导体层两者。
[0031]本发明的第二实施例具有与第一实施例相同的优点。半绝缘层39的高度掺杂导致形成增强型器件,半绝缘层39导致在器件工作期间的低门极泄漏,并且半绝缘层39的绝缘性减小了器件的门极电容。此外,第二实施例的器件的性能对涉及氢和/或高温的后续处理步骤不敏感。
[0032]就在图3-图6中所示的步骤而言,制造GaN晶体管2的方法与制造GaN晶体管1的方法相同。参考图11,在第二实施例的制造中,在图6所示的步骤之后的下一步,是生长包括杂质原子的半绝缘层39。
[0033]参考图12,下一步是在半绝缘层39上沉积门极触点层37。参考图13,下一步是施加光掩模,以蚀刻门极触点层37,并且蚀刻掉除了门极触点层37下方的那部分半绝缘层39之外的半绝缘层39。随后移除光刻胶掩模。下一步是在阻挡层34上提供源极和漏极欧姆触点35、36,这形成了图10中所示的最终器件2。
[0035]图14示出了根据本发明第三实施例的GaN晶体管3。GaN晶体管3类似于GaN晶体管2,区别在于在半绝缘层上和门极触点层下设置限制层。该限制层可以由AlGaN、SiN、SiO2或其他绝缘材料形成。
[0036]就图3-图6中所示的步骤而言,制造GaN晶体管3的方法与制造GaN晶体管1的方法相同,就图11中所示的步骤而言与制造GaN晶体管2的方法相同。参考图15,下一步是沉积绝缘限制层40。
[0037]第三实施例与实施例1和实施例2相比,优点在于进一步减少了门极泄漏。缺点是进一步减小了当通过向门极触点施加正电压来导通器件时的导电性。第三实施例的独特优点在于形成了可变阈值电压器件。限制层厚度可以调整,从而在正常工作电压下,例如当导通和关闭器件时,发生非常少量的泄漏,通常向门极施加5V以导通器件,向门极施加0V以关闭器件。然而,在较高的偏压下,电流可以穿透限制层,并且对半绝缘GaN层充电。该电荷随后被捕获在阻挡层和限制层之间。该被捕获的电荷导致器件导通和关闭的电压偏移。通过适当地施加门极电压,该器件可以改变成耗尽型器件,从而在门极上施加0V时器件导通。或者,该器件可以改变成增强型器件,其需要大于门极驱动才导通,从而有效地形成断路。当编程控制具有集成门极驱动的GaN FET的集成电路时,这两种类型的器件是有用的。
[0038]图16示出了根据本发明第四实施例的GaN晶体管4。GaN晶体管4类似于GaN晶体管2,区别在于其具有分隔层49,位于半绝缘层48之下且在阻挡层44之上。分隔层49是低Mg区,与分隔层49相关的是掺杂偏移厚度。在阻挡层附近的低Mg浓度减少了向阻挡层的反向扩散。