English:
[0001] This relates in general to scan testing, and in particular to scan testing of semiconductor devices such as integrated circuits (ICs).
[0002] Scan based techniques offer an efficient alternative to achieve high fault coverage compared to the functional pattern based testing. As the design size increases and multi-core SoCs (system-on-chip) becomes essential to drive high speed applications, test data volume and test application time grow unwieldy even in the highly efficient and balanced scan based designs. Scan compression technique is, so far, the best technique for test data volume and test time reduction during pattern execution of scan inserted designs. Few compression techniques that are implemented in SoCs include broadcast or Illinois architecture, muxed and XOR architecture or MISR (multiple input shift register) based compression architecture. A problem in today's power consuming devices is to handle the leakage power. Efforts are made to use ultra-low leakage library (ULL) cells. A ULL cell library based input/output (IO) receives a scan input on an input terminal and generates a scan output on an output terminal. The ULL cell library based IOs have relatively high inertial delay on clock and data path at the output terminal that can reach as high as the order of 30ns. The input terminal of these IOs is not affected by this timing issue because the inertial delay between clock and data path is relatively low. Under such conditions, it is not possible to drive scan operation at higher frequency, such as 30MHz or higher. Even though a very low cost tester (VLCT) can support data to be driven at higher clock frequency, slower scan output is a bottle neck to the operation. Accordingly, scan operation is not executed at optimal frequency resulting in higher test time.
[0003] In described examples of a circuit for testing an integrated circuit, the circuit includes a scan compression architecture driven by a scan clock and generates M scan outputs, where M is an integer. A clock divider is configured to divide the scan clock by k to generate k number of phase-shifted scan clocks, where k is an integer. A packing logic is coupled to the scan compression architecture and generates kM slow scan outputs in response to the M scan outputs and the k number of phase shifted scan clocks. The packing logic further includes M number of packing elements, and each packing element of the M number of packing elements receives a scan output of the M scan outputs. Each packing element includes k number of flip-flops, and each flip-flop of the k number of flip-flops in a packing element receives a scan output of the M scan outputs. Each flip-flop receives a phase-shifted scan clock of the k number of phase-shifted scan clocks, such that each flip-flop generates a slow scan output of the kM slow scan outputs in response to the scan output and the phase-shifted scan clock.
[0004] Another embodiment provides a method of testing, in which k number of phase-shifted scan clocks is generated from a scan clock, where k is an integer. A packing logic generates kM slow scan outputs from M scan outputs. The packing logic includes M number of packing elements, where M is an integer. Each packing element of the M number of packing elements generates k slow scan output in response to a scan output of the M scan outputs and the k number of phase-shifted scan clocks.
[0005] Additionally, an embodiment provides a computing device that includes a processing unit, multiple logic circuits coupled to the processing unit and a testing circuit. The testing circuit is coupled to at least one logic circuit of the multiple logic circuits. The testing circuit includes a scan compression architecture driven by a scan clock and generates M scan outputs, where M is an integer. A clock divider is configured to divide the scan clock by k to generate k number of phase-shifted scan clocks, where k is an integer. A packing logic is coupled to the scan compression architecture and generates kM slow scan outputs in response to the M scan outputs and the k number of phase shifted scan clocks. The packing logic further includes M number of packing elements, and each packing element of the M number of packing elements receives a scan output of the M scan outputs. Each packing element includes k number of flip-flops, and each flip-flop of the k number of flip-flops in a packing element receives a scan output of the M scan outputs. Each flip-flop receives a phase-shifted scan clock of the k number of phase-shifted scan clocks, such that each flip-flop generates a slow scan output of the kM slow scan outputs in response to the scan output and the phase-shifted scan clock.
[0006] FIG. 1 is a schematic of a circuit for testing an integrated circuit (IC).
[0007] FIG. 2 is a schematic of a circuit for testing an integrated circuit (IC), according to an embodiment.
[0008] FIG. 3 is a schematic of a packing logic, according to an embodiment.
[0009] FIG. 4A is a timing diagram of a clock divider, according to an embodiment.
[0010] FIG. 4B is a schematic of a packing logic, according to an embodiment.
[0011] FIG. 5 is a timing diagram of a packing logic, according to an embodiment.
[0013] FIG. 1 is a schematic of a circuit 100 for testing an integrated circuit (IC). The circuit 100 includes IO (input/output) circuits 104, a decompressor 108, scan chains 112, a scan clock 128, a compressor 118, an internal comparator 122 and a status register 126. The IO circuits 104 receive N data inputs 102 from a tester (not shown in FIG. 1), where N is an integer. Examples of testers include very low cost testers (VLCT) and high-end testers. The IO circuits 104 are coupled to the decompressor 108. The decompressor 108 is coupled to the scan chains 112. Each scan chain of the scan chains 112 includes scan cells, such as scan cells 114 of FIG. 1. The scan chains 112 are driven by the scan clock 128. The compressor 118 is coupled to the scan chains 112. The IO circuits 104, the decompressor 108, the scan chains 112 and the compressor 118 together form a scan compression architecture 105. The compressor 118 is coupled to the internal comparator 122. The internal comparator 122 receives an expected scan response input 124 from the tester. The status register 126 is coupled to the internal comparator 122.
[0014] In operation of the circuit 100, the IO circuits 104 receive N data inputs 102 from the tester and generate N scan inputs 106. The decompressor 108 receives the N scan inputs 106 and generates core scan inputs 110 in response to the N scan inputs 106. The core scan inputs 110 are provided to the scan chains 112. Each scan cell 114 of the scan cells shifts a core scan input of the core scan inputs 110 at a frequency of the scan clock 128. The scan chains 112 generate core scan outputs 116, in response to the core scan inputs 110 received by the scan chains 112. The compressor 118 receives the core scan outputs 116 and generates M scan outputs 120 in response to the core scan outputs 116, where M is an integer. The internal comparator 122 receives the M scan outputs 120 from the compressor 118. The internal comparator 122 also receives the expected scan response input 124 from the tester. The internal comparator 122 is configured to compare the M scan outputs 120 and the expected scan response input 124 to generate a test result 125. The test result 125 is stored in the status register 126. The status register 126 is capable of storing the test results in the form of one or more bits. In at least one example, the status register 126 includes one or more flip-flops (such as a D flip-flop) or latches. In each testing cycle, the tester generates a set of bits, which are provided as N data inputs 102 to the scan compression architecture 105, and multiple testing cycles constitute a testing pattern. The test result 125 generated in each testing cycle is stored in the status register 126 and analyzed at the end of each testing pattern.
[0015] In some situations, the internal comparator 122 also receives unknown values (either "0" or "1"), which are termed as masked bits. In those situations, when values in M scan outputs 120 include masked bits, it is excluded from comparison with the expected scan response input 124 by the internal comparator 122. The internal comparator 122 continues to compare the normal logic "1" bits and logic "0" bits for comparison to ascertain the nature (faulty/fault-free) of the integrated circuit that is being tested. However, the use of internal comparator 122 inhibits analysis of test results at the end of each testing cycle, and the test results in circuit 100 are analyzed at the end of the testing pattern. Also, the unknown values are needed to be masked in M scan outputs 120, which add an additional overhead per scan output.
[0016] FIG. 2 is a schematic of a circuit 200 for testing an integrated circuit (IC), according to an embodiment. The circuit 200 includes first IO circuits 204, a decompressor 208, scan chains 212, a compressor 218, a packing logic 222, second IO circuits 226, a scan clock 230 and a clock divider 232. The IO circuits 204 receive N data inputs 202 from a tester (not shown in FIG. 2), where N is an integer. Examples of testers include very low cost testers (VLCT) and high-end testers. The IO circuits 204 are coupled to the decompressor 208. The decompressor 208 is coupled to the scan chains 212. Each scan chain of the scan chains 212 includes scan cells, such as scan cells 214. The scan chains 212 are driven by the scan clock 230. The compressor 218 is coupled to the scan chains 212. The IO circuits 204, the decompressor 208, the scan chains 212 and the compressor 218 together form a scan compression architecture 205. The compressor 218 is coupled to the packing logic 222. The packing logic 222 receives a signal from the clock divider 232. The packing logic 222 is coupled to the IO circuits 226.
[0017] In operation of the circuit 200, the IO circuits 204 receive N data inputs 202 from the tester and generate N scan inputs 206. The decompressor 208 receives the N scan inputs 206 and generates core scan inputs 210 in response to the N scan inputs 206. The core scan inputs 210 are provided to the scan chains 212. The scan chains 212 are driven by the scan clock 230. Each scan cell 214 of the scan cells shifts a core scan input of the core scan inputs 210 at a frequency of the scan clock 230. The scan chains 212 generate core scan outputs 216 in response to the core scan inputs 210 received by the scan chains 212. The compressor 218 receives the core scan outputs 216 and generates M scan outputs 220 in response to the core scan outputs 216, where M is an integer. In one embodiment, M is equal to N. The clock divider 232 is configured to divide the scan clock 230 by k to generate k number of phase-shifted scan clocks, where k is an integer. For example, when frequency of scan clock 230 is 30 MHz, and k is equal to 3, the clock divider generates three phase-shifted scan clocks each of 10MHz. In one embodiment, the phase shift in the scan clocks is a function of k, such as 360° / k. In one embodiment, the phase shift in the scan clocks is 0 degrees, so the generated scan clocks are in same phase. The phase-shift in the clocks is predefined by a user and hardwired in the circuit 200. In at least one example, the clocks are phase shifted by 45, 90 or 180 degrees.
[0018] The packing logic 222 is coupled to the scan compression architecture 205 and generates kM slow scan outputs 224 in response to the M scan outputs 220 and k number of phase-shifted scan clocks. The features and operation of the packing logic 222 are further discussed in connection with FIG. 3. The packing logic 222 is coupled to the IO circuits 226. The IO circuits 226 are configured to generate kM data outputs 228 in response to the kM slow scan outputs 224. The N data inputs 202, the N scan inputs 206 and the M scan outputs 220 operate at a higher frequency, as compared to the kM slow scan outputs 224 and kM data outputs 228. Accordingly, the circuit 200 addresses the issue of handling kM slow scan outputs 224, even when the M scan outputs 220 are received at a faster rate, without loss of data and thereby saving time for testing the integrated circuit. In each testing cycle, the tester generates a set of bits, which are provided as N data inputs 202 to the scan compression architecture 205, and multiple testing cycles constitute a testing pattern. The packing logic 222 allows analysis of test results at the end of each testing cycle. Also, in situations when packing logic 222 receives unknown values (either "0" or "1"), which are termed as masked bits, these masked bits are treated as regular bits and do not add more overhead on the circuit 200.
[0020] FIG. 4A is a timing diagram of a clock divider, according to an embodiment. FIG. 4A shows the timing diagram when a clock divider, such as clock divider 232 (shown in FIG. 2), receives a scan clock (such as scan clock 230) and generates k number of phase-shifted scan clocks, where k is an integer. In at least one example, FIG. 4A shows the phase-shifted scan clocks from the clock divider 232, when k is equal to 3. The clock divider is configured to divide the scan clock by k to generate k number of phase-shifted scan clocks. For example, if the frequency of the scan clock is 30MHz, then the clock divider would generate three phase-shifted scan clocks of 10MHz each. The scan clock 430 is received by the clock divider 232. The clock divider generates phase-shifted scan clock 1 (415a), scan clock 2 (415b) and scan clock 3 (415c). Each scan clock is phase-shifted by 120 degrees. For example, scan clock 2 (415b) is phase-shifted 120 degrees with respect to the scan clock 1(415a) and similarly, scan clock 3 (415c) is phase shifted 120 degrees with respect to the scan clock 2 (415b). In one embodiment, the phase shift in the scan clocks is a function of k, such as 360° / k. In one embodiment, the phase shift in the scan clocks is 0 degrees, so the generated scan clocks are in same phase. The phase-shift in the clocks is predefined by a user and hardwired in the clock divider 232. In at least one example, the clocks are phase shifted by 45, 90 or 180 degrees.
[0022] FIG. 5 is a timing diagram 500 of a packing logic, according to an embodiment. The timing diagram 500 is explained with reference to FIG. 4A, FIG. 4B and packing logic 400. FIG. 5 shows the phase-shifted scan clocks and the slow scan outputs, when k is equal to 3 and M is equal to 4. FIG. 5 shows the timing diagram 500 when a clock divider, such as clock divider 232 (shown in FIG. 2), receives a scan clock 430 and generates phase-shifted scan clock 1 (415a), scan clock 2 (415b) and scan clock 3 (415c). The generation of scan clocks is discussed hereinabove in connection with FIG. 4A. The packing element 405A receives the scan output 420A. The timing diagram 500 shows three slow scan outputs, which are being generated by a packing element, such as packing element 405A in the packing logic 400 (shown in FIG. 4B). The flip-flop 402a receives the scan clock 1(415a) and the scan output 420A and generates a slow scan output 1 (424A1). Similarly, the flip-flop 402b generates a slow scan output 2 (424A2) in response to the scan clock 2(415b) and the scan output 420A. Also, the flip-flop 402c generates a slow scan output (424 A3) in response to the scan clock 3 (415 c) and the scan output 420 A. The timing diagram 500 further shows that for one scan output, the packing element generates three slow scan outputs. The scan output 420 A is received by the packing logic 400 at the frequency of the scan clock 430, but the slow scan outputs (424A1-424A3) are generated at a frequency that is one-third of the frequency of the scan clock 430. Accordingly, each slow scan output is available as an output of the packing logic 400 for three pulses of the scan clock 430, so the packing logic 400 allows analysis of test results at the end of each pulse of clock cycle. The test results at the end of each pulse of clock cycle enable diagnosis of failing scan chain. Accordingly, the packing logic 400 addresses the issue of handling 12 slow scan outputs, even when the four scan outputs are received at a faster rate, without loss of data and thereby saving time for testing the integrated circuit.
[0023] FIG. 6 shows a computing device 600 of an embodiment. The computing device 600 is, or is an integrated circuit incorporated into, a server farm, a computing device with hard-drive, a video recorder, a bluetooth device, a remote control, a keyboard, a mobile communication device (such as a mobile phone or a personal digital assistant), a personal computer, or any other type of electronic system.
[0024] In some examples, the computing device 600 can be a microcontroller, microprocessor or a system-on-chip (SoC), which includes a processing unit 612 such as a central processing unit (CPU). For example, the processing unit 612 can be a CISC-type (complex instruction set computer) CPU, RISC-type (reduced instruction set computer) CPU, or a digital signal processor (DSP). A tester 610 is coupled to the computing device 600. The tester 610 includes logic that supports testing and debugging of the computing device 600 executing the software applications 630. For example, the tester 610 is useful to emulate a defective or unavailable component(s) of the computing device 600. This allows verification of how the component(s), were it (they) actually present on the computing device 600, would perform in various situations (such as how the component(s) would interact with the software applications 630). In this way, the software applications 630 can be debugged in an environment that resembles post-production operation.
[0025] In at least one example, the processing unit 612 includes cache-memory and logic, which store and use information frequently accessed from the tester 610, so the processing unit 612 is responsible for directing complete functionality of the computing device 600. The computing device 600 includes logic circuits 615. At least one of the logic circuits 615 is coupled to a testing circuit 620. The testing circuit 620 is analogous to the circuit 200 in connection and operation. The testing circuit operates in conjunction with the tester 610. The testing circuit 620 addresses the issue of handling kM slow scan outputs, even when the M scan outputs are received at a faster rate, without loss of data and thereby saving time for testing the integrated circuit, where k, M and N are integers. In each testing cycle, the tester 610 generates a set of bits, which are provided as N data inputs to the testing circuit 620, and multiple testing cycles constitute a testing pattern. The testing circuit 620 allows analysis of test results at the end of each testing cycle. Also, in situations when testing circuit 620 receives unknown values (either "0" or "1"), which are termed as masked bits, the testing circuit 620 treats them as regular bits and does not add more overhead on the computing device 600.
[0026] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

中文:
[0001]本申请通常涉及扫描测试,并且特别地,涉及诸如集成电路(IC)的半导体器件的扫描测试。
[0002]基于扫描的技术提供有效的替代物以实现与基于功能模式的测试相比的高故障覆盖。随着设计尺寸增加以及多芯的SoC(片上系统)对于驱动高速应用变得必不可少,测试数据量和测试应用时间甚至是在高效并基于平衡扫描的设计中逐渐变得不实用。目前为止,扫描压缩技术是在扫描插入设计的模式执行期间用于测试数据量和测试时间减少的最佳技术。在SoC上实施的少数压缩技术包括广播或伊利诺(Illinois)体系结构、多路复用的和异或门体系结构、或基于MISR(多输入移位寄存器)的压缩体系结构。在现今的功耗性器件中的问题是处理漏泄功率。做出努力以使用超低漏泄库(ULL)单元。基于ULL单元库的输入/输出(IO)在输入端上接收扫描输入并且在输出端上生成扫描输出。基于ULL单元库的IO在时钟上具有相对高的惯性延迟,和在输出端处的数据路径,该数据路径能够达到高达30ns量级。这些IO的输入端不受该计时问题的影响,因为时钟和数据路径之间的惯性延迟相对较低。在此情况下,不可能在较高的频率下驱动扫描操作,例如30MHz或更高。虽然超低成本测试器(VLCT)能够支持数据在较高的时钟频率下被驱动,但是较慢的扫描输出对于操作是个瓶颈。相应地,扫描操作不在最佳频率下执行,导致较多的测试时间。
[0003]在描述的用于测试集成电路的电路的示例中,该电路包括由扫描时钟驱动的扫描压缩体系结构并生成M个扫描输出,其中M为整数。时钟分频器被配置为将扫描时钟除以k,以生成k个数量的相移扫描时钟,其中k为整数。打包逻辑耦接到扫描压缩体系结构并响应于M个扫描输出和k个数量的相移扫描时钟,生成kM个慢扫描输出。打包逻辑进一步包括M个数量的打包元件,并且M个数量的打包元件的每个打包元件接收M个扫描输出中的扫描输出。每个打包元件包括k个数量的触发器,并且在打包元件中的k个数量的触发器的每个触发器接收M个扫描输出中的扫描输出。每个触发器接收k个数量的相移扫描时钟的相移扫描时钟,致使响应于扫描输出和相移扫描时钟,每个触发器生成kM个慢扫描输出的慢扫描输出。
[0004]另一种实施例提供一种测试的方法,其中k个数量的相移扫描时钟从扫描时钟生成,其中k为整数。打包逻辑从M个扫描输出生成kM个慢扫描输出。打包逻辑包括M个数量的打包元件,其中M为整数。M个数量的打包元件的每个打包元件响应于M个扫描输出的扫描输出和k个数量的相移扫描时钟,生成k慢扫描输出。
[0005]此外,实施例提供一种计算装置,该计算装置包括处理单元、多个逻辑电路和测试电路,该多个逻辑电路耦接到处理单元。测试电路耦接到多个逻辑电路的至少一个逻辑电路。测试电路包括由扫描时钟驱动的扫描压缩体系结构并生成M个扫描输出,其中M为整数。时钟分频器被配置为将扫描时钟除以k,以生成k个数量的相移扫描时钟,其中k为整数。打包逻辑耦接到扫描压缩体系结构并响应于M个扫描输出和k个数量的相移扫描时钟,生成kM个慢扫描输出。打包逻辑进一步包括M个数量的打包元件,并且M个数量的打包元件的每个打包元件接收M个扫描输出中的扫描输出。每个打包元件包括k个数量的触发器,并且在打包元件中的k个数量的触发器的每个触发器接收M个扫描输出中的扫描输出。每个触发器接收k个数量的相移扫描时钟中的相移扫描时钟,致使响应于扫描输出和相移扫描时钟,每个触发器生成kM个慢扫描输出中的慢扫描输出。
[0006]图1是用于测试集成电路(IC)的电路的原理图。
[0007]图2是根据实施例的用于测试集成电路(IC)的电路的原理图。
[0008]图3是根据实施例的打包逻辑的原理图。
[0009]图4A是根据实施例的时钟分频器的时序图。
[0010]图4B是根据实施例的打包逻辑的原理图。
[0011]图5是根据实施例的打包逻辑的时序图。
[0013]图1是用于测试集成电路(IC)的电路100的原理图。电路100包括IO(输入/输出)电路104、解压器108、扫描链112、扫描时钟128、压缩器118、内部比较器122和状态寄存器126。IO电路104从测试器(图1中未示出)接收N个数据输入102,其中N为整数。测试器的示例包括超低成本测试器(VLCT)和高端测试器。IO电路104耦接到解压器108。解压器108耦接到扫描链112。扫描链112的每个扫描链包括扫描单元,例如图1的扫描单元114。扫描链112由扫描时钟128驱动。压缩器118耦接到扫描链112。IO电路104、解压器108、扫描链112和压缩器118一起形成扫描压缩体系结构105。压缩器118耦接到内部比较器122。内部比较器122从测试器接收预期的扫描响应输入124。状态寄存器126耦接到内部比较器122。
[0014]在电路100的操作中,IO电路104从测试器接收N个数据输入并生成N个扫描输入106。解压器108接收N个扫描输入106并响应于N个扫描输入106,生成核心扫描输入110。核心扫描输入110被提供到扫描链112。扫描单元的每个扫描单元114在扫描时钟128的频率下移位核心扫描输入110中的核心扫描输入。响应于由扫描链112接收的核心扫描输入110,扫描链112生成核心扫描输出116。压缩器118接收核心扫描输出116并响应于核心扫描输出116,生成M个扫描输出120,其中M为整数。内部比较器122接收来自压缩器118的M个扫描输出120。内部比较器122也接收来自测试器的预期的扫描响应输入124。内部比较器122被配置为比较M个扫描输出120和预期的扫描响应输入124以生成测试结果125。测试结果125存储在状态寄存器126中。状态寄存器126能够以一个或更多个位的形式存储测试结果。在至少一个示例中,状态寄存器126包括一个或更多个触发器(例如D触发器)或锁存器。在每个测试周期中,测试器生成一组位,其作为N个数据输入102被提供到扫描压缩体系结构105,并且多个测试周期构成测试模式。在每个测试周期中生成的测试结果125被存储在状态寄存器126中并且在每个测试模式结束时被分析。
[0015]在某些情况下,内部比较器122也接收未知值(“0”或“1”),其被称为屏蔽位。在那些情况下,当M个扫描输出120中的值包括屏蔽位时,排除用内部比较器122进行的与预期的扫描响应输入124的比较。内部比较器122继续比较常规逻辑“1”位和逻辑“0”位作为比较,以确定正被测试的集成电路的性质(有故障/无故障)。然而,内部比较器122的使用禁止了在每个测试周期结束时的测试结果的分析,并且电路100中的测试结果在测试模式结束时被分析。并且,未知值需要在M个扫描输出120中被屏蔽,其在每个扫描输出增加附加开销(overhead)。
[0016]图2是根据实施例的用于测试集成电路(IC)的电路200的原理图。电路200包括第一IO电路204、解压器208、扫描链212、压缩器218、打包逻辑222、第二IO电路226、扫描时钟230和时钟分频器232。IO电路204从测试器(图2中未示出)接收N个数据输入202,其中N为整数。测试器的示例包括超低成本测试器(VLCT)和高端测试器。IO电路204耦接到解压器208。解压器208耦接到扫描链212。扫描链212中的每个扫描链包括扫描单元,例如扫描单元214。扫描链212由扫描时钟230驱动。压缩器218耦接到扫描链212。IO电路204、解压器208、扫描链212和压缩器218一起形成扫描压缩体系结构205。压缩器218耦接到打包逻辑222。打包逻辑222从时钟分频器232接收信号。打包逻辑222耦接到IO电路226。
[0017]在电路200的操作中,IO电路204从测试器接收N个数据输入202并生成N个扫描输入206。解压器208接收N个扫描输入206并响应于N个扫描输入206,生成核心扫描输入210。核心扫描输入210被提供到扫描链212。扫描链212由扫描时钟230驱动。扫描单元的每个扫描单元214在扫描时钟230的频率下移位核心扫描输入210中的核心扫描输入。响应于由扫描链212接收的核心扫描输入210,扫描链212生成核心扫描输出216。压缩器218接收核心扫描输出216并响应于核心扫描输出216,生成M个扫描输出220,其中M为整数。在一个实施例中,M等于N。时钟分频器232被配置为将扫描时钟230除以k,以生成k个数量的相移扫描时钟,其中k为整数。例如,当扫描时钟230的频率为30MHz且k等于3时,时钟分频器生成三个相移扫描时钟,每个10MHz。在一个实施例中,扫描时钟中的相移是k的函数,例如360°/k。在一个实施例中,扫描时钟中的相移是0度,所以生成的扫描时钟同相。扫描时钟中的相移由用户预定义并且被硬接线在电路200中。在至少一个示例中,时钟被相移45度、90度或180度。
[0018]打包逻辑222耦接到扫描压缩体系结构205并响应于M个扫描输出220和k个数量的相移扫描时钟,生成kM个慢扫描输出224。关联图3进一步讨论打包逻辑222的特征和操作。打包逻辑222耦接到IO电路226。IO电路226被配置为响应于kM个慢扫描输出224,生成kM个数据输出228。与kM个慢扫描输出224和kM个数据输出228相比,N个数据输入202、N个扫描输入206和M个扫描输出220在较高的频率下操作。相应地,电路200解决处理kM个慢扫描输出224的问题,甚至当在较快速率下接收M个扫描输出220时,而不丢失数据并且从而节省用于测试集成电路的时间。在每个测试周期中,测试器生成一组位,其作为N个数据输入202被提供到扫描压缩体系结构205,并且多路测试周期构成测试模式。打包逻辑222允许在每个测试周期结束时的测试结果的分析。并且,在当打包逻辑222接收未知值(“0”或“1”)(其被称为屏蔽位)的情况下,这些屏蔽位被当做常规位,并且不在电路200上增加更多的开销。
[0020]图4A是根据实施例的时钟分频器的时序图。图4A示出当时钟分频器(例如时钟分频器232(如图2所示))接收扫描时钟(例如扫描时钟230)并生成k个数量的相移扫描时钟(其中k为整数)时的时序图。在至少一个示例中,图4A示出当k等于3时,来自时钟分频器232的相移扫描时钟。时钟分频器被配置为将扫描时钟除以k,以生成k个数量的相移扫描时钟。例如,若扫描时钟的频率为30MHz,那么时钟分频器将生成三个相移扫描时钟,每个10MHz。扫描时钟430由时钟分频器232接收。时钟分频器生成相移扫描时钟1(415a)、扫描时钟2(415b)和扫描时钟3(415c)。每个扫描时钟被相移120度。例如,扫描时钟2(415b)关于扫描时钟1(415a)相移120度,且类似地,扫描时钟3(415c)关于扫描时钟2(415b)相移120度。在一个实施例中,扫描时钟中的相移是k的函数,例如360°/k。在一个实施例中,扫描时钟中的相移是0度,所以生成的扫描时钟同相。时钟中的相移由用户预定义并且被硬接线在时钟分频器232中。在至少一个示例中,时钟被相移45度、90度或180度。
[0022]图5是根据实施例的打包逻辑的时序图500。时序图500根据图4A、图4B和打包逻辑400解释。图5示出当k等于3且M等于4时的相移扫描时钟和慢扫描输出。图5示出当时钟分频器(例如时钟分频器232(如图2所示))接收扫描时钟430并生成相移扫描时钟1(415a)、扫描时钟2(415b)和扫描时钟3(415c)时的时序图500。关联图4A讨论上文的扫描时钟的生成。打包元件405A接收扫描输出420A。时序图500示出三个慢扫描输出,其由打包元件生成,例如打包逻辑400(如图4B所示)中的打包元件405A。触发器402a接收扫描时钟1(415a)和扫描输出420A,并且生成慢扫描输出1(424A1)。类似地,响应于扫描时钟2(415b)和扫描输出420A,触发器402b生成慢扫描输出2(424A2)。并且,响应于扫描时钟3(415c)和扫描输出420A,触发器402c生成慢扫描输出(424A3)。时序图500进一步示出对于一个扫描输出而言,打包元件生成三个慢扫描输出。扫描输出420A在扫描时钟430的频率下由打包逻辑400接收,然而,慢扫描输出(424A1-424A3)在扫描时钟430的频率的三分之一的频率下生成。相应地,对于扫描时钟430的三个脉冲,每个慢扫描输出可用作打包逻辑400的输出,因此打包逻辑400允许在每个时钟周期脉冲结束时分析测试结果。每个时钟周期脉冲结束时的测试结果能够诊断失败的扫描链。相应地,打包逻辑400解决处理12个慢扫描输出的问题,甚至当在较快速率下接收四个扫描输出时,而不丢失数据并且从而节省用于测试集成电路的时间。
[0023]图6示出计算装置600的实施例。计算装置600是或是被并入服务器机群的集成电路、具有硬驱动、视频记录仪、蓝牙器件、远程控制、键盘、移动通信器件(例如移动电话或个人数字助理)的计算装置、个人计算机或任何其他类型的电子系统。
[0024]在某些示例中,计算装置600能够是微控制器、微处理器或片上系统(SoC),其包括处理单元612,例如中央处理单元(CPU)。例如,处理单元612能够是CISC类型(复杂指令集计算机)的CPU、RISC类型(精简指令集计算机)的CPU或数字信号处理器(DSP)。测试器610耦接到计算装置600。测试器610包括支持执行软件应用630的计算装置600的测试和调试的逻辑。例如,测试器610可用于仿真计算装置600的(一个或更多个)缺陷或不可用组件。这允许验证(一个或更多个)组件(如果(一个或更多个)组件实际地存在于计算装置600上)将怎样在各种情况下表现(例如,(一个或更多个)组件将怎样与软件应用630交互)。以此方式,软件应用630能够在类似于后期生产操作的环境中调试。
[0025]在至少一个示例中,处理单元612包括高速缓冲存储器和逻辑,其存储和使用从测试器610频繁地访问的信息,因此处理单元612对指导计算装置600的完全功能性负责。计算装置600包括逻辑电路615。逻辑电路615的至少一个耦接到测试电路620。测试电路620在连接和操作上与电路200类似。测试电路与测试器610共同操作。测试电路620解决处理kM个慢扫描输出的问题,甚至当在较快速率下接收M个扫描输出时,而不丢失数据并且从而节省用于测试集成电路的时间,其中k、M和N为整数。在每个测试周期中,测试器610生成一组位,其作为N个数据输入被提供到测试电路620,并且多个测试周期构成测试模式。测试电路620允许在每个时钟周期结束时分析测试结果。并且,在当测试电路620接收未知值(“0”或“1”)(其被称为屏蔽位)的情况下,测试电路620将这些屏蔽位当做常规位,并且不在计算装置600上增加更多的开销。
[0026]在权利要求的范围内,在所述的实施例中的修改是可能的,并且其他实施例是可能的。