English:
[0001] Portable computing devices (e.g., cellular telephones, smart phones, tablet computers, portable digital assistants (PDAs), portable game consoles, wearable devices, and other battery-powered devices) and other computing devices continue to offer an ever-expanding array of features and services, and provide users with unprecedented levels of access to information, resources, and communications. To keep pace with these service enhancements, such devices have become more powerful and more complex. Portable computing devices now commonly include a system on chip (SoC) comprising a plurality of memory clients embedded on a single substrate (e.g., one or more central processing units (CPUs), a graphics processing unit (GPU), digital signal processors (DSPs), etc.). The memory clients may read data from and store data in an external dynamic random access memory (DRAM) electrically coupled to the SoC via a high-speed bus, such as, a double data rate (DDR) bus.
[0002] Although various memory standards define the protocols and timings with which the SoC may interface with the DRAM, existing system have several disadvantages for selecting optimal bandwidth/frequency operating points. In existing systems, there are generally three degrees of freedom from which the SoC may select the optimal operating points. First, there are silicon various between DRAM suppliers, between different process nodes, and to a large extent between different wafers coming from the same supplier and process node. Second, there are channel variations between platform industrial designs, SoC and DRAM package designs, and radio frequency compliance. Third, various DRAM interface parameter settings (e.g., clock frequency, latency, on-die termination, etc.) may be adjusted.
[0003] Existing systems employ best-effort lumped parameters for these variables, which are designed to provide reliable error-free operation. Such a "one-size-to-fit-all" parameter setting can be wasteful of energy because there may be device samples that outperform the norm and could benefit from optimized settings.
[0004] Accordingly, there is a need for improved systems and methods for customizing DRAM interface parameter settings to enable individual units to expend the least amount of energy and to allow finer granularity of bandwidth/frequency operating points.
[0005] Systems and methods are disclosed for reducing double data rate (DDR) memory power consumption via device-specific customization of DDR interface parameters. One embodiment comprises a method for minimizing double data rate (DDR) power consumption. The method selects one of a plurality of operating points for a DDR interface electrically coupling a DDR memory to a memory controller residing on a system on chip (SoC). The memory controller executes a memory test via the DDR interface at the selected operating point. During the execution of the memory test at the selected operating point, the method determines an optimal value of a setting for one or more DDR interface parameters associated with the DDR interface that minimizes memory power consumption and maintains a predetermined DDR eye margin.
[0006] Another embodiment of a system comprises a double date rate (DDR) memory and a system on chip (SoC). The SoC comprises a memory controller electrically coupled to the DDR memory via a DDR interface. The memory controller is configured to execute a memory test via the DDR interface at one or more of a plurality of operating points. During the execution of the memory test, the memory controller determines an optimal value of a setting for one or more DDR interface parameters associated with the DDR interface that minimizes memory power consumption and maintains a predetermined DDR eye margin.
[0007] In the Figures, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with letter character designations such as " 102 A" or "102B", the letter character designations may differentiate two like parts or elements present in the same Figure. Letter character designations for reference numerals may be omitted when it is intended that a reference numeral to encompass all parts having the same reference numeral in all Figures.
[0008] FIG. 1 is a block diagram of an embodiment of a system for reducing double data rate (DDR) memory power consumption by customizing device-specific DDR interface parameters.
[0009] FIG. 2 is a flowchart illustrating an embodiment of a method for reducing DDR memory power consumption by customizing device-specific DDR interface parameters.
[0010] FIG. 3 is an exemplary graph illustrating memory power consumption at various voltage frequency bins for two different sample devices incorporating the system of FIG. 1.
[0011] FIG. 4 is a flowchart illustrating another embodiment of a method for reducing DDR memory power consumption by customizing device-specific DDR interface parameters during OEM testing.
[0012] FIG. 5 is a table illustrating various exemplary common DDR interface parameters that may be customized to minimize memory power consumption while maintaining a predetermined DDR eye margin.
[0013] FIG. 6 illustrates an embodiment of the physical layer channel coupling the SoC memory controller PHY to the DRAM PHY.
[0014] FIG. 7 illustrates an exemplary DDR data eye with corresponding predetermined DDR eye margins.
[0015] FIG. 8 is a block diagram of an exemplary embodiment of a portable computing device for incorporating the system of FIG. 1.
[0017] In this description, the term "application" may also include files having executable content, such as: object code, scripts, byte code, markup language files, and patches. In addition, an "application" referred to herein, may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.
[0018] The term "content" may also include files having executable content, such as: object code, scripts, byte code, markup language files, and patches. In addition, "content" referred to herein, may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.
[0019] As used in this description, the terms "component," "database," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, a processor, an obj ect, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device may be a component. One or more components may reside within a process and/or thread of execution, and a component may be localized on one computer and/or distributed between two or more computers. In addition, these components may execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems by way of the signal).
[0020] In this description, the terms "communication device," "wireless device," "wireless telephone", "wireless communication device," and "wireless handset" are used interchangeably. With the advent of third generation ("3G"), fourth generation ("4G"), fifth generation ("5G") and other wireless technology, greater bandwidth availability has enabled more portable computing devices with a greater variety of wireless capabilities.
[0021] FIG. 1 illustrates an embodiment of a system 100 for reducing memory power consumption by customizing device-specific double data rate (DDR) interface parameters. The system 100 comprises a system on chip (SoC) 102 electrically coupled to a memory via a DDR interface. As known in the art, the DDR interface comprises a physical layer channel or bus that transfers data on both a rising and falling edges of a clock signal. In the embodiment of FIG. 1, the memory comprises a dynamic random access memory (DRAM) 104, and the DDR interface comprises a DRAM clock 136 and a DRAM control and data bus 134. It should be appreciated that system 100 may be implemented in any computing device, including a personal computer, a workstation, a server, a laptop computer, a gaming console, and a portable computing device (PCD), such as a cellular telephone, a smartphone, a portable digital assistant (PDA), a portable game console, a navigation device, a tablet computer, a fitness computer, and a wearable device (e.g., a sports watch, a fitness tracking device, etc.) or other battery- powered devices with a wireless connection or link.
[0022] The SoC 102 comprises various on-chip components electrically coupled via SoC bus 115. In the embodiment of FIG. 1, the SoC 102 comprises one or more memory clients (e.g., central processing unit(s) (CPU) 112, graphics processing unit(s) (GPU), digital signal processor(s) (DSPs)), a static random access memory (SRAM) 1 16, read only memory (ROM) 118, a DRAM controller 1 14, a storage controller 122, a power controller 124, and a dynamic clock and voltage scaling (DCVS) controller 120 interconnected via SoC bus 1 15.
[0023] The CPU 1 12 may support a high-level operating system (O/S) 126. As described below in more detail, the CPU 112 may execute various modules (e.g., DDR data eye training module 128, DDR interface parameter customization module 130) for performing the customization of device-specific DDR interface parameters.
[0024] The power controller 124 is electrically coupled to a power supply 138 via a power control bus 142, which comprises a power monitor 140 configured to measure energy usage associated with the SoC 102 and the DRAM 104 and, thereby, monitor memory power consumption.
[0025] As further illustrated in FIG. 1, the storage controller 122 may be electrically coupled via a storage bus 146 to external storage memory, such as, for example, flash memory 144 or other non-volatile memory device(s). Storage controller 122 controls communication with the external storage memory.
[0026] The DCVS controller 120 is configured to implement various DCVS techniques. As known in the art, the DCVS techniques involve selectively adjusting the frequency and/or voltage applied to the SoC components (e.g., CPU 1 12, power controller 124, and other hardware devices) to yield a desired performance and/or power efficiency characteristics.
[0027] The DRAM controller 114 comprises a physical layer 132, which is electrically coupled to a physical layer 106 residing on DRAM 104. Physical layer 106 is coupled to DRAM peripheral logic 108, which is coupled to a cell array 1 10.
[0028] As further illustrated in FIG. 1, the system 100 comprises specially-configured modules (i.e., DDR interface parameter customization module 130) for implementing device-specific customization of DDR interface parameters. It should be appreciated that finer granularity control of bandwidth/frequency operating points via device- specific customized DDR interface parameters may enable individual units of the same system design to consume less power at any given bandwidth/frequency operating point.
[0029] As known in the art, the memory interface frequency may be determined by the required traffic bandwidth requested from all memory clients. This frequency may rise or fall as the traffic bandwidth demand changes. Typically, several voltage/frequency bins may be used. For each frequency operating point, the system comprising the SoC, the physical channel, and the DRAM are tuned during factory initialization to establish "common parameter settings" that will provide reliable operation. FIG. 5 illustrates an exemplary embodiment of common parameter settings that may be used to improve the electrical signal quality of the DRAM control and data bus 134. The common parameter settings resulting from the tuning are tested across a large sample size of identical system design units (differing only by the individual SoC and DRAM component serial numbers), and then a common parameter setting is deployed, which represents a compromise to support a least common denominator across part-to-part variation. The common parameter settings are reliable and easy to deploy, but due to chip-to-chip and system variability, the settings may be conservative for a large majority of systems and result in unnecessary power consumption and/or reduced performance.
[0030] FIG. 2 illustrates an embodiment of a method 200 implemented in the system 100 for reducing DDR memory power consumption by customizing device-specific DDR interface parameters. The method 200 may be initiated, at block 202, as part of a factory initialization/configuration process or upon device boot-up. It should be appreciated that the method 200 may be performed successively at device boot-up to compensate for aging over the lifetime of the device. The method 200 may be initiated and controlled by DDR interface parameter customization module 130. As illustrated by decision block 204, the method 200 may be repeated for each of a plurality of bandwidth/frequency operating points. At block 206, one of the bandwidth/frequency operating points is selected. At block 208, a memory test pattern 151 is initiated at the selected operating point. During execution of the memory test 151 at the selected operating point, at block 210, the method 200 determines an optimal value of a setting for one or more DDR interface parameters associated with the DDR interface (i.e., buses 134 and 136) that (1) minimizes memory power consumption and (2) maintains predetermined DDR data eye margin(s). The feature of minimizing memory power consumption is described below with reference to FIG. 3. The feature of maintaining predetermined DDR date eye margin(s) may be facilitated by communication with DDR data eye training module 120, which is described below with reference to FIGS. 6 & 7. At block 212, the optimal value of the DDR interface parameter setting is stored in a memory for operational use at the selected operating point. For example, in an embodiment, the optimal value of the DDR interface parameter setting may be stored in a non-volatile memory and, in response to a subsequent boot of the computing device, the optimal value of the setting may be retrieved from the non-volatile memory.
[0031] In this manner, the DDR interface parameter settings at each frequency operating point may be optimized for individual devices or units to address potential chip-to-chip variation. During the execution of the memory test pattern 151 at the various frequency operating points, the power monitor 140 may measure power consumption of the SoC 102 and DRAM 104 while the DDR interface parameter settings are adjusted. It should be appreciated that the memory test pattern 151 exercises the DRAM 104 to characterize the magnitude of the power consumption for each frequency bin. There may be multiple reliable or successful parameter settings for each frequency bin. In an embodiment, the optimal setting is determined to be the setting that results in the lowest power consumption while maintaining the DDR data eye margin within predetermined margin(s).
[0032] FIG. 3 illustrates an exemplary power vs. bandwidth graph 300 for two different samples {i. e. , sample A and sample B) having the identical system design 100. For example, sample A may comprise a first portable computing device having a system design 100, and sample B may comprise a second portable computing device having the same system design 100. In this example, the system 100 provides six voltage frequency bins. A first voltage frequency bin0comprises the frequency range 0 - 400 MHz. A second voltage frequency bin40o comprises the frequency range 400 - 800 MHz. A third voltage frequency bingoo compri ses the frequency range 800 - 1 200 MHz. A fourth voltage frequency bini2oo comprises the frequency range 1200 - 1600 MHz. A fifth voltage frequency binieoo comprises the frequency range 1600 - 2000 MHz. A sixth voltage frequency bin2ooo comprises the frequency range 2000 - 2400 MHz. The solid line plots the memory power consumption measured by the power monitor 140 for a first device (sample A). The dashed line plots the memory power consumption measured by the power monitor 140 for a second device (sample B).
[0033] One of ordinary skill in the art will appreciate that the variations in memory power consumption between sample A and sample B may result from chip-to-chip variations related to the SoC 102 chip, the DRAM 104 chip(s), and/or variations in the physical channel comprising DRAM control and data bus 134 and DRAM clock bus 136. These and other variations between different devices having an identical system design may be caused by silicon process variation(s) between chips, which affect the DDR interface parameter settings that determine the operational characteristics such as interface power, frequency of operation, and bit error rate. For example, if either the SoC 102 or any DRAM 104 silicon is " slow", then for a given target frequency of operation the device may need to be configured with parameters, such as, drive strength or termination strength to compensate, resulting in higher power consumption compared to "fast" silicon. "Fast" or "slow" refers to the circuit signal propagation delay, rise/fall times, and skew characteristics.
[0034] The exemplary graph 300 shows that the power monitor 140 may determine different power consumption levels at the same frequency bins for sample A and sample B. For example, sample A has the lowest energy at low frequency (i.e. , PAOin bin0). Sample B has the lowest energy at peak frequency (i.e., PDB2„0„0„0 in bin2ooo). Sample A has a generally steeper slope than sample B (i.e. , [PA8(J(J- PA(J] > PB800- PB„] )· Sample A may require elevated power earlier at 1 100MHz compared to sample B at 1 500MHz. To minimize memory power consumption, the power monitor 140 residing in sample A and sample B may measure the corresponding illustrated memory power consumption and determine the DDR interface parameter settings, for each frequency bin, that results in the lowest memory power consumption for each sample.
[0035] FIG. 4 is a flowchart illustrating another embodiment of a method 400 for reducing DDR memory power consumption by customizing device-specific DDR interface parameters. A factory initialization may begin at block 402. At block 404, captive lab testing is performed for a plurality of units or devices comprising the system 1 00. The captive lab testing involves determining common voltage and timing parameters. In an embodiment, the multi-unit captive lab testing may involve a determination of common parameter settings or values, in the conventional manner described above. The common parameter settings or values may involve, for example, any of the parameters illustrated in column 502 in the data table 500 of FIG. 5 : SoC TX drive strength; DRAM TX drive strength; SoC RX termination; DRAM RX termination; WRITE duty cycle correction; READ duty cycle correction; WRITE equalization; READ equalization; WRITE data bus inversion; READ data bus inversion; WRITE link ECC/EDC; READ link ECC/EDC, and control bus link ECC/EDC. Column 504 describes how adjustments in the corresponding value or setting impacts memory power consumption. It should be appreciated that the multi- unit captive lab testing may determine so-called common parameter settings or values that result in reliable, error-free operation of the system 100.
[0036] At block 406, the common parameter settings or values may be committed to a software build for devices incorporating the system 100. At block 408, a device incorporating the system 100 may be initially booted up during OEM factory installation. At block 410, the common parameter settings or values are applied to the device and the system 100 may begin executing the memory test pattern 151. At block 412, the DDR date eye training module 128 may begin training DDR data eye parameters (e.g. , horizontal eye sampling point, vertical eye sampling point) to maximize DDR data eye margins for each frequency operating point. It should be appreciated that these DDR data eye parameters may not affect the shape, size, and/or quality of the data eye. For example, the DDR data eye training may determine an optimal sampling decision point within the eye. In contrast, the common parameter settings are capable of changing the shape, size, and/or quality of the data eye (e.g., making the eye clean versus noisy, large versus closed, etc.).
[0037] Referring to FIG. 6, the SoC 102 and the DRAM 104 transmit and receive data using a data strobe signal (DQS) 604 and a data signal (DQ) 602. The DQS signal 604 comprises a reference signal that transitions between logical 0 and 1. The DQ data 602 is captured on the transitioning edge of the DQS signal 604 on both the rising and falling edges. As known in the art, a DDR data eye 700 (FIG. 7) is generated when multiple captured data signals are superimposed on one another. The rising time refers to the time to transition from logical 0 to 1, and the falling time refers to the time to transition from logical 1 to 0. The reference voltage refers to the threshold voltage for differentiating logical 1 and 0.
[0039] Referring again to FIG. 4, when the "eye" parameters have been determined to maximize DDR data eye margins for each frequency operating point, the method 400 may initiate a process to determine customized, device-specific common parameters. At block 414, the settings or values for the common parameters (FIG. 5) may be adjusted while the power monitor 140 measures power consumption. In an embodiment, the DDR interface parameter customization module 130 (FIG. 1) sweeps through the values for one or more of the parameters identified in the table of FIG. 5 to determine the setting that yields the lowest power consumption for each frequency. At decision block 416, if the lowest power setting does not maintain the DDR data eye 700 within predetermined eye margin(s), the process may return to block 412. For example, referring to FIG. 7, the predetermined eye margin(s) may comprise a minimum value in the time domain (e.g., 176 ps) and/or minimum upper and lower voltage margins (e.g., 38 mV for the upper margin and 78 mV for the lower margin). If, however, the lowest power setting does maintain the DDR data eye 700 within the predetermined eye margin(s), the table 500 may be updated with the optimal setting or value (block 418). After determining adjusted settings or values for the common interface parameters for each frequency, the factory initialization may terminate at block 420. In this manner, the end result is a reliable bus operation that meets the predetermined eye margin(s) with common parameter settings that use the least energy.
[0040] As mentioned above, the system 100 may be incorporated into any desirable computing system. FIG. 8 illustrates the system 100 incorporated in an exemplary portable computing device (PCD) 800. It will be readily appreciated that certain components of the system 100 may be included on the SoC 822 (e.g. , DRAM controller 1 14, DRAM PHY 132, test pattern 1 51 , DDR data eye training module 128, DDR interface parameter customization module 130, etc.) while other components (e.g., DRAM 104) may be external components coupled to the SoC 822. The SoC 822 may include a multicore CPU 802. The multicore CPU 802 may include a zeroth core 810, a first core 812, and an Nth core 814. One of the cores may comprise, for example, a graphics processing unit (GPU) with one or more of the others comprising the CPU 802.
[0042] FIG. 8 further shows that a video encoder 834, e.g., a phase alternating line (PAL) encoder, a sequential color a memoire (SECAM) encoder, or a national television system(s) committee (NTSC) encoder, is coupled to the multicore CPU 802. Further, a video amplifier 836 is coupled to the video encoder 834 and the touch screen display 806. Also, a video port 838 is coupled to the video amplifier 836. As shown in FIG. 8, a universal serial bus (USB) controller 840 is coupled to the multicore CPU 802. Also, a USB port 842 is coupled to the USB controller 840.
[0043] Further, as shown in FIG. 8, a digital camera 848 may be coupled to the multicore CPU 802. In an exemplary aspect, the digital camera 848 is a charge-coupled device (CCD) camera or a complementary metal-oxide semiconductor (CMOS) camera.
[0044] As further illustrated in FIG. 8, a stereo audio coder-decoder (CODEC) 850 may be coupled to the multicore CPU 802. Moreover, an audio amplifier 852 may coupled to the stereo audio CODEC 850. In an exemplary aspect, a first stereo speaker 854 and a second stereo speaker 856 are coupled to the audio amplifier 852. FIG. 8 shows that a microphone amplifier 858 may be also coupled to the stereo audio CODEC 850. Additionally, a microphone 860 may be coupled to the microphone amplifier 858. In a particular aspect, a frequency modulation (FM) radio tuner 862 may be coupled to the stereo audio CODEC 850. Also, an FM antenna 864 is coupled to the FM radio tuner 862. Further, stereo headphones 866 may be coupled to the stereo audio CODEC 850.
[0045] FIG. 8 further illustrates that a radio frequency (RF) transceiver 868 may be coupled to the multicore CPU 802. An RF switch 870 may be coupled to the RF transceiver 868 and an RF antenna 872. A keypad 804 may be coupled to the multicore CPU 802. Also, a mono headset with a microphone 876 may be coupled to the multicore CPU 802. Further, a vibrator device 878 may be coupled to the multicore CPU 802.
[0046] FIG. 8 also shows that a power supply 880 may be coupled to the on-chip system 822. In a particular aspect, the power supply 880 is a direct current (DC) power supply that provides power to the various components of the PCD 800 that require power. Further, in a particular aspect, the power supply is a rechargeable DC battery or a DC power supply that is derived from an alternating current (AC) to DC transformer that is connected to an AC power source.
[0047] FIG. 8 further indicates that the PCD 800 may also include a network card 888 that may be used to access a data network, e.g., a local area network, a personal area network, or any other network. The network card 888 may be a Bluetooth network card, a WiFi network card, a personal area network (PAN) card, a personal area network ultra-low-power technology (PeANUT) network card, a television/cable/satellite tuner, or any other network card well known in the art. Further, the network card 888 may be incorporated into a chip, i.e., the network card 888 may be a full solution in a chip, and may not be a separate network card 888.
[0048] As depicted in FIG. 8, the touch screen display 806, the video port 838, the USB port 842, the camera 848, the first stereo speaker 854, the second stereo speaker 856, the microphone 860, the FM antenna 864, the stereo headphones 866, the RF switch 870, the RF antenna 872, the keypad 874, the mono headset 876, the vibrator 878, and the power supply 880 may be external to the on-chip system 822.
[0049] It should be appreciated that one or more of the method steps described herein may be stored in the memory as computer program instructions, such as the modules described above. These instructions may be executed by any suitable processor in combination or in concert with the corresponding module to perform the methods described herein.
[0050] Certain steps in the processes or process flows described in this specification naturally precede others for the invention to function as described. However, the invention is not limited to the order of the steps described if such order or sequence does not alter the functionality of the invention. That is, it is recognized that some steps may performed before, after, or parallel (substantially simultaneously with) other steps without departing from the scope and spirit of the invention. In some instances, certain steps may be omitted or not performed without departing from the invention. Further, words such as "thereafter", "then", "next", etc. are not intended to limit the order of the steps. These words are simply used to guide the reader through the description of the exemplary method.
[0051] Additionally, one of ordinary skill in programming is able to write computer code or identify appropriate hardware and/or circuits to implement the disclosed invention without difficulty based on the flow charts and associated description in this specification, for example.
[0052] Therefore, disclosure of a particular set of program code instructions or detailed hardware devices is not considered necessary for an adequate understanding of how to make and use the invention. The inventive functionality of the claimed computer implemented processes is explained in more detail in the above description and in conjunction with the Figures which may illustrate various process flows.
[0053] In one or more exemplary aspects, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer-readable media may comprise RAM, ROM, EEPROM, NAND flash, NOR flash, M-RAM, P-RAM, R-RAM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to carry or store desired program code in the form of instructions or data structures and that may be accessed by a computer.
[0054] Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line ("DSL"), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.
[0055] Disk and disc, as used herein, includes compact disc ("CD"), laser disc, optical disc, digital versatile disc ("DVD"), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer- readable media.
[0056] Alternative embodiments will become apparent to one of ordinary skill in the art to which the invention pertains without departing from its spirit and scope. Therefore, although selected aspects have been illustrated and described in detail, it will be understood that various substitutions and alterations may be made therein without departing from the spirit and scope of the present invention, as defined by the following claims.

中文:
[0001]便携式计算设备(例如,蜂窝电话、智能电话、平板电脑、便携式数字助理(PDA)、便携式游戏控制台、可穿戴设备和其它电池供电的设备)和其它计算设备持续提供不断扩展的大量功能和服务,以及提供给用户对信息、资源和通信的前所未有的访问级别。为了与这些服务增强保持同步,这样的设备已经变得越来越强大和越来越复杂。便携式计算设备现在通常包括片上系统(SoC),所述SoC包括嵌入在单个衬底上的多个存储器客户端(例如,一个或多个中央处理单元(CPU)、图形处理单元(GPU)、数字信号处理器(DSP)等等)。存储器客户端可以经由诸如双倍数据速率(DDR)总线的高速总线,来从电力地耦合到SoC的外部动态随机存取存储器(DRAM)中读取数据和将数据存储在其中。
[0002]虽然各种存储器标准定义了SoC可以与DRAM连接的协议和时序,但是现有系统对于选择最佳带宽/频率操作点而言具有若干缺点。在现有系统中,通常存在三个自由度,SoC可以从所述三个自由度中选择最佳操作点。首先,在DRAM供应商之间、在不同工艺节点之间、以及很大程度上在来自于相同的供应商和工艺节点的不同晶圆之间存在各种各样的硅。其次,在平台工业设计、SoC和DRAM封装设计以及射频兼容性之间存在通道变化。第三,可以调整各种DRAM接口参数设置(例如,时钟频率、延时、管芯上终端电阻等等)。
[0003]现有系统对于被设计为提供可靠的无错误操作的这些变量采用尽力而为的集总参数。这样的“一个尺寸适合全部”的参数设置可能是浪费能量的,因为可能存在超出基准以及可能受益于优化后的设置的设备样本。
[0004]相应地,存在针对用于自定义DRAM接口参数设置的改进的系统和方法的需要,以使独立的单元能够消耗最少的能量以及允许更精细粒度的带宽/频率操作点。
[0005]公开了用于对经由DDR接口参数的特定于设备的自定义来减少双倍数据速率(DDR)存储器功耗的系统和方法。一个实施例包括用于使双倍数据速率(DDR)功耗最小化的方法。该方法选择多个操作点中的一个操作点以用于DDR接口将DDR存储器电力地耦合到存在于片上系统(SoC)的存储器控制器。存储器控制器在所选择的操作点处经由DDR接口执行存储器测试。在所选择的操作点处执行存储器测试期间,该方法确定用于与DDR接口相关联的一个或多个DDR接口参数的设置的最佳值,所述最佳值使存储器功耗最小化以及维持预先确定的DDR眼图容限(eye margin)。
[0006]系统的另一实施例包括双倍数据速率(DDR)存储器和片上系统(SoC)。所述SoC包括经由DDR接口电力地耦合到DDR存储器的存储器控制器。该存储器控制器被配置为在多个操作点中的一个或多个操作点处经由DDR接口来执行存储器测试。在执行存储器测试期间,存储器控制器确定用于与DDR接口相关联的一个或多个DDR接口参数的设置的最佳值,所述最佳值使存储器功耗最小化以及维持预先确定的DDR眼图容限。
[0007]在附图中,除非以其它方式指示的,否则遍及各个视图的类似的附图标记指代类似的部分。对于利用诸如“102A”或“102B”的字母字符名称的附图标记而言,所述字母字符名称可以区分在相同的附图中给出的两个类似的部分或者元素。当附图标记旨在涵盖在全部附图中具有相同的附图标记的全部部分时,可以省略用于附图标记的字母字符名称。
[0008]图1是用于通过自定义特定于设备的双倍数据速率(DDR)接口参数来减少DDR存储器功耗的系统的实施例的方块图。
[0009]图2是示出用于通过自定义特定于设备的DDR接口参数来减少DDR存储器功耗的方法的实施例的流程图。
[0010]图3是示出在用于并入图1的系统的两个不同示例设备的各个电压频率频段处的存储器功耗的示例性示意图。
[0011]图4是示出用于在OEM测试期间通过自定义特定于设备的DDR接口参数来减少DDR存储器功耗的的另一实施例的流程图。
[0012]图5是示出可以被自定义为使存储器功耗最小化同时保持预先确定的DDR眼图容限的各种示例性公共DDR接口参数的表格。
[0013]图6示出了将SoC存储器控制器PHY耦合到DRAM PHY的物理层通道的实施例。
[0014]图7示出了具有对应的预先确定的DDR眼图容限的示例性DDR数据眼图。
[0015]图8是用于并入图1的系统的便携式计算设备的示例性实施例的方块图。
[0017]在本描述中,术语“应用”还可以包括具有可执行内容的文件,诸如:目标代码、脚本、字节代码、标记语言文件和补丁。另外,在本文中涉及的“应用”还可以包括在性质上不可执行的文件,诸如可能需要打开的文档或者需要访问的其它数据文件。
[0018]此外,术语“内容”还可以包括具有可执行内容的文件,诸如:目标代码、脚本、字节代码、标记语言文件和补丁。另外,在本文中涉及的“内容”还可以包括在性质上不可执行的文件,诸如可能需要打开的文档或者需要访问的其它数据文件。
[0019]如在本描述中使用的,术语“组件”、“数据库”、“模块”、“系统”等等旨在指的是与计算机相关的实体,无论是硬件、固件、硬件和软件的组合、软件,还是在运行中的软件。例如,组件可以是,但不限于是:在处理器上运行的过程、处理器、对象、可执行文件、执行的线程、程序和/或计算机。通过说明的方式,在计算设备上运行的应用和该计算设备两者可以是组件。一个或多个组件可以存在于过程和/或执行的线程内,以及组件可以位于一个计算机上和/或分布在两个或更多个计算机之间。另外,这些组件可以从在其上存储有各种数据结构的各种计算机可读介质中执行。所述组件可以通过诸如根据具有一个或多个数据分组的信号(例如,来自一个组件的数据,该组件与在本地系统、分布式系统中的另一组件进行交互和/或以信号的方式跨越诸如互联网的网络来与其它系统进行交互),来以本地和/或远程处理的方式进行通信。
[0020]在本描述中,术语“通信设备”、“无线设备”、“无线电话”、“无线通信设备”和“无线手持设备”是可交换地使用的。随着第三代(“3G”)、第四代(“4G”)、第五代(“5G”)和其它无线技术的出现,更大的带宽可用性已经使更多便携式计算设备具有更加多种多样的无线能力。
[0021]图1示出了用于通过自定义特定于设备的双倍数据速率(DDR)接口参数来减少存储器功耗的系统100的实施例。系统100包括经由DDR接口电力地耦合到存储器的片上系统(SoC)102。如本领域中已知的,DDR接口包括在时钟信号的上升沿和下降沿两者上传输数据的物理层通道或总线。在图1的实施例中,该存储器包括动态随机存取存储器(DRAM)104,以及DDR接口包括DRAM时钟136以及DRAM控制和数据总线134。应当认识到的是,系统100可以是在包括以下各项的任何计算设备中实现的:个人计算机、工作站、服务器、笔记本电脑、游戏控制台、以及诸如蜂窝电话、智能手机、便携式数字助理(PDA)、便携式游戏控制台、导航设备、平板电脑、健身计算机和可穿戴设备(例如,运动手表、健身跟踪设备等)的便携式计算设备(PCD)或者具有无线连接或链路的其它电池供电的设备。
[0022]SoC 102包括经由SoC总线115电力地耦合的各种片上组件。在图1的实施例中,SoC102包括一个或多个存储器客户端(例如,中央处理单元(CPU)112、图形处理单元(GPU)、数字信号处理器(DSP))、静态随机访问存储器(SRAM)116、只读存储器(ROM)118、DRAM控制器114、存储器控制器122、功率控制器124、以及经由SoC总线115互相连接的动态时钟和电压缩放(DCVS)控制器120。
[0023]CPU 112可以支持高级别操作系统(O/S)126。如在下文中更详细地描述的,CPU112可以执行各种模块(例如,DDR数据眼图训练模块128、DDR接口参数自定义模块130)以用于执行对特定于设备的DDR接口参数的自定义。
[0024]功率控制器124是经由功率控制总线142电力地耦合到功率138的,功率控制总线142包括功率监测器140,功率监测器140被配置为测量与SoC 102和DRAM 104相关联的能量使用,以及从而监测存储器功耗。
[0025]如在图1中进一步示出的,存储器控制器122可以是经由存储器总线146电力地耦合到外部存储器的(诸如,例如闪速存储器144或其它非易失性存储器设备)。存储器控制器122控制与外部存储器的通信。
[0026]DCVS控制器120被配置为实现各种DCVS技术。如本领域中已知的,DCVS技术指的是:选择性地调整应用于SoC组件(例如,CPU 112、功率控制器124和其它硬件设备)的频率和/或电压,以产生期望的性能和/或功率效率特性。
[0027]DRAM控制器114包括物理层132,其是电力地耦合到存在于DRAM104上的物理层106的。物理层106是耦合到DRAM外围逻辑108的,DRAM外围逻辑108是耦合到单元阵列110的。
[0028]如在图1中进一步示出的,系统100包括用于实现对DDR接口参数的特定于设备的自定义的专门配置的模块(即,DDR接口参数自定义模块130)。应当认识到的是,对经由特定于设备的自定义后的DDR接口参数的带宽/频率操作点的更精细粒度控制,可以使相同系统设计的独立的单元能够在任何给定的带宽/频率操作点处消耗更少的功率。
[0029]如本领域中已知的,存储器接口频率可以是通过从全部存储器客户端请求的需要的业务带宽来确定的。随着业务带宽需求变化,该频率可以上升或下降。通常,可以使用若干电压/频率频段。对于各频率操作点而言,包括SoC、物理通道和DRAM的系统在工厂初始化(factory initialization)期间被调谐为建立将提供可靠操作的“公共参数设置”。图5示出了可以用以改进DRAM控制和数据总线134的电子信号质量的公共参数设置的示例性实施例。由调谐造成的公共参数设置是跨越大样本尺寸的完全相同的系统设计单元(所述单元仅通过独立的SoC和DRAM组件序列号进行区分)来测试的,以及然后部署公共参数设置,其表示对支持跨越部分对部分的改变的最小公分母的让步。公共参数设置是可靠的以及是易于部署的,但由于芯片对芯片以及系统可变性,对于大多数系统而言所述设置可能是保守的,以及导致不必要的功耗和/或性能降低。
[0030]图2是示出在用于通过自定义特定于设备的DDR接口参数来减少DDR存储器功耗的系统100中实现的方法200的实施例。作为工厂初始化/配置过程的一部分或者在设备启动时,方法200可以在方块202处开始。应当认识到的是,方法200可以在设备启动时连续地执行以补偿在设备的整个寿命中的老化。方法200可以由DDR接口参数自定义模块130开始和控制。如通过决定方块204示出的,方法200可以重复用于多个带宽/频率操作点中的各带宽/频率操作点。在方块206处,选择带宽/频率操作点中的一个带宽/频率操作点。在方块208处,在所选的操作点处开始存储器测试模式151。在方块210处,在所选择的操作点执行存储器测试151期间,方法200确定用于与DDR接口(即,总线134和136)相关联的一个或多个DDR接口参数的设置的最佳值,所述最佳值:(1)使存储器功耗最小化,以及(2)维持预先确定的DDR数据眼图容限。使存储器功耗最小化的特征是在下文中参考图3来描述的。维持预先确定的DDR数据眼图容限的特征可以是通过与DDR数据眼图训练模块120的通信来促进的,DDR数据眼图训练模块120是在下文中参考图6和图7来描述的。在方块212处,将DDR接口参数设置的最佳值存储在存储器中,以用于在所选择的操作点进行操作时使用。例如,在一实施例中,可以将DDR接口参数设置的最佳值存储在非易失性存储器中,以及响应于计算设备的后续启动,可以从非易失性存储器中检索该设置的最佳值。
[0031]在该方式中,在各频率操作点处的DDR接口参数设置可以是针对独立的设备或单元来优化的,以解决潜在的芯片对芯片的改变。在各个频率操作点处执行存储器测试模式151期间,在调整DDR接口参数设置的同时,功率监测器140可以测量SoC 102和DRAM 104的功耗。应当认识到的是,存储器测试模式151运用DRAM 104以表征各频率频段的功耗的大小。可能存在用于各频率频段的多个可靠或成功的参数设置。在一实施例中,最佳设置被确定为导致最低功耗同时将DDR数据眼图容限维持在预先确定的容限内的设置。
[0032]图3示出了用于具有完全相同的系统设计100的两个不同样本(即,样本A和样本B)的示例性功率带宽对比图300。例如,样本A可以包括具有系统设计100的第一便携式计算设备,以及样本B可以包括具有相同系统设计100的第二便携式计算设备。在该示例中,系统100提供六个电压频率频段。第一电压频率bin0包括0-400MHz的频率范围。第二电压频率频段bin400包括400-800MHz的频率范围。第三电压频率频段bin800包括800-1200MHz的频率范围。第四电压频率频段bin1200包括1200-1600MHz的频率范围。第五电压频率频段bin1600包括频率范围1600-2000MHz。第六电压频率频段bin2000包括2000-2400MHz的频率范围。实线绘制了由功率监测器140针对第一设备测量的存储器功耗(样本A)。虚线绘制了由功率监测器140针对第二设备测量的存储器功耗(样本B)。
[0033]本领域普通技术人员将认识到的是,在样本A与样本B之间的存储器功耗的变化可能是由与SoC 102芯片、DRAM 104芯片相关的芯片对芯片的变化、和/或在包括DRAM控制和数据总线134以及DRAM时钟总线136的物理通道中的变化造成的。在具有完全相同的系统设计的不同设备之间的这些和其它变化可能是由在芯片之间的硅工艺变化引起的,所述变化影响DDR接口参数设置,所述DDR接口参数设置确定诸如接口功率、操作的频率和误比特率的操作特性。例如,如果SoC 102或任何DRAM 104硅片是“慢的”,则对于操作的给定目标频率而言,可能需要被配置有诸如驱动强度或终止强度的参数以进行补偿,导致比“快的”硅片相要高的功耗。“快的”或“慢的”指的是电路信号传播延迟、上升/下降时间和偏斜特性。
[0034]示例性示意图300示出了功率监测器140可以确定针对样本A和样本B在相同的频率频段的不同功耗水平。例如,样本A在低频(即,在bin0中的PA0)处具有最低的能量。样本B在峰值频率(即,在bin2000中的PB2000)处具有最低的能量。样本A的斜率通常比样本B要陡(即,[PA800-PA0]>[PB800-PB0])。与在1500MHz处的样本B相比,样本A需要在1100MHz处较早地提升功率。为了使存储器功耗最小化,存在于样本A和样本B中的功率监测器140可以测量对应的示出的存储器功耗,以及确定用于各频率频段的、导致用于各样本的最低存储器功耗的DDR接口参数设置。
[0035]图4是示出用于通过自定义特定于设备的DDR接口参数来减少DDR存储器功耗的的另一实施例的流程图。工厂初始化可以开始于方块402处。在方块404处,针对包括系统100的多个单元或设备执行可控实验室测试(captive lab testing)。可控实验室测试涉及确定公共电压和时序参数。在一实施例中,多单元可控实验室测试可以涉及以在上文中描述的常规方式对公共参数设置或值的确定。例如,该公共参数设置或值可以涉及在图5的数据表格500的列502中示出的参数中的任何参数:SoC TX驱动强度、DRAM TX驱动强度、SoC RX终止、DRAM RX终止、写占空比校正、读占空比校正、写均衡、读均衡、写数据总线反转、读数据总线反转、写链路ECC/EDC、读链路ECC/EDC和控制总线链路ECC/EDC。列504描述了在对应的值或设置中的调整如何影响存储器功耗。应当认识到的是,多单元可控实验室测试可以确定导致系统100的可靠、无错误操作的所谓的公共参数设置或值。
[0036]在方块406处,公共参数设置或值可以交付给并入系统100的设备的软件构建。在方块408处,在OEM工厂安装期间,并入系统100的设备可以首先启动。在方块410处,公共参数设置或值可以应用于设备,以及系统100可以开始执行存储器测试模式151。在方块412处,DDR数据眼图训练模块128可以开始训练DDR数据眼图参数(例如,水平眼图采样点、垂直眼图采样点),以使针对各频率操作点的DDR数据眼图容限最大化。应当认识到的是,这些DDR数据眼图参数可能不影响数据眼图的形状、尺寸和/或质量。例如,DDR数据眼图训练可以确定在眼图内的最佳采样决定点。相比而言,公共参数设置能够改变数据眼图的形状、尺寸和/或质量(例如,使眼图与嘈杂相对是干净的、与封闭相对是较大的等等)。
[0037]参考图6,SoC 102和DRAM 104使用数据选通信(data strobe signal)号(DQS)604和数据信号(DQ)602来发送和接收数据。DQS信号604包括在逻辑0与1之间的转换的参考信号。DQ数据602是在DQS信号604的转换沿(在上升沿和下降沿两者)上捕获的。如本领域中已知的,DDR数据眼图700(图7)是在多个捕获到的数据信号相互叠加时生成的。上升时间指的是从逻辑0转换到1的时间,以及下降时间指的是从逻辑1转换到0的时间。参考电压指的是用于区分逻辑1和0的门限电压。
[0039]再次参考图4,当“眼图”参数已经被确定为使针对各频率操作点的DDR数据眼图容限最大化时,方法400可以开始确定自定义的、特定于设备的公共参数的过程。在方块414处,在功率监测器140测量功耗的同时,可以调整用于公共参数的设置或值(图5)。在一实施例中,DDR接口参数自定义模块130(图1)扫描通过针对在图5的表格中标识的一个或多个参数的值,以确定产生针对各频率的最低功耗的设置。在决定方块416处,如果最低功率设置没有将DDR数据眼图700维持在预先确定的眼图容限内,则过程可以返回到方块412。例如,参考图7,预先确定的眼图容限可以包括在时域中的最小值(例如,176皮秒)和/或最小的上限和下限电压容限(例如,针对上限容限的38毫伏以及针对下限容限的78毫伏)。然而,如果最低功率设置将DDR数据眼图700维持在预先确定的眼图容限内,则可以利用最佳设置或值来更新表格500(方块418)。在确定用于各频率的公共接口参数的调整后的设置或值之后,工厂初始化可以在方块420处终止。以此方式,最终结果是以使用最少能量的公共参数设置来满足预先确定的眼图容限的可靠的总线操作。
[0040]如在上文中提及的,系统100可以并入到任何期望的计算系统中。图8示出了并入示例性便携式计算设备(PCD)800中的系统100。将容易认识到的是,系统100的某些组件可以是包括在SoC 822(例如,DRAM控制器114、DRAM PHY 132、测试模式151、DDR数据眼图训练模块128、DDR接口参数自定义模块130等等)上的,而其它组件(例如,DRAM 104)可以是耦合到SoC 822的外部组件的。SoC 822可以包括多核心CPU 802。多核心CPU 802可以包括第零核心810、第一核心812和第N核心814。例如,所述核心中的一个核心可以包括图形处理单元(GPU),其中其它一个或多个核心包括CPU 802。
[0042]图8进一步示出了视频编码器834(例如,逐行倒相(PAL)编码器、顺序传送彩色与存储(SECAM)编码器或者国家电视标准委员会(NTSC)编码器)是耦合到多核心CPU 802的。进一步地,视频放大器836是耦合到视频编码器834和触摸屏显示器806的。另外,视频端口838是耦合到视频放大器836的。如在图8中示出的,通用串行总线(USB)控制器840是耦合到多核心CPU 802的。另外,USB端口842是耦合到USB控制器840的。
[0043]进一步地,如在图8中示出的,数字相机848可以是耦合到多核心CPU802的。在一示例性方面中,数字相机848是电荷耦合器件(CCD)相机或者互补金属氧化半导体(CMOS)相机。
[0044]如在图8中进一步示出的,立体声音频编码器解码器(CODEC)850可以是耦合到多核心CPU 802的。此外,音频放大器852可以是耦合到立体声音频CODEC 850的。在示例性方面中,第一立体声扬声器854和第二立体声扬声器856是耦合到音频放大器852的。图8示出了麦克风放大器858还可以是耦合到立体声音频CODEC 850的。另外,麦克风860可以是耦合到麦克风放大器858的。在特定的方面中,调频(FM)无线调谐器862可以是耦合到立体声音频CODEC 850的。另外,FM天线864是耦合到FM无线调谐器862的。进一步地,立体声耳机866可以是耦合到立体声音频CODEC 850的。
[0045]图8进一步示出了射频(RF)收发机868可以是耦合到多核心CPU 802的。RF开关870可以是耦合到RF收发机868和RF天线872的。键盘804可以是耦合到多核心CPU 802。另外,具有麦克风的单声道耳机876可以是耦合到多核心CPU 802的。进一步地,振动器设备878可以是耦合到多核心CPU 802的。
[0046]图8还示出了电源880可以是耦合到片上系统822的。在特定的方面中,电源880是向需要功率的PCD 800的各个组件提供功率的直流(DC)电源。进一步地,在特定的方面中,该电源是可充电DC电池或者DC电源,所述DC电源是从连接到AC电源的交流电(AC)到DC转换器得到的。
[0047]图8进一步指示PCD 800还可以包括网卡888,该网卡888可以用以访问数据网络(例如,局域网、个人区域网或任何其它网络)。网卡888可以是蓝牙网卡、WiFi网卡、个人区域网(PAN)卡、个人区域网超低功率技术(PeANUT)网卡、电视/有线电视/卫星调谐器单元或者本领域公知的任何其它网卡。进一步地,网卡888可以并入到芯片中,即,网卡888可以是在芯片中的完整解决方案,以及可以不是单独的网卡888。
[0048]如在图8中描绘的,触摸屏显示器806、视频端口838、USB端口842、照相机848、第一立体声扬声器854、第二立体声扬声器856、麦克风860、FM天线864、立体声耳机866、RF开关870、RF天线872、键盘874、单声道耳机876、振动器878和电源880可以是在片上系统822之外的。
[0049]应当认识到的是,在本文中描述的方法步骤中的一个或多个方法步骤可以作为计算机程序指令(诸如在上文中描述的模块)存储在存储器中。这些指令可以由任何合适的处理器结合对应的模块或者与对应的模块一起执行,以执行在本文中描述的方法。
[0050]在本说明书中描述的过程或者过程流中的某些步骤,自然地在本发明的其它步骤之前,以实现如描述的功能。然而如果所描述的步骤的顺序或者序列不改变本发明的功能,则本发明不受限于这样的顺序或序列。就是说,应当认识到,在不背离本发明的保护范围或者精神的情况下,一些步骤可以在其它步骤之前、之后或者并行(与其它步骤大体上同时地)执行。在一些实例中,在不背离本发明的情况下,可以省略或者不执行某些步骤。进一步地,诸如“其后”、“然后”、“接下来”等等的词语不旨在限制步骤的顺序。这些词语仅用以引导读者通读示例性方法的描述。
[0051]另外,在编程领域的普通技术人员能够编写计算机代码或者识别适当的硬件和/或电路,以例如基于在本说明书中的流程图和关联的描述在没有困难的情况下实现所公开的发明。
[0052]因此,对于充分地理解如何利用和使用本发明而言,特定的程序代码指令集合或者详细的硬件设备的公开内容不认为是必需的。所要求保护的计算机实现的过程的创新的功能是在上文的描述中以及结合可以示出各个过程流的附图来更详细地解释的。
[0053]在一个或多个示例性方面中,所描述的功能可以在硬件、软件、固件或其任何组合中实现的。如果在软件中实现,所述功能可以作为一个或多个指令或代码存储在计算机可读介质中或者在计算机可读介质上进行发送。计算机可读介质包括计算机存储介质和通信介质两者,所述通信介质包括促进将计算机程序从一个地方传送到另一地方的任何介质。存储介质可以是由计算机能够存取的任何可用的介质。举例而言以及不是限制,这样的计算机可读介质可以包括RAM、ROM、EEPROM、NAND闪存、NOR闪存、M-RAM、P-RAM、R-RAM、CD-ROM或者其它光盘存储器、磁盘存储器或其它磁存储设备、或者能够用以以指令或数据结构的形式携带或存储期望的程序代码并能够由计算机进行存取的任何其它介质。
[0054]另外,任何连接适当地称为计算机可读介质。例如,如果软件是使用同轴电缆、光纤电缆、双绞线、数字用户线路(“DSL”)或者诸如红外线、无线电和微波的无线技术从网站、服务器或其它远程源发送的,则同轴电缆、光纤光缆、双绞线、DSL或者诸如红外线、无线电和微波的无线技术是包括在介质的定义中的。
[0055]如在本文中使用的,磁盘和光盘包括压缩光盘(“CD”)、激光光盘、光盘、数字通用光盘(“DVD”)、软盘和蓝光光盘,其中磁盘通常磁性地复制数据,而光盘则用激光来光学地复制数据。上述的组合也应当是包括在计算机可读介质的保护范围内的。
[0056]对于与本发明相关的领域普通技术人员而言,在不背离本发明的精神和保护范围的情况下,替代的实施例将变得显而易见。因此,虽然已经详细地说明和描述了选择的各方面,但将理解的是,可以在不背离本发明的精神和保护范围的情况下在其中做出各种替换和替代,如通过下文的权利要求规定的。