English:
[0003] Solar cells are photovoltaic devices that convert sunlight directly into electrical power. The most common solar cell material is silicon, which is in the form of single or polycrystalline wafers. However, the cost of electricity generated using silicon- based solar cells is higher than the cost of electricity generated by the more traditional methods. Therefore, since early 1970's there has been an effort to reduce cost of solar cells for terrestrial use. One way of reducing the cost of solar cells is to develop low-cost thin film growth techniques that can deposit solar-cell-quality absorber materials on large area substrates and to fabricate these devices using high-throughput, low-cost methods.
[0004] Group IBIIIAVIA compound semiconductors comprising some of the Group IB (Cu, Ag, Au), Group HIA (B, Al, Ga, In, Tl) and Group VIA (O, S, Se, Te, Po) materials or elements of the periodic table are excellent absorber materials for thin film solar cell structures. Especially, compounds of Cu, In, Ga, Se and S which are generally referred to as CIGS(S), or Cu(In,Ga)(S,Se) 2 or CuIni- x Ga x (S y Se 1 . y ) k , where O≤x≤l, 0<y<l and k is approximately 2, have already been employed in solar cell structures that yielded conversion efficiencies approaching 20%. Among the family of compounds, best efficiencies have been obtained for those containing both Ga and In, with a Ga amount in the 15-25%. Absorbers containing more Ga or no In gave lower efficiencies which is believed to be due to the lower carrier lifetimes in Ga-rich materials. Absorbers containing no Ga, on the other hand, have a low bandgap of about 1 eV and also have poor adhesion characteristics to their substrate, limiting their efficiencies. Absorbers containing Group IHA element Al and/or Group VIA element Te also showed promise. Therefore, in summary, compounds containing: i) Cu from Group IB, ii) at least one of In, Ga, and Al from Group IHA, and iii) at least one of S, Se, and Te from Group VIA, are of great interest for solar cell applications.
[0005] The structure of a conventional Group IBIIIAVIA compound photovoltaic cell such as a Cu(In,Ga, Al)(S, Se,Te) 2 thin film solar cell is shown in Figure 1. The device 10 is fabricated on a substrate 11, such as a sheet of glass, a sheet of metal, an insulating foil or web, or a conductive foil or web. The absorber film 12, which comprises a material in the family of Cu(In,Ga, Al)(S,Se,Te>2 , is grown over a conductive layer 13 or a contact layer, which is previously deposited on the substrate 11 and which acts as the electrical ohmic contact to the device. The most commonly used contact layer or conductive layer in the solar cell structure of Figure 1 is Molybdenum (Mo). If the substrate itself is a properly selected conductive material such as a Mo foil, it is possible not to use a conductive layer 13, since the substrate 11 may then be used as the ohmic contact to the device. The conductive layer 13 may also act as a diffusion barrier in case the metallic foil is reactive. For example, foils comprising materials such as Al, Ni, Cu may be used as substrates provided a barrier such as a Mo layer is deposited on them protecting them from Se or S vapors. The barrier is often deposited on both sides of the foil to protect it well. After the absorber film 12 is grown, a transparent layer 14 such as a CdS, ZnO or CdS/ZnO stack is formed on the absorber film. Radiation 15 enters the device through the transparent layer 14. Metallic grids (not shown) may also be deposited over the transparent layer 14 to reduce the effective series resistance of the device. The preferred electrical type of the absorber film 12 is p-type, and the preferred electrical type of the transparent layer 14 is n-type. However, an n-type absorber and a p-type window layer can also be utilized. The preferred device structure of Figure 1 is called a "substrate- type" structure. A "superstrate-type" structure can also be constructed by depositing a transparent conductive layer on a transparent superstrate such as glass or transparent polymeric foil, and then depositing the Cu(In, Ga,Al)(S,Se,Te)2 absorber film, and finally forming an ohmic contact to the device by a conductive layer. In this superstrate structure light enters the device from the transparent superstrate side. A variety of materials, deposited by a variety of methods, can be used to provide the various layers of the device shown in Figure 1.
[0006] In a thin film solar cell employing a Group IBIIIAVIA compound absorber, the cell efficiency is a strong function of the molar ratio of IB/IIIA. If there are more than one Group IIIA materials in the composition, the relative amounts or molar ratios of these IIIA elements also affect the properties. For a Cu(In,Ga)(S,Se>2 absorber layer, for example, the efficiency of the device is a function of the molar ratio of Cu/(In+Ga). Furthermore, some of the important parameters of the cell, such as its open circuit voltage, short circuit current and fill factor vary with the molar ratio of the IIIA elements, i.e. the Ga/(Ga+In) molar ratio. In general, for good device performance Cu/(In+Ga) molar ratio is kept at around or below 1.0. Alternately, if the ratio is larger than 1.0, the film is etched in a solution, such as a cyanide solution, to etch away the excess Cu-Se phase before constructing the solar cell devices. As the Ga/(Ga+In) molar ratio increases, on the other hand, the optical bandgap of the absorber layer increases and therefore the open circuit voltage of the solar cell increases while the short circuit current typically may decrease. It is important for a thin film deposition process to have the capability of controlling both the molar ratio of D3/IIIA, and the molar ratios of the Group IHA components in the composition. It should be noted that although the chemical formula is often written as Cu(In,Ga)(S,Se>2, a more accurate formula for the compound is Cu(In,Ga)(S,Se) k , where k is typically close to 2 but may not be exactly 2. For simplicity we will continue to use the value of k as 2. It should be further noted that the notation "Cu(X, Y)" in the chemical formula means all chemical compositions of X and Y from (X=0% and Y= 100%) to (X= 100% and Y=0%). For example, Cu(In,Ga) means all compositions from CuIn to CuGa. Similarly, Cu(In 5 Ga)(S 5 Se) 2 means the whole family of compounds with Ga/(Ga+In) molar ratio varying from 0 to 1 , and Se/(Se+S) molar ratio varying from 0 to I.
[0007] The first technique that yielded high-quality Cu(In,Ga)Se 2 films for solar cell fabrication was co-evaporation of Cu, In, Ga and Se onto a heated substrate in a vacuum chamber. However, low materials utilization, high cost of equipment, difficulties faced in large area deposition and relatively low throughput are some of the challenges faced in commercialization of the co-evaporation approach.
[0008] Another technique for growing Cu(In 1 Ga)(S 1 Se) 2 type compound thin films for solar ceil applications is a two-stage process where metallic components of the Cu(In,Ga)(S,Se)2 material are first deposited onto a substrate, and then reacted with S and/or Se in a high temperature annealing process. For example, for CuInSe 2 growth, thin layers of Cu and In are first deposited on a substrate and then this stacked precursor layer is reacted with Se at elevated temperature. If the reaction atmosphere also contains sulfur, then a CuIn(S,Se)2 layer can be grown. Addition of Ga in the precursor layer, i.e. use of a Cu/In/Ga stacked film precursor, allows the growth of a Cu(In,Ga)(S,Se)2 absorber.
[0009] Sputtering and evaporation techniques have been used in prior art approaches to deposit the layers containing the Group IB and Group IHA components of the precursor stacks. In the case of CulnSe 2 growth, for example, Cu and In layers were sequentially sputter-deposited on a substrate and then the stacked film was heated in the presence of gas containing Se at elevated temperature for times typically longer than about 30 minutes, as described in U.S. 4,798,660. More recently U.S. Patent 6,048,442 disclosed a method comprising sputter-depositing a stacked precursor film comprising a Cu-Ga alloy layer(s) and an In layer to form a Cu-Ga/In stack on a metallic back electrode layer and then reacting this precursor stack film with one of Se and S to form the absorber layer. U.S. Patent 6,092,669 described sputtering-based equipment for producing such absorber layers. Such techniques may yield good quality absorber layers and efficient solar cells, however, they suffer from the high cost of capital equipment, and relatively slow rate of production. Also physical vapor deposition (PVD) techniques such as sputtering and evaporation, although flexible in changing the deposition sequence of the elements forming a metallic stack, have certain drawbacks in terms of ability to form stacks with layers of un-alloyed, pure materials as will be discussed later.
[00010] One prior art method described in U.S. Patent 4,581 , 108 utilizes a low cost electrodeposition approach for metallic precursor preparation. In this method a Cu layer is first electrodeposited on a substrate covered with Mo. This is then followed by electrodeposition of an In layer and heating of the deposited Cu/In stack in a reactive atmosphere containing Se to obtain CIS. In later work an electrodeposition sequence of Cu/In/Ga was also reported to obtain CIGS films. Although low-cost in nature, both of these techniques were found to yield CIS films with poor adhesion to the Mo contact layer. In a publication ("Low Cost Thin Film Chalcopyrite Solar Cells", Proceedings of 18 th IEEE Photovoltaic Specialists Conf., 1985, p. 1429) electrodeposition and selenization of Cu/In and Cu/In/Ga layers were demonstrated for CIS and CIGS growth. One problem area was identified as peeling of the compound films during solar cell processing. Later, in another reference ("Low Cost Methods for the Production of Semiconductor Films for CIS/CdS Solar Cells", Solar Cells, vol. 21, p. 65, 1987) researchers studied the cross-section of Mo/CuInSβ2 interface obtained by the above- mentioned method and found the CuInSe 2 to have poor adhesion to the Mo contact layer.
[00011] As mentioned above Mo, is the most commonly used ohmic contact material (or conductive layer 13 in Figure 1) in CIS or CIGS type solar cells. The conductive layer 13 or contact layer of Figure 1 has multiple functions and must meet certain criteria. Contact layer must be relatively inert not to react extensively with Se , Te or S or the CIS or CIGS layers themselves. It has to function as a barrier for impurity diffusion from the substrate into the CIS or CIGS layer or protect the substrate with reaction with Se, S or Te * . It has to make a good ohmic contact to the solar cell and provide good optical reflection so that, especially in very thin device structures, photons reaching the back of the device get reflected and provide more light-generated carriers to be collected. Molybdenum was found to provide these qualities to a large extent and therefore has been used widely as the contact layer or ohmic contact material, although some researchers used Gold (Au) also in their experiments (see for example, C. Huang et al, Solar Energy Materials and Solar Ceils, vol:82, p. 553, (2004)). In a recent publication, Orgassa et al evaluated Tungsten (W), Mo, Tantalum (Ta), Niobium (Nb), Chromium (Cr), Vanadium (V), Titanium (Ti) and Manganese (Mn) as back contact to CIGS solar cells for the purpose of identifying a material that would yield the most stable and repeatable performance (see; Thin Solid Films, vol:431, p: 387 (2003)). They found that W, Mo, Ta and Nb were inert during the CIGS deposition process, which was a co- evaporation method. Other metals reacted with Se and some were totally consumed into the growing layer during the CIGS film growth. Researchers concluded that W, Ta and Nb could replace Mo as the ohmic contact metal to CIGS solar cells. U.S. Patent 6,307, 148 described a method wherein an interfacial layer of Palladium (Pd) or Platinum (R) was coated over the Mo contact layer before the formation of a Cu-rich (Cu to Group IIIA metal ratio higher than 1.6) copper indium or copper indium gallium sulfide or selenide compound layer mixed with Cu-sulfide or copper selenide phases. This mixed phase material was then etched in a KCN solution to etch away the Cu-sulfide or Cu-selenide phases, leaving beside the solar-cell-grade copper-indium selenide or sulfide layer. It was stated, in the absence of Pd or Pt interfacial layers, the KCN etching step led to film peeling problems if the Cu to Group IIIA ratio was larger than 1.6. With the Pt or Pd interfacial layers, films did not peel after the KCN etching step even if their Cu to Group IHA. ratios were larger than 1.6. U.S. Patent 5,028,274 used a Tellurium (Te) interfacial layer to enhance adhesion of CIS films to the contact layers which were selected from the group comprising Mo, W, Ta, Ti, Au and Titanium Nitride (TiN). U.S. Patent 4,915,745 cited Mo, W, Au, Nickel (Ni) and Nickel-phosphide (Ni-P) as possible contact layers to CIGS type solar cells. In U.S. Patent 5,695,627 researchers electroplated Cu-In-Se-S using as contact layers metals from the group of Mo, Ti, Cr, and Pt. U.S. Patent 5,676,766 listed Cr, Ti, Ta and TiN as interlayers to improve adhesion. In U.S. Patent 5,626,688 Mo, TiN, Pd and Pt are mentioned as contacts to CIS type films. In U.S. Patent 5,501,786 Mo, TiN and Zirconium nitride (ZrN) were used as base conductors over which layers comprising Se particles were plated.
[00012] Wet processing techniques such as electrodeposition and electroless deposition, although lower cost than the PVD approaches such as evaporation and sputtering, have their unique challenges. For example, electrodeposition or electroplating techniques are much more substrate-sensitive compared to the PVD techniques. In a PVD process metal A may be evaporated or sputter deposited on metal B and the deposition sequence may be reversed at will, i.e. metal B may be deposited on metal A or stacks such as A/B/A/B or B/A/B/A may be formed. In an electrodeposition process, however, there have been limitations in forming metallic stacks comprising various different metals. For example, as reviewed above, prior art methods electroplated Cu, In and optionally Ga to form Cu/In and Cu/In/Ga stacks on Mo coated substrates for the fabrication of Mo/CIS and Mo/CIGS structures, which were then used for solar cell fabrication. One of the reasons for selecting Cu/In and Cu/In/Ga electrodeposition sequence was the fact that Cu, In and Ga have very different standard plating potentials. The molar standard electrode potentials of Cu/Cu 2+ , InZIn 3+ and Ga/Ga 3+ metal/ion couples in aqueous solutions are about +0.337 V, -0.342 V, and -0.52 V, respectively. This means that Cu can be plated out at low negative voltages. For In deposition, on the other hand, larger negative voltages are needed. For Ga deposition, which is challenging due to hydrogen evolution, even larger negative voltages are required. Therefore, to form a stack containing Cu, In and Ga, Cu was typically electroplated first. This was then followed by deposition of In and then Ga so that while plating the second metal over the first metal, the first metal does not dissolve into the electrolyte of the second metal. Therefore, prior-art methods have employed Cu/In/Ga stacks electroplated in that order. However, after selenization such stacks yielded compound layers with poor morphology and poor adhesion to the base or the Mo coated substrate as was discussed before.
[00013] Other attempts to use electrodeposited precursors for the formation of Cu(In,Ga)Sβ 2 layers included electroplating of a Cu-Ga film followed by electroplating of a Cu-In-Se film thereby forming a Cu-Ga/Cu-In-Se stack; and annealing the stack at 600 C (Friedfeld et al., Solar Energy Materials and Solar Cells, vol: 58, p: 375, 1999). Zank et al. (Thin Solid Films, vol: 286, p:259, 1996) sputter deposited a Cu-Ga alloy film on a glass/Mo substrate. They then electroplated, from a single bath, an In-Ga film, forming a Cu-Ga/In-Ga stack. This stack was then reacted with Se to form the compound. This approach would not be low cost because preparation of Cu-Ga alloy sputtering targets is in itself expensive and utilization of the target material is very low (typically lower than 40%) in a sputtering approach. Ganchev et al. electrodeposited a Cu-In-Ga precursor film from a single bath and obtained Cu(In,Ga)Se 2 layer after selenizing this precursor layer (Thin Solid Films, vol: 511-512, p: 325, 2006).
[00014] Macro and micro-scale non-uniformities in the thickness and morphology of sub-layers in a precursor film including Cu, In, and/or Ga cause morphological and compositional non-uniformities in the CIGS(S) absorber after Cu, and/or In and/or Ga are reacted with a Group VIA material such as Se and/or S forming the CIGS(S) absorber. This topic has been discussed in detail in our U.S. Patent Application Publication No. 2005/0202589 (Sep. 15, 2005) and U.S. Patent Application Publication No. 2006/0121701 (Jun. 8, 2006).
[00015] As the brief review above demonstrates, there is still need to develop alternative ohmic contact materials to CIGS type solar cells for better mechanical, structural, compositional and electrical properties of the CIGS type absorber layers. There is also need to provide low cost electrodeposition approaches with flexibilities similar to those of the more expensive PVD techniques in forming various metallic precursor stacks comprising Cu, In and Ga together, since precursors containing only Cu and In or only Cu and Ga would provide CuIn(S 1 Se) 2 or CuGa(S,Se>2 absorber layers which yield solar cells with efficiencies much lower than 20% which has been demonstrated for Cu(In,Ga)(S,Se)2 material. There is also need for electroplated precursor films that, when reacted with at least one Group VIA element, yields CIGS(S) type absorber layers that adhere well to their substrate or base.
[00018] In one embodiment, the technique for preparing precursor films and compound layers for thin film solar cell fabrication includes forming an absorber layer by depositing a set of distinct layers over a top surface of the conductive layer, the set of distinct layers including at least four layers, with two of the layers being a pair of non- adjacent layers made of one of Cu, In and Ga, and the other two layers being made of the remaining two of the Cu, In and Ga, and then treating the set of distinct layers to form the absorber layer.
[00020] In another embodiment, solar cell fabrication includes forming a conductive layer over a sheet-shaped base; forming a semiconductor absorber layer over a surface of the conductive layer, wherein die semiconductor absorber layer comprises a Group VIA material; and forming an additional layer over the absorber layer, wherein one of the steps of forming the conductive layer and forming the additional layer includes at least one of Ru, Ir, and Os in the conductive layer and the additional layer, respectively. When a substrate type solar cell is fabricated, the at least one of Ru, Ir, and Os will exist in the conductive layer and the additional layer is transparent, whereas in a superstrate type solar cell, the at least one of Ru, Ir, and Os will exist in the additional layer and the substrate and the conductive layer are both transparent.
[00021] A solar cell, according to one embodiment of the invention, includes a sheet-shaped substrate; a conductive layer disposed over the sheet shaped substrate; an absorber layer disposed over the conductive layer, wherein the absorber layer includes at least one Group IB material, at least one Group IIIA material, and at least one Group VIA material; and an additional layer disposed over the absorber layer, wherein one of the conductive layer and the additional layer includes at least one of Ru, Os, and Ir. When the solar cell is of the substrate type, the at least one of Ru, Ir, and Os will exist in the conductive layer and the additional layer is transparent, whereas in a superstrate type solar cell, the at least one of Ru, Ir, and Os will exist in the additional layer and the substrate and the conductive layer are both transparent.
[00023] FIG. 1 is a cross-sectional view of a solar cell employing a Group IBπIAVIA absorber layer.
[00026] FIG. 3A shows a structure comprising a CIGS(S) absorber film on a preferred contact layer.
[00027] FIG. 3B shows a structure comprising a CIGS(S) absorber film on a nucleation layer.
[00028] As described in the discussion of prior art, the PVD techniques have the ability to alter the deposition sequence of Cu, In and Ga during the preparation of metallic precursors for the formation of CIGS type solar cell absorber layers by two-stage processes. In the electroplating approaches this has not been possible due to the sensitivity of the technique to the surface on which electroplating process is performed. Present invention overcomes the shortcomings of prior art electroplating techniques and provides more flexibility to formation of various metallic stacks comprising Cu, In and Ga and also addresses the issues of adhesion, yield, manufacturability and micro-scale morphological, structural and compositional uniformity.
[00030] The following examples will demonstrate the flexibility offered by using complex copper solutions for the formation of various metallic stacks for CIGS type absorber fabrication. In these examples, the following exemplary solutions are used for the various deposition steps. A) Copper deposition solution (SOLCu) comprises 0.1 M copper sulfate-penta hydrate, 0.5 M trisodium citrate and a pH of 11 , B) Ga deposition solution (SOLGa) comprises IM gallium chloride in glycerol and a pH of 2, and C) In deposition solution (SOLIn) is an In sulfamate solution purchased from Indium Corporation of America. This solution has a pH in the range of about 1-3, typically about 1.5.
[00031] For a typical CIGS solar cell, the absorber layer is in the range of 1-3 um thick, thinner layers being preferable because of lower materials cost. An absorber thickness of 2-2.5 um requires a copper layer thickness of about 200 nm, Ga layer thickness of about 92 nm and In layer of about 368 nm for a Cu/(In+Ga) molar ratio of about 0.9, and Ga/(Ga+In) molar ratio of about 25%. Therefore, in the examples below £ stacks with total Cu, In and Ga thicknesses of about 200 nm, 100 nm and 400 nm, respectively are electrodeposited to approximate the desired values given above. Example 1. Cu/Ga/Cu/In stack formation:
[00032] A glass/Mo base is used in the experiment. Mo is sputter deposited to a thickness of about 700 nm on the glass sheet Then SOLCu is employed to electroplate 150 nm thick Cu sub-layer over the Mo surface at a current density of 5 mA/cm 2 . The resulting Cu sub-layer is uniform and smooth with 3-5 nm surface roughness. A 100 nm thick Ga layer is deposited on the Cu sub-layer using SOLGa at a current density of 10 mA/cm 2 . A smooth and shiny silver-colored layer is obtained. SOLCu solution is utilized again to deposit 50 run thick Cu sub-layer over the Ga layer at a current density of 5 mA/cm 2 . No Ga is lost into the SOLCu during Cu plating since the plating potential of Cu with respect to a calomel electrode placed into the solution was measured to be in the (- 1 to -2 V) range. Such high cathodic potential protects the Ga layer from dissolving and also allows deposition of a small-grained and continuous Cu sub-layer on the Ga surface. After the formation of the 50 nm thick Cu sub-layer over the 100 run thick Ga layer, SOLIn is used at 15 mA/cm 2 current density to form a 400 nm thick In layer.
[00033] A glass/Mo base is used. Mo is sputter deposited to a thickness of about 700 nm on the glass sheet. Then SOLCu is employed to electroplate 150 nm thick Cu sub-layer over the Mo surface at a current density of 5 mA/cm 2 . The resulting Cu sublayer is uniform and smooth with 3-5 nm surface roughness. A 100 nm thick Ga layer is deposited on the Cu sub- layer using SOLGa at a current density of 10 mA/cm 2 . A smooth and shiny silver-colored layer is obtained. SOLCu solution is utilized again to deposit 10 nm thick Cu sub-layer over the Ga layer at a current density of 5 mA/cm 2 . After the formation of the 10 nm thick Cu sub-layer over the 100 nm thick Ga layer, SOLIn is used at 15 mA/cm 2 current density to form a 400 nm thick In layer. Over the In layer, another Cu sub-layer is plated using SoICu to a thickness of 40 nm. No In is lost into the SOLCu during Cu plating since the plating potential of Cu with respect to a calomel electrode placed into the solution was measured to be in the (-1 to -2 V) range. Such high cathodic potential protects the In layer from dissolving and also allows deposition of a small- grained and continuous Cu sub-layer on the In surface.
[00034] A glass/Mo base is used. Mo is sputter deposited to a thickness of about 700 nm on the glass sheet. Then SOLCu is employed to electroplate 150 run thick Cu sub-layer over the Mo surface at a current density of 5 mA/cm 2 . The resulting Cu sublayer is uniform and smooth with 3-5 nm surface roughness. A 400 nm thick In layer is deposited on the Cu sub-layer using SOLIn at a current density of 15 mA/cm 2 . SOLCu solution is utilized again to deposit 50 nm thick Cu sub-layer over the In layer at a current density of 5 mA/cm 2 . No In is lost into the SOLCu during Cu plating since the plating potential of Cu- with respect to a calomel electrode placed into the solution is measured to be in the (- 1 to -2 V) range. Such high cathodic potential protects the In layer from dissolving and also allows deposition of a small-grained and continuous Cu layer on the In surface. After the formation of the 50 nm thick Cu sub-layer over the 400 nm thick Ga layer, SOLGa is used at 5 mA/cm 2 current density to form a 100 nm thick Ga layer. Example 4. Cu/In/Cu/Ga/Cu stack formation:
[00035] A glass/Mo base is used. Mo is sputter deposited to a thickness of about 700 nm on the glass sheet. Then SOLCu is employed to electroplate 150 nm thick Cu sub-layer over the Mo surface at a current density of 5 mA/cm 2 . The resulting Cu sublayer is uniform and smooth with 3-5 nm surface roughness. A 400 nm thick In layer is deposited on the Cu sub-layer using SOLIn at a current density of 15 mA/cm 2 . SOLCu solution is utilized again to deposit 20 nm thick Cu sub-layer over the In layer at a current density of 5 mA/cm 2 . No In is lost into the SOLCu during Cu plating since the plating potential of Cu with respect to a calomel electrode placed into the solution is measured to be in the (-1 to -2 V) range. Such high cathodic potential protects the In layer from dissolving and also allows deposition of a small-grained and continuous Cu sub-layer on the In surface. After the formation of the 20 nm thick Cu sub-layer over the 400 nm thick In layer, SOLGa is used at 5 mA/cm 2 current density to form a 100 nm thick Ga layer. Over the Ga layer a 30 nm thick Cu sub-layer is formed using the SOLCu solution at a current density of 5 mA/cm 2 .
[00036] It should be noted that the metallic precursor stacks discussed in the above examples may have even more number of sub-layers. For example, the In layer may be divided into two or more In sub-layers. Similarly, Ga layer may be divided into two or more Ga sub-layers that may be distributed within the metallic stack. Although up to three Cu sub-layers are described in the examples above, more Cu sub-layers may also be formed and distributed within the electroplated metallic stack. By distributing Cu, In and Ga in electroplated metallic precursors several benefits may be obtained. One of these benefits is the easy intermixing/reaction between the thin sub-layers distributed within the stack during the reaction step. Another benefit is improved adhesion after reaction with a Group VIA material. For example, as opposed to the prior art electroplated Cu/In/Ga precursor stack, the electroplated Cu/Ga/Cu/In precursor stack of the present invention brings the Ga closer to the Mo interface. This improves adhesion of the compound to the Mo surface after reaction with Se and/or S and formation of the CIGS(S) compound layer. The Ga may be brought even closer to the contact layer interface, by τ for example, reducing the thickness of the Cu sub-layer deposited on the contact layer to a range of 2- 50 nm and then increasing the thickness of the Cu sublayer deposited over the Ga layer (see examples I and 2). In some RTP approaches a Se layer is deposited over a metallic precursor layer comprising Cu, In and Ga and then the whole structure is heated to elevated temperatures to react Se with the Cu, In and Ga and form CIGS. In such an approach, if the prior art electroplated Cu/In/Ga stack is employed and a Se film is deposited onto the Ga surface to form a Cu/In/Ga/Se structure, the morphology of the CIGS layer may be rough and non-uniform. The reason is the fact that Ga is a low melting metal with a melting temperature of less than 30 C. The In/Ga interface within this stack has even lower melting temperature since the eutectic composition of l6%In-84%Ga has a melting temperature of about 15.7 C. Therefore, even before any reaction between Se and the metallic stack initiates, the near- surface region of the metallic stack melts and causes balling. As the temperature is raised to react Se with the metallic stack situation may get even worse and rough morphology and compositional non-uniformity may result. In the present electroplated stacks a higher melting temperature layer, such as an In layer (Example 1) or a Cu layer/sub-layer (Examples 2 and 4) may be placed at the top of the metallic stack. Such higher melting phase at the surface of the stack reduces phenomenon of balling and improves the resulting morphology and the micro-scale compositional uniformity. The thickness of the Cu cap on the metallic stack (Examples 2 and 4) may be varied at will and may be in the range of 2-200 nm, preferably in the range of 5-50 nm. It should be noted that a metallic precursor stack comprising Cu, In and Ga, wherein, the Ga and In are separated from each other by a Cu layer or sub-layer has benefits. In stacks comprising material sequences of Ga/Cu/In, Cu/Ga/Cu/In, In/Cu/Ga, and/or Cu/In/Cu/Ga, the Ga and In phases are separated by a Cu phase and therefore do not form the low melting Ga-In region at their interface as mentioned above. Cu, in this case, acts as a full or partial barrier between Ga and In, slowing down or stopping intermixing between Ga and In and formation of low melting (below 30 C) compositions during or after fabrication of the precursor stacks.
[00037] Electroplated metallic stacks have certain properties that are not provided by stacks obtained by PVD. As discussed before, PVD has the flexibility of changing the deposition sequence of Cu, In and Ga. However, metallic precursors obtained by PVD may not end up to be the intended stacks. This is because PVD methods are relatively high energy. In other words material arriving onto the substrate comes with high energy that causes alloying between the depositing species and the species that were already on the substrate. For example, when Cu is deposited over In or Ga layers by evaporation or sputtering, what is obtained may not be InJCu or Ga/Cu stacks but layers comprising various alloys of these materials along with elemental phases, since In and Ga have low melting temperatures and arriving Cu species have high enough energy to cause intermixing between In and/or Ga and Cu . Wet techniques such as electroplating and electroless plating, when carried out at low temperature, such as at a temperature below the melting point of species depositing or species already on the substrate, have the unique ability to yield stacks with layers and/or sub-layers with well defined phases that can be obtained repeatably. For example, a Cu/Ga/Cu/In stack electroplated at 20 C is substantially non-alloyed, as explained before, due to the low temperature nature of electroplating and due to the presence of a Cu sub-layer between the Ga and In sub-layers. This way the starting phase content of the precursor is repeatable and known. Having a low-melting pure phase such as Ga or In buried in a precursor stack has certain benefits, especially for the case of rapid thermal processing during reaction with the Group VIA materials such as Se, S or Te. One of these benefits is to have an elemental liquid phase within the stack during the reaction period which gives the forming CIGS(S) compound a liquid environment to grow in. It is known that crystals or grains growing in a melted or liquid environment grow larger due to the high mobility of grain boundaries in such liquid flux. Large grain absorber material, such as CIGS(S) is one of the key ingredients of making high efficiency solar cells. If Cu/Ga/Cu/In stack was substantially alloyed, melting temperature of the alloys would be higher than the melting temperatures of the elemental phases of Ga and In.
[00039] In the examples above, each layer or sub-layer within the metallic stack is made of a pure element, i.e. Cu, In or Ga. It should be noted that, it is within the scope of the invention to include alloys and/or mixtures in the metallic stack. For example, at least one of the Cu sub-layers in the above examples may be replaced with a Cu-Ga alloy or mixture sub-layer, or a Cu-In alloy or mixture sub-layer. Similarly, any Ga or In layer may be replaced with an In-Ga mixture or alloy sub-layer. In cases where at least one layer or sub-layer is replaced with an alloy or mixture sub-layer or layer, the thicknesses of the rest of the layers and sub-layers within the stack may be adjusted to keep the overall Cu/(Ga+In) and Ga/(Ga+In) molar ratios at the desired levels.
[00040] It should be noted that in the exemplary stacks discussed so far a Cu sub-layer is first electroplated on the base and forms a repeatable surface over which an In layer or a Ga layer is electroplated. Then, another Cu sub-layer is electroplated using the complex solution forming a well-behaved Cu surface over which the stack may continue to be built by depositing another In and/or Ga sub-layer over the Cu sub-layer. Although the preferred method is to provide a Cu surface for the electrodeposition of an In and/or Ga layer, in some experiments we observed that a Cu/Ga/In stack may also be formed by plating In over the Ga surface directly. Having In coated over the low melting Ga surface and building a Cu/Ga/In stack has relative benefits in avoiding the morphology problems associated with the prior art Cu/In/Ga stack as explained before. In other words it is better to have a higher melting point In at the surface of the stack rather than having low melting Ga surface exposed to the Group VIA element during compound formation. This is further discussed in Provisional Patent Application Serial No. 60/729,846 filed October 24, 2005, entitled "Method and Apparatus for Thin Film Solar Cell Manufacturing", the contents of which are expressly incorporated by reference herein. In case a Cu sub-layer is provided in the stack over which an In or Ga sub-layer or layer is electroplated, the thickness of the Cu sub-layer may be as little as an atomic layer, just to convert the surface of the underlying layer comprising Ga and/or In into Cu. However, a thickness of at least 2 nm is preferred for this Cu sub-layer.
[00041] In the above examples, the widely used glass/Mo structures were employed as the base for electrodeposited stack layers. It is also possible to replace the glass substrate with a conductive or non-conductive sheet or foil such as a polyimide, stainless steel, aluminum (Al), aluminum alloy, Ti or Mo foil and deposit the contact layer Mo over the foil substrate. Since electrodeposition is surface sensitive, the nature of the contact layer over which electrodeposition is performed is especially important for preparing a metallic stack comprising Cu, In and Ga using electroplating.
[00043] The elements of the preferred group are Ruthenium (Ru), Iridium (Ir), Osmium (Os), Rhodium (Rh), Zirconium (Zr), Hafnium (Hf), Rhenium (Re), Scandium (Sc), Yitrium (Y), and Lanthanum (La). Out of these elements, three of them, namely Ru, Ir and Os are the most preferred materials as will be described later.
[00046] Macro and micro-scale non-uniformities in the thickness and morphology of sub-layers in a precursor film comprising at least one of Cu, In and Ga, cause morphological and compositional non-uniformities in the CIGS(S) absorber after Cu, and/or In, and/or Ga are reacted with a Group VIA material such as Se and/or S forming the CIGS(S) absorber. This topic has been discussed in detailed in U.S. Patent Application Publication No. 2005/0202589 (Sep. 15, 2005) and U.S. Patent Application Publication No. 2006/0121701 (Jun. 8, 2006) mentioned previously, and the contents of which are expressly incorporated by reference herein. Thickness non-uniformities and morphological and compositional non-uniformities in Group EBIIIAVIA compound thin films may result from poor wetting of the substrate surface by the depositing species and therefore may be minimized or eliminated by careful selection of the chemical composition of the surface on which a Group IB material and/or a Group HIA material and/or a Group VIA material is deposited. For example, Cu, In, Ga and Se nucleate well on materials from the most preferred group, thus forming small-grain, smooth and well adhering layers. This better nucleation property is universal for all deposition techniques. In other words, Cu, In, Ga layers nucleate well on Ru, Ir and Os surface when they are deposited by electroplating, evaporation, sputtering, chemical vapor deposition, ink deposition, plasma spraying, melt deposition, among many other techniques. Se and/or S are also expected to behave similarly.
[00047] The preferred embodiments of the present invention are shown in Figures 2A and 2B. In Figure 2A, a preferred contact layer 21 is deposited on a substrate 20. A metallic precursor layer 22 is then deposited over the preferred contact layer 21. The substrate 20 is a glass substrate or a conductive or insulating sheet or foil. The preferred contact layer 21 may have a thickness of 50-1000 nra and comprises at least one of the elements in the preferred group of Ru, Rh, Ir, Os, Zr, Hf and Re. The contact layer 21 most preferably comprises at least one of Ru, Ir and Os. It should be noted that preferred contact layer may be made of nitrides or other compounds of the elements of the preferred group or it may be made of alloys comprising at least one of the elements in the preferred group. For the case of Ru, Ir and Os, the preferred contact layer may be an oxide of these materials because these oxides are highly conductive, unlike oxides of many other materials. Oxides of Mo, Ta, Ti, W, etc., for example, are either high resistivity (>100 ohm-cm) or insulating depending on their composition. Ruθ2, on the other hand, has a resistivity of much lower than 0.1 ohm-cm, typically in the range of 10 "3 - 10 "4 ohm-cm. The metallic precursor layer 22 comprises Cu, In and Ga and optionally Se and/or S and/or Te. The metallic precursor layer may be deposited by various techniques such as PVD, CVD techniques, but is preferably electroplated on the preferred contact layer 21. The metallic precursor layer may be in the form of alloys, or mixtures of Cu, In, Ga and optionally a Group VIA material, or it may be in the form of metallic stacks such as those described previously. The structure of the Fig. 2A may be converted into the preferred structure shown into Fig. 3A after the formation of a CIGS(S) compound layer. In Figure 3 A the CIGS(S) layer 30 is formed over the preferred contact layer 21 and the preferred contact layer 21 forms a well adhering electrical contact to the CIGS(S) layer 30. It should be noted that part of the preferred contact layer 21 right at the interface 25 with the CIGS(S) layer 30 may be in the form of a selenide, and/or sulfide since certain degree of reaction between the preferred contact layer 21 and Group VIA materials and even with Cu, In and Ga is possible and may form a thinjnterface layer. If Te was also included in the absorber, a telluride phase may also be formed in the interface layer. The structure of Figure 3A may be used to fabricate an efficient solar cell with a structure similar to the one in Figure 1 by depositing additional layers over the CIGS(S) absorber layer. In Figure 2B, a nucleation layer 24 is deposited on a contact layer 23, which is previously deposited on a substrate 20. A metallic precursor layer 22 is then deposited over the nucleation layer 24. The substrate 20 is a glass substrate or a conductive or insulating sheet or foil. The contact layer 23 may have a thickness of 100-1000 run and comprises a conductive material, such as Mo, Ta, W, Ni, Cu, Ti, Cr etc. Practically any conductive material may be used as a contact layer in this case because diffusion barrier aspects of the nucleation layer 24 protects the contact layer from reacting with the metallic precursor layer 22 and/or with Group VIA materials. The nucleation layer may have a thickness of 1-300 nm, preferably 5-100 nm and comprises at least one of the elements in the preferred group of Ru, Rh, Ir, Os, Zr, Hf and Re. The nucleation layer most preferably comprises at least one of Ru, Ir and Os. It should be noted that the nucleation layer may be made of nitrides or other compounds of the elements of the preferred group or it may be made of alloys comprising at least one of the elements in the preferred group. The metallic precursor layer 22 comprises Cu, In and Ga and optionally Se and/or S and/or Te. The metallic precursor layer is preferably electroplated on the nucleation layer 24. The metallic precursor layer may be in the form of alloys, or mixtures of Cu, In, Ga and optionally a Group VIA material, or it may be in the form of metallic stacks such as those described previously. The structure of the Fig. 2B may be converted into the preferred structure shown into Fig. 3B after the formation of a CIGS(S) compound layer. In Figure 3B the CIGS(S) layer 30 is formed over the nucleation layer 24. It should be noted that part of the nucleation layer 24 right at the interface 25 with the CIGS(S) layer 30 may be in the form of a selenide and/or sulfide since certain degree of reaction between the nucleation layer 24 and Group VIA materials and even with Cu, In and Ga is possible and may form an interface layer. If the thickness of the nucleation layer is small (such as 1-50 nm), substantially all of the nucleation layer may be converted into a selenide, and/or sulfide during the formation of the CIGS(S) layer. If Te was also included in the absorber, a telluride phase may also be formed in the nucleation layer. The structure of Figure 3B may be used to fabricate an efficient solar cell with a structure similar to the one in Figure 1 by depositing additional layers, such as transparent conductive or semiconductive layers, over the CIGS(S) absorber layer.
[00048] The metallic precursor stack layers of the present invention may also comprise small amounts of dopants such as Na, K, Li, Sb, P etc. Dopants may be plated along with the layers or sublayers of the stack or may be plated as a separate micro-layer. For example, dopants such as K and Na may be included into the electroplating electrolytes of Cu, and/or In and/or Ga. Up to about 1% (molar) of dopants may be included into the precursor. The overall Cu/(In+Ga) molar ratio in the metallic precursor stack may be in the range of 0.7-1.2, preferably in the range of 0.8-1.0. The Ga/(Ga+In) molar ratio may be in the range of 0.01 -0.99, preferably in the range of 0.1 -0.4.
[00049] Reaction of metallic precursors (such as the ones shown in Figures 2A and 2B) with Group VIA materials may be achieved various ways. In one case the precursor layer is exposed to Group VIA vapors at elevated temperatures. These techniques are well known in the field and they involve heating the precursor layer to a temperature range of 350-600 0 C in the presence of at least one of Se vapors, S vapors, and Te vapors provided by sources such as solid Se, solid S, solid Te, H 2 Se gas, H 2 S gas CtC 1 for periods ranging from 5 minutes to 1 hour. In another case a layer or multi layers of Group VIA materials are deposited on the precursor layer and the stacked layers are then heated up in a furnace or in a rapid thermal annealing furnace and like. Group VIA materials may be evaporated on, sputtered on or plated on the precursor layer. Alternately inks comprising Group VIA nano particles may be prepared and these inks may be deposited on the precursor layers to form a Group VIA material layer comprising Group VIA nano particles. Dipping, spraying, doctor-blading or ink writing techniques may be employed to deposit such layers. Reaction may be carried out at elevated temperatures for times ranging from 1 minute to 30 minutes depending upon the temperature. As a result of reaction, the Group IBIIIA VIA compound is formed from the precursor and the structures shown in Figures 3A and 3B may be obtained.
[00050] Although certain embodiments of the present invention have been described using electrodeposited precursor layers and reaction of these layers with a Group VIA material, they are generally applicable to structures obtained by various other techniques such as evaporation, sputtering etc. For example, present inventor recognized certain unique features of Ru, Ir and Os (i.e. the most preferred materials) that make these materials especially attractive as contact materials or nucleation layers in Group IBπiAVIA compound solar cell structures.
[00051] As reviewed before, the standard contact material for a CIGS(S) type solar cell is Mo. A wide range of materials have also been evaluated by researchers as possible contact layers to CIGS(S) type solar cells. These materials are Au, W, Ta, Nb, Cr, V, Ti, Mn, Pd, Pt, TiN, Ni, Ni-P and ZrN. Motivations for identifying a new contact layer for the CIGS(S) solar cell changed from research group to research group and included; i) improving adhesion of the CIGS(S) layer to the substrate in processes that involve fabrication of a highly Cu-rich layer with Cu/(In+Ga) ratio of higher than 1.6 followed by a wet etching step, and ii) increasing the optical reflection of the back contact. Some of the materials listed above were found to be unsuitable as contact layers because they reacted extensively with the Group VIA materials and/or with Cu, In, Ga species. Some reportedly performed well. Mo, however, is the most widely used contact material in commercial CIGS(S) solar cell structures.
[00052] One important aspect to be taken into consideration in selecting a contact material for Group IBIIIAVIA compound films such as CIGS(S) layers and solar cells is the long term stability. Solar cells need to be built to last at least 20 years and possibly 30 years. They get as hot as 60-80 C during operation in desert areas. Therefore, short term chemical interactions between the contact layer and the absorber layer components, i.e. Cu, In, Ga, Se, S etc. during the formation of the CIGS(S) layer as well as the long term (20-30 years) interactions between the contact layer and the already formed CIGS(S) layer need to be taken into consideration. Table I provides information about interactions between six possible contact materials (Ru, Ir, Os, Rh, Pt, Pd) and Cu, In, Ga, Se and S. The solubilities and possible reaction products are listed in this table. Information for reaction products with Se and S was obtained from the publication titled "Platinum Group Metal Chalcogenides" by S. Dey and V. Jain (Platinum Metals Review, vol: 48, p:16, 2004). Information about solubilities and interactions between the six materials and Cu, In and Ga were obtained from the available binary phase diagrams which show the various new materials phases formed as a result of chemical interaction between two materials.
[000531 Data in Table 1 point out to important differences between a first group of materials comprising Ru, Os, Ir and a second group of materials comprising Rh, Pd and Pt, in terms of their interactions with Cu, In, Ga, Se and S. despite the fact that they all belong to a group of materials known as "platinum group metals". These differences can be summarized as follows: A) Ru, Os, and Ir do not have much solubility in Cu, whereas Rh, Pt and Pd have continuous solid solutions with Cu, B) there is very small solubility of Ru, Os and Ir in In wheras several Pd-In and Pt-In compounds exist suggesting extensive reactivity between these elements, C) although, data for Ga is lacking, it can be assumed that situation would be similar to the case of In, D) reacting with selenium, Ru, Os and Ir form a well defined single phase selenide, whereas Rh, Pt and Pd form multiple selenide phases with different crystalline structures, E) reacting with sulfur, Ru and Os form a well defined single phase sulfide, Ir forms two well defined sulfide phases with similar crystal structure, whereas Rh, Pt and Pd form multiple sulfide phases with different crystalline structures.
[00054] The unit cell lattice parameters for cubic RuSe 2 and RuS 2 are and a=5.61 A, respectively. Corresponding cell parameters for cubic OsSe2 and OsS 2 are and a=5.62A. The solar cell absorbers of CuInSe 2 , CuGaSe 2 , CuInS 2 , and CuGaS 2 have tetragonal structures with unit cell parameters of around C=I l. OδA) and (a=5.36A, c=10.49A), respectively. For absorbers containing Al and/or Te, the "a" values vary between about 5.3A and 6.1 A. Therefore, Ru(Se 1 S) 2 and Os(Se 1 S) 2 have excellent lattice match to CIGS(S) material (typically less than 10% lattice mismatch), and in general Ru(Se,S,Te) 2 and Os(Se,S,Te) 2 have very good lattice match to Group IBIHAVIA materials comprising at least one of Cu and Ag as Group IB material, at least one of In, Ga, Al as the Group iπA material and at least one of Se, S and Te as the Group VIA material. For example, for the case OfRuSe 2 and CuInSe 2 the lattice mismatch is only (5.93-5.78)/5.93 = 2.5%.
[00055] The lattice match between Group IBIIIAVIA absorbers and IrSe 2 is also good. IrSe 2 has orthorhombic structure with b=5.94A and c=3.74A. Therefore, the base of the unit cell matches well, in one crystalline direction, to the base of the tetragonal unit cell of the absorber. In the other direction (along a) the mismatch is about (22.44-20.95)/20.95 = 7%, for the case OfCuGaSe 2 , where 22.44A is four times the "a" value of the CuGaSe 2 absorber. IrS 2 and Ir 2 S 3 have unit cell parameters of b=5.62A, respectively. The discussion above demonstrates that the group of materials, comprising Ru, Os and Ir offer unique benefits as contact layers, nucleation layers or interfacial layers making electrical as well as physical contact to Group IBIHAVIA materials. One of these benefits, as reviewed before is the fact that chemical interactions between Cu, In, Ga and the group comprising Ru, Os and Ir are quite limited. Therefore, while growing, for example, a CIGS(S) compound layer on a Ru surface, the Ru layer does not extensively react with the elements of the compound and does not negatively influence the composition of the compound. If a contact layer interacted with at least one of Cu, In and Ga, it would form intermetallics by tying down at least part of the available Cu, In or Ga. This would, therefore, reduce the amount of that element in the absorber layer and thus deteriorate the composition and electrical properties of the absorber. This lack of interaction is also good for long term stability of the solar cell structure after the CIGS(S) layer is formed. Solar cells operating at elevated temperatures for 20-30 years need to be stable. This requires that the interface between the absorber layer and the contact or nucleation layer be stable.
[00056] The other benefit of using contact layers or interfacial layers comprising Ru, Os and Ir relates to how these materials interact with the Group VIA elements such as Se, S and Te. During the deposition of a Group IBIIIAVIA material on a surface comprising Ru, and/or Os and/or Ir, an interfacial layer forms between the Group IBIIIAVIA absorber and the Ru, and/or Os and/or Ir. This interfacial layer comprises at least one of a selenide, sulfide and telluride of Ru, and/or Os and/or Ir , which as we showed have good lattice match to the Group IBIIIAVIA layer. Lattice match reduces structural and electrical imperfections at the contact/absorber interface and it reduces strain and stress at that location. This may help grain growth and produce Group IBIIIAVIA absorber layers with columnar, large grains, which are superior for solar cell fabrication. In contrast, contact layers made of only Rh, Pt and Pd, when reacted with Se or S, or even Te, produce multi-phase interfacial layers as can be seen from Table 1. It would be appreciated that lattice mismatch between such interfacial layers and the Group IBπiAVIA absorber layers grown over them would be large and even un-defined (because there are so many different possible lattice structures) because the interfacial layer may have various chemical compositions and crystalline structures.
[00057] Additionally, present inventor found that reaction of materials from the most preferred group with Group VIA materials was much more limited than reaction of prior art Mo layers with the same Group VIA materials. For example, when a sputter deposited Mo layer and a sputter deposited Ru layer on glass substrates were selenized in H 2 Se containing atmosphere for 1 hour at 500 C, a Mo-selenide layer of about 200nm thickness formed on the surface of die Mo layer, whereas the thickness of Ru-selenide layer on the Ru layer was about 20 run. This shows that much thinner contact layers of materials from the most preferred list may be used in the solar cell structures, compared to the prior art Mo contact layers. For example, 500-700 run Mo layers, which are typical for prior art devices, may be replaced by 50-70 nm thick Ru layers and still protect the substrate or base from reactive environments comprising Group VIA materials. Furthermore, use of contact layers comprising at least one of Ru, Ir and Os allows the reaction temperature to be higher. For example, in two-stage processes that involve reacting a precursor layer comprising Cu, In and Ga with Iϊ2Se and/or H 2 S the reaction temperature is typically kept below 500 C. This is because, above this temperature, for example at temperatures close to 600 C, the Mo contact layer reacts excessively with die Se and/or S and the film adhesion to the substrate also worsens. It should be appreciated that use of the more inert group of materials from the most preferred group allows the reaction temperature to be close to, even higher than 600 C. Consequently, Cu(In,Ga)(Se,S)2 layers, or more generally Group IBIIIAVIA compound layers may be grown with larger grain size and better electrical and optical properties in shorter process times. This way the quality of the films may be improved while the throughput of the process is increased. This is important for RTP-type processes where substrates are processed one at a time. As an example, the reaction time for the formation of good quality Cu(In 5 Ga)Se 2 layer through reaction of a Cu(In 1 Ga) precursor with H 2 Se gas at 450 C may be 45-90 minutes, whereas, at a reaction temperature of 575 C, this may be achieved in 10-20 minutes.
[00058] Interaction of contact materials and oxygen and water vapor is also important for long term reliability of thin film materials. The standard prior-art contact of CIGS solar cells is Mo. When prior-art cells are exposed to humidity and/or oxygen, especially at elevated temperatures, a reaction takes place at the Mo/CIGS absorber that causes instabilities. Same is true for monolithically integrated CIGS modules built on glass substrates. In such structures, adjacent solar cells are connected in series by forming a ZπO/Mo interface, i.e. ZnO transparent layer or top electrode of one cell is shorted to the Mo contact layer or bottom electrode of the next cell. When the ZnO/Mo connection is exposed to moisture and/or oxygen for long periods of time, the resistance of the interface increases reducing the fill factor of the module, which is not acceptable in solar modules which need to have 20-30 year lifetime. Sensitivity of Mo to water vapor and oxygen is partly due to its high reactivity with oxygen, which is a Group VIA element just like Se and S. Molybdenum does not form a protective oxide layer on its surface. Therefore as it gets oxidized, the surface oxide grows and introduces high resistance at the Mo/CIGS and/or the ZnO/Mo interfaces. This contributes to the above mentioned instabilities in solar cells and modules employing Mo contacts. Use of a material from the preferred group, especially at least one of Ru, Ir and Os in place of Mo or on the surface of Mo in a CIGS type solar cell or module eliminates this problem. For example, if the structure of a CIGS solar cell is Mo/Ru/CIGS or Ru/CIGS, exposure of this structure to water vapor (H 2 O) and/or oxygen would result in a very thin (compared to a Mo layer) oxide layer on the Ru surface at the Ru/CIGS interface, just as reaction of Ru with HaSe and H2S results in a very thin (compared to a Mo layer) selenide or sulfide layer as described earlier. It should be noted that chemically, HjSe, H 2 S and H 2 O belong to the same group, as Se, S and O belong to the same Group VIA, and reactivity of Ru, Ir and Os is much less with these materials compared to reactivity of many other common metals such as Mo, W, Ta, Ti, Ni etc.
[00059] Thin nature of oxides formed on Ru, Ir and Os surfaces as well as their high electrical conductivity yield interfaces) with these materials (such as Ru/CIGS interface or ZnO/Ru interface that are stable in moisture and/or oxygen containing environment. This means longer lifetime for un-packaged or packaged solar cells or modules, wherein the packaging may not provide absolute hermetic sealing.
[00060] It should be noted that the contact layers comprising at least one of Ru, Os and Ir may have these materials in the form of alloys, compounds or mixtures. For example, Ru may be in the form of Ru, Ru-oxide, Ru-selenide, Ru-sulfide, Ru-telluride, Ru-sulfo-selenide, Ru-sulfo-teUuride, Ru-seleno-telluride, Ru-M alloys or mixtures where M is a metal or a Group IVA material, Ru-nitride, Ru-carbide etc. Similar arguments are valid for Os and Ir also. Although, formation of C-GroupVIA compound(s) at the interface between a "C" contact layer (where C may comprise Ru and/or Ir and/or Os) and a Group EBIIIA VIA absorber film may happen during the growth of the Group IBHIAVIA absorber layer on the surface of the "C" layer, it is also possible to deposit a C-Group VIA compound layer on a substrate and then grow the Group IBIIIAVIA compound layer over it. For example, a Ru(S,Se) 2 layer may first be grown on a conductive surface such as a Mo, Ti, Cr, Al, Ta, W, Ni etc surface. A high quality Cu(In 7 Ga)(Se 5 S) 2 absorber layer may then be grown on the Ru(S 1 Se) 2 layer. Such an approach still benefits from die excellent lattice match between Ru(S,Se)2 and Cu(In, Ga)(Se,S)2 as described above. It should be noted that when a Group EBIDAVIA absorber layer is grown on die commonly used Mo contact layers, a Mo-Group VIA interface forms between the Mo layer and the Group IBIILAVIA absorber. Since Mo forms many different sulfide, telluride and selenide phases, each with their own different crystalline structure, die lattice mismatch between these Mo-Group VIA interface layers and the Group IBIIIAVIA absorber layers is large. For example, during growth of a Cu(In,Ga)Se 2 absorber on a Mo surface, phases such as MoSe 2 (JCPDS diffraction file 29-914), Mo 3 Se 4 (JCPDS diffraction file 24-772), Mo 9 Seu (JCPDS diffraction file 40-908), Mo 15 SeI 9 (JCPDS diffraction file 39-786), etc., may form at the Mo/Cu(In,Ga)Se 2 interface. These phases have crystalline structures of hexagonal, rhombohedral, orthorhombic, and hexagonal, respectively. Some of the other attractive features of Ru, Ir and Os as contact layers to solar cells using Group IBIIIAVIA absorber films include better wetting characteristics of these materials by the Group IB and Group HIA elements. Copper, for example, wets Ru, 'Ir and Os surfaces well with small contact angle. This improves nucleation of Cu on such contact layer surfaces, allowing good coverage by thin Cu layers formed by a variety of techniques such as electroplating, chemical vapor deposition, atomic layer deposition, evaporation, sputtering, etc. For example, Cu layers as thin as 10 nm can be coated on Ru surface with excellent coverage, whereas this cannot be achieved on materials such as Mo, Ti, Ta etc. This is because the density of nucleation centers for Cu on Ru is much larger than on the other materials cited. Situation is similar for In and Ga also, i.e. nucleation of Ga and In on Ru, Ir and Os is better than their nucleation on prior art contact materials such as Mo. Good wetting plays a role even after the deposition of precursors or layers comprising at least one of Cu, In and Ga on the contact films or layers. For example, as described in U.S. Patent Application Publication Nos. 2005/0202589 and 2006/0121701 mentioned previously, after precursors including Cu, In and/or Ga, and optionally a Group VIA material are deposited on a substrate, they may be heated up to enhance alloying or reaction between the elements. If the wetting characteristics of the substrate surface or the contact layer are not good, morphology of the precursor layer deteriorates during heating. For example, low melting phases such as In and Ga may give rise to "balling" phenomenon which in turn introduces compositional non-uniformity in the plane of the film. This compositional non-uniformity, i.e. variation in the Cu/(In+Ga) and Ga/(Ga+In) ratios in the plane of the film, carries over to the Group IBIIIAVIA compound layer after the reaction is completed and the compound is formed. Solar cell efficiencies are low on such non-uniform compound layers because efficiency is a function of composition. Presence of a material from the most preferred list on the substrate surface minimizes or eliminates problems giving rise to compositional micro-scale non-uniformities, such as "balling", because nucleation and wetting are superior.
[00061] Solar cells may be fabricated on the compound layers of the present invention using materials and methods well known in the field. For example a thin (<0.1 microns) CdS layer may be deposited on the surface of the compound layer using the chemical dip method. A transparent window of ZnO may be deposited over the CdS layer using MOCVD or sputtering techniques. A metallic finger pattern is optionally deposited over the ZnO to complete the solar cell. ZnO layers alloyed or doped with In are especially suited for CIGS(S) solar cells. Such In-Zn-O (IZO) transparent conductors may be deposited by various techniques such as sputtering and may yield amorphous layers as opposed to ZnO films which are typically polycry stall ine in nature. CIGS(S) solar cells are moisture sensitive and amorphous layers are much better moisture barriers than polycrystalline layers since they don't have grain boundaries through which species may . diffuse. Therefore a CIGS(S) solar cell structure comprising amorphous IZO as at least part of its transparent conductive window layer is attractive for moisture resistance. Such a structure may be substrate/contact layer/CIGS(S)/CdS/IZO, with CdS layer being optional, or it may have ZnO or other transparent conductive oxides such as In-Sn-O either under or over the IZO layer.
[00062] Although the present invention is described with respect to certain preferred embodiments, modifications thereto will be apparent to those skilled in the art. For example, the contact layers or nucleation layers of the present invention may be used to form contacts to various important semiconducting layers belonging to the Group IIBVIA materials such as CdTe, ZnTe, CdSe, and their alloys, etc.

中文:
[0003]太阳能电池是将日光直接转变为电能的光电器件。最为常见的太阳能电池材料是单晶或多晶晶片形式的硅。然而,使用硅基太阳能电池产生的电的成本高于用较常规方法产生的电的成本。因此,从1970年代早期已努力降低用于地面用太阳能电池的成本。降低太阳能电池成本的一种方式是开发低成本的能在大面积衬底上沉积太阳能电池品质的吸收材料的薄膜生长技术和使用高产量、低成本的方法制造这些器件。
[0004]包括一些IB族(Cu、Ag、Au)、IIIA族(B、Al、Ga、In、T1)和VIA族(O、S、Se、Te、Po)材料或周期表元素的IBIIIAVIA族化合物半导体是用于薄膜太阳能电池结构的优异吸收材料。特别地,通常称作CIGS(S)、或Cu(In,Ga)(S,Se)2或CuIn1-xGax(SySe1-y)k(其中0≤x≤1,0≤y≤1且k为约2)的Cu、In、Ga、Se和S的化合物已经用于产生接近20%转化率的太阳能电池结构。在这些化合物族中,对于含有Ga和In(Ga的量为15-25%)的那些化合物,已获得最好的效率。含有更多Ga而不含In的吸收体产生较低的效率,认为这是因为富Ga材料中的较低载流子寿命。在另一方面,不含有Ga的吸收体具有约1eV的低带隙并且还对它们的衬底具有差的附着特性,从而限制它们的效率。含有IIIA族元素Al和/或VIA族元素Te的吸收体也显示出前景。因此,总之,包含i)IB族的铜,ii)IIIA族的In、Ga和Al中至少一种,和iii)VIA族的S、Se和Te中的至少一种的化合物对于太阳能电池应用具有极大的重要性。
[0005]在图1中显示了常规IBIIIAVIA族化合物光电电池例如Cu(In,Ga,Al)(S,Se,Te)2薄膜太阳能电池的结构。在衬底11例如玻璃片、金属片、绝缘箔或网、或者导电箔或网上制造器件10。在导电层13或接触层上生长包含Cu(In,Ga,Al)(S,Se,Te)2族材料的吸收膜12,导电层13或接触层预先沉积在衬底11上并且充当器件的电欧姆接触。图1的太阳能电池结构中最常使用的接触层或导电层是钼(Mo)。如果衬底本身是适当选择的导电材料(例如Mo箔),则可能不使用导电层13,因为衬底11此时可用作器件的欧姆接触。在金属箔具有反应性的情形中,导电层13也可充当扩散阻挡层。例如,包含诸如Al、Ni、Cu的材料的箔可用作衬底,条件是将阻挡体例如Mo层沉积在它们之上以保护它们免受Se或S蒸气。阻挡层通常沉积在箔的两侧来对其进行良好保护。在生长吸收膜12后,在该吸收膜上形成透明层14例如CdS、ZnO或CdS/ZnO叠层。辐射15穿过透明层14进入器件。还可在透明层14上沉积金属栅格(未示出)来减小器件的有效串联电阻。吸收膜12优选的电类型是p-型,而透明层14优选的电类型是n-型。然而,还可使用n-型吸收体和p-型窗层。图1的优选器件结构被称为“衬底型”结构。还可通过在透明覆盖层(superstrate)例如玻璃或透明聚合物箔上沉积透明导电层、并然后沉积Cu(In,Ga,Al)(S,Se,Te)2吸收膜、和最后通过导电层形成器件的欧姆接触来构造“覆盖层型”结构。在这种覆盖层结构中,光从透明覆盖层侧进入器件。可使用通过各种方法沉积的各种材料来提供图1中所示器件的各种层。
[0006]在使用IBIIIAVIA族化合物吸收体的薄膜太阳能电池中,电池效率是IB/IIIA摩尔比的强函数。如果组成中存在多于一种的IIIA族材料,则这些IIIA族元素的相对量或摩尔比也影响性能。例如,对于Cu(In,Ga)(S,Se)2吸收层,器件的效率是Cu/(In+Ga)摩尔比的函数。此外,一些重要的电池参数例如其开路电压、短路电流和填充系数也随IIIA族元素摩尔比即Ga/(Ga+In)摩尔比发生变化。一般而言,对于良好的器件性能,Cu/(In+Ga)摩尔比保持在约或低于1.0。作为替代方案,如果该比例大于1.0,则在溶液例如氰化物溶液中将膜蚀刻掉,以在构建太阳能电池器件前蚀刻掉过量的Cu-Se相。在另一方面,当Ga/(Ga+In)摩尔比增加时,吸收层的光学带隙增加,且因此太阳能电池的开路电压升高而短路电流通常可降低。对于薄膜沉积工艺重要的是有能力控制组成中的IB/IIIA摩尔比以及IIIA族组分的摩尔比。应注意的是,虽然化学式通常写为Cu(In,Ga)(S,Se)2,但对于该化合物更为准确的式是Cu(In,Ga)(S,Se)k,其中k典型地接近2但可以不精确为2。为了简便,将继续使用k值为2。还应注意的是,化学式中符号“Cu(X,Y)”表示X和Y从(X=0%和Y=100%)到(X=100%和Y=0%)的所有化学组成。例如,Cu(In,Ga)表示从CuIn到CuGa的所有组成。类似地,Cu(In,Ga)(S,Se)2表示具有的Ga/(Ga+In)摩尔比从0-1不等且Se/(Se+S)摩尔比从0-1不等的全部化合物族。
[0007]对于太阳能电池制造,得到高品质的Cu(In,Ga)Se2膜的首要技术是在真空室中将Cu、In、Ga和Se共蒸发到经加热的衬底上。然而,低的材料利用、高的设备费用、在大面积沉积中面临的困难和相对低的产量是共蒸发方法商业化中面临的一些挑战。
[0008]生长用于太阳能电池应用的Cu(In,Ga)(S,Se)2型化合物薄膜的另一种技术是两阶段工艺,其中首先将Cu(In,Ga)(S,Se)2材料的金属组分沉积到衬底上,并然后在高温退火过程中与S和/或Se反应。例如,对于CuInSe2生长,首先在衬底上沉积Cu和In的薄层,并然后将这种堆叠的前体层与Se在提高的温度下反应。如果反应气氛还包含硫,则可生长CuIn(S,Se)2层。在所述前体层中添加Ga,即,使用Cu/In/Ga堆叠的膜前体,则允许生长Cu(In,Ga)(S,Se)2吸收体。
[0009]在现有技术中已经使用溅射和蒸发技术来沉积所述前体叠层的含有IB族和IIIA族组分的层。在CuInSe2生长的情形中,例如,在衬底上顺序溅射沉积Cu和In层,然后在含Se气体的存在下于提高的温度下加热所述堆叠的膜并持续典型地大于约30分钟的时间,如U.S.4,798,660中所描述的。更为近期的美国专利6,048,442公开了一种方法,该方法包括溅射沉积包含Cu-Ga合金层和In层的堆叠前体膜以便在金属背电极层上形成Cu-Ga/In叠层,然后将该前体叠层膜与Se和S之一进行反应形成吸收层。美国专利6,092,669描述了用于产生这样的吸收层的溅射基装置。这些技术可产生高品质的吸收层和高效的太阳能电池,然而,它们具有设备投资成本高和生产率相对低的问题。尽管灵活改变形成金属叠层的元素的沉积顺序,但物理气相沉积(PVD)技术例如溅射和蒸发在形成具有稍后将描述的未合金化纯材料层的叠层的能力方面也具有某些缺点。
[00010]美国专利4,581,108中描述的一种现有技术方法利用低成本的电沉积方法用于金属前体的制备。在这种方法中,首先在覆盖有Mo的衬底上电沉积Cu层。然后进行In层的电沉积和在含有Se的反应气氛中加热所述沉积的Cu/In叠层以获得CIS膜。虽然本质上成本低,但发现这些技术均产生与Mo接触层附着性差的CIS膜。在文献(“Low Cost Thin Film Chalcopyrite Solar Cells”,Proceedingsof 18th IEEE Photovoltaic Specialists Conf.,1985,p.1429)中证明了CIS和CIGS生长的Cu/In和Cu/In/Ga层的电沉积和硒化。一个问题经确定是在太阳能电池加工期间化合物膜的剥落。之后,在另一篇参考文献(“Low Cost Methods for the Production ofSemiconductor Films for CIS/CdS Solar Cells”,Solar Cells,vol.21,p.65,1987)中研究者研究了通过上述方法获得的Mo/CuInSe2界面的横截面,并发现CuInSe2对Mo接触层具有差的附着性。
[00011]如上所述,Mo是CIS或GIGS型太阳能电池中最常使用的欧姆接触材料(或图1中的导电层)。图1的导电层13或接触层具有多种功能并且必须满足一定标准。接触层必须呈相对惰性,从而不与Se、Te或S或者CIS或GIGS层本身广泛反应。其还起到从衬底到CIS或GIGS层内的杂质扩散的阻挡体的作用,或者保护衬底不与Se、S或Te反应。其必须与太阳能电池具有良好的欧姆接触并且提供良好的光反射,使得特别在非常薄的器件结构中,到达器件背部的光子被反射并且提供更多要收集的光生载流子。发现钼很大程度上提供这种性质且因此已广泛用作接触层或欧姆接触层,尽管一些研究者在他们的实验中还使用金(Au)(见例如,C.Huang等,Solar Energy Materialsand Solar Cells,vol:82,p.553,(2004))。在最近的文献中,出于确定产生最稳定和可重复性能的材料的目的,Orgassa等对钨(W)、Mo、钽(Ta)、铌(Nb)、铬(Cr)、钒(V)、钛(Ti)和锰(Mn)作为CIGS太阳能电池的背接触进行了评价(见:Thin Solid Films,vol.431,p.387(2003))。他们发现W、Mo、Ta和Nb在CIGS沉积加工期间呈惰性,所述沉积加工是共蒸发方法。在CIGS膜生长期间,其它金属与Se反应并且一些被完全消耗进入生长中的层内。研究者断定,W、Ta和Nb可替代Mo作为CIGS太阳能电池的欧姆接触金属。美国专利6,307,148描述了这样的方法,该方法中,在形成混合有Cu硫化物或铜硒化物相的富Cu(Cu与IIIA族金属比例高于1.6)铜铟或铜铟镓硫化物或硒化物化合物层之前,在Mo接触层上方涂覆钯(Pd)或铂(Pt)的界面层。然后在KCN溶液中对该混合相材料进行蚀刻以蚀刻掉Cu硫化物或Cu硒化物相,从而留下太阳能电池级铜铟硒化物或硫化物层。据称,当不存在Pd或Pt界面层时,如果Cu与IIIA族比例大于1.6,则KCN蚀刻步骤导致膜剥落问题。具有Pd或Pt界面层时,膜在KCN蚀刻步骤后没有剥落,即使它们的Cu与IIIA族比例大于1.6。美国专利5,028,274使用碲(Te)界面层来增强CIS膜对选自包含Mo、W、Ta、Ti、Au和氮化钛(TiN)的组的接触层的附着性。美国专利4,915,745列举Mo、W、Au、镍(Ni)和磷化镍(Ni-P)作为CIGS型太阳能电池的可能接触层。在美国专利5,695,627中,研究者使用来自Mo、Ti、Cr和Pt的金属作为接触层来电镀Cu-In-Se-S。美国专利5,676,766列出Cr、Ti、Ta和TiN作为中间层来改善附着性。在美国专利5,626,688中,述及Mo、TiN、Pd和Pt作为CIS型膜的接触体。在美国专利5,501,786中,使用Mo、TiN和氮化锆(ZrN)作为基底导体,在该基底导体上方镀覆包含Se颗粒的层。
[00012]湿加工技术例如电沉积和无电沉积,虽然成本比PVD方法例如蒸发和溅射低,但具有它们独有的挑战。例如,与PVD技术相比,电沉积或电镀技术具有大很多的衬底敏感性。在PVD方法中,金属A可蒸发或溅射沉积在金属B上,并且沉积顺序可任意反转,即金属B可沉积在金属A上或者可形成例如A/B/A/B或B/A/B/A的叠层。然而,在电沉积加工中,在形成包含各种不同金属的金属叠层中存在限制。例如,如上文所回顾,现有技术方法在涂覆Mo的衬底上电镀Cu、In和任选的Ga以形成Cu/In和Cu/In/Ga叠层,用以制造Mo/CIS和Mo/CIGS结构,这些结构然后用于太阳能电池制造。选择Cu/In和Cu/In/Ga电沉积顺序的原因之一在于这样的事实,Cu、In和Ga具有非常不同的标准镀覆电势。在水溶液中Cu/Cu2+、In/In3+和Ga/Ga3+金属/离子对的摩尔标准电极电势分别为约+0.337V、-0.342V和-0.52V。这意味着可以在低的负电压下镀覆Cu。另一方面对于In沉积,需要较大的负电压。对于因析氢而具有挑战性的Ga沉积,需要甚至更大的负电压。因此,为了形成含有Cu、In和Ga的叠层,典型地首先电镀Cu。然后接着进行In的沉积和之后的Ga沉积,使得在第一金属上方镀覆第二金属时,第一金属不溶解到第二金属的电解质中。因此,现有技术方法使用以该顺序电镀的Cu/In/Ga叠层。然而,在硒化后这样的叠层产生具有差形貌和对基底或上述涂覆Mo的衬底具有差附着性的化合物层。
[00013]为形成Cu(In,Ga)Se2层而使用电沉积前体的其它尝试包括,进行Cu-Ga膜的电沉积,接着进行Cu-In-Se膜的电沉积,从而形成Cu-Ga/Cu-In-Se叠层;和将该叠层在600C退火(Friedfeld等,Solar Energy Materials and Solar Cells,vol:58,p:375,1999)。Zank等(Thin Solid Films,vol:286,p:259,1996)在玻璃/Mo衬底上溅射沉积Cu-Ga合金膜。他们然后由单一镀液电镀In-Ga膜,从而形成Cu-Ga/In-Ga叠层。然后将该叠层与Se反应形成化合物。这种方法不是低成本的,这是因为Cu-Ga合金溅射靶的制备本身是昂贵的并且在溅射方法中靶材的利用非常低(典型地低于40%)。Ganchev等由单一镀液电沉积Cu-In-Ga前体膜,并且在硒化该前体层后获得Cu(In,Ga)Se2层(Thin Solid Films,vol:511-512,p:325,2006)。
[00014]包含Cu、In和/或Ga的前体膜中亚层厚度和形貌的宏观及微观不均匀性,导致在Cu和/或In和/或Ga与VIA族材料例如Se和/或S反应形成CIGS(S)吸收体后CIGS(S)吸收体的形貌和组成的不均匀性。在我们的美国专利申请公开No.2005/0202589(2005年9月15日)和美国专利申请公开No.2006/0121701(2006年6月8日)中详细讨论了该主题。
[00015]正如以上简述所证实的,为了CIGS型吸收层更好的机械、结构、组成和电性能,仍然需要开发CIGS型太阳能电池的替代性欧姆接触材料。在形成各种同时包含Cu、In和Ga的金属前体叠层中,还需要提供所具有的灵活性类似于更加高成本的PVD技术的那些灵活性的低成本电沉积方法,这是因为仅包含Cu和In或者仅包含Cu和Ga的前体会提供CuIn(S,Se)2或CuGa(S,Se)2吸收层,这些吸收层产生的太阳能电池的效率比关于Cu(In,Ga)(S,Se)2材料所证明的20%低很多。还需要这样的电镀前体膜,该前体膜在与至少一种VIA族元素反应时产生CIGS(S)型吸收层,这些吸收层良好地附着至它们的衬底或基底。
[00018]在一个实施方案中,制备用于薄膜太阳能电池制造的前体膜和化合物层的技术包括,通过在导电层的上表面上方沉积一组相异层来形成吸收层,该组相异层包括至少4个层,其中2个层是一对由Cu、In和Ga之一制成的非相邻层,而另2个层由Cu、In和Ga中剩余的两种制成,然后处理该组相异层以形成吸收层。
[00020]在另一个实施方案中,太阳能电池制造包括:在片状基底上方形成导电层;在该导电层的表面上方形成半导体吸收层,其中该半导体吸收层包含VIA族材料;和在该吸收层上方形成附加层,其中形成导电层和形成附加层的步骤之一将Ru、Ir和Os中的至少一种分别包括在导电层和附加层中。当制造衬底型太阳能电池时,Ru、Ir和Os中的至少一种将存在于导电层中并且附加层是透明的,而在覆盖层型太阳能电池中,Ru、Ir和Os中的至少一种将存在于附加层中并且衬底和导电层均是透明的。
[00021]根据本发明一个实施方案的太阳能电池包括:片状衬底;置于该片状衬底上方的导电层;置于该导电层上方的吸收层,其中该吸收层包括至少一种IB族材料、至少一种IIIA族材料和至少一种VIA族材料;和置于所述吸收层上方的附加层,其中导电层和附加层之一包括Ru、Os和Ir中至少一种。当太阳能电池是衬底型时,Ru、Ir和Os中的至少一种将存在于导电层中并且附加层是透明的,而在覆盖层型太阳能电池中,Ru、Ir和Os中的至少一种将存在于附加层中并且衬底和导电层均是透明的。
[00023]图1是使用IBIIIAVIA族吸收层的太阳能电池的横截面图。
[00026]图3A显示了在优选接触层上包含CIGS(S)吸收膜的结构。
[00027]图3B显示了在成核层上包含CIGS(S)吸收膜的结构。
[00028]如现有技术的讨论中所描述,在为通过两阶段工艺形成CIGS型太阳能电池吸收层而制备金属前体期间,PVD技术具有改变Cu、In和Ga的沉积顺序的能力。在电镀方法中这一直是不可能的,因为该技术对其上进行电镀加工的表面的敏感性。本发明克服了现有电镀技术的缺点,并且向包含Cu、In和Ga的各种金属叠层的形成提供更大的灵活性,还解决了附着性、产率、可制造性和微观尺度形貌、结构及组成均匀性的问题。
[00030]下面的实施例将证明为形成用于CIGS型吸收层制造的各种金属叠层而使用络合铜溶液所提供的灵活性。在这些实施例中,对于各个沉积步骤使用下面的示例性溶液。A)铜沉积溶液(SOLCu),包含0.1M五水硫酸铜、0.5M柠檬酸三钠并且pH为11,B)Ga沉积溶液(SOLGa),包含1M在甘油中的氯化镓并且pH为2,和C)In沉积溶液(SOLIn),该溶液是购自Indium Corporation of America的氨基磺酸铟溶液。该溶液具有约1-3、典型地约1.5的pH。
[00031]对于典型的CIGS太阳能电池,吸收层是1-3μm厚,因为较低的材料成本而优选较薄的层。对于约0.9的Cu/(In+Ga)摩尔比和约25%的Ga/(Ga+In)摩尔比,2-2.5μm的吸收体厚度需要约200nm的铜层厚度、约92nm的Ga层厚度和约368nm的In层。因此,在下面的实施例中,电沉积分别具有约200nm、100nm和400nm的总Cu、In和Ga厚度的叠层以接近上面给出的所需值。
[00032]在该实验中使用玻璃/Mo基底。在玻璃片上溅射沉积Mo至约700nm的厚度。然后使用SOLCu以5mA/cm2的电流密度在Mo表面上方电镀150nm厚的Cu亚层。所得Cu亚层是均匀且平滑的,具有3-5nm的表面粗糙度。使用SOLGa以10mA/cm2的电流密度在Cu亚层上沉积100nm厚的Ga层。获得平滑且光亮的银色层。再次使用SOLCu溶液以5mA/cm2的电流密度在Ga层上方沉积50nm厚的Cu亚层。在Cu镀覆期间没有Ga损失到SOLCu中,这是因为Cu相对于置入溶液内的甘汞电极的镀覆电势经测量在(-1至-2V)范围内。这样高的阴极电势保护Ga层不溶解并且还允许在Ga表面上沉积小晶粒且连续的Cu亚层。在100nm厚Ga层上方形成50nm厚的Cu亚层后,使用SOLIn以15mA/cm2的电流密度形成400nm厚的In层。
[00033]使用玻璃/Mo基底。在玻璃片上溅射沉积Mo至约700nm的厚度。然后使用SOLCu以5mA/cm2的电流密度在Mo表面上方电镀150nm厚的Cu亚层。所得Cu亚层是均匀且平滑的,具有3-5nm的表面粗糙度。使用SOLGa以10mA/cm2的电流密度在Cu亚层上沉积100nm厚的Ga层。获得平滑且光亮的银色层。再次使用SOLCu溶液以5mA/cm2的电流密度在Ga层上方沉积10nm厚的Cu亚层。在100nm厚的Ga层上方形成10nm厚的Cu亚层后,使用SOLIn以15mA/cm2的电流密度形成400nm厚的In层。在该铟层上方,使用SolCu镀覆另一个Cu亚层至40nm的厚度。在Cu镀覆期间没有In损失到SOLCu中,这是因为Cu相对于置入溶液内的甘汞电极的镀覆电势经测量在(-1至-2V)范围内。这样高的阴极电势保护In层不溶解并且还允许在In表面上沉积晶粒小且连续的Cu亚层。
[00034]使用玻璃/Mo基底。在玻璃片上溅射沉积Mo至约700nm的厚度。然后使用SOLCu以5mA/cm2的电流密度在Mo表面上方电镀150nm厚的Cu亚层。所得Cu亚层是均匀且平滑的,具有3-5nm的表面粗糙度。使用SOLIn以15mA/cm2的电流密度在Cu亚层上沉积400nm厚的In层。再次使用SOLCu溶液以5mA/cm2的电流密度在In层上方沉积50nm厚的Cu亚层。在Cu镀覆期间没有In损失到SOLCu中,这是因为Cu相对于置入溶液内的甘汞电极的镀覆电势经测量在(-1至-2V)范围内。这样高的阴极电势保护In层不溶解并且还允许在In表面上沉积晶粒小且连续的Cu层。在400nm厚的Ga层上方形成50nm厚的Cu亚层后,使用SOLGa以5mA/cm2的电流密度形成100nm厚的Ga层。
[00035]使用玻璃/Mo基底。在玻璃片上溅射沉积Mo至约700nm的厚度。然后使用SOLCu以5mA/cm2的电流密度在Mo表面上方电镀150nm厚的Cu亚层。所得Cu亚层是均匀且平滑的,具有3-5nm的表面粗糙度。使用SOLIn以15mA/cm2的电流密度在Cu亚层上沉积400nm厚的In层。再次使用SOLCu溶液以5mA/cm2的电流密度在In层上方沉积20nm厚的Cu亚层。在Cu镀覆期间没有In损失到SOLCu中,这是因为Cu相对于置入溶液内的甘汞电极的镀覆电势经测量在(-1至-2V)范围内。这样高的阴极电势保护In层不溶解并且还允许在In表面上沉积晶粒小且连续的Cu亚层。在400nm厚的In层上方形成20nm厚的Cu亚层后,使用SOLGa以5mA/cm2的电流密度形成100nm厚的Ga层。使用SOLCu溶液以5mA/cm2的电流密度在Ga层上方形成30nm厚的Cu亚层。
[00036]应注意的是,上面实施例中讨论的金属前体叠层可具有甚至更多数目的亚层。例如,In层可分成两个或更多In亚层。类似地,Ga层可分成两个或更多可分布在金属叠层内的Ga亚层。虽然在上面实施例中描述了至多三个Cu亚层,但还可形成更多Cu亚层并将其分布在电镀的金属叠层内。通过将Cu、In和Ga分布在电镀的金属前体中,可获得若干益处。这些益处之一是在反应步骤期间分布在叠层内的薄亚层之间易于混合/反应。另一个益处是在与VIA族材料反应后附着性得到改善。例如,与现有技术的电镀Cu/In/Ga前体叠层相对的是,本发明的电镀Cu/Ga/Cu/In前体叠层使Ga更加接近Mo界面。这改善化合物在与Se和/或S反应并形成CIGS(S)化合物层后对Mo表面的附着性。例如通过将沉积在接触层上的Cu亚层的厚度减小至2-50nm并然后提高沉积在Ga层上方的Cu亚层的厚度(见实施例1和2),可使Ga甚至更接近层界面。在一些RTP方法中,在包含Cu、In和Ga的金属前体层上方沉积Se层,并然后将整个结构加热至提高的温度以使Se与Cu、In和Ga反应形成CIGS。在这种方法中,如果使用现有技术的电镀Cu/In/Ga叠层并且将Se膜沉积到Ga表面形成Cu/In/Ga/Se结构,则CIGS层的形貌可能是粗糙和不均匀的。原因在于Ga是熔化温度小于30C的低熔点金属。该叠层内的In/Ga界面具有甚至更低的熔化温度,这是因为16%In-84%Ga的低共熔组合物具有约15.7C的熔化温度。因此,甚至在Se和金属叠层之间的任何反应开始之前,金属叠层的近表面区域熔化并导致成球。随着升高温度以使Se与金属叠层反应,情况可变得甚至更糟并且可产生粗糙形貌和组成不均匀性。在本电镀叠层中,可在金属叠层的顶部放置熔化温度较高的层例如In层(实施例1)或Cu层/亚层(实施例2和4)。在叠层表面的这种较高熔点的相减少成球现象并且改善所得形貌和微观组成均匀性。金属叠层上Cu盖层(cap)的厚度(实施例2和4)可任意变化并且在2-200nm、优选5-50nm内。应注意的是,其中Ca和In被Cu层或亚层互相隔开的包含Cu、In和Ga的金属前体叠层具有益处。在包含Ga/Cu/In、Cu/Ga/Cu/In、In/Cu/Ga和/或Cu/In/Cu/Ga的材料顺序的叠层中,Ga相和In相如上述被Cu相隔开且因此在它们的界面处不形成低熔点Ga-In区域。在这种情形中,Cu充当Ga和In之间的全部或部分阻挡体,在前体叠层制造期间或之后减缓或终止Ga和In之间的混合及低熔点(低于30C)组合物的形成。
[00037]电镀的金属叠层具有通过PVD获得的叠层所不能提供的某些性能。如上所述,PVD具有改变Cu、In和Ga的沉积顺序的灵活性。然而,通过PVD获得金属前体可能并不最终成为预计的叠层。这是因为PVD方法具有相对高的能量。换言之,到达衬底上的材料伴有高能量,该高能量导致沉积物质和衬底上已有物质之间的合金化。例如,当通过蒸发或溅射在In或Ga层上方沉积Cu时,所获得的可能不是In/Cu或Ga/Cu叠层,而是连同单质相包含这些材料的各种合金的层,这是因为In和Ga具有低熔化温度,并且到达的Cu物质具有导致In和/或Ga与Cu之间混合的足够高能量。湿法技术例如电镀或无电镀覆,在低温下例如在低于沉积物质或衬底上已有物质的熔点的温度下进行时,具备产生这样的叠层的独特能力,所述叠层具有的层和/或亚层具备明确界定的相并且可重复获得。例如,在20C下电镀的Cu/Ga/Cu/In叠层基本上是非合金化的,如前文所说明,这是因为电镀的低温性质以及因为Ga和In亚层之间存在Cu亚层。这样,前体的起始相内含物是可重复且已知的。特别对于与VIA族材料如Se、S或Te反应期间的快速热加工情形,具备埋在前体叠层中的低熔点纯相如Ga和In具有某些益处。这些益处之一是在反应阶段期间叠层内具有单质液体相,该相为形成中的CIGS(S)化合物提供从中生长的液体环境。已知在熔化或液体环境中生长的晶体或晶粒由于这种液体熔剂中晶界的高迁移率而生长得更大。大晶粒吸收材料例如CIGS(S)是制造高效率太阳能电池的关键成分之一。如果Cu/Ga/Cu/In叠层是基本合金化的,则合金的熔化温度会高于Ga或In的单质相的熔化温度。
[00039]在上面的实施例中,金属叠层内的各个层或亚层由纯元素即Cu、In或Ga制成。应注意的是,在金属叠层中包含合金和/或混合物是在本发明的范围内。例如,上述实施例中的至少一个Cu亚层可用Cu-Ga合金或混合亚层或者Cu-In合金或混合亚层替代。类似地,任何Ga或In层可用In-Ga混合物或合金亚层替代。在至少一个层或亚层用合金或混合亚层或层替代的情形中,可调节叠层内其余层或亚层的厚度以保持总Cu/(Ga+In)和Ga/(Ga+In)摩尔比处于所需水平。
[00040]应注意的是,在到目前为止所讨论的示例性叠层中,首先将Cu亚层电镀在基底上并形成可重复的表面,在该表面上方电镀In层或Ga层。然后,使用络合物溶液电镀另一个Cu亚层,从而形成表现良好的Cu表面,在该Cu表面上方通过在Cu亚层上方沉积另一个In和/或Ga亚层继续构建叠层。虽然优选的方法为In和/或Ga层的电沉积提供Cu表面,但在一些实验中观测到,还可通过在Ga表面上方直接镀覆In来形成Cu/Ga/In叠层。使In涂覆在低熔点Ga表面上方并且构建Cu/Ga/In叠层具有相对的益处,这些益处在于避免了前面所说明的与现有技术的Cu/Ga/In叠层有关的形貌问题。换言之,在化合物形成期间,在叠层表面最好具有较高熔点的In,而不是将低熔点Ga表面暴露于VIA族元素。在2005年10月24日提交的题为“Methodand Apparatus for Thin Film Solar Cell Manufacturing”的临时专利申请No.60/729,846对此另外进行了讨论,通过引用将该申请的内容明确合并到本文中。如果在叠层中提供上方电镀了In或Ga亚层或层的Cu亚层,则Cu亚层的厚度可小至原子层,仅将包含Ga和/或In的下方层的表面转换成Cu。然而,对于该Cu亚层优选至少2nm的厚度。
[00041]在上述实施例中,采用广泛使用的玻璃/Mo结构用作电沉积叠层的基底。还有可能用导电或不导电的片或箔例如聚酰亚胺、不锈钢、铝(Al)、铝合金、Ti或Mo箔替代玻璃衬底以及在箔衬底上方沉积接触层Mo。因为电沉积具有表面敏感性,上方进行电沉积的接触层的性质对于使用电镀制备包含Cu、In和Ga的金属叠层特别重要。
[00043]优选组的元素是钌(Ru)、铱(Ir)、锇(Os)、铑(Rh)、锆(Zr)、铪(Hf)、铼(Re)、钪(Sc)、钇(Y)和镧(La)。在这些元素中,它们中的三种即Ru、Ir和Os是稍后将描述的最优选的材料。
[00046]包含Cu、In和Ga中至少一种的前体膜中的亚层厚度和形貌的宏观和微观不均匀性,导致在Cu和/或In、和/或Ga与VIA族材料例如Se和/或S反应形成CIGS(S)吸收体后CIGS(S)吸收体中的形貌和组成不均匀性。在前文述及的美国专利申请公开No.2005/0202589(2005年9月15日)和美国专利申请公开No.2006/0121701(2006年6月8日)中详细讨论了该主题,并且通过引用将所述申请的内容明确合并到本文中。IBIIIAVIA族化合物薄膜中的厚度不均匀性和形貌及组成不均匀性可由沉积物质对衬底表面差的润湿引起,且因此可通过表面(其上沉积IB族材料和/或IIIA族材料和/或VIA族材料)化学组成的仔细选择得以最小化或被消除。例如,Cu、In、Ga和Se在来自最优选组的材料上成核良好,因此形成晶粒小、平滑且附着良好的层。这种较好的成核性能对于所有沉积技术是通用的。换言之,Cu、In、Ga层在它们通过电镀、蒸发、溅射、化学气相沉积、油墨沉积、等离子喷涂、熔体沉积和许多其它技术进行沉积时,在Ru、Ir和Os表面上成核良好。还预期Se和/或S具有类似表现。
[00047]在图2A和2B中显示了本发明的优选实施方案。在图2A中,在衬底20上沉积优选的接触层21。然后在该优选的接触层21上方沉积金属前体层22。衬底20是玻璃衬底或者是导电或绝缘的片或箔。优选的接触层21可具有50-1000nm的厚度并且包含Ru、Rh、Ir、Os、Zr、Hf和Re的优选组中的至少一种元素。接触层21最优选包含Ru、Ir和Os中的至少一种。应注意的是,优选的接触层可由优选组元素的氮化物或其它化合物制成,或者其可由包含优选组中的至少一种元素的合金制成。对于Ru、Ir和Os的情形,优选的接触层可以是这些材料的氧化物,这是因为这些氧化物是高度导电的,不同于许多其它材料的氧化物。例如,Mo、Ta、Ti、W等的氧化物取决于它们的组成或者是具有高电阻率(>100ohm-cm)或者是绝缘的。在另一方面,RuO2具有比0.1ohm-cm低很多的电阻率,典型地在10-3-10-4ohm-cm范围内。金属前体层22包含Cu、In和Ga及任选的Se和/或S和/或Te。金属前体层可通过各种技术例如PVD、CVD技术进行沉积,但优选电镀在优选的接触层21上。金属前体层可以是Cu、In、Ga和任选的VIA族材料的合金或混合物形式,或者其可以是例如前述那些的金属叠层的形式。在形成CIGS(S)化合物层后,图2A的结构可转变成图3A中所示的优选结构。在图3A中,在优选的接触层21上方形成CIGS(S)层30,并且优选的接触层21形成对CIGS(S)层30附着良好的电接触。应注意的是,恰好在与CIGS(S)层30的界面25处的优选接触层21的一部分可以是硒化物和/或硫化物形式,这是因为优选接触层21和VIA族材料以及甚至与Cu、In和Ga之间一定程度的反应是可能的并且可形成薄界面层。如果吸收体中还包括Te,还可在界面层中形成碲化物相。可使用图3A的结构通过在CIGS(S)吸收层上方沉积附加层来制造有效的太阳能电池,该太阳能电池具有的结构类似于图1中的结构。在图2B中,在接触层23上沉积成核层24,所述接触层23预先沉积在衬底20上。然后在成核层24上方沉积金属前体层22。衬底20是玻璃衬底或者是导电或绝缘的片或箔。接触层23可具有100-1000nm的厚度并且包含导电材料例如Mo、Ta、W、Ni、Cu、Ti、Cr等。实际上在这种情形中可使用任何导电材料作为接触层,因为成核层24的扩散阻挡方面防护接触层不与金属前体层22和/或与VIA族材料反应。成核层可具有1-300nm、优选5-100nm的厚度,并且包含Ru、Rh、Ir、Os、Zr、Hf和Re的优选组中的至少一种元素。成核层最优选包含Ru、Ir和Os中的至少一种。应注意的是,成核层可由优选组中元素的氮化物或其它化合物制成,或者其可由包含优选组中至少一种元素的合金制成。金属前体层22包含Cu、In和Ga及任选的Se和/或S和/或Te。金属前体层优选电镀在成核层24上。金属前体层可以是Cu、In、Ga和任选的VIA族材料的合金或混合物形式,或者其可以是例如前述那些的金属叠层的形式。在形成CIGS(S)化合物层后,图2B的结构可转变成图3B中所示的优选结构。在图3B中,在成核层24的上方形成CIGS(S)层30。应注意的是,恰好在与CIGS(S)层30的界面25处的成核层24的一部分可以是硒化物和/或硫化物形式,这是因为成核层24和VIA族材料之间以及甚至与Cu、In和Ga的一定程度的反应是可能的并且可形成界面层。如果成核层的厚度小(例如1-50nm),则在CIGS(S)层形成期间基本所有成核层可转变成硒化物和/或硫化物。如果吸收体中还包括Te,则还可在界面层中形成碲化物相。可使用图3B的结构通过在CIGS(S)吸收层上方沉积附加层例如透明导电层或半导体层来制造有效的太阳能电池,该太阳能电池具有的结构类似于图1中的结构。
[00048]本发明的金属前体叠层还可包含少量掺杂剂例如Na、K、Li、Sb、P等。掺杂剂可随叠层的层或亚层一起进行镀覆,或者可作为单独的微层进行镀覆。例如,掺杂剂如K和Na可包括到Cu和/或In和/或Ga的电镀电解质中。至多约1%(摩尔)的掺杂剂可包括到前体中。金属前体叠层中的总Gu/(In+Ga)摩尔比可以为0.7-1.2、优选0.8-1.0。Ga/(Ga+In)摩尔比可以为0.01-0.99、优选0.1-0.4。
[00049]可通过各种方式实现金属前体(例如图2A和图2B中所示的前体)与VIA族材料的反应。在一种情形中,将前体层在提高的温度下暴露于VIA族蒸气中。这些技术在本领域中是公知的并且它们涉及在由例如固体Se、固体S、固体Te、H2Se气体、H2S气体等的源提供的Se蒸气、S蒸气和Te蒸气中至少一种的存在下加热前体层到350-600°C的温度范围持续5分钟-1小时。在另一种情形中,在前体层上沉积一层或多层VIA族材料,然后在炉中或在快速热退火炉等中加热叠层。可以在前体层上蒸发、溅射或镀覆VIA族材料。作为替代,可制备包含VIA族纳米颗粒的油墨,可将这些油墨沉积在前体层上以形成包含VIA族纳米颗粒的VIA族材料层。可使用浸渍、喷涂、刮涂或油墨印写(ink writing)技术来沉积这些层。取决于温度,可在提高的温度下进行反应持续1-30分钟。反应的结果是,由前体形成IBIIIAVIA族化合物并且可以获得图3A和3B中所示的结构。
[00050]虽然使用电沉积前体层和这些层与VIA族材料的反应描述了本发明的某些实施方案,但它们通常适用于通过各种其它技术例如蒸发、溅射等获得的结构。例如,本发明人认识到Ru、Ir和Os(即最优选的材料)的某些独特特征,这些特征使这些材料作为IBIIIAVIA族化合物太阳能电池结构中的接触材料或成核层特别具有吸引力。
[00051]如前面所回顾,CIGS(S)型太阳能电池的标准接触材料是Mo。研究者还对许多材料作为CIGS(S)型太阳能电池的可能接触层进行了评价。这些材料是Au、W、Ta、Nb、Cr、V、Ti、Mn、Pd、Pt、TiN、Ni、Ni-P和ZrN。确定CIGS(S)太阳能电池的新接触层的动机在研究组与研究组之间有所不同并且包括;i)在涉及制备具有大于1.6的Cu/(In+Ga)比例的高度富Cu层并接着进行湿法蚀刻步骤的方法中,改善CIGS(S)层对衬底的附着性;和ii)提高背接触的光反射。发现一些上面所列材料不适合作为接触层,这是因为它们与VIA族材料和/或与Cu、In、Ga物质广泛反应。一些据报导表现良好。然而,Mo是商业CIGS(S)太阳能电池结构中使用最广泛的接触材料。
[00052]在选择IBIIIAVIA族化合膜的接触材料例如CIGS(S)层和太阳能电池中,要考虑的一个重要方面是长期稳定性。太阳能电池需要构建成持续至少20年和可能30年。它们在沙漠地区工作期间变热至60-80C。因此,需要考虑接触层和吸收层组分(即Cu、In、Ga、Se、S)之间在CIGS(S)层形成期间的短期化学相互作用以及接触层和已形成的CIGS(S)层之间的长期(20-30年)相互作用。表1提供了关于6种可能接触材料(Ru、Ir、Os、Rh、Pt、Pd)与Cu、In、Ga、Se及S之间的相互作用的信息。在该表中列出了溶解度和可能的反应产物。由S.Dey和V.Jain的题为“Platinum Group MetalChalcogenides”(Platinum Metals Review,vol:48,p:16,2004)的文献获得与Se和S的反应产物的信息。由可用的二元相图获得关于溶解度和6种材料与Cu、In及Ga之间的相互作用的信息,所述二元相图显示了由于两种材料之间的化学相互作用而形成的各种新材料相。
[00053]表1中的数据指出包含Ru、Os、Ir的第一组材料和包含Rh、Pd和Pt的第二组材料在它们与Cu、In、Ga、Se和S的相互作用方面的重要差异,尽管它们均属于称作“铂族金属”的材料组。这些差异可汇总如下:A)Ru、Os和Ir在Cu中不具有大的溶解度,而Rh、Pt和Pd具有与Cu的连续固溶体,B)Ru、Os和Ir在In中具有非常小的溶解度,而若干Pd-In和Pt-In化合物的存在暗示了这些元素之间的广泛反应性,C)虽然缺少Ga的数据,但可认为该情形类似于In的情形,D)Ru、Os和Ir与硒反应形成明确界定的单相硒化物,而Rh、Pt和Pd形成多个具有不同晶体结构的硒化物相,E)Ru和Os与硫反应形成明确界定的单相硫化物,Ir形成两个具有类似晶体结构的明确界定的硫化物相,而Rh、Pt和Pd形成多个具有不同晶体结构的硒化物相。
[00054]立方RuSe2和RuS2的晶胞晶格参数分别为和立方OsSe2和OsS2的相应晶胞参数为和CuInSe2、CuGaSe2、CuInS2和CuGaS2的太阳能电池吸收体具有四方结构,分别具有约和的晶胞参数。对于含有Al和/或Te的吸收体,“a”值为不等。因此,Ru(Se,S)2和Os(Se,S)2对CIGS(S)材料具有优异的晶格匹配(典型地小于10%晶格失配),并且通常Ru(Se,S,Te)2和Os(Se,S,Te)2对如下的IBIIIAVIA族材料具有非常良好的晶格匹配,所述IBIIIAVIA族材料包含作为IB族材料的Cu和Ag中的至少一种、作为IIIA族材料的In、Ga、Al中的至少一种和作为VIA族材料的Se、S和Te中的至少一种。例如,对于RuSe2和CuInSe2的情形,晶格失配仅为(5.93-5.78)/5.93=2.5%。
[00055]IBIIIAVIA族吸收体和IrSe2之间的晶格匹配也是良好的。IrSe2具有正斜方结构,该结构具有和因此,晶胞的底部在一个晶向上与吸收体的四方晶胞的底部匹配良好。对于CuGaSe2的情形,在其它方向上(沿a)失配为约(22.44-20.95)/20.95=7%,其中是CuGaSe2吸收体的“a”值的4倍。IrS2和Ir2S3分别具有和的晶胞参数。上述讨论证明,包含Ru、Os和Ir的一组材料作为接触层、成核层或界面层提供独特的益处,从而产生与IBIIIAVIA族材料的电接触及物理接触。如前面所回顾,这些益处之一是Cu、In、Ga和包含Ru、Os及Ir的组之间的化学相互作用非常有限。因此,例如,虽然在Ru表面上生长CIGS(S)化合物层,但Ru层不与化合物的元素广泛反应并且不负面地影响化合物的组成。如果接触层与Cu、In和Ga中的至少一种相互作用,则可通过束缚至少部分可用Cu、In或Ga形成金属间化合物。因此,这可减少吸收层中元素的量且因此劣化吸收体的组成和电性能。相互作用的这种缺乏对形成CIGS(S)层后太阳能电池结构的长期稳定性也是有益的。在提高的温度下工作20-30年的太阳能电池需要是稳定的。这要求吸收层与接触层或成核层之间的界面是稳定的。
[00056]使用包含Ru、Os和Ir的接触层或界面层的其它益处涉及这些材料如何与VIA族元素例如Se、S和Te相互作用。在包含Ru和/或Os和/或Ir的表面上沉积IBIIIAVIA族材料期间,在IBIIIAVIA族吸收体与Ru和/或Os和/或Ir之间形成界面层。该界面层包含Ru和/或Os和/或Ir的硒化物、硫化物和碲化物中的至少一种,已显示所述硒化物、硫化物和碲化物对IBIIIAVIA族材料具有良好的晶格匹配。晶格匹配减小在接触/吸收体界面处的结构不完整性和电学不完整性,并且其减小该位置的应变和应力。这可有助于晶粒生长和产生具有柱形大晶粒的IBIIIAVIA族吸收层,这对于太阳能电池制造是较好的。相比之下,如由表1可以看出,仅由Rh、Pt和Pd制成的接触层在与Se和S或甚至Te反应时产生多相界面层。应理解,这些界面层与在它们上方生长的IBIIIAVIA族吸收层之间的晶格失配会是大的并且甚至是未界定的(由于存在很多不同的可能晶格结构),这是因为界面层可具有各种化学组成和晶体结构。
[00057]另外,本发明人发现,最优选组的材料与VIA族材料的反应比现有技术的Mo层与相同VIA族材料的反应受到大很多的限制。例如,当在含H2Se的气氛中将玻璃衬底上溅射沉积的Mo层和溅射沉积的Ru层在500C硒化1小时,在Mo层的表面上形成约200nm厚的Mo硒化物层,而Ru层上Ru硒化物层的厚度为约20nm。这显示,与现有技术的Mo接触层相比,在太阳能电池结构中可以使用薄很多的最优选序列材料的接触层。例如,对于现有技术器件典型为500-700nm的Mo层可被50-70nm厚的Ru层替代,并且仍保护衬底或基底不受包含VIA族材料的反应性气氛。此外,使用包含Ru、Ir和Os中至少一种的接触层允许反应温度较高。例如,在两阶段工艺中这包括使包含Cu、In和Ga的前体层与H2Se和/或H2S反应,反应温度典型地保持低于500C。这是因为,在高于该温度例如在接近600C的温度下,Mo接触层与Se和/或S过度反应并且膜对衬底的附着性也变差。应理解,最优选组的惰性更大材料组的使用允许反应温度接近、甚至高于600C。因此,Cu(In,Ga)(Se,S)2层或更通常的IBIIIAVIA化合物层在较短加工时间内可生长成具有较大的晶粒尺寸和较好的电性能和光性能。这样,膜的品质可得到改善并同时加工产量得到提高。这对于其中每次加工一个衬底的RTP型工艺是重要的。作为例子,通过Cu(In,Ga)前体与H2Se气体在450C的反应形成良好品质Cu(In,Ga)Se2的反应时间可以为45-90分钟,而在575C的反应温度下,这可在10-20分钟内得以实现。
[00058]接触材料和氧及水蒸气的相互作用对于薄膜材料的长期可靠性也是重要的。标准的现有技术CIGS太阳能电池接触体是Mo。当现有技术的电池暴露于湿气和/或氧中时,特别在提高的温度下,在Mo/CIGS吸收体处发生反应,使得导致不稳定性。构建在玻璃衬底上的单片集成CIGS组件同样如此。在这些结构中,相邻的太阳能电池通过形成ZnO/Mo界面串联连接,即一个电池的ZnO透明层或上电极短接至下一个电池的Mo接触层或底电极。当ZnO/Mo连接长期暴露于湿气和/或氧中时,界面电阻的增加减小组件的填充系数,这在需要20-30年寿命的太阳能组件中是不可接受的。Mo对水蒸气和氧的敏感性部分是由于其与氧的高反应性,氧是VIA族元素,正如同Se和S。钼在其表面上不形成保护性氧化物。因此当其被氧化时,表面氧化生长并且在Mo/CIGS和/或ZnO/Mo界面处产生高电阻。这造成太阳能电池和使用Mo接触体的组件中的上述不稳定性。优选组的材料,特别是Ru、Ir和Os中的至少一种用来代替Mo或者在CIGS型太阳能电池或组件中的Mo表面上使用消除了该问题。例如,如果CIGS太阳能电池的结构是Mo/Ru/CIGS或Ru/CIGS,这种结构暴露于水蒸气(H2O)和/或氧将在Ru/CIGS界面的Ru表面上产生非常薄(相比于Mo层)的氧化物层,正是因为先前所述Ru与H2Se和H2S的反应产生非常薄(相比于Mo层)的硒化物或硫化物层。应注意,H2Se、H2S和H2O在化学上属于同一组,因为Se、S和O同属VIA族,并且与许多其它常见金属例如Mo、W、Ta、Ti、Ni等相比,Ru、Ir和Os与这些材料的反应性小很多。
[00059]Ru、Ir和Os表面上形成的氧化物的薄性质以及它们的高电导率使得与这些材料产生的界面(例如Ru/CIGS界面或ZnO/Ru界面)在含有湿气和/或氧的环境中是稳定的。这对于未封装或封装的太阳能电池或组件意味着较长寿命,其中封装可以不提供绝对的气密密封。
[00060]应注意的是,包含Ru、Os和Ir中至少一种的接触层可具有合金、化合物或混合物形式的这些材料。例如,Ru可以是Ru、Ru氧化物、Ru硒化物、Ru硫化物、Ru碲化物、Ru硫代硒化物、Ru硫代碲化物、Ru硒代碲化物、Ru-M合金或混合物的形式(其中M是金属或IVA族材料)、Ru氮化物、Ru碳化物等。类似的论点对于Os和Ir也是有效的。虽然在“C”层的表面上生长IBIIIAVIA吸收层期间,在“C”接触层(其中C可包含Ru和/或Ir和/或Os)和IBIIIAVIA族吸收膜之间的界面处可发生C-VIA族化合物的形成,但也有可能在衬底上沉积C-VIA族化合物层并然后在其上方生长IBIIIAVIA族化合物。例如,可首先在导电表面例如Mo、Ti、Cr、Al、Ta、W、Ni等表面上生长Ru(S,Se)2层。然后可在Ru(S,Se)2层上生长高品质的Cu(In,Ga)(Se,S)2吸收层。这样的方法仍得益于上述Ru(S,Se)2和Cu(In,Ga)(Se,S)2之间优异的晶格匹配。应注意的是,当在共用Mo接触层上生长IBIIIAVIA族吸收层时,Mo层和IBIIIAVIA族吸收体之间形成Mo-VIA族界面。因为Mo形成许多不同的硫化物、碲化物和硒化物相,每个相具有它们各自不同的晶体结构,Mo-VIA族界面层和IBIIIAVIA族吸收层之间的晶格失配是大的。例如,在Mo表面上生长Cu(In,Ga)Se2吸收体期间,可在Mo/Cu(In,Ga)Se2界面处形成例如MoSe2(JCPDS衍射文件29-914)、Mo3Se4(JCPDS衍射文件24-772)、Mo9Se11(JCPDS衍射文件40-908)、Mo15Se19(JCPDS衍射文件39-786)等的相。这些相分别具有六方、斜方六面体、正斜方和六方的晶体结构。Ru、Ir和Os作为使用IBIIIAVIA族吸收膜的太阳能电池的接触层的一些其它引人关注的特征包括,IB族和IIIA族元素所致的这些材料的较好润湿特性。例如,Cu以小接触角良好地润湿Ru、Ir和Os表面。这改善了Cu在这些接触层表面上的成核,从而允许受到Cu层的良好覆盖,所述Cu层是通过各种技术例如电镀、化学气相沉积、原子层沉积、蒸发、溅射等形成的。例如,可将薄至10nm的Cu层覆盖到Ru表面上且具有优异的覆盖率,而这在例如Mo、Ti、Ta等的材料上不能得以实现。这是因为Cu在Ru上的成核中心密度比在所引述的其它材料上大很多。对于In和Ga也是类似情形,即Ga和In在Ru、Ir和Os上的成核比它们在现有技术的接触材料例如Mo上更佳。甚至在接触膜或层上沉积包含Cu、In和Ga中至少一种的前体或层后,良好的润湿也起作用。例如,如前述美国专利申请公开No.2005/0202589和2006/0121701中所描述,在衬底上沉积包括Cu、In和/或Ga以及任选的VIA族材料的前体后,可加热这些前体以提高元素间的合金化或反应。如果衬底表面或接触层的润湿特性并不良好,则在加热期间前体层的形貌发生劣化。例如,低熔点相例如In和Ga可引起“成球”现象,这进而在膜平面中带来组成不均匀性。在反应完成和化合物形成后,膜平面中的这种组成不均匀性即Cu/(In+Ga)和Ga/(Ga+In)比例的变化延续至IBIIIAVIA族化合物层。太阳能电池效率在这样的不均匀化合物层上是低的,因为效率是组成的函数。因为成核和润湿是优异的,因此衬底表面上最优选序列的材料的存在使引起组成微观不均匀性的问题例如“成球”最小化或将其消除。
[00061]可使用本领域公知的材料和方法在本发明的化合物层上制造太阳能电池。例如可使用化学浸渍法在所述化合物层的表面上沉积薄(<0.1微米)CdS层。可使用MOCVD或溅射技术在CdS层上沉积ZnO的透明窗口。任选在ZnO上沉积金属指形图案以完成太阳能电池。用In进行合金化或掺杂的ZnO层特别适合于CIGS(S)太阳能电池。可通过各种技术例如溅射沉积这样的In-Zn-O(IZO)透明导体,并且可产生与典型为多晶态性质的ZnO膜相对的非晶态层。CIGS(S)太阳能电池具有湿气敏感性,而非晶态层是比多晶态层好很多的湿气阻挡体,这是因为它们不具有物质可从中扩散通过的晶界。因此,包含非晶态IZO作为其透明导电窗层的至少一部分的CIGS(S)太阳能电池结构就抗湿性而言具有吸引力。这样的结构可以是衬底/接触层/CIGS(S)/CdS/IZO(CdS层是任选的),或者其可以在IZO层下方或上方具有ZnO或其它透明导电氧化物如In-Sn-O。
[00062]虽然就某些优选实施方案描述了本发明,但对本领域技术人员而言对其修改是显而易见的。例如,本发明的接触层或成核层可用于形成属于IIBVIA族材料例如CdTe、ZnTe、CdSe和它们的合金等的各种重要半导体层的接触体。