English:
[0001] Phase-locked loop (PLL) systems are used in various applications to match the phase and frequency of one signal to those of a reference signal. Although different PLLs may include different components, most PLLs include a phase-frequency detector (PFD), a low-pass filter, and an oscillator (e.g., a voltage-controlled oscillator (VCO)). Some of these components may introduce phase noise to the tuning signal that is provided to the VCO— such as distortions in the rising or falling edges of each pulse in the tuning signal. The VCO applies a gain to the tuning signal when producing the output signal, and this gain is undesirably applied to the phase noise as well.
[0002] To mitigate the amplification of phase noise, it may be desirable to reduce the VCO gain. Decreasing the VCO gain requires widening the voltage swing of the tuning signal provided to the VCO (e.g., a rail-to-rail swing). However, the PLL may contain components— such as charge pumps and VCO varactors— that do not respond favorably to wide-swing tuning signals because they do not operate linearly at all tuning signal voltage values.
[0003] In some examples, a phase-locked loop (PLL) system comprises a phase-frequency detector (PFD) configured to compare a phase-frequency reference signal and a feedback signal, a charge pump (CP) electrically coupled to the PFD and configured to produce a first tuning signal based on an output of the PFD, multiple integrator cells electrically coupled to the CP and configured to output multiple second tuning signals based on a voltage of the first tuning signal relative to a voltage reference signal, and a voltage-controlled oscillator (VCO) electrically coupled to the CP and to the multiple integrator cells and configured to adjust a capacitance value of the VCO based on the multiple second tuning signals. The capacitance value and the first tuning signal affect a frequency of the feedback signal. One or more such examples may be supplemented using one or more of the following techniques, in any order and in any combination: further comprising a low-pass filter coupled to the CP; wherein the low-pass filter comprises multiple capacitors and a resistor; wherein the low-pass filter comprises multiple capacitors and a switch; further comprising a logic NOR gate to control the switch, the NOR gate configured to receive the feedback signal and the phase-frequency reference signal as inputs; further comprising a comparator configured to receive the first tuning signal and the voltage reference signal as inputs; wherein the comparator produces a comparator output that controls multiple current sources in the multiple integrator cells; wherein alteration of the multiple current sources causes a change in the frequency of the feedback signal; wherein the multiple integrator cells cause the first tuning signal to remain within a predetermined voltage range; wherein each of the multiple integrator cells provides an output signal to control a corresponding transistor switch in the VCO, and wherein each corresponding transistor switch is configured to increase or decrease the capacitance value.
[0004] In some examples, a phase-locked loop (PLL) system comprises a comparator configured to receive a voltage reference signal and a tuning signal and to produce a comparator output. The system also comprises a chain of integrator cells coupled to a plurality of transistor switches and configured to operate the plurality of transistor switches based on the comparator output. The system further includes a voltage-controlled oscillator (VCO) comprising a plurality of capacitors coupled to the plurality of transistor switches. The VCO is configured to provide an output signal having a frequency based at least in part on at least one of the plurality of capacitors. One or more such examples may be supplemented using one or more of the following techniques, in any order and in any combination: wherein the VCO comprises the plurality of transistor switches; further comprising a filter, positioned between the comparator and a charge pump, that is configured to dampen a ripple associated with a PLL update; wherein the tuning signal maintains a voltage within a predetermined range of the voltage reference signal; wherein the voltage reference signal is within 10% of half of a voltage rail supply.
[0005] In some examples, a method comprises generating a tuning signal in a phase-locked loop (PLL) based on a phase-frequency reference signal and a voltage-controlled oscillator (VCO) feedback signal, providing the tuning signal to the VCO, controlling a capacitance value of the VCO based on a comparison of the tuning signal and a voltage reference signal, and generating the VCO feedback signal based on the tuning signal and the capacitance value. One or more such examples may be supplemented using one or more of the following techniques, in any order and in any combination: wherein controlling the capacitance value of the VCO comprises controlling multiple transistor switches coupled to multiple capacitors, the multiple transistors switches and the multiple capacitors located within the VCO; further comprising maintaining the tuning signal within a predetermined voltage range; wherein controlling the capacitance value comprises using a comparator, and further comprising using a resistor to provide the tuning signal to the comparator; wherein controlling the capacitance value comprises using a comparator, and further comprising using a switch to provide the tuning signal to the comparator.
[0006] FIG. 1 is a block diagram of a PLL system implementing the techniques described herein.
[0007] FIG. 2 is a circuit schematic diagram of a PLL system implementing the techniques described herein.
[0008] FIG. 3 is another circuit schematic diagram of a PLL system implementing the techniques described herein.
[0009] FIG. 4 is another circuit schematic diagram of a PLL system implementing the techniques described herein.
[0010] FIG. 5 is a circuit schematic diagram of an integrator cell chain for use in a PLL system.
[0011] FIG. 6 is a circuit schematic diagram of an inductor/capacitor voltage-controlled oscillator (LC-VCO) for use in a PLL system.
[0012] FIG. 7 is a flow diagram of a method for operating a PLL system according to various examples.
[0013] For at least the reasons set forth above, a PLL that provides minimal VCO gain without requiring a large tuning signal swing is desirable. At least some of the embodiments described herein are directed to methods and systems for maintaining a combination of a smaller voltage- controlled oscillator (VCO) gain and a smaller voltage swing in a fine tuning signal provided to a VCO than is possible in other methods and systems. The described embodiments include a comparator that compares the voltage of the fine tuning signal with a voltage reference signal to produce an output, and a chain of integrator cells that uses the comparator output to produce a coarse tuning signal that controls the frequency of the VCO output signal. Specifically, the comparator output controls the currents generated by the integrator cells, and, in turn, these currents open and close transistor switches in the VCO via the coarse tuning signal. Opening and closing the transistor switches in the VCO causes changes in a capacitor network in the VCO, and such changes in the VCO capacitor network result in a change in the overall capacitance value of the VCO. Adjusting the overall capacitance value in the VCO causes the frequency of the output signal to rise or fall. In this way, the coarse tuning signal maintains the frequency of the VCO output signal close to the target frequency of a reference signal provided to the PLL. The proximity between the VCO output signal frequency and the target frequency as a result of the coarse tuning signal means that a smaller swing is required of the fine tuning signal. In particular, the fine tuning signal may have a voltage swing that is maintained within a narrow range centering on the voltage reference signal provided to the comparator. By maintaining a small swing in the fine tuning signal and a low VCO gain, phase noise is mitigated without the charge pump and varactor linearity problems traditionally associated with reducing VCO gain.
[0014] FIG. 1 is a block diagram of an illustrative PLL system 100 implementing techniques described herein. The system 100 comprises a phase-frequency detector (PFD) 102; a charge pump (CP) 104; an inductor/capacitor voltage-controlled oscillator (LC-VCO) 106; a frequency divider 108; a low-pass filter (LPF) 110; a coarse tuning logic 112; a phase-frequency (P-F) reference signal 114; a PFD output signal 116; a CP output node 118; a fine tuning signal 120; a filter control signal 122; a LPF output signal 124; a voltage reference signal 126; a coarse tuning signal 128; a LC-VCO output node 130; a VCO output signal 132; a feedback signal 134; and a divided feedback signal 136. The feedback signal 134 and the divided feedback signal 136 may be synonymously referred to herein because the divided feedback signal 136 is derived from, and is simply a divided version of, the feedback signal 134.
[0015] The P-F reference signal 114 may be a reference signal that has a target frequency and phase that the VCO output signal 132 is to match. In some examples, a phase difference may exist between the VCO output signal 132 and the P-F reference signal 114, but the PLL system 100 may cause such phase difference to remain substantially constant. The P-F reference signal 114 may be generated by any suitable circuit, either internal or external to the PLL system 100. The PFD 102 receives the P-F reference signal 114 and a divided feedback signal 136, the latter being derived from the output of the LC-VCO 106. The PFD 102 determines the difference between the P-F reference signal 114 and the divided feedback signal 136 to produce a PFD output signal 116. The PFD output signal 116 is provided to the CP 104. The CP 104, in some embodiments, comprises a bipolar switched current source that uses the PFD output signal 116 to produce the fine tuning signal 120 at node 118. The fine tuning signal 120 may be provided to the LC-VCO 106, and the LC-VCO 106 may use the fine tuning signal 120 to adjust the frequency of the VCO output signal 132 upward or downward toward the P-F reference signal 114. The LC-VCO 106 adjusts the frequency of the VCO output signal 132 by adjusting a varactor diode within the LC-VCO 106 (e.g., element 610 in FIG. 6, described below).
[0016] In some embodiments, the voltage swing of the fine tuning signal 120 may be kept small compared to the swing that would otherwise be present by using the fine tuning signal 120 to generate a coarse tuning signal 128. The coarse tuning signal 128 brings the P-F reference signal 114 close to the P-F reference signal 114 so that the fine tuning signal 120 need only cause minor shifts in the VCO output signal 132 frequency to obtain a lock between the VCO output signal 132 and the P-F reference signal 114.
[0017] The coarse tuning signal 128 is generated using the LPF 110 and the coarse tuning logic 112. Specifically, the LPF 110 receives the fine tuning signal, filters the signal, and produces a filtered signal 124. The LPF 110 may allow signals of any suitable frequency band to pass through (e.g., 100 kHz-10 MHz). The coarse tuning logic 112 receives the filtered signal and compares it to a voltage reference signal 126. The coarse tuning logic 112 uses the result of the comparison to adjust the overall capacitance of the LC-VCO 106, which, in turn, causes the frequency of the VCO output signal 132 (and the equivalent feedback signal 134) to move toward the P-F reference signal 114. The voltage reference signal 126 may be any suitable voltage, but, in at least some embodiments, it is half of the rail voltage supply (VDD) provided to the PLL system 100 or it is within 10% of half of the rail voltage supply.
[0018] The filter control signal 122 may be used to control components, e.g., switches within the LPF 110 as described below. The divider 108 is a frequency divider that divides the frequency of the feedback signal 134 down by a predetermined factor (e.g., one-quarter, one-half) to produce the divided feedback signal 136. The divided feedback signal 136, in turn, is provided as an input into the PFD 102.
[0019] FIG. 2 is a circuit schematic diagram of the PLL system 100. Specifically, FIG. 2 depicts the contents of the LPF 110 and the coarse tuning logic 112. The LPF 110 includes a capacitor 200 (e.g., 50 pF) coupled to node 118 and to ground 202. The LPF 110 further comprises a resistor 204 (e.g., 2 kOhms) coupled to node 118 and to a capacitor 206 (e.g., 500 pF). The capacitor 206 couples to ground 202. The LPF 110 averages the proportional charge pump current over the entire update period (i.e., the time period required to update the capacitor 206 with the value present at the capacitor 200) to minimize voltage ripple. The result is a reduction in phase noise.
[0020] In the example of FIG. 2, the coarse tuning logic 112 includes a comparator 208 that receives two inputs: the voltage reference signal 126, and the signal present at the node between the resistor 204 and the capacitor 206. The comparator 208 provides a comparator output signal to an integrator cell chain 210. The integrator cell chain 210 contains multiple integrator cells, described below, each of which couples to a different capacitor in the LC-VCO 106. The integrator cell chain 210 provides the coarse tuning signal 128 (which, in some embodiments, actually comprises multiple tuning signals, each of which is provided by a separate integrator cell in the integrator cell chain 210) to the LC-VCO 106. The coarse tuning signal 128 causes capacitors in the LC-VCO 106 to be added to or removed from the overall capacitance of the LC-VCO 106. Changes in the overall capacitance value of the LC-VCO 106 cause the frequency of the VCO output signal 132 to change and approach the voltage reference signal 126. The integrating nature of the integrator cells causes a smooth frequency response in the VCO output signal 132.
[0021] FIG. 3 is a circuit schematic diagram of the PLL system 100. The embodiment depicted in FIG. 3 differs from that depicted in FIG. 2 only in the design of the LPF 110. Specifically, the LPF 110 in FIG. 3 includes a switch 300 (e.g., a transistor) positioned between the node 118 and the inverting input to the comparator 208. The switch 300 is controlled by the filter control signal 122. In some embodiments, the filter control signal 122 is generated by a logic NOR gate 302, which receives the P-F reference signal 114 and the divided feedback signal 136 as inputs. When both of these inputs are LOW, the filter control signal 122 is HIGH, and the switch 300 is closed. If either of the inputs to the NOR gate 302 is HIGH, the filter control signal 122 is LOW, and the switch 300 is open. When the switch 300 is closed, the charge present at the capacitor 200 is applied to the capacitor 206. In this way, signal updates are provided to the capacitor 206 when the clock signals input into the PFD 102 are both low— that is, when no new pulses are incoming. This time period during which the pulses are simultaneously low may be termed a "PLL update period."
[0022] FIG. 4 is another circuit schematic diagram of a PLL system 100 implementing the techniques described herein. The embodiment depicted in FIG. 4 is identical or nearly identical to those depicted in FIGS. 2 and 3, with some exceptions. For example, the LPF 110 includes a component 400, which may include a resistor (as depicted in FIG. 2) or a switch (as depicted in FIG. 3). Also, the PLL system 100 of FIG. 4 includes a filter 402 to reduce the PLL update ripple (i.e., noise introduced when the capacitor 206 is updated using the capacitor 200 as a result of the filter control signal 122 changing states) before the signal is provided to the comparator 208. In some embodiments, the filter 402 includes a resistor 404 (e.g., 10 kilo-Ohms), a capacitor 406 (e.g., 500 pF), and a ground connection 202. Further, the PLL system 100 of FIG. 4 comprises a pulser 410 positioned between the comparator 208 and the integrator cell chain 210. The pulser 410 receives the output of the comparator 208 as an input, receives a suitable clock signal 412 (e.g., having a frequency of the P-F reference signal 114) as another input, and provides its output to the integrator cell chain 210. The pulser 410 divides the direct current into current pulses, which mitigates phase noise introduced by the integrator cells in the integrator cell chain 210 and provides a lower bandwidth of the integrator path.
[0024] In operation, the output of the comparator 208 causes the current sources 518A and 520 A to provide for increased or decreased current at the node 534A. Although a single output from the comparator 208 is shown in the figures for clarity, the comparator 208 in at least some embodiments has multiple mirrored outputs, each one controlling a different current source in the integrator cell chain 210. For example, this may be accomplished using a transconductance amplifier. If the current produced by current source 518A is increased above that provided by the current source 520A, the node 534A is HIGH, the NMOS transistor 528A is ON, and the frequency of the VCO output signal 132 drops because— as described below— the overall capacitance of the LC-VCO 106 rises. If the current produced by current source 520A is increased above that provided by the current source 518A, the node 534A is LOW, the NMOS transistor 528 A is OFF, and the frequency of the VCO output signal 132 increases because— as described below— the overall capacitance of the LC-VCO 106 drops. One purpose of the capacitor 522A is to define the pole of the integrator chain and, thus, the speed of the frequency control. The speed of the frequency control should be relatively slow in comparison to the PLL bandwidths. The frequency control (integrator chain) should not influence the PLL behavior. The switches 514A and 516A short the current sources 518A and 520 A, respectively, depending on the outputs of the NOR gate 506 A and AND gate 508 A, respectively. The capacitor 53 OA couples to the remainder of the LC-VCO 106 via node 532A.
[0026] FIG. 6 is a circuit schematic diagram of at least a portion of an illustrative LC-VCO 106. The LC-VCO 106 comprises a voltage supply rail connection 600; a current source 602 (e.g., 12 mA); a pair of inductors 606, 608 (e.g., 120 pH); nodes 624 and 626 between which a variable capacitor 610 is positioned; transistors (e.g., NMOS) 620, 622 whose gates couple to nodes 626 and 624, respectively; and a ground connection 604 that couples to the sources of the transistors 620, 622. The LC-VCO 106 further includes the transistors 528A, 528B and capacitors 530A, 530B described above with respect to FIG. 5. The set of transistors and capacitors that couples to the node 624 is replicated to couple to the node 626, as shown. The variable capacitor 610 may include a capacitance control input that is coupled to the fine tuning signal 120 via a fine tuning signal input of the LC-VCO 106. Each of transistors 528A, 528B may have a control input that is coupled to an output of a respective integrator cell. For example, the gates of transistors 528 A (left- hand and right-hand sides) may be coupled to the output of a first integrator cell, and the gates of transistors 528B (left-hand and right-hand side) may be coupled to the output of a second integrator cell. Activating one or more transistors (e.g., transistors 528A, 528B) effectively causes the corresponding capacitors (e.g., capacitors 530A, 530B) to be coupled in parallel. In turn, this effectively increases the overall capacitance of the LC-VCO 106. Conversely, deactivating transistors decreases the overall capacitance of the LC-VCO 106. Activating or deactivating even a single transistor, in some embodiments, may affect the overall capacitance of the LC-VCO 106. The output of the LC-VCO 106 is across terminals nodes 624 and 626. By increasing and decreasing capacitance of the LC-VCO 106 in this manner, the frequency of the VCO output signal 132 can be decreased or increased to more closely match the frequency of the P-F reference signal 114. This, in turn, causes the fine tuning signal 120 to have a smaller voltage swing than would otherwise be the case. When the fine tuning signal 120 has a smaller voltage swing and the gain of the LC-VCO 106 is kept low (e.g., gain factor of 10 MHz/V), phase noise is mitigated without the charge pump and varactor linearity problems traditionally associated with reducing VCO gain.
[0027] FIG. 7 is a flow diagram of a method 700 for operating a PLL system according to various embodiments. The method 700 begins by generating a fine tuning signal based on a phase- frequency reference signal and a VCO feedback signal (step 702). The method 700 next comprises providing the fine tuning signal to the VCO (step 704). For the reasons provided above, the fine tuning signal will have a smaller voltage swing than would be the case if the techniques described herein were not implemented— e.g., a narrow range above and below half of the voltage supply rail. The method 700 next includes controlling the overall capacitance value of the LC-VCO based on a comparison of the fine tuning signal and a voltage reference signal (step 706). In some examples, the comparison may be a comparison between a low-pass filtered version of the fine tuning signal and the voltage reference signal. As described hereinabove, the result of the comparison of the fine tuning signal and the voltage reference signal manipulates the output of current sources in the integrator cell chain. This, in turn, opens and closes transistors, which increases of decreases the overall capacitance of the LC-VCO by manipulating a network of capacitors coupled to the transistors. The method 700 finally comprises generating a VCO output/feedback signal based on the fine tuning signal and the VCO capacitance value (e.g., by using the fine tuning signal to adjust a varactor value in the LC-VCO) (step 708). The method 700 may be modified as desired, including by adding, deleting, modifying or rearranging one or more steps.
[0028] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

中文:
[0001]锁相回路(PLL)系统在各种应用中用于使一个信号的相位和频率与参考信号的相位和频率匹配。尽管不同PLL可包含不同组件,但大多数PLL包含相位-频率检测器(PFD)、低通滤波器和振荡器(例如压控振荡器(VCO))。这些组件中的一些可能将相位噪声引入到提供给VCO的调谐信号,例如调谐信号中每一脉冲的上升沿或下降沿中的失真。当产生输出信号时,VCO将增益施加到调谐信号,且此增益也不合需要地施加到相位噪声。
[0002]为了减轻相位噪声的放大,可能需要减小VCO增益。减小VCO增益需要加宽提供到VCO的调谐信号的电压摆幅(例如轨对轨摆幅)。然而,PLL可含有组件,例如电荷泵和VCO变抗器,其不会有利地响应宽摆幅调谐信号,因为它们不会以所有调谐信号电压值线性地操作。
[0003]在一些实例中,锁相回路(PLL)系统包括:相位-频率检测器(PFD),其经配置以将相位-频率参考信号与反馈信号进行比较;电荷泵(CP),其电耦合到PFD,且经配置以基于PFD的输出,产生第一调谐信号;多个积分器单元,其电耦合到CP,且经配置以基于第一调谐信号相对于电压参考信号的电压,输出多个第二调谐信号;以及压控振荡器(VCO),其电耦合到所述CP,且电耦合到所述多个积分器单元,且经配置以基于所述多个第二调谐信号来调整VCO的电容值。所述电容值和所述第一调谐信号影响反馈信号的频率。可按任何次序且以任何组合,使用以下技术中的一或多者来补充一或多个此类实例:进一步包括耦合到CP的低通滤波器;其中所述低通滤波器包括多个电容器和电阻器;其中所述低通滤波器包括多个电容器和开关;进一步包括逻辑“或非”门来控制开关,所述“或非”门经配置以接收反馈信号和相位-频率参考信号作为输入;进一步包括比较器,其经配置以接收第一调谐信号和电压参考信号作为输入;其中所述比较器产生控制多个积分器单元中的多个电流源的比较器输出;其中更改所述多个电流源导致反馈信号的频率的改变;其中所述多个积分器单元导致第一调谐信号保持在预定电压范围内;其中所述多个积分器单元中的每一者提供输出信号来控制VCO中的对应晶体管开关,且其中每一对应晶体管开关经配置以增加或减小电容值。
[0004]在一些实例中,锁相回路(PLL)系统包括比较器,其经配置以接收电压参考信号和调谐信号,且产生比较器输出。所述系统还包括积分器单元链,其耦合到多个晶体管开关,且经配置以基于所述比较器输出来操作所述多个晶体管开关。所述系统进一步包含压控振荡器(VCO),其包括耦合到所述多个晶体管开关的多个电容器。所述VCO经配置以提供具有至少部分地基于所述多个电容器中的至少一者的频率的输出信号。可按任何次序且以任何组合,使用以下技术中的一或多者来补充一或多个此类实例:其中所述VCO包括所述多个晶体管开关;进一步包括定位在比较器与电荷泵之间的滤波器,其经配置以减弱与PLL更新相关联的纹波;其中调谐信号使电压维持在电压参考信号的预定范围内;其中所述电压参考信号在电压轨供应的一半的10%内。
[0005]在一些实例中,一种方法包括:基于相位-频率参考信号和压控振荡器(VCO)反馈信号,产生锁相回路(PLL)中的调谐信号;将所述调谐信号提供到VCO;基于所述调谐信号与电压参考信号的比较,控制所述VCO的电容值;以及基于所述调谐信号和所述电容值,产生VCO反馈信号。可按任何次序且以任何组合,使用以下技术中的一或多者来补充一或多个此类实例:其中控制VCO的电容值包括控制耦合到位于VCO内的多个电容器、多个晶体管开关和多个电容器的多个晶体管开关;进一步包括使调谐信号维持在预定电压范围内;其中控制所述电容值包括使用比较器,且进一步包括使用电阻器来将调谐信号提供到比较器;其中控制电容值包括使用比较器,且进一步包括使用开关来将调谐信号提供到比较器。
[0006]图1是实施本文中所描述的技术的PLL系统的框图。
[0007]图2是实施本文中所描述的技术的PLL系统的电路示意图。
[0008]图3是实施本文中所描述的技术的PLL系统的另一电路示意图。
[0009]图4是实施本文中所描述的技术的PLL系统的另一电路示意图。
[0010]图5是用于PLL系统积分器单元链的电路示意图。
[0011]图6是用于PLL系统中的电感器/电容器压控振荡器(LC-VCO)的电路示意图。
[0012]图7是用于根据各种实例操作PLL系统的方法的流程图。
[0013]至少出于上述原因,提供最小VCO增益而不需要大调谐信号摆幅的PLL是合意的。本文所述实施例的至少一些是针对用于与其它方法和系统中的可能情况相比,维持提供VCO的较小压控振荡器(VCO)增益与微调信号中的较小电压摆幅的组合的方法和系统。所描述的实施例包含:比较器,其将微调信号的电压与电压参考信号进行比较以产生输出;以及积分器单元链,其使用比较器输出来产生控制VCO输出信号的频率的粗调信号。具体地说,比较器输出控制积分器单元所产生的电流,且这些电流又经由粗调信号打开和闭合VCO中的晶体管开关。打开和闭合VCO中的晶体管开关导致VCO中的电容器网络的改变,且VCO电容器网络的此类改变导致VCO的总电容值的改变。调整VCO中的总电容值导致输出信号的频率上升或下降。以此方式,粗调信号使VCO输出信号的频率维持接近提供到PLL的参考信号的目标频率。VCO输出信号频率与目标频率之间由于粗调信号而导致的接近性意味着微调信号需要较小摆幅。明确地说,微调信号可具有维持在中心在提供到比较器的电压参考信号上的窄范围内的电压摆幅。通过维持微调信号中的小摆幅以及低VCO增益,减轻相位噪声,而无传统上与减小VCO增益相关联的电荷泵和变抗器线性问题。
[0014]图1是实施本文中所描述的技术的说明性PLL系统100的框图。系统100包括相位-频率检测器(PFD)102;电荷泵(CP)104;电感器/电容器压控振荡器(LC-VCO)106;分频器108;低通滤波器(LPF)110;粗调逻辑112;相位-频率(P-F)参考信号114;PFD输出信号116;CP输出节点118;微调信号120;滤波器控制信号122;LPF输出信号124;电压参考信号126;粗调信号128;LC-VCO输出节点130;VCO输出信号132;反馈信号134;以及经分频的反馈信号136。反馈信号134和经分频的反馈信号136在本文中可同义指代,因为经分频的反馈信号136是从反馈信号134导出且仅为所述反馈信号的经分频版本。
[0015]P-F参考信号114可为具有VCO输出信号132将与之匹配的目标频率和相位的参考信号。在一些实例中,相位差可存在于VCO输出信号132与P-F参考信号114之间,但PLL系统100可致使此类相位差保持大体上恒定。P-F参考信号114可由在PLL系统100内部或外部的任何合适电路产生。PFD 102接收P-F参考信号114和经分频的反馈信号136,后者是从LC-VCO 106的输出导出。PFD 102确定P-F参考信号114与经分频的反馈信号136之间的差,以产生PFD输出信号116。将PFD输出信号116提供到CP 104。在一些实施例中,CP 104包括双极切换电流源,其使用PFD输出信号116来在节点118产生微调信号120。可将微调信号120提供到LC-VCO 106,且LC-VCO 106可使用微调信号120来将VCO输出信号132的频率朝P-F参考信号114上下调整。LC-VCO 106通过调整LC-VCO 106内的变抗器二极管(例如图6中的元件610,下文描述),来调整VCO输出信号132的频率。
[0016]在一些实施例中,与通过使用微调信号120来产生粗调信号128原本将出现的摆幅相比,微调信号120的电压摆幅可保持较小。粗调信号128使P-F参考信号114接近P-F参考信号114,使得微调信号120仅需要导致VCO输出信号132的频率中的微量偏移,来获得VCO输出信号132与P-F参考信号114之间的锁定。
[0017]使用LPF 110和粗调逻辑112来产生粗调信号128。具体地说,LPF 110接收微调信号,对所述信号进行滤波,且产生经滤波的信号124。LPF 110可允许任何合适的频带的信号穿过(例如100kHz到10MHz)。粗调逻辑112接收经滤波的信号,并将其与电压参考信号126进行比较。粗调逻辑112使用与比较的结果来调整LC VCO 106的总电容,其又致使VCO输出信号132(和等效反馈信号134)的频率朝P-F参考信号114移动。电压参考信号126可以是任何合适的电压,但在至少一些实施例中,其为提供到PLL系统100的轨电压供应(VDD)的一半,或其在轨电压供应的一半的10%内。
[0018]滤波器控制信号122可用于控制组件,例如LPF 110内的开关,如下所述。除法器108是将反馈信号134的频率向下除以预定因子(例如四分之一、二分之一)以产生经分频的反馈信号136的分频器。经分频的反馈信号136又作为输入提供到PFD 102中。
[0019]图2是PLL系统100的电路示意图。具体地说,图2描绘LPF 110和粗调逻辑112的内容。LPF 110包含电容器200(例如50pF),其耦合到节点118且耦合到接地202。LPF 110进一步包括电阻器204(例如2千欧),其耦合到节点118且耦合到电容器206(例如500pF)。电容器206连接到接地202。LPF 110将整个更新周期(即,用电容器200处存在的值来更新电容器206所需的时间周期)内的成比例电荷泵电流平均,以最小化电压纹波。结果是相位噪声的减小。
[0020]在图2的实例中,粗调逻辑112包含比较器208,其接收两个输入:电压参考信号126;以及存在于电阻器204与电容器206之间的节点处的信号。比较器208将比较器输出信号提供到积分器单元链210。积分器单元链210含有多个下文描述的积分器单元,其中的每一者耦合到LC-VCO 106中的不同电容器。积分器单元链210将粗调信号128(其在一些实施例中,实际包括多个调谐信号,其中的每一者由积分器单元链210中的单独积分器单元提供)提供到LC-VCO 106。粗调信号128导致LC-VCO 106中的电容器添加到LC-VCO 106的总电容或从其去除。LC-VCO 106的总电容值的改变导致VCO输出信号132的频率改变且接近电压参考信号126。积分器单元的积分性质导致VCO输出信号132中的平滑频率响应。
[0021]图3是PLL系统100的电路示意图。图3中所描绘的实施例与图2中描绘的实施例的不同之处仅在于LPF 110的设计。具体地说,图3中的LPF 110包含定位在节点118与比较器208到反相输入之间的开关300(例如晶体管)。开关300由滤波器控制信号122控制。在一些实施例中,滤波器控制信号122由逻辑“或非”门302产生,其接收P-F参考信号114和经分频的反馈信号136作为输入。当这两个输入为低时,滤波器控制信号122为高,且开关300闭合。如果到“或非”门302的输入中的任一者为高,那么滤波器控制信号122为低,且开关300断开。当开关300闭合时,存在于电容器200处的电荷施加到电容器206。以此方式,当输入到PFD 102中的时钟信号两者均为低时,即当无新的脉冲传入时,将信号更新提供到电容器206。在此期间脉冲同时为低的此时间周期可被称为“PLL更新周期”。
[0022]图4是实施本文中所描述的技术的PLL系统100的另一电路示意图。图4中所描绘的实施例与图2和3中描绘的那些实施例相同或几乎相同,有一些例外。举例来说,LPF110包含组件400,其可包含电阻器(如图2中所描绘)或开关(如图3中所描绘)。并且,图4的PLL系统100包含滤波器402,以在将信号提供到比较器208之前,减少PLL更新纹波(即,由于滤波器控制信号122改变状态,所以当使用电容器200来更新电容器206时,引入噪声)。在一些实施例中,滤波器402包含电阻器404(例如10千欧)、电容器406(例如500pF)和接地连接202。另外,图4的PLL系统100包括定位在比较器208与积分器单元链210之间的脉冲发生器410。脉冲发生器410接收比较器208的输出作为输入,接收合适的时钟信号412(例如具有P-F参考信号114的频率)作为另一输入,且将其输出提供到积分器单元链210。脉冲发生器410将直流电分成电流脉冲,这减轻了积分器单元链210中的积分器单元引入的相位噪声,且提供积分器路径的较低带宽。
[0024]在操作中,比较器208的输出致使电流源518A和520A在节点534A处提供增加或减少的电流。尽管为了清楚起见图中示出来自比较器208的单个输出,但至少一些实施例中的比较器208具有多个镜像输出,各自控制积分器单元链210中的不同电流源。举例来说,这可使用跨导放大器来实现。如果电流源518A产生的电流增加到高于电流源520A所提供的电流,那么节点534A为高,NMOS晶体管528A接通,且VCO输出信号132的频率下降,因为如下文所描述,LC-VCO 106的总电容升高。如果电流源520A产生的电流增加到高于电流源518A提供的电流,那么节点534A为低,NMOS晶体管528A断开,且VCO输出信号132的频率增加,因为如下所述LC-VCO 106的总电容下降。电容器522A的一个目的是积分器定义链的极点,以及因此频率控制的速度。与PLL带宽相比,频率控制的速度应相对较慢。频率控制(积分器链)不应影响PLL行为。开关514A和516A分别使电流源518A和520A短路,分别取决于“或非”门506A和“与”门508A的输出。电容器530A经由节点532A耦合到LC-VCO 106的其余部分。
[0026]图6是说明性LC-VCO 106的至少一部分的电路示意图。LC-VCO 106包括电压供应轨连接600;电流源602(例如12mA);一对电感器606,608(例如120pH);节点624和626,其间定位有可变电容器610;晶体管(例如NMOS)620,622,其栅极分别耦合到节点626和624;以及接地连接604,其耦合到晶体管620,622的源极。LC-VCO 106进一步包含上文相对于图5所述的晶体管528A,528B和电容器530A,530B。复制耦合到节点624的所述组晶体管和电容器以耦合到节点626,如图所示。可变电容器610可包含电容控制输入,其经由LC-VCO 106的微调信号输入耦合到微调信号120。晶体管528A,528B中的每一者可具有耦合到相应积分器单元的输出的控制输入。举例来说,晶体管528A的栅极(左手侧和右手侧)可耦合到第一积分器单元的输出,且晶体管528B的栅极(左手和右手侧)可耦合到第二积分器单元的输出。激活一或多个晶体管(例如晶体管528A,528B)有效地致使对应电容器(例如电容器530A,530B)并联耦合。这又有效地增加LC-VCO 106的总电容。相反,使晶体管去活减小了LC-VCO 106的总电容。在一些实施例中,激活或去活甚至单个晶体管也可影响LC-VCO 106的总电容。LC-VCO 106的输出跨越端子节点624和626。通过以此方式增加和减小LC-VCO 106的电容,可降低或增加VCO输出信号132的频率,来与P-F参考信号114的频率更密切匹配。这又导致微调信号120具有比原本将具有的电压摆幅小的电压摆幅。当微调信号120具有较小电压摆幅,且LC-VCO 106的增益保持较低(例如增益因数10MHz/V)时,相位噪声减轻,而无传统上与减小VCO增益相关联的电荷泵和变抗器线性问题。
[0027]图7是用于根据多个实施例操作PLL系统的方法700的流程图。方法700通过基于相位-频率参考信号和VCO反馈信号产生微调信号来开始(步骤702)。方法700接下来包括将所述微调信号提供到VCO(步骤704)。出于上面提到的原因,微调将具有比不实施本文中所描述的技术的情况将产生的电压摆幅小的电压摆幅,例如高于和低于电压供应轨的一半的窄范围。方法700接下来包含基于微调信号与电压参考信号的比较来控制LC-VCO的总电容值(步骤706)。在一些实例中,所述比较可为微调信号的经低通滤波版本与电压参考信号之间的比较。如上文所描述,微调信号与电压参考信号的比较结果操纵积分器单元链中的电流源的输出。这又断开和闭合晶体管,其通过操控耦合到晶体管的电容器网络,来增加或减小LC-VCO的总电容。方法700最后包括基于微调信号和VCO电容值产生VCO输出/反馈信号(例如通过使用微调信号来调整LC-VCO中的变抗器值)(步骤708)。可按需要修改方法700,包含通过添加、删除、修改或重排一或多个步骤。
[0028]在所描述实施例中可能进行修改,且其它实施例在权利要求的范围内是可能的。