English:
[0001] In many applications, transistors should have a relatively low specific resistance. For some field-effect-transistors, such as drain-extended metal-oxide-semiconductor (DEMOS) transistors, increasing the oxide thickness over part of the gate oxide may lower specific resistance. SUMMARY
[0002] In at least one example, a method to fabricate a transistor comprises: forming a first dielectric layer on a semiconductor substrate; depositing a barrier layer on the first dielectric layer; depositing an anti-reflective coating on the barrier layer; depositing a photoresist layer; exposing a pattern in the photoresist layer to radiation; etching the photoresist layer according to the pattern to provide an opening in the photoresist layer; etching a portion of the anti -reflective coating below the opening in the photoresist layer; etching a portion of the barrier layer below the opening to expose a portion of the first dielectric layer; providing an ambient oxidizing agent after etching the portion of the barrier layer below the opening to grow an oxide region; removing the barrier layer after providing the ambient oxidizing agent; implanting dopants into the semiconductor substrate after removing the barrier layer; removing the first dielectric layer after implanting dopants into the semiconductor substrate; and forming a second dielectric layer after removing the first dielectric layer, wherein the oxide region is grown to be thicker than the second dielectric layer.
[0003] In at least one example, a method to fabricate a transistor comprises: forming a sacrificial oxide layer on a semiconductor substrate; depositing a silicon nitride layer on the sacrificial oxide layer; depositing an anti -reflective coating on the silicon nitride layer; depositing a photoresist layer; exposing a pattern in the photoresist layer to radiation; etching the photoresist layer according to the pattern to provide an opening in the photoresist layer; etching a portion of the anti-reflective coating below the opening; etching a portion of the silicon nitride layer below the opening to expose a portion of the sacrificial oxide layer; and growing an oxide region on the exposed portion of the sacrificial oxide layer; removing the silicon nitride layer after growing the oxide region; implanting dopants into the semiconductor substrate after removing the silicon nitride layer; removing the sacrificial oxide layer after implanting dopants into the semiconductor substrate; and forming a gate oxide layer on the semiconductor substrate after removing the sacrificial oxide layer, wherein the oxide region is grown to thickness greater than a thickness of the gate oxide layer.
[0004] In at least one example, a method to fabricate a transistor comprises: forming a sacrificial oxide layer on a semiconductor substrate; depositing a silicon nitride layer on the sacrificial oxide layer; depositing a photoresist layer; exposing a pattern in the photoresist layer to radiation; etching the photoresist layer according to the pattern to provide an opening in the photoresist layer; etching a portion of the silicon nitride layer below the opening to expose a portion of the sacrificial oxide layer; growing an oxide region of at least 400 angstroms thick on the exposed portion of the sacrificial oxide layer; removing the silicon nitride layer after growing the oxide region; implanting dopants into the semiconductor substrate after removing the silicon nitride layer to form a drain region in the semiconductor substrate; removing the sacrificial oxide layer after implanting dopants into the semiconductor substrate; and forming a gate oxide layer on the semiconductor substrate after removing the sacrificial oxide layer, the gate oxide layer having a thickness less than 400 angstroms.
[0005] FIG. 1 shows a transistor in various examples.
[0006] FIG. 2 shows a semiconductor substrate with several layers in various examples.
[0007] FIG. 3 shows a silicon substrate after etching in various examples.
[0008] FIG. 4 shows a silicon substrate with an oxide region in various examples.
[0009] FIG. 5 shows a process flow in various examples.
[0010] FIG. 6 shows two transistors in various examples.
[0011] In the described embodiments, a method to fabricate transistors, such as a DEMOS transistor, includes growing a thick oxide below the transistor gate, where the process steps can be incorporated into a standard bipolar complementary-metal-oxide-semiconductor (BiCMOS) process flow.
[0012] FIG. 1 shows a cross-sectional view of an example transistor 100, not drawn to scale. In the example of FIG. 1, the example transistor 100 is a DEMOS transistor. A drain region 104 and a source region 106 are formed in a semiconductor substrate 102. In the example of FIG. 1, the semiconductor substrate 102 is a silicon crystal, and the example transistor 100 is an n-type DEMOS transistor, where the drain region 104 and the source region 106 are each highly doped n- type regions. The source region 106 is formed within a lightly doped p-type well 108, and the drain region 104 is extended by way of the lightly doped n-type region 110.
[0014] When the example transistor 100 is ON, so that the channel below the gate 114 is in an inversion mode, a channel current of majority carriers (e.g., electrons for an n-type channel) flows from the source region 106 to the drain region 104. The presence of the oxide region 116 affects the path of the channel current. The relatively large depth of the oxide region 116 into the channel forces the majority carriers of the channel current to accelerate as they move underneath the oxide region 116 and toward the drain region 104. The acceleration of the majority carriers helps to reduce the specific resistance of the example transistor 100.
[0015] The oxide region 116 may be employed in other types of transistors, such as a double-diffusion metal-oxide-semiconductor (DMOS) transistor, as well as other types of lateral or vertical transistors. Although not shown in FIG. 1, other semiconductor devices may be formed in the semiconductor substrate 102 and coupled to the example transistor 100 to realize various circuits. In some embodiments in which other semiconductor devices are integrated with the example transistor 100, a silicon trench isolation (STI) region is formed around the example transistor 100 to provide electrical isolation from other semiconductor devices.
[0016] FIG. 2 shows a cross-sectional view (not drawn to scale) of the semiconductor substrate 102 and several layers formed during part of a process flow according to embodiments. A sacrificial dielectric layer 204 is formed over the semiconductor substrate 102. In silicon technology, the sacrificial dielectric layer 204 typically comprises silicon dioxide, and will be referred to as a sacrificial oxide layer 204. A barrier layer 206, typically silicon nitride, is deposited on the sacrificial oxide layer 204. A bottom antireflective coating (BARC) 208 is deposited on the barrier layer 206, and a photoresist layer 210 is deposited on the BARC 208.
[0017] The photoresist layer 210 is exposed to radiation according to an illumination pattern defined by a mask (not shown). The pattern illuminated on the photoresist layer 210 defines an opening for growing the oxide region 116 of FIG. 1. In the example of FIG. 2, arrows, such as an arrow 212, pictorially represent the radiation. In some embodiments, the radiation may be in the deep ultraviolet (DUV) region, such as, for example, a wavelength of 248 nm, or a wavelength of 193 nm for an argon fluoride excimer laser source. As process technology nodes move to smaller sizes, embodiments may utilize other types of illumination sources and masks, such as extreme ultraviolet (EUC) lasers used with reflective masks (not shown).
[0018] FIG. 2 does not show all features formed within and on the semiconductor substrate 102. For example, buried layers and STI regions may be formed to electrically isolate various devices formed within and on the semiconductor substrate 102.
[0019] FIG. 3 shows a cross-sectional view (not drawn to scale) of the silicon substrate 102, with the layers of FIG. 2, after etching is performed to provide an opening 302, according to embodiments. The etching may include plasma reactive-ion etching (RIE). The plasma RIE may be performed in a gas mixture of oxygen (02), a carrier gas (e.g., argon), or fluorocarbons comprising carbon (C), Hydrogen (H), and Fluorine (F) having a stoichiometry CxHyFz with x = 1 or 2; y = 0, 1, 2, 3, or 4; and z = 1, 2, 3, or 4.
[0020] FIG. 4 shows a cross-sectional view (not drawn to scale) of the silicon substrate 102, with the layers of FIG. 3, where the oxide region 116 has been grown, according to embodiments. For some embodiments, the oxide region 116 may have a thickness of at least 400 angstroms, for example in the range of 400 angstroms to 4000 angstroms. The semiconductor substrate 102 is exposed to an ambient oxidizing agent to grow the oxide region 116. For some embodiments, the ambient oxidizing is performed in a thermal furnace oxidation process using oxygen and/or steam. For some embodiments, the semiconductor substrate 102 is exposed to oxygen and/or steam at a temperature above 900°C, for example in the range of 950°C to l000°C.
[0021] The thickness of the barrier layer 206 affects formation of the“bird’s beak” (also sometimes referred to as a“birds beak”) shape of the oxide region 116 because of lateral oxidation under the barrier layer 206. The thickness of the barrier layer 206 may have a thickness from 300 angstroms to 1000 angstroms. In some embodiments, the barrier layer 206 may be about
[0022] After forming the oxide region 116, the various layers (excluding the oxide region 116) above the semiconductor substrate 102 illustrated in FIG. 4 are removed, followed by additional process steps to fabricate a transistor, such the example transistor 100 of FIG. 1. For example, dopants can be implanted to form the lightly doped n-type region 110, the drain region 104, and the source region 106. The sacrificial oxide layer 204 is removed before growing the gate oxide layer 112, and the gate 114 is formed over the gate oxide layer 112.
[0023] FIG. 5 shows an example process flow 500. The example process flow 500 includes, in step 501, formation of one or more STI regions; in step 502, forming a first dielectric layer (e.g., the sacrificial oxide layer 204) on a semiconductor substrate (e.g., the semiconductor substrate 102); in step 504, depositing a barrier layer 206 (e.g., a silicon nitride layer) on the first dielectric layer; in step 506, depositing an anti-reflective coating (e.g., the BARC 208) on the barrier layer; in step 508, depositing a photoresist layer (e.g., the photoresist layer 210); in step 510, exposing a pattern in the photoresist layer to radiation; in step 512, etching the photoresist layer according to the pattern to provide an opening in the photoresist layer; in step 514, etching a portion of the anti- reflective coating below the opening in the photoresist layer; in step 516, etching a portion of the barrier layer below the opening to expose a portion of the first dielectric layer; in step 518, providing an ambient oxidizing agent after etching the portion of the barrier layer below the opening; in step 520, removing the barrier layer after providing the ambient oxidizing agent; in step 522, implanting dopants into the semiconductor substrate after removing the barrier layer (e.g., to form the drain region 104 or the source region 106); in step 524, removing the first dielectric layer after implanting dopants into the semiconductor substrate; and in step 526, forming a second dielectric layer (e.g., the gate oxide layer 112) after removing the first dielectric layer.
[0024] The process steps in fabricating a transistor according to embodiments (e.g., the process flow 500) can be incorporated into a standard process flow, for example, a standard BiCMOS process, or a linear BiCMOS (LBC) process. Additional process steps may be performed before and after the process steps in an embodiment, such as the process steps described with respect to FIG. 5. For example, implanting dopants into the semiconductor substrate 102 to form buried regions may be performed before the process flow 500. As another example, an epitaxial layer may be grown on the semiconductor substrate 102 before the process flow 500.
[0025] Some or all of the steps illustrated in FIG. 5 may be repeated when fabricating multiple devices on a wafer. For example, step 526 (and steps related to step 526) may be repeated to fabricate multiple transistors having different thicknesses for their respective gate oxide layers. As a specific example, the dielectric layer formed in an iteration of step 526 may have a thickness of about 40 angstroms, so that one or more transistors are fabricated having a gate oxide layer of about 40 angstroms. In another iteration of step 526, the dielectric layer may have a thickness of about 100 angstroms, so that one or more transistors are fabricated having a gate oxide layer of about 100 angstroms, suitable for a higher operating voltage.
[0026] FIG. 6 shows a cross-sectional view (not drawn to scale) of two example transistors. FIG. 6 shows a semiconductor substrate 602 in which the example transistor 100 is formed, but where the highly doped p-type region 118 (body contact) is not shown. Formed in the semiconductor substrate 602 is an example transistor 600 (with its body contact not shown). An STI region 601 isolates the example transistor 100 from the example transistor 600.
[0027] The example transistor 600 comprises a drain region 604 and a source region 606. In the example of FIG. 6, the example transistor 600 is an n-type DEMOS transistor, where the drain region 604 and the source region 606 are each highly doped n-type regions. The source region 606 is formed within a lightly doped p-type well 608, and the drain region 604 is extended by way of the lightly doped n-type region 610.
[0029] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

中文:
[0001]在许多应用中,晶体管应具有相对低的比电阻。对于一些场效应晶体管,例如漏极延伸金属氧化物半导体(DEMOS)晶体管,增加栅极氧化物部分上方的氧化物厚度可降低比电阻。
[0002]在至少一个实例中,一种制造晶体管的方法包含:在半导体衬底上形成第一电介质层;在所述第一电介质层上沉积阻挡层;在所述阻挡层上沉积抗反射涂层;沉积光致抗蚀剂层;使光致抗蚀剂层中的图案暴露于辐射;根据所述图案蚀刻所述光致抗蚀剂层以在所述光致抗蚀剂层中提供开口;蚀刻光致抗蚀剂层中的开口下方的抗反射涂层的一部分;蚀刻开口下方的阻挡层的一部分以暴露第一电介质层的一部分;在蚀刻开口下方的阻挡层的所述部分之后提供环境氧化剂,以生长氧化物区域;在提供环境氧化剂之后移除阻挡层;在移除阻挡层之后,将掺杂剂植入到半导体衬底中;在将掺杂剂植入到半导体衬底中之后移除第一电介质层;及在移除所述第一电介质层之后形成第二电介质层,其中所述氧化物区域生长为比所述第二电介质层厚。
[0003]在至少一个实例中,一种制造晶体管的方法包含:在半导体衬底上形成牺牲氧化物层;在牺牲氧化物层上沉积氮化硅层;在氮化硅层上沉积抗反射涂层;沉积光致抗蚀剂层;使光致抗蚀剂层中的图案暴露于辐射;根据所述图案蚀刻光致抗蚀剂层以在光致抗蚀剂层中提供开口;蚀刻开口下方的抗反射涂层的一部分;蚀刻开口下方的氮化硅层的一部分以暴露牺牲氧化物层的一部分;及在牺牲氧化物层的暴露部分上生长氧化物区域;在生长氧化物区域之后移除氮化硅层;在移除氮化硅层之后,将掺杂剂植入到半导体衬底中;在将掺杂剂植入到半导体衬底中之后移除牺牲氧化物层;及在移除牺牲氧化物层之后在半导体衬底上形成栅极氧化物层,其中所述氧化物区域生长到比栅极氧化物层的厚度更大的厚度。
[0004]在至少一个实例中,一种制造晶体管的方法包含:在半导体衬底上形成牺牲氧化物层;在牺牲氧化物层上沉积氮化硅层;沉积光致抗蚀剂层;使光致抗蚀剂层中的图案暴露于辐射;根据所述图案蚀刻所述光致抗蚀剂层以在所述光致抗蚀剂层中提供开口;蚀刻开口下方的氮化硅层的一部分以暴露牺牲氧化物层的一部分;在牺牲氧化物层的暴露部分上生长至少400埃厚的氧化物区域;在生长氧化物区域之后移除氮化硅层;在移除氮化硅层之后,将掺杂剂植入到半导体衬底中,以在半导体衬底中形成漏极区域;在将掺杂剂植入到半导体衬底中之后移除牺牲氧化物层;及在移除牺牲氧化物层之后在半导体衬底上形成栅极氧化物层,所述栅极氧化物层具有小于400埃的厚度。
[0005]图1展示在各种实例中的晶体管。
[0006]图2展示在各种实例中具有数个层的半导体衬底。
[0007]图3展示在各种实例中蚀刻之后的硅衬底。
[0008]图4展示在各种实例中具有氧化物区域的硅衬底。
[0009]图5展示在各种实例中的工艺流程。
[0010]图6展示在各种实例中的两个晶体管。
[0011]在所描述的实施例中,制造晶体管(例如DEMOS晶体管)的方法包括在晶体管栅极下方生长厚氧化物,其中工艺步骤可并入到标准双极互补金属氧化物半导体(BiCMOS)工艺流程中。
[0012]图1展示未按比例绘制的实例晶体管100的横截面图。在图1的实例中,实例晶体管100是DEMOS晶体管。漏极区域104及源极区域106在半导体衬底102中形成。在图1的实例中,半导体衬底102是硅晶体,且实例晶体管100是n型DEMOS晶体管,其中漏极区域104及源极区域106每一者是高掺杂n型区域。源极区域106在轻掺杂p型阱108内形成,且漏极区域104通过轻掺杂n型区域110延伸。
[0014]当实例晶体管100导通,使得栅极114下方的沟道处于反转模式时,大多数载流子的沟道电流(例如,n型沟道的电子)从源极区域106流向漏极区域104。氧化物区域116的存在影响沟道电流的路径。氧化物区域116进入沟道的相对较大深度迫使沟道电流的大多数载流子随着它们在氧化物区域116下面并朝向漏极区域104移动时加速。大多数载流子的加速有助于减小实例晶体管100的比电阻。
[0015]氧化物区域116可用在其它类型的晶体管中,例如双扩散金属氧化物半导体(DMOS)晶体管以及其它类型的横向或垂直晶体管。尽管在图1中未展示,但是其它半导体装置可在半导体衬底102中形成且耦合到实例晶体管100以实现各种电路。在其它半导体装置与实例晶体管100集成的一些实施例中,在实例晶体管100周围形成硅沟槽隔离(STI)区域以提供与其它半导体装置的电隔离。
[0016]图2展示根据实施例的在工艺流程的部分期间半导体衬底102及形成的数个层的横截面图(未按比例绘制)。在半导体衬底102上形成牺牲电介质层204。在硅技术中,牺牲电介质层204通常包含二氧化硅,且将被称为牺牲氧化物层204。在牺牲氧化物层204上沉积阻挡层206,通常为氮化硅。在阻挡层206上沉积底部抗反射涂层(BARC)208,且在BARC 208上沉积光致抗蚀剂层210。
[0017]光致抗蚀剂层210根据由掩模(未展示)定义的照射图案暴露于辐射。照射在光致抗蚀剂层210上的图案定义用于生长图1的氧化物区域116的开口。在图2的实例中,箭头(例如箭头212)图示地表示辐射。在一些实施例中,辐射可在深紫外线(DUV)区域中,举例来说,例如波长为248nm,或对于氟化氩准分子激光源,波长为193nm。随着工艺技术节点向更小的尺寸移动,实施例可利用其它类型的照射源及掩模,例如与反射掩模(未展示)一起使用的极紫外线(EUC)激光器。
[0018]图2未展示在半导体衬底102内及其上形成的所有特征。例如,可形成掩埋层及STI区域,以电隔离在半导体衬底102内及其上形成的各种装置。
[0019]图3展示根据实施例的在执行蚀刻以提供开口302之后,具有图2的层的硅衬底102的横截面图(未按比例绘制)。蚀刻可包括等离子体反应离子蚀刻(RIE)。等离子体RIE可在氧气(O2)、载气(例如氩气)或氟碳化合物的气体混合物中执行,所述氟碳化合物包含碳(C)、氢(H)及氟(F),具有化学计量CxHyFz,其中x=1或2;y=0、1、2、3或4;及z=1、2、3或4。
[0020]图4展示根据实施例的具有图3的层的硅衬底102的横截面图(未按比例绘制),其中氧化物区域116已经生长。对于一些实施例,氧化物区域116可具有至少400埃的厚度,例如在400埃到4000埃的范围内。半导体衬底102暴露于环境氧化剂以生长氧化物区域116。对于一些实施例,环境氧化是在使用氧气及/或蒸汽的热炉氧化工艺中进行的。对于一些实施例,半导体衬底102在高于900°C的温度下(例如在950°C至1000°C的范围内)暴露于氧气及/或蒸汽。
[0021]由于阻挡层206下方的横向氧化,阻挡层206的厚度影响氧化物区域116的“鸟嘴”(有时也称为“鸟喙”)形状的形成。阻挡层206的厚度可具有300埃到1000埃的厚度。在一些实施例中,阻挡层206可为约950埃厚。
[0022]在形成氧化物区域116之后,移除图4所说明的半导体衬底102上方的各个层(除氧化物区域116之外),然后是制造晶体管的额外工艺步骤,例如图1的实例晶体管100。例如,可将掺杂剂植入以形成轻掺杂n型区域110、漏极区域104及源极区域106。在生长栅极氧化物层112之前移除牺牲氧化物层204,且栅极114在栅极氧化物层112上方形成。
[0023]图5展示实例工艺流程500。在步骤501中,实例工艺流程500包括形成一或多个STI区域;在步骤502中,在半导体衬底(例如,半导体衬底102)上形成第一电介质层(例如,牺牲氧化物层204);在步骤504中,在第一电介质层上沉积阻挡层206(例如,氮化硅层);在步骤506中,在阻挡层上沉积抗反射涂层(例如,BARC 208);在步骤508中,沉积光致抗蚀剂层(例如,光致抗蚀剂层210);在步骤510中,使光致抗蚀剂层中的图案暴露于辐射;在步骤512中,根据图案蚀刻光致抗蚀剂层以在光致抗蚀剂层中提供开口;在步骤514中,蚀刻光致抗蚀剂层中的开口下方的抗反射涂层的一部分;在步骤516中,蚀刻开口下方的阻挡层的一部分以暴露第一电介质层的一部分;在步骤518中,在蚀刻开口下方的阻挡层的所述部分之后提供环境氧化剂;在步骤520中,在提供环境氧化剂之后移除阻挡层;在步骤522中,在移除阻挡层之后将掺杂剂植入到半导体衬底中(例如,用于形成漏极区域104或源极区域106);在步骤524中,在将掺杂剂植入到半导体衬底中之后移除第一电介质层;及在步骤526中,在移除第一电介质层之后形成第二电介质层(例如,栅极氧化物层112)。
[0024]根据实施例的制造晶体管的工艺步骤(例如,工艺流程500)可并入到标准工艺流程中,例如,标准BiCMOS工艺或线性BiCMOS(LBC)工艺。可在实施例中的工艺步骤(例如关于图5描述的工艺步骤)之前及之后执行额外工艺步骤。例如,可在工艺流程500之前执行将掺杂剂植入到半导体衬底102中以形成掩埋区域。作为另一实例,可在工艺流程500之前在半导体衬底102上生长外延层。
[0025]当在晶圆上制造多个装置时,可重复图5所说明的一些或全部步骤。例如,可重复步骤526(及与步骤526相关的步骤)以制造对于其相应的栅极氧化物层具有不同厚度的多个晶体管。作为具体实例,在步骤526的迭代中形成的电介质层可具有约40埃的厚度,使得一或多个晶体管被制造成具有约40埃的栅极氧化物层。在步骤526的另一迭代中,电介质层可具有约100埃的厚度,使得一或多个晶体管被制造成具有约100埃的栅极氧化物层,适于较高的操作电压。
[0026]图6展示两个实例晶体管的横截面图(未按比例绘制)。图6展示在其中形成实例晶体管100的半导体衬底602,但其中未展示高掺杂p型区域118(主体接触)。在半导体衬底602中形成实例晶体管600(其主体接触未展示)。STI区域601将实例晶体管100与实例晶体管600隔离。
[0027]实例晶体管600包含漏极区域604及源极区域606。在图6的实例中,实例晶体管600是n型DEMOS晶体管,其中漏极区域604及源极区域606每一者是高掺杂n型区域。源极区域606在轻掺杂p型阱608内形成,且漏极区域604通过轻掺杂n型区域610延伸。
[0029]在权利要求书的范围内,在所描述的实施例中修改是可行的,且其它实施例是可行的。