English:
[0001] Generally, the invention relates to testing storage devices under certain test conditions. More specifically, the invention relates to adjusting an error correction capability of an LDPC code such that the sector failure rate of the storage device can be incrementally determined.
[0002] In many storage devices, data is commonly written to and retrieved from the devices in contiguous blocks. In a disk drive, a read/write channel in performs such reading and writing. The read/write channel improves the detection of the data that is written to and read from the hard disk using certain detection algorithms. For example, algorithms like PRML (Partial Response signaling with Maximum Likelihood detection) increase the signal to noise ratio (SNR) of the data being read from the hard disk which increases the likelihood that the data will be read properly. Since correct detection of the data is more likely, these algorithms may allow for the increase of areal densities on the disk (i.e., an increased number of storable bits on the hard disk). As data errors can increase with increased areal density, however, error control coding is used to improve the performance of the detection algorithm. Often, Reed-Solomon codes (RS codes) provide for this error correction capability.
[0004] Disk drive manufacturers generally establish a code level of "T=20" for the maximum level of correction required to meet the maximum error rates that a disk drive is expected to endure as the hard disk degrades. A T=20 code level requires 20 bits of code for 40 bits of data. During the manufacturing process, the disk drives are tested to ensure that the drives meet some requisite level of error rates for given SNRs. Since the hard disks are new, they are likely to encounter fewer errors than their aging counterparts. However, some new disks will experience an unacceptable number of errors due to inconsistencies in the manufacturing process. To ensure that the disks meet acceptable SFRs for certain SNRs without being recovered by the full T=20 error correction, the code level is "dialed back" to T=5.
[0005] Presently, disk drive manufacturers are seeking to employ other codes as areal densities and processing capabilities increase with technological advances. One code presently being implemented is called the Low Density Parity Check (LDPC) code. The LDPC codes are relatively complex and thus computationally intensive. For example, the LDPC codes correct errors in larger contiguous blocks of data than the RS codes and thus require more computations. The LDPC codes are generally capable of correcting more errors than the RS codes and appear to be the heirs apparent in error correction as processing capabilities have significantly increased over time. The LDPC codes, however, do not have the RS code capability of "dialing back" to ensure that manufactured test drives meet some requisite minimum level of SFRs. Thus, there exists a need to reduce the level of LDPC error correction for testing purposes if the LDPC codes are to be used in storage devices.
[0006] The present invention solves the above and other problems, thereby advancing the state of the useful arts, by providing methods and structure for adjusting an error correction capability of a low density parity check error correction code. For example, storage devices generally require testing prior to customer delivery. Previously, the storage devices were tested by dialing back the RS code of the encoded data, as described above. Since the advent of LDPC codes in storage devices, error correction capabilities of the LDPC was essentially at "full scale", requiring the computationally intensive full use of the LDPC while forgoing the ability to establish the SFR of a recently manufactured storage device. A system, in one embodiment, overcomes these limitations by providing a decoder that adapted to decode LDPC encoded data. A detector is communicatively coupled to the decoder and adapted to estimate bit values in the data prior to decoding by the decoder. The detector is further adapted to change bit values based on bit value estimations to reduce the error correction capability of the low density parity check error correction code.
[0007] Another aspect of the invention regards a method of testing a disk drive includes encoding data with an LDPC code and storing the encoded data on the disk drive. The method further includes reading the encoded data from the disk drive, estimating bit values in the encoded data, and changing a portion of the bit values in the encoded data based on bit value estimations. The method also includes decoding the encoded data according to the low density parity check code in response to changing said portion of the bit values to determine a sector failure rate in the disk drive.
[0008] Another aspect of the invention regards a system adapted to test a disk drive. The system includes a write module adapted to encode data with an LDPC code and write the encoded data to the disk drive. The system also includes a read module adapted to read the encoded data from the disk drive, estimate bit values in the encoded data and change a portion of the bit values based on the bit value estimations. The changed bit values reduce an error correction capability of the low density parity check code to determine a sector failure rate of the disk drive.
[0009] FIG. 1 is an exemplary system for adjusting an error correction capability of an LDPC code.
[0010] FIG. 2 is a graph illustrating SFR analysis for various LDPC error correction adjustments.
[0012] FIG. 4 is an exemplary flow chart of a method for testing a storage device.
[0013] FIGS. 1-4 and the following description depict specific exemplary embodiments of the invention to teach those skilled in the art how to make and use the invention. For the purpose of teaching inventive principles, some conventional aspects of the invention have been simplified or omitted. Those skilled in the art will appreciate variations from these embodiments that fall within the scope of the invention. Those skilled in the art will appreciate that the features described below can be combined in various ways to form multiple variations of the invention. As a result, the invention is not limited to the specific embodiments described below, but only by the claims and their equivalents.
[0014] FIG. 1 is an exemplary system 10 for adjusting an error correction capability of an LDPC code. In this embodiment, the system 10 includes an LDPC decoder 12 that is adapted to decode LDPC encoded data. LDPC codes are codes that, when decoded, approach the "Shannon limit", or the theoretical bound for channel capacity for a given modulation and code rate. That is, Shannon's limit may be viewed as being the data rate to be used in a communication channel, having a particular SNR, that achieves error free transmission through the communication channel.
[0016] When reading data from the storage system, the LDPC decoder 12 may decode the data based on a bipartite graph of a given LDPC code such that the graph includes both bit nodes and check nodes. The In-phase/Quadrature (I/Q) values associated with received symbols are associated with a symbol node and that symbol node is associated with corresponding bit nodes. Bit metrics are then calculated for the individual bits of the corresponding symbols and those bit metrics are provided to the bit nodes of the bipartite graph of the given LDPC code. Edge information corresponding to the edges that interconnect the bit nodes and the check nodes is calculated, appropriately updated, and communicated back and forth between the bit nodes and the check nodes during iterative decoding of the LDPC encoded signal. The bit metric values that are employed are generally fixed values that are used repeatedly in the iterative decoding process.
[0017] Due to the structure of the LDPC codes, the decoder 12 is not readily configurable to change error correction capabilities. That is, the decoder 12 is configured in such a way so as to decode data according to the same LDPC code used to encode the data. Thus, the error correction capabilities of the decoder 12 are generally static, unlike the scalable RS codes. As mentioned, manufacturers generally desire to test storage devices by "dialing back" the error correction capability of a code to approach an expected failure rate of the storage device associated with manufacturing processes. Since the decoder 12 is generally incapable of readily adjusting the error correction capability, the system 10 is configured with the detector 11 that is adapted to estimate bit values in the data prior to decoding by the decoder 12. The detector 11 changes bit values based on bit value estimations, prior to decoding by the decoder 12, to reduce the error correction capability of the LDPC error correction code.
[0018] To illustrate, when the decoder 12 receives a valid codeword with bits in error (e.g., degraded to the point which they are unrecognizable), the decoder 12 considers the bits to be missing from the codeword. The decoder 12 responds by correcting the bits using the error correction capabilities of the LDPC code. The system 10 overcomes this error correction capability by having the detector 11 correct the missing bits, or a portion thereof, prior to decoding by the decoder 12 thereby removing the need for the decoder 12 to correct the bits. By having the detector 11 operate on a predetermined interval of bits, the error correction capability of the decoder 12 may, in essence, be "dialed back".
[0019] By adjusting the data interval in which the detector 11 corrects bits, the system 10 is capable of analyzing SFRs for various signal-to-noise ratios in a storage system. For example, FIG. 2 is a graph illustrating SFR analysis for various LDPC error correction adjustments. The y-axis 41 illustrates the SFR for a storage device. The SFR of the y-axis 41 is shown in symbol (i.e., 10-bits) errors per LDPC codeword. The x-axis 42 illustrates the SNR of the read signal (i.e., the LDPC encoded data) in decibels. Each of the "steps" 43 - 48 illustrate a bit interval check performed by the detector 11.
[0020] To illustrate, when the detector corrects every 50thbit in the LDPC encoded data (i.e., step 48), the SFR decreases as SNR increases; however, it does so at a less dramatic rate as when the LDPC decoder 12 is allowed to decode every bit of the LDPC encoded data, as illustrated in step 43. By removing the ability to correct every bit in the LDPC encoded data, a technician may be able to determine whether a manufactured storage device meets some requisite minimum level of SFR for a given SNR in a manner similar to the RS code dialing back described above. Accordingly, when a storage device is tested by reading data from the device and correcting bits at a particular bit interval, the determined SFR may be used to qualify the storage device for customer use.
[0021] In one embodiment, the detector 11 employs a soft output Viterbi algorithm (SOVA). A SOVA differs from the classical Viterbi algorithm in that it uses a modified path metric, which takes into account known probabilities of input symbols and produces a soft output indicating the reliability of the decision. For example, detector 11 may estimate the log likelihood ratio (LLR) at a particular bit interval to establish the bit value at that bit interval. When a possible error is detected, the detector 11 may estimate whether the bit is either a one or a zero. Detection of the present invention, however, is not intended be limited to SOVA as other detection algorithms may be used to estimate the probability of a particular received bit.
[0022] FIG. 3 represents a block diagram of a disk drive 70 having a read/write channel 74 employing the system 10 of FIG. 1. In this embodiment, the read/write heads 72 are operative Iy disposed adjacent to the magnetic disks 71 to magnetically record (i.e., write) data onto the magnetic disks 71 from the host device 76. The read/write heads 72 also sense magnetic flux reversals on the magnetic disks 71 to read from the magnetic disks 71 and transfer data to the host device 76. To write data onto the magnetic disks 71, the host device 76 provides the controller 75 with a data signal and the location (e.g., a sector address of the magnetic disks 71) to write the data signal on the magnetic disks. The controller 75 directs the read/write heads 72 to move into the proper location and transfers the data signal to the read/write channel 74. The read/write channel 74 LDPC encodes the data signal and converts it to analog signals. The read/write channel 74 transfers the analog signals to the amplifiers 73 for amplification. The amplifiers 73 then transfer the amplified analog signals to the read/write heads 72. The read/write heads 72 impart magnetic flux reversals onto the magnetic disks 71 representative of the data signal. The read/write channel 74 may control the magnetic flux reversals via peak detection, PRML encoding, or the like.
[0023] Generally, to read data from the magnetic disks 71, the host device 76 provides a location identifier, or sector address of the magnetic disk 71, to the disk drive 70. The controller 10 receives the location identifier and determines the physical location of the data on the disks 71. The controller 75 directs one or more of the read/write heads 72 to move into the proper position for the data on the magnetic disks 71 to spin adjacent to the read/write heads 72. As the magnetic disks 71 spin, the read/write heads 72 sense the presence or absence of flux reversals on the magnetic disks 71. The read/write heads generate an analog signal in response to the flux reversals. The read/write heads 72 transfer the analog signal to the amplifiers 73, which amplify and convey the analog signal to the read/write channel 74. The read/write channel 74 decodes the amplified analog signal into a binary digital data signal via peak detection, PRML decoding, or the like. The read/write channel 74 transfers the data signal to the controller 75, which subsequently transfers the data signal to the host device 76.
[0024] The read/write channel 74, in this embodiment, includes the system 10 FIG. 1 so as to reduce the error correction capability of the LDPC code used to originally encode the data signal. That is, when the data is read from the magnetic disks 71, the system 10 detects missing bits in LDPC codewords and corrects them prior to being decoded by the LDPC decoder (e.g., the LDPC decoder 12). Since the missing bits have been corrected, the system 10 bypasses the LDPC decoding of those bits and thereby reduce the effectiveness of the LDPC decoder.
[0025] Although shown and described with respect to the system 10 being implemented with the disk drive 70, the invention is not intended to be so limited. Rather, the system 10 may be implemented in any device employing LDPC codes where it is desired to have the error correction capability of the LDPC code "dialed back". For example, LDPC codes may be used to encode data for storage on flash memory devices. Accordingly, when manufacturers wish to test the SFRs of the flash memory devices before customer delivery, the LDPC code error correction capability may be dialed back in a similar manner. Nor is the invention intended to be limited to implementation with the read/write channel 74. For example, the system 10 may be implemented as hardware, software, firmware, or combinations thereof in almost any device where the error correction capabilities of the LDPC code require dialing back. In this regard, the system 10 may be implemented with the controller 75 or even the host device 76.
[0026] FIG. 4 is an exemplary flow chart of a method 80 for testing a storage device. In this embodiment, data is first encoded with an LDPC code in the process element 81 and the encoded data is then stored with the storage device in the process element 82. The storage device may be any storage device capable of storing digital data, such as a disk drive, a flash memory drive, an optical drive (e.g., CD-ROM), etc. More particularly, any storage device may be used where it is technologically feasible to employ LDPC codes for data storage.
[0027] The LDPC encoded data is read from the storage device, in the process element 83. In one particular embodiment, a read head in a disk drive may detect magnetic flux reversals on a magnetic disk of the disk drive to form an analog signal that is subsequently converted to a digital signal (i.e., digital data). Then, prior to decoding LDPC encoded data, bit values in the data are estimated, in the process element 84. For example, a detector may periodically analyze bits in the read datastream to determine possible errors in the data. More particularly, the detector may be a SOVA detector that estimates the LLR at a particular bit interval to establish the bit value at that bit interval. When a possible error is detected, the detector may estimate whether the bit is either a one or a zero. Accordingly, when these possible errors are detected at the bit intervals, the detector may change a portion of the bit values based on the bit value estimations, in the process element 85. Thereafter, the data may be decoded according to the LDPC code, in the process element 86. For example, an LDPC decoder may decode the data according to the LDPC code used to encode the data. Because various errors were previously estimated and corrected via the detector, the error correction capability of the LDPC code is thereby reduced, or "dialed back".
[0028] The decoder while decoding the LDPC encoded data may determine a SFR with a storage device, in the process element 87. For example, even with certain bit errors being estimated and corrected in the data via the detector, errors are still likely to occur in the read data. The decoder may accumulate statistics regarding the number of errors that are corrected relative to the overall read data during the LDPC decoding process. Thus, the decoder may determine a bit error rate, or SFR, in the read data. Generally, since the detector is correcting a portion of the read data prior to decoding by the decoder, the SFR is likely to decrease. However, the SFR in a relatively new device is likely to be fairly low. Accordingly, the scaling back of the LDPC error correction capability allows a technician to observe SFRs that are generally associated with manufacturing inconsistencies. In this regard, the method 80 may continue by determining whether the SFR is greater than a threshold, in the process element 88. If so, the storage device may be removed from production (e.g., for refurbishing, destruction, etc.), in the process element 89. Otherwise, the storage device may be readied for customer delivery, in the process element 90.
[0029] While the invention has been illustrated and described in the drawings and foregoing description, such illustration and description is to be considered as exemplary and not restrictive in character. One embodiment of the invention and minor variants thereof have been shown and described. Protection is desired for all changes and modifications that come within the spirit of the invention. Those skilled in the art will appreciate variations of the above-described embodiments that fall within the scope of the invention. As a result, the invention is not limited to the specific examples and illustrations discussed above, but only by the following claims and their equivalents.

中文:
[0001]总的来说,本发明涉及在某些测试条件下测试存储装置。更具体地,本发明涉及调节LDPC码的纠错能力以使得能够渐进地确定存储装置的扇区故障率。
[0002]在许多存储装置中,通常以连续的块将数据写入到所述装置和从所述装置取回数据。在盘驱动器中,读/写通道执行这样的读取和写入。读/写通道利用某些检测算法改善对写入到硬盘和从硬盘读取的数据的检测。例如,如PRML(利用最大似然性检测的部分响应信令)的算法增加了从硬盘读取的数据的信噪比(SNR),这增加了数据将被正确地读取的可能性。由于更加可能正确检测数据,因此这些算法可以允许增加盘上的面积密度(areal densities)(即,硬盘上可存储比特数目增加)。然而,由于数据误差可以随着面积密度的增加而增加,因此使用误差控制编码来改善检测算法的性能。通常,里德-所罗门码(RS码)提供了这样的纠错能力。
[0004]盘驱动器制造商通常对于满足预期盘驱动器由于硬盘劣化而承受的最大错误率所需的最大校正水平建立“T=20”的码等级(code level)。T=20的码等级对于40比特的数据要求20比特的码。在制造处理过程期间,盘驱动器被测试以确保驱动器对于给定的SNR满足某些必须的错误率等级。由于这些硬盘是新的,因此与老化的硬盘相比它们很可能遇到较少的错误。然而,由于制造处理过程中的不一致性,某些新的盘将经历数目不可接受的错误。为了确保对于某些SNR盘满足可接受的SFR而不需通过完全的T=20纠错恢复,码等级被“回拨”到T=5。
[0005]目前,随着技术进步面积密度和处理能力增加,盘驱动器制造商在寻求采用其它的码。目前实现的一种码被称作低密度奇偶校验(LDPC)码。LDPC码相对复杂,并因此是计算密集的。例如,与RS码相比,LDPC码以更大的连续的数据块纠正错误,并因此要求更多的计算。由于处理能力随着时间已经显著增长,因此,与RS码相比,LDPC码通常能够纠正更多的错误,并且看起来在纠错方面要成为显然的继任者。然而,LDPC码并不具有RS码的用以确保制造的测试驱动器满足某些必须的最低等级的SFR的“回拨”能力。因此,如果要在存储装置中使用LDPC码,则出于测试目的需降低LDPC纠错的等级。
[0006]本发明通过提供用于调节低密度奇偶校验纠错码的纠错能力的方法和结构,来解决上述的以及其它问题,从而促进了本领域的当今技术的发展。例如,存储装置通常要求在递送客户之前进行测试。以前,如上所述的,通过将编码的数据的RS码回拨来测试存储装置。由于在存储装置中出现LDPC码,因此LDPC的纠错能力基本上处在“满幅(full scale)”,要求计算密集地完全使用LDPC同时放弃建立新近制造的存储装置的SFR的能力。在一个实施例中,一种系统通过提供适于对LDPC编码的数据解码的解码器克服了这些限制。检测器通信地耦接到所述解码器,并且该检测器适于在解码器解码之前估计数据中的比特值。所述检测器进一步适于基于比特值估计改变比特值,以降低所述低密度奇偶校验纠错码的纠错能力。
[0007]本发明的另一方面涉及一种测试盘驱动器的方法,包括:以LDPC码编码数据和将编码的数据存储在所述盘驱动器上。所述方法进一步包括:从所述盘驱动器读取所述编码的数据;估计所述编码的数据中的比特值;以及基于比特值估计改变所述编码的数据中的比特值中的一部分。所述方法还包括:响应于对所述比特值的所述部分的改变,根据所述低密度奇偶校验码解码所述编码的数据,以确定所述盘驱动器中的扇区故障率。
[0008]本发明的另一方面涉及一种适于测试盘驱动器的系统。所述系统包括写入模块,所述写入模块适于以LDPC码对数据编码以及将编码的数据写入到所述盘驱动器。所述系统还包括读取模块,其适于:从所述盘驱动器读取所述编码的数据;估计所述编码的数据中的比特值;以及基于比特值估计改变所述比特值中的一部分。所述改变的比特值降低了所述低密度奇偶校验码的纠错能力,以确定所述盘驱动器的扇区故障率。
[0009]图1是用于调节LDPC码的纠错能力的示例性系统。
[0010]图2是示出了对于多种LDPC纠错调节的SFR分析的图。
[0012]图4是用于测试存储装置的方法的示例性流程图。
[0013]图1-4以及下面的说明描述了本发明的具体的示例性实施例,以教导本领域技术人员如何制造和使用本发明。出于教导发明原理的目的,本发明的某些常规方面已经被简化或省略。本领域技术人员将理解,源自这些实施例的各种变化,其都落在本发明的范围内。本领域技术人员将理解,下面描述的特征可以以多种方式组合来形成本发明的多种变型。因此,本发明并不限于下面描述的具体实施例,而是仅由权利要求及其等同物决定。
[0014]图1是用于调节LDPC码的纠错能力的示例性系统10。在该实施例中,系统10包括LDPC解码器12,LDPC解码器12适于解码LDPC编码的数据。LDPC码是这样的码:对于给定的调制及码率,其在被解码时逼近信道容量的理论界限或“香农限”。也即,香农限可以被视为要在具有特定的SNR的通信信道中使用的、实现通过所述通信信道的无错误传输的数据率(data rate)。
[0016]在从所述存储系统读取数据时,LDPC解码器12可以基于给定的LDPC码的二部图(bipartite graph)对数据解码,所述图包括比特节点和检查节点。与接收到的码元相关联的同相/正交(I/Q)值被与码元节点相关联,并且该码元节点被与相应的比特节点相关联。然后对于相应码元的单独的比特计算比特量度(Bit metrics),并且将这些比特量度提供到给定的LDPC码的二部图的比特节点。在LDPC编码的信号的迭代解码期间,计算、适当地更新并在比特节点和检查节点之间来回通信与互联比特节点和检查节点的边缘对应的边缘信息。被采用的比特量度值通常是在迭代解码处理中重复使用的固定值。
[0017]由于LDPC码的结构,解码器12并不是可容易配置来改变纠错能力的。也即,解码器12被以这样的方式配置来根据用来对数据编码的相同LDPC码来解码数据。因此,解码器12的纠错能力通常是静态的,不同于可缩放的RS码。如所述的,制造商通常期望通过“回拨”码的纠错能力以逼近存储装置的与制造处理过程相关联的预期故障率来测试存储装置。由于解码器12通常不能容易地调节纠错能力,因此系统10配置有检测器11,检测器11适于在解码器12解码之前估计数据中的比特值。检测器11在解码器12解码之前基于比特值估计改变比特值,以降低LDPC纠错码的纠错能力。
[0018]为了说明起见,在解码器12接收到具有错误比特的有效码字(例如,劣化到它们不可识别的程度)时,解码器12将这些比特视为从码字丢失。解码器12通过利用LDPC码的纠错能力纠正该比特来做出响应。系统10通过使检测器11在解码器12解码之前纠正所述丢失的比特或者其一部分,从而不需要解码器12纠正这些比特,来“压制”该纠错能力。通过使检测器11操作在预定的比特间隔上,解码器12的纠错能力实质上可以被“回拨”。
[0019]通过调节检测器11纠正比特的数据间隔,系统10能够分析存储系统中的多种信噪比的SFR。例如,图2是示出了对于多种LDPC纠错调节的SFR分析的图。y轴41示出了存储装置的SFR。y轴41的SFR以每LDPC码字的码元(即,10比特)错误来表示。x轴42示出了以分贝表示的读取信号(即,LDPC编码的数据)的SNR。“步阶(step)”43-48中的每一个示出了检测器11执行的比特间隔检查。
[0020]出于说明的目的,当检测器在LDPC编码的数据中每50个比特进行纠正时(即,步阶48),SFR随着SNR增加而降低;然而,如在步阶43中所示,在允许LDPC解码器12解码LDPC编码的数据中的每一比特时,也是如此,只是以较不显著的比率。通过去除纠正LDPC编码的数据中的每一比特的能力,技术人员可以能够以与上面所述的RS码回拨类似的方式来确定所制造的存储装置对于给定的SNR是否满足某一必须的最低SFR等级。因此,在通过从存储装置读取数据并以特定的比特间隔纠正比特来测试存储装置时,可以使用所确定的SFR来验证存储装置合格以供客户使用。
[0021]在一个实施例中,检测器11采用软输出维特比(Viterbi)算法(SOVA)。SOVA不同于经典的维特比算法之处在于其利用修改的路径量度,这考虑了输入码元已知的可能性并产生指示判决的可靠性的软输出。例如,检测器11可以以特定的比特间隔估计对数似然比(LLR),来以该比特间隔建立比特值。在检测到可能的错误时,检测器11可以估计该比特是一还是零。然而,本发明的检测意图并不限于SOVA,因为也可以使用其它的检测算法来估计特定的接收比特的概率。
[0022]图3表示具有采用图1的系统10的读/写通道74的盘驱动器70的框图。在该实施例中,读/写头72操作设置为与磁盘71相邻,以将数据从主机装置76磁性地记录(即,写入)到磁盘71上。读/写头72还感测磁盘71上的磁通量反转(reversal),以从磁盘71读取并传输数据到主机装置76。为了写入数据到磁盘71上,主机装置76向控制器75提供数据信号以及要将该数据信号写入在磁盘上的位置(例如,磁盘71的扇区地址)。控制器75指引读/写头72移动到适当位置中,并将数据信号传输到读/写通道74。读/写通道74对该数据信号LDPC编码,并将其转换为模拟信号。读/写通道74将该模拟信号传输到放大器73以供放大。然后放大器73将放大的模拟信号传输到读/写头72。读/写头72将表示该数据信号的磁通量反转施加到磁盘71上。读/写通道74可以通过峰值检测、PRML编码、或类似物来控制所述磁通量反转。
[0023]通常,为了从磁盘71读取数据,主机装置76将位置标识符或磁盘71的扇区地址提供到盘驱动器70。控制器10接收该位置标识符并确定盘71上数据的物理位置。控制器75指引一个或更多个读/写头72移动到与读/写头72相邻地旋转的磁盘71上数据的适当设置中。随着磁盘71的旋转,读/写头72感测磁盘71上通量反转的存在或不存在。读/写头响应于通量反转产生模拟信号。读/写头72将该模拟信号传输到放大器73,放大器73放大该模拟信号并将其传递到读/写通道74。读/写通道74通过峰值检测、PRML解码或类似物将放大的模拟信号解码成二进制数字数据信号。读/写通道74将该数据信号传输到控制器75,控制器75随后将该数据信号传输到主机装置76。
[0024]在该实施例中,读/写通道74包括图1的系统10以便降低用来对数据信号原始编码的LDPC码的纠错能力。也即,在从磁盘71读取数据时,系统10检测LDPC码字中的丢失比特,并在它们被LDPC解码器(例如,LDPC解码器12)解码之前纠正它们。由于丢失比特已经被纠正,因此系统10绕过(bypass)这些比特的LDPC解码,从而降低了LDPC解码器的效能。
[0025]尽管就结合盘驱动器70实现的系统10进行了示出和说明,然而本发明意图并不限于此。而是,系统10可以实现在任何采用LDPC码的、其中期望使LDPC码的纠错能力“回拨”的装置中。例如,可以使用LDPC码来编码用于存储在闪存存储器装置上的数据。因此,在制造商希望在递送客户之前测试闪存存储器装置的SFR时,可以以类似的方式将LDPC码纠错能力回拨。本发明意图也不限于具有读/写通道74的实现方式。例如,系统10可以在几乎任何要求回拨LDPC码的纠错能力的装置中实现为硬件、软件、固件、或其组合。就此而言,系统10可以结合控制器75或甚至主机装置76实现。
[0026]图4是用于测试存储装置的方法80的示例性流程图。在该实施例中,在处理元81中,数据首先被用LDPC码编码,然后在处理元82中,用存储装置存储编码的数据。所述存储装置可以是任何能够存储数字数据的存储装置,诸如盘驱动器、闪存存储器驱动器、光学驱动器(例如,CD-ROM)等。更特别地,在采用LDPC码以用于数据存储在技术上可行的情况下,可以使用任何存储装置。
[0027]在处理元83中,从所述存储装置读取LDPC编码的数据。在一个特定实施例中,盘驱动器中的读取头可以检测盘驱动器的磁盘上的磁通量反转来形成模拟信号,该模拟信号随后被转换为数字信号(即,数字数据)。然后,在解码LDPC编码的数据之前,在处理元84中,估计数据中的比特值。例如,检测器可以周期性地分析读取数据流中的比特以确定数据中可能的错误。更特别地,所述检测器可以是SOVA检测器,其以特定的比特间隔估计LLR以建立在该比特间隔的比特值。在检测到可能的错误时,检测器可以估计该比特是一还是零。因此,当在该比特间隔处检测到这些可能的错误时,在处理元85中,检测器可以基于比特值估计改变比特值的一部分。之后,在处理元86中,可以根据LDPC码解码数据。例如,LDPC解码器可以根据用来对数据编码的LDPC码解码数据。由于先前通过检测器估计并纠正了多种错误,从而LDPC码的纠错能力被降低或“回拨”。
[0028]在处理元87中,解码器可以在对LDPC编码的数据解码的同时确定存储装置的SFR。例如,即使利用数据中的通过检测器估计并纠正了的某些比特错误,在读取数据中也仍很可能出现错误。解码器可以累计关于在LDPC解码处理期间纠正的错误的数目相对于总的读取数据的统计数据。因此,解码器可以确定读取数据中的误比特率(bit error rate)或SFR。通常,由于检测器在解码器解码之前纠正一部分读取数据,因此SFR很可能减小。然而,相对新的装置中的SFR很可能是相当低的。因此,将LDPC纠错能力缩放回(scaling back)允许技术人员观察通常与制造不一致性相关联的SFR。就此而言,方法80可以在处理元88中通过确定SFR是否大于阈值来继续进行。如果是的话,在处理元89中,可以将该存储装置从生产中移除(例如,以用于重新整修、销毁等)。否则,在处理元90中,存储装置可以被准备就绪以供递送客户。
[0029]尽管已经在附图和前述的说明中示例说明并描述了本发明,但是这些示例说明和描述被认为是示例性的,而不是限制性的。已经示出和说明了本发明的一个实施例以及一些变型。期望对所有落在本发明的精神内的改变和修改进行保护。本领域技术人员将理解源自上述实施例的各种变型其都落在本发明的范围内。因此,本发明并不限于上面讨论的具体示例和图示,而是仅由下面的权利要求及其等同物限定。