English:
[0002] Many modern electronic integrated circuits integrate essentially all necessary functional components of a computer system, whether general purpose or arranged for a particular end application. Those large scale integrated circuits that include the computational capability for controlling and managing a wide range of functions and useful applications are often referred to as "system on a chip", or "SoC", devices. Typical modern SoC architectures include one or more processor "cores" that perform the digital computer functions of retrieving executable instructions from memory, performing arithmetic and logical operations on digital data retrieved from memory, and storing the results of those operations in memory. Other digital, analog, mixed-signal, or even RF functions may also be integrated into the SoC for acquiring and outputting the data processed by the processor cores. In any case, considering the large amount of digital data often involved in performing the complex functions of these modern devices, significant solid-state memory capacity is now commonly implemented in these SoC devices.
[0003] To optimize performance, memory resources are typically distributed throughout the typical modern SoC device. These memory resources can include both volatile and non-volatile memory. This distributed memory architecture results in memory resources being physically and electrically (or logically) proximate to the processing function that will be accessing it, but may be physically and logically remote from other similar memory of the same type. For example, the deployment of local memory resources will minimize the traffic over the system bus, which reduces the likelihood of bus contention and undesirable latency, and also reduces access time and memory management overhead. The number of memory arrays implemented throughout a modern large-scale SoC devices can be quite large, numbering into the hundreds in some cases.
[0004] At the time of manufacture, a full test of the integrated circuits' functionality and performance is important, especially because memory resources can occupy much of the chip area of a typical modern SoC. Conventional memory test algorithms can be quite time-consuming, particularly those involving test patterns of order O(nx) where x is greater than one, and as such the test time and test cost involved can be dominated by memory test. The distribution of embedded memory resources throughout typical SoC devices further complicates the task of memory test, as many memory arrays are not directly accessible to external automated test equipment yet must still be tested.
[0005] SoC devices typically include internal test circuitry ("built-in self-test," or "BIST," circuitry) that executes a self-test operation for the device upon power-up or reset. BIST may also be involved in the testing of memory, both at the time of manufacture and also on power-up. Conventional BIST memory test techniques can include the placement of hardwired logic in the SoC, for implementing memory test algorithms developed at the time of circuit design. However, at that early stage of the process, a determination of the particular tests to be performed may not be feasible. Another conventional BIST approach is to use the central processing unit of the SoC itself to perform the memory test. But this approach can be limited, because not all embedded memory arrays in the device may be visible to the CPU, and are thus not testable by the CPU. Direct memory access (DMA) techniques for providing external access to embedded memories are also known, but typically are unable to access the memory at its full operating speed.
[0006] Because of these limitations, programmable BIST ("pBIST") techniques have been developed to test embedded memories in the SoC context. U.S. Patent No. 7,324,392 and U.S. Patent Application Publication No. US 2014/0164856, both commonly assigned herewith and incorporated herein by reference, describe examples of these pBIST techniques for testing embedded memories in large-scale integrated circuits such as SoC devices. According to these approaches, the pBIST circuitry includes a general purpose test controller that is programmed by a set of instructions to produce test conditions for the various internal and embedded functions of the device, and to receive and log the responses of those functions to those test conditions. In the memory test context, these operations include the writing of the desired data pattern to an embedded memory, and then addressing the memory to retrieve and compare the stored data to the expected data. Typically, the BIST data path over which the data are communicated during memory test is a separate and independent data path from that by which the embedded memories are accessed in normal operation of the SoC.
[0007] Because of the high test time and test cost for testing the memory capacity of the SoC device, as discussed above, BIST techniques have been developed for the parallel testing of embedded memories, such that multiple memory arrays are simultaneously tested. According to one conventional approach, this parallel test is implemented by multiple BIST controllers that simultaneously execute a test of an associated embedded memory. The provision of multiple BIST controllers multiplies the chip area required for the BIST test logic and data paths, forcing a trade-off between chip area and test time.
[0008] Conventional pBIST architectures, such as described in the above-incorporated U.S. Patent No. 7,324,392, include a BIST controller that is shared by multiple memories of similar memory type (e.g., single-port, double-port). The shared BIST controller generates the test pattern to be written to the memories, and also the expected response from the memories when read. Each memory has a local comparator that compares the data read from its memory during the test with the expected data from the shared BIST controller, and forwards the results to the shared BIST controller. For the expected data from the shared BIST controller to align with the data read from the parallel embedded memories, this conventional arrangement includes a local response delay generator that aligns the expected data to account for access latency for that particular memory, and a local comparator that compares the delayed expected data with the data read from that particular memory and generates a pass/fail signature accordingly.
[0009] FIG 1 illustrates an example of the architecture of a BIST memory test data path in a conventional SoC, in which shared BIST controller 10 supports the parallel test of memories 15 in a manner such as described in the above-incorporated U.S. Patent No. 7,324,392. This test data path is separate and independent from the data path by which memories 15 are accessed in normal operation, which is not shown in FIG 1 for the sake of clarity. As shown in this example, BIST controller 10 communicates with each memory 15 through one or more pipeline delay stages 12, in combination with an instance of local response delay generator 14 that is dedicated to that embedded memory 15. BIST controller 10 may be one of multiple such BIST controllers within the SoC. In architectures such as this example, a given BIST controller 10 is typically associated with memories 15 that are of a common type (e.g., single-port, double-port), considering that BIST controller 10 generates the particular test data pattern to be applied to its associated memories 15; as such, if the SoC includes multiple memory types, multiple BIST controllers 10 and associated data paths may be present. The data pattern generated by BIST controller 10 is applied directly to memories 15, after passing through the pipeline delay stages 12, but these data are not delayed by local response delay generators 14.
[0010] In this arrangement, pipeline delays 12 and each local response delay generator 14 delay the expected data response communicated from BIST controller 10 before application to the instance of local comparator 16 with which that local response delay generator 14 is associated. Local comparator 16 compares that delayed expected data response with the data read from its associated memory 15 during the memory test, and generates a pass/fail signature based on the results of that comparison. In this example, the pass/fail signatures generated by comparators 16 are communicated back to BIST controller 10, such as by parallel test data comparator 17 function, which produces an overall pass/fail signature for those memories 15 that were tested in parallel.
[0011] In this conventional architecture, instances of pipeline delays 12 may be shared by embedded memories 15 that are generally in the vicinity of one another. For example, pipeline delay 120 is shared by all embedded memories 15 shown in FIG 1, while pipeline delay 121 is shared by embedded memories 15 of group 181 that are in the general vicinity of one another, and pipeline delay 122 is shared by embedded memories 15 in group 182 that are in the general vicinity of one another. Each of pipeline delays 12 essentially operate as one or more clocked buffer stages for the data communicated by BIST controller 10, such that a data word applied at the input of an instance of pipeline delay 12 will appear at its output after a delay of x clock cycles, where x is the number of buffer stages in that pipeline delay 12. Each local response delay generator 14 is similarly constructed, and operates to delay the expected data it receives by one or more clock cycles, in order to align it with the memory access latency of its associated embedded memory 15.
[0012] Although the pipeline architecture in this conventional arrangement is "physically aware" by sharing pipeline stages 12 based on the general physical proximity of embedded memories 15, dedicated local response delay generators 14 are still provided in this architecture. These dedicated local response delay generators 14 can each occupy significant chip area, especially in the case of very wide data words (e.g., up to 128 bit) that are now often required in many modern SoC devices. In some cases, particularly those in which the overall chip area of the SoC is constrained by packaging considerations and other constraints, the chip area consumed by these dedicated local response delay generators can be prohibitive, such that parallel memory test cannot be implemented.
[0013] In described examples, a BIST controller generates test data patterns to be applied to embedded memories through a BIST data path. Each embedded memory is coupled to a dedicated local comparator that compares data read from the memory during test with an expected data response forwarded from the BIST controller. The local comparators associated with a group of the memories to be tested in parallel receive the expected data response in parallel from a local response delay generator that is shared among the group.
[0014] FIG 1 is an electrical diagram, in block form, of a conventional built-in self-test (BIST) data path architecture for the parallel test of embedded memories in a system-on-a-chip (SoC).
[0016] FIG 3 is an electrical diagram, in block form, of the architecture of BIST circuitry and a BIST data path for the parallel test of embedded memories in the SoC of FIG 2, according to embodiments.
[0017] FIG 4 is an electrical diagram, in block form, of the construction of a shared local response delay generator in the architecture of FIG 3, according to embodiments.
[0018] Example embodiments provide a built-in self-test (BIST) architecture for the parallel test of distributed memories in a large-scale integrated circuit can be implemented with reduced chip area. In at least one example, such embodiments provide such a BIST parallel memory test architecture that is suitable for implementation in system-on-a-chip (SoC) devices. Also, example embodiments provide such a BIST parallel memory test architecture that enables parallel test of embedded memories at full operating speed.
[0019] The embodiments described in this specification are implemented into a large-scale integrated circuit device including a number of computing and other operational functions, such as those integrated circuits commonly referred to as a "system-on-a-chip" or "SoC", because such implementation is particularly advantageous in that context. However, example embodiments may be beneficially applied to in other applications, such as any type of integrated circuit in which a number of memory arrays are embedded at various locations within the device.
[0020] FIG 2 illustrates, in block diagram form, the generalized architecture of SoC 400 constructed according to these embodiments. In this example, programmable logic serving as the central processing unit (CPU) of SoC 400 is provided by CPU 430 (e.g., microprocessor), such as an OMAP processor available from Texas Instruments Incorporated. SoC 400 may be constructed to include multiple CPUs 430, which may be of the same type as one another or which may be processors of other types such as generic programmable processors, digital signal processors (DSPs) or other application-specific or customized logic, including fixed sequence generators, as appropriate for the particular function of SoC 400.
[0021] Memory resources in SoC 400 are provided by non-volatile flash memory 410, read-only memory (ROM) 411, and random access memory 412, a portion of each of which is accessible to CPU 430 through address bus MAB and data bus MDB. The flash memory 410, ROM 411 and RAM 412 are shown in FIG 2 as unitary blocks, but these memory resources may alternatively be implemented as multiple memory blocks or arrays. Particularly in the case of RAM 412, these memory instances may be implemented by any one or more of a number of memory cell types and arrangements, including static RAM (SRAM), dynamic RAM (DRAM), and ferroelectric memory (FRAM). Also, for the case of RAM 412, individual instances of memory resources may have any one of a number of access architectures, including single-port and double-port access types.
[0022] Various peripheral functions may be also coupled to buses MAB, MDB, in order to be accessible to CPU 430 and one another. In the architecture of FIG 2, these peripherals include various signal processing functions, such as analog-to-digital (ADC) and digital-to-analog (DAC) converters, communications ports, timers, a "brownout" protection function, and serial and other interface functions. These various peripheral functions may be within the address space of SoC 400, as suggested by their accessibility via buses MAB, MDB; alternatively, one or more of these or other functions may be accessible to CPU 430 directly or via other functional circuitry. Security features may also be implemented within SoC 400, such as by secure state machine 448 in combination with stored security parameters in secure flash memory 440 and secure tag hardware 446, in order to execute features such as preventing data reads or writes to areas of memory that are specified to be secure areas unless a secure mode is enabled. SoC 400 also includes other functions, such as its clock system, emulation system 420 and JTAG interface 421 for debug and emulation.
[0023] SoC 400 may include additional or alternative functions to those shown in FIG 2, or may have its functions arranged according to a different architecture from that shown in FIG 1.
[0024] In addition to the various memory resources 410, 411, 412 that are accessible via address bus MAB and data bus MDB, many of the circuit functions within SoC 400 may themselves include local memory resources that are not directly accessible to CPU 430. For example, digital functions, such as the various interfaces, state machines (e.g., SM 448) and timers, can include blocks of RAM for data storage, or even flash memory or ROM for storage of configuration data or program instructions. Especially for those functions that operate largely in the digital domain, these memory resources may collectively, if not individually, occupy significant chip area in SoC 400. As mentioned above, functional testing of these memory resources is important, even though they may not be directly accessible to CPU 430 via buses MAB, MDB or otherwise. CPU 430 itself may also include local memory resources, such as one or more levels of cache memory.
[0025] More generally, the various memory resources and other functions in the architecture of SoC 400 may not be physically implemented in the arrangement shown in FIG 2, but may instead be placed at various locations within the integrated circuit. In this regard, those memory resources and other functions may in fact be physically (and logically, for that matter) distributed as multiple instances of SoC 400.
[0026] According to these embodiments, SoC 400 includes built-in self-test (BIST) circuitry 450, which controls the execution of self-test program routines for SoC 400. BIST 450 may have an external interface to receive commands from automated test equipment (not shown), and to communicate test results in response. Additionally or alternatively, BIST 450 may perform a self-test function upon power-up of SoC 400. In any case, according to these embodiments, BIST 450 is coupled to memory resources 410, 411, 412, and other functions of SoC 400 that include local memory, including CPU 430 in this example. As shown in FIG 2, BIST 450 is coupled to these other memories and functions through BIST data path BIST DP. Data path BIST DP is separate and independent of buses MAB, MDB, and as such is able to directly access local memory arrays and other local functions that may not be accessible to CPU 430 over the data path of buses MAB, MDB, through which data are communicated during the normal operation of SoC 400. Also, as described in further detail below, BIST data path BIST DP includes: conductors arranged as data and control buses; and various circuit functions as will be used in the BIST of the memory resources of SoC 400.
[0027] Referring to FIG 3, the architecture of a portion of BIST circuitry 450 and its associated BIST data path BIST DP according to an embodiment will now be described. The portion of the BIST functionality of SoC 400 shown in FIG 3 performs the parallel test of several memories 45 of the same memory type, such as single-port SRAM. The BIST architecture involved with the testing of other memory types such as double-port memory and non-volatile memory may be similarly constructed. This constraining of parallel test to groups of embedded memories of the same type enables the test data patterns and address patterns for those memories to be simultaneously generated; the test patterns for different memory types will generally differ by type. In the architecture of FIG 3 according to this embodiment, BIST controller 40 is implemented within BIST 450, and is constructed of logic circuitry for generating the desired test data pattern and address sequences that are to be applied, in parallel, to its associated memories 45 in carrying out the test. Multiple BIST controllers 40 may be provided within BIST 450, to similarly control the parallel test of other groups of memories 45, such as those of different memory type or architecture. Alternatively or additionally, multiple BIST controllers 40 for the same memory type may be provided, if desired.
[0028] In this example, the test data pattern generated by BIST controller 40 is in the form of a sequence of parallel data words of a width corresponding to the widest data word width among the embedded memories 45 with which this BIST controller 40 is associated. As mentioned above, in modern SoC devices, memories can support a data word of up to 128 bits, if not wider. Bit-wise "masks" may be applied downstream in BIST data path BIST DP as appropriate for the testing of embedded memories 45 of smaller data word widths. This test data pattern is communicated by BIST controller to its memories 45 through one or more pipeline delay stages 42 within BIST data path BIST DP. As in the conventional arrangement described above, each pipeline delay stage 42 according to this embodiment may be constructed as one or more clocked buffer stages, to delay the propagation of a test data word at its input for one or more system clock cycles (i.e., the number of buffer stages in that pipeline delay stage 42). The delay inserted by a pipeline delay stage 42 will usually correspond to the delay of one or more pipeline stages in the execution flow of SoC 400.
[0029] In this embodiment, similarly as in the conventional architecture of FIG 1, pipeline delay stages 42 may be shared by those embedded memories 45 that are in the general vicinity of one another and that are to be tested in parallel with one another. For the example of FIG 3, pipeline delay 420 is shared by all embedded memories 45, while pipeline delay 421 is shared by embedded memories 45 of group 481 that are in the general vicinity of one another, and pipeline delay 422 is shared by embedded memories 45 in group 482 that are in the general vicinity of one another. In this manner, the placement and use of pipeline delay stages 42 can be considered to be "physically aware". The total number of pipeline stages 42 that are in BIST data path BIST DP is selected so that the parallel memory test can be carried out at the full operating speed of embedded memories 45, in normal operation.
[0030] The output of the last of pipeline stages 42 in BIST data path BIST DP for a given group of embedded memories 45 is coupled to each of the memories in that group. For example, the output of pipeline delay stage 421 is coupled to embedded memories 45 in group 481.
[0031] According to this embodiment, a shared local delay response generator 44 is inserted into BIST data path BIST DP for each group 48 of embedded memories 45, at a point following the last of the pipeline delay stages 42 for that group. The output of this shared local delay response generator 44 is directly coupled to local comparators 46 associated with those embedded memories 45 in its group 48, with no additional dedicated delay response generators or other delay in BIST data path BIST DP between shared local delay response generator 44 and any of its associated local comparators 46. FIG 4 illustrates the functional arrangement of an example of shared local delay response generator 44j . In this generalized architecture, shared local delay response generator 44j includes m buffer stages B0 through Bm-1 (m > 1), each clocked by a clock signal such as system clock SYS CLK. As a result, expected data word EDR in, of a width of n bits, is delayed by a time corresponding to m cycles of system clock SYS CLK before appearing as expected data word EDR out, for application to its associated local comparators 46.
[0032] According to this embodiment, shared local delay response generator 44 provides the entirety of the local delay in the expected response data applied to local comparators 46 for the embedded memories 45 in the associated group. Conversely, this architecture has no additional local delay response generator that is dedicated to a particular embedded memory 45 within that group. As a result, shared local delay response generator 44 is shared by those embedded memories 45 in SoC 400 that have essentially the same latency as one another. This allows shared local delay response generator 44 to provide the same delay in the expected data response for each memory 45 in that group 48; accordingly, the expected data response is applied by shared local delay response generator 44 simultaneously to each of the local comparators 46 in that group 48. In a general sense, the latency time of these memories 45 includes such factors as the operational timing (e.g., read access time) of those memories 45, and other local delays such as those corresponding to the physical length of the data path to those memories 45. In operation, the delay in the expected data response inserted by shared local delay response generator 44 ensures that the expected data response is applied to local comparators 46 at the correct time for those local comparators 46 to compare the output of their associated embedded memories 45 with the corresponding expected response, in parallel with one another. Each local comparator 46 generates a pass/fail signature from the results of these comparisons in the memory test algorithm, and forwards that pass/fail signature to parallel test data comparator 47, which combines the results from local comparators 46 into data for return to BIST controller 40 for this memory type.
[0033] As evident from FIG 3, multiple groups 481, 482 of embedded memories 45 that are associated with this instance of BIST controller 40 can be tested either sequentially relative to one another, or in parallel with one another. In this example, shared local delay response generator 442 for embedded memories 45 in group 482 can insert a different delay into the expected data response for its local comparators 46 than that inserted by local delay response generator 441 for group 481. In some cases, the inserted delay by these local delay response generators 44 may be the same delay, but the physical distance between the groups 481, 482 may be such that a single shared local delay response generator 44 would not work.
[0034] The sharing of a single local delay response generator 44 among multiple embedded memories 45 according to this embodiment significantly reduces the chip area required to implement parallel memory test in this BIST context. As discussed above, the area required to implement dedicated local delay response generators for each embedded memory can be significant, especially for wide data words. However, in this embodiment, this chip area is reduced by the number of embedded memories 45 that can share an instance of shared local delay response generator 44. This area savings is especially significant in those devices in which the memory data path is extremely wide, such as on the order of 128 bits or more. For example, one modern SoC device includes as many as twelve instances of 128 bit wide memory that can share a single local delay response generator, resulting in an area reduction of nearly 60% for the memory data path in that device as compared with the conventional BIST architecture with dedicated delay response generators for each memory, such as discussed above relative to FIG 1.
[0035] These embodiments thus enable the efficient implementation of parallel memory test within a BIST framework in very large-scale integrated circuits such as SoC devices, even where many embedded memory arrays and functions are widely distributed throughout the device. The reduction of chip area provided by these embodiments permit this parallel memory test, even in devices for which the chip area are severely constrained, such as due to packaging requirements. Parallel testability, even of deeply embedded memories (i.e., not directly accessible to the CPU of the device), is thus provided in a cost-effective manner. Also, these embodiments permit the parallel memory test to be performed at the full operating speed of the memories, ensuring a thorough and complete test of embedded memories.
[0036] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

中文:
[0002]不管通用还是针对特定端应用程序布置,许多现代电子集成电路基本上都集成了计算机系统的所有必需的功能组件。包含用于控制并管理广泛范围的功能和有用的应用程序的计算能力的那些大规模集成电路常常被称作“芯片上系统(system on a chip)”或“SoC”装置。典型的现代SoC架构包含执行以下数字计算机功能的一或多个处理器“核心”:从存储器检索可执行指令、对从存储器检索的数字数据执行算术和逻辑运算、和存储那些运算的结果。其它数字、模拟、混合信号或甚至RF功能也可集成到SoC中来获取并输出由处理器核心处理的数据。在任何状况下,考虑到大量数字数据常常涉及执行这些现代装置的复杂功能,在这些SoC装置中现通常实施相当大的固态存储器容量。
[0003]为了优化性能,存储器资源通常分布在整个典型的现代SoC装置中。这些存储器资源可包含易失性存储器和非易失性存储器两者。此分布式存储器架构致使存储器资源物理上且电气地(或逻辑地)接近于将存取存储器架构的处理功能,但可物理上且逻辑地远离同一类型的其它类似存储器。举例来说,展开本地存储器资源将最小化系统总线上的业务,这会降低总线争用和不期望时延的可能性,并还减少存取时间并降低存储器管理开销。在整个现代大规模SoC装置中实施的存储器阵列的数目可以是相当大的,在一些状况下数目达到数百个。
[0004]在制造时,对集成电路的功能性和性能的完全测试是重要的,这尤其是因为存储器资源会占据典型现代SoC的相当大的芯片面积。常规存储器测试算法会是相当耗时的,涉及数量级O(nx)的测试样式的存储器测试算法尤其如此,其中x大于一,且因而可通过存储器测试控制所涉及测试时间和测试成本。在整个典型SoC装置中分布嵌入式存储器资源进一步使存储器测试的任务复杂,这是因为许多存储器阵列不可由外部自动化测试设备直接存取但又仍必须经受测试。
[0005]SoC装置通常包含在加电或重设之后即刻为装置执行自测试操作的内部测试电路系统(“内置自测试(built-in self-test)”或“BIST”电路系统)。BIST还可涉及在制造时以及在加电时测试存储器。常规BIST存储器测试技术可包含在SoC中放置固线式逻辑,来实施在电路设计时开发的存储器测试算法。但是,在所述过程的早期阶段,确定待执行的特定测试可能并不可行。另一常规BIST方法是使用SoC自身的中央处理单元以执行存储器测试。但此方法可能是受限制的,这是因为装置中的并非所有嵌入式存储器阵列可对CPU可见,并因此不可由CPU测试。用于提供对嵌入式存储器的外部存取的直接存储器存取(directmemory access,DMA)技术也已知,但通常不能够按其完全操作速度存取存储器。
[0006]由于这些限制,已开发出可编程BIST(“programmable BIST,pBIST”)技术来在SoC情境中测试嵌入式存储器。彼此一起共同转让且以引用的方式并入本文中的第7,324,392号美国专利和第US 2014/0164856号美国专利申请公开描述了用于测试例如SoC装置等大规模集成电路中的嵌入式存储器的这些pBIST技术的实例。根据这些方法,pBIST电路系统包含通用测试控制器,通用测试控制器由一组指令编程以产生用于装置的各种内部和嵌入式功能的测试条件,并接收并记录那些功能对那些测试条件的响应。在存储器测试情境中,这些操作包含将期望数据样式写入到嵌入式存储器,并接着对存储器进行寻址以检索并比较所存储数据与预期数据。通常,在存储器测试期间在其上方传达数据的BIST数据路径是与有助于在SoC的正常操作中存取嵌入式存储器的数据路径分离且非相依的数据路径。
[0007]由于用于测试SoC装置的存储器容量的高测试时间和测试成本,如上文所论述,已开发出用于嵌入式存储器的并行测试的BIST技术,使得同时测试多个存储器阵列。根据一个常规方法,此并行测试由同时执行相关联嵌入式存储器的测试的多个BIST控制器实施。供应多个BIST控制器会使对于BIST测试逻辑和数据路径所需的芯片面积倍增,从而迫使在芯片面积与测试时间之间作出取舍。
[0008]描述于例如上文并入的第7,324,392号美国专利中的常规pBIST架构包含BIST控制器,BIST控制器由类似存储器类型(例如单端口、双端口)的多个存储器共享。共享BIST控制器产生待写入到存储器的测试样式,并还在被读取时从存储器产生期望响应。每个存储器具有本地比较器,本地比较器比较在测试期间从其存储器读取的数据与来自共享BIST控制器的预期数据,并将结果转发到共享BIST控制器。为了使来自共享BIST控制器的预期数据与从并行嵌入式存储器读取的数据对准,此常规布置包含本地响应延迟产生器和本地比较器,本地响应延迟产生器对准预期数据以考虑那个特定存储器的存取时延,本地比较器比较延迟预期数据与从那个特定存储器读取的数据并相应地产生通过/失败签名。
[0009]图1说明常规SoC中的BIST存储器测试数据路径的架构的实例,其中共享的BIST控制器10支持对存储器15的并行测试,其方式例如描述于上文并入的第7,324,392号美国专利中。此测试数据路径分离于且独立于有助于在正常操作中存取存储器15的数据路径,为清楚起见在图1中未展示此测试数据路径。如本实例中所展示,结合专用于每个存储器15的本地响应延迟产生器14的个例,BIST控制器10通过一或多个管线延迟级12与那个嵌入式存储器15通信。BIST控制器10可以是SoC内的多个此类BIST控制器中的一个。在例如本实例等架构中,考虑到给定BIST控制器10产生待应用于其相关联存储器15的特定测试数据样式,BIST控制器10通常与属于共同类型(例如单端口、双端口)的存储器15相关联;因而,如果SoC包含多种存储器类型,那么可存在多个BIST控制器10和相关联数据路径。在通过管线延迟级12之后,由BIST控制器10产生的数据样式直接应用于存储器15,但这些数据并未由本地响应延迟产生器14延迟。
[0010]在此布置中,管线延迟12和每个本地响应延迟产生器14在将其应用于与那个本地响应延迟产生器14相关联的本地比较器16的个例之前使从BIST控制器10传达的预期数据响应延迟。本地比较器16比较那个延迟预期数据响应与在存储器测试期间从其相关联存储器15读取的数据,并基于那个比较的结果而产生通过/失败签名。在此实例中,由比较器16产生的通过/失败签名例如通过并行测试数据比较器17功能被传达回到BIST控制器10,并行测试数据比较器17功能用于被并行地测试的那些存储器15产生总体通过/失败签名。
[0011]在此常规架构中,管线延迟12的个例可由彼此大体上接近的嵌入式存储器15共享。举例来说,管线延迟120由图1中展示的所有嵌入式存储器15共享,而管线延迟121由群组181中的彼此大体上接近的嵌入式存储器15共享,且管线122由群组182中的彼此大体上接近的嵌入式存储器15共享。管线延迟12中的每一个基本上操作为用于由BIST控制器10传达的数据的一或多个时控缓冲器级,使得在管线延迟12的个例的输入处应用的数据字将在x个时钟周期的延迟之后在其输出处出现,其中x是那个管线延迟12中的缓冲器级的数目。每个本地响应延迟产生器14类似地建构,并操作以使其按一或多个时钟周期接收的预期数据延迟,以便使预期数据与其相关联嵌入式存储器15的存储器存取时延对准。
[0012]虽然此常规布置中的管线架构通过基于嵌入式存储器15的一般物理接近度而共享管线级12来“物理上感知”,但是专用本地响应延迟产生器14仍设置于此架构中。这些专用本地响应延迟产生器14可各自占据相当大的芯片面积,在极宽数据字(例如高达128位)的状况下尤其如此,而在许多现代SoC装置中现常常需要极宽数据字。在一些状况下,具体地说,在SoC的总体芯片面积由封装考量和其它约束约束的状况下,由这些专用本地响应延迟产生器消耗的芯片面积会过高,使得无法实施并行存储器测试。
[0013]在所描述实例中,BIST控制器通过BIST数据路径产生待应用于嵌入式存储器的测试数据样式。每个嵌入式存储器耦合到专用本地比较器,专用本地比较器比较在测试期间从所述存储器读取的数据与从所述BIST控制器转发的预期数据响应。与一组待并行测试的存储器相关联的本地比较器从所述组当中共享的所述本地响应延迟产生器并行地接收所述预期数据响应。
[0014]图1是用于芯片上系统(SoC)中的嵌入式存储器的并行测试的常规内置自测试(BIST)数据路径架构的呈框形式的电气图。
[0016]图3根据实施例的用于图2的SoC中的嵌入式存储器的并行测试的BIST电路系统和BIST数据路径的架构的呈框形式的电气图。
[0017]图4是根据实施例的图3的架构中的共享本地响应延迟产生器的构造的呈框形式的电气图。
[0018]实例实施例提供用于大规模集成电路中的分布式存储器的并行测试的内置自测试(BIST)架构,BIST架构可以减小的芯片面积予以实施。在至少一个实例中,此类实施例提供适合于在芯片上系统(SoC)装置中实施的此BIST并行存储器测试架构。而且,实例实施例提供使得能够按完全操作速度进行嵌入式存储器的并行测试的此BIST并行存储器测试架构。
[0019]本说明书中描述的实施例实施成包含数个计算和其它操作功能的大规模集成电路装置,例如通常被称为“芯片上系统”或“SoC”的那些集成电路,这是因为此类实施方案在那种情境中特别有利。但是,实例实施例可有利地应用于其它应用,例如其中数个存储器阵列嵌入于装置内的各位置处的任何类型的集成电路。
[0020]图2以框图形式说明根据这些实施例建构的SoC 400的通用架构。在此实例中,充当SoC 400的中央处理单元(central processing unit,CPU)的可编程逻辑由CPU 430(例如微处理器)提供,例如可购自德州仪器(Texas Instruments)有限公司的OMAP处理器。SoC400可建构成包含多个CPU 430,CPU 430可彼此属于同一类型,或可以是其它类型的处理器,例如一般可编程处理器、数字信号处理器(digital signal processor,DSP)或其它专用或自定义逻辑,包含固定序列产生器、如对于SoC 400的特定功能适用。
[0021]SoC 400中的存储器资源由非易失性快闪存储器410、只读存储器(read-onlymemory,ROM)411和随机存取存储器412提供,CPU 430可通过地址总线MAB和数据总线MDB存取以上各项中的每一个的部分。快闪存储器410、ROM 411和RAM 412在图2中展示为单式块,但这些存储器资源可替代地实施为多个存储器块或阵列。具体地说,在RAM 412的状况下,这些存储器个例可由数个存储器单元类型和布置中的任何一个或多个实施,包含静态RAM(static RAM,SRAM)、动态RAM(dynamic RAM,DRAM)和铁电存储器(ferroelectric memory,FRAM)。而且,对于RAM 412的状况,存储器资源的个别个例可具有数个存取架构中的任一个,包含单端口和双端口存取类型。
[0022]各种外围功能也可耦合到总线MAB、MDB,以便对于CPU 430和彼此可存取。在图2的架构中,这些外围装置包含各种信号处理功能,例如模数转换器(analog-to-digital,ADC)和数模转换器(digital-to-analog,DAC)、通信端口、定时器、“电压过低”保护功能、以及串行和其它接口功能。这些各种外围功能可位于SoC 400的地址空间内,如由其通过总线MAB、MDB的可存取性暗示;替代地,这些或其它功能中的一或多个可直接或通过其它功能电路系统对于CPU 430可存取。例如通过安全状态机448结合安全快闪存储器440和安全标签硬件446中的所存储安全参数,还可在SoC 400内实施安全性特征,以便执行各种特征,例如在未启用安全模式的情况下防止数据读取或写入到指定为安全区域的存储器区域。SoC 400还包含其它功能,例如其时钟系统、仿真系统420、以及用于调试和仿真的JTAG接口421。
[0023]SoC 400可包含图2中展示的那些功能的额外或替代性功能,或可根据与图1中展示的架构不同的架构而布置其功能。
[0024]除了可通过地址总线MAB和数据总线MDB存取的各种存储器资源410、411、412以外,SoC 400内的许多电路功能本身还可包含并非对于CPU 430可直接存取的本地存储器资源。举例来说,数字功能,例如各种接口、状态机(例如SM 448)和定时器,可包含用于数据存储的RAM或甚至用于存储配置数据或程序指令的快闪存储器或ROM的块。尤其对于主要在数字域中操作的那些功能,如果不个别地,那么这些存储器资源可共同地在SoC 400中占据相当大的芯片面积。如上文所提及,这些存储器资源的功能测试是重要的,即使CPU 430不可通过总线MAB、MDB或以其它方式直接存取这些存储器资源的情况下也是如此。CPU 430自身还可包含本地存储器资源,例如一或多级高速缓存存储器。
[0025]更一般来说,SoC 400的架构中的各种存储器资源和其它功能可不在物理上实施于图2中展示的布置中,而是可替代地放置于集成电路内的各位置处。在这点上,那些存储器资源和其它功能可实际上在物理上(且在那点来说,在逻辑上)分布为SoC 400的多个个例。
[0026]根据这些实施例,SoC 400包含内置自测试(BIST)电路系统450,BIST电路系统450针对SoC 400控制对自测试程序例程的执行。BIST 450可具有外部接口以从自动化测试设备(未展示)接收命令并作为响应而传达测试结果。另外或替代地,BIST 450可在SoC 400的加电之后即刻执行自测试功能。在任何状况下,根据这些实施例,BIST 450耦合到存储器资源410、411、412和SoC 400的包含本地存储器的其它功能,本地存储器在此实例中包含CPU430。如图2中所展示,BIST 450耦合到这些其它存储器,并通过BIST数据路径BIST_DP起作用。数据路径BIST_DP分离于且独立于总线MAB、MDB,并因而能够直接存取本地存储器阵列和CPU 430不可通过总线MAB、MDB的数据路径存取的其它本地功能,在SoC 400的正常操作期间通过所述数据路径传达数据。而且,如在下文进一步详细描述,BIST数据路径BIST_DP包含:布置为数据和控制总线的导体;以及如将用于SoC 400的存储器资源的BIST中的各种电路功能。
[0027]参考图3,现将描述根据实施例的BIST电路系统450的部分和其相关联BIST数据路径BIST_DP的架构。图3中展示的SoC 400的BIST功能性的部分执行同一存储器类型的若干存储器45的并行测试,存储器类型例如单端口SRAM。可以类似方式建构参与例如双端口存储器和非易失性存储器等其它存储器类型的测试的BIST架构。并行测试对同一类型的嵌入式存储器的群组的此约束使得能够同时产生那些存储器的测试数据样式和地址样式;不同存储器类型的测试样式将大体上类型相异。在根据此实施例的图3的架构中,BIST控制器40实施于BIST 450内,并由用于执行以下操作的逻辑电路构成:在执行测试的过程中产生待并行地应用于其相关联存储器45的期望测试数据样式和地址序列。多个BIST控制器40可设置于BIST 450内,以类似地控制其它组存储器45的并行测试,例如属于不同存储器类型或具有不同架构的存储器。替代地或另外,必要时,可提供相同存储器类型的多个BIST控制器40。
[0028]在此实例中,由BIST控制器40产生的测试数据样式呈并行数据字的序列的形式,并行数据字的宽度对应于与此BIST控制器40相关联的嵌入式存储器45当中的最宽数据字宽度。如上文所提及,在现代SoC装置中,除非数据字更宽,否则存储器可支持高达128位的数据字。逐位“掩码”可在适当时应用于BIST数据路径BIST_DP下游中,以测试具有更小数据字宽度的嵌入式存储器45。此测试数据样式由BIST控制器通过BIST数据路径BIST_DP内的一或多个管线延迟级42传达给其存储器45。如同上文所描述的常规布置,根据此实施例的每个管线延迟级42可建构为一或多个时控缓冲器级,以在一或多个系统时钟周期内(即,那个管线延迟级42中的缓冲器级的数目)使测试数据字在其输入处的传播延迟。由管线延迟级42插入的延迟将通常对应于SoC 400的执行流程中的一或多个管线级的延迟。
[0029]在此实施例中,类似地如同图1的常规架构,管线延迟级42可由彼此大体上接近且将彼此并行地测试的那些嵌入式存储器45共享对于图3的实例,管线延迟420由所有嵌入式存储器45共享,而管线延迟421由群组481中的彼此大体上接近的嵌入式存储器45共享,且管线422由群组482中的彼此大体上接近的嵌入式存储器45共享。以此方式,对管线延迟级42的放置和使用可被认为是“物理上感知”的。选择BIST数据路径BIST_DP中的管线级42总数目,以使得在正常操作中,可按嵌入式存储器45的完全操作速度执行并行存储器测试。
[0030]嵌入式存储器45的给定群组的BIST数据路径BIST_DP中的管线级42中的最后一个的输出耦合到那个群组中的存储器中的每一个。举例来说,管线延迟级421的输出耦合到群组481中的嵌入式存储器45。
[0031]根据此实施例,在嵌入式存储器45的每个群组48的管线延迟级42中的最后一个之后的点处,共享本地延迟响应产生器44插入到那个群组的BIST数据路径BIST_DP中。此共享本地延迟响应产生器44的输出直接耦合到与其群组48中的那些嵌入式存储器45相关联的本地比较器46,而没有额外的专用延迟响应产生器,或在共享本地延迟响应产生器44与其相关联本地比较器46中的任一个之间的BIST数据路径BIST_DP中没有其它延迟。图4说明共享本地延迟响应产生器44j的实例的功能布置。在此通用架构中,共享本地延迟响应产生器44j包含m个缓冲器级B0到Bm-1(m≥1),每个缓冲器级由例如系统时钟SYS_CLK等时钟信号时控。因此,在显现为预期数据字EDR_out之前,n个位的宽度的预期数据字EDR_in按对应于系统时钟SYS_CLK的m个周期的时间延迟,以应用于其相关联本地比较器46。
[0032]根据此实施例,共享本地延迟响应产生器44在应用于相关联群组中的嵌入式存储器45的本地比较器46中的期望响应数据提供全部本地延迟。相反地,此架构不具有专用于那个群组内的特定嵌入式存储器45的额外本地延迟响应产生器。因此,共享本地延迟响应产生器44由SoC 400中的彼此具有基本上相同时延的那些嵌入式存储器45共享。这允许共享本地延迟响应产生器44在那个群组48中的每个存储器45的预期数据响应中提供相同延迟;相应地,预期数据响应由共享本地延迟响应产生器44同时应用于那个群组48中的本地比较器46中的每一个。在广义上,这些存储器45的时延时间包含各种因素,例如那些存储器45的操作定时(例如读存取时间),和其它本地延迟,例如对应于到那些存储器45的数据路径的物理长度的本地延迟。在操作中,由共享本地延迟响应产生器44插入的预期数据响应中的延迟确保预期数据响应那些本地比较器46的正确时间在处应用于本地比较器46,以彼此并行地比较其相关联嵌入式存储器45的输出与对应期望响应。每个本地比较器46在存储器测试算法中从这些比较的结果产生通过/失败签名,并将那个通过/失败签名转发到并行测试数据比较器47,并行测试数据比较器47将来自本地比较器46的结果组合成用于返回到此存储器类型的BIST控制器40的数据。
[0033]如从图3显而易见,可相对于彼此依序或彼此并行地测试与BIST控制器40的此个例相关联的多组481、482嵌入式存储器45。在此实例中,群组482中的嵌入式存储器45的共享本地延迟响应产生器442可将不同延迟插入到其本地比较器46的预期数据响应中,所述延迟不同于由群组481的本地延迟响应产生器441插入的延迟。在一些状况下,由这些本地延迟响应产生器44插入的延迟可以是相同延迟,但群组481、482之间的物理距离可以是使得单个共享本地延迟响应产生器44将无法工作。
[0034]在根据此实施例的多个嵌入式存储器45当中共享单个本地延迟响应产生器44显著地减小在此BIST情境中实施并行存储器测试所需的芯片面积。如上文所论述,实施每个嵌入式存储器的专用本地延迟响应产生器所需的面积可以是相当大的,对于宽数据字尤其如此。但是,在此实施例中,此芯片面积以可共享共享本地延迟响应产生器44的个例的嵌入式存储器45的数目减小。此面积节约在存储器数据路径极其宽的那些装置中尤其显著,存储器数据路径宽度例如是约128位或更大。举例来说,一个现代SoC装置包含可共享单个本地延迟响应产生器的128位宽存储器的多达十二个个例,从而相比于具有例如上文关于图1所论述的每个存储器的专用延迟响应产生器的常规BIST架构,引起那个装置中的存储器数据路径的几乎60%的面积减小。
[0035]这些实施例因此使得能够在例如SoC装置等极大规模集成电路中的BIST框架内有效率地实施并行存储器测试,甚至在许多嵌入式存储器阵列和功能广泛地分布式在整个装置中时也是如此。减小由这些实施例提供的芯片面积准许此并行存储器测试,甚至在其芯片面积例如由于封装要求而严重受约束的装置中也是如此。因此以节约成本的方式提供了并行可测试性,甚至深入嵌入式存储器(即,对于装置的CPU不可直接存取)的并行可测试性。而且,这些实施例准许按存储器的完全操作速度执行并行存储器测试,从而确保对嵌入式存储器的彻底且完全的测试。
[0036]在所描述实施例中可能进行修改,且其它实施例在权利要求的范围内是可能的。