English:
[0001] Conventional polysilicon resistors in semiconductor processes can have a wide range of values for their temperature coefficient of resistance (TCR), from positive to negative, whereas diffused resistors in monocrystalline silicon typically have a positive TCR. For many device applications, resistors with small or zero TCR are desired. Examples of device applications wherein low or zero TCR resistors are often desirable include voltage dividers, amplifier gains and/or other devices wherein reference voltage is used. In the past, resistors with small or zero TCR have been fabricated using relatively expensive materials and/or with additional processing steps that add complexity to fabrication. In certain applications, controlled TCR is important, even if the TCR is nonzero.
[0002] The present disclosure sets forth a device in the form of a resistor, and a method for making the same, having a small or zero TCR without the use of relatively expensive materials and/or fabrication techniques. In one embodiment, an example resistor is fabricated alongside and/or in conjunction with other integrated circuit components on a wafer using fabrication steps and materials already used in fabrication of the other integrated circuit components on a given wafer. As such, aspects of the present disclosure provide for the fabrication of low or zero TCR resistors with virtually no additional cost or processing steps. Also disclosed is a method of lowering the TCR of a resistor, whether the TCR of the base resistor material has a positive or negative TCR.
[0003] Disclosed examples include a resistor comprising a semiconductor structure between the first and second ends. The resistor also includes first and second metal-semiconductor compound structures on the semiconductor structure proximate the first and second ends of the semiconductor structure, where the first and second metal-semiconductor compound structures are spaced apart from each other along the length dimension of the semiconductor structure. The resistor further includes at least one intermediate metal-semiconductor compound structure on a portion of the intermediate region of the semiconductor structure between the first and second ends, where the intermediate metal-semiconductor compound structure is spaced apart from the first and second metal-semiconductor compound structures on the semiconductor structure.
[0004] Another example resistor includes a resistor region of a semiconductor substrate. The resistor region has a length dimension with first and second ends spaced from one another and an intermediate region between the first and second ends. The resistor further includes an oxide structure formed on or in the semiconductor substrate surrounding the resistor region of the semiconductor substrate, as well as first and second metal-semiconductor compound structures on the first and second ends of the resistor region, where the first and second metal-semiconductor compound structures are spaced apart from each other along the length dimension of the resistor region. The resistor also includes at least one intermediate metal-semiconductor compound structure on a portion of the intermediate region of the resistor region between the first and second ends, where the intermediate metal -semi conductor compound structure is spaced apart from the first and second metal-semiconductor compound structures on the resistor region of the semiconductor substrate.
[0005] FIG. 1 is a top view of an example resistor according to an embodiment.
[0006] FIG. 2 is a cross-sectional view of the resistor taken along the line 2-2 in FIG. 1.
[0007] FIG. 3 is a flow diagram showing an example method of fabricating a resistor according to one embodiment.
[0008] FIG. 4 is a side elevation view of first and second resistors in a partially fabricated state including a polysilicon layer disposed on top of an insulating layer on a bulk semiconductor substrate.
[0009] FIG. 5 is a side elevation view of the first and second resistors of FIG. 4 in a partially fabricated state further including a silicide block layer disposed over the polysilicon layer.
[0010] FIG 6. is a side elevation view of the first and second resistors of FIG. 5 in a partially fabricated state further including a photoresist layer;
[0011] FIG. 7 is a side elevation view of the first and second resistors of FIG. 6, wherein the photoresist layer has been patterned.
[0012] FIG. 8 is a side elevation view of the first and second resistors of FIG. 7 in a partially fabricated state wherein the silicide block layer has been etched to expose the polysilicon of the first resistor and second resistor in specific regions using photoresist as an etch mask.
[0013] FIG. 9 is a side elevation view of the first and second resistors of FIG. 8 in a partially fabricated state wherein the photoresist layer has been removed.
[0014] FIG. 10 is a side elevation view of the first and second resistors of FIG. 9 in a partially fabricated state further including a metal layer deposited over the polysilicon and remaining silicide block layers.
[0015] FIG. 11 is a side elevation view of the first and second resistors of FIG. 10 in a partially fabricated state undergoing an annealing process to form silicide structures where the metal layer is in contact with the polysilicon layer.
[0016] FIG. 12 is a side elevation view of the first and second resistors of FIG. 11 in a partially fabricated state after silicide formation wherein excess metal has been removed.
[0017] FIG. 13 is a top view of another example resistor according to an embodiment.
[0018] FIG. 14 is a cross-sectional view of the resistor of FIG. 13 taken along the line 14-14 in FIG. 13.
[0019] In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. In the following discussion and in the claims, the terms "including", "includes", "having", "has", "with", or variants thereof are intended to be inclusive in a manner similar to the term "comprising", and thus should be interpreted to mean "including, but not limited to... " Also, the term "couple" or "couples" is intended to include indirect or direct electrical or mechanical connection or combinations thereof. For example, if a first device couples to or is coupled with a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via one or more intervening devices and connections.
[0020] Referring initially to FIGS. 1-2, an example resistor is illustrated and identified generally by reference numeral 110. The resistor 110 generally includes a semiconductor substrate 212, an insulating layer 214 such as an oxide or the like, and a polysilicon layer 116 formed on top of the insulating layer 214. First and second silicide structures 118 and 120 are disposed adjacent respective first and second ends 126 and 128 of the polysilicon layer 116. Electrical contacts 122 are situated on the respective first and second silicide structures 118 and 120 for connecting the resistor to other electrical components in subsequently formed upper metallization layers (not shown) in a conventional fashion. Interposed between the first and second silicide structures 118 and 120 on an intermediate portion 130 of the polysilicon layer 116 are a plurality of intermediate silicide structures 132. The intermediate structures 132 are separate from each other and from the first and second silicide structures 118 and 120. The first and last silicide structures 118 and 120 in certain examples are implanted, such as during a CMOS source/drain processing step to form a low-ohmic end resistance, shown as implant regions 140 in FIG. 2.
[0021] As illustrated in FIGS. 1 and 2, the intermediate silicide structures 132 extend generally across the width of the polysilicon layer 116 in a similar fashion to end portions 118 and 120. In the illustrated example, the intermediate silicide structures 132 are generally coextensive in width, although not a requirement of all possible embodiments. In some embodiments, the intermediate silicide structures 132 can extend partially across the polysilicon layer 112. In still other embodiments, the intermediate silicide structures 132 can be grouped closer to one or the other of the structures 118 and 120. Any number of intermediate silicide structures 132 can be provided depending on the material and/or desired TCR of the resistor 110. The length of the intermediate silicide structures 132 can be varied along the length of the structure and the segments do not need to be of the same length.
[0022] It should be appreciated that the example resistor 110 with intermediate silicide structures 132 has a lowered TCR compared to a conventional resistor having only first and second silicide structures at respective ends thereof. In regions of the polysilicon layer 116 between the intermediate silicide portions 132, current traveling between the first and second end silicide structures 118 and 120 is forced to leave the low-ohmic silicide and travel across the interface into the polysilicon layer 116. This is a tunneling process and is enhanced by higher temperature. Thus, the interface between the silicide structures and the polysilicon has a lower resistivity at higher temperatures (i.e., a negative TCR). The TCR of the polysilicon layer 116 and the silicide will remain at their respective baselines, but the interface resistance of the silicide to polysilicon has a negative TCR. By selecting the length and number of silicided and unsilicided intermediate segments between the first and second silicide structures 118 and 120, the resistance and TCR of the resistor 110 can be adjusted over a wide range of values. Thus, if the polysilicon resistor material 116 has a positive TCR to begin with, a resistor with zero or negative TCR can be created by tailoring the intermediate silicide structures in accordance with the present disclosure. In general, the provision of the intermediate silicide portions 132 operates to decrease the TCR of the resulting resistor structure 110.
[0023] It should also be appreciated that the example resistor 110 can be fabricated with little or no additional cost or processing time in any fabrication process that includes both a polysilicon deposition step and a silicidation step.
[0024] Turning to FIG. 3, an example method 300 for making a resistor in accordance with the present disclosure is illustrated and identified generally by reference numeral 300. Method 300 will also be described in connection with FIGS. 4-12, which illustrate the example resistor 110 with intermediate silicide portions 132 at successive intermediate stages of fabrication. A second resistor 410 that does not include intermediate silicide portions is also illustrated in successive intermediate stages of fabrication in FIGS. 4-12. As will be appreciated, both resistors 110 and 410 can be fabricated alongside each other in a common process if desired, such as method 300.
[0025] The method in FIG. 3 begins with process step 304, where an insulating layer is formed on a bulk semiconductor substrate. The bulk semiconductor substrate can be a silicon (Si) substrate, although aspects of the disclosure can be carried out in association with SOI wafers, epitaxial silicon layers formed over silicon wafers, and any other semiconductor body including III-V materials. The bulk semiconductor substrate can be a monocrystalline Si substrate, or an epitaxially grown Si layer on top of a single crystal Si substrate, for example. The bulk substrate can have an implant (e.g. well). The semiconductor material could also be another polysilicon layer if the process offers a double poly stack (e.g. double poly in analog or BiCMOS process). The insulating layer can be any suitable material such as an oxide or the like, including a gate oxide or field oxide. In one example, the insulating layer includes a thermally grown Si02oxide 516 or any other dielectric material formed by any suitable technique. Example insulating materials include one or more of Si02, SiON, high-k dielectrics, and stacks or combinations thereof, including but not limited to binary metal oxides including aluminum oxide (A1203), zirconium oxide (Zr02), hafnium oxide (Hf02), lanthanum oxide (La203), yttrium oxide (Y203), titanium oxide (Ti02), as well as their silicates and aluminates; metal oxynitrides including aluminum oxynitride (AION), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), lanthanum oxynitride (LaON), yttrium oxynitride (YON), as well as their silicates and aluminates such as ZrSiON, HfSiON, LaSiON, YSiON, etc.; and perovskite-type oxides including a titanate system material such as barium titanate, strontium titanate, barium strontium titanate (BST), lead titanate, lead zirconate titanate, lead lanthanum zirconate titanate, barium lanthanum titanate, barium zirconium titanate; a niobate or tantalate system material such as lead magnesium niobate, lithium niobate, lithium tantalate, potassium niobate, strontium aluminum tantalate and potassium tantalum niobate; a tungsten-bronze system material such as barium strontium niobate, lead barium niobate, barium titanium niobate; and bilayered perovskite system material such as strontium bismuth tantalate, bismuth titanate and others.
[0026] In process step 306, polysilicon is deposited on the oxide above the bulk semiconductor substrate and patterned by a process 402 to form silicon structures 116, as shown in FIG 4. The deposition and patterning of the polysilicon can be performed in a shared process with the patterning of polysilicon to form gate structures for NMOS and PMOS transistors (not shown), for example. Further, in some examples, the polysilicon 116 can be undoped, in-situ doped, or doped in a subsequent implant step. In one example, the polysilicon 116 is doped with p-type or n-type dopants. Doping of the polysilicon may be accomplished using any suitable technique within the scope of the disclosure, including direct implantation and/or diffusion. In one example, diffusion is employed wherein an implantation process provides p-type or n-type dopants to the polysilicon, thereby creating p-doped or n-doped polysilicon. An anneal process is then performed to diffuse the dopants in certain examples. Doping may also be performed in a shared process with the doping of, for example, gate structures of transistors being constructed elsewhere on the substrate 212.
[0028] In one example, the regions 140 are implanted as shown in FIG. 9, for example, using an implantation process (not shown) concurrently used to implant n and p type source/drain structures in transistors of the IC. For instance, the prospective end regions 116 and 118 can receive the source/drain implant if part of a CMOS process.
[0029] In process step 308, a silicide block 134 is applied over the polysilicon structures 116 and insulating layer 214, for example, using a deposition process 502 in FIG. 5. The silicide block 134 can be any suitable material for blocking the formation of silicide, and typical includes a combination of oxide and/or nitride.
[0030] In process step 310, a photoresist 612 is applied over the silicide block 134, as shown by a deposition process 602 in FIG. 6.
[0032] In process step 314, the silicide block layer 134 is etched to remove portions thereof not covered by the remaining photoresist 612, as shown by process 802 in FIG. 8. The silicide block layer 134 is removed from the polysilicon layer 116 and/or any other location not covered by the photoresist 612. This exposes the polysilicon layer 116 in areas to be silicided, while leaving regions of the polysilicon structures 116 blocked from silicide formation by silicide block layer 134. For resistor 110, the regions to be silicided include the prospective locations of the first and second silicide structures 118 and 120 and the plurality of intermediate structures 132 shown in FIGS. 1 and 2. For resistor 410, the regions to be silicided include first and second silicide structures 1118 and 1120 (see FIG. 12).
[0033] In process step 316, the remaining photoresist is removed, as shown by process 902 in FIG. 9 and appropriate surface cleans are done. In process step 318, a metal layer 1012 is deposited over the polysilicon structures 116 and remaining silicide block 134, using a deposition process 1002 in FIG. 10. The metal layer 1012 can be cobalt or nickel, for example, or any other metal suitable for silicide formation.
[0034] In process step 320, the assembly undergoes a silicidation step whereat silicide is formed at the interface of the polysilicon layer and the metal layer through an annealing process 1102 in FIG. 11. As will be appreciated, silicide is prevented from forming in the regions where the silicide block layer 134 exists. As such, resistor 110 includes silicide end structures 118 and 120, and a plurality of intermediate silicide structures 132 spaced from one another by the interleaved block structures 134. Resistor 410 includes only silicide end structures 1118 and 1120.
[0035] In process step 322, excess metal 1012 is removed, as shown by process 1202 in FIG. 12.
[0036] In the illustrated example, a further annealing step is performed at 322 to complete the silicide formation. An optional implant may be performed at this step to modulate the contact resistance of the silicide. Resistors 110 and 410 are now ready for contact formation and other back-end processing, at 324 in FIG. 3 which can include, for example, the formation of a top oxide layer and/or formation of contacts in the end silicide structures.
[0037] A further optional process step can include doping via implantation through the silicide structures 118, 120, 132 to modify the response of the interface resistance between the silicide and the polysilicon 212. This increases the doping level just at the metal semiconductor interface and can assist electron transport through the interface.
[0038] It should be appreciated that the silicide structures of the disclosed examples can be formed by any suitable silicide formation techniques. In one possible implementation, a nitride mask is formed and patterned to expose portions of the polysilicon, and cobalt or other suitable metal is deposited so as to contact the exposed portions of the polysilicon. The polysilicon and metal are then heated (e.g., 800-900° C) to react the polysilicon with the deposited metal to form the silicide structure, to a thickness of about several hundred angstroms in one possible implementation. In another possible implementation, the silicide structures are formed (e.g., Titanium Silicide TiSi2, or Tungsten Silicide WSix) by chemical vapor deposition (CVD) using monosilane or dichlorosilane with tungsten hexafluoride as source gases, followed by annealing at 800-900° C. to create conductive stoichiometric silicide structures. In another possible implementation, titanium or tungsten metal is sputter deposited onto the polysilicon and remaining silicide block and is then heated to a certain temperature (e.g., 800-900° C) to react the polysilicon with the deposited metal to form the silicide structures, preferably to a thickness of about several hundred angstroms. In materials not suitable for silicide formation such as III-V a metal stack using suitable metals such as Ti, Pt, Pd, W, Ni or Au may be used. Also, a chemical mechanical polishing (CMP) process may be performed to create a smooth surface appropriate for wafer bonding.
[0040] It should now be appreciated that resistor 110 can be fabricated using steps common to the fabrication of a resistor, such as resistor 410, that does not include the intermediate silicide portion through etching of the photoresist in additional regions to leave a pattern that blocks silicide formation in certain intermediate regions in addition to the end regions of the resistor. Additionally, or in the alternative, example resistor 110 can be fabricated alongside a transistor in shared process steps including polysilicon deposition and patterning, oxide formation, masking/etching, and silicidation steps. As such, the present disclosure sets forth a low or zero cost adding method of fabricating low or zero TCR resistors in fabrication processes that include at least a polysilicon deposition step and a silicidation step.
[0041] With reference to FIGS. 13 and 14, another example resistor in accordance with the present disclosure is illustrated and identified generally by reference numeral 1310. In this example, the resistor 1310 is formed in a bulk semiconductor substrate 1312, as opposed to the polysilicon resistor 110 of FIGS. 1 and 2. In general, resistor 1310 is formed in a process similar to the above-described method 300, with the exception that instead of depositing and patterning a polysilicon structure on a semiconductor substrate, a resistor region is isolated in the semiconductor substrate and then the silicide structures are formed directly on the isolated resistor region.
[0042] To this end, it will be appreciated that the resistor 1310 includes a resistor region 1314 of the semiconductor substrate 1312 that is isolated from the remainder of the semiconductor substrate 1312. The semiconductor substrate 1310 can be a silicon substrate, although aspects of the disclosure can be carried out in association with SOI wafers, epitaxial silicon layers formed over silicon wafers, and any other semiconductor body including III-V materials. The bulk semiconductor substrate can be plain Si substrate, or an epitaxially grown Si layer on top of a plain Si substrate, for example. The bulk substrate could have received an implant (e.g. well). The resistor region 1314 can be formed by, for example, an oxide structure 1316 surrounding the resistor region 1314 (e.g., LOCOS or shallow trench isolation (STI)), or by various other isolation techniques such as junction isolation. The resistor 1310 includes first and second silicide end structures 1318 and 1320, and a plurality of intermediate silicide structures 1332. The semiconductor material beneath the end structures 1318 and 1320 can be doped, as shown in regions 1340 in FIG. 14. In one example, the regions 1340 are doped during source/drain implant process steps used in making transistors (not shown) in the IC. It should be appreciated that the formation of the first and second silicide end structures 1318 and 1320, and plurality of intermediate silicide structures 1332 on the semiconductor substrate 1312 can be performed in the manner previously described in connection with the example of FIGS. 1-12, and the resistor structure 1310 can include interleaved remaining silicide block layer structures 1334 as shown in FIGS. 13 and 14.

中文:
[0001]半导体工艺中的常规多晶硅电阻器的电阻温度系数(TCR)可具有宽范围的值,从正到负,而单晶硅中的扩散电阻器通常具有正TCR。针对许多装置应用,需要具有小或零TCR的电阻器。通常需要低或零TCR电阻器的装置应用的实例包含分压器、放大器增益及/或其中使用参考电压的其它装置。在过去,使用相对昂贵材料及/或利用增加制造的复杂性的额外处理步骤来制造具有小或零TCR的电阻器。在某些应用中,即使TCR非零,受控TCR也很重要。
[0002]本发明阐述一种电阻器形式的装置及其制造方法,所述电阻器具有小的或零TCR而无需使用相对昂贵材料及/或制造技术。在一个实施例中,使用已经用于制造给定晶片上的其它集成电路组件的制造步骤及材料,在晶片上与其它集成电路组件一起及/或结合其它集成电路组件来制造实例电阻器。因而,本发明的方面在实际上没有额外的成本或处理步骤的情况下提供低或零TCR电阻器的制造。还揭示一种降低电阻器的TCR的方法,无论基本电阻器材料的TCR具有正TCR还是负TCR。
[0003]所揭示的实例包含电阻器,所述电阻器包括介于第一端与第二端之间的半导体结构。所述电阻器还包含在所述半导体结构上靠近所述半导体结构的所述第一及第二端的第一及第二金属-半导体化合物结构,其中所述第一及第二金属-半导体化合物结构沿所述半导体结构的所述长度维度彼此间隔开。所述电阻器进一步包含至少一个中间金属-半导体化合物结构,其在介于所述第一端与第二端之间的所述半导体结构的中间区的一部分上,其中所述中间金属-半导体化合物结构与所述半导体结构上的所述第一及第二金属-半导体化合物结构间隔开。
[0004]另一实例电阻器包含半导体衬底的电阻器区。所述电阻器区具有长度维度,其中第一及第二端彼此隔开且中间区介于所述第一端与第二端之间。所述电阻器进一步包含形成在所述半导体衬底上或中的环绕所述半导体衬底的电阻器区的氧化物结构,以及在所述电阻器区的所述第一及第二端上的第一及第二金属-半导体化合物结构,其中所述第一及第二金属-半导体化合物结构沿所述电阻器区的所述长度维度彼此间隔开。所述电阻器还包含至少一个中间金属-半导体化合物结构,其在介于所述第一端与第二端之间的所述电阻器区的中间区的一部分上,其中所述中间金属-半导体化合物结构与所述半导体衬底的所述电阻器区上的第一及第二金属-半导体化合物结构间隔开。
[0005]图1是根据实施例的实例电阻器的俯视图。
[0006]图2是沿图1中的线2-2截取的电阻器的横截面图。
[0007]图3是展示根据一个实施例的制造电阻器的实例方法的流程图。
[0008]图4是包含安置在体半导体衬底上的绝缘层顶部上的多晶硅层的处于部分制造状态的第一及第二电阻器的侧视图。
[0009]图5是进一步包含安置在多晶硅层上方的硅化物阻挡层的处于部分制造状态的图4的第一及第二电阻器的侧视图。
[0010]图6是进一步包含光致抗蚀剂层的处于部分制造状态的图5的第一及第二电阻器的侧视图;
[0011]图7是图6的第一及第二电阻器的侧视图,其中光致抗蚀剂层已被图案化。
[0012]图8是处于部分制造状态的图7的第一及第二电阻器的侧视图,其中硅化物阻挡层已使用光致抗蚀剂作为蚀刻掩模来被蚀刻以暴露特定区中的第一电阻器及第二电阻器的多晶硅。
[0013]图9是其中光致抗蚀剂已被去除的处于部分制造状态的图8的第一及第二电阻器的侧视图。
[0014]图10是进一步包含沉积在多晶硅及剩余硅化物阻挡层上方的金属层的处于部分制造状态的图9的第一及第二电阻器的侧视图。
[0015]图11是经历退火工艺以形成其中金属层与多晶硅层接触的硅化物结构的处于部分制造状态的图10的第一及第二电阻器的侧视图。
[0016]图12是在硅化物形成之后的处于部分制造状态的图11的第一及第二电阻器的侧视图,其中过量金属已被去除。
[0017]图13是根据实施例的另一实例电阻器的俯视图。
[0018]图14是沿图13中的线14-14截取的图13的电阻器的横截面图。
[0019]在图式中,相似参考数字始终指代相似元件,并且各种特征不一定按比例绘制。在以下论述及权利要求书中,术语“包含”、“具有”、“拥有”或其变体希望以与术语“包括”类似的方式为包容性的,且因此,应该解释为意指“包含但不限于...”。并且,术语“耦合(couple/couples)”希望包含间接或直接电或机械连接或其组合。举例来说,如果第一装置耦合到第二装置或与第二装置耦合,那么所述连接可通过直接电连接,或通过经由一或多个中介装置及连接的间接电连接。
[0020]首先参见图1到2,实例电阻器通常由参考数字110说明及识别。电阻器110通常包含半导体衬底212,例如氧化物或类似物的绝缘层214,以及形成在绝缘层214顶部的多晶硅层116。第一及第二硅化物结构118及120邻近多晶硅层116的相应第一及第二端126及128安置。电触点122位于相应第一及第二硅化物结构118及120上,以用于将电阻器连接到在随后以常规方式形成的上金属化层(未展示)中的其它电组件。在多晶硅层116的中间部分130上插入在第一化物结构118与第二硅化物结构120之间的是多个中间硅化物结构132。中间结构132彼此分离并且与第一及第二硅化物结构118及120分离。在某些实例中,第一及最后的硅化物结构118及120例如在CMOS源极/漏极处理步骤期间被植入以形成低欧姆端电阻,如图2中的植入区140所展示。
[0021]如图1及2中所说明,中间硅化物结构132以与端部分118及120类似的方式大体上跨越多晶硅层116的宽度延伸。在所说明实例中,中间硅化物结构132在宽度上通常是共同延伸的,但在所有可能的实施例中不是必需的。在一些实施例中,中间硅化物结构132可跨越多晶硅层112部分延伸。在其它实施例中,中间硅化物结构132可更接近结构118及120中的一者或另一者来分组。可取决于电阻器110的材料及/或期望TCR来提供任何数目的中间硅化物结构132。中间硅化物结构132的长度可沿结构的长度变化,并且区段不需要具有相同长度。
[0022]应了解,与在其相应端处仅具有第一及第二硅化物结构的常规电阻器相比,具有中间硅化物结构132的实例电阻器110具有降低的TCR。在介于中间硅化物部分132之间的多晶硅层116的区中,在第一端部硅化物结构118与第二端部硅化物结构120之间行进的电流被迫离开低欧姆硅化物并行进跨越界面进入多晶硅层116。这是隧穿工艺,并通过更高温度增强。因此,硅化物结构与多晶硅之间的界面在较高温度下具有较低电阻率(即,负TCR)。多晶硅层116及硅化物的TCR将保持在其相应基线上,但硅化物与多晶硅的界面电阻具有负TCR。通过选择在第一硅化物结构118与第二硅化物结构120之间的硅化及非硅化中间区段的长度及数目,可在宽值范围内调整电阻器110的电阻及TCR。因此,如果多晶硅电阻器材料116以具有正TCR开始,那么可通过根据本发明定制中间硅化物结构来创建具有零或负TCR的电阻器。一般来说,提供中间硅化物部分132操作以降低所得到的电阻器结构110的TCR。
[0023]应了解,可在包含多晶硅沉积步骤及硅化步骤两者的任何制造工艺中以极少成本或在没有额外成本或处理时间的情况下来制造实例电阻器110。
[0024]转到图3,通常由参考数字300说明及识别用于制作根据本发明的电阻器的实例方法300。还将结合图4到12描述方法300,图4到12说明在制造的连续中间阶段的具有中间硅化物部分132的实例电阻器110。不包含中间硅化物部分的第二电阻器410也在图4到12中的制造的连续中间阶段中说明。如将了解,在需要的情况下,电阻器110及410两者可在共同工艺(例如方法300)中彼此并排制造。
[0025]图3中的方法开始于工艺步骤304,其中在体半导体衬底上形成绝缘层。体半导体衬底可为硅(Si)衬底,但本发明的方面可与SOI晶片、在硅晶片上方形成的外延硅层及包含III-V材料的任何其它半导体本体相关联地实行。体半导体衬底可为单晶Si衬底,或者例如在单晶Si衬底的顶部上外延生长的Si层。体衬底可具有植入物(例如,阱)。如果所述工艺提供双多晶硅堆叠(例如,模拟或BiCMOS工艺中的双多晶硅),那么半导体材料也可为另一多晶硅层。绝缘层可为任何合适材料,例如氧化物或类似物,包含栅极氧化物或场氧化物。在一个实例中,绝缘层包含热生长的SiO2氧化物516或通过任何合适技术形成的任何其它电介质材料。实例绝缘材料包含SiO2、SiON、高k电介质中的一或多者以及其堆叠或组合,包含(但不限于)包含氧化铝(Al2O3)、氧化锆(ZrO2)、氧化铪(HfO2)、氧化镧(La2O3)、氧化钇(Y2O3)、氧化钛(TiO2)的二元金属氧化物,以及其硅酸盐及铝酸盐;包含氮氧化铝(AlON)、氮氧化锆(ZrON)、氮氧化铪(HfON)、氮氧化镧(LaON)、氮氧化钇(YON)的金属氮氧化物,以及其硅酸盐及铝酸盐,例如ZrSiON、HfSiON、LaSiON、YSiON等等;及钙钛矿型氧化物,其包含例如钛酸钡、钛酸锶、钛酸锶钡(BST)、钛酸铅、锆钛酸铅、锆钛酸铅镧、钛酸镧钡、钛酸钡锆的钛酸盐系材料;例如铌酸铅镁、铌酸锂、钽酸锂、铌酸钾、钽酸锶铝及铌酸钾钽的铌酸盐或钽酸盐系材料;例如铌酸锶钡、铌酸铅钡、铌酸钛钡的钨青铜系材料;及例如钽酸锶铋、钛酸铋及其它的双层钙钛矿系材料。
[0026]在工艺步骤306中,将多晶硅沉积在体半导体衬底之上的氧化物上,并通过工艺402图案化以形成硅结构116,如图4所展示。举例来说,多晶硅的沉积及图案化可以与多晶硅的图案化共享的工艺执行以形成针对NMOS及PMOS晶体管(未展示)的栅极结构。此外,在一些实例中,多晶硅116可在随后植入步骤中未掺杂、原位掺杂或掺杂。在一个实例中,多晶硅116掺杂有p型或n型掺杂剂。可使用本发明范围内的任何合适技术(包含直接植入及/或扩散)来实现多晶硅的掺杂。在一个实例中,采用扩散,其中植入工艺向多晶硅提供p型或n型掺杂剂,借此产生p掺杂或n掺杂多晶硅。在某些实例中,然后执行退火工艺以扩散掺杂剂。掺杂也可在与例如在衬底212上的别处构造的晶体管的栅极结构的掺杂共享的工艺中执行。
[0028]在一个实例中,如图9中所展示那样植入区140,例如使用同时用于在IC的晶体管中植入n及p型源极/漏极结构的植入工艺(未展示)。例如,如果是CMOS工艺的部分,那么预期端区116及118可接收源/漏植入。
[0029]在工艺步骤308中,举例来说,使用图5中的沉积工艺502,在多晶硅结构116及绝缘层214上方施加硅化物块134。硅化物块134可为用于阻挡硅化物形成的任何合适材料,并且通常包含氧化物及/或氮化物的组合。
[0030]在工艺步骤310中,将光致抗蚀剂612施加在硅化物块134上方,如通过图6中的沉积工艺602所展示。
[0032]在工艺步骤314中,硅化物阻挡层134经蚀刻以去除未被剩余光致抗蚀剂612覆盖的其部分,如图8中的工艺802所展示。从多晶硅层116及/或未被光致抗蚀剂612覆盖的任何其它位置去除硅化物阻挡层134。这使在待硅化的区域中的多晶硅层116暴露,同时留下被硅化物阻挡层134阻挡而无法进行硅化物形成的多晶硅结构116的区。针对电阻器110,待硅化的区包含图1及2中所展示的第一及第二硅化物结构118及120以及多个中间结构132的预期位置。针对电阻器410,待硅化的区包含第一及第二硅化物结构1118及1120(参见图12)。
[0033]在工艺步骤316中,去除剩余光致抗蚀剂,如图9中的工艺902所展示并进行适当的表面清洁。在工艺步骤318中,使用图10中的沉积工艺1002,在多晶硅结构116及剩余硅化物块134上方沉积金属层1012。金属层1012可为例如钴或镍,或者适合于硅化物形成的任何其它金属。
[0034]在工艺步骤320中,组合件经历硅化步骤,其中通过图11中的退火工艺1102在多晶硅层及金属层的界面处形成硅化物。将了解,防止在硅化物阻挡层134存在的区中形成硅化物。因而,电阻器110包含硅化物端结构118及120,以及通过交错的块结构134彼此隔开的多个中间硅化物结构132。电阻器410仅包含硅化物端结构1118及1120。
[0035]在工艺步骤322中,去除过量金属1012,如图12中的工艺1202所展示。
[0036]在所说明实例中,在322处执行进一步退火步骤以完成硅化物形成。可在此步骤中执行任选植入以调制硅化物的接触电阻。现在,电阻器110及410准备用于接触形成及其它后端处理,在图3中的324处,其可包含例如顶部氧化物层的形成及/或端硅化物结构中的触点的形成。
[0037]另一个任选工艺步骤可包含经由通过硅化物结构118、120、132的植入的掺杂,以修改硅化物与多晶硅212之间的界面电阻的响应。这增加刚好在金属半导体界面处的掺杂水平并且可辅助通过界面的电子传递。
[0038]应了解,所揭示实例的硅化物结构可通过任何合适硅化物形成技术来形成。在一个可能的实施方案中,形成氮化物掩模并对其进行图案化以曝光多晶硅的部分,并沉积钴或其它合适金属以便于接触多晶硅的暴露部分。在一个可能的实施方案中,然后加热多晶硅及金属(例如,800到900°C)以使多晶硅与经沉积金属反应以形成硅化物结构到约为几百埃的厚度。在另一可能的实施方案中,通过化学气相沉积(CVD)使用甲硅烷或二氯硅烷与六氟化钨作为源气体形成硅化物结构(例如,钛硅化物TiSi2或钨硅化物WSix),然后在800到900°C下进行退火以产生导电化学计量硅化物结构。在另一种可能的实施方案中,将钛或钨金属溅射沉积在多晶硅及剩余硅化物块上,然后将其加热到某一温度(例如,800到900°C)以使多晶硅与沉积金属反应以形成硅化物结构,优选地,厚度约为几百埃。在不适合硅化物形成的材料例如III-V中,可使用使用例如Ti、Pt、Pd、W、Ni或Au的合适金属的金属堆叠。此外,可执行化学机械抛光(CMP)工艺以产生适合于晶片接合的光滑表面。
[0040]现在应了解,电阻器110可使用通常用于制造电阻器(例如电阻器410)的步骤来制造,所述电阻器通过在额外区中蚀刻光致抗蚀剂以留下除电阻器的端区之外还阻挡某些中间区中的硅化物形成的图案而不包含中间硅化物部分。另外,或者替代地,实例电阻器110可在包含多晶硅沉积及图案化、氧化物形成、遮蔽/蚀刻及硅化步骤的共享工艺步骤中与晶体管一起制造。因而,本发明阐述在制造工艺中制造低或零TCR电阻器的低或零成本添加方法,其包括至少多晶硅沉积步骤及硅化步骤。
[0041]参考图13及14,通常由参考数字1310说明及识别根据本发明的另一实例电阻器。在此实例中,电阻器1310形成在体半导体衬底1312中,如与图1及2的多晶硅电阻器110相对。一般来说,电阻器1310以与上文描述的方法300类似的工艺形成,区别在于不同于在半导体衬底上沉积及图案化多晶硅结构,在半导体衬底中隔离电阻器区,然后,在隔离电阻器区上直接形成硅化物结构。
[0042]为此,应了解,电阻器1310包含半导体衬底1312的电阻器区1314,其与半导体衬底1312的其余部分隔离。半导体衬底1310可为硅衬底,但本发明的方面可与SOI晶片、在硅晶片上方形成的外延硅层及包含III-V材料的任何其它半导体本体相关联地实行。举例来说,体半导体衬底可为普通的Si衬底,或者是在普通Si衬底顶部上的外延生长的Si层。体衬底可已经接收植入物(例如,阱)。电阻器区1314可由例如环绕电阻器区1314的氧化物结构1316(例如,LOCOS或浅沟槽隔离(STI))形成,或者通过例如结隔离的各种其它隔离技术形成。电阻器1310包含第一及第二硅化物端结构1318及1320,以及多个中间硅化物结构1332。端结构1318及1320之下的半导体材料可为经掺杂的,如图14中的区1340中所展示。在一个实例中,区1340在用于制作IC中的晶体管(未展示)的源极/漏极植入工艺步骤期间被掺杂。应了解,半导体衬底1312上的第一及第二硅化物端部结构1318及1320以及多个中间硅化物结构1332的形成可先前结合图1到12的实例所描述的方式来执行,且电阻器结构1310可包含交错的剩余硅化物阻挡层结构1334,如图13及14中所展示。