Office Action 2: Final Rejection (2024-02-07)
Rejection types: 102 - Lack of Novelty, 103 - Obviousness

CLAIMS:
AMENDMENTSTOTHECLAIMSPlease AMEND claims 1, 3, 7, 8, 10, 11, and 13 as shown below.

The following list of claims replaces any prior listing of claims:

1\. (Currently Amended) A chip package structure, comprising:
a glass substrate, wherein a first surface of the glass substrate has solder joints and a second surface of the glass substrate has substrate solder balls;- a routing layer, wherein the routing layer is located in the glass substrate and the solder joints are electrically connected to the substrate solder balls by using the routing layer;; and
a plurality of dies, wherein each die has chip solder balls, is located on the first surface of the glass substrate, and the solder joints are bonded to the chip solder balls, wherein a coefficient of thermal expansion ofeach die ofthe plurality ofdies is close to a coefficient ofthermal expansion ofthe glass substrate.

2\. (Previously Presented) The chip package structure according to claim 1, wherein the glass substrate comprises a plurality of glass layers, there is at least one routing layer, and each routing layer is located between two adjacent glass layers.

3\. (Currently Amended) The chip package structure according to claim 1, wherein the first surface of the glass substrate has a groove, some dies of the plurality of dies are located in the groove and other dies of the plurality of dies are located outside the groove.

4\. (Previously Presented) The chip package structure according to claim 3, wherein the groove comprises a groove bottom and n steps, the n steps are located on two sides of the groove bottom, n is a positive integer, some dies of the plurality of dies in the groove are located on the groove bottom, and the other dies of the plurality of dies are located on an upper surface of an fi step in the n steps, wherein i is set to a value from 1 to n.

5\. (Previously Presented) The chip package structure according to claim 4, wherein each step comprises a first sub-step and a second sub-step, the first sub-step and the second sub-step are respectively located on the two sides of the groove bottom in opposite positions and one end of each die on the upper surface of the ithstep islocated on an upper surface of the first sub-step, and the other end of each die is located on an upper surface of the second sub-step.

6\. (Previously Presented) The chip package structure according to claim 3, wherein one end of each die outside the groove is located on a first side of the groove, the other end of each die is located on a second side of the groove, and the first side and the second side of the groove are in opposite positions.

7\. (Currently Amended) A chip package structure preparation method comprising:
distributing a routing layer in a glass substrate;
disposing solder joints on a first surface of the glass substrate;
disposing substrate solder balls on a second surface of the glass substrate, wherein the solder

Response to Office Action of August 17, 2023 joints are electrically connected to the substrate solder balls by using the routing layer;
disposing chip solder balls on a surface of each die of at least one die, wherein a coefficient of thermal expansion of each die is close to a coefficient of thermal expansion of the glass substrate;
fastening the at least one die to the first surface of the glass substrate; and
bonding the solder joints to the chip solder balls.

8\. (Currently Amended) The method according to claim 7, wherein the glass substrate comprises m glass layers-, m is a positive integer greater than 1, and distributing -the routing layer in -the glass substrate further comprises:
distributing a copper layer on a surface of a k\* glass layer;
performing circuit printing on the copper layer to form the routing layer on the surface of the k\* glass layer; and
fastening a (k+1)\* glass layer to a surface of the routing layer to obtain the glass substrate with the routing layer distributed between the two adjacent glass layers, wherein k is set to a value from 1 to m-1.

9\. (Previously Presented) The method according to claim 7, wherein the first surface of the glass substrate has a groove, there are a plurality of dies, and the fastening of the at least one die to the first surface of the glass substrate further comprises:
fastening some dies of the plurality of dies in the groove; and fastening other dies of the plurality of dies outside the groove.

10\. (Currently Amended) The method according to claim 9, wherein the groove comprises a groove bottom -and n steps-, -the n steps are located on two sides of the groove bottom, n is a positive integer, and fastening some dies of the plurality of dies in the groove -further comprises:
fastening some dies of the plurality of dies on the groove bottom; and
fastening the other dies of the plurality of dies to an upper surface of an ith step in the n steps, wherein i is set to a value from 1 to n.

11\. (Currently Amended) The method according to claim 10, wherein each step comprises a first sub-step and a second sub-step, the first sub-step and the second sub-step are respectively located on the two sides of the groove bottom in opposite positions, fastening the other dies of the plurality of dies to the pper surface of the ith step in the n steps further comprises:
fastening one end of -each die to an upper surface of the first sub-step of the ith step -in the n steps; and
fastening the other end of each die to an upper surface of the second sub-step of the ithstep.

12\. (Previously Presented) The method according to claim 9, wherein the fastening of the other dies of the plurality of dies outside the groove comprises:
fastening one end of the die to a first side of the groove; and
fastening the other end of the die to a second side of the groove, wherein the first side and the second side of the groove are in opposite positions.

13\. (Currently Amended) An electronic device comprising a chip package structure, and the chip package structure comprises:
a glass substrate, wherein a first surface of the glass substrate has solder joints and a second surface of the glass substrate has substrate solder balls;
a routing layer, wherein the routing layer is located in the glass substrate and the solder joints are electrically connected to the substrate solder balls by using the routing layer; and
a plurality of dies, wherein each die has chip solder balls, is located on the first surface of the glass substrate, and the solder joints are bonded to the chip solder balls, wherein a coefficient of thermal expansion of each die of the plurality of dies is close to a coefficient of thermal expansion of the glass substrate.

14\. (Previously Presented) The electronic device according to claim 13, wherein the glass substrate comprises a plurality of glass layers, there is at least one routing layer, and each routing layer is located between two adjacent glass layers.

15\. (Previously Presented) The electronic device according to claim 13, wherein the first surface of the glass substrate has a groove, some dies of the plurality of dies are located in the groove, and other dies of the plurality of dies are located outside the groove.

16\. (Previously Presented) The electronic device according to claim 15, wherein the groove comprises a groove bottom and n steps, the n steps are located on two sides of the groove bottom,

n is a positive integer, and some dies of the plurality of dies in the groove are located on the groove bottom, and the other dies of the plurality of dies are located on an upper surface of an fi step in the n steps, wherein i is set to a value from 1 to n.

17\. (Previously Presented) The electronic device according to claim 16, wherein each step comprises a first sub-step and a second sub-step, and the first sub-step and the second sub-step are respectively located on the two sides of the groove bottom in opposite positions, one end of each die on the upper surface of the fi step is located on an upper surface of the first sub-step, and the other end of each die is located on an upper surface of the second sub-step.

18\. (Previously Presented) The electronic device according to claim 15, wherein the one end of each die outside the groove is located on a first side of the groove, the other end of each die is located on a second side of the groove, and the first side of the groove and the second side of the groove are in opposite positions.

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA  35 U.S.C. 102 and 103 (or as subject to pre-AIA  35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA  to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 7, 9, 13, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eisherbini et al. (US 2020/0364600, previously cited hereinafter, Eisherbini.)
In regard to claims 1, 7, and 13, in fig. 1, Eisherbini discloses a chip package structure, comprising:
a glass substrate (para [0040]), wherein a first surface of the glass substrate has solder joints, or contact, 146 (para [0040]) and a second surface of the glass substrate has substrate solder balls 137 (para [0055]);
a routing layer, wherein the routing layer is located in the glass substrate and the solder joints are electrically connected to the substrate solder balls by using the routing layer, fig. 1; and
a plurality of dies 114 (para [0040]), wherein each die has chip solder balls is located on the first surface of the glass substrate, and the solder joints are bonded to the chip solder balls, and wherein a coefficient of thermal expansion of each die of the plurality of dies is close to a coefficient of thermal expansion of the glass substrate. The CTE of the element is close because the substrate is made of glass and the die is made from semiconductor materials. This is known to one of ordinary skill in the art.
Regarding claims 3 and 9, and 15, wherein the first surface of the glass substrate has a groove, or recess, 108 (para [0040]), some dies of the plurality of dies are located in the groove, and other dies of the plurality of dies are located outside the groove. Fig. 6.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 8, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eisherbini as applied to claim 1 above, and further in view of MASUKAWA et al. (US 2018/0277395, previously cited, hereinafter, Masukawa.)
Regarding claims 2 and 8, 14, Eisherbini discloses all of the claimed limitations as mentioned above. Eisherbini also further mentions that the substrate may be formed of multiple layers (para [0041]) wherein the routing layers formed inside the substrate, except, wherein each routing layer is located between two adjacent glass layers.
Masukawa, in figs. 1b and 4a-d, discloses an analogous semiconductor device including a glass substrate 101/280 (para [0039]), a cavity111 (para [0039]) in the substrate, and electrical contacts 112/113 (para [0039]) on both sides of the substrate, and routing elements are formed between layers, fig. 4a. Masukawa further teaches the substrate is a laminated substrate (para [0063]), and the routing elements are formed in between in order to provide protection, support, and external connection. This is common in the art.
Therefore, it would have been obvious to one of ordinary skill in the art to use the laminate substrate as taught in order to provide protection, support, and external connection.
Furthermore, regarding claim 8, the combination of Eisherbini and Matsukawa further discloses the routing layers comprises copper and the method of printing to form conductive traces (Eisherbini’s para [0048] and Matsukawa’s para [0051].)
Claim(s) 4-6, 10-12, and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eisherbini as applied to claims 1 and 3 above, and further in view of Kang (US 2004/0154164.)
In regard to claims 4 and 5, and 10-11, 16-17, Eisherbini discloses all of the claimed limitations as mentioned above. Eisherbini also further discloses n steps located on the side of the groove (fig. 7), except on both sides.
Kang, in fig. 2, discloses an analogous device including a ceramic (glass) substrate 204 (para [0012]). The substrate further includes n steps on both sides in order to provide additional connection to additional die. Thus, is common in the art.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the application was filed to have additional steps or substeps as taught in order to create additional contact area.
Regarding claims 6, 12, and 18, Kang further discloses wherein one end of each die outside the groove is located on a first side of the groove, the other end of each die is located on a second side of the groove, and the first side and the second side of the groove are in opposite positions. Fig. 2.
Response to Arguments
Applicant's arguments filed 11/14/23 have been fully considered but they are not persuasive. The Applicant argues that the cited art, Elsherbini, does not disclose the newly added claimed limitation, wherein a coefficient of thermal expansion (CTE) of each die of the plurality of dies is close to a coefficient of thermal expansion of the glass substrate, by reasoning that the cited reference is teaching away from the newly added claimed limitation (see the remarks’ pages 8-9.) The Examiner respectfully disagrees. In fact the term “close” limitation is vague and broad in light if the specification. Thus, without a specific range it is not clear how close is a close value. The cited reference, Elsherbini, discloses an analogous semiconductor package. The substrate of the package is made of glass that is the same material of the substrate as currently claimed (para [0041].) And the die is also a semiconductor die that is made of similar martial as the currently claimed die, semiconductor materials, for example (para [0040].) Therefore, these materials would inherently have the similar CTEs as currently claimed and considered to be relatively close in value. It is known to one of ordinary skill in the art. Therefore, the prior art indeed discloses all of the claimed limitations as discussed above and the rejection remains the same.
Conclusion
THIS ACTION IS MADE FINAL.  Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action.  In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action.  In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.

APPLICANT REBUTTAL: REMARKS
Favorable reconsideration of this Application, in light of the following discussion, is respectfully requested. Claims 1-18 were previously presented. Claims 1, 3, 7, 8, 10, 11, and 13 are amended. Accordingly, claims 1-18 are pending in the present Application. Applicant submits that upon entry of the present Response, claims 1-18 are in condition for allowance. Moreover, Applicant submits that no new matter has been introduced by the foregoing amendments.
Prior Art Re
jections
The Office Action rejected claims 1, 3, 7, 9, 13, and 15 under 35 U.S.C. § 102(a)(1) as being anticipated by Pub. No. US2020/0364600 to Elsherbini et al. ("Elsherbini"), mistakenly listed as "Eisherbini" by the Examiner in the Office Action.
The Office Action rejected claims 2, 8, and 14 under 35 U.S.C. § 103 as unpatentable over Elsherbini in view of Pub. No. US2018/0277395 to Masukawa et al. ("Masukawa").
The Office Action rejected claims 4-6, 10-12, and 16-18 under 35 U.S.C. § 103 as unpatentable over Elsherbini in view of Pub. No. US2004/0154164 to Kang ("Kang").
"wherein a coefficient of thermal expansion of each die ofthe plurality of dies is close to a coefficient of thermal expansion of the glass substrate" (emphasis added). Similar subject matter appears in claims 7 and 13. In the Specification, paragraph [0004] discloses that coefficients of thermal expansion of most glass substrates are
far greater
than a coefficient of thermal expansion of a die. Paragraph [0038] discloses that "the coefficient of thermal expansion of the glass may be adjusted by adjusting composition proportions of the glass during glass preparation, so that the coefficient of thermal expansion of the glass is close to the coefficient of thermal expansion of the die." Also see paragraph [0055].
The Office Action relied upon Elsherbini for both a glass substrate and a plurality of dies, citing paragraph [0040]. In paragraph [0056], Elsherbini discloses that because substrate 102 and dies 114 have significantly different coefficients of thermal expansion (CTE), Elsherbini adds a mold material 127 with an intermediate CTE between 114 and 102 to reduce stress.
Hence, Elsherbini teaches away from a coefficient of thermal expansion of each die of the plurality of dies being close to a coefficient of thermal expansion of the glass substrate because
Elsherbini must add mold material 127 to compensate for differential thermal expansion of the packet substrate 102 and the dies 114 due to their significantly different CTEs. Masukawa and Kang do not remedy the deficiencies of Elsherbini.
Accordingly, claims 1, 7, and 13 are allowable over the references of record. Claims 2-6 depend upon claim 1, claims 8-12 depend upon claim 7, and claims 14-18 depend upon claim 13. Thus, claims 2-6, 8-12, and 14-18 are allowable due to their respective dependencies upon allowable claims. Therefore, Applicant respectfully requests withdrawal of these rejections.
CONCLUSION

NEXT OFFICE ACTION: DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA  35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA  35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 1, 7, and 13 recite a new limitation, “substantially matches”. The new limitation renders new matter situation because the original specification does not describe the limitation directly or inherently that would be understood by one of ordinary skill in the art. The specification instead discloses that by adjusting composition proportions of the glass so that the thermal expansion of the glass substrate is close to that of the die. This description does not mean that the TEC of elements actually substantially match (see the current specification paras [0038, 0083, 0123], for example.)
The following is a quotation of 35 U.S.C. 112(b):
(b)  CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA  35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 7, and 13 recite a new limitation, “substantially matches”, in lines 9, 8, and 10, respectively. The new limitation renders indefinite situation because the original specification does not describe the limitation directly or inherently that would be understood by one of ordinary skill in the art. The specification instead discloses that by adjusting composition proportions of the glass so that the thermal expansion of the glass substrate is close to that of the die. This description does not mean that the CTE of elements actually substantially match (see the current specification paras [0038, 0083, 0123], for example.) The phrase “substantially matches, therefore, is unclear since there is not an actual value that was mentioned to further limit a value or a range of the elements. The term matches may also mean the same. Thus, for the examination purposes, the office presumes the CTE of the elements as currently claimed is close in value, but not identical or the same.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA  35 U.S.C. 102 and 103 (or as subject to pre-AIA  35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA  to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7, and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Goida et al. (US 2016/0167951, newly cited, hereinafter, Goida.)
In regard to claims 1, 7, and 13, in figs. 1A-1B, for example, Goida discloses a chip package structure, or an integrated device package 1 (para [0028], comprising:
a glass substrate, or an interposer 6 (paras [0028 and 0031]), wherein a first surface of the glass substrate has solder joints (not shown, however, the surface of the substrate has connecting element to accommodate the electrical connection with elements 8 and routing 10 (paras [0030-0031]) and a second surface of the glass substrate has substrate solder balls 9 (para [0034]);
a routing layer 10, wherein the routing layer is located in the glass substrate and the solder joints are electrically connected to the substrate solder balls by using the routing layer; and
a plurality of dies 2/3 (para [0004], where more dies may be formed), wherein each die has chip solder balls 8 (para [0030]), is located on the first surface of the glass substrate, and the solder joints are bonded to the chip solder balls, wherein composition proportions of the glass substrate ensure that a coefficient of thermal expansion of each die of the plurality of dies substantially closely matches is close to a coefficient of thermal expansion of the glass substrate (para [0031].)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 8, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goida as applied to claim 1 above, and further in view of MASUKAWA et al. (US 2018/0277395, previously cited, hereinafter, Masukawa.)
Regarding claims 2 and 8, and 14, Goida discloses all of the claimed limitations as mentioned above. Eisherbini also further mentions that the substrate may be laminated substrate (para [0031]) wherein the routing layers formed inside the substrate, except, further shows the detail wherein each routing layer is located between two adjacent glass layers.
Masukawa, in figs. 1b and 4a-d, discloses an analogous semiconductor device including a glass substrate 101/280 (para [0039]), a cavity111 (para [0039]) in the substrate, and electrical contacts 112/113 (para [0039]) on both sides of the substrate, and routing elements are formed between layers, fig. 4a. Masukawa further teaches the substrate is also a laminated substrate (para [0063]), and the routing elements are formed in between in order to provide protection, support, and external connection. This is common in the art.
Therefore, it would have been obvious to one of ordinary skill in the art to use the laminate substrate as taught in order to provide protection, support, and external connection.
Furthermore, regarding claim 8, the combination of Goida and Matsukawa further discloses the routing layers comprises copper and the method of printing to form conductive traces (Masukawa’s para [0043] and para [0051].)
Claim(s) 3, 6, 9, 12, 15, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goida as applied to claim 1 above, and further in view of Kang (US 2004/0154164.)
In regard to claims 3, 6, 9, 12, 15 and 18, Goida discloses all of the claimed limitations as mentioned above and further discloses a groove in the substrate 6, and other dies of the plurality of dies are located outside the groove, except some dies of the plurality of dies are located in the groove.
Kang, in fig. 2, discloses an analogous device including a ceramic (glass) substrate 204 (para [0012]) including a groove with steps on both sides and bottom chip or semiconductor die 206 disposed in and on the bottom of the groove in order to create addition surface area in the package as a whole. This is common in the art. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the application was filed to include the die in the groove a taught in order to create addition surface area in the package as a whole.
Allowable Subject Matter
Claims 4-5, 8, 10-11, and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art do not show some dies of the plurality of dies in the groove are located on the groove bottom, and the other dies of the plurality of dies are located on an upper surface of an ith step in the n steps.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion

CITED REFERENCE SUMMARIES: Ref US5227583A: Claims:
A ceramic package suitable for a semiconductor device comprising a) a ceramic base component having a first portion for receiving a semiconductor chip and a second portion outward from said first portion, b) a plurality of bonding pads of an electrically conductive metallic material covering a first area of said second portion of said base component and suitable for being electrically connected to said chip, c) a first bus of an electrically conductive metallic material covering a second area of said second portion of said base component and suitable for being electrically connecting to said chip, d) a second bus of an electrically conductive metallic material covering a third area of said second portion of said base component and suitable for being electrically connecting to said chip, said bonding pad, said first and second buses being electrically insulated from each other, e) a signal shielding component bonded to said base component outward of and electrically insulated from said bonding pad and said first and second buses, said shielding component comprising first and second electrically conductive metallic layers electrically insulated from each other by a first layer of a dielectric material, all of said layers being substantially in alignment, and said first electrically conductive metallic layer being electrically connected to said first bus and said second electrically conductive metallic layer being electrically connected to said second bus, f) a second layer of a dielectric material covering the surface of said shielding component opposing the surface bonded to said base component, and g) a glass frit bonded to said second layer of dielectric material having the metallic leads that extend from a metallic lead frame embedded therein, wherein said leads and said signal shielding component ar in substantial alignment an said leads are electrically insulated from said shielding component and are connected to said bonding pads.
a) a ceramic base component having a first portion for receiving a semiconductor chip and a second portion outward from said first portion,
b) a plurality of bonding pads of an electrically conductive metallic material covering a first area of said second portion of said base component and suitable for being electrically connected to said chip,
c) a first bus of an electrically conductive metallic material covering a second area of said second portion of said base component and suitable for being electrically connecting to said chip,
d) a second bus of an electrically conductive metallic material covering a third area of said second portion of said base component and suitable for being electrically connecting to said chip, said bonding pad, said first and second buses being electrically insulated from each other,
e) a signal shielding component bonded to said base component outward of and electrically insulated from said bonding pad and said first and second buses, said shielding component comprising first and second electrically conductive metallic layers electrically insulated from each other by a first layer of a dielectric material, all of said layers being substantially in alignment, and said first electrically conductive metallic layer being electrically connected to said first bus and said second electrically conductive metallic layer being electrically connected to said second bus,
f) a second layer of a dielectric material covering the surface of said shielding component opposing the surface bonded to said base component, and
g) a glass frit bonded to said second layer of dielectric material having the metallic leads that extend from a metallic lead frame embedded therein, wherein said leads and said signal shielding component ar in substantial alignment an said leads are electrically insulated from said shielding component and are connected to said bonding pads.
A semiconductor package according to claim 1 wherein said one of said electrically conductive metallic layers is a ground plate and the other electrically conductive metallic layer is a power plate whereby when s id package is utilized in, high frequency semiconductor applications and where the density of leads is relatively high, the interference in the semiconductor circuits is significantly reduced.
A semiconductor package according to claim 2 wherein said electrically conductive metallic materials are precious metal materials.
A semiconductor package according to claim 3 wherein said precious metal material is selected from the group consisting of gold, silver, palladium and platinum metal and alloys of said metals.
A semiconductor package according to claim 3 wherein said precious metal material is a silver-platinum alloy.
A semiconductor package according to claim 1 wherein said ceramic in said base component is selected from the group consisting of Al 2 O 3 , MgO, AlN, Si 3 N 4 , BN, SiC, BeO, TiO 2 , Zr 2 O and mixtures thereof.
A semiconductor package according to claim 1 wherein said first and second buses are generally concentric.
A semiconductor package according to claim 1 wherein said first conductive metallic layer and said first bus are spaced apart vertically from said second conductive metallic layer.
A semiconductor package according to claim 1 wherein said dielectric material is borosilicate.
A method of forming a semiconductor package comprising a) providing a prefired ceramic base component having a first portion and a second portion outward of said first portion, b) depositing an electrically conductive material over a first segment of said second portion adjacent said first portion, to provide a plurality of electrically conductive bonding pads, c) forming a signal shielding component by depositing, in sequence and in substantial alignment, a first layer of an electrically conductive metallic material, a layer of a first dielectric material and a second layer of an electrically conductive metallic material, d) bonding an external surface of said signal shielding component to said ceramic base component, e) depositing a layer of a second dielectric material on the opposing external surface of said shielding component, f) depositing a layer of glass frit upon the layer of said second dielectric material and between said bonding pad and said shielding component and positioning a metallic lead frame having its leads extending therefrom substantially in alignment with said signal shielding component and g) firing said package to melt said frit thereby embedding said leads [frame] into said glass frit.
a) providing a prefired ceramic base component having a first portion and a second portion outward of said first portion,
b) depositing an electrically conductive material over a first segment of said second portion adjacent said first portion, to provide a plurality of electrically conductive bonding pads,
c) forming a signal shielding component by depositing, in sequence and in substantial alignment, a first layer of an electrically conductive metallic material, a layer of a first dielectric material and a second layer of an electrically conductive metallic material,
d) bonding an external surface of said signal shielding component to said ceramic base component,
e) depositing a layer of a second dielectric material on the opposing external surface of said shielding component,
f) depositing a layer of glass frit upon the layer of said second dielectric material and between said bonding pad and said shielding component and positioning a metallic lead frame having its leads extending therefrom substantially in alignment with said signal shielding component and
g) firing said package to melt said frit thereby embedding said leads [frame] into said glass frit.
A method according to claim 10 wherein said metallic conductive materials are formed by depositing a photoetchable thick film material and thereafter etching the conductive segments.
A method according to claim 10 wherein said metallic conductive materials are formed by screening.
Ref US6232251B1: Claims:
Dielectric ceramics comprising:
a diopside oxide crystal phase;
at least one crystal phase selected from the group consisting of a quartz crystal phase and a composite oxide crystal phase containing Ti and Mg or Zn; and
a glass phase of an amount of not larger than 30% by weight;
said dielectric ceramics having a coefficient of thermal expansion of not smaller than 5.5 ppm/Â° C. at room temperature to 400Â° C. and a dielectric loss of not larger than 30Ã10 â4 at 60 to 77 GHz.
Dielectric ceramics according to claim 1 , wherein an ilmenite crystal phase or a spinel crystal phase is contained as a composite oxide crystal phase containing Ti and Mg or Zn.
Dielectric ceramics according to claim 1 , wherein not less than 70% by weight of said glass phase is amorphous silica.
Dielectric ceramics according to claim 1 , wherein said quartz crystals are contained in an amount of from 1 to 50% by weight.
Dielectric ceramics according to claim 2 , wherein said composite oxide crystal phase containing Ti and Mg or Zn is contained in an amount of from 1 to 50% by weight.
Dielectric ceramics according to claim 1 , wherein SrO is contained in said diopside oxide crystal phase or in said glass phase.
Dielectric ceramics according to claim 1 , further comprising a MgSiO 3 crystal phase or a Mg 2 SiO 4 crystal phase.
Dielectric ceramics according to claim 7 , wherein the MgSiO 3 crystal phase and the Mg 2 SiO 4 crystal phase are contained in a total amount of from 0.1 to 20% by weight.
Dielectric ceramics according to claim 4 , containing the quartz crystal phase, and having a coefficient of thermal expansion of not smaller than 8.5 ppm/Â° C. at room temperature up to 400Â° C. and a dielectric constant of not larger than 7.
Dielectric ceramics according to claim 5 , containing the composite oxide crystal phase containing Ti and Mg or Zn, and having a coefficient of thermal expansion of not smaller than 7 ppm/Â° C. at room temperature up to 400Â° C. and a dielectric constant of not smaller than 8.
A wiring board equipped with an insulating substrate comprising dielectric ceramics of claim 1 .
Ref US20210043528A1: Claims:
An electronic package assembly comprising: a glass substrate comprising: an upper glass cladding layer; a lower glass cladding layer; a glass core layer fused to the upper glass cladding layer and the lower glass cladding layer, wherein the upper glass cladding layer and the lower glass cladding layer have a higher etch rate in an etchant than the glass core layer; a first cavity positioned within one of the upper glass cladding layer or the lower glass cladding layer; and a second cavity positioned within one of the upper glass cladding layer or the lower glass cladding layer; a microprocessor positioned within the first cavity; and a micro-electronic component positioned within the second cavity.
a glass substrate comprising: an upper glass cladding layer; a lower glass cladding layer; a glass core layer fused to the upper glass cladding layer and the lower glass cladding layer, wherein the upper glass cladding layer and the lower glass cladding layer have a higher etch rate in an etchant than the glass core layer; a first cavity positioned within one of the upper glass cladding layer or the lower glass cladding layer; and a second cavity positioned within one of the upper glass cladding layer or the lower glass cladding layer;
an upper glass cladding layer;
a lower glass cladding layer;
a glass core layer fused to the upper glass cladding layer and the lower glass cladding layer, wherein the upper glass cladding layer and the lower glass cladding layer have a higher etch rate in an etchant than the glass core layer;
a first cavity positioned within one of the upper glass cladding layer or the lower glass cladding layer; and
a second cavity positioned within one of the upper glass cladding layer or the lower glass cladding layer;
a microprocessor positioned within the first cavity; and
a micro-electronic component positioned within the second cavity.
The electronic package assembly of claim 1 , wherein the upper glass cladding layer has a thickness that is different than a thickness of the lower glass cladding layer.
The electronic package assembly of claim 1 , wherein the micro-electronic component comprises a memory chip positioned within the second cavity.
The electronic package assembly of claim 3 , wherein the first cavity is positioned on the lower glass cladding layer.
The electronic package assembly of claim 3 , wherein the second cavity is positioned on the upper glass cladding layer.
The electronic package assembly of claim 3 , wherein the first cavity and the second cavity are positioned on the lower glass cladding layer.
The electronic package assembly of claim 3 , wherein the glass substrate further comprises a third cavity, and the electronic package assembly further comprises a second micro-electronic component positioned within the third cavity of the glass substrate.
The electronic package assembly of claim 7 , wherein the third cavity and the second cavity are positioned on the same glass cladding layer.
The electronic package assembly of claim 3 , further comprising: a thermal via extending through the glass substrate and thermally coupled to the microprocessor; and a heat spreader thermally coupled to the thermal via.
a thermal via extending through the glass substrate and thermally coupled to the microprocessor; and
a heat spreader thermally coupled to the thermal via.
The electronic package assembly of claim 1 , wherein the upper glass cladding layer and the lower glass cladding layer have a photosensitivity that is different than a photosensitivity of the glass core layer.
The electronic package assembly of claim 1 , further comprising: a plurality of solder bumps positioned on a single surface of the electronic package assembly; and a plurality of vias extending between the plurality of solder bumps and the microprocessor and between the plurality of solder bumps and the micro-electronic component.
a plurality of solder bumps positioned on a single surface of the electronic package assembly; and
a plurality of vias extending between the plurality of solder bumps and the microprocessor and between the plurality of solder bumps and the micro-electronic component.
A wafer-level electronic package assembly comprising: a glass substrate comprising: an upper glass cladding layer; a lower glass cladding layer; a glass core layer fused to the upper glass cladding layer and the lower glass cladding layer, wherein the upper glass cladding layer and the lower glass cladding layer have a higher etch rate in an etchant than the glass core layer; a plurality of first cavities positioned within one of the upper glass cladding layer or the lower glass cladding layer; and a plurality of second cavities positioned within one of the upper glass cladding layer or the lower glass cladding layer; a plurality of microprocessors positioned within the plurality of first cavities; and a plurality of micro-electronic components positioned within the plurality of second cavities.
a glass substrate comprising: an upper glass cladding layer; a lower glass cladding layer; a glass core layer fused to the upper glass cladding layer and the lower glass cladding layer, wherein the upper glass cladding layer and the lower glass cladding layer have a higher etch rate in an etchant than the glass core layer; a plurality of first cavities positioned within one of the upper glass cladding layer or the lower glass cladding layer; and a plurality of second cavities positioned within one of the upper glass cladding layer or the lower glass cladding layer;
a plurality of first cavities positioned within one of the upper glass cladding layer or the lower glass cladding layer; and
a plurality of second cavities positioned within one of the upper glass cladding layer or the lower glass cladding layer;
a plurality of microprocessors positioned within the plurality of first cavities; and
a plurality of micro-electronic components positioned within the plurality of second cavities.
The wafer-level electronic package assembly of claim 12 , further comprising: a plurality of solder bumps positioned on a single surface of the electronic package assembly; and a plurality of vias extending between the plurality of solder bumps and the plurality of microprocessors and between the plurality of solder bumps and the plurality of micro-electronic components.
a plurality of vias extending between the plurality of solder bumps and the plurality of microprocessors and between the plurality of solder bumps and the plurality of micro-electronic components.
The wafer-level electronic package assembly of claim 12 , further comprising a plurality of passive RF devices positioned on a top surface of the electronic package assembly.
The wafer-level electronic package assembly of claim 13 , wherein the upper glass cladding layer has a thickness that is different than a thickness of the lower glass cladding layer.
A method for forming an electronic package assembly, the method comprising: applying a mask to a surface of a glass substrate comprising a glass cladding layer fused to a glass core layer such that the mask is positioned on the glass cladding layer, the mask comprising one or more open regions at which the glass cladding layer remains uncovered by the mask, the glass cladding layer having a higher etch rate in an etchant than the glass core layer; exposing the glass substrate to the etchant, thereby selectively etching a portion of the glass cladding layer and forming one or more cavities in the glass substrate; and positioning a micro-electronic component within the one or more cavities of the glass substrate.
applying a mask to a surface of a glass substrate comprising a glass cladding layer fused to a glass core layer such that the mask is positioned on the glass cladding layer, the mask comprising one or more open regions at which the glass cladding layer remains uncovered by the mask, the glass cladding layer having a higher etch rate in an etchant than the glass core layer;
exposing the glass substrate to the etchant, thereby selectively etching a portion of the glass cladding layer and forming one or more cavities in the glass substrate; and
positioning a micro-electronic component within the one or more cavities of the glass substrate.
The method of claim 16 , wherein exposing the glass substrate to the etchant comprises selectively etching all of the glass cladding layer at the one or more open regions.
The method of claim 16 , wherein the glass cladding layer of the glass substrate is an upper glass cladding layer and the glass substrate further comprises a lower glass cladding layer fused to the glass core layer on a surface opposite the upper glass cladding layer, and the method further comprises applying the mask to a surface of the lower glass cladding layer, the mask comprising one or more open regions at which the lower glass cladding layer remains uncovered.
The method of claim 18 , wherein exposing the glass substrate to the etchant further comprises selectively etching a portion of the lower glass cladding layer and forming one or more cavities in the lower glass cladding layer.
The method of claim 18 , wherein exposing the glass substrate to the etchant comprises selectively etching all of the lower glass cladding layer at the one or more open regions.
Ref US20200321301A1: Claims:
A semiconductor device comprising: a glass substrate on a front surface or front and back surfaces of which a wiring layer including one or more layers of wiring is formed; an electronic component arranged inside an opening formed on the glass substrate; and a redistribution layer that connects the wiring of the glass substrate and the electronic component.
a glass substrate on a front surface or front and back surfaces of which a wiring layer including one o
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