Office Action 1: Non-Final Rejection (2024-12-12)
Rejection types: 102 - Lack of Novelty, 112 - Written Description/Enablement

CLAIMS:
CLAIMS
1\. A semiconductor structure, comprising a stacked structure, wherein the stacked structure comprises a plurality of stacked semiconductor dies, and each of the semiconductor dies comprises: a first base; a channel provided on the first base; and at least one first auxiliary through electrode and a plurality of connection through electrodes running through the first base, wherein the at least one first auxiliary through electrode is surrounded by the plurality of connection through electrodes, wherein connection through electrodes of adjacent ones of the semiconductor dies are connected through a first electrical connection structure to form a plurality of mutually isolated transmission paths, and each of the transmission paths is connected to at least one channel through at least one connection through electrode thereon.
2\. The semiconductor structure according to claim 1, wherein in one of the semiconductor dies, the plurality of connection through electrodes form at least one through electrode ring, and the at least one first auxiliary through electrode is arranged in each through electrode ring.
3\. The semiconductor structure according to claim 1, wherein each of the semiconductor dies is provided with at least two channels and at least two through electrode sets, each of the through electrode sets comprises the plurality of connection through electrodes, and the connection through electrodes in the at least two through electrode sets are alternately arranged around the at least one first auxiliary through electrode; and the plurality of mutually isolated transmission paths form at least two transmission path groups, and connection through electrodes in a same through electrode set are respectively located on different transmission paths of a same transmission path group.
4\. The semiconductor structure according to claim 3, wherein positions of channels on all of the semiconductor dies are in a one-to-one correspondence, and transmission paths in a same transmission path group are respectively connected to channels at corresponding positions on the semiconductor dies.
5\. The semiconductor structure according to claim 4, wherein positions of connection through electrodes connected to the channels at the corresponding positions are in a one-to-one correspondence.
6\. The semiconductor structure according to claim 3, wherein the at least two channels on each of the semiconductor dies comprise a first channel and a second channel, the at least two through electrode sets on each of the semiconductor dies comprise a first through electrode set and a second through electrode set, connection through electrodes in the first through electrode set are each a first through electrode, and connection through electrodes in the second through electrode set are each a second through electrode; in one of the semiconductor dies, the first through electrodes and the second through electrodes are alternately arranged around the at least one first auxiliary through electrode; first through electrodes on each of the semiconductor dies are connected to form one of the transmission path groups, transmission paths in the transmission path group are first transmission paths, and each of the first transmission paths is connected to one first channel; and second through electrodes on each of the semiconductor dies are connected to form one of the transmission path groups, transmission paths in the transmission path group are second transmission paths, and each of the second transmission paths is connected to one second channel.
7\. The semiconductor structure according to claim 6, wherein each of the first transmission paths is a spiral path extending spirally along a first direction; and each of the second transmission paths is a spiral path extending spirally along a second direction, and the second direction is opposite to the first direction.
8\. The semiconductor structure according to claim 6, wherein the at least two channels on each of the semiconductor dies comprise a plurality of first channels and a plurality of second channels in a one-to-one correspondence with the plurality of first channels, the at least two through electrode sets on each of the semiconductor dies comprise a plurality of first through electrode sets and a plurality of second through electrode sets in a one-to-one correspondence with the plurality of first through electrode sets, each of the first through electrode sets and a corresponding second through electrode set form a through unit, and a plurality of the through units are arranged in an array.
9\. The semiconductor structure according to claim 8, wherein each transmission path formed by the corresponding first through electrode set and second through electrode set in each of the semiconductor dies is used for a connection to a same signal source.
10\. The semiconductor structure according to claim 6, wherein one of the first through electrode sets comprises four first through electrodes, one of the second through electrode sets comprises four second through electrodes, and the four first through electrodes and the four second through electrodes are alternately arranged around one first auxiliary through electrode to form a through unit in a 3X3 array.
11\. The semiconductor structure according to claim 1, wherein the first auxiliary through electrodes in all of the semiconductor dies are connected together through a second electrical connection structure and grounded.
12\. The semiconductor structure according to claim 11, wherein positions of the first auxiliary through electrodes in all of the semiconductor dies are in a one-to-one correspondence.
13\. The semiconductor structure according to claim 1, wherein the semiconductor structure comprises a buffer layer provided below the stacked structure, the buffer layer comprises a second base and a plurality of transfer through electrodes running through the second base, and the plurality of transfer through electrodes are respectively connected to the plurality of the transmission paths.
14\. The semiconductor structure according to claim 13, wherein the plurality of semiconductor dies form at least two semiconductor die sets, the semiconductor dies in the semiconductor die sets are in a one-to-one correspondence, and each of the transmission paths is connected to a channel on corresponding semiconductor dies in the semiconductor die sets.
15\. The semiconductor structure according to claim 13, wherein the buffer layer comprises a second auxiliary through electrode running through the second base, the first auxiliary through electrodes in all of the semiconductor dies are connected together through a second electrical connection structure and connected to the second auxiliary through electrode, and one end of the second auxiliary through electrode facing away from the stacked structure is provided with a ground terminal.

OFFICE ACTION:
DETAILED ACTION
This application, 17/80,7759, attorney docket 107033-1451142(056800US), filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to Changxin Memory Technologies, Inc., and  is a continuation of PCT/CN2022/091871, filed 05/10/2022 which  claims foreign priority to Chinese application 202210208256.6, filed 03/03/2022.  Claims 1-15 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-15 are rejected under 35 U.S.C. 112(a) as failing to comply with the enablement requirement. Claim 1 contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The disclosure lacks a description or explanation for “a first base” or “channel”  recited in  claim 1.  A base is not a term of art and a channel is not used in the ordinary meaning of switching semiconductive portion of a transistor. One skilled, who is a memory circuit designer and he would not be able to produce the device based on the disclosure and what is known in the art without undue experimentation.  Claims 2-15 depend from claim 1 and include the same defect
The following is a quotation of 35 U.S.C. 112(b):
(b)  CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 recites, “to form a plurality of mutually isolated transmission paths…”  It is not clear what elements form the plurality, for example, do vertically adjacent sets of connection electrodes form mutually isolated transmission paths? Are sets that share a common connection electrode considered mutually isolated transmission paths?
Claim 1 recited “…to form a plurality of mutually isolated transmission paths, and each of the transmission paths” transmission path lacks antecedent
Claim 3 recites “and the connection through electrodes in the at least two through electrode sets are alternately arranged around the at least one first auxiliary through electrode”, it is not clear what constitutes alternately arranged, and it is not clear what a “through electrode set” includes or excludes.
Claims 2-15 depend from claim 1 and include the same defect. Claim 3 and its dependents are unexaminable due to the lack of clarity.
Claim 4 recites, “are in a one-to-one correspondence” it is unclear what this means. Geometrically, numerically, or signals?  Claim 5, 12 and 14 have the same issue.
Claim 6 states “first through electrodes on each of the semiconductor dies are connected….” It is not clear what they are connected to.  Could be each other or another element.
Claim 14 recited “is connected to a channel on corresponding semiconductor dies” is not clear how the semiconductor dies correspond.
Drawings
The drawings are objected to under 37 CFR 1.83(a).  The drawings must show every feature of the invention specified in the claims.  Therefore, a die’s first base and channel and  a buffer’s second base must be shown or the feature(s) canceled from the claim(s).  No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA  35 U.S.C. 102 and 103 (or as subject to pre-AIA  35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA  to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 8-15 are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Konno et al. (U.S. 2015/0236003).
As for claim 1,
Konno teaches in figures 4, 5 and 6, a semiconductor structure comprising
a stacked structure (LC, MC1-MC4), wherein the stacked structure comprises a plurality of stacked semiconductor dies (LC is a semiconductor logic chip, MC1-4 are semiconductor memory chips [0071,0083]),
and each of the semiconductor dies comprises:
a first base (contained in perimeter 3c));
a channel (Four peripheral regions MR in figure 6) provided on the first base;
and at least one first auxiliary through electrode (7) and a plurality of connection through electrodes (3bp) running through the first base, wherein the at least one first auxiliary through electrode is surrounded by the plurality of connection through electrodes (shown in figures 6 and 6),
wherein connection through electrodes of adjacent ones of the semiconductor dies are connected through a first electrical connection structure (6) to form a plurality of mutually isolated transmission paths, and each of the transmission paths is connected to at least one channel through at least one connection through electrode thereon. ([0116]).
As for claim 2,
Konno teaches the semiconductor structure according to claim 1, wherein in one of the semiconductor dies, the plurality of connection through electrodes form at least one through electrode ring, and the at least one first auxiliary through electrode is arranged in each through electrode ring. The auxiliary electrodes, 7 are surrounded by through electrodes, BP, which could be represented as a ring).
As for claim 3,
the semiconductor structure according to claim 1, wherein each of the semiconductor dies is provided with at least two channels (MR) and at least two through electrode sets (4 are shown, 3x9 groups), each of the through electrode sets comprises the plurality of connection through electrodes (3ap), and the connection through electrodes in the at least two through electrode sets are alternately arranged around the at least one first auxiliary through electrode (they are staggered across the groups);
and the plurality of mutually isolated transmission paths form at least two transmission path groups (4 are shown), and connection through electrodes in a same through electrode set are respectively located on different transmission paths of a same transmission path group (shown in figures).
As for claim 4,
Konno teaches the semiconductor structure according to claim 3, wherein positions of channels on all of the semiconductor dies are in a one-to-one correspondence, and transmission paths in a same transmission path group are respectively connected to channels at corresponding positions on the semiconductor dies. (they are stacks arranged directly vertically with the same footprint).
As for claim 5,
Konno teaches the semiconductor structure according to claim 4, wherein positions of connection through electrodes connected to the channels at the corresponding positions are in a one-to-one correspondence. (The through electrodes are arranged directly vertically with the same footprint
As for claim 6,
Konno teaches the semiconductor structure according to claim 3, wherein the at least two channels on each of the semiconductor dies comprise a first channel and a second channel (MR1, MR2),
the at least two through electrode sets on each of the semiconductor dies comprise a first through electrode set and a second through electrode set (there are 4 sets, one per channel),
connection through electrodes in the first through electrode set are each a first through electrode, and connection through electrodes in the second through electrode set are each a second through electrode;
in one of the semiconductor dies, the first through electrodes and the second through electrodes are alternately arranged around the at least one first auxiliary through electrode (they are in odd or even rows);
first through electrodes on each of the semiconductor dies are connected to form one of the transmission path groups, transmission paths in the transmission path group are first transmission paths, and each of the first transmission paths is connected to one first channel ([0116]);
and second through electrodes on each of the semiconductor dies are connected to form one of the transmission path groups, transmission paths in the transmission path group are second transmission paths, and each of the second transmission paths is connected to one second channel  ([0116]).
As for claim 8,
Konno teaches the semiconductor structure according to claim 6, wherein the at least two channels on each of the semiconductor dies comprise a plurality of first channels and a plurality of second channels in a one-to-one correspondence with the plurality of first channels (there are 4 memory regions MR),
the at least two through electrode sets on each of the semiconductor dies comprise a plurality of first through electrode sets and a plurality of second through electrode sets in a one-to-one correspondence with the plurality of first through electrode sets (there are multiple sets of possible sets), each of the first through electrode sets and a corresponding second through electrode set form a through unit, and a plurality of the through units are arranged in an array (the array is shown in figure 6).
As for claim 9,
Konno teaches the semiconductor structure according to claim 8, wherein each transmission path formed by the corresponding first through electrode set and second through electrode set in each of the semiconductor dies is used for a connection to a same signal source (all of the sets originate in the signal generating logic chip [0080])
As for claim 10,
Konno teaches the semiconductor structure according to claim 6, wherein one of the first through electrode sets comprises four first through electrodes, one of the second through electrode sets comprises four second through electrodes, and the four first through electrodes and the four second through electrodes are alternately arranged around one first auxiliary through electrode to form a through unit in a 3X3 array. (the sets include at lease a 3x3 array in figure 6, and include both bp and )
As for claim 11,
Konno teaches the semiconductor structure according to claim 1, wherein the first auxiliary through electrodes in all of the semiconductor dies are connected together through a second electrical connection structure (2) and grounded ([0118]).
As for claim 12,
Konno teaches the semiconductor structure according to claim 11, wherein positions of the first auxiliary through electrodes in all of the semiconductor dies are in a one-to-one correspondence. (all are aligned)
As for claim 13,
Konno teaches the semiconductor structure according to claim 1,
wherein the semiconductor structure comprises a buffer layer (LC) provided below the stacked structure, the buffer layer comprises a second base and a plurality of transfer through electrodes running through the second base (shown in figure 4), and the plurality of transfer through electrodes are respectively connected to the plurality of the transmission paths.
As for claim 14,
Konno teaches the semiconductor structure according to claim 13, wherein the plurality of semiconductor dies form at least two semiconductor die sets (there are 4), the semiconductor dies in the semiconductor die sets are in a one-to-one correspondence (aligned vertically) , and each of the transmission paths is connected to a channel on corresponding semiconductor dies in the semiconductor die sets.(Bp’s connect to the 4 memory regions on each level).
As for claim 15,
Konno teaches the semiconductor structure according to claim 13, wherein the buffer layer comprises a second auxiliary through electrode (7) running through the second base, the first auxiliary through electrodes in all of the semiconductor dies are connected together through a second electrical connection structure and connected to the second auxiliary through electrode (LC controls communication to all the memory), and one end of the second auxiliary through electrode facing away from the stacked structure is provided with a ground terminal. (Bumps inherently must provide the device a ground. [0118]).
Allowable Subject Matter
Claim 7 may be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.  Examiner cannot determine the scope of the invention due to the §112 defects.
Conclusion


NEXT OFFICE ACTION: DETAILED ACTION
This application, 17/80,7759, attorney docket 107033-1451142(056800US), filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to Changxin Memory Technologies, Inc., and  is a continuation of PCT/CN2022/091871, filed 05/10/2022 which  claims foreign priority to Chinese application 202210208256.6, filed 03/03/2022.  Claims 1, 3, 8-11, 13 and 15 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Applicant has incorporated the limitations from claim 7 into independent claim 1 and correctly argues that the amendment renders claim 1 and its dependents allowable.  Applicant has amended claim 1 to delete the limitations rejected in the previous office action under 112a and identified as missing from the drawings.  Applicant has cancelled claims 4, 5, 12 and 14 rendering the §112b rejections moot.
Allowable Subject Matter
Claims 1, 3, 8-11, 13 and 15 are allowed.
The following is an examiner’s statement of reasons for allowance:
As for claim 1, The prior art does not teach or make obvious a stack of semiconductor dies with alternating sets of through electrodes that are vertically connected in a “spiral patterns” that spiral in opposing directions, as shown in figure 8, and also includes a central  auxiliary electrode set.
Dependent claims include the novel electrode configuration of claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee.  Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion

CITED REFERENCE SUMMARIES: Ref US20150230003A1: Claims:
A device, comprising: a processor; and a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising: receiving media content for distribution to a media device; determining a content weight for the media content by motion estimation between video frames of the media content; determining a bit rate for the media content according to the content weight for the media content; encoding the media content at a first bit rate to generate a first data stream for the media content; selecting a first data channel that supports a first bit rate; and transmitting, to the media device via the first data channel, the first data stream associated with the media content.
a processor; and
a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising: receiving media content for distribution to a media device; determining a content weight for the media content by motion estimation between video frames of the media content; determining a bit rate for the media content according to the content weight for the media content; encoding the media content at a first bit rate to generate a first data stream for the media content; selecting a first data channel that supports a first bit rate; and transmitting, to the media device via the first data channel, the first data stream associated with the media content.
receiving media content for distribution to a media device;
determining a content weight for the media content by motion estimation between video frames of the media content;
determining a bit rate for the media content according to the content weight for the media content;
encoding the media content at a first bit rate to generate a first data stream for the media content;
selecting a first data channel that supports a first bit rate; and
transmitting, to the media device via the first data channel, the first data stream associated with the media content.
The device of claim 1 , wherein the operations further comprise: selecting a second data channel that supports a second bit rate; and transmitting, to the media device via the second data channel, a second data stream that is encoded at the second bit rate.
selecting a second data channel that supports a second bit rate; and
transmitting, to the media device via the second data channel, a second data stream that is encoded at the second bit rate.
The device of claim 2 , wherein the operations further comprise: determining the second bit rate for second media content according to second content weight for the second media content; encoding the second media content at the second bit rate to generate the second data stream for the second media content.
determining the second bit rate for second media content according to second content weight for the second media content;
encoding the second media content at the second bit rate to generate the second data stream for the second media content.
The device of claim 1 , wherein the first data channel comprises an Internet Protocol link and wherein the second data channel comprises a wireless cellular link.
The device of claim 1 , wherein the content weight corresponds to a level of information change within the media content.
The device of claim 1 , wherein the content weight comprises one of a first parameter indicative of a high level of information change, a second parameter indicative of a mid-level of information change, a third parameter indicative of a low level of information change, or any combination thereof.
The device of claim 1 , wherein the operations further comprise: determining a media delivery policy associated with the media device, wherein the media delivery policy prescribes an encoded bit rate for the media content that is delivered to the media device; adapting the bit rate for the media content according to the encoded bit rate that is prescribed to generate an adapted bit rate for the media content; and encoding the media content of the plurality of media content segments according to the bit rate that is adapted to generate the data stream for the media content.
determining a media delivery policy associated with the media device, wherein the media delivery policy prescribes an encoded bit rate for the media content that is delivered to the media device;
adapting the bit rate for the media content according to the encoded bit rate that is prescribed to generate an adapted bit rate for the media content; and
encoding the media content of the plurality of media content segments according to the bit rate that is adapted to generate the data stream for the media content.
The device of claim 7 , wherein the media delivery policy of the media device is determined according to a service level associated with the media device.
The device of claim 7 , wherein the media delivery policy of the media device is determined according to one of a present location of the media device, a media content type associated with the media content for distribution to the media device, or combinations thereof.
A method, comprising: dividing, by a system comprising a processor, media content into a first media content segment and a second media content segment; determining a first content weight for the first media content segment and a second content weight for the second media content segment; determining a first bit rate for the first media content segment according to the first content weight and a second bit rate for the second media content segment according to the second content weight; encoding the first media content segment at the first bit rate to generate a first data stream and the second media content segment at the second bit rate to generate a second data stream; transmitting to a first media device the first data stream associated with the first media segment according to a first media delivery policy associated with the first media device; and transmitting to a second media device the second data stream associated with the second media segment according to a second media delivery policy associated with the second media device.
dividing, by a system comprising a processor, media content into a first media content segment and a second media content segment;
determining a first content weight for the first media content segment and a second content weight for the second media content segment;
determining a first bit rate for the first media content segment according to the first content weight and a second bit rate for the second media content segment according to the second content weight;
encoding the first media content segment at the first bit rate to generate a first data stream and the second media content segment at the second bit rate to generate a second data stream;
transmitting to a first media device the first data stream associated with the first media segment according to a first media delivery policy associated with the first media device; and
transmitting to a second media device the second data stream associated with the second media segment according to a second media delivery policy associated with the second media device.
The method of claim 10 , wherein the determining the first content weight of the first media content segment is determined from motion estimation between video frames of the first media content segment.
The method of claim 10 , wherein the first data stream is transmitted via a first data channel and wherein the second data stream is transmitted via a second data channel.
The method of claim 12 , further comprising switching from the first data channel to the second data channel according to an available bandwidth at the second data channel.
The method of claim 10 , further comprising receiving from the first media device a request for a fixed bit rate for the first data stream, wherein the encoding of the first media content segment is performed according to the fixed bit rate.
The method of claim 10 , wherein the encoding of the first media content segment at the first bit rate is performed by applying digital compression to the first media content segment according to the first bit rate.
The method of claim 10 , wherein the encoding of the first media content segment at the first bit rate is performed by applying a display pixel resolution to the first media content segment according to the first bit rate.
A machine-readable storage medium, comprising executable instructions that, when executed by a processor, facilitate performance of operations, comprising: requesting first media content from a server; receiving, from the server, a first data stream associated with the first media content according to a first media delivery policy, wherein the first data stream is encoded at a first bit rate according to a first content weight of the first media content, and wherein the content weight is determined according to a motion estimation between video frames of the first media content; and presenting the first media content at a display.
requesting first media content from a server;
receiving, from the server, a first data stream associated with the first media content according to a first media delivery policy, wherein the first data stream is encoded at a first bit rate according to a first content weight of the first media content, and wherein the content weight is determined according to a motion estimation between video frames of the first media content; and
presenting the first media content at a display.
The machine-readable storage medium of claim 17 , wherein the operations further comprise transmitting to the server a request for a fixed bit rate for the first data stream, wherein the encoding of the first media content is performed according to the fixed bit rate.
The machine-readable storage medium of claim 17 , wherein the encoding of the first media content at the first bit rate is performed by applying digital compression to the first media content according to the first bit rate.
The machine-readable storage medium of claim 17 , wherein the encoding of the first media content at the first bit rate is performed by applying a display pixel resolution to the first media content according to the first bit rate.
Ref US20150236003: Claims:
1. A method of manufacturing a semiconductor device comprising the steps of:
(a) providing a wiring board having a first surface, a plurality of bonding leads formed on the first surface, a second surface opposite to the first surface, and a plurality of lands formed on the second surface and electrically connected with the plurality of bonding leads, respectively; (b) arranging a first adhesive material on the first surface of the wiring board; (c) after the step of (b), mounting a first semiconductor chip on the first surface of the wiring board via the first adhesive material such that a first front surface of the first semiconductor chip faces the first surface of the wiring board, and electrically connecting the plurality of bonding leads with a plurality of first front-surface electrodes, respectively, the first semiconductor chip having the first front surface, the plurality of first front-surface electrodes formed on the first front surface, a first back surface opposite to the first front surface, a plurality of first back-surface electrodes formed on the first back surface, and a plurality of through electrodes each formed so as to penetrate from either one of the first front surface and the first back surface toward the other and electrically connecting the plurality of first front-surface electrodes with the plurality of first back-surface electrodes, respectively; (d) after the step of (c), arranging a second adhesive material on the first back surface of the first semiconductor chip and on a surface of the first adhesive material exposed from the first semiconductor chip; (e) after the step of (d), mounting a second semiconductor chip on the first semiconductor chip via the second adhesive material such that a second front surface of the second semiconductor chip faces the first back surface of the first semiconductor chip, and electrically connecting the plurality of first back-surface electrodes with the plurality of second front-surface electrodes, respectively, the second semiconductor chip having the second front surface, the plurality of second front-surface electrodes formed on the second front surface, and a second back surface opposite to the second front surface; and (f) after the step of (e), sealing the first surface of the wiring board, the first semiconductor chip, and the second semiconductor chip with resin, wherein the second semiconductor chip has a planar size larger than a planar size of the first semiconductor chip, and, wherein, after the step of (e) and before the step of (f), a space between the first surface of the wiring board and a portion of the second semiconductor chip not overlapping the first semiconductor chip is filled with the first and second adhesive materials.
2. The method of manufacturing the semiconductor device according to claim 1,
wherein, in the step of (f), the first surface of the wiring board, the first semiconductor chip, and the second semiconductor chip are sealed by arranging the wiring board in a forming mold and supplying the resin into the forming mold, and the resin is molded by the forming mold.
3. The method of manufacturing the semiconductor device according to claim 2,
wherein the first semiconductor chip mounted in the step of (c) has a thickness thinner than a thickness of the second semiconductor chip mounted in the step of (e).
4. The method of manufacturing the semiconductor device according to claim 1,
wherein, in the step of (e), the second semiconductor chip is mounted on a second chip mount part larger in a planar size than a first chip mount part where the first semiconductor chip is mounted, and, wherein, in the step of (b), an outer edge part of the first adhesive material is arranged at a position closer to an outer edge part of the second chip mount part than an outer edge part of the first chip mount part.
5. The method of manufacturing the semiconductor device according to claim 1,
wherein, in the step of (f), a plurality of filler particles are contained in the resin for sealing the first surface of the wiring board, the first semiconductor chip, and the second semiconductor chip.
6. The method of manufacturing the semiconductor device according to claim 5,
wherein filler particles having a particle diameter larger than a separated distance between the second semiconductor chip and the first surface of the wiring board are contained in the plurality of filler particles.
7. The method of manufacturing the semiconductor device according to claim 1,
wherein, in the step of (e), a plurality of the second semiconductor chips are laminated on the first semiconductor chip, and wherein, a space between the plurality of second semiconductor chips is sealed with a sealing body different from the sealing body.
8. The method of manufacturing the semiconductor device according to claim 7,
wherein, in the step of (f), the resin for sealing the first surface of the wiring board and the first semiconductor chip has a viscosity higher than a viscosity of the sealing body for sealing the space between the plurality of second semiconductor chips.
9. The method of manufacturing the semiconductor device according to claim 1,
wherein the first adhesive material arranged on the first chip mount part of the first surface of the wiring board is a film-shaped adhesive material.
10. The method of manufacturing the semiconductor device according to claim 1,
wherein, in the step of (d), the second adhesive material is arranged by coating the first back surface of the first semiconductor chip and the surface of the first adhesive material exposed from the first semiconductor chip with the second adhesive material of a paste type.
11. The method of manufacturing the semiconductor device according to claim 1,
wherein, in the step of (c), more than half of a side surface of the first semiconductor chip on the front surface side of the first semiconductor chip is covered with the first adhesive material.
12. A method of manufacturing a semiconductor device comprising the steps of:
(a) providing a wiring board having a first surface, a plurality of bonding leads formed on the first surface, a second surface opposite to the first surface, and a plurality of lands formed on the second surface and electrically connected with the plurality of bonding leads, respectively; (b) arranging a first adhesive material on the first surface of the wiring board; (c) after the step of (b), mounting a first semiconductor chip on the first surface of the wiring board via the first adhesive material such that a first front surface of the first semiconductor chip faces the first surface of the wiring board, and electrically connecting the plurality of bonding leads with a plurality of first front-surface electrodes, the first semiconductor chip having the first front surface, the plurality of first front-surface electrodes formed on the first front surface, a plurality of first circuits formed on the first front surface side and electrically connected with the plurality of first front-surface electrodes, respectively, a first back surface opposite to the first front surface, a plurality of first back-surface electrodes formed on the first back surface, and a plurality of through electrodes each formed so as to penetrate from either one of the first front surface and the first back surface toward the other and electrically connecting the plurality of first front-surface electrodes with the plurality of first back-surface electrodes, respectively; (d) after the step of (c), arranging a second adhesive material on the first back surface of the first semiconductor chip and on a surface of the first adhesive material exposed from the first semiconductor chip; (e) after the step of (d), mounting a second semiconductor chip on the first semiconductor chip via the second adhesive material such that a second front surface of the second semiconductor chip faces the first back surface of the first semiconductor chip, and electrically connecting the plurality of first back-surface electrodes with a plurality of second front-surface electrodes, respectively, the second semiconductor chip having the second front surface, the plurality of second front-surface electrodes formed on the second front surface, a plurality of second circuits formed on the second front surface side and electrically connected with the plurality of second front-surface electrodes, respectively, and a second back surface opposite to the second front surface; and (f) after the step of (e), sealing the first surface of the wiring board, the first semiconductor chip, and the second semiconductor chip with resin, wherein the plurality of second circuits include a storage circuit which stores data communicated with the first semiconductor chip via a plurality of first protruding electrodes provided between the first semiconductor chip and the second semiconductor chip, wherein the plurality of first circuits include a control circuit which controls operation of the storage circuit of the second semiconductor chip via a plurality of second protruding electrodes provided between the first semiconductor chip and the second semiconductor chip, wherein the second semiconductor chip has a planar size larger than a planar size of the first semiconductor chip, and, wherein, after the step of (e) and before the step of (f), a space between the first surface of the wiring board and a portion of the second semiconductor chip not overlapping the first semiconductor chip is filled with the first and second adhesive materials.
13. A method of manufacturing a semiconductor device comprising the steps of
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