Office Action 1: Non-Final Rejection (2024-04-05)
Rejection types: 103 - Obviousness

CLAIMS:
CLAIMS

1\. A method of assembling a flipchip semiconductor package, comprising:
placing a semiconductor die having circuitry electrically coupled to bond pads having bumps with solder paste thereon onto bonding features of a package substrate; and
arc welding using a biased electrode having a tip spaced apart from the solder paste, wherein electrical current generated by the arc welding melts the solder paste to provide a solder connection.

2\. The method of claim 1, wherein the bumps comprise solder balls or pillars.

3\. The method of claim 1, wherein the method excludes a solder reflow step.

4\. The method of claim 1, further comprising flux washing after applying the electrical current.

5\. The method of claim 1, wherein an arc welding apparatus used for the method includes a plurality of the biased electrodes, and wherein the arc welding simultaneously forms a plurality of the solder connections.

6\. The method of claim 1, wherein the package substrate comprises a leadframe, and
wherein the bonding features comprise leads.
7\. The method of claim 1, wherein the tip is positioned at an angle from 150 to 450 relative to a normal drawn from a top surface of the package substrate.

8\. The method of claim 1, wherein the bond pads are all positioned along a periphery of the semiconductor die.

9\. The method of claim 1, wherein the electrical current is in a range from 60mA to 200mA.

10\. The method of claim 1, wherein the electrical current is applied for a time between 0.5 msec and 1.3 msec.

11\. The method of claim 1, wherein an arc welding apparatus used for the method includes a substrate holder having the package substrate thereon that is grounded, and wherein the package substrate is grounded by the substrate holder.

12\. The method of claim 1, wherein there is solder flux on the bonding features.

13\. A method of assembling a semiconductor package, comprising:
placing a semiconductor die having circuitry electrically coupled to electrical contacts with solder paste thereon onto bonding features of a package substrate; and arc welding using a biased electrode having a tip spaced apart from the solder paste, wherein electrical current generated by the arc welding melts the solder paste to provide a solder connection.

14\. The method of claim 13, wherein the package substrate comprises a leadframe, and
wherein the bonding features comprise leads.

15\. The method of claim 13, wherein the tip is positioned at an angle from 150 to 450 relative to a normal drawn from a top surface of the package substrate.

16\. The method of claim 13, wherein the bond pads are all positioned along a periphery of the semiconductor die.

17\. The method of claim 13, wherein the electrical current is in a range from 60mA to 200mA.

18\. The method of claim 13, wherein the electrical current is applied for a time between 0.5 msec and 1.3 msec.

19\. The method of claim 13, wherein the bumps comprise pillars.
20\. The method of claim 13, wherein the bumps comprise solder balls.

21\. The method of Claim 13, wherein the method excludes a solder reflow step.

22\. A method of assembling a semiconductor package, comprising:
placing a semiconductor die having circuitry electrically coupled to electrical contacts with solder paste thereon onto bonding features of a package substrate; and
generating an arc using a biased electrode having a tip spaced apart from the solder paste to melt the solder paste to provide a solder connection. T101535US0110 T101535US017 T101535US018 T101535US019

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/27/2022 is in compliance with the provisions 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
Paragraph [0008], line 1, states: optional “orc” welding… It appears the Applicant intended to write --optional arc welding--.
Paragraph [0019], line 1, states: pillars or “sider” balls. It appears the Applicant intended to write --pillars or solder balls--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA  35 U.S.C. 102 and 103 (or as subject to pre-AIA  35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA  to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5-7, 9-10, 13-15, 17- 18, 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teshima, Kouichi (US 6280858) in view of Blankenship, George et al. (US 20050133488).
As for claim(s) 1, 13, and 22, a method of assembling a flip chip semiconductor package, comprising:
Placing a semiconductor die (substrate package (15) Teshima) having circuitry electrically coupled to bond pads (bond pads (12) Teshima) having bumps (bonding portion (13) Teshima)
With solder paste (tin-zinc alloy solder [col 10 line 66-68] Teshima) thereon onto bonding features ((12) and (13) Teshima) of a package substrate (package substrate 11 Teshima); and
Arc welding ([col 9 lines 19-22] Teshima) using a biased electrode (electrode (12) Blankenship et al.) having a tip spaced ((58) tip, inherent for arc welding, Fig. 4, Blankenship et al.) apart from the solder paste (tin-zinc alloy solder [col 10 line 66-68] Teshima) wherein
Electrical current generated by the arc welding (obvious) melts the solder paste (tin-zinc alloy solder ([col 10 line 66-68] Teshima) to provide a solder connection (bonding portion/solder bump (13), [col 11, lines 19-21] Teshima).
(Regarding claim(s) 1, 13 and 22, the use of arc welding in semiconductors is known in the art. Teshima discloses component (15) as an arc welded substrate to be flip chip mounted to another device. See [(SOIC) Small Outline Integrated Circuit, col 9, line 60, Teshima]. Specifically, Teshima teaches placing a semiconductor die having circuitry electrically coupled to bond pads having bumps with solder paste thereon onto bonding features of a package substrate utilizing arc welding, wherein electrical current generated by arc welding produces heat which melts the solder paste, providing a solder connection.  This process of using heat generated by the electrical current of arc welding is obvious, as this fusion method and resulting bond in the presence of solder, is well known in the art. It is also understood that when bonding materials by arc welding, the tip of the welding apparatus is apart from the workpiece and does not typically touch the solder, as the heat generated from the electrical charge, may be optimized to a temperature sufficient to melt solder paste without direct contact, given the relatively low melting point of solder. Hence, Teshima does not explicitly teach a biased electrode having a tip spaced apart from the solder paste.However, Blankenship et al. teaches a biased electrode having a tip spaced apart from the workpiece as illustrated in Fig. 4. And since it is known in the art to use arc welding for bonding semiconductor components, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to combine the arc welding device of Blankenship et al. with the semiconductor fabrication scope and method of Teshima to fabricate a device that conforms to the design specification disclosed by the Applicant in the claims.)
As for claim(s) 3 and 21, the method of claims 1 and 13 respectively, wherein
The method excludes a solder reflow step (obvious).
(Regarding claim(s) 3 and 21, Teshima teaches the methods of claims 1 and 13 for coupling bonding features through the process of arc welding.
Teshima does not explicitly teach the exclusion of a solder reflow step. It is well known in the art that the electrical current generated by the arc welding process both melts and bonds solder paste to provide a solder connection and would obviously, if not inherently exclude a solder reflow step as the arc created by the electric current flowing between the two electrodes, creates such an intense heat that the bonding of components would not need a reflow step. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was filed that the solder reflow step would be excluded from the device fabrication process.)
As for claim(s) 5, the method of claim 1, wherein
An arc welding ([0023], Blankenship et al.) apparatus used for the method includes a plurality ([0023], Blankenship et al.) of the biased electrodes (tandem electrodes (12), (14), (16), (18), Blankenship et al.), and wherein
The arc welding (0023, Blankenship et al.) simultaneously forms a plurality of the solder connections (Abstract, Blankenship).
(Regarding claim(s) 5, Blankenship teaches an arc welding apparatus and method including a plurality of biased electrodes programmed to cooperatively and systemically, execute a number of simultaneous operations in tandem. Specifically in [0023], Blankenship et al. employs a method wherein “ tandem electrodes 12, 14, 16, 18 are arranged linearly and spaced apart along a direction designated the x-direction in FIGS. 1 and 2, and move together along the x-direction at a selected travel speed..” such that the electrodes 12, 14, 16, 18 move along the designated x-direction simultaneously, at a common travel speed welding joints of a workpiece, thereby forming a plurality of the solder connections.Teshima teaches the forming of a plurality of solder connections as disclosed in Claim 15 of Teshima. …”electrically conductive bonding member comprises a plurality of bumps or leads provided in a high-density mounting.” The Examiner has shown in the previous rejection of claims 1, 13, and 22 above, that the arc welding apparatus of Blankenship et al. may be used in the method of assembling a flip chip semiconductor package disclosed in Teshima.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to combine the inventions of Teshima and Blankenship et al. to fabricate a device that conforms to the design specification, i.e. an arc welding apparatus and method including a plurality of the biased electrodes, wherein the arc welding device of Blankenship et al. simultaneously forms a plurality of solder connections on the plurality of bumps of Teshima).
As for claims 6 and 14, the method of claims 1 and 13 respectively, wherein
The package substrate comprises a lead frame (obvious), and wherein
The bonding features comprise leads (obvious).
(Regarding claim(s) 6 and 14, Teshima teaches a package substrate with bonding features. Teshima does not explicitly teach that the package substrate comprises a lead frame wherein the bonding features comprise leads. However, in col. 9 lines 64-67 and col. 10, lines 1-4, Teshima discloses that the methods of the claim are applicable to the field of mounting substrates. “For example, that field includes bonding of IC package and CPU for use in semiconductor field”. This disclosure would then obviously include the utilization of a package substrate comprising a lead frame, wherein the bonding features comprise leads, since IC packages involve the integration of circuits within lead frames.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was filed that the package substrate would comprise a lead frame, wherein the bonding features comprise leads, so as to use an industrially tested and accepted device/process/material.)
As for claim(s) 7 and 15, the method of claims 1 and 13 respectively, wherein
The tip is positioned at an angle from 15 degrees to 45 degrees (optimize) relative to a normal drawn from a top surface of the package substrate.
(Regarding claim(s) 7 and 15, Teshima does not explicitly teach an optimized tip position angle from 15 degrees to 45 degrees relative to a normal drawn from a top surface of the package substrate. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to optimize the angular position of the arc welding tip, so as to ensure the current is delivered to the optimized location for bonding device components. Since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233.
The Applicant has not shown that the specific discovery of a tip position angle from 15 degrees to 45 degrees relative to a normal drawn from a top surface of the package substrate is somehow unique, novel or cutting edge in the fabrication method and use of the disclosed device.
As for claim(s) 9 and 17, the method of claims 1 and 13 respectively, wherein
The electrical current is in a range from 60 mA to 200 mA (optimize).
(Regarding claim(s) 9 and 17, Teshima  teaches arc welding, which inherently requires the use of an electrical current. Teshima does not explicitly teach the use of an electrical current  in a range from 60 mA to 200 mA.
However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to use an electrical current strong enough to melt the solder, bonding the components, i.e., a current in a range from 60 mA to 200 mA. Since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233.) The Applicant has not shown that the specific discovery of an electrical current in a range from 60 mA to 200 mA is somehow unique, novel or cutting edge in the fabrication method and use of the disclosed device.
As for claims 10 and 18, the method of claims 1 and 13 respectively, wherein
The electrical current is applied for a time between 0.5 msec and 1.3 msec (optimize).
(Regarding claim(s) 10 and 18, Teshima  teaches arch welding with inherently requires the use of an electrical current applied to a work piece for an amount of time.
Teshima does not explicitly teach that the electrical current is applied for a time between 0.5 msec and 1.3 msec.
However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to apply the electrical current long enough to sufficiently melt the solder and bond the components. i.e., for a time between 0.5 msec and 1.3 msec. Since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233.)
The Applicant has not shown that the specific discovery of an electrical current applied for a time between 0.5 msec and 1.3 msec is somehow unique, novel or cutting edge in the fabrication method and use of the disclosed device.
Claim(s) 11, is/are rejected under 35 U.S.C. 103 as being unpatentable over Teshima, Kouichi (US 6280858) in view of Blankenship, George et al. (US 20050133488), as applied to claim 1, and further in view of Kato et al. (US 20060069466) and Azzalina, Brandon (“The Importance of Grounding While Welding”).
As for claim(s) 11, the method of claim 1, wherein
An arc welding apparatus (Fig. 17, Kato et al.) used for the method includes a substrate holder (robot holding- Claim 1, Kato et al.) having the package substrate thereon that is grounded, and wherein
The package substrate (workpiece, [0017], Kato et al. ) is grounded by the substrate holder (robot holding- Claim 1, Kato et al.).
(Regarding claim(s) 11 Teshima teaches the application of arc welding to electrically couple components to a substrate.
Teshima does not explicitly teach the use of a substrate holder having the package substrate thereon that is grounded, wherein the package substrate is grounded by the substrate holder.
However, Kato et al. does teach an arc welding apparatus/method utilizing a substrate holder and having the package substrate thereon that is grounded. The use of an arc welding apparatus, employing a tip that never actually touches the solder, would benefit from a feature of the device that would securely hold the workpiece in place, and that would ground the workpiece given the electrical charge emitted from the welding method. The Examiner has already discussed in the rejection of claims 1, 13 and 22 above, the combination of the arc welding device of Blankenship et al. with the semiconductor fabrication scope and method of Teshima. It would follow that the implementation of the substrate holder of Kato et al. could be combined with the Teshima and Blankenship inventions.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to ground the apparatus and the package substrate, so as to both secure and ground the package substrate to protect against shock hazards. See Azzalina, Brandon, “The Importance of Grounding While Welding”
Claim(s) 2, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teshima, Kouichi (US 6280858) in view of Blankenship, George et al. (US 20050133488), as applied to claims 1 and 13, and in further view of Ho et al. (US 20200350285).
As for claim(s) 2, 19 and 20, the methods of claims 1 and 13 respectively, wherein
The bumps comprise solder balls (Annotated Fig. 2B, Teshima below) or pillars ([0037] Ho et al.)
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(Regarding claim(s) 2, 19 and 20 Teshima teaches the use of solder bumps to bond the substrate to the circuit.
Although the bonding portions of the Teshima Annotated Fig. 2B above do appear to be comprised of solder balls or pillars, Teshima does not explicitly teach the use of solder balls or pillars. Nonetheless, Ho et al. does teach the use of bumps comprising solder balls or pillars ([0037]). Solder balls require a small amount of solder and flux to be placed on the component such that the component can then be connected to the circuit board with a minimum of production heating.Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to bond the package components using solder balls or pillars, so as to use an industrially tested and accepted device/process/material.)
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teshima, Kouichi (US 6280858) in view of Blankenship, George et al. (US 20050133488), as applied to claim 1, and in further view of Shimizu et al. (US 20190335119).
As for claim 4, the method of claim 1, further comprising
Flux washing (flux washing, [131] Shimizu et al.) after applying the electrical current.
(Regarding claim(s) 4, Teshima  teaches the use of flux.
Teshima does not explicitly teach a flux washing process after applying the electrical current. However, it is known in the art that the arc welding process of Teshima melts solder paste to provide a solder connection. Hence, it would follow that solder may drip or pool on the substrate necessitating the need for cleaning of the substrate to ensure the proper functioning of the device.
Shimizu et al. does teach flux washing in [0131] after previously applying the electrical current  disclosed in [0130].  Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to remove excess flux by using a washer, a dryer, and a flux washing solution after the solder bonding step was completed, such as disclosed in the methods of Shimizu et al., so as to use a functioning, industrially tested and accepted device/process/material.)
Claim(s) 8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teshima, Kouichi (US 6280858) in view of Blankenship, George et al. (US 20050133488), as applied to claims 1 and 13, and in further view of Matsuura et al. (US 20210111136).
As for claims 8 and 16, the method of claim 1, wherein
The bond pads (bond pad 181 Matsuura et al.) are all positioned along a periphery of the semiconductor die (substrate package (15) Teshima).
(Regarding claim(s) 8 and 16, Teshima  teaches a semiconductor die.
Teshima does not explicitly teach that the bond pads are all positioned along a periphery of the semiconductor die. Nonetheless, Matsuura et al. discloses in [0004] “bond pads connected to nodes in the circuitry all arranged along the periphery of the die”. Bonding pads along the periphery of the die would improve bonding efficiency during angle rotation of the device arm and tip, giving better access to tightly spaced bonding components within reach of the arm and electric arc emanating from the welding tip.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to position the bond pads along a periphery of the semiconductor die, so as to fabricate a device that conforms to the design specification.)
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teshima, Kouichi (US 6280858) in view of Blankenship, George et al. (US 20050133488), as applied to claims 1, and in further view of Bayot, Arthur (US 20050133573).
As for claim 12, the method of claim 1, wherein
There is solder flux on the bonding features ([0020] Bayot).
(Regarding claim(s) 12, Teshima teaches the use of solder flux on the bonding features.
Teshima does not explicitly teach the use of solder flux on the bonding features, though the use of flux for semiconducting mounting is disclosed in [col 2, lines 8-24, Teshima].However, Bayot teaches solder flux on the bonding features. It is well known in the art to use flux when soldering as it increases the wetting ability of the solder, causing it to flow more uniformly over surfaces without beading up. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to use solder flux on the bonding features of Teshima, as disclosed by Bayot, to prevent oxidation of the materials and allow for a free flow of solder over joints.
Conclusion


NEXT OFFICE ACTION: DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/27/2022, is in compliance with the provisions 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant’s arguments, see pages 7 - 9 of argument, filed  08/27/2024, with respect to independent claims 1, 13 and 22 have been fully considered and are not persuasive.  The previous rejection of claims 1-10, 12-22 has been upheld. Claims 11 is cancelled. No new claims have been added. With regard to the rejection of record based on previously considered prior art, Teshima, U.S. Patent No. 6280858 (Teshima),  Blankenship et al., U.S. Patent Publication No. 2005/0 133488 (Blankenship), Kato et al., U.S. Patent Publication No. 2006/0069466 (Kato), Azzalina (The Importance of Grounding While Welding) (Azzalina), Ho et al., U.S. Patent Publication No. 2020/0350285 (Ho), Shimizu et al., U.S. Patent Publication No. 2019/0335119 (Shimizu) , Matsuura et al., U.S. Patent Publication No. 2021/0111136 (Matsuura) and Bayot, U.S. Patent Publication No. 2005/0133573 (Bayot).
The Examiner respectfully disagrees with the argument on page 7 relative to the ground disclosed by Kato. The argument is not persuasive. The Examiner has used the reference Kato in conjunction with Azzalina in a 35 USC § 103 rejection to address the limitation “an arc welding apparatus used includes a substrate holder having the package substrate thereon that is grounded, and wherein the package substrate is grounded by the substrate holder.” See page 11 of Examiner’s Non-Final rejection.
The Examiner notes that the Applicant has remarked “ The office action admitted Teshima did not disclose the above-referenced features. Blankenship is cited to disclose the components of the arc welding apparatus. Azzalina is cited to disclose the impact of grounding for welding.” Azzalina has not been only cited for the impact of grounding during welding. Azzalina is cited also to disclose the likelihood that, though the Teshima device does not explicitly teach grounding, the Teshima device would be grounded as anyone skilled in the art would expect an arc welded electrical device to be grounded by the substrate holder.
The Applicant does not address the rejection of the remaining claims.  Therefore, the previous rejections detailed in office action 04/05/2024 remains. Though claims 1, 5, 13, 19, 20, and 22 were amended.  The independent claims 1, 13, and 22 stand rejected. See Examiner’s arguments above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 5-7, 9-10, 13-15, 17- 18, 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teshima, Kouichi (US 6280858) in view of Kato; Tetsuaki (US 20060069466); Azzalina, Brandon (“The Importance of Grounding While Welding”) and further in view of Blankenship, George et al. (US 20050133488).
As for claim(s) 1, 13, and 22, a method of assembling a flip chip semiconductor package, comprising:
Placing a semiconductor die (substrate package (15) Teshima) having circuitry electrically coupled to bond pads (bond pads (12) Teshima) having bumps (bonding portion (13) Teshima)
With solder paste (tin-zinc alloy solder [col 10 line 66-68] Teshima) thereon onto bonding features ((12) and (13) Teshima) of a package substrate (package substrate 11 Teshima); and
Arc welding ([col 9 lines 19-22] Teshima) using a biased electrode (electrode (12) Blankenship et al.) having a tip spaced ((58) tip, inherent for arc welding, Fig. 4, Blankenship et al.) apart from the solder paste (tin-zinc alloy solder [col 10 line 66-68] Teshima) wherein
Electrical current generated by the arc welding (obvious) melts the solder paste (tin-zinc alloy solder ([col 10 line 66-68] Teshima) to provide a solder connection (bonding portion/solder bump (13), [col 11, lines 19-21] Teshima).
Wherein an arc welding apparatus (Fig. 17, Kato et al.) used includes a substrate holder (robot holding- Claim 1, Kato et al.) having the package substrate thereon that is grounded, and wherein
The package substrate (workpiece, [0017], Kato et al. ) is grounded by the substrate holder (robot holding- Claim 1, Kato et al.).
(Regarding claim(s) 1, 13 and 22, the use of arc welding in semiconductors is known in the art. Teshima discloses component (15) as an arc welded substrate to be flip chip mounted to another device. See [(SOIC) Small Outline Integrated Circuit, col 9, line 60, Teshima]. Specifically, Teshima teaches placing a semiconductor die having circuitry electrically coupled to bond pads having bumps with solder paste thereon onto bonding features of a package substrate utilizing arc welding, wherein electrical current generated by arc welding produces heat which melts the solder paste, providing a solder connection.  This process of using heat generated by the electrical current of arc welding is obvious, as this fusion method and resulting bond in the presence of solder, is well known in the art. It is also understood that when bonding materials by arc welding, the tip of the welding apparatus is apart from the workpiece and does not typically touch the solder, as the heat generated from the electrical charge, may be optimized to a temperature sufficient to melt solder paste without direct contact, given the relatively low melting point of solder. Hence, Teshima does not explicitly teach a biased electrode having a tip spaced apart from the solder paste.However, Blankenship et al. teaches a biased electrode having a tip spaced apart from the workpiece as illustrated in Fig. 4. And since it is known in the art to use arc welding for bonding semiconductor components, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to combine the arc welding device of Blankenship et al. with the semiconductor fabrication scope and method of Teshima to fabricate a device that conforms to the design specification disclosed by the Applicant in the claims.)
Also, Teshima teaches the application of arc welding to electrically couple components to a substrate. Teshima does not explicitly teach the use of a substrate holder having the package substrate thereon that is grounded, wherein the package substrate is grounded by the substrate holder.
However, Kato et al. does teach an arc welding apparatus/method utilizing a substrate holder and having the package substrate thereon that is grounded. The use of an arc welding apparatus, employing a tip that never actually touches the solder, would benefit from a feature of the device that would securely hold the workpiece in place, and that would ground the workpiece given the electrical charge emitted from the welding method. The Examiner has already discussed in the rejection of claims 1, 13 and 22 above, the combination of the arc welding device of Blankenship et al. with the semiconductor fabrication scope and method of Teshima. It would follow that the implementation of the substrate holder of Kato et al. could be combined with the Teshima and Blankenship inventions.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to ground the apparatus and the package substrate, so as to both secure and ground the package substrate to protect against shock hazards. See Azzalina, Brandon, “The Importance of Grounding While Welding”)
As for claim(s) 3 and 21, the method of claims 1 and 13 respectively, wherein
The method excludes a solder reflow step (obvious).
(Regarding claim(s) 3 and 21, Teshima teaches the methods of claims 1 and 13 for coupling bonding features through the process of arc welding.
Teshima does not explicitly teach the exclusion of a solder reflow step. It is well known in the art that the electrical current generated by the arc welding process both melts and bonds solder paste to provide a solder connection and would obviously, if not inherently exclude a solder reflow step as the arc created by the electric current flowing between the two electrodes, creates such an intense heat that the bonding of components would not need a reflow step. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was filed that the solder reflow step would be excluded from the device fabrication process.)
As for claim(s) 5, the method of claim 1, wherein
An arc welding ([0023], Blankenship et al.) apparatus used for the method includes a plurality ([0023], Blankenship et al.) of the biased electrodes (tandem electrodes (12), (14), (16), (18), Blankenship et al.), and wherein
The arc welding (0023, Blankenship et al.) simultaneously forms a plurality of the solder connections (Abstract, Blankenship).
(Regarding claim(s) 5, Blankenship teaches an arc welding apparatus and method including a plurality of biased electrodes programmed to cooperatively and systemically, execute a number of simultaneous operations in tandem. Specifically in [0023], Blankenship et al. employs a method wherein “ tandem electrodes 12, 14, 16, 18 are arranged linearly and spaced apart along a direction designated the x-direction in FIGS. 1 and 2, and move together along the x-direction at a selected travel speed..” such that the electrodes 12, 14, 16, 18 move along the designated x-direction simultaneously, at a common travel speed welding joints of a workpiece, thereby forming a plurality of the solder connections.Teshima teaches the forming of a plurality of solder connections as disclosed in Claim 15 of Teshima. …”electrically conductive bonding member comprises a plurality of bumps or leads provided in a high-density mounting.” The Examiner has shown in the previous rejection of claims 1, 13, and 22 above, that the arc welding apparatus of Blankenship et al. may be used in the method of assembling a flip chip semiconductor package disclosed in Teshima.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to combine the inventions of Teshima and Blankenship et al. to fabricate a device that conforms to the design specification, i.e. an arc welding apparatus and method including a plurality of the biased electrodes, wherein the arc welding device of Blankenship et al. simultaneously forms a plurality of solder connections on the plurality of bumps of Teshima).
As for claims 6 and 14, the method of claims 1 and 13 respectively, wherein
The package substrate comprises a lead frame (obvious), and wherein
The bonding features comprise leads (obvious).
(Regarding claim(s) 6 and 14, Teshima teaches a package substrate with bonding features. Teshima does not explicitly teach that the package substrate comprises a lead frame wherein the bonding features comprise leads. However, in col. 9 lines 64-67 and col. 10, lines 1-4, Teshima discloses that the methods of the claim are applicable to the field of mounting substrates. “For example, that field includes bonding of IC package and CPU for use in semiconductor field”. This disclosure would then obviously include the utilization of a package substrate comprising a lead frame, wherein the bonding features comprise leads, since IC packages involve the integration of circuits within lead frames.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was filed that the package substrate would comprise a lead frame, wherein the bonding features comprise leads, so as to use an industrially tested and accepted device/process/material.)
As for claim(s) 7 and 15, the method of claims 1 and 13 respectively, wherein
The tip is positioned at an angle from 15 degrees to 45 degrees (optimize) relative to a normal drawn from a top surface of the package substrate.
(Regarding claim(s) 7 and 15, Teshima does not explicitly teach an optimized tip position angle from 15 degrees to 45 degrees relative to a normal drawn from a top surface of the package substrate. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to optimize the angular position of the arc welding tip, so as to ensure the current is delivered to the optimized location for bonding device components. Since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233.
The Applicant has not shown that the specific discovery of a tip position angle from 15 degrees to 45 degrees relative to a normal drawn from a top surface of the package substrate is somehow unique, novel or cutting edge in the fabrication method and use of the disclosed device.
As for claim(s) 9 and 17, the method of claims 1 and 13 respectively, wherein
The electrical current is in a range from 60 mA to 200 mA (optimize).
(Regarding claim(s) 9 and 17, Teshima  teaches arc welding, which inherently requires the use of an electrical current. Teshima does not explicitly teach the use of an electrical current  in a range from 60 mA to 200 mA.
However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to use an electrical current strong enough to melt the solder, bonding the components, i.e., a current in a range from 60 mA to 200 mA. Since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233.) The Applicant has not shown that the specific discovery of an electrical current in a range from 60 mA to 200 mA is somehow unique, novel or cutting edge in the fabrication method and use of the disclosed device.
As for claims 10 and 18, the method of claims 1 and 13 respectively, wherein
The electrical current is applied for a time between 0.5 msec and 1.3 msec (optimize).
(Regarding claim(s) 10 and 18, Teshima  teaches arch welding with inherently requires the use of an electrical current applied to a work piece for an amount of time.
Teshima does not explicitly teach that the electrical current is applied for a time between 0.5 msec and 1.3 msec.
However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to apply the electrical current long enough to sufficiently melt the solder and bond the components. i.e., for a time between 0.5 msec and 1.3 msec. Since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233.)
The Applicant has not shown that the specific discovery of an electrical current applied for a time between 0.5 msec and 1.3 msec is somehow unique, novel or cutting edge in the fabrication method and use of the disclosed device.
Claim(s) 2, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teshima, Kouichi (US 6280858) in view of Kato; Tetsuaki (US 20060069466); Azzalina, Brandon (“The Importance of Grounding While Welding”) and Blankenship, George et al. (US 20050133488), as applied to claims 1 and 13, and in further view of Ho et al. (US 20200350285).
As for claim(s) 2, 19 and 20, the methods of claims 1 and 13 respectively, wherein
The bumps comprise solder balls (Annotated Fig. 2B, Teshima below) or pillars ([0037] Ho et al.)
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(Regarding claim(s) 2, 19 and 20 Teshima teaches the use of solder bumps to bond the substrate to the circuit.
Although the bonding portions of the Teshima Annotated Fig. 2B above do appear to be comprised of solder balls or pillars, Teshima does not explicitly teach the use of solder balls or pillars. Nonetheless, Ho et al. does teach the use of bumps comprising solder balls or pillars ([0037]). Solder balls require a small amount of solder and flux to be placed on the component such that the component can then be connected to the circuit board with a minimum of production heating.Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to bond the package components using solder balls or pillars, so as to use an industrially tested and accepted device/process/material.)
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teshima, Kouichi (US 6280858) in view of Kato; Tetsuaki (US 20060069466); Azzalina, Brandon (“The Importance of Grounding While Welding”), and Blankenship, George et al. (US 20050133488), as applied to claim 1, and in further view of Shimizu et al. (US 20190335119).
As for claim 4, the method of claim 1, further comprising
Flux washing (flux washing, [131] Shimizu et al.) after applying the electrical current.
(Regarding claim(s) 4, Teshima  teaches the use of flux.
Teshima does not explicitly teach a flux washing process after applying the electrical current. However, it is known in the art that the arc welding process of Teshima melts solder paste to provide a solder connection. Hence, it would follow that solder may drip or pool on the substrate necessitating the need for cleaning of the substrate to ensure the proper functioning of the device.
Shimizu et al. does teach flux washing in [0131] after previously applying the electrical current  disclosed in [0130].  Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to remove excess flux by using a washer, a dryer, and a flux washing solution after the solder bonding step was completed, such as disclosed in the methods of Shimizu et al., so as to use a functioning, industrially tested and accepted device/process/material.)
Claim(s) 8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teshima, Kouichi (US 6280858) in view of Kato; Tetsuaki (US 20060069466); Azzalina, Brandon (“The Importance of Grounding While Welding”) and Blankenship, George et al. (US 20050133488), as applied to claims 1 and 13, and in further view of Matsuura et al. (US 20210111136).
As for claims 8 and 16, the method of claim 1, wherein
The bond pads (bond pad 181 Matsuura et al.) are all positioned along a periphery of the semiconductor die (substrate package (15) Teshima).
(Regarding claim(s) 8 and 16, Teshima  teaches a semiconductor die.
Teshima does not explicitly teach that the bond pads are all positioned along a periphery of the semiconductor die. Nonetheless, Matsuura et al. discloses in [0004] “bond pads connected to nodes in the circuitry all arranged along the periphery of the die”. Bonding pads along the periphery of the die would improve bonding efficiency during angle rotation of the device arm and tip, giving better access to tightly spaced bonding components within reach of the arm and electric arc emanating from the welding tip.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to position the bond pads along a periphery of the semiconductor die, so as to fabricate a device that conforms to the design specification.)
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teshima, Kouichi (US 6280858) in view of Kato; Tetsuaki (US 20060069466) and Blankenship, George et al. (US 20050133488), as applied to claims 1, and in further view of Bayot, Arthur (US 20050133573).
As for claim 12, the method of claim 1, wherein
There is solder flux on the bonding features ([0020] Bayot).
(Regarding claim(s) 12, Teshima teaches the use of solder flux on the bonding features.
Teshima does not explicitly teach the use of solder flux on the bonding features, though the use of flux for semiconducting mounting is disclosed in [col 2, lines 8-24, Teshima].However, Bayot teaches solder flux on the bonding features. It is well known in the art to use flux when soldering as it increases the wetting ability of the solder, causing it to flow more uniformly over surfaces without beading up. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to use solder flux on the bonding features of Teshima, as disclosed by Bayot, to prevent oxidation of the materials and allow for a free flow of solder over joints.
Conclusion
THIS ACTION IS MADE FINAL.  Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action.  In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action.  In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.

CITED REFERENCE SUMMARIES: Ref US6280858B1: [content unavailable]
Ref US20190335119A1: Claims:
An imaging device module comprising: a substrate having a first primary surface, a second primary surface, and an outer edge continuous to the first primary surface and the second primary surface and including a plurality of conductor layers and a plurality of insulating layers; a solid state imaging device attached to the first primary surface; a frame attached to the first primary surface so as to surround a circumference of the solid state imaging device; and a light transmitting member fixed on the frame, wherein a relationship of Tgp>Tgf, Î±f1<Î±PCB1, and (Tgp-To)ÃÎ±PCB1<(Tgf-To)ÃÎ±f1+(Tgp-Tgf)ÃÎ±f2 or a relationship of Tgp<Tgf, Î±PCB1<Î±f1, and (Tgf-To)ÃÎ±f1<(Tgp-To)ÃÎ±PCB1+(Tgf-Tgp)ÃÎ±PCB2 is satisfied, wherein a linear expansion coefficient in an in-plane direction of the substrate at a temperature below a glass transition temperature Tgp of the substrate is denoted as Î±PCB1, a linear expansion coefficient in the in-plane direction of the substrate at a temperature above the glass transition temperature Tgp is denoted as Î±PCB2, a linear expansion coefficient of the frame at a temperature below a glass transition temperature Tgf of the frame is denoted as Î±f1, a linear expansion coefficient of the frame at a temperature above the glass transition temperature Tgf is denoted as Î±f2, and a room temperature is denoted as To.
a substrate having a first primary surface, a second primary surface, and an outer edge continuous to the first primary surface and the second primary surface and including a plurality of conductor layers and a plurality of insulating layers;
a solid state imaging device attached to the first primary surface;
a frame attached to the first primary surface so as to surround a circumference of the solid state imaging device; and
a light transmitting member fixed on the frame,
wherein a relationship of
Î±f1<Î±PCB1, and
(Tgp-To)ÃÎ±PCB1<(Tgf-To)ÃÎ±f1+(Tgp-Tgf)ÃÎ±f2
or a relationship of
Î±PCB1<Î±f1, and
(Tgf-To)ÃÎ±f1<(Tgp-To)ÃÎ±PCB1+(Tgf-Tgp)ÃÎ±PCB2
is satisfied, wherein a linear expansion coefficient in an in-plane direction of the substrate at a temperature below a glass transition temperature Tgp of the substrate is denoted as Î±PCB1, a linear expansion coefficient in the in-plane direction of the substrate at a temperature above the glass transition temperature Tgp is denoted as Î±PCB2, a linear expansion coefficient of the frame at a temperature below a glass transition temperature Tgf of the frame is denoted as Î±f1, a linear expansion coefficient of the frame at a temperature above the glass transition temperature Tgf is denoted as Î±f2, and a room temperature is denoted as To.
The imaging device module according to claim 1 , wherein the glass transition temperature Tgp is higher than the glass transition temperature Tgf, and the frame is molded on the substrate.
The imaging device module according to claim 1 , wherein the linear expansion coefficient Î±PCB1 and the linear expansion coefficient Î±f1 are smaller than a linear expansion coefficient Î±L in an in-plane direction of the light transmitting member and larger than a linear expansion coefficient Î±c in an in-plane direction of the solid state imaging device.
The imaging device module according to claim 1 , wherein the substrate is a printed board containing a prepreg.
The imaging device module according to claim 1 , wherein the frame contains a resin.
The imaging device module according to claim 1 , wherein the solid state imaging device is attached by an adhesive agent to the first primary surface.
The imaging device module according to claim 6 , wherein the adhesive agent is a resin having rubber elasticity.
The imaging device module according to claim 1 , wherein the frame covers the outer edge of the substrate.
The imaging device module according to claim 1 , wherein the frame does not cover the outer edge of the substrate.
An imaging system comprising a signal processing device that processes pixel signals output from the solid state imaging device according to claim 1 .
The imaging system according to claim 10 , further comprising: a detection unit that detects motion of the imaging system; and an actuator that displaces the imaging device module based on a signal from the detection unit.
a detection unit that detects motion of the imaging system; and
an actuator that displaces the imaging device module based on a signal from the detection unit.
The imaging system according to claim 10 , wherein the solid state imaging device comprises a plurality of pixels, wherein each of the pixels has a plurality of photoelectric conversion portions, and wherein the signal processing device processes the pixel signals generated by the plurality of photoelectric conversion portions, respectively, and acquires information based on a distance from the solid state imaging device to a subject.
wherein the solid state imaging device comprises a plurality of pixels,
wherein each of the pixels has a plurality of photoelectric conversion portions, and
wherein the signal processing device processes the pixel signals generated by the plurality of photoelectric conversion portions, respectively, and acquires information based on a distance from the solid state imaging device to a subject.
An imaging device package comprising: a substrate having a first primary surface, a second primary surface, and an outer edge continuous to the first primary surface and the second primary surface and including a plurality of conductor layers and a plurality of insulating layers; and a frame attached to the first primary surface, wherein a relationship of Tgp>Tgf, Î±f1<Î±PCB1, and (Tgp-To)ÃÎ±PCB1<(Tgf-To)ÃÎ±f1+(Tgp-Tgf)ÃÎ±f2 or a relationship of Tgp<Tgf, Î±PCB1<Î±f1, and (Tgf-To)ÃÎ±f1<(Tgp-To)ÃÎ±PCB1+(Tgf-Tgp)ÃÎ±PCB2 is satisfied, wherein a linear expansion coefficient in an in-plane direction of the substrate at a temperature below a glass transition temperature Tgp of the substrate is denoted as Î±PCB1, a linear expansion coefficient in the in-plane direction of the substrate at a temperature above the Tgp is denoted as Î±PCB2, a linear expansion coefficient of the frame at a temperature below a glass transition temperature Tgf of the frame is denoted as Î±f1, a linear expansion coefficient of the frame at a temperature above the Tgf is denoted as Î±f2, and a room temperature is denoted as To.
a substrate having a first primary surface, a second primary surface, and an outer edge continuous to the first primary surface and the second primary surface and including a plurality of conductor layers and a plurality of insulating layers; and
a frame attached to the first primary surface,
is satisfied, wherein a linear expansion coefficient in an in-plane direction of the substrate at a temperature below a glass transition temperature Tgp of the substrate is denoted as Î±PCB1, a linear expansion coefficient in the in-plane direction of the substrate at a temperature above the Tgp is denoted as Î±PCB2, a linear expansion coefficient of the frame at a temperature below a glass transition temperature Tgf of the frame is denoted as Î±f1, a linear expansion coefficient of the frame at a temperature above the Tgf is denoted as Î±f2, and a room temperature is denoted as To.
A manufacturing method of an imaging device module, the manufacturing method comprising steps of: preparing a substrate having a first primary surface, a second primary surface, and an outer edge continuous to the first primary surface and the second primary surface and including a plurality of conductor layers and a plurality of insulating layers; attaching a solid state imaging device to the first primary surface; attaching a frame to the first primary surface so as to surround a circumference of the solid state imaging device; and attaching a light transmitting member on the frame, wherein a relationship of Tgp>Tgf, Î±f1<Î±PCB1, and (Tgp-To)ÃÎ±PCB1<(Tgf-To)ÃÎ±f1+(Tgp-Tgf)ÃÎ±f2 or a relationship of Tgp<Tgf, Î±PCB1<Î±f1, and (Tgf-To)ÃÎ±f1<(Tgp-To)ÃÎ±PCB1+(Tgf-Tgp)ÃÎ±PCB2 is satisfied, wherein a linear expansion coefficient in an in-plane direction of the substrate at a temperature below a glass transition temperature Tgp of the substrate is denoted as Î±PCB1, a linear expansion coefficient in the in-plane direction of the substrate at a temperature above the glass transition temperature Tgp is denoted as Î±PCB2, a linear expansion coefficient of the frame at a temperature below a glass transition temperature Tgf of the frame is denoted as Î±f1, a linear expansion coefficient of the frame at a temperature above the glass transition temperature Tgf is denoted as Î±f2, and a room temperature is denoted as To, and wherein the step of attaching the frame to the substrate is performed at a temperature between the glass transition temperature Tgp and the glass transition temperature Tgf.
preparing a substrate having a first primary surface, a second primary surface, and an outer edge continuous to the first primary surface and the second primary surface and including a plurality of conductor layers and a plurality of insulating layers;
attaching a solid state imaging device to the first primary surface;
attaching a frame to the first primary surface so as to surround a circumference of the solid state imaging device; and
attaching a light transmitting member on the frame,
is satisfied, wherein a linear expansion coefficient in an in-plane direction of the substrate at a temperature below a glass transition temperature Tgp of the substrate is denoted as Î±PCB1, a linear expansion coefficient in the in-plane direction of the substrate at a temperature above the glass transition temperature Tgp is denoted as Î±PCB2, a linear expansion coefficient of the frame at a temperature below a glass transition temperature Tgf of the frame is denoted as Î±f1, a linear expansion coefficient of the frame at a temperature above the glass transition temperature Tgf is denoted as Î±f2, and a room temperature is denoted as To, and
wherein the step of attaching the frame to the substrate is performed at a temperature between the glass transition temperature Tgp and the glass transition temperature Tgf.
The manufacturing method of the imaging device module according to claim 14 , wherein the glass transition temperature Tgp is higher than the glass transition temperature Tgf, and the frame is molded on the substrate at a temperature between the glass transition temperature Tgp and the glass transition temperature Tgf.
Ref US20210111136A1: [content unavailable]
Ref US20050133573A1: Claims:
A method of forming solder contacts on a substrate, the method comprising: providing a substrate having a plurality conductive site and a plurality of solder contacts, each solder contact including a top surface and a bottom surface, the bottom surface of each solder contact being connected to one of the plurality of conductive sites; at least partially immersing the plurality of solder contacts in a layer of solder flux to provide solder flux on each solder contact; and reflowing the solder contacts, which are provided with solder flux, to improve the adhesion of the solder contacts to the conductive sites.
providing a substrate having a plurality conductive site and a plurality of solder contacts, each solder contact including a top surface and a bottom surface, the bottom surface of each solder contact being connected to one of the plurality of conductive sites;
at least partially immersing the plurality of solder contacts in a layer of solder flux to provide solder flux on each solder contact; and
reflowing the solder contacts, which are provided with solder flux, to improve the adhesion of the solder contacts to the conductive sites.
The method of claim 1 , the reflowed solder contacts each having a substantially spherical shape.
The method of claim 1 , the at least partial immersion of the plurality of solder contacts further comprising: providing a pick-up apparatus having a receiving end to which a surface of the substrate is held; providing a flux plate having a recess formed therein, the recess containing a substantially uniform layer of solder flux; positioning the receiving end of the pick-up apparatus relative to the flux plate to at least partially immerse the solder contacts in the substantially uniform layer of solder flux.
providing a pick-up apparatus having a receiving end to which a surface of the substrate is held;
providing a flux plate having a recess formed therein, the recess containing a substantially uniform layer of solder flux;
positioning the receiving end of the pick-up apparatus relative to the flux plate to at least partially immerse the solder contacts in the substantially uniform layer of solder flux.
The method of claim 3 , further comprising using a squeegee to form the substantially uniform layer of solder flux.
The method of claim 4 , the surface of the substrate being held to the receiving end of the apparatus by a vacuum.
The method of claim 1 , the solder flux being provided on the top surfaces of the solder contacts.
The method of claim 1 , the substrate comprising a portion of a ball grid array package.
A method of forming solder contacts on a substrate, the method comprising: providing a substrate having a plurality conductive sites; adhering a plurality of preformed solder ball to the plurality of conductive sites, such that each solder ball adheres to one of the plurality of conductive sites; reflowing the plurality of solder balls to form a plurality solder contacts, each solder contact including a top surface and a bottom surface, the bottom surface of each solder contact being connected to one of the plurality of conductive sites; at least partially immersing the plurality of solder contacts in a layer of solder flux to provide solder flux on each solder contact; and reflowing the solder contacts, which are provided with solder flux, to improve the adhesion of the solder contacts to the conductive sites.
providing a substrate having a plurality conductive sites;
adhering a plurality of preformed solder ball to the plurality of conductive sites, such that each solder ball adheres to one of the plurality of conductive sites;
reflowing the plurality of solder balls to form a plurality solder contacts, each solder contact including a top surface and a bottom surface, the bottom surface of each solder contact being connected to one of the plurality of conductive sites;
The method of claim 8 , the plurality of solder balls being adhered to the plurality of conductive sites with solder flux.
The method of claim 8 , the reflowed solder contacts each having a substantially spherical shape.
The method of claim 8 , the substrate comprising a portion of a ball grid array package.
The method of claim 8 , the immersion of the top surfaces of the plurality of solder contacts further comprising: providing a pick-up apparatus having a receiving end to which a surface of the substrate is held; providing a flux plate having a recess formed therein, the recess containing a substantially uniform layer of solder flux; positioning the receiving end of the pick-up apparatus relative to the flux plate to immerse the solder contacts in the substantially uniform layer of solder flux.
positioning the receiving end of the pick-up apparatus relative to the flux plate to immerse the solder contacts in the substantially uniform layer of solder flux.
The method of claim 12 , further comprising using a squeegee to form the substantially uniform layer of solder flux.
The method of claim 13 , the surface of the substrate being held to the receiving end of the apparatus by a vacuum.
The method of claim 1 , the solder flux being supplied to the recess through an opening in the squeegee.
A method for improving the adhesion of solder contacts on a substrate, the method comprising: providing a flux plate including a recess containing a substantially uniform layer of solder flux, providing a substrate having a plurality conductive site and a plurality of solder contacts, each solder contact including a top surface and a bottom surface, the bottom surface of each solder contact being connected to one of the plurality of conductive sites; at least partially immersing the plurality of solder contacts in the solder flux to provide solder flux on each solder contact; and reflowing the solder contacts, which are provided with the solder flux, to improve the adhesion of the solder contacts to the conductive sites.
providing a flux plate including a recess containing a substantially uniform layer of solder flux,
at least partially immersing the plurality of solder contacts in the solder flux to provide solder flux on each solder contact; and
reflowing the solder contacts, which are provided with the solder flux, to improve the adhesion of the solder contacts to the conductive sites.
The method of claim 16 , the at least partial immersion of the plurality of solder contacts further comprising: providing a pick-up apparatus having a receiving end to which a surface of the substrate is held; positioning the receiving end of the pick-up apparatus relative to the flux plate to immerse the solder contacts in the substantially uniform layer of solder flux.
The method of claim 17 , further comprising using a squeegee to form the substantially uniform layer of solder flux.
The method of claim 17 , the surface of the substrate being held to the receiving end of the apparatus by a vacuum.
Ref US20200350285A1: [content unavailable]
Ref US20050133488A1: [content unavailable]
Ref US20060069466A1: Claims:
A method for controlling a trajectory of a robot when a plurality of robots are operated by cooperative control, the plurality of robots including a leading robot having a work tool and at least one tracking robot holding a workpiece to be processed by the work tool, the method comprising: controlling the position and the orientation of the tracking robot corresponding to the change of the position and the orientation of the leading robot such that the position and the orientation of a first tool coordinate system set on the leading robot moves along a desired trajectory on a second tool coordinate system set on the tracking robot.
controlling the position and the orientation of the tracking robot corresponding to the change of the position and the orientation of the leading robot such that the position and the orientation of a first tool coordinate system set on the leading robot moves along a desired trajectory on a second tool coordinate system set on the tracking robot.
The method as set forth in claim 1 , comprising: preparing a plurality of teaching points by teaching an operating position of each of the leading robot and the tracking robot; calculating the interpolative position and the interpolative orientation of the first tool coordinate system of the leading robot by interpolating the position and the orientation of the first coordinate system at the teaching points of the leading robot at every interpolative time during a playback operation; determining the relative position and the relative orientation of the first tool coordinate system of the leading robot to the second tool coordinate system of the tracking robot at every interpolative time by interpolating the relative position and the relative orientation of the first tool coordinate system at the teaching point; calculating the interpolative position and the interpolative orientation of the second tool coordinate system of the tracking robot based on the interpolative position and the interpolative orientation of the first tool coordinate system of the leading robot and the relative position and the relative orientation of the first tool coordinate system of the leading robot at every interpolative time; and controlling each joint of the leading robot and the tracking robot such that the positions and 
[Truncated to input limit]