Office Action 1: Non-Final Rejection (2024-08-06)
Rejection types: 102 - Lack of Novelty, 103 - Obviousness, 112 - Written Description/Enablement

CLAIMS:
WHAT IS CLAIMED IS:

1\. A logic gate comprising at least two phase change memory - PCM - cells, said at least two PCM cells having a high resistance phase and a low resistance phase, said at least two PCM cells being connected at a common connection and further having at least one input for an input logic state, wherein a logic output for the gate comprises a phase of an output one of said at least two phase change memory cells following provision of said input logic state.

2\. The logic gate of claim 1, configured for a predetermined logic operation by switching said output one of said at least two PCM cells to a predetermined one of said high resistance and said low resistance phases.

3\. The logic gate of claim 1 or claim 2, configured for a predetermined logic operation by presetting said input logic state to a specified member of the group consisting of a set pulse and a reset pulse.

4\. The logic gate of claim 3, wherein said set pulse and said reset pulse each have a duration and a level, and wherein the duration of the set pulse is longer than the duration of the reset pulse and the level of the set pulse is lower than the level of the reset pulse.

5\. The logic gate of claim 4, wherein the set pulse is configured to raise a temperature of the cell to a crystallization temperature and the reset pulse is configured to raise the temperature of the cell to a melting temperature,

6\. The logic gate of any one of the preceding claims, comprising two of said at least two PCM cells connected between a word line and respective bit lines, which said at least two PCM cells serve as inputs to the gate, a third PCM cell being connected between said word line and ground serving as the output for the gate.

7\. The logic gate of claim 6, wherein the output is preswitched to the low resistance phase, and wherein said input logic state is set to a reset pulse to provide a NOR or a NAND gate.

8\. The logic gate of claim 6, wherein the output is preswitched to the high resistance phase, and the input logic pulse is set to a set pulse to provide an OR gate.

9\. The logic gate of any one of claims 1 to 5, comprising two of said at least two PCM cells.

10\. The logic gate of claim 9, wherein the output is preswitched to the low resistive state and the input logic pulse is set to a reset pulse, the gate thereby providing a NOT gate.

11\. The logic gate of claim 9, wherein the output is preswitched to the high resistive state and the input logic pulse is set to a set pulse, to provide a copy function.

12\. The logic gate of claim 9, wherein the output is preswitched to the low resistive state and the input logic pulse is set to a reset pulse.

13\. The logic gate of claim 9, wherein the output is preswitched to the high resistive state and the input logic pulse is set to a set pulse, thereby to provide an OR gate.

14\. The logic gate of any one of claims 1 to 5, comprising two of said at least two PCM cells connected at a common node to a resistor.

15\. The logic gate of claim 14, wherein the input logic pulse is set to a reset pulse, to provide a N\[MP function.

16\. The logic gate of claim 14, wherein the input logic pulse is set to a set pulse to provide IMP or NOR functions.

17\. The logic gate of any one of claims 1 to 5, wherein three of said at least two PCM cells are connected between respective inputs and a common node, the common node being connected to a resistance.

18\. The logic gate of claim 17, wherein the output is initialized to the low resistive state and the input logic pulse is set to a reset pulse, to provide NAND and NOR functionality.

19\. The logic gate of claim 17, wherein the output is initialized to the high resistive state and the input logic pulse is set to a set pulse, to provide NAND, NOR and XOR functionality.

20\. The logic gate of claim 17, wherein the output is initialized to the high resistive state and the input logic pulse is set to a set pulse, to provide NIMP functionality.

21\. An electronic data storage device comprising phase change memory cells, some of said phase change memory cells comprising logic gates according to any one of the preceding claims.

22\. An electronic memory block comprising phase change memory cells for memory storage and further phase change memory cells forming logic gates.

23\. A method of carrying out a logic function using at least two phase change memory cells connected at a common connection and having predetermined set and reset pulses, the method comprising:
placing one of the memory cells in a predetermined one of first and second phases; and
selecting one of said predeternined set and reset pulses as a logic input pulse.

OFFICE ACTION:
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Specification
35 U.S.C. 112(a) or pre-AIA  35 U.S.C.  112, requires the specification to be written in “full, clear, concise, and exact terms.” The specification is replete with terms which are not clear, concise and exact. The specification should be revised carefully in order to comply with 35 U.S.C. 112(a) or pre-AIA  35 U.S.C.  112. Examples of some unclear, inexact or verbose terms used in the specification are:
Page 10 line 15 “three PCM devices 112 and 114 and ground” and page 11 line 1 “node of the three PCM devices 132 and 134 and ground”. It is unclear to one of common knowledge in the art at the time the invention was filed to understand the ground can be a PCM device.
Claim Rejections - 35 USC § 112
Claims 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections.  See MPEP § 2172.01.  The omitted structural cooperative relationships are: Claim 17 line 2 states “three of said at least two PCM cells”, it is unclear to one of common understanding in the art at the time of the filing this limitation, it can be understood to claim have two of the at least three PCM cells.
Claims 18 thru 20 are rejected based upon their relationship to claim 17.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA  35 U.S.C. 102 and 103 (or as subject to pre-AIA  35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA  to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 9, 14, 21, and 23 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Miao U.S. Pub 2015/0236697.
With regards to claim 1. Miao teaches a logic gate comprising at least two phase change memory - PCM – cells (as shown in Miao figure 4), said at least two PCM cells having a high resistance phase and a low resistance phase (see Miao para [0036]), said at least two PCM cells being connected at a common connection (301 and 302 commonly connected) and further having at least one input for an input logic state (305), wherein a logic output for the gate comprises a phase of an output one of said at least two phase change memory cells following provision of said input logic state (see Miao para [0035-0037]).
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With regards to claim 2. Miao discloses the logic gate of claim 1, and Miao also teaches configured for a predetermined logic operation by switching said output one of said at least two PCM cells to a predetermined one of said high resistance and said low resistance phases (see Miao para [0035-0037]).
With regards to claim 3. Miao discloses the logic gate of claim 1, and Miao also teaches configured for a predetermined logic operation by presetting said input logic state to a specified member of the group consisting of a set pulse and a reset pulse (see Miao para [0035-0038]).
With regards to claim 4. Miao discloses the logic gate of claim 3, and Miao also teaches wherein said set pulse and said reset pulse each have a duration and a level, and wherein the duration of the set pulse is longer than the duration of the reset pulse and the level of the set pulse is lower than the level of the reset pulse (see Miao para [0039]).
With regards to claim 9. Miao discloses the logic gate of claim1, and Miao also teaches comprising two of said at least two PCM cells (as shown in Miao figure 4, item 301 and 302).
With regards to claim 14. Miao discloses the logic gate of claim 1, and Miao also teaches comprising two of said at least two PCM cells connected at a common node to a resistor (as shown in Miao figure 4, item 301 and 302 connected to 304).
With regards to claim 21. Miao teaches an electronic data storage device comprising phase change memory cells (see Miao para [0007]), some of said phase change memory cells comprising logic gates according to claim1 (see the rejection of claim 1 above).
With regards to claim 23. Miao teaches a method of carrying out a logic function using at least two phase change memory cells connected at a common connection (as shown in Miao figure 4) and having predetermined set and reset pulses (see Miao para [0036-0040]), the method comprising:
placing one of the memory cells in a predetermined one of first and second phases (see Miao para [0036-0040]); and
selecting one of said predetermined set and reset pulses as a logic input pulse (see Miao para [0036-0040]).
Claim 22 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim U.S. Pub 2013/0105756.
With regards to claim 22. Kim teaches an electronic memory block comprising phase change memory cells for memory storage (see Kim para [0127] and as shown in figure 20, item 220 which is a memory) and further phase change memory cells forming logic gates (see Kim para [0127]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA  35 U.S.C. 102 and 103 (or as subject to pre-AIA  35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA  to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 is rejected under 35 U.S.C. 103 as being unpatentable over Maio U.S. Pub 2015/0236697 as applied to claim 4 above, and further in view of Gong U.S. Pub 2022/0173309.
With regards to claim 5. Miao discloses the logic gate of claim 4, but Miao does not teach wherein the set pulse is configured to raise a temperature of the cell to a crystallization temperature and the reset pulse is configured to raise the temperature of the cell to a melting temperature.
However Gong does teach the set pulse is configured to raise a temperature of the cell to a crystallization temperature and the reset pulse is configured to raise the temperature of the cell to a melting temperature (see Gong para [0022-0024]). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the undisclosed temperature requirements for a set and reset of the phase change memory of Miao with the temperature requirements of a phase change device to change state of Gong to provide a Phase Change Material that is reduced in size and lower power that can be switched between high and low resistance (see Gong para [0001 and 0021]).
Claims 6-8, 10-13, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Maio U.S. Pub 2015/0236697 as applied to claims 1, 9 and 14 above, and further in view of Kvatinsky U.S. Pub.
With regards to claim 6. Miao discloses the logic gate of claim 1, but Miao does not teach comprising two of said at least two PCM cells connected between a word line and respective bit lines, which said at least two PCM cells serve as inputs to the gate, a third PCM cell being connected between said word line and ground serving as the output for the gate.
However Kvatinsky does teach two of said at least two PCM cells connected between a word line and respective bit lines, which said at least two PCM cells serve as inputs to the gate (as shown in Kvatinsky figure 10, items in1 and in2), a third PCM cell being connected between said word line and ground serving as the output for the gate (out). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the individual elements to make the circuit of Miao with the crossbar circuit providing the elements of Kvatinsky to provide a single structure that can perform multiple logic functions (see Kvatinsky para [0129-0134]).
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With regards to claim 7. Miao and Kvatinsky disclose the logic gate of claim 6, and Kvatinsky also teaches wherein the output is preswitched to the low resistance phase, and wherein said input logic state is set to a reset pulse to provide a NOR or a NAND gate (see Kvatinsky para [0099-0107]).
With regards to claim 8. Miao and Kvatinsky disclose the logic gate of claim 6, and Kvatinsky also teaches wherein the output is preswitched to the high resistance phase, and the input logic pulse is set to a set pulse to provide an OR gate (see Kvatinsky para [0147-0153]).
With regards to claim 10. Miao discloses the logic gate of claim 9, but Miao does not teach wherein the output is preswitched to the low resistive state and the input logic pulse is set to a reset pulse, the gate thereby providing a NOT gate.
However Kvatinsky does teach the output is preswitched to the low resistive state and the input logic pulse is set to a reset pulse, the gate thereby providing a NOT gate (see Kvatinsky para [0092-0096]). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the individual elements to make the NOT circuit of Miao with the crossbar circuit providing the NOT elements of Kvatinsky to provide a single structure that can perform multiple logic functions (see Kvatinsky para [0129-0134]).
With regards to claim 11. Miao discloses the logic gate of claim 9, but Miao does not teach wherein the output is preswitched to the high resistive state and the input logic pulse is set to a set pulse, to provide a copy function.
However Kvatinsky discloses the claimed invention except for the output is preswitched to the high resistive state and the input logic pulse is set to a set pulse, to provide a copy function.  It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to understand that Kvatinsky figure 1A performs either the NOT or COPY function by setting the output device to high resistive state verses the low resistive state since the examiner takes Official Notice of the equivalence of the circuit to perform a NOT operation and the circuit to perform a COPY function for their use in the phase change device art and the selection of any of these known equivalents to use the circuit to perform a NOT or COPY operation would be within the level of ordinary skill in the art.
With regards to claim 12. Miao discloses the logic gate of claim 9, but Miao does not teach wherein the output is preswitched to the low resistive state and the input logic pulse is set to a reset pulse.
However Kvatinsky does teach the output is preswitched to the low resistive state and the input logic pulse is set to a reset pulse (see Kvatinsky para [0092-0096]). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the individual elements to make the resistive states of Miao with the crossbar circuit providing the elements with the resistive states of Kvatinsky to provide a single structure that can perform multiple logic functions (see Kvatinsky para [0129-0134]).
With regards to claim 13. Miao discloses the logic gate of claim 9, but Miao does not teach wherein the output is preswitched to the high resistive state and the input logic pulse is set to a set pulse, thereby to provide an OR gate.
However Kvatinsky does teach the output is preswitched to the high resistive state and the input logic pulse is set to a set pulse, thereby to provide an OR gate (see Kvatinsky para [0147-0152]). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the individual elements to make the NOT circuit of Miao with the crossbar circuit providing the NOT elements of Kvatinsky to provide a single structure that can perform multiple logic functions (see Kvatinsky para [0129-0134]).
With regards to claim 16. Miao discloses the logic gate of claim 14, and Miao also teaches wherein the input logic pulse is set to a set pulse to provide IMP or NOR functions.
However Kvatinsky does teach the input logic pulse is set to a set pulse to provide IMP or NOR functions (see Kvatinsky para [0099-0107] for the NOR function). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the individual elements to make the NOT circuit of Miao with the crossbar circuit providing the NOT elements of Kvatinsky to provide a single structure that can perform multiple logic functions (see Kvatinsky para [0129-0134]).
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Maio U.S. Pub 2015/0236697 as applied to claim 14 above, and further in view of Mahmoudi EP 2736044 A1.
With regards to claim 15. Miao discloses the logic gate of claim 14, but Miao does not teach wherein the input logic pulse is set to a reset pulse, to provide a NIMP function.
However Mahmoudi teaches the input logic pulse is set to a reset pulse, to provide a NIMP function (see Mahmoudi para [0044-0051 and 0059]). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the individual elements to make the PCM circuit of Miao with the NIMP function of the PCM elements of Mahmoudi to provide a single structure that can perform any Boolean function which includes IMP and NIMP functions (see Mahmoudi para [0017-0018]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Miao U.S. Patent 9,473,137 – Boolean functions for resistive elements
Lee U.S. Pub 2014/0169068 – Resistive device memory blocks
Gaillardo U.S. Pub 2012/0236626 – Resistive device memory blocks

APPLICANT REBUTTAL: REMARKS
This application is a National Phase Application of PCT Patent Application No. PCT/IL2021/050403 having International filing date of April 7, 2021.
Reconsideration of the above-identified application in view of the amendments above and the remarks following is respectfully requested.
Claims 1 - 23 are in this Application and have been rejected. Claims 1, 17 and 23 have been amended herewith without prejudice. Claim 5 is cancelled without prejudice.
Amendments To The Specification
The paragraphs pointed out by the Examiner are clarified.
Amendments To The Claims
35 U.S.C. § 112 Rejections
Claim 17 is amended to clarify the three cells.
35 U.S.C. § 102/3 Rejections
Claim 1 is rejected over Miao.
Claim 1 is amended in two respects. The first point is to define more clearly the gate inputs as the logic inputs.
The second point is to specify that the set and reset pulses a) serve as logic input pulses and b) are set to crystallize or melt the material. The feature is taken from original claim 5, which is now cancelled.
Examiner cites Gong, which teaches a reset pulse above the melt temperature and a set pulse below the crystallization temperature. However in Gong, the set and reset pulses are distinct from the logic inputs. Examiner is referred to paragraph 26, which refers to heater 408. What is described is a heating effect via a heater that effects the phase of the material. An insulator layer 406 separates between the heating current to the heater and the logic signals in the device itself -
"as the heater current path is not directly mixed with the PCM current flow" - Gong - passage bridging pages 2 and 3.
That is to say an auxiliary signal is used, not the actual logic signals that appear on the gates of the devices. However the wording of claim 1 as amended requires the logic signals appearing at the device gates to themselves change the phases.
Thus consideration of Gong by the skilled person would not suggest the invention as claimed, but rather an indirect system in which one circuit provides the logic signals to the devices and an auxiliary circuit changes the phases using a heater.
Thus there is no straightforward application of the set and reset signals of Gong to the circuit of Maio to arrive at the present invention since Gong uses a heater circuit insulated from the PCM device itself, in order to carry out the phase change.
Thus the combination of Miao and Gong fails to teach or suggest:
A logic gate comprising at least two phase change memory - PCM - cells, said at least two PCM cells having a high resistance phase and a low resistance phase, said at least two PCM cells being connected at a common connection and further the logic gate having at least one gate input for an input logic state, wherein a logic output for the logic gate comprises a phase of an output one of said at least two phase change memory cells, the phase of the output one of said at least two phase change memory cells forming the logic output following provision of said input logic state at said gate input, the logic gate being configured to react to a set pulse and a reset pulse as logic input pulses, wherein the set pulse is configured to raise a temperature of the cell to a crystallization temperature and the reset pulse is configured to raise the
temperature of the cell to a melting temperature.
The same features are added to independent claim 23, which is believed to be allowable for the same reasons.
Conclusion

NEXT OFFICE ACTION: Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Arguments
Applicant's arguments filed 11/6/2024 have been fully considered but they are not persuasive. The applicant asserts that the prior art Miao U.S. Pub 2015/0236697 and further in view of Gong U.S. Patent 2022/0173309 do not teach “The first point is to define more clearly the gate inputs as the logic inputs. The second point is to specify that the set and reset pulses a) serve as logic input pulses and b) are set to crystallize or melt the material”. The examiner respectfully disagrees.
Concerning the first point Miao in paragraphs 0035 thru 0037 teach each phase change memory (PCM) receive logic inputs and Gong in paragraphs 0027 thru 0028 teaches logic inputs.
Concerning the second point Miao does teach in paragraph 0039 a SET being a longer duration with lower amplitude and the reset being shorter duration with higher amplitude inputs as described in the instant application specification page 5 lines 11 thru 13 but Miao is absent teaching how the inputs control the temperature to create the change for the logic output. Gong does teach the use of a heat source to create the crystallize or melt conditions using input voltage and duration as described in the instant application specification page 5 lines 11 thru 13 to provide that one of common knowledge in the art at the time the invention was filed would understand that the desired input voltage with pulse width would create the desired output from the PCM memory.
Claim Objections
Claims 17 is objected to because of the following informalities: Claim 17 lines 1-2 have the following limitation “wherein three PCM cells, said three PCM cells including”.  This is not proper English when stating the PCM cells claimed in claim 1 can be a group of three PCM cells. For examination purposes this shall be interpreted as “wherein the PCM cells may consist of three PCM cells, said three PCM cells including” Appropriate correction is required.
Claims 18 thru 20 are objected to based upon their relationship to claim 17.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA  35 U.S.C. 102 and 103 (or as subject to pre-AIA  35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA  to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 22 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim U.S. Pub 2013/0105756.
With regards to claim 22. Kim teaches an electronic memory block comprising phase change memory cells for memory storage (see Kim para [0127] and as shown in figure 20, item 220 which is a memory) and further phase change memory cells forming logic gates (see Kim para [0127]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA  35 U.S.C. 102 and 103 (or as subject to pre-AIA  35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA  to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9, 14, 21, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Miao U.S. Pub 2015/0236697, and further in view of Gong U.S. Pub 2022/0173309.
With regards to claim 1. Miao teaches a logic gate comprising at least two phase change memory - PCM – cells (as shown in Miao figure 4), said at least two PCM cells having a high resistance phase and a low resistance phase (see Miao para [0036]), said at least two PCM cells being connected at a common connection (301 and 302 commonly connected) and further the logic gate having at least one gate input for an input logic state (305), wherein a logic gate output for the gate comprises a phase of an output one of said at least two phase change memory cells, the phase of the output one of said at least two phase change memory cells forming the logic output following provision of said input logic state at said gate input (see Miao para [0035-0037] figure 4 is a logic circuit performing a logic operation), the logic gate being configured to react to a set pulse and a reset pulse as logic input pulses (see Miao para [0040]), but Miao does not teach wherein the set pulse is configured to raise a temperature of the cell to a crystallization temperature and the reset pulse is configured to raise the temperature of the cell to a melting temperature.
However Gong does teach the set pulse is configured to raise a temperature of the cell to a crystallization temperature and the reset pulse is configured to raise the temperature of the cell to a melting temperature (as shown in Gong figures 2 and 4 and see para [0024 and 0028]; Figure 2 is a graph showing how the inputs in figure 4 use the heater to provide the desired output). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the undisclosed temperature requirements for a set and reset of the phase change memory of Miao with the temperature requirements of a phase change device to change state of Gong to provide a Phase Change Material that is reduced in size and lower power that can be switched between high and low resistance (see Gong para [0001 and 0021]).
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With regards to claim 2. Miao and Gong disclose the logic gate of claim 1, and Miao also teaches configured for a predetermined logic operation by switching said output one of said at least two PCM cells to a predetermined one of said high resistance and said low resistance phases (see Miao para [0035-0037]).
With regards to claim 3. Miao and Gong disclose the logic gate of claim 1, and Miao also teaches configured for a predetermined logic operation by presetting said input logic state to a specified member of the group consisting of a set pulse and a reset pulse (see Miao para [0035-0038]).
With regards to claim 4. Miao and Gong disclose the logic gate of claim 3, and Miao also teaches wherein said set pulse and said reset pulse each have a duration and a level, and wherein the duration of the set pulse is longer than the duration of the reset pulse and the level of the set pulse is lower than the level of the reset pulse (see Miao para [0039]).
With regards to claim 9. Miao and Gong disclose the logic gate of claim1, and Miao also teaches comprising two of said at least two PCM cells (as shown in Miao figure 4, item 301 and 302).
With regards to claim 14. Miao and Gong disclose the logic gate of claim 1, and Miao also teaches comprising two of said at least two PCM cells connected at a common node to a resistor (as shown in Miao figure 4, item 301 and 302 connected to 304).
With regards to claim 21. Miao and Gong disclose an electronic data storage device comprising phase change memory cells (see Miao para [0007]), some of said phase change memory cells comprising logic gates according to claim1 (see the rejection of claim 1 above).
With regards to claim 23. Miao teaches a method of carrying out a logic function using at least two phase change memory cells connected at a common connection (as shown in Miao figure 4) and having predetermined set and reset pulses (see Miao para [0036-0040]), the method comprising:
placing one of the memory cells in a predetermined one of first and second phases (see Miao para [0036-0040]); and
selecting one of said predetermined set and reset pulses as a logic input pulse (see Miao para [0036-0040]),
But does not teach wherein the set pulse is configured to raise a temperature of the cell to a crystallization temperature and the reset pulse is configured to raise the temperature of the cell to a melting temperature.
However Gong does teach the set pulse is configured to raise a temperature of the cell to a crystallization temperature and the reset pulse is configured to raise the temperature of the cell to a melting temperature (as shown in Gong figures 2 and 4 and see para [0024 and 0028]; Figure 2 is a graph showing how the inputs in figure 4 use the heater to provide the desired output). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the undisclosed temperature requirements for a set and reset of the phase change memory of Miao with the temperature requirements of a phase change device to change state of Gong to provide a Phase Change Material that is reduced in size and lower power that can be switched between high and low resistance (see Gong para [0001 and 0021]).
Claims 6-8, 10-13, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Miao U.S. Pub 2015/0236697 and Gong U.S. Pub 2022/0173309. as applied to claims 1, 9 and 14 above, and further in view of Kvatinsky U.S. Pub.
With regards to claim 6. Miao and Gong disclose the logic gate of claim 1, but Miao and Gong do not teach comprising two of said at least two PCM cells connected between a word line and respective bit lines, which said at least two PCM cells serve as inputs to the gate, a third PCM cell being connected between said word line and ground serving as the output for the gate.
However Kvatinsky does teach two of said at least two PCM cells connected between a word line and respective bit lines, which said at least two PCM cells serve as inputs to the gate (as shown in Kvatinsky figure 10, items in1 and in2), a third PCM cell being connected between said word line and ground serving as the output for the gate (out). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the individual elements to make the circuit of Miao with the crossbar circuit providing the elements of Kvatinsky to provide a single structure that can perform multiple logic functions (see Kvatinsky para [0129-0134]).
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With regards to claim 7. Miao, Gong, and Kvatinsky disclose the logic gate of claim 6, and Kvatinsky also teaches wherein the output is preswitched to the low resistance phase, and wherein said input logic state is set to a reset pulse to provide a NOR or a NAND gate (see Kvatinsky para [0099-0107]).
With regards to claim 8. Miao, Gong, and Kvatinsky disclose the logic gate of claim 6, and Kvatinsky also teaches wherein the output is preswitched to the high resistance phase, and the input logic pulse is set to a set pulse to provide an OR gate (see Kvatinsky para [0147-0153]).
With regards to claim 10. Miao and Gong disclose the logic gate of claim 9, but Miao and Gong do not teach wherein the output is preswitched to the low resistive state and the input logic pulse is set to a reset pulse, the gate thereby providing a NOT gate.
However Kvatinsky does teach the output is preswitched to the low resistive state and the input logic pulse is set to a reset pulse, the gate thereby providing a NOT gate (see Kvatinsky para [0092-0096]). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the individual elements to make the NOT circuit of Miao with the crossbar circuit providing the NOT elements of Kvatinsky to provide a single structure that can perform multiple logic functions (see Kvatinsky para [0129-0134]).
With regards to claim 11. Miao and Gong disclose the logic gate of claim 9, but Miao and Gong do not teach wherein the output is preswitched to the high resistive state and the input logic pulse is set to a set pulse, to provide a copy function.
However Kvatinsky discloses the claimed invention except for the output is preswitched to the high resistive state and the input logic pulse is set to a set pulse, to provide a copy function.  It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to understand that Kvatinsky figure 1A performs either the NOT or COPY function by setting the output device to high resistive state verses the low resistive state since the examiner takes Official Notice of the equivalence of the circuit to perform a NOT operation and the circuit to perform a COPY function for their use in the phase change device art and the selection of any of these known equivalents to use the circuit to perform a NOT or COPY operation would be within the level of ordinary skill in the art.
With regards to claim 12. Miao and Gong disclose the logic gate of claim 9, but Miao and Gong do not teach wherein the output is preswitched to the low resistive state and the input logic pulse is set to a reset pulse.
However Kvatinsky does teach the output is preswitched to the low resistive state and the input logic pulse is set to a reset pulse (see Kvatinsky para [0092-0096]). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the individual elements to make the resistive states of Miao with the crossbar circuit providing the elements with the resistive states of Kvatinsky to provide a single structure that can perform multiple logic functions (see Kvatinsky para [0129-0134]).
With regards to claim 13. Miao and Gong disclose the logic gate of claim 9, but Miao and Gong do not teach wherein the output is preswitched to the high resistive state and the input logic pulse is set to a set pulse, thereby to provide an OR gate.
However Kvatinsky does teach the output is preswitched to the high resistive state and the input logic pulse is set to a set pulse, thereby to provide an OR gate (see Kvatinsky para [0147-0152]). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the individual elements to make the NOT circuit of Miao with the crossbar circuit providing the NOT elements of Kvatinsky to provide a single structure that can perform multiple logic functions (see Kvatinsky para [0129-0134]).
With regards to claim 16. Miao and Gong disclose the logic gate of claim 14, but Miao and Gong do not teach wherein the input logic pulse is set to a set pulse to provide IMP or NOR functions.
However Kvatinsky does teach the input logic pulse is set to a set pulse to provide IMP or NOR functions (see Kvatinsky para [0099-0107] for the NOR function). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the individual elements to make the NOT circuit of Miao with the crossbar circuit providing the NOT elements of Kvatinsky to provide a single structure that can perform multiple logic functions (see Kvatinsky para [0129-0134]).
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Miao U.S. Pub 2015/0236697 and Gong U.S. Pub 2022/0173309 as applied to claim 14 above, and further in view of Mahmoudi EP 2736044 A1.
With regards to claim 15. Miao and Gong disclose the logic gate of claim 14, but Miao and Gong do not teach wherein the input logic pulse is set to a reset pulse, to provide a NIMP function.
However Mahmoudi teaches the input logic pulse is set to a reset pulse, to provide a NIMP function (see Mahmoudi para [0044-0051 and 0059]). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the individual elements to make the PCM circuit of Miao with the NIMP function of the PCM elements of Mahmoudi to provide a single structure that can perform any Boolean function which includes IMP and NIMP functions (see Mahmoudi para [0017-0018]).
Allowable Subject Matter
Claims 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With regards to claim 17. Miao U.S. Pub 2015/0236697, and further in view of Gong U.S. Pub 2022/0173309 teach Phase Change Memory cells forming logic circuits but along with the cited prior arts listed in the PTO-892 fail to teach the following limitations in the independent claims as follows “said three PCM cells including said at least two PCM cells are connected between respective inputs and a common node, the common node being connected to a resistance”.
Claims 18-20 are objected to based upon their dependency to claim 17.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Miao U.S. Patent 9,473,137 – Boolean functions for resistive elements
Lee U.S. Pub 2014/0169068 – Resistive device memory blocks
Gaillardo U.S. Pub 2012/0236626 – Resistive device memory blocks
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action.  Accordingly, THIS ACTION IS MADE FINAL.  See MPEP § 706.07(a).  Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action.  In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action.  In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.

CITED REFERENCE SUMMARIES: Ref US20220173309A1: Claims:
An apparatus comprising: a phase-change material; a first electrode at a first end of the phase-change material; a second electrode at a second end of the phase-change material; a heating element coupled to a least a given portion of the phase-change material between the first end and the second end; a first input terminal coupled to the heating element; a second input terminal coupled to the heating element; and an output terminal coupled to the second electrode.
a phase-change material;
a first electrode at a first end of the phase-change material;
a second electrode at a second end of the phase-change material;
a heating element coupled to a least a given portion of the phase-change material between the first end and the second end;
a first input terminal coupled to the heating element;
a second input terminal coupled to the heating element; and
an output terminal coupled to the second electrode.
The apparatus of claim 1 , wherein the first input terminal comprises a first diode comprising a first terminal and a second terminal, and a first resistive element, the second terminal of the first diode being coupled to the first resistive element, the first resistive element being coupled to the heating element.
The apparatus of claim 2 , wherein the second input terminal comprises a second diode comprising a first terminal and a second terminal, and a second resistive element, the second terminal of the second diode being coupled to the second resistive element, the second resistive element being coupled to the heating element.
The apparatus of claim 1 , further comprising an electrically insulating and thermally conducting layer disposed between the heating element and the given portion of the phase-change material.
The apparatus of claim 1 , further comprising an additional heating element coupled to another portion of the phase-change material between the first end and the second end, the additional heating element being coupled to an enable input terminal.
The apparatus of claim 5 , further comprising an electrically insulating and thermally conducting layer disposed between the additional heating element and the other portion of the phase-change material.
The apparatus of claim 1 , further comprising an enable output terminal coupled to the heating element, the enable output terminal being coupled to an enable input terminal of an additional device.
The apparatus of claim 1 , wherein the phase-change material and the heating element form at least part of a logic gate interconnected such that when one of the first and second input terminals, exclusively, is at a true logic state, the output terminal is at a true logic state.
A method comprising: providing a first voltage to a first input terminal coupled to a heating element, the heating element being coupled to at least a given portion of a phase-change material between a first end of the phase-change material and a second end of the phase-change material, the first end of the phase-change material being coupled to a first electrode, the second end of the phase-change material being coupled to a second electrode; providing a second voltage to a second input terminal coupled to the heating element; and measuring a magnitude of a voltage at an output terminal coupled to the second electrode.
providing a first voltage to a first input terminal coupled to a heating element, the heating element being coupled to at least a given portion of a phase-change material between a first end of the phase-change material and a second end of the phase-change material, the first end of the phase-change material being coupled to a first electrode, the second end of the phase-change material being coupled to a second electrode;
providing a second voltage to a second input terminal coupled to the heating element; and
measuring a magnitude of a voltage at an output terminal coupled to the second electrode.
The method of claim 9 , further comprising determining an output value of a logic gate based on the measured magnitude of the voltage at the output terminal coupled to the second electrode, wherein the first input terminal comprises a first input to the logic gate, the second input terminal comprises a second input to the logic gate, and the output terminal comprises an output of the logic gate.
The method of claim 10 , wherein providing the first voltage to the first input terminal comprises applying one or more positive voltage pulses to the first input terminal when a value of the first input is true.
The method of claim 10 , wherein providing the second voltage to the second input terminal comprises applying one or more positive voltage pulses to the second input terminal when a value of the second input is true.
The method of claim 9 , wherein the phase-change material in a first phase has a first resistivity and the phase-change material in a second phase has a second resistivity higher than the first resistivity, and further comprising, prior to providing the first voltage to the first input terminal and prior to providing the second voltage to the second input terminal, resetting the given portion of the phase-change material to the first phase.
A method of operating a logic gate, comprising: setting at least a given portion of a phase-change material to a first phase having a first resistivity in response to one of the two or more inputs to the logic gate being exclusively true; setting the given portion of the phase-change material to a second phase having a second resistivity higher than the first resistivity in response to two of the two or more inputs to the logic gate being true; and determining an output logical state of the logic gate based on a measured resistance between an input electrode coupled to a first end of the phase-change material and an output electrode coupled to a second end of the phase-change material.
setting at least a given portion of a phase-change material to a first phase having a first resistivity in response to one of the two or more inputs to the logic gate being exclusively true;
setting the given portion of the phase-change material to a second phase having a second resistivity higher than the first resistivity in response to two of the two or more inputs to the logic gate being true; and
determining an output logical state of the logic gate based on a measured resistance between an input electrode coupled to a first end of the phase-change material and an output electrode coupled to a second end of the phase-change material.
The method of claim 14 , wherein a heating element is coupled to the given portion of the phase-change material between the first end and the second end, and wherein setting the given portion of the phase-change material to the first phase comprises applying one or more positive voltage pulses to one of a first input terminal coupled to the heating element and a second input terminal coupled to the heating element.
The method of claim 15 , wherein setting the given portion of the phase-change material to the second phase comprises applying one or more positive voltage pulses to both of the first input terminal coupled to the heating element and the second input terminal coupled to the heating element.
A system comprising: two or more logic stages, each of the two or more logic stages comprising one or more logic devices; at least one of the one or more logic devices in a given one of the two or more logic stages comprising a phase-change material-based logic gate comprising a phase-change material and a heating element interconnected such that when one of first and second input terminals coupled to the heating element, exclusively, is at a true logic state, an output terminal is at a true logic state; wherein the phase-change material-based logic gate in the given logic stage comprises an enable output terminal coupling the heating element to a logic device in another one of the two or more logic stages.
two or more logic stages, each of the two or more logic stages comprising one or more logic devices;
at least one of the one or more logic devices in a given one of the two or more logic stages comprising a phase-change material-based logic gate comprising a phase-change material and a heating element interconnected such that when one of first and second input terminals coupled to the heating element, exclusively, is at a true logic state, an output terminal is at a true logic state;
wherein the phase-change material-based logic gate in the given logic stage comprises an enable output terminal coupling the heating element to a logic device in another one of the two or more logic stages.
The system of claim 17 , wherein the phase-change material-based logic gate in the given logic stage comprises an enable input terminal coupled to an additional heating element coupled to at least another portion of the phase-change material.
The system of claim 18 , wherein the enable input terminal of the phase-change material-based logic gate in the given logic stage is coupled to an enable output terminal of a logic device in a previous one of the two or more logic stages.
The system of claim 17 , wherein the enable output terminal of the phase-change material-based logic gate in the given logic stage is coupled to an enable input terminal of a logic device in a subsequent one of the two or more logic stages.
The system of claim 17 , wherein the logic device in the subsequent logic stage comprises another phase-change material-based logic gate.
The system of claim 21 , wherein the output terminal of the phase-change material-based logic gate in the given logic stage is coupled to an input to another heating element coupled to a phase-change material of the other phase-change material-based logic gate in the subsequent logic stage.
A method comprising: measuring a current at an enable output terminal of a first logic device in a first one of two or more logic stages; determining whether the measured current at the enable output terminal of the first logic device in the first logic stage exceeds a designated threshold enabling current; and triggering an enable input terminal of a second logic device in a second one of the two or more logic stages responsive to determining that the measured current at the enable output terminal of the first logic device in the first logic stage exceeds the designated threshold enabling current; wherein the second logic device comprises a phase-change material-based logic gate a phase-change material-based logic gate comprising a phase-change material and a heating element interconnected such that when one of first and second input terminals coupled to the heating element, exclusively, is at a true logic state, an output terminal is at a true logic state.
measuring a current at an enable output terminal of a first logic device in a first one of two or more logic stages;
determining whether the measured current at the enable output terminal of the first logic device in the first logic stage exceeds a designated threshold enabling current; and
triggering an enable input terminal of a second logic device in a second one of the two or more logic stages responsive to determining that the measured current at the enable output terminal of the first logic device in the first logic stage exceeds the designated threshold enabling current;
wherein the second logic device comprises a phase-change material-based logic gate a phase-change material-based logic gate comprising a phase-change material and a heating element interconnected such that when one of first and second input terminals coupled to the heating element, exclusively, is at a true logic state, an output terminal is at a true logic state.
The method of claim 23 , wherein triggering the enable input terminal of the second logic device comprises controlling application of heat to the given portion of the phase-change material from an additional heating element coupled to the given portion of the phase-change material.
The method of claim 23 , wherein the phase-change material in a first phase has a first resistivity and the phase-change material in a second phase has a second resistivity higher than the first resistivity, and wherein triggering the enable input terminal of the second logic device comprises resetting the given portion of the phase-change material to the second phase.
Ref US9473137B2: Claims:
A non-volatile Boolean logic operation circuit, comprising: a) a first resistive switching element, the first resistive switching element comprising a positive electrode and a negative electrode; and b) a second resistive switching element, the second resistive switching element comprising a positive electrode and a negative electrode;
a) a first resistive switching element, the first resistive switching element comprising a positive electrode and a negative electrode; and
b) a second resistive switching element, the second resistive switching element comprising a positive electrode and a negative electrode;
wherein: said negative electrode of said first resistive switching element operates as a first input end of said logic operation circuit and is adapted to receive a first input signal; said negative electrode of said second resistive switching element operates as a second input end of said logic operation circuit and is adapted to receive a second input signal; and said positive electrode of said second resistive switching element is connected to said positive electrode of said first resistive switching element, and a connected end thereof operates as an output end of said logic operation circuit and is adapted to output a logic operation result of the first input signal and the second input signal.
said negative electrode of said first resistive switching element operates as a first input end of said logic operation circuit and is adapted to receive a first input signal;
said negative electrode of said second resistive switching element operates as a second input end of said logic operation circuit and is adapted to receive a second input signal; and
said positive electrode of said second resistive switching element is connected to said positive electrode of said first resistive switching element, and a connected end thereof operates as an output end of said logic operation circuit and is adapted to output a logic operation result of the first input signal and the second input signal.
The circuit of claim 1 , wherein in operation, forward writing of an initial state W=1 is facilitated by applying high level to said first input end, and low level to said second input end, and reverse writing of said initial state W =1 is facilitated by applying low level to said first input end, and high level to said second input end; resistive switching of said first resistive switching element and said second resistive switching element is facilitated by inputting a signal A to said first input end, and a signal B to said second input end according to an initial state of each of said resistive switching elements, and results of said input signals A and B after logic operation are stored according to said resistive switching; outputting of a storage state of said first resistive switching element is facilitated by inputting a read voltage to said first input end and suspending said second input end, and outputting of a storage state of said second resistive switching element is facilitated by inputting said read voltage to said second input end and suspending said first input end; and said input signal A or said input signal B is a high-level signal or a low-level signal, and an amplitude of said read voltage is less than that of a voltage of each of said resistive switching elements as resistive switching occurs, namely a threshold voltage thereof.
in operation, forward writing of an initial state W=1 is facilitated by applying high level to said first input end, and low level to said second input end, and reverse writing of said initial state W =1 is facilitated by applying low level to said first input end, and high level to said second input end;
resistive switching of said first resistive switching element and said second resistive switching element is facilitated by inputting a signal A to said first input end, and a signal B to said second input end according to an initial state of each of said resistive switching elements, and results of said input signals A and B after logic operation are stored according to said resistive switching;
outputting of a storage state of said first resistive switching element is facilitated by inputting a read voltage to said first input end and suspending said second input end, and outputting of a storage state of said second resistive switching element is facilitated by inputting said read voltage to said second input end and suspending said first input end; and
said input signal A or said input signal B is a high-level signal or a low-level signal, and an amplitude of said read voltage is less than that of a voltage of each of said resistive switching elements as resistive switching occurs, namely a threshold voltage thereof.
The circuit of claim 1 , wherein an operation result of said non-volatile Boolean logic operation circuit is expressed by: L=AÂ· B Â· W Â· R +(Ä+B)Â· W Â·R+ÄÂ·BÂ·WÂ·R+(A+ B )Â·WÂ· R ; where A represents a signal input to said first input end, B represents a signal input to said second input end, W represents a write direction of initialization, and R represents a readout direction of said operation result.
The circuit of claim 1 , wherein said first resistive switching element and said second resistive switching element are memristors.
An operation method of the non-volatile Boolean logic operation circuit of claim 1 , the method comprising: 1) controlling an initial state of each of said first resistive switching element and said second resistive switching element by inputting a high-level signal or a low-level signal to said first input end, and inputting a signal having an opposite level thereto to said second input end;
1) controlling an initial state of each of said first resistive switching element and said second resistive switching element by inputting a high-level signal or a low-level signal to said first input end, and inputting a signal having an opposite level thereto to said second input end;
wherein: an initial state of said first resistive switching element being written as a high resistance state as a signal input to said first input end is high level and a signal input to said second input end is low level, and an initial state of said second resistive switching element being written as a low resistance state, and this type of writing being labeled as forward writing W=1; said initial state of said first resistive switching element being written as a low resistance state as said signal input to said first input end is low level and said signal input to said second input end is high level, and said initial state of said second resistive switching element being written as a high resistance state, and
an initial state of said first resistive switching element being written as a high resistance state as a signal input to said first input end is high level and a signal input to said second input end is low level, and an initial state of said second resistive switching element being written as a low resistance state, and this type of writing being labeled as forward writing W=1;
said initial state of said first resistive switching element being written as a low resistance state as said signal input to said first input end is low level and said signal input to said second input end is high level, and said initial state of said second resistive switching element being written as a high resistance state, and
this type of writing being labeled as reverse writing W =1; and said high resistance state of each of said resistive switching elements operating to st
[Truncated to input limit]