Office Action 2: Final Rejection (2022-10-18)
Rejection types: 103 - Obviousness, Double Patenting

CLAIMS:
Amendments to the Claims:

This listing of claims will replace all prior versions, and listings, of claims in the application:

1\. (Currently Amended) A system comprising:
memory;
a microcontroller including an analog-to-digital converter (ADC) and in communication with the memory and configured to:
define a fingerprint that includes a baseline measurement of side-channel traces of a side-channel of a separate processor retrieved from the ADC, during an enrollment period of the system, wherein the enrollment period includes measuring a voltage of the separate processor prior to runtime operation via a power supply pin of the ADC;
receive a runtime measurement from the ADC regarding the voltage of at least the separate processor during runtime, wherein the runtime measurement is retrieved directly from the power supply pin;
compare the runtime measurement to the fingerprint; and
in response to the measurement exceeding a threshold, executing a countermeasure operation against software ran by the separate processor, a hardware modification, or one or more fault-attacks.
2\. (Original) The system of claim 1, wherein the countermeasure includes outputting a message or a notification.
3\. (Original) The system of claim 1, wherein the ADC includes an ADC input pin connected to an internal voltage pin of the microcontroller, a powers supply, an internal regulator, or an intermediate voltage.
4\. (Original) The system of claim 1, wherein the ADC includes an encryption unit.
5\. (Original) The system of claim 1, wherein the ADC includes an ADC input pin connected to an internal voltage pin of the microcontroller to measure drain power voltage.
6\. (Original) The system of claim 1, wherein a channel of the side-channel includes a higher bandwidth than other channels of the side-channel, wherein the channel is utilized for the baseline measurement.
7\. (Original) The system of claim 1, wherein the ADC is connected via a least one data bus to the separate processor, wherein the ADC includes at least one channel connected via a secure bus that requires encryption or authentication or both.
8\. (Original) The system of claim 7, wherein the secure bus is controlled by a secure element or in response to a secure state of the microcontroller.
9\. (Original) The system of claim 1, wherein a channel of the side-channel includes a higher sampling rate than other channels of the side-channel of the ADC, wherein the channel is utilized for the baseline measurement.

10\. (Original) The system of claim 1, wherein the ADC is unconnected and configured to measure parasitic noise on the ADC.

11\. (Currently Amended) A computer-implement method, comprising:
defining a fingerprint that includes a baseline measurement retrieved from a side- channel of at least a separate processor during an enrollment period, wherein the baseline measurement includes one or more physical attributes received from an analog-to-digital converter (ADC) of a microcontroller;
receiving a runtime measurement from the ADC, wherein the runtime measurement includes the one or more physical attributes of at least the separate processor during runtime, wherein the runtime measurement is retrieved directly from a power supply pin of the ADC;
comparing the runtime measurement of the physical attribute to the fingerprint; and in response to the runtime measurement exceeding a threshold, executing a countermeasure operation against software ran by the separate processor, a hardware modification, or one or more fault-attacks.

12\. (Original) The computer-implemented method of claim 11, wherein the physical attribute includes a voltage.

13\. (Currently Amended) A system comprising:
memory;
a microcontroller including an analog-to-digital converter (ADC) and in communication with the memory and configured to:
define a fingerprint that includes a baseline measurement of side-channel traces of a side-channel retrieved from the ADC, during an enrollment period of the system, wherein the enrollment period includes measuring voltage prior to runtime operation;
receive a runtime measurement from the ADC that includes voltage of at least a separate microcontroller during runtime, wherein the runtime measurement is retrieved from a power supply pin of the ADC;
compare the runtime measurement to the fingerprint; and
in response to the measurement exceeding a threshold, executing a countermeasure operation against software ran by the separate processor, a hardware modification, or one or more fault-attacks.

14\. (Original) The system of claim 13, wherein the runtime measurement is retrieved from a connection between an input supply pin of the ADC and a voltage supply of the microcontroller.

15\. (Original) The system of claim 13, wherein the runtime measurement is retrieved from a connection between an input supply pin of the ADC and a ground of the microcontroller.

16\. (Original) The system of claim 13, wherein the runtime measurement is retrieved from no connection with an input supply pin of the ADC, wherein the runtime measurement includes parasitic noise of the ADC.

17\. (Original) The system of claim 13, wherein the countermeasure operation includes reprogramming the software to original code.

18\. (Original) The system of claim 13, wherein the countermeasure operation includes reprogramming the software.

19\. (Original) The system of claim 13, wherein the side-channel is associated with a separate microcontroller.

20\. (Original) The system of claim 13, wherein runtime measurement is sent to an intrusion detection system segregated from the separate processor and MCU, wherein the intrusion detection system is configured to compare the runtime measurement to the baseline measurement utilizing a neural network.
2 3 4 5

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The following is a Final Office action in response to communications received on 07/27/2022.
Response to Amendment
Claims 1, 11 and 13 have been amended.
Claims 1-20 have been examined.
Applicant’s arguments with respect to claim(s) 1, 11 and 13 regarding the new limitations: “wherein the enrollment period includes measuring a voltage of the separate processor prior to runtime operation via a power supply pin of the ADC” and “wherein the runtime measurement is retrieved directly from the power supply pin” have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA  as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 16/723861 in view of US 20040268159 to Aasheim et al (hereinafter Aasheim) and Behavior Profiling of Power Distribution Networks for Runtime Hardware Trojan Detection by Khalid et al (hereinafter Khalid).
Instant application
Copending Application No. 16/723861
1. (Currently Amended) A system comprising: memory; a microcontroller including an analog-to-digital converter (ADC) and in communication with the memory and configured to:
define a fingerprint that includes a baseline measurement of side-channel traces of a side-channel of a separate processor retrieved from the ADC, during an enrollment period of the system, wherein the enrollment period includes measuring a voltage of the separate processor prior to runtime operation via a power supply pin of the ADC;
receive a runtime measurement from the ADC regarding the voltage of at least the separate processor during runtime, wherein the runtime measurement is retrieved directly from the power supply pin;
compare the runtime measurement to the fingerprint; and
in response to the measurement exceeding a threshold, executing a countermeasure operation against software ran by the separate processor, a hardware modification, or one or more fault-attacks.
1. (Currently Amended) A system comprising: memory; a processor in communication with the memory and programmed to:
during an enrollment period, define a fingerprint that includes a baseline measurement of a physical attribute of at least a separate processor during an enrollment period of the system, wherein the enrollment period includes measuring the physical attribute of the separate processor prior to runtime operation;
receive a runtime measurement-from a sensor, the physical attribute of at least the separate processor during runtime;
compare the runtime measurement of the physical attribute to the fingerprint; and in response to the measurement exceeding a threshold, executing a countermeasure operation against software ran by the separate processor.
2. (Original) The system of claim 1, wherein the physical attribute includes a power consumption.
Copending Application No. 16/723861 does not teach: an analog-to-digital converter (ADC) and in communication with the memory; measuring a voltage of the separate processor via a power supply pin of the ADC; and wherein the runtime measurement is retrieved directly from the power supply pin. However, Aasheim teaches:
an analog-to-digital converter (ADC) and in communication with the memory; measuring a voltage of the separate processor via a power supply pin of the ADC (Aasheim: [0027] Power measurement circuit 106 typically includes an analog to digital converter (ADC) 208, a communications interface 210 and a memory 212. [0028] FIG. 3 illustrates an example of how a typical ADC 208 on circuit 106 might be coupled to an embedded device 102 to measure power consumption. ADC 208 generally converts a continuously variable (i.e., analog) power consumption signal from device 102 into a digital (discrete) form).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Aasheim in the invention of Co-pending application 16/723861 to include the above limitations. The claim would have been obvious because a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art (see KSR Int’l Co. v. Teleflex Inc. 550 U.S. ___, 82 USPQ2d 1385 (Supreme Court 2007) (KSR)).
Co-pending application 16/723861 in view of Aasheim does not teach: wherein the runtime measurement is retrieved directly from the power supply pin. However, Khalid teaches:
wherein the runtime measurement is retrieved directly from the power supply pin (Khalid: Page 1317, Fig. 1 and right column: B. Runtime Power Analysis: Fig. 1 shows the proposed off-chip runtime power monitors, which operates in two steps. In the first step, it obtains runtime power profile by measuring the current from the power ports of each module (PP1, PP2, ..., PPn) of integrated circuits. These values are then converted into the respective digital values through an analog to digital converter and then stored into memory. Fig. 1 shows the current from power ports of modules PP1, PP2, PPn being directly measured by the ADC).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Khalid in the invention of Co-pending application 16/723861 to include the above limitations. The claim would have been obvious because a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art (see KSR Int’l Co. v. Teleflex Inc. 550 U.S. ___, 82 USPQ2d 1385 (Supreme Court 2007) (KSR)).
Similarly, the rest of the independent and dependent claims of the instant application are analogous to the rest of the independent and dependent claims of Co-pending application 16/723861.
This is a provisional nonstatutory double patenting rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-3, 7-9, 11-15 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Behavior Profiling of Power Distribution Networks for Runtime Hardware Trojan Detection by Khalid et al (hereinafter Khalid), US 20040268159 to Aasheim et al (hereinafter Aasheim) and prior art of record US 10157278 to Gonzalez et al (hereinafter Gonzalez).
As per claim 1, Khalid teaches:
A system comprising:
memory; a microcontroller including an analog-to-digital converter (ADC) and in communication with the memory (Khalid: page 1317: Fig. 1 shows an ADC in communication with a memory) and configured to: define a fingerprint that includes a baseline measurement of side-channel traces of a side-channel of a separate processor retrieved from the (Khalid: Page 1317: Fig. 1, Left column, 2nd paragraph: The first step is to obtain the signature power behavior of the given integrated circuit that consists of sequentially connected modules at the pre-market test stage. A. Pre-Market Stage Power Behavior Extraction: The first phase of proposed methodology is to obtain the power behavior of different modules that are sequentially connected by utilizing the following steps: 1) In the first, we measure the power of each sequentially connected modules to extract the modular power behavior. Right column: In the proposed methodology, we utilized rate power consumption in different sequentially connected blocks of IP modules to develop a two stage classification criteria. In order to establish this criteria, the first step is to identify the normal behavior zone, which is the range between the maximum and minimum values of δP. Similarly, its normal behavior zone is the range between the maximum and minimum values of ΔP. Page 1318: left column: III Case Study: A. Signature obtained for the Power Behavior of AES: The first step is to obtain the signature power behavior of the AES, which is obtained by implementing AES modules without intrusion and with some of the benchmarks intrusions [18] in Verilog. The extraction of signature behavior of AES module is completed in two stages: In the first stage, the AES module is implemented in Verilog and its power rating is extracted using the Xillinx power (Xpower) analyzer for Virtex-5 (xc5vlx330) and Virtex-6 (Xc6vlx760). The highlighted columns of Table I show the dynamic power behavior signature of the AES in Xpower analyzer.);
receive a runtime measurement from the ADC regarding the voltage of at least the separate processor during runtime, wherein the runtime measurement is retrieved directly from the power supply pin (Khalid: Page 1317, Fig. 1 and right column: B. Runtime Power Analysis: Fig. 1 shows the proposed off-chip runtime power monitors, which operates in two steps. In the first step, it obtains runtime power profile by measuring the current from the power ports of each module (PP1, PP2, ..., PPn) of integrated circuits. These values are then converted into the respective digital values through an analog to digital converter and then stored into memory. Fig. 1 shows the current from power ports of modules PP1, PP2, PPn being directly measured by the ADC);
compare the runtime measurement to the fingerprint (Khalid: Page 1317, Fig. 1 and right column: B. Runtime Power Analysis: In the second step, the extracted power behavior is used to calculate the changes in current with respect to the sequentially connected modules (first and second derivatives of power behavior) and then compared to the upper and lower bounds of the changes in current from the signature power profile); and
in response to the measurement exceeding a threshold, (Khalid: Page 1317, Fig. 1 and right column: B. Runtime Power Analysis: If it lies outside the bounds then the integrated circuit is considered as intruded).
Khalid teaches obtaining power behavior signature at pre-market test stage using a Xillinx power (Xpower) analyzer but does not teach: via a power supply pin of the ADC. Also, Khalid does not teach: executing a countermeasure operation against software ran by the separate processor, a hardware modification, or one or more fault-attacks. However, Aasheim teaches:
a baseline measurement of side-channel traces of a side-channel … via a power supply pin of the ADC (Aasheim: [0027] Power measurement circuit 106 typically includes an analog to digital converter (ADC) 208, a communications interface 210 and a memory 212. [0028] FIG. 3 illustrates an example of how a typical ADC 208 on circuit 106 might be coupled to an embedded device 102 to measure power consumption. ADC 208 generally converts a continuously variable (i.e., analog) power consumption signal from device 102 into a digital (discrete) form. [0029]. Memory 218 includes a power profiler 220 module that is configured to execute on processor 216 to track and identify software instructions 206 executing on embedded device 102. [0033] Power profiler 220 is also configured to correlate the power consumption data 214 received from power measurement circuit 106 with the software instructions 206 executing on processor 200 of embedded device 102. Power profiler 220 generates a power profile 224 that quantifies the power consumed for the precise software instruction executing on processor 200 of embedded device 102.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Aasheim in the invention of Khalid to include the above limitations. The claim would have been obvious because a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art (see KSR Int’l Co. v. Teleflex Inc. 550 U.S. ___, 82 USPQ2d 1385 (Supreme Court 2007) (KSR)).
Khalid in view of Aasheim does not teach: executing a countermeasure operation against software ran by the separate processor, a hardware modification, or one or more fault-attacks. However, Gonzalez teaches:
executing a countermeasure operation against software ran by the separate processor, a hardware modification, or one or more fault-attacks (Gonzalez: column 4, lines 10-16: Based on the comparison, the fingerprinting system 100 can determine whether there is an anomaly of the measured target device/system at 104. If yes, the fingerprinting system can alert a user at 106. Column 7, lines 43-54: The response module 210 triggers automatic actions that affect the target device in response to integrity violations. Some of the actions/responses 221 can include, but not limited to activating another device, disabling control ports of the target device, notifying user of the target device, etc.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Gonzalez in the invention of Khalid in view of Aasheim to include the above limitations. The claim would have been obvious because a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art (see KSR Int’l Co. v. Teleflex Inc. 550 U.S. ___, 82 USPQ2d 1385 (Supreme Court 2007) (KSR)).
As per claim 2, Khalid in view of Aasheim and Gonzalez teaches:
The system of claim 1, wherein the countermeasure includes outputting a message or a notification (Gonzalez: Column 7, lines 43-54: Some of the actions/responses 221 can include, but not limited to …, notifying user of the target device).
The examiner provides the same rationale to combine prior arts Khalid in view of Aasheim and Gonzalez as in claim 1 above.
As per claim 3, Khalid in view of Aasheim and Gonzalez teaches:
The system of claim 1, wherein the ADC includes an ADC input pin connected to an internal voltage pin of the microcontroller, a powers supply, an internal regulator, or an intermediate voltage (Khalid: page 1317: Fig. 1, Right column: B. Runtime Power Analysis: In the first step, it obtains runtime power profile by measuring the current from the power ports of each module (PP1, PP2, ..., PPn) of integrated circuits. Fig. 1 shows the ADC connected to the power ports of the modules. Aasheim: Fig. 3 and [0028] FIG. 3 illustrates an example of how a typical ADC 208 on circuit 106 might be coupled to an embedded device 102 to measure power consumption).
The examiner provides the same rationale to combine prior arts Khalid and Aasheim as in claim 1 above.
As per claim 7, Khalid in view of Aasheim and Gonzalez teaches:
The system of claim 1, wherein the ADC is connected via a least one data bus to the separate processor, wherein the ADC includes at least one channel connected via a secure bus that requires encryption or authentication or both (Aasheim: [0021]: In the exemplary environment 100, the host computer 104 and the power measurement circuit 106 are also coupled via bus 108. [0027] Power measurement circuit 106 typically includes an analog to digital converter (ADC) 208. Gonzalez: Column 6, lines 1-21: After the signals are digitized, however, they can be stored for later processing or transferred to another location to be processed. Thus, the link or network 204 between the digitizer 203 and the DSP 205 can be a direct connection, a storage element for later processing, or a network connection for sending the digitized signals to a remote location. For added security, the network 204 may be physically or logically separated from the other network that carries traffic for the device being monitored. In some cases, encryption of the link (secure bus) or network 204 for added security may be desirable).
The examiner provides the same rationale to combine prior arts Khalid in view of Aasheim and Gonzalez as in claim 1 above.
As per claim 8, Khalid in view of Aasheim and Gonzalez teaches:
The system of claim 7, wherein the secure bus is controlled by a secure element or in response to a secure state of the microcontroller (Gonzalez: Column 6, lines 1-21: After the signals are digitized, however, they can be stored for later processing or transferred to another location to be processed. Thus, the link or network 204 between the digitizer 203 and the DSP 205 can be a direct connection, a storage element for later processing, or a network connection for sending the digitized signals to a remote location. For added security, the network 204 may be physically or logically separated from the other network that carries traffic for the device being monitored. In some cases, encryption of the link or network 204 for added security may be desirable).
The examiner provides the same rationale to combine prior arts Khalid in view of Aasheim and Gonzalez as in claim 1 above.
As per claim 9, Khalid in view of Aasheim and Gonzalez teaches:
The system of claim 1, wherein a channel of the side-channel includes a higher sampling rate than other channels of the side-channel of the ADC, wherein the channel is utilized for the baseline measurement (Aasheim: [0028]: The analog power consumption signal from device 102 is sampled at a rate that is typically greater than the rate at which instructions 206 are being executed by processor 200 on embedded device 102).
The examiner provides the same rationale to combine prior arts Khalid and Aasheim as in claim 1 above.
As per claim 11, Khalid teaches:
A computer-implement method, comprising:
defining a fingerprint that includes a baseline measurement retrieved from a side-channel of at least a separate processor during an enrollment period, wherein the baseline measurement includes one or more physical attributes (Khalid: Page 1317: Fig. 1, Left column, 2nd paragraph: The first step is to obtain the signature power behavior of the given integrated circuit that consists of sequentially connected modules at the pre-market test stage. A. Pre-Market Stage Power Behavior Extraction: The first phase of proposed methodology is to obtain the power behavior of different modules that are sequentially connected by utilizing the following steps: 1) In the first, we measure the power of each sequentially connected modules to extract the modular power behavior. Right column: In the proposed methodology, we utilized rate power consumption in different sequentially connected blocks of IP modules to develop a two stage classification criteria. In order to establish this criteria, the first step is to identify the normal behavior zone, which is the range between the maximum and minimum values of δP. Similarly, its normal behavior zone is the range between the maximum and minimum values of ΔP. Page 1318: left column: III Case Study: A. Signature obtained for the Power Behavior of AES: The first step is to obtain the signature power behavior of the AES, which is obtained by implementing AES modules without intrusion and with some of the benchmarks intrusions [18] in Verilog. The extraction of signature behavior of AES module is completed in two stages: In the first stage, the AES module is implemented in Verilog and its power rating is extracted using the Xillinx power (Xpower) analyzer for Virtex-5 (xc5vlx330) and Virtex-6 (Xc6vlx760). The highlighted columns of Table I show the dynamic power behavior signature of the AES in Xpower analyzer.);
receiving a runtime measurement from the ADC, wherein the runtime measurement includes the one or more physical attributes of at least the separate processor during runtime, wherein the runtime measurement is retrieved directly from a power supply pin of the ADC (Khalid: Page 1317, Fig. 1 and right column: B. Runtime Power Analysis: Fig. 1 shows the proposed off-chip runtime power monitors, which operates in two steps. In the first step, it obtains runtime power profile by measuring the current from the power ports of each module (PP1, PP2, ..., PPn) of integrated circuits. These values are then converted into the respective digital values through an analog to digital converter and then stored into memory. Fig. 1 shows the current from power ports of modules PP1, PP2, PPn being directly measured by the ADC);
comparing the runtime measurement of the physical attribute to the fingerprint (Khalid: Page 1317, Fig. 1 and right column: B. Runtime Power Analysis: In the second step, the extracted power behavior is used to calculate the changes in current with respect to the sequentially connected modules (first and second derivatives of power behavior) and then compared to the upper and lower bounds of the changes in current from the signature power profile); and
in response to the runtime measurement exceeding a threshold  (Khalid: Page 1317, Fig. 1 and right column: B. Runtime Power Analysis: If it lies outside the bounds then the integrated circuit is considered as intruded).
Khalid teaches obtaining power behavior signature at pre-market test stage using a Xillinx power (Xpower) analyzer but does not teach: physical attributes received from an analog-to-digital converter (ADC) of a microcontroller. Also, Khalid does not teach: executing a countermeasure operation against software ran by the separate processor, a hardware modification, or one or more fault-attacks. However, Aasheim teaches:
physical attributes received from an analog-to-digital converter (ADC) of a microcontroller (Aasheim: [0027] Power measurement circuit 106 typically includes an analog to digital converter (ADC) 208, a communications interface 210 and a memory 212. [0028] FIG. 3 illustrates an example of how a typical ADC 208 on circuit 106 might be coupled to an embedded device 102 to measure power consumption. ADC 208 generally converts a continuously variable (i.e., analog) power consumption signal from device 102 into a digital (discrete) form. [0029]. Memory 218 includes a power profiler 220 module that is configured to execute on processor 216 to track and identify software instructions 206 executing on embedded device 102. [0033] Power profiler 220 is also configured to correlate the power consumption data 214 received from power measurement circuit 106 with the software instructions 206 executing on processor 200 of embedded device 102. Power profiler 220 generates a power profile 224 that quantifies the power consumed for the precise software instruction executing on processor 200 of embedded device 102).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Aasheim in the invention of Khalid to include the above limitations. The claim would have been obvious because a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art (see KSR Int’l Co. v. Teleflex Inc. 550 U.S. ___, 82 USPQ2d 1385 (Supreme Court 2007) (KSR)).
Khalid in view of Aasheim does not teach: executing a countermeasure operation against software ran by the separate processor, a hardware modification, or one or more fault-attacks. However, Gonzalez teaches:
executing a countermeasure operation against software ran by the separate processor, a hardware modification, or one or more fault-attacks (Gonzalez: column 4, lines 10-16: Based on the comparison, the fingerprinting system 100 can determine whether there is an anomaly of the measured target device/system at 104. If yes, the fingerprinting system can alert a user at 106. Column 7, lines 43-54: The response module 210 triggers automatic actions that affect the target device in response to integrity violations. Some of the actions/responses 221 can include, but not limited to activating another device, disabling control ports of the target device, notifying user of the target device, etc.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Gonzalez in the invention of Khalid in view of Aasheim to include the above limitations. The claim would have been obvious because a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art (see KSR Int’l Co. v. Teleflex Inc. 550 U.S. ___, 82 USPQ2d 1385 (Supreme Court 2007) (KSR)).
As per claim 12, Khalid in view of Aasheim and Gonzalez teaches:
The computer-implemented method of claim 11, wherein the physical attribute includes a voltage (Aasheim: [0028] FIG. 3 illustrates an example of how a typical ADC 208 on circuit 106 might be coupled to an embedded device 102 to measure power consumption. Gonzalez: Column 11, lines 57-60: The on-chip sensor may be located in a processor, support chip, or in the power management chip, and may detect voltage).
The examiner provides the same rationale to combine prior arts Khalid in view of Aasheim and Gonzalez as in claim 11 above.
As per claim 13, Khalid teaches:
A system comprising:
memory; a microcontroller including an analog-to-digital converter (ADC) and in communication with the memory (Khalid: page 1317: Fig. 1 shows an ADC in communication with a memory) and configured to: define a fingerprint that includes a baseline measurement of side-channel traces of a side-channel retrieved from the ADC, during an enrollment period of the system, wherein the enrollment period includes measuring voltage prior to runtime operation (Khalid: Page 1317: Fig. 1, Left column, 2nd paragraph: The first step is to obtain the signature power behavior of the given integrated circuit that consists of sequentially connected modules at the pre-market test stage. A. Pre-Market Stage Power Behavior Extraction: The first phase of proposed methodology is to obtain the power behavior of different modules that are sequentially connected by utilizing the following steps: 1) In the first, we measure the power of each sequentially connected modules to extract the modular power behavior. Right column: In the proposed methodology, we utilized rate power consumption in different sequentially connected blocks of IP modules to develop a two stage classification criteria. In order to establish this criteria, the first step is to identify the normal behavior zone, which is the range between the maximum and minimum values of δP. Similarly, its normal behavior zone is the range between the maximum and minimum values of ΔP. Page 1318: left column: III Case Study: A. Signature obtained for the Power Behavior of AES: The first step is to obtain the signature power behavior of the AES, which is obtained by implementing AES modules without intrusion and with some of the benchmarks intrusions [18] in Verilog. The extraction of signature behavior of AES module is completed in two stages: In the first stage, the AES module is implemented in Verilog and its power rating is extracted using the Xillinx power (Xpower) analyzer for Virtex-5 (xc5vlx330) and Virtex-6 (Xc6vlx760). The highlighted columns of Table I show the dynamic power behavior signature of the AES in Xpower analyzer);
receive a runtime measurement from the ADC that includes voltage of at least a separate microcontroller during runtime, wherein the runtime measurement is retrieved from a power supply pin of the ADC (Khalid: Page 1317, Fig. 1 and right column: B. Runtime Power Analysis: Fig. 1 shows the proposed off-chip runtime power monitors, which operates in two steps. In the first step, it obtains runtime power profile by measuring the current from the power ports of each module (PP1, PP2, ..., PPn) of integrated circuits. These values are then converted into the respective digital values through an analog to digital converter and then stored into memory. Fig. 1 shows the current from power ports of modules PP1, PP2, PPn being directly measured by the ADC);
compare the runtime measurement to the fingerprint (Khalid: Page 1317, Fig. 1 and right column: B. Runtime Power Analysis: In the second step, the extracted power behavior is used to calculate the changes in current with respect to the sequentially connected modules (first and second derivatives of power behavior) and then compared to the upper and lower bounds of the changes in current from the signature power profile); and
in response to the measurement exceeding a threshold (Khalid: Page 1317, Fig. 1 and right column: B. Runtime Power Analysis: If it lies outside the bounds then the integrated circuit is considered as intruded).
Khalid teaches obtaining power behavior signature at pre-market test stage using a Xillinx power (Xpower) analyzer but does not teach: a baseline measurement retrieved from the ADC. Also, Khalid does not teach: executing a countermeasure operation against software ran by the separate processor, a hardware modification, or one or more fault-attacks. However, Aasheim teaches:
a baseline measurement retrieved from the ADC (Aasheim: [0027] Power measurement circuit 106 typically includes an analog to digital converter (ADC) 208, a communications interface 210 and a memory 212. [0028] FIG. 3 illustrates an example of how a typical ADC 208 on circuit 106 might be coupled to an embedded device 102 to measure power consumption. ADC 208 generally converts a continuously variable (i.e., analog) power consumption signal from device 102 into a digital (discrete) form. [0029]. Memory 218 includes a power profiler 220 module that is configured to execute on processor 216 to track and identify software instructions 206 executing on embedded device 102. [0033] Power profiler 220 is also configured to correlate the power consumption data 214 received from power measurement circuit 106 with the software instructions 206 executing on processor 200 of embedded device 102. Power profiler 220 generates a power profile 224 that quantifies the power consumed for the precise software instruction executing on processor 200 of embedded device 102.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Aasheim in the invention of Khalid to include the above limitations. The claim would have been obvious because a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art (see KSR Int’l Co. v. Teleflex Inc. 550 U.S. ___, 82 USPQ2d 1385 (Supreme Court 2007) (KSR)).
Khalid in view of Aasheim does not teach: executing a countermeasure operation against software ran by the separate processor, a hardware modification, or one or more fault-attacks. However, Gonzalez teaches:
executing a countermeasure operation against software ran by the separate processor, a hardware modification, or one or more fault-attacks (Gonzalez: column 4, lines 10-16: Based on the comparison, the fingerprinting system 100 can determine whether there is an anomaly of the measured target device/system at 104. If yes, the fingerprinting system can alert a user at 106. Column 7, lines 43-54: The response module 210 triggers automatic actions that affect the target device in response to integrity violations. Some of the actions/responses 221 can include, but not limited to activating another device, disabling control ports of the target device, notifying user of the target device, etc.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Gonzalez in the invention of Khalid in view of Aasheim to include the above limitations. The claim would have been obvious because a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art (see KSR Int’l Co. v. Teleflex Inc. 550 U.S. ___, 82 USPQ2d 1385 (Supreme Court 2007) (KSR)).
As per claim 14, Khalid in view of Aasheim and Gonzalez teaches:
The system of claim 13, wherein the runtime measurement is retrieved from a connection between an input supply pin of the ADC and a voltage supply of the microcontroller (Khalid: Page 1317, Fig. 1 and right column: B. Runtime Power Analysis: Fig. 1 shows the proposed off-chip runtime power monitors, which operates in two steps. In the first step, it obtains runtime power profile by measuring the current from the power ports of each module (PP1, PP2, ..., PPn) of integrated circuits. Aasheim: Fig. 3 show a input supply pin of the ADC Vin connected to the voltage supply).
The examiner provides the same rationale to combine prior arts Khalid and Aasheim as in claim 13 above.
As per claim 15, Khalid in view of Aasheim and Gonzalez teaches:
The system of claim 13, wherein the runtime measurement is retrieved from a connection between an input supply pin of the ADC and a ground of the microcontroller (Khalid: Page 1317, Fig. 1 and right column: B. Runtime Power Analysis: Fig. 1 shows the proposed off-chip runtime power monitors, which operates in two steps. In the first step, it obtains runtime power profile by measuring the current from the power ports of each module (PP1, PP2, ..., PPn) of integrated circuits. Aasheim: Fig. 3 show a input supply pin of the ADC and the ground).
The examiner provides the same rationale to combine prior arts Khalid and Aasheim as in claim 13 above.
As per claim 17, Khalid in view of Aasheim and Gonzalez teaches:
The system of claim 13, wherein the countermeasure operation includes reprogramming the software to original code (Gonzalez: column 7, lines 43-54: Some of the actions/responses 221 can include, but not limited to activating another device, disabling control ports of the target device, notifying user of the target device, triggering the target device for reboot and reinitiating virtualization. Column 8, lines 3-9: In the case of that a virtual machine is running at the target device and anomalous behavior is found in one of the side channels, the virtual machine can be restarted or migrated).
The examiner provides the same rationale to combine prior arts Khalid in view of Aasheim and Gonzalez as in claim 13 above.
As per claim 18, Khalid in view of Aasheim and Gonzalez teaches:
The system of claim 13, wherein the countermeasure operation includes reprogramming the software (Gonzalez: column 7, lines 43-54: Some of the actions/responses 221 can include, but not limited to activating another device, disabling control ports of the target device, notifying user of the target device, triggering the target device for reboot and reinitiating virtualization. Column 8, lines 3-9: In the case of that a virtual machine is running at the target device and anomalous behavior is found in one of the side channels, the virtual machine can be restarted or migrated).
The examiner provides the same rationale to combine prior arts Khalid in view of Aasheim and Gonzalez as in claim 13 above.
As per claim 19, Khalid in view of Aasheim and Gonzalez teaches:
The system of claim 13, wherein the side-channel is associated with a separate microcontroller (Khalid: page 1317: Fig. 1 and left column, 2nd paragraph: The first step is to obtain the signature power behavior of the given integrated circuit).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Khalid in view of Aasheim and Gonzalez as applied to claim 1 above, and further in view of prior art of record An Encryption-Authentication Unified A/D Conversion Scheme for loT Sensor Nodes by Gadde et al (hereinafter Gadde).
As per claim 4, Khalid in view of Aasheim and Gonzalez does not teach: wherein the ADC includes an encryption unit. However, Gadde teaches:
wherein the ADC includes an encryption unit (Gadde: Abstract: We have proposed an Analog-to-Digital Conversion scheme, based on slope A/D conversion, involving two randomized slopes, to realize resistance to side channel attacks and perform data encryption-authentication during the A/D conversion process. We have designed and fabricated the proposed encryption- authentication unified ADC in 0.18pm CMOS process).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Gadde in the invention of Khalid in view of Aasheim and Gonzalez to include the above limitations. The motivation to do so would be to realize resistance to side channel attacks (Gadde: Abstract).
Claims 5, 6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Khalid in view of Aasheim and Gonzalez as applied to claims 1 and 13 above, and further in view of prior art of record US 20150317475 to Aguayo Gonzalez et al (hereinafter Gonzalez’475).
As per claim 5, Khalid in view of Aasheim and Gonzalez teaches:
The system of claim 1, wherein the ADC includes an ADC input pin connected to an internal voltage pin of the microcontroller (Aasheim: [0028] FIG. 3 illustrates an example of how a typical ADC 208 on circuit 106 might be coupled to an embedded device 102 to measure power consumption).
Khalid in view of Aasheim and Gonzalez does not teach: to measure drain power voltage. However, Gozalez’475 teaches:
measure drain power voltage (Gonzalez’475: [0074] The physical location of the sensor is a critical element for the success of this approach. The ideal location 210 is shown in FIG. 2 at the VDD signal of the processor 205).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Gonzalez’475 in the invention of Khalid in view of Aasheim and Gonzalez to include the above limitations. The motivation to do so would be to provide an integrity assessment and intrusion detection solution for critical cyber systems (Gonzalez’475: [0005)).
As per claim 6, Khalid in view of Aasheim and Gonzalez teaches:
The system of claim 1, wherein the channel is utilized for the baseline measurement (Aasheim: [0028] FIG. 3 illustrates an example of how a typical ADC 208 on circuit 106 might be coupled to an embedded device 102 to measure power consumption).
Khalid in view of Aasheim and Gonzalez does not teach: wherein a channel of the side-channel includes a higher bandwidth than other channels of the side-channel. However, Gonzalez’475 teaches:
wherein a channel of the side-channel includes a higher bandwidth than other channels of the side-channel (Gonzalez’475: [0073] The general PFP method begins by collecting fine-grained measurements from the power consumption during the execution of trusted code. The sensor 110 can be implemented by means of ..., a high-bandwidth current mirror. [0353] One example approach to reduce the variance of the estimates, and thus the probabilities of making a classification error, is to increase the time-bandwidth product of the observation).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Gonzalez’475 in the invention of Khalid in view of Aasheim and Gonzalez to include the above limitations. The motivation to do so would be to provide an integrity assessment and intrusion detection solution for critical cyber systems (Gonzalez’475: [0005)).
As per claim 20, Khalid in view of Aasheim and Gonzalez teaches:
The system of claim 13, wherein runtime measurement is sent to an intrusion detection system segregated from the separate processor and MCU (Gonzalez: column 7, lines 24-35: Upon performing comparison and analytics, the PFP analytics 206 can forward comparison data to a decision module 206b to determine whether an intrusion or anomaly exists. In other instances, the PFP analytics 206 can send the analytics data to other intrusion detectors 223).
Khalid in view of Aasheim and Gonzalez does not teach: wherein the intrusion detection system is configured to compare the runtime measurement to the baseline measurement utilizing a neural network. However, Gonzalez’475 teaches:
wherein the intrusion detection system is configured to compare the runtime measurement to the baseline measurement utilizing a neural network (Gonzalez’475: [0091]: Other techniques for detector design and machine training include: Neural Networks. [0343] In one embodiment, the PFP system may enable intrusion detection based on a supervised learning approach, preventing attackers from training the intrusion detection system (IDS) after deployment to accept their malicious actions, traffic packets or other activities. In supervised learning, the specific features and patterns used as a baseline reference (power fingerprint) to determine when anomalies exist are determined during a pre-characterization stage and are not changed until the system gets updated. [0347] The PFP system can observe and characterize the fine-grained patterns in the power consumption of digital systems).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Gonzalez’475 in the invention of Khalid in view of Aasheim and Gonzalez to include the above limitations. The motivation to do so would be to provide an integrity assessment and intrusion detection solution for critical cyber systems (Gonzalez’475: [0005)).
Claims 10 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Khalid in view of Aasheim and Gonzalez as applied to claims 1 and 13 above, and further in view of prior art of record Measurements of spurious emission with a time-domain EMI measurement system using multi-sampling techniques by Braun et al (hereinafter Braun).
As per claim 10, Khalid in view of Aasheim and Gonzalez does not teach the limitations of claim 10. However, Braun teaches:
wherein the ADC is unconnected and configured to measure parasitic noise on the ADC (Braun: Page 793: Left column: A Nonlinearity of ADCs: Analog-to- Digital Converter show deviations from the ideal quantization steps that are described by the differential nonlinearity (DNL) and integral nonlinearity (INL). Right column: B. Methods to determine INL and DNL of ADCs: A sinusoidal signal is applied to the ADC. The sinusoidal signal x(t) = sin (ωt) is digitized by an ADC with K quantization steps. For a full scale sinusoidal signal we obtain a digitized signal x[k] of an ideal ADC according to: x[k] = round(
K
2
sin (ωt). The probability density function (PDF) PDF[k] is calculated according to: PDF[k] =
∑
n
=
1
N
δ
(
x
n
-
k
)
(4) where
δ
(
x
n
-
k
)
is the Kronnecker Symbol and returns 1 if x[n] = k. From the relation between the PDF of an ideal ADC and the measured PDF the DNL of the ADC is determined. By performing a numeric integration of the DNL the INL is calculated. Page 794: 1) Stationary spurious signals: Stationary spurious signals are independent of the input signals and are mainly caused by internal ADC clocking signals. Their frequencies are a fraction of the sampling frequency. The frequency of the spurious signals can be described by (6) fspur =
m
f
s
l
I,m = 1, 2, 3, ... (6)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Braun in the invention of Khalid in view of Aasheim and Gonzalez to include the above limitations. The motivation to do so would be to enhance the spurious free dynamic range of the Time-domain EMI Measurement System (Braun: Abstract).
As per claim 16, Khalid in view of Aasheim and Gonzalez does not teach the limitations of claim 16. However, Braun teaches:
wherein the runtime measurement is retrieved from no connection with an input supply pin of the ADC, wherein the runtime measurement includes parasitic noise of the ADC (Braun: Page 793: Left column: A Nonlinearity of ADCs: Analog-to- Digital Converter show deviations from the ideal quantization steps that are described by the differential nonlinearity (DNL) and integral nonlinearity (INL). Right column: B. Methods to determine INL and DNL of ADCs: A sinusoidal signal is applied to the ADC. The sinusoidal signal x(t) = sin (ωt) is digitized by an ADC with K quantization steps. For a full scale sinusoidal signal we obtain a digitized signal x[k] of an ideal ADC according to: x[k] = round(
K
2
sin (ωt). The probability density function (PDF) PDF[k] is calculated according to: PDF[k] =
∑
n
=
1
N
δ
(
x
n
-
k
)
(4) where
δ
(
x
n
-
k
)
is the Kronnecker Symbol and returns 1 if x[n] = k. From the relation between the PDF of an ideal ADC and the measured PDF the DNL of the ADC is determined. By performing a numeric integration of the DNL the INL is calculated. Page 794: 1) Stationary spurious signals: Stationary spurious signals are independent of the input signals and are mainly caused by internal ADC clocking signals. Their frequencies are a fraction of the sampling frequency. The frequency of the spurious signals can be described by (6) fspur =
m
f
s
l
I,m = 1, 2, 3, ... (6)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Braun in the invention of Khalid in view of Aasheim and Gonzalez to include the above limitations. The motivation to do so would be to enhance the spurious free dynamic range of the Time-domain EMI Measurement System (Braun: Abstract).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action.  Accordingly, THIS ACTION IS MADE FINAL.  See MPEP § 706.07(a).  Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action.  In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action.  In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.

APPLICANT REBUTTAL: Remarks
Reconsideration of the above-identified application in view of the present Amendment is respectfully requested
Claims 1-20 are currently rejected. Claims 1, 11, and 13 are currently amended. No new matter has been added by these amendments.
Double Patentin
-
Claims 1-20 are provisionally rejected on the grounds of nonstatutory double patenting as being unpatentable over claims 1-20 of Application No. 16/723,861 in view of U.S. Patent No. 10,157,278 to Gonzalez et al., hereinafter Gonzalez. While the Applicant traverses the Rejection, the claims are now amended and the rejection is therefore moot. Notably, Gonzalez relies on a sensor, which is distinct from the claims in the instant application.
Rej
ection Un
d
er 35 U
.S.C.
.
Claims 1-3, 7-9, 11-14, and 17-19 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Gonzalez. While the Applicant traverses the Rejection, the claims are now amended to facilitate prosecution. Specifically, the claims require, among other things "wherein the runtime measurement is retrieved directly from a power supply pin of the ADC." This is distinct from Gonzalez and does not utilize sensors such as those in Gonzalez. Non-limiting examples of this is shown in FIG 2 (note power supply pin 217) and FIG. 3A (note power supply pin 307):
FIG. 2
FtG. 3A
In contrast, Gonazalez utilizes side-channel information measured by side-channel probes. ("FIG. 1 is a combined system structure and work flow diagram illustrating aspects of a fingerprinting system 100 for anomaly detection based on side-channel information measured by side-channel probes. See Gonzalez at 2: 64-67.) Gonzales is directed to reprogrammable devices (e.g. FPGA), where you can observe certain pins to see if they are being reprogrammed. At best, Gonzalez discloses "[a]n EM sensor or a direct circuit connection is used for monitoring a change of state in the pin on the chip 1001a that enables flash memory to be reprogrammed or for enabling the FPGA or the BIOS to be reprogrammed." (Gonzalez at 19; 41-45.) In contrast, the power supply pin has nothing directly to do with a device being reprogrammed. It's simply a power supply pin. Thus, Gonzalez fails to disclose the limitations as claimed.
Specifically, with respect to claim 14, the claim requires "wherein the runtime measurement is retrieved from a connection between an input supply pin of the ADC and a ground of the microcontroller." Gonzalez again utilizes an on-chip sensor. The on-chip sensor of Gonzalez is an internal sensor, and thus, does not need to be connected to anything, nor is it "retrieved from a connection between an input supply pin of the ADC and a ground of the microcontroller." The cited portion simply states "The on-chip sensor may be located in a processor, support chip, or in the power management chip, and may detect voltage, current, power, signal delay, radiation, audio and/or temperature." The cited portion never states that the measurement is "retrieved from a connection between an input supply pin of the ADC and a ground of the microcontroller." For at least this reason, the claim is in condition for allowance.
Rej
ection Under 35 U.S.
C.
.
Claim 4 is rejected under 35 U.S.C. § 103 as being unpatentable over Gonzalez and Non- Patent Literature "An Encryption-Authentication Unified A/D Conversion Scheme for loT Sensor Nodes" to Gadde et al., hereinafter Gadde. Claim 4 is allowable based on its dependency to claim 1.
Claims 5, 6, 15, and 20 are rejected under 35 U.S.C. § 103 as being unpatentable over Gonzalez and U.S. Publication No. 2015/0317475 to Gonzalez et al., hereinafter '475 Gonzalez. These claims are allowable based on their dependency to their corresponding independent claim.
Claims 10 and 16 are rejected under 35 U.S.C. § 103 as being unpatentable over Gonzalez and Non-Patent Literature "Measurements of spurious emission with a time-domain EMI measurement system using multi-sampling techniques" to Braun et al., hereinafter Braun. These claims are allowable based on their dependency to their corresponding independent claim.
Sum
marv
Applicant has made a genuine effort to respond to the rejections and advance prosecution of this application. Applicant respectfully submits that all formal and substantive requirements for patentability have been met and that this case is in condition for allowance, which action is respectfully requested.
The Examiner is requested to telephone the undersigned to discuss resolution of any remaining issues.
No additional fee is believed be due as a result of filing this paper. However, please charge any fees or credit any overpayments as a result of the filing of this paper to Deposit Account No. 04-1061.
Respectfully submitted,Dickinson Wright PLLC

NEXT OFFICE ACTION: DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The text of those sections of Title 35 U.S. Code not included in this section can be found in the prior office action.
The prior office actions are incorporated herein by reference. In particular, the observations with respect to claim language, and response to previously presented arguments.
The examiner is withdrawing the double patenting rejection in view of the different scopes of the claims brought about as a result of the various amendments made to the independent claims of both the applications.
Claims 1-7, 9, and 11-22, now renumbered as claims 1-20, have been examined.
EXAMINER’S AMENDMENT
Authorization for this examiner’s amendment was given in an interview with Mr. Mark A. Jotanovic on 07/22/2024.
Claims have been amended as follows:
1. (Currently Amended) A system comprising:
memory;
a microcontroller including an analog-to-digital converter (ADC) and in communication with the memory and configured to:
define a fingerprint that includes a baseline measurement of side-channel traces of a side-channel of a separate processor retrieved from the ADC, during an enrollment period of the system, wherein the enrollment period includes measuring a voltage of the separate processor prior to runtime operation via a power supply pin of the ADC, wherein the ADC includes a security register that is accessible upon passing security measures;
receive a runtime measurement from the ADC regarding the voltage of at least the separate processor during runtime, wherein the runtime measurement is retrieved directly from the power supply pin;
compare the runtime measurement to the fingerprint; and
in response to the measurement exceeding a threshold, executing a countermeasure operation against software ran by the separate processor, a hardware modification, or one or more fault-attacks, wherein the countermeasure operation is associated with a context defined by the runtime measurement from the ADC.
4. (Currently Amended) The system of claim 1, wherein the ADC includes an encryption unit that receives output via security register
11. (Currently Amended) A computer-implement method, comprising:
defining a fingerprint that includes a baseline measurement retrieved from a side- channel of at least a separate processor during an enrollment period, wherein the baseline measurement includes one or more physical attributes received from an analog-to-digital converter (ADC) of a microcontroller, wherein the ADC includes a security register that is accessible upon passing security measures;
receiving a runtime measurement from the ADC, wherein the runtime measurement includes the one or more physical attributes of at least the separate processor during runtime, wherein the runtime measurement is retrieved directly from a power supply pin of the ADC;
comparing the runtime measurement of the physical attribute to the fingerprint; and
in response to the runtime measurement exceeding a threshold, executing a countermeasure operation against software ran by the separate processor, a hardware modification, or one or more fault-attacks, wherein the countermeasure operation is associated with a context defined by the runtime measurement from the ADC.
Allowable Subject Matter
Claims 1-7, 9, and 11-22 are allowed over prior art of record.
Response to Arguments
Applicant’s arguments, see Remarks, filed 04/08/2024, have been fully considered.
Examiner's Statement of Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Independent claims 1, 11, and 13 are allowed in view of the examiner’s amendment and for reasons presented by the applicant in the Remarks. Claims 2-7, 9, 12, and 14-22 depend on one of the above independent claims and are therefore, allowed by virtue of their dependency.
Prior art of record Khalid teaches:  A signature power behavior of a given integrated circuit is obtained at the pre-market test stage. During the runtime operation of the IC, the an analog-to-digital converter (ADC) measures current from the power ports of the IC to obtain the runtime power profile of the IC. The runtime power profile is compared to the signature power behavior to determine if there is an intrusion attack on the IC. Prior art of record Aasheim teaches: A power measurement circuit includes an ADC. The power supply pin of the ADC is coupled to an embedded device to measure power consumption. A power profiler uses the measured power consumption to generate a power profile that quantifies the power consumed for the precise software instruction executing on a processor of embedded device. Prior art of record Gonzalez teaches: When it is determined that there is an anomaly or intrusion in a target device based on the measurements from an ADC, automatic actions are triggered. The correct actions to take are determined based on evaluating a response policy and depend on the context such as detecting malware, anomalous behavior in the side channels, etc.
However, the prior arts fail to teach: “wherein the ADC includes a security register that is accessible upon passing security measures”.
None of the prior art of record, either taken by itself or in any combination, would have anticipated or made obvious the invention of the present application at or before the time it was filed.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee.  Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 10685118 to Prowell et al: A system and method (referred to as the system) detects malware, viruses, and/or malicious activity by generating a direct current source power consumption profile by causing a monitored device to execute a fully automated recurrent software operation. The system receives by an automated detection system, the direct current source power consumption profile generated by an intelligent power sensor and generates by a detection engine, a power security profile that identifies suspicious code by profiling direct current consumed by monitored type devices. The system executes a detection engine remote from the monitored device that identifies an infected device.

CITED REFERENCE SUMMARIES: Ref US20040268159A1: Claims:
A processor-readable medium comprising processor-executable instructions configured for: identifying instructions executing on a processor; receiving power consumption data from a power measurement circuit; and correlating the power consumption data with the identified instructions.
identifying instructions executing on a processor;
receiving power consumption data from a power measurement circuit; and
correlating the power consumption data with the identified instructions.
A processor-readable medium as recited in claim 1 , wherein the identifying comprises: interrupting the processor; sampling a program counter of the processor; scanning a lookup table to find an address indicated by the program counter; and determining an instruction located at the address.
interrupting the processor;
sampling a program counter of the processor;
scanning a lookup table to find an address indicated by the program counter; and
determining an instruction located at the address.
A processor-readable medium as recited in claim 1 , wherein the receiving comprises: querying the power measurement circuit; and receiving digital power readings from the power measurement circuit based on the querying.
querying the power measurement circuit; and
receiving digital power readings from the power measurement circuit based on the querying.
A processor-readable medium as recited in claim 1 , wherein the receiving comprises receiving digital power readings from the power measurement circuit at preset time intervals.
A processor-readable medium as recited in claim 1 , wherein the correlating comprises associating with an identified instruction, a measured amount of power consumed during execution of the identified instruction on the processor.
A processor-readable medium as recited in claim 1 , wherein the correlating comprises generating a power profile that includes a plurality of power consumption values and a plurality of identified instructions, wherein each power consumption value is associated with an identified instruction in the power profile.
A processor-readable medium as recited in claim 6 , wherein the power profile is selected from the group comprising: a table having pairs of data, each pair of data comprising a power consumption value and an identified instruction; and a graph correlating power consumption values with identified instructions.
a table having pairs of data, each pair of data comprising a power consumption value and an identified instruction; and
a graph correlating power consumption values with identified instructions.
A processor-readable medium as recited in claim 1 , wherein the power consumption data comprises power consumption values measured during execution of the instructions on the processor.
A processor-readable medium as recited in claim 1 , wherein the processor is a component of a device selected from the group comprising: an embedded mobile PDA (personal digital assistant) computing device operable by battery power; a cell phone; a smart phone; a notebook computer; a desktop PC (personal computer); a workstation; a server; a mainframe computer; and an Internet appliance.
an embedded mobile PDA (personal digital assistant) computing device operable by battery power;
a notebook computer;
a desktop PC (personal computer);
a mainframe computer; and
an Internet appliance.
A processor-readable medium comprising processor-executable instructions configured for associating a software instruction with an amount of power consumed by executing the software instruction.
A processor-readable medium as recited in claim 10 , wherein the associating comprises generating a power profile that matches software instructions executing on an embedded device with corresponding power consumption values measured during execution of the software instructions.
A processor-readable medium comprising processor-executable instructions configured for: measuring power consumption of software instructions executing on a target computing device; converting analog power measurements into digital power measurements; and transmitting the digital power measurements to a host computer.
measuring power consumption of software instructions executing on a target computing device;
converting analog power measurements into digital power measurements; and
transmitting the digital power measurements to a host computer.
A processor-readable medium as recited in claim 12 , comprising further processor-executable instructions configured for storing the digital power measurements in a memory after the converting.
A processor-readable medium as recited in claim 12 , wherein the transmitting comprises: receiving a request for the digital power measurements from the host computer; and transmitting the digital power measurements to the host computer based on the request.
receiving a request for the digital power measurements from the host computer; and
transmitting the digital power measurements to the host computer based on the request.
A processor-readable medium as recited in claim 12 , wherein the transmitting comprises transmitting the digital power measurements to the host computer at preset time intervals.
A processor-readable medium as recited in claim 12 , wherein the target computing device is selected from a group comprising: an embedded mobile PDA (personal digital assistant); a cell phone; a smart phone; a notebook computer; a desktop PC (personal computer); a workstation; a server; a mainframe computer; and an Internet appliance.
an embedded mobile PDA (personal digital assistant);
A method comprising generating a power profile that associates a software instruction with an amount of power consumed during execution of the software instruction.
A method as recited in claim 17 , wherein the execution of the software instruction is performed by a processor on a target computing device and the amount of power consumed is an amount of power consumed by the processor.
A method as recited in claim 17 , wherein the generating comprises: identifying the software instruction executing on a processor; receiving power consumption data from a power measurement circuit; and correlating the power consumption data with the identified software instruction.
identifying the software instruction executing on a processor;
correlating the power consumption data with the identified software instruction.
A computer comprising a power profiler configured to identify software instructions executing on a processor, receive power consumption data, and correlate the power consumption data with the software instructions such that each software instruction is associated with a power consumption value indicating an amount of power consumed during the executing of the software instruction.
A computer as recited in claim 20 , further comprising a lookup table, the power profiler further configured to monitor a program counter on the processor and to identify the software instructions through the lookup table based on the program counter.
A computer as recited in claim 20 , further comprising a power profile having a plurality of power consumption values each paired with a corresponding software instruction to indicate an amount of power consumed during execution of the corresponding software instruction.
A computer comprising a power profiler configured to generate a power profile that correlates software instructions with power consumed during execution of the software instructions.
A computer comprising: means for identifying instructions executing on a processor; means for receiving power consumption data from a power measurement circuit; and means for generating a power profile that correlates the power consumption data with the identified instructions.
means for identifying instructions executing on a processor;
means for receiving power consumption data from a power measurement circuit; and
means for generating a power profile that correlates the power consumption data with the identified instructions.
A computer as recited in claim 24 , wherein the means for identifying instructions comprises: means for interrupting the processor; means for sampling a program counter of the processor; and means for determining an instruction based on the program counter.
means for interrupting the processor;
means for sampling a program counter of the processor; and
means for determining an instruction based on the program counter.
A computer as recited in claim 24 , wherein the means for receiving comprises: means for querying the power measurement circuit; and means for receiving digital power readings from the power measurement circuit based on the querying.
means for querying the power measurement circuit; and
means for receiving digital power readings from the power measurement circuit based on the querying.
A power measurement circuit comprising: means for measuring power consumption of software instructions executing on an embedded device; means for converting analog power measurements into digital power measurements; and means for transmitting the digital power measurements to a host computer in response to a query from the host computer.
means for measuring power consumption of software instructions executing on an embedded device;
means for converting analog power measurements into digital power measurements; and
means for transmitting the digital power measurements to a host computer in response to a query from the host computer.
A power measurement circuit as recited in claim 27 , further comprising means for storing the digital power measurements.
A computer comprising: a processor; instructions stored in a memory and executable on the processor; and a power measurement circuit configured to measure power consumed by the processor during execution of each instruction.
instructions stored in a memory and executable on the processor; and
a power measurement circuit configured to measure power consumed by the processor during execution of each instruction.
A computer as recited in claim 29 , further comprising an analog to digital converter integrated as part of the power measurement circuit and configured to convert analog power signals to digital power consumption data.
The computer of claim 29 implemented as a device selected from the group comprising: an embedded mobile PDA (personal digital assistant); a cell phone; a smart phone; a notebook computer; a desktop PC (personal computer); a workstation; a server; a mainframe computer; and an Internet appliance.
A system comprising: a power profiler configured to correlate an identified software instruction with an amount of power consumed during execution of the identified software instruction; a lookup table having information for identifying the identified software instruction; and a power profile generated by the power profiler and having power consumption values and identified software instructions, each power consumption value paired with a corresponding identified software instruction.
a power profiler configured to correlate an identified software instruction with an amount of power consumed during execution of the identified software instruction;
a lookup table having information for identifying the identified software instruction; and
a power profile generated by the power profiler and having power consumption values and identified software instructions, each power consumption value paired with a corresponding identified software instruction.
A system as recited in claim 32 , further comprising: a power measurement circuit configured to measure the amount of power consumed during execution of the identified software instruction; and an analog to digital converter configured as part of the power measurement circuit to convert analog power consumption measurements into digital power consumption data.
a power measurement circuit configured to measure the amount of power consumed during execution of the identified software instruction; and
an analog to digital converter configured as part of the power measurement circuit to convert analog power consumption measurements into digital power consumption data.
A system as recited in claim 33 , wherein the power measurement circuit is a component of a target computing device on which the identified software instruction is executed.
Ref US20040268159: Claims:
1. A processor-readable medium comprising processor-executable instructions configured for: 
identifying instructions executing on a processor;  receiving power consumption data from a power measurement circuit; and  correlating the power consumption data with the identified instructions.
2. A processor-readable medium as recited in claim 1, wherein the identifying comprises: 
interrupting the processor;  sampling a program counter of the processor;  scanning a lookup table to find an address indicated by the program counter; and  determining an instruction located at the address.
3. A processor-readable medium as recited in claim 1, wherein the receiving comprises: 
querying the power measurement circuit; and  receiving digital power readings from the power measurement circuit based on the querying.
4. A processor-readable medium as recited in claim 1, wherein the receiving comprises receiving digital power readings from the power measurement circuit at preset time intervals.
5. A processor-readable medium as recited in claim 1, wherein the correlating comprises associating with an identified instruction, a measured amount of power consumed during execution of the identified instruction on the processor.
6. A processor-readable medium as recited in claim 1, wherein the correlating comprises generating a power profile that includes a plurality of power consumption values and a plurality of identified instructions, wherein each power consumption value is associated with an identified instruction in the power profile.
7. A processor-readable medium as recited in claim 6, wherein the power profile is selected from the group comprising: 
a table having pairs of data, each pair of data comprising a power consumption value and an identified instruction; and  a graph correlating power consumption values with identified instructions.
8. A processor-readable medium as recited in claim 1, wherein the power consumption data comprises power consumption values measured during execution of the instructions on the processor.
9. A processor-readable medium as recited in claim 1, wherein the processor is a component of a device selected from the group comprising: 
an embedded mobile PDA (personal digital assistant) computing device operable by battery power;  a cell phone;  a smart phone;  a notebook computer;  a desktop PC (personal computer);  a workstation;  a server;  a mainframe computer; and  an Internet appliance.
10. A processor-readable medium comprising processor-executable instructions configured for associating a software instruction with an amount of power consumed by executing the software instruction.
11. A processor-readable medium as recited in claim 10, wherein the associating comprises generating a power profile that matches software instructions executing on an embedded device with corresponding power consumption values measured during execution of the software instructions.
12. A processor-readable medium comprising processor-executable instructions configured for: 
measuring power consumption of software instructions executing on a target computing device;  converting analog power measurements into digital power measurements; and  transmitting the digital power measurements to a host computer.
13. A processor-readable medium as recited in claim 12, comprising further processor-executable instructions configured for storing the digital power measurements in a memory after the converting.
14. A processor-readable medium as recited in claim 12, wherein the transmitting comprises: 
receiving a request for the digital power measurements from the host computer; and  transmitting the digital power measurements to the host computer based on the request.
15. A processor-readable medium as recited in claim 12, wherein the transmitting comprises transmitting the digital power measurements to the host computer at preset time intervals.
16. A processor-readable medium as recited in claim 12, wherein the target computing device is selected from a group comprising: 
an embedded mobile PDA (personal digital assistant);  a cell phone;  a smart phone;  a notebook computer;  a desktop PC (personal computer);  a workstation;  a server;  a mainframe computer; and  an Internet appliance.
17. A method comprising generating a power profile that associates a software instruction with an amount of power consumed during execution of the software instruction.
18. A method as recited in claim 17, wherein the execution of the software instruction is performed by a processor on a target computing device and the amount of power consumed is an amount of power consumed by the processor.
19. A method as recited in claim 17, wherein the generating comprises: 
identifying the software instruction executing on a processor;  receiving power consumption data from a power measurement circuit; and  correlating the power consumption data with the identified software instruction.
20. A computer comprising a power profiler configured to identify software instructions executing on a processor, receive power consumption data, and correlate the power consumption data with the software instructions such that each software instruction is associated with a power consumption value indicating an amount of power consumed during the executing of the software instruction.
21. A computer as recited in claim 20, further comprising a lookup table, the power profiler further configured to monitor a program counter on the processor and to identify the software instructions through the lookup table based on the program counter.
22. A computer as recited in claim 20, further comprising a power profile having a plurality of power consumption values each paired with a corresponding software instruction to indicate an amount of power consumed during execution of the corresponding software instruction.
23. A computer comprising a power profiler configured to generate a power profile that correlates software instructions with power consumed during execution of the software instructions.
24. A computer comprising: 
means for identifying instructions executing on a processor;  means for receiving power consumption data from a power measurement circuit; and  means for generating a power profile that correlates the power consumption data with the identified instructions.
25. A computer as recited in claim 24, wherein the means for identifying instructions comprises: 
means for interrupting the processor;  means for sampling a program counter of the processor; and  means for determining an instruction based on the program counter.
26. A computer as recited in claim 24, wherein the means for receiving comprises: 
means for querying the power measurement circuit; and  means for receiving digital power readings from the power measurement circuit based on the querying.
27. A power measurement circuit comprising: 
means for measuring power consumption of software instructions executing on an embedded device;  means for converting analog power measurements into digital power measurements; and  means for transmitting the digital power measurements to a host computer in response to a query from the host computer.
28. A power measurement circuit as recited in claim 27, further comprising means for storing the digital power measurements.
29. A computer comprising: 
a processor;  instructions stored in a memory and executable on the processor; and  a power measurement circuit configured to measure power consumed by the processor during execution of each instruction.
30. A computer as recited in claim 29, further comprising an analog to digital converter integrated as pa
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