Office Action 1: Non-Final Rejection (2025-03-13)
Rejection types: document_number: US-11699636-B2
date: 2023-07-11
name: Do; Jung Ho
cpc_classification: H01L21/028

CLAIMS:
WHAT IS CLAIMED IS:
1\. An integrated circuit device comprising: a substrate; an upper transistor; a lower transistor that is between, in a vertical direction, the substrate and the upper transistor; and a power via that is adjacent and overlaps, in a horizontal direction, a sidewall of the lower transistor and a sidewall of the upper transistor.
2\. The integrated circuit device of Claim 1, wherein the power via is electrically connected to the upper transistor.
3\. The integrated circuit device of Claim 2, wherein the upper transistor is a P-type transistor, and wherein the lower transistor is an N-type transistor.
4\. The integrated circuit device of Claim 3, wherein the power via is electrically connected to a source/drain region of the P-type transistor.
5\. The integrated circuit device of Claim 1, further comprising a power line, wherein the upper transistor is electrically connected to the power line by the power via.
6\. The integrated circuit device of Claim 5, wherein the power line is in the substrate.
7\. The integrated circuit device of Claim 1, wherein an uppermost surface of the power via is at a higher level, in the vertical direction, than an uppermost surface of a channel region of the upper transistor.
8\. The integrated circuit device of Claim 1, wherein a lowermost surface of the power via is at a lower level, in the vertical direction, than a lowermost surface of a channel region of the lower transistor.
9\. The integrated circuit device of Claim 1, wherein the upper transistor and the lower transistor each include nanosheets.
10\. The integrated circuit device of Claim 1, further comprising a contact on and electrically connected to the upper transistor, wherein the power via is electrically connected to the contact.
11\. An integrated circuit device comprising: a standard cell that includes a transistor; and a power via that is electrically connected to the transistor and is adjacent and overlaps, in a horizontal direction, a sidewall of the transistor, wherein the power via is at a cell boundary of the standard cell.
12\. The integrated circuit device of Claim 11, further comprising a contact that is on and electrically connected to a source/drain region of the transistor, wherein the power via is electrically connected to the source/drain region of the transistor by the contact.
13\. The integrated circuit device of Claim 12, wherein the power via is in contact with the contact.
14\. The integrated circuit device of Claim 11, further comprising: a second standard cell that includes a second transistor; and a second power via that is adjacent and overlaps, in the horizontal direction, a sidewall of the second transistor, wherein the standard cell and the second standard cell are in different rows of standard cells, and wherein the second power via is aligned, in the horizontal direction, with the power via and is at a cell boundary of the second standard cell.
15\. The integrated circuit device of Claim 11, further comprising: a second standard cell that includes a second transistor; and a second power via that is adjacent and overlaps, in the horizontal direction, a sidewall of the second transistor, wherein the standard cell and the second standard cell are in the same row of standard cells, wherein the second power is aligned with the power via along a second horizontal direction that intersects the horizontal direction.
16\. The integrated circuit device of Claim 11, further comprising a power line that is electrically connected to the transistor by the power via, wherein the power via overlaps the power line in a vertical direction, and wherein the power line is at the cell boundary.
17\. The integrated circuit device of Claim 16, wherein an uppermost surface of the power line is at a lower level, in the vertical direction, than a lowermost surface of the transistor.
18\. The integrated circuit device of Claim 11, wherein an uppermost surface of the power via is at a higher level, in a vertical direction, than an uppermost surface of a channel region of the transistor.
19\. The integrated circuit device of Claim 11, wherein a lowermost surface of the power via is at a lower level, in a vertical direction, than a lowermost surface of a channel region of the transistor.
20\. The integrated circuit device of Claim 11, wherein the transistor includes nanosheets.

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 4/25/2024 and 2/3/2025 are being acknowledged and considered by the examiner.
Obviousness Typed Double Patenting
Statutory Basis
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the right to exclude granted by a patent and to prevent possible harassment by multiple assignees.  See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application.  See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer.  A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
The Rejections
Claims 1-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-9 of U.S. Patent No. 11,699,636.
Although the conflicting claims are not identical, they are claiming common subject matter, as follows: both U.S. Patent and instant application claimed an integrated circuit device. Specifically, regarding claim 1 of instant application discloses an integrated circuit device (claim 1 of Pat. 11,699,636, column 12, line 61) comprising: a substrate (claim 1 of Pat. 11,699,636, column 12, line 62); an upper transistor (claim 1 of Pat. 11,699,636, column 13, line 3); a lower transistor that is between, in a vertical direction, the substrate and the upper transistor (claim 1 of Pat. 11,699,636, column 13, lines 9-10); and a power via that is adjacent and overlaps, in a horizontal direction, a sidewall of the lower transistor and a sidewall of the upper transistor (claim 1 of Pat. 11,699,636, column 13, lines 15-22 and claim 5, column 14, lines 8-10).
Although the conflicting claims are not identical, they are not patentably distinct from each other because as follows: both U.S. Patent and instant application claimed a semiconductor structure. Moreover, the claims 1-9 in the U.S. Patent No. 11,699,636 are either narrower or broader version of the claims of the instant application by omitting limitations or obvious variations thereof. The facts are that the claims of the U.S. Patent No. 11,699,636 and instant application have claimed the same goal and are not distinguished from each other.
For these reasons, claim 1-20 are seen as obvious variations of the patented claims.
Conclusion


NEXT OFFICE ACTION: DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on March 24, 2025 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of the US Patent Number 11,699,636 has been reviewed and is accepted.  The terminal disclaimer has been recorded.
The assignment document filed on March 24, 2025 is acceptable as the documentary evidence required by 37 CFR 3.73.  If the assignment document is not already recorded with the Patent and Trademark Office, it is suggested that the assignment document be submitted for recording among the Office assignment records.  See 37 CFR 3.11 and MPEP § 302.
Allowable Subject Matter
Claims 1-20 are allowed.
The following is an examiner's statement of reasons for allowance:  The invention is allowable after it was rejected as Obvious Double Patenting in the first office action.  However, the applicant filed terminal disclaimer in a timely manner in compliance with 37 CFR 1.321(c).  It may be used to overcome an actual patent is shown to be commonly owned with this application.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee.  Such submissions should be clearly labeled Comments on Statement of Reasons for Allowance.”
Conclusion

CITED REFERENCE SUMMARIES: Ref US11699636: Claims:
1. An integrated circuit device comprising:
a plurality of standard cells arranged on a substrate in multiple rows that each extend in a first direction, wherein the plurality of standard cells comprises a first standard cell in a first row and a second standard cell in a second row that is immediately adjacent to the first row,
wherein each of the first and second standard cells comprises:
an upper transistor comprising:
an upper active region;
an upper gate structure on the upper active region; and
an upper source/drain region on the upper active region;

a lower transistor between the substrate and the upper transistor, the lower transistor comprising:
a lower active region;
a lower gate structure on the lower active region; and
a lower source/drain region on the lower active region;

a first power line and a second power line;
a first power via electrically connecting the first power line to the lower source/drain region; and
a second power via electrically connecting the second power line to the upper source/drain region, and
wherein the first power via of the first standard cell and the first power via of the second standard cell are aligned with each other along the first direction.
2. The integrated circuit device of claim 1, wherein the first and second power vias of the first standard cell are spaced apart from each other in a second direction that traverses the first direction.
3. The integrated circuit device of claim 2, wherein, in the first standard cell, the lower transistor is between the upper transistor and the first and second power lines.
4. The integrated circuit device of claim 2, wherein the second direction is perpendicular to the first direction, and the first and second power vias of the first standard cell are aligned with each other along the second direction.
5. The integrated circuit device of claim 1, wherein, in the first standard cell, the second power via vertically overlaps the first power via.
6. The integrated circuit device of claim 5, wherein, in the first standard cell, the lower transistor is between the upper transistor and the first power line, and the upper transistor is between the lower transistor and the second power line.
7. The integrated circuit device of claim 1, wherein, in the first standard cell, the upper active region extends longitudinally in the first direction, and the upper gate structure is spaced apart from the upper source/drain region in the first direction.
8. The integrated circuit device of claim 1, wherein the first standard cell and the second standard cell are the same kind of standard cell.
9. The integrated circuit device of claim 1, wherein the first standard cell and the second standard cell are each an inverter.