Office Action 1: Non-Final Rejection (2024-12-02)
Rejection types: 103 - Obviousness

CLAIMS:
Claims

What is claimed is:

1\. A method of manufacturing a semiconductor device, the method comprising:
performing one or more grinding processes on a backside surface of a device wafer to thin the device wafer from a first thickness to a second thickness;
performing a first chemical mechanical polish (CMP) process on the backside surface of the device wafer to thin the device wafer from the second thickness to
a third thickness; and
performing a second CMP process on the backside surface of the device wafer to selectively remove device wafer material that is disposed over an active device area of the semiconductor device, wherein a removal rate of the device wafer material is a function of depth.

2\. The method of claim 1, further comprising bonding a carrier wafer to the device wafer prior to performing the one or more grinding processes.

3\. The method of claim 2, wherein the carrier wafer is made of silicon, quartz, or glass.

4\. The method of claim 1, wherein the device wafer comprises:
the active device area disposed at a frontside surface of the device wafer;
a first isolation region disposed at the frontside surface of the device wafer
and adjacent to a first edge of the active device area; and
a second isolation region disposed at the frontside surface of the device wafer and adjacent to a second edge of the active device area.
5\. The method of claim 4, wherein performing the second CMP process on the backside surface of the device wafer to selectively remove bulk device wafer material that is disposed over the active device area of the semiconductor device produces a trench between the first isolation region and the second isolation region and exposes a backside surface of the active device area.

6\. The method of claim 5, wherein the trench has a depth of approximately one hundred nanometers.

7\. The method of claim 5, further comprising forming a mold compound in the trench.

8\. The method of claim 7, wherein the mold compound is thermally conductive and is included in a heat transfer path for the semiconductor device.

9\. The method of claim 1, further comprising:
bonding a carrier wafer to the device wafer prior to performing the one or
more grinding processes; and
removing the carrier wafer after forming the mold compound in the trench.

10\. The method of claim 1, wherein the device wafer is a silicon wafer.

11\. The method of claim 1, wherein the first thickness is approximately seven hundred and twenty-five micrometers and the second thickness is approximately five micrometers.

12\. The method of claim 1, wherein the third thickness is approximately two hundred and fifty nanometers.

13\. The method of claim 1, wherein performing the one or more grinding processes on the backside surface of the device wafer to thin the device wafer from the first thickness to the second thickness comprises performing a first grinding process and a second grinding process.

14\. The method of claim 13, further comprising adjusting at least one first grinding parameter during performance of the first grinding process based on a first total thickness variation (TTV), the at least one first grinding parameter comprising a revolutions per minute (rpm) of a spindle in a grinding tool or a wheel type used in the grinding tool.

15\. The method of claim 13, further comprising adjusting at least one first grinding parameter during performance of the first grinding process based on a first total thickness variation (TTV), the at least one first grinding parameter comprising a revolutions per minute (rpm) of a stage of the grinding tool or a tilt of the stage of the grinding tool.

16\. The method of claim 13, further comprising adjusting at least one second grinding parameter during performance of the second grinding process based on a second total thickness variation (TTV), the at least one second grinding parameter comprising a revolutions per minute (rpm) of a spindle in a grinding tool, a wheel type used in the grinding tool, an rpm of a stage of the grinding tool, or a tilt of the stage of the grinding tool.

17\. The method of claim 1, wherein performing the first CMP process on the backside surface of the device wafer further comprises adjusting at least one CMP parameter based on a thickness profile for the device wafer, the at least CMP parameter comprising the thickness profile of the device wafer or a slurry flow rate.

18.The method of claim 1, wherein performing the first CMP process on the backside surface of the device wafer further comprises adjusting at least one CMP parameter based on a thickness profile for the device wafer, the at least CMP parameter comprising a revolutions per minute (rpm) of a polish head of a polishing tool or an rpm of a platen of the polishing tool.
19.The method of claim 1, wherein performing the first CMP process on the backside surface of the device wafer further comprises adjusting at least one CMP parameter based on a thickness profile for the device wafer, the at least CMP parameter comprising at least one zonal pressure of a polish head of a polishing tool. 5 10 15 20 25 30

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-12 and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schmidt et al. (2021/0249503) in view of Chung et al. (2020/0094369).
Regarding claim 1, Schmidt (Fig. 8d) discloses a method of manufacturing a semiconductor device ([0001]), the method comprising: performing one or more grinding processes on a backside surface 10b of a device wafer 200 to thin the device wafer 200 from a first thickness (T1) to a second thickness (Fig. 8d, [0064-0066]); performing a first chemical mechanical polish (CMP) process on the backside surface 10b of the device wafer 200 to thin the device wafer 200 from the second thickness to a third thickness T3 (Fig. 8d, [0065]); and wherein a removal rate of the device wafer material is a function of depth (Fig. 8d, [0059-0061]).
Schmidt discloses all the limitation as discussed above except for performing a second CMP process on the backside surface of the device wafer.
However, Chung (Fig. 5B) discloses performing a first chemical mechanical polish (CMP) process on the surface (A, B) of the device wafer 500 to thin the device wafer 500 from the second thickness to another thickness (Fig. 5B, [0041], [0043-0046]); and performing a second CMP process on the surface (A) of the fixture wafer 500 to selectively remove device wafer material that is disposed over an active device area of the semiconductor device (Fig. 5C, [0048]-[0050]), wherein a removal rate of the device wafer material is a function of depth (Fig. 5B, [0041], [0043-0046]).
Accordingly, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the methods of Schmidt by performing a second CMP process on the surface of the fixture wafer to selectively remove device wafer material that is disposed over an active device area of the semiconductor device, because such the CMP process is one of the alternative methods and is also one of the conventional methods used for removing the wafer in the semiconductor device as taught by Chung (Figs. 5B-5C, [0041], [0043-0046] and [0048]-[0050]).
Regarding claim 2, Schmidt (Fig. 8d) discloses further comprising bonding a carrier wafer to the device wafer prior to performing the one or more grinding processes (Fig. 8d, [0064-0066]).
Regarding claim 3, Schmidt (Fig. 8d) discloses wherein the carrier wafer is made of silicon, quartz, or glass (Fig. 8d, [0066]).
Regarding claim 4, Schmidt (Fig. 8b) discloses wherein the device wafer comprises: the active device area disposed at a frontside surface of the device wafer; a first isolation region disposed at the frontside surface of the device wafer and adjacent to a first edge of the active device area; and a second isolation region disposed at the frontside surface of the device wafer and adjacent to a second edge of the active device area (Fig. 8b, [0058]-[0060]).
Regarding claim 5, as discussed, the combination above, Chung (Fig. 5B) discloses wherein performing the second CMP process on the backside surface of the device wafer to selectively remove bulk device wafer material that is disposed over the active device area of the semiconductor device produces a trench between the first isolation region and the second isolation region and exposes a backside surface of the active device area (Fig. 5C, [0048]-[0050]).
Regarding claims 6 and 11-12, Schmidt and Chung disclose all the claimed limitations except for the trench has a depth of approximately one hundred nanometers (in claim 6); the first thickness is approximately seven hundred and twenty-five micrometers and the second thickness is approximately five micrometers (claim 11); and the third thickness is approximately two hundred and fifty nanometers (claim 12).
However, the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.  In Gardner v. TEC Systems, Inc., 725 F. 2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to form the trench has a depth of approximately one hundred nanometers (in claim 6); the first thickness is approximately seven hundred and twenty-five micrometers and the second thickness is approximately five micrometers (claim 11); and the third thickness is approximately two hundred and fifty nanometers (claim 12) as claimed, because the dimensions can be varied depending upon the device in a particular application.
Regarding claim 7, as discussed, the combination above, Chung (Figs. 5D and 5E) discloses further comprising forming a mold compound 544 in the trench 542 ([0050]).
Regarding claim 9, Schmidt (Fig. 8c) discloses further comprising: bonding a carrier wafer to the device wafer prior to performing the one or more grinding processes; and removing the carrier wafer after forming the mold compound in the trench ([0044] and [0061]).
Regarding claim 10, Schmidt (Fig. 8d) discloses wherein the device wafer is a silicon wafer ([0066]).
Regarding claim 17, as discussed, the combination above, Chung (Figs. 5B-5E) discloses performing the first CMP process on the backside surface of the device wafer further comprises adjusting at least one CMP parameter based on a thickness profile for the device wafer, the at least CMP parameter comprising the thickness profile of the device wafer or a slurry flow rate ([0007], [0010] and [0033]).
Regarding claim 18, as discussed, the combination above, Chung (Figs. 5B-5E) discloses performing the first CMP process on the backside surface of the device wafer further comprises adjusting at least one CMP parameter based on a thickness profile for the device wafer, the at least CMP parameter comprising a revolutions per minute (rpm) of a polish head of a polishing tool or an rpm of a platen of the polishing tool ([0007], [0010] and [0033]).
Regarding claim 19, as discussed, the combination above, Chung (Figs. 5B-5E) discloses performing the first CMP process on the backside surface of the device wafer further comprises adjusting at least one CMP parameter based on a thickness profile for the device wafer, the at least CMP parameter comprising at least one zonal pressure of a polish head of a polishing tool ([0007], [0010] and [0033]).
Claim 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schmidt et al. (2021/0249503) in view of Chung et al. (2020/0094369) and further in view of Wan et al. (20200098666).
Regarding claim 8, Schmidt and Chung disclose all the claimed limitations except for the mold compound is thermally conductive and is included in a heat transfer path for the semiconductor device.
Wan (Fig. 1) discloses the mold compound 103 is thermally conductive and is included in a heat transfer path for the semiconductor device ([0030]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of Schmidt and Chung by forming the mold compound which is thermally conductive and is included in a heat transfer path for the semiconductor device as taught by Wan in order to create a heat path (Fig. 1, [0030]).
Claim 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schmidt et al. (2021/0249503) in view of Chung et al. (2020/0094369) and further in view of Chang (CN-1295762-C) as Applicant cited.
Regarding claim 13, Schmidt and Chung disclose all the claimed limitations except for performing the one or more grinding processes on the backside surface of the device wafer to thin the device wafer from the first thickness to the second thickness comprises performing a first grinding process and a second grinding process.
Chang (Figs. 1-4) discloses performing the one or more grinding processes on the backside surface of the device wafer to thin the device wafer from the first thickness to the second thickness comprises performing a first grinding process and a second grinding process
(page 1, para. 1 and page 2, para. 2). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of Schmidt and Chung by performing a first grinding process and a second grinding process as taught by Chang because such the grinding process is one of the conventional methods used in the semiconductor device (Figs. 1-4).
Allowable Subject Matter
Claims 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record fails to disclose all the limitations recited in the above claims. Specifically, the prior art of record fails to disclose further comprising adjusting at least one first grinding parameter during performance of the first grinding process based on a first total thickness variation (TTV), the at least one first grinding parameter comprising a revolutions per minute (rpm) of a spindle in a grinding tool or a wheel type used in the grinding tool (claim 14);  or further comprising adjusting at least one first grinding parameter during performance of the first grinding process based on a first total thickness variation (TTV), the at least one first grinding parameter comprising a revolutions per minute (rpm) of a stage of the grinding tool or a tilt of the stage of the grinding tool (claim 15); or further comprising adjusting at least one second grinding parameter during performance of the second grinding process based on a second total thickness variation (TTV), the at least one second grinding parameter comprising a revolutions per minute (rpm) of a spindle in a grinding tool, a wheel type used in the grinding tool, an rpm of a stage of the grinding tool, or a tilt of the stage of the grinding tool (claim 16).
Conclusion


NEXT OFFICE ACTION: DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The amendment filed on 02/18/25 has been acknowledged and entered. By this amendment claims 13-15 are cancelled and claims 1-12 and 16-20 are pending in the application.
Reasons for Allowance
Claims 1-12 and 16-20 are allowed.
The following is an examiner's statement of reasons for allowance:
The prior art of record neither anticipates nor renders obvious all the limitations in the base claims 1 and 20. Specifically, the combination of a method of manufacturing a semiconductor device, the method comprising: performing the one or more grinding processes on the backside surface of the device wafer to thin the device wafer from the first thickness to the second thickness comprises performing a first grinding process and a second grinding process; performing a first chemical mechanical polish (CMP) process on the backside surface of the device wafer to thin the device wafer from the second thickness to a third thickness; performing a second CMP process on the backside surface of the device wafer to selectively remove device wafer material that is disposed over an active device area of the semiconductor device, wherein a removal rate of the device wafer material is a function of depth; and adjusting at least one first grinding parameter during the performance of the first grinding process based on a first total thickness variation (TTV), the at least one first grinding parameter comprising a revolutions per minute (rpm) of a spindle in a grinding tool or a wheel type used in the grinding tool.
The dependent claims being further limiting and definite are also allowable.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee.  Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”

CITED REFERENCE SUMMARIES: Ref US20210249503A1: Claims:
A method of forming an integrated spiral inductor having low substrate loss, said method comprising the following operations: providing a semiconductor wafer having a semiconductor substrate, said semiconductor substrate having a first surface and a second surface, the first and second surfaces disposed on opposite sides of the substrate; disposing a multilayer isolation structure on said first surface; forming metal wiring embedded in the multilayer isolation structure; providing a high resistivity carrier wafer and attaching the carrier wafer to said semiconductor wafer so that the first surface of said semiconductor substrate faces towards the carrier wafer; thinning said semiconductor substrate from said second surface; creating at least one trench gap in the remaining semiconductor substrate from the thinned second surface; filling said at least one trench gap with dielectric layer; forming through-silicon vias, said through-silicon vias connecting the metal wiring embedded in the multilayer isolation structure; forming a spiral inductor on the dielectric layer using at least one conductive layer wherein said spiral inductor has an inductor coil with more than one winding, the step of forming a spiral inductor on the dielectric layer comprises the formation of a metal wire embedded in the multilayer isolation structure, the formation of through-silicon vias, and the formation of a conductive layer on the dielectric layer, embedded in a passivation layer, said through-silicon vias and said metal wire defining at least one underpass and said conductive layer defining the inductor coil.
providing a semiconductor wafer having a semiconductor substrate, said semiconductor substrate having a first surface and a second surface, the first and second surfaces disposed on opposite sides of the substrate;
disposing a multilayer isolation structure on said first surface;
forming metal wiring embedded in the multilayer isolation structure;
providing a high resistivity carrier wafer and attaching the carrier wafer to said semiconductor wafer so that the first surface of said semiconductor substrate faces towards the carrier wafer;
thinning said semiconductor substrate from said second surface;
creating at least one trench gap in the remaining semiconductor substrate from the thinned second surface;
filling said at least one trench gap with dielectric layer;
forming through-silicon vias, said through-silicon vias connecting the metal wiring embedded in the multilayer isolation structure;
forming a spiral inductor on the dielectric layer using at least one conductive layer wherein said spiral inductor has an inductor coil with more than one winding, the step of forming a spiral inductor on the dielectric layer comprises the formation of a metal wire embedded in the multilayer isolation structure, the formation of through-silicon vias, and the formation of a conductive layer on the dielectric layer, embedded in a passivation layer, said through-silicon vias and said metal wire defining at least one underpass and said conductive layer defining the inductor coil.
The method according to claim 1 wherein the carrier wafer is a high-ohmic silicon substrate having a resistivity in the range of 1 kOhm-cm to 10 kOhm-cm;
The method according to claim 1 wherein the carrier wafer is of dielectric material such as glass or of ceramic material such as sapphire.
The method according to claim 1 wherein the at least one trench gap created in the semiconductor substrate from the second surface extends to the multilayer isolation structure.
The method according to claim 4 wherein the dielectric layer filling the at least one trench gap is disposed also on the thinned second surface of the semiconductor substrate.
The method according to claim 1 wherein the material of the dielectric layer filling the trench gap is selected among the followings: Tetraethylorthosilicate (TEOS), spin-on glass (SOG), polyimide (PI), polybenzoxazole (PBO) or benzocyclobutene (BCB).
The method according to claim 1 wherein the spiral inductor formed on the dielectric layer is placed entirely within the region of the at least one trench-gap.
The method according to claim 1 wherein the through-silicon vias electrically connecting the spiral inductor to the metal wiring embedded in the multilayer isolation structure are placed entirely in said at least one trench gap filled with dielectric material.
The method according to claim 1 wherein the passivation layer may be selected among the followings: silicon oxide, low-k dielectric, spin-on dielectric such as polyimide (PI).
The method according to claim 1 wherein the thickness of said semiconductor substrate after the thinning step is less than 12 micrometers.
The method according to claim 1 wherein the thickness of said semiconductor substrate after the thinning step is less than 3 micrometers.
The method according to claim 1 wherein at least one bonding pad is disposed on the dielectric layer, said bonding pad being electrically connected to the metal wiring by said through-silicon vias.
The method according to claim 12 wherein the through-silicon vias ( 16 ) providing an electrical connection of said bonding pad ( 17 d ) to the metal wiring ( 15 ) are placed in a trench gap ( 21 b ) filled with the dielectric layer ( 21 ).
The method according to claim 1 wherein the step of forming through-silicon vias comprises the steps of: etching said through-silicon vias through the dielectric layer and through a portion of the multilayer dielectric by masked dry etch process, exposing the metal wiring at said through-silicon vias bottom, and filling said through-silicon vias with conductive material.
The method according to claim 1 wherein said conductive layer is made of metal materials selected among the followings: Cu, Au, Al.
A product chip having an integrated spiral inductor fabricated with the method according to claim 1 , comprising: a CMOS device circuit area comprising at least one MOS transistor; an area dedicated to the integrated spiral inductor; an I/O area comprising at least one bonding pad; wherein a trench gap is formed in the area dedicated to the spiral inductor where the silicon substrate is completely removed, said trench gap being filled with dielectric layer.
a CMOS device circuit area comprising at least one MOS transistor;
an area dedicated to the integrated spiral inductor;
an I/O area comprising at least one bonding pad;
wherein a trench gap is formed in the area dedicated to the spiral inductor where the silicon substrate is completely removed, said trench gap being filled with dielectric layer.
Ref US20200094369A1: Claims:
A method of performing chemical mechanical polishing (CMP) on a wafer, comprising: identifying a first zone and a second zone on a surface of the wafer, the first zone having a structure feature different from a structure feature of the second zone; achieving a first CMP target thickness on the first zone by polishing the wafer using a first CMP process that is selective to the structure feature of the second zone; and achieving the first CMP target thickness on the second zone by polishing the wafer using a second CMP process.
identifying a first zone and a second zone on a surface of the wafer, the first zone having a structure feature different from a structure feature of the second zone;
achieving a first CMP target thickness on the first zone by polishing the wafer using a first CMP process that is selective to the structure feature of the second zone; and
achieving the first CMP target thickness on the second zone by polishing the wafer using a second CMP process.
The method of claim 1 , wherein the first CMP process is selective to a structure feature in the second zone.
The method of claim 1 , wherein the second CMP process is selective to a structure feature in the first zone.
The method of claim 1 , further comprising achieving a second CMP target thickness on the first zone and the second zone together by polishing the wafer using a third CMP process.
The method of claim 4 , wherein the polishing the wafer using the third CMP process is one or more of having a lower polishing rate than the first CMP process and the second CMP process or a buffing polishing.
The method of claim 1 , wherein the polishing the wafer using the first CMP process includes applying a higher pushing pressure toward a wafer backside of the first zone than toward a wafer backside of the second zone.
The method of claim 1 , wherein the first zone and the second zone are substantially concentric among one another.
The method of claim 1 , before the polishing the wafer using the second CMP process, further comprising: removing a first structure feature having a first material from the second zone to generate a recess; and filing the recess with a second material that is different from the first material.
removing a first structure feature having a first material from the second zone to generate a recess; and
filing the recess with a second material that is different from the first material.
The method of claim 1 , wherein the polishing the wafer using the first CMP process includes a buffing polishing.
The method of claim 1 , wherein the polishing the wafer using the first CMP process and the polishing the wafer using the second CMP process are sequential to one another in time.
The method of claim 1 , wherein the first zone includes a long channel metal gate structure and the second zone includes a short channel metal gate structure.
The method of claim 1 , wherein the first zone and the second zone are different in a metal versus dielectric ratio.
The method of claim 1 , wherein the first zone and the second zone are different in a density of structure features.
A method of performing chemical mechanical polishing (CMP) on a wafer, comprising: identifying a first feature, a second feature, and a third feature on a surface of the wafer, the first feature being different from the second feature and the third feature; polishing the wafer using a first CMP process until the first feature reaches a first CMP target thickness; removing the third feature to form a recess; forming a fourth feature within the recess; and polishing the wafer using a second CMP process until the second feature reaches the first CMP target thickness.
identifying a first feature, a second feature, and a third feature on a surface of the wafer, the first feature being different from the second feature and the third feature;
polishing the wafer using a first CMP process until the first feature reaches a first CMP target thickness;
removing the third feature to form a recess;
forming a fourth feature within the recess; and
polishing the wafer using a second CMP process until the second feature reaches the first CMP target thickness.
The method of claim 14 , wherein the first CMP process is selective to the second feature and the second CMP process is selective to the first feature.
The method of claim 14 , further comprising reaching a second CMP target thickness on the first feature and the second feature by polishing the wafer using a third CMP process.
The method of claim 14 , wherein the polishing the wafer using the first CMP process includes applying a higher pushing pressure toward a wafer backside of the first feature than toward a wafer backside of the second feature.
A system for performing chemical mechanical polishing (CMP) on a wafer; comprising: a CMP platform; and a controller operable to control the CMP platform in polishing the wafer until a first target thickness is reached, the controller being configured to: identify a first zone and a second zone on a surface of the wafer, the first zone having a structure feature different from a structure feature of the second zone; control the CMP platform in polishing the wafer with a first CMP process until the first target thickness is reached on the first zone, the first CMP process being selective to the structure feature of the second zone; after the first target thickness is reached on the first zone, controlling the CMP platform to unload the wafer for a fabrication process different from CMP; and control the CMP platform in polishing the wafer with a second CMP process until the first target thickness is reached on the second zone, the second CMP process being selective to the structure feature of the first zone.
a CMP platform; and
a controller operable to control the CMP platform in polishing the wafer until a first target thickness is reached, the controller being configured to: identify a first zone and a second zone on a surface of the wafer, the first zone having a structure feature different from a structure feature of the second zone; control the CMP platform in polishing the wafer with a first CMP process until the first target thickness is reached on the first zone, the first CMP process being selective to the structure feature of the second zone; after the first target thickness is reached on the first zone, controlling the CMP platform to unload the wafer for a fabrication process different from CMP; and control the CMP platform in polishing the wafer with a second CMP process until the first target thickness is reached on the second zone, the second CMP process being selective to the structure feature of the first zone.
identify a first zone and a second zone on a surface of the wafer, the first zone having a structure feature different from a structure feature of the second zone;
control the CMP platform in polishing the wafer with a first CMP process until the first target thickness is reached on the first zone, the first CMP process being selective to the structure feature of the second zone;
after the first target thickness is reached on the first zone, controlling the CMP platform to unload the wafer for a fabrication process different from CMP; and
control the CMP platform in polishing the wafer with a second CMP process until the first target thickness is reached on the second zone, the second CMP process being selective to the structure feature of the first zone.
The system of claim 18 , wherein the fabrication process is removing a metal structure from the first zone.
The system of claim 18 , wherein the controller identifies a first wafer surface area having a long channel gate structure as the first zone and identifies a second wafer surface area having a short channel gate structure as the second zone.
Ref US20200098666A1: Claims:
An integrated circuit package, comprising: a first die; a second die above the first die; a mold material over the first die and at least partially adjacent to the second die; a metal feature in thermal contact with the first die and having a surface that extends both vertically and laterally from a bottom surface of the mold material to an upper or side surface of the mold material; and a heat spreader in thermal contact with the metal feature.
a second die above the first die;
a mold material over the first die and at least partially adjacent to the second die;
a metal feature in thermal contact with the first die and having a surface that extends both vertically and laterally from a bottom surface of the mold material to an upper or side surface of the mold material; and
a heat spreader in thermal contact with the metal feature.
The integrated circuit package of claim 1 , wherein the metal feature is a slanted metal pillar that runs through at least a portion of the mold material.
The integrated circuit package of claim 2 , wherein the slanted metal pillar slants from the vertical axis at an angle in the range of 5 to 60 degrees.
The integrated circuit package of claim 2 , wherein the slanted metal pillar is one of a plurality of metal pillars in the mold material.
The integrated circuit package of claim 2 , wherein the slanted metal pillar thermally connects the first die to the heat spreader.
The integrated circuit package of claim 1 , wherein the metal feature is a metal body on the first die and that extends under at least a portion of the mold material.
The integrated circuit package of claim 6 , wherein the metal body has a major surface that slopes at an angle in the range of 5 to 60 degrees.
The integrated circuit package of claim 7 , wherein the major surface is nonlinear.
The integrated circuit package of claim 6 , wherein the metal body thermally connects the first die to one or both of the heat spreader and the second die.
The integrated circuit package of claim 1 , wherein the heat spreader is integrated with a package to provide an enclosed area, and the first die, second die, mold material, and metal feature are within the enclosed area.
The integrated circuit package of claim 1 , wherein the metal feature is copper or silver.
An integrated circuit package, comprising: a package integrated with a heat spreader thereby defining an internal volume; a first die within the internal volume; a second die within the internal volume and above the first die; a mold material within the internal volume and over the first die and at least partially adjacent to the second die; a metal feature in thermal contact with the first die and having a surface that extends both vertically and laterally from a bottom surface of the mold material to an upper or side surface of the mold material; and a bonding material thermally connecting the heat spreader to the second die.
a package integrated with a heat spreader thereby defining an internal volume;
a first die within the internal volume;
a second die within the internal volume and above the first die;
a mold material within the internal volume and over the first die and at least partially adjacent to the second die;
a bonding material thermally connecting the heat spreader to the second die.
The integrated circuit package of claim 12 , wherein the metal feature is a slanted metal pillar that runs through at least a portion of the mold material.
The integrated circuit package of claim 13 , wherein the slanted metal pillar slants from the vertical axis at an angle in the range of 5 to 60 degrees.
The integrated circuit package of claim 13 , wherein the slanted metal pillar thermally connects the first die to one or both of the heat spreader and the second die.
The integrated circuit package of claim 12 , wherein the metal feature is a metal body on the first die and that extends under at least a portion of the mold material, and wherein the metal body thermally connects the first die to one or both of the heat spreader and the second die.
The integrated circuit package of claim 16 , wherein the metal body has a major surface that slopes at an angle in the range of 5 to 60 degrees.
The integrated circuit package of claim 17 , wherein the major surface is stepped or curvilinear.
A method forming an integrated circuit package, comprising: forming a metal feature in thermal contact with a first die; depositing a mold material over the first die and at least partially adjacent to a second die, the second die being above the first die in a stacked-die configuration; providing a heat spreader in thermal contact with the metal feature; and integrating the heat spreader with a package to provide an enclosed area, the first die, second die, mold material, and metal feature being within the enclosed area; wherein the metal feature has a surface that extends both vertically and laterally from a bottom surface of the mold material to an upper or side surface of the mold material.
forming a metal feature in thermal contact with a first die;
depositing a mold material over the first die and at least partially adjacent to a second die, the second die being above the first die in a stacked-die configuration;
providing a heat spreader in thermal contact with the metal feature; and
integrating the heat spreader with a package to provide an enclosed area, the first die, second die, mold material, and metal feature being within the enclosed area;
wherein the me
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