Office Action 1: Notice of Allowance (2025-02-26)

CLAIMS:
CLAIMS
1\. A system with a low-drift on-chip oscillator (10) with lowered sensitivity to Random Telegraph Noise, for generating a current (Id) in operation for the LD-RC oscillator (10), said system comprising a control resistor (R) connected through an intermediary arrangement (50) to one of a first MOS transistor (M1) or of a second MOS transistor (M2) between two terminals of a supply voltage source (Vdd), the gate of the first MOS transistor (M1) is connected to the gate of the second MOS transistor (M2), whereas the source of the first MOS transistor (M1) and the source of the second MOS transistor (M2) are connected in direction to a first terminal of the supply voltage source (Vdd), the control resistor (R) being connected to a second terminal opposite to the first terminal of the supply voltage source, and the system comprising still a feedback unit, which is an operational amplifier (40) for a comparison of the voltage (Vr) generated by the current (Is) through the control resistor R and the supply voltage (Vc) generated by the current (Id) through the LD-RC oscillator, the output (VrP) of the operational amplifier (40) being connected to gates of the first and second MOS transistors (M1, M2), the intermediary arrangement (50) including chopping switches (S1A, S1B, S2B, S2A) controlled by a switch control unit (30) which is intended to be clocked by the frequency signal (F0) of the LD-RC oscillator (10) in operation and placed between the control resistor (R) and the first and second MOS transistors (M1, M2), and between the LD-RC oscillator (10) and the first and second MOS transistors (M1, M2),a first controlled chopping switch (S1A) being placed between the control resistor (R) and the drain of the first MOS transistor (M1) of a first branch, whereas a second controlled chopping switch (S1B) is placed between the LD-RC oscillator (10) and the drain of the second MOS transistor (M2) of a second branch, a third controlled chopping switch (S2B) being placed between the control resistor (R) and the drain of the second MOS transistor (M2), whereas a fourth controlled chopping switch (S2A) is placed between the LD-RC oscillator (10) and the drain of the first MOS transistor (M1), the first and second switches (S1A, S1B) being intended to be controlled by a first control signal (PH1) from the switch control unit (30) intended to be in conducting mode during a first phase P1, whereas the third and fourth switches (S2B, S2A) are intended to be controlled by a second control signal (PH2) from the switch control unit (30) intended to be in non-conductive mode during a first phase P1, and the third and fourth switches (S2B, S2A) being intended to be controlled by the second control signal (PH2) intended to be in conducting mode during a second phase P2, whereas the first and second switches (S1A, S1B) are intended to be controlled by the first control signal (PH1) intended to be in non-conductive mode during the second phase P2, characterized in that the LD-RC oscillator is a ring oscillator (10) having an odd number n of inverters (11, 12, 13), which are connected in series to form a ring.
2\. The system according to claim 1, characterized in that the ring oscillator (10) comprises three inverters (11, 12, 13) connected in series, an output of the first inverter (11) being connected to an input of the second inverter (12), an output of the second inverter (12) being connected to an input of the third inverter (13), and an output of the third inverter (13) being connected to an input of the first inverter (11) in order to form a ring, the output of the third inverter (13) generating the frequency signal (F0), which is an oscillating signal at a frequency F0, and in that the oscillating signal is a sinusoidal signal or a square signal or a triangular signal or a sawtooth signal.
3\. The system according to claim 2, characterized in that each inverter (11, 12, 13) has an intrinsic capacitor Co, and in that in operation, the current Id is defined by the equation : Id = F0·C·Vc, with C = n·Co and Vc being the voltage across a capacitor Cc connected to the inverters (11, 12, 13) and is the voltage supply for each inverter (11, 12, 13) of the ring oscillator (10) of the system with respect to the second supply terminal, and which is provided to be always active during different system intervals or times, in particular during sleep times of the system.
4\. The system according to claim 1, characterized in that the first and second MOS transistors (M1, M2) are PMOS transistors with their source connected to the first terminal, which is the terminal of the supply voltage Vdd, and in that the control resistor (R) and the LD-RC oscillator (10) are connected to the second terminal, which is the ground.
5\. The system according to claim 1, characterized in that cascade MOS transistors (M3, M4) are added and placed between the arrangement of controlled chopping switches (S1A, S1B, S2A, S2B), and the control resistor (R) and also the LD-RC oscillator (10), in that a first cascode MOS transistor (M3) is connected to the resistor (R) in one side and in other side to the first and third switches (S1A, S2B), whereas a second cascode MOS transistor (M4) is connected in one side to the LD-RC oscillator (10), and in the other side to the second and fourth switches (S1B, S2A).
6\. The system according to claim 5, characterized in that cascode MOS transistors (M3, M4) are PMOS transistors, and in that first and second MOS transistors (M1, M2) are PMOS transistors with their source connected to the first terminal, which is the terminal of the supply voltage Vdd, whereas the control resistor (R) and the LD-RC oscillator (10) are connected to the second terminal, which is the ground.
7\. Method for lowering sensitivity to Random Telegraph Noise of a system with a low-drift on-chip oscillator (10) in an oscillator stage for generating a current (Id) for the LD-RC oscillator (10), said system comprising a control resistor (R) connected through an intermediary arrangement (50) to one of a first MOS transistor (M1) or of a second MOS transistor (M2) between two terminals of a supply voltage source (Vdd), the gate of the first MOS transistor (M1) being connected to the gate of the second MOS transistor (M2), whereas the source of the first MOS transistor (M1) and the source of the second MOS transistor (M2) are connected in direction to a first terminal of the supply voltage source (Vdd), the control resistor (R) being connected to a second terminal opposite to the first terminal of the supply voltage source (Vdd), and the system comprising in the oscillator stage still a feedback unit, which is an operational amplifier (40) in operation for the comparison between a voltage (Vr) generated by the current (Is) through the control resistor R and the supply voltage (Vc) generated by the current (Id) through the LD-RC oscillator (10), the output (VrP) of the operational amplifier (40) being connected to gates of the first and second MOS transistors (M1, M2), for implementing the method, the intermediary arrangement (50) includes first, second, third, fourth controlled chopping switches (S1A, S1B, S2B, S2A) controlled by a switch control unit (30), placed between the control resistor (R) and the first and second MOS transistors (M1, M2), and between the LD-RC oscillator (10) and the first and second MOS transistors (M1, M2), wherein a first controlled chopping switch (S1A) is placed between the control resistor (R) and the drain of the first MOS transistor (M1) of a first branch, whereas a second controlled chopping switch (S1B) is placed between the LD-RC oscillator (10) and the drain of the second MOS transistor (M2) of a second branch, and wherein a third controlled chopping switch (S2B) is placed between the control resistor (R) and the drain of the second MOS transistor (M2), whereas a fourth controlled chopping switch (S2A) is placed between the LD-RC oscillator (10) and the drain of the first MOS transistor (M1), and the first and second switches (S1A, S1B) being controlled by a first control signal (PH1) to be in conducting mode during a first phase P1, whereas the third and fourth switches (S2B, S2A) are controlled by a second control signal (PH2) to be in non-conductive mode during the first phase P1, the third and fourth switches (S2B, S2A) being controlled by the second control signal (PH2) to be in conducting mode during a second phase P2, whereas the first and second switches (S1A, S1B) are controlled by the first control signal (PH1) intended to be in non-conductive mode during the second phase P2, all the controlled chopping switches (S1A, S1B, S2B, S2A) being controlled by the switch control unit (30) at least during a predefined time, which is a sleep time (Tsleep), or all the time of some parts of the system other than the oscillator stage, and during the predefined time or all the time, phases P1 and phases P2 alternating successively in order to perform a chopping operation by commuting the first and second MOS transistors (M1, M2) from phase P1 to phase P2, and from phase P2 to phase P1, characterized in that the ring oscillator (10) made of an odd number n of CMOS inverters has the balance ensured via a feedback unit, which is implemented by an operational amplifier (40) in the depicted case.
8\. The method according to claim 7, characterized in that during a period corresponding to the predefined time or all the time, all the chopping switches (S1A, S1B, S2B, S2A) are commuted to pass successively from phase P1 to phase P2 and from phase P2 to phase P1, and each phase approximately during 50% of the time by phases P1 and 50% of time by phases P2.
9\. The method according to claim 7, characterized in that the oscillating signal (F0) from the LD-RC oscillator (10) is supplied to clock a timer of a switch logic unit (30) to determine a sleep time before waking up all the system.

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
EXAMINER’S AMENDMENT
An examiner’s amendment to the record appears below. Should the changes and/or additions be unacceptable to applicant, an amendment may be filed as provided by 37 CFR 1.312. To ensure consideration of such an amendment, it MUST be submitted no later than the payment of the issue fee.
The application has been amended as follows:
Claim 1, line 11: The phrase “the voltage (Vr) generated by the current (Is)” has been changed to—a voltage (Vr) generated by a current (Is)—to correct antecedent basis issues.
Claim 1, line 12: The phrase “the supply voltage” has been changed to—a supply voltage—to correct an antecedent basis issue.
Claim 1, line 13: The phrase “the output (VrP)” has been changed to—an output (VrP)—to correct an antecedent basis issue.
Claim 1, line 32: The phrase “a first phase P1” has been changed to—the first phase P1—to correct an antecedent basis issue.
Claim 7, line 12: The phrase “the current (Is)” has been changed to—a current (Is)—to correct an antecedent basis issue.
Claim 7, line 13: The phrase “the supply voltage” has been changed to—a supply voltage—to correct an antecedent basis issue.
Claim 7, line 14: The phrase “the output (VrP)” has been changed to—an output (VrP)—to correct an antecedent basis issue.
Claim 7, line 42: The phrase “wherein the ring oscillator made of” has been changed to—wherein the LD-RC oscillator is a ring oscillator having—to correct an antecedent basis issue. This language is taken from a similar limitation at the end of independent system claim 1.
Allowable Subject Matter
Claims 1-9 are allowed.
The following is an examiner’s statement of reasons for allowance:
The best prior art reference of record, Choo et al. (US 11,736,112; “Choo”), teaches a system (figures 5A, 10, 11B, 11C) with a low-drift on-chip oscillator (80) with lowered sensitivity to Random Telegraph Noise, for generating a current (ISUP) in operation for the LD-RC oscillator, said system comprising a control resistor (83) connected through an intermediary arrangement (81) to one of a first MOS transistor (X1 in figure 11B) or of a second MOS transistor (X1 in figure 11C) between two terminals of a supply voltage source (VDD), the gate of the first MOS transistor is connected to the gate of the second MOS transistor (at VBIAS), whereas the source of the first MOS transistor and the source of the second MOS transistor are connected in direction to a first terminal of the supply voltage source (VDD), the control resistor (83) being connected to a second terminal opposite to the first terminal of the supply voltage source, and the system comprising still a feedback unit, which is an operational amplifier (82) for a comparison of a voltage generated by a current (IREF) through the control resistor and a supply voltage generated by the current through the LD-RC oscillator, the output of the operational amplifier (82) being connected to gates of the first and second MOS transistors (X1),
the intermediary arrangement including chopping switches (receiving CTR1[1] in figure 11B and /CTR2[1] in figure 11C) controlled by a switch control unit (generating CTR) which is intended to be clocked by the frequency signal of the LD-RC oscillator in operation and placed between the control resistor and the first and second MOS transistors, and between the LD- RC oscillator and the first and second MOS transistors, a first controlled chopping switch (receiving CTR1[1] in figure 11B) being placed between the control resistor (83) and the drain of the first MOS transistor (X1) of a first branch, whereas a second controlled chopping switch (receiving /CTR2[1] in figure 11C) is placed between the LD-RC oscillator and the drain of the second MOS transistor (X1) of a second branch,
wherein the LD-RC oscillator is a ring oscillator (see figure 5) having an odd number n of inverters (INV1-INV5), which are connected in series to form a ring.
Choo fails to teach “a third controlled chopping switch being placed between the control resistor and the drain of the second MOS transistor, whereas a fourth controlled chopping switch is placed between the LD-RC oscillator and the drain of the first MOS transistor, whereas the third and fourth switches are intended to be controlled by a second control signal from the switch control unit intended to be in non-conductive mode during the first phase P1, and the third and fourth switches being intended to be controlled by the second control signal intended to be m conducting mode during a second phase P2”, as set forth in claim 1; and
“wherein a third controlled chopping switch is placed between the control resistor and the drain of the second MOS transistor, whereas a fourth controlled chopping switch is placed between the LD-RC oscillator and the drain of the first MOS transistor, and whereas the third and fourth switches are controlled by a second control signal to be in non-conductive mode during the first phase PH, the third and fourth switches being controlled by the second control signal to be in conducting mode during a second phase P2”, as set forth in claim 7.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee.  Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion



CITED REFERENCE SUMMARIES: Ref US11736112B2: Claims:
A digitally controlled oscillator (DCO) comprising: a current mirror configured to generate a supply current in response to a bias voltage corresponding to a reference current; a variable resistor connected to the current mirror through a first node outputting the reference current and configured to provide a variable resistance in response to a first control signal; an oscillation circuit connected to the current mirror through a second node outputting the supply current and configured to generate an oscillation signal in response to the supply current; and a feedback circuit configured to control the bias voltage in relation to at least one of a voltage at the first node and a voltage at the second node, wherein: the feedback circuit comprises: a first input terminal connected to the first node; a second input terminal connected to the second node; and an output terminal connected to a third node associated with the current mirror, the current mirror comprises: a bias circuit including the third node and configured to generate the bias voltage in response to the reference current and the first control signal; and a current source circuit configured to generate the supply current in response to the bias voltage, and the third node outputs the bias voltage to the current source circuit.
a current mirror configured to generate a supply current in response to a bias voltage corresponding to a reference current;
a variable resistor connected to the current mirror through a first node outputting the reference current and configured to provide a variable resistance in response to a first control signal;
an oscillation circuit connected to the current mirror through a second node outputting the supply current and configured to generate an oscillation signal in response to the supply current; and
a feedback circuit configured to control the bias voltage in relation to at least one of a voltage at the first node and a voltage at the second node, wherein:
the feedback circuit comprises: a first input terminal connected to the first node; a second input terminal connected to the second node; and an output terminal connected to a third node associated with the current mirror,
a first input terminal connected to the first node;
a second input terminal connected to the second node; and
an output terminal connected to a third node associated with the current mirror,
the current mirror comprises: a bias circuit including the third node and configured to generate the bias voltage in response to the reference current and the first control signal; and a current source circuit configured to generate the supply current in response to the bias voltage, and
a bias circuit including the third node and configured to generate the bias voltage in response to the reference current and the first control signal; and
a current source circuit configured to generate the supply current in response to the bias voltage, and
the third node outputs the bias voltage to the current source circuit.
The DCO of claim 1 , wherein the feedback circuit is further configured to increase the bias voltage in response to an increase in the voltage at the first node and decrease the bias voltage in response to a decrease in the voltage at the first node.
The DCO of claim 1 , wherein the feedback circuit comprises an amplifier configured to amplify a difference between the voltage at the first node and the voltage at the second node to generate feedback and provide the feedback to the current mirror.
The DCO of claim 3 , wherein the bias voltage is adjusted in response to the feedback.
The DCO of claim 1 , wherein the current source circuit is further configured to generate the supply current in response to a second control signal.
The DCO of claim 1 , further comprising a calibration circuit configured to calibrate the voltage at the first node in response to a change in resistance of the variable resistor due to a change in temperature.
The DCO of claim 6 , wherein the calibration circuit comprises: a calibration current source having a characteristic corresponding to a temperature change characteristic of the variable resistor, the calibration current source connected in parallel with the variable resistor between the first node and ground, and a calibration current source configured to generate a calibration current that calibrates the voltage at the first node.
a calibration current source having a characteristic corresponding to a temperature change characteristic of the variable resistor, the calibration current source connected in parallel with the variable resistor between the first node and ground, and
a calibration current source configured to generate a calibration current that calibrates the voltage at the first node.
The DCO of claim 7 , wherein each of the variable resistor and the calibration current source has a proportional-to-absolute-temperature (PTAT) characteristic.
The DCO of claim 7 , wherein the calibration current source is further configured to generate the calibration current in response to a second control signal.
A digitally controlled oscillator (DCO) comprising: a current mirror including a third node and configured to generate a supply current in response to a bias voltage corresponding to a reference current; a variable resistor connected to the current mirror through a first node outputting the reference current and configured to provide a variable resistance; an oscillation circuit connected to the current mirror through a second node outputting the supply current and configured to receive the supply current; a calibration circuit configured to calibrate a voltage at the first node in response to a change in resistance of the variable resistor due to a change in temperature; and an amplifier including a first input terminal connected to the first node to receive the voltage at the first node, a second input terminal connected to the second node to receive a voltage at the second node, and an output terminal connected to the third node, wherein: the amplifier is configured to generate feedback in response to a difference between the voltage at the first node and the voltage of the second node and provide the feedback to the third node, and the calibration circuit comprises: a calibration current source having a characteristic corresponding to a temperature change characteristic of the variable resistor, the calibration current source connected in parallel with the variable resistor between the first node and ground; and the calibration current source configured to generate a calibration current that calibrates the voltage at the first node.
a current mirror including a third node and configured to generate a supply current in response to a bias voltage corresponding to a reference current;
a variable resistor connected to the current mirror through a first node outputting the reference current and configured to provide a variable resistance;
an oscillation circuit connected to the current mirror through a second node outputting the supply current and configured to receive the supply current;
a calibration circuit configured to calibrate a voltage at the first node in response to a change in resistance of the variable resistor due to a change in temperature; and
an amplifier including a first input terminal connected to the first node to receive the voltage at the first node, a second input terminal connected to the second node to receive a voltage at the second node, and an output terminal connected to the third node, wherein:
the amplifier is configured to generate feedback in response to a difference between the voltage at the first node and the voltage of the second node and provide the feedback to the third node, and
the calibration circuit comprises: a calibration current source having a characteristic corresponding to a temperature change characteristic of the variable resistor, the calibration current source connected in parallel with the variable resistor between the first node and ground; and the calibration current source configured to generate a calibration current that calibrates the voltage at the first node.
a calibration current source having a characteristic corresponding to a temperature change characteristic of the variable resistor, the calibration current source connected in parallel with the variable resistor between the first node and ground; and
the calibration current source configured to generate a calibration current that calibrates the voltage at the first node.
The DCO of claim 10 , wherein a voltage at the third node corresponds to the bias voltage.
The DCO of claim 10 , wherein the current mirror comprises: a bias circuit configured to generate the bias voltage in response to the reference current; and a current source circuit configured to generate the supply current in response to the bias voltage, wherein the third node is connected to the bias circuit and the current source circuit.
a bias circuit configured to generate the bias voltage in response to the reference current; and
a current source circuit configured to generate the supply current in response to the bias voltage, wherein
the third node is connected to the bias circuit and the current source circuit.
The DCO of claim 10 , wherein the feedback increases the bias voltage in response to an increase in the voltage at the first node and decreases the bias voltage in response to a decrease in the voltage at the first node.
The DCO of claim 10 , further comprising: a calibration current source connected in parallel with the variable resistor between the first node and ground, wherein the calibration current source is configured to adjust the voltage at the first node.
a calibration current source connected in parallel with the variable resistor between the first node and ground, wherein
the calibration current source is configured to adjust the voltage at the first node.
A digital phase locked loop (PLL) comprising: a divider configured to divide a clock signal and output a divided signal; a time-to-digital converter configured to compare the divided signal with a reference signal and output a comparison signal; a digital loop filter configured to output a control signal in response to the comparison signal; and a digital control oscillator (DCO) configured to output a clock signal having a frequency adjusted in response to the control signal, wherein: the DCO comprises: a current mirror including a third node and configured to generate a supply current in response to a bias voltage corresponding to a reference current; a variable resistor connected to the current mirror through a first node outputting the reference current; an oscillation circuit connected to the current mirror through a second node outputting the supply current; and an amplifier including a first input terminal connected to the first node, a second input terminal connected to the second node, and an output terminal connected to the third node, the current mirror comprises: a bias circuit configured to generate the bias voltage in response to the reference current; and a current source circuit configured to generate the supply current in response to the bias voltage, and the third node is connected to the bias circuit and the current source circuit.
a divider configured to divide a clock signal and output a divided signal;
a time-to-digital converter configured to compare the divided signal with a reference signal and output a comparison signal;
a digital loop filter configured to output a control signal in response to the comparison signal; and
a digital control oscillator (DCO) configured to output a clock signal having a frequency adjusted in response to the control signal, wherein:
the DCO comprises: a current mirror including a third node and configured to generate a supply current in response to a bias voltage corresponding to a reference current; a variable resistor connected to the current mirror through a first node outputting the reference current; an oscillation circuit connected to the current mirror through a second node outputting the supply current; and an amplifier including a first input terminal connected to the first node, a second input terminal connected to the second node, and an output terminal connected to the third node,
a variable resistor connected to the current mirror through a first node outputting the reference current;
an oscillation circuit connected to the current mirror through a second node outputting the supply current; and
an amplifier including a first input terminal connected to the first node, a second input terminal connected to the second node, and an output terminal connected to the third node,
the current mirror comprises: a bias circuit configured to generate the bias voltage in response to the reference current; and a current source circuit configured to generate the supply current in response to the bias voltage, and
The digital PLL of claim 15 , wherein: the third node outputs the bias voltage, and the amplifier is configured to increase the bias voltage in response to an increase in a voltage at the first node and decrease the bias voltage in response to a decrease in the voltage at the first node.
the third node outputs the bias voltage, and
the amplifier is configured to increase the bias voltage in response to an increase in a voltage at the first node and decrease the bias voltage in response to a decrease in the voltage at the first node.
Ref US11705897B2: Claims:
An apparatus, comprising: a ring oscillator coupled between a first node and a first voltage rail; a control circuit coupled to the first node; a delay line coupled between a second node and the first voltage rail; and a voltage regulator including an input coupled to the first node and an output coupled to the second node, wherein the voltage regulator comprises: a field effect transistor (FET) coupled between a second voltage rail and the second node; and an operational amplifier including a first input coupled to the first node, a second input coupled to the second node, and an output coupled to a gate of the FET.
a ring oscillator coupled between a first node and a first voltage rail;
a control circuit coupled to the first node;
a delay line coupled between a second node and the first voltage rail; and
a voltage regulator including an input coupled to the first node and an output coupled to the second node, wherein the voltage regulator comprises: a field effect transistor (FET) coupled between a second voltage rail and the second node; and an operational amplifier including a first input coupled to the first node, a second input coupled to the second node, and an output coupled to a gate of the FET.
a field effect transistor (FET) coupled between a second voltage rail and the second node; and
an operational amplifier including a first input coupled to the first node, a second input coupled to the second node, and an output coupled to a gate of the FET.
The apparatus of claim 1 , wherein the control circuit comprises: a resistive device; a first current source coupled in series with the resistive device between a second voltage rail and the first voltage rail; a second current source coupled between the second voltage rail and the first node; and an operational amplifier including a first input coupled to a third node between the first current source and the resistive device, a second input coupled to the first node, and an output coupled to control inputs of the first and second current sources, respectively.
a resistive device;
a first current source coupled in series with the resistive device between a second voltage rail and the first voltage rail;
a second current source coupled between the second voltage rail and the first node; and
an operational amplifier including a first input coupled to a third node between the first current source and the resistive device, a second input coupled to the first node, and an output coupled to control inputs of the first and second current sources, respectively.
The apparatus of claim 2 , wherein the resistive device comprises a switched capacitor resistor or a thin-film resistor.
The apparatus of claim 2 , further comprising a leakage current compensation circuit coupled between the third node and the first voltage rail.
The apparatus of claim 4 , wherein the leakage current compensation circuit comprises a leakage current sensor.
The apparatus of claim 5 , wherein the leakage current sensor comprises a set of dummy inverters.
The apparatus of claim 5 , further comprising a delay controller coupled to the ring oscillator and the leakage current sensor.
The apparatus of claim 1 , wherein the control circuit is configured to control an operating point of the ring oscillator.
The apparatus of claim 1 , further comprising a delay controller coupled to the ring oscillator.
The apparatus of claim 1 , wherein the ring oscillator comprises: a ring of cascaded inverters coupled between the first node and the first voltage rail; and a set of capacitors coupled between outputs of the ring of cascaded inverters and the first voltage rail, respectively.
a ring of cascaded inverters coupled between the first node and the first voltage rail; and
a set of capacitors coupled between outputs of the ring of cascaded inverters and the first voltage rail, respectively.
The apparatus of claim 10 , wherein each cascaded inverter of the ring oscillator comprises a set of selectable parallel inverters.
The apparatus of claim 11 , further comprising a delay controller coupled to enable inputs of the set of selectable parallel inverters.
The apparatus of claim 1 , wherein the delay line comprises: a set of cascaded inverters coupled between the second node and the first voltage rail, wherein the set of cascaded inverters includes an input configured to receive an input signal, and an output configured to produce an output signal being a delayed version of the input signal; and a set of capacitors coupled between outputs of the set of cascaded inverters and the first voltage rail, respectively.
a set of cascaded inverters coupled between the second node and the first voltage rail, wherein the set of cascaded inverters includes an input configured to receive an input signal, and an output configured to produce an output signal being a delayed version of the input signal; and
a set of capacitors coupled between outputs of the set of cascaded inverters and the first voltage rail, respectively.
The apparatus of claim 1 , wherein the voltage regulator comprises a low-dropout (LDO) regulator.
The apparatus of claim 1 , further comprising a low pass filter (LPF) coupled to at least one of the first or second node.
The apparatus of claim 1 , further comprising a leakage current compensation circuit coupled to the first node.
The apparatus of claim 16 , wherein the leakage current compensation circuit comprises: a leakage current sensor; and a current mirror coupled to the leakage current sensor and the first node.
a leakage current sensor; and
a current mirror coupled to the leakage current sensor and the first node.
The apparatus of claim 17 , wherein the leakage current compensation circuit includes a current input error amplifier configured to control a first voltage across the leakage current sensor to be related to a second voltage at the first node.
A wireless communication device, comprising: one or more baseband signal processing modules; at least one antenna; a transceiver coupled to the at least one antenna and the one or more baseband signal processing modules, wherein the transceiver comprises: a ring oscillator coupled between a first node and a first voltage rail; a control circuit coupled to the first node; a delay line coupled between a second node and the first voltage rail; and a voltage regulator including an input coupled to the first node and an output coupled to the second node, wherein the voltage reg
[Truncated to input limit]