Office Action 1: Non-Final Rejection (2024-11-21)
Rejection types: 102 - Lack of Novelty, 103 - Obviousness

CLAIMS:
CLAIMS
1\. A forming method of a semiconductor structure, comprising: placing a target structure in a reaction chamber; and forming a first oxide layer on the target structure, wherein the first oxide layer has a first thickness; and forming a second oxide layer under the first oxide layer, wherein the second oxide layer has a second thickness, and the first thickness is less than the second thickness.
2\. The forming method of a semiconductor structure according to claim 1, wherein the forming a first oxide layer on the target structure comprises: adjusting a pressure in the reaction chamber to a first pressure; and continuously heating the target structure for a first duration under the first pressure, to heat the target structure to a first temperature, and forming the first oxide layer on a surface of the target structure.
3\. The forming method of a semiconductor structure according to claim 2, wherein the forming a second oxide layer under the first oxide layer comprises: adjusting the pressure in the reaction chamber to a second pressure; and heating the target structure to a second temperature under the second pressure, maintaining the second temperature for a preset duration, and forming the second oxide layer under the first oxide layer, wherein the target structure is heated to the second temperature and the second temperature is maintained for a second duration.
4\. The forming method of a semiconductor structure according to claim 3, wherein the first pressure is greater than the second pressure, the first pressure is 3 atm to 20 atm, and the second pressure is 0.5 atm to 2 atm.
5\. The forming method of a semiconductor structure according to claim 3, wherein the first pressure and the second pressure are both 3 atm to 20 atm.
6\. The forming method of a semiconductor structure according to claim 3, wherein the first pressure is less than the second pressure, the first pressure is 0.5 atm to 2 atm, and the second pressure is 3 atm to 20 atm.
7\. The forming method of a semiconductor structure according to claim 1, wherein the first thickness is greater than 0.1 nm, and a sum of the first thickness and the second thickness is less than 3 nm.
8\. The forming method of a semiconductor structure according to claim 3, wherein a value of the first temperature is less than or equal to 1/2 of a value of the second temperature, the first temperature is 450°C to 550°C, and the second temperature is 950°C to 1100°C.
9\. The forming method of a semiconductor structure according to claim 3, the forming method further comprises: injecting an oxygen-containing gas into the reaction chamber at a first flow rate; and injecting a catalyst into the reaction chamber at a second flow rate, wherein the catalyst is a gas, and the catalyst comprises a halogen monomer or a halogen compound.
10\. The forming method of a semiconductor structure according to claim 9, the forming method further comprises: performing thermal treatment on the target structure, and controlling the second flow rate to be positively correlated with a duration of the thermal treatment, wherein densities of the first oxide layer and the second oxide layer gradually increase from a top surface of the first oxide layer to a bottom surface of the second oxide layer; or, performing thermal treatment on the target structure, and controlling the second flow rate to be negatively correlated with a duration of the thermal treatment, wherein densities of the first oxide layer and the second oxide layer gradually decrease from a top surface of the first oxide layer to a bottom surface of the second oxide layer.
11\. The forming method of a semiconductor structure according to claim 9, the forming method further comprises: injecting the oxygen-containing gas and the catalyst into the reaction chamber in the first duration; and stopping injecting the catalyst into the reaction chamber at an end of the first duration, such that a density of the first oxide layer is greater than that of the second oxide layer.
12\. The forming method of a semiconductor structure according to claim 9, the forming method further comprises: injecting the oxygen-containing gas into the reaction chamber in the first duration and the second duration; and injecting the catalyst into the reaction chamber at a beginning of the second duration, such that a density of the second oxide layer is greater than that of the first oxide layer.
13\. The forming method of a semiconductor structure according to claim 9, wherein a ratio of the first flow rate to the second flow rate is greater than 10:1.
14\. The forming method of a semiconductor structure according to claim 9, wherein the first flow rate is 200 sccm to 500 sccm; and the second flow rate is 10 sccm to 50 sccm.
15\. The forming method of a semiconductor structure according to claim 9, wherein a gaseous mixture of the oxygen-containing gas and the catalyst is injected into the reaction chamber; or, the oxygen-containing gas and the catalyst are injected into the reaction chamber alternately by pulses.
16\. The forming method of a semiconductor structure according to claim 2, wherein the target structure comprises a doped region, dopant ions are implanted in the doped region, and a temperature at which the dopant ions are activated and escape from the target structure is greater than the first temperature.
17\. A semiconductor structure, comprising: a doped region, wherein the doped region comprises dopant ions; a first oxide layer, wherein the first oxide layer covers a surface of the semiconductor structure, and the first oxide layer has a first thickness; and a second oxide layer, wherein the second oxide layer is located under the first oxide layer, the second oxide layer has a second thickness, and the first thickness is less than the second thickness.
18\. The semiconductor structure according to claim 17, wherein the first thickness is greater than 0.1 nm, and a sum of the first thickness and the second thickness is less than 3 nm.
19\. The semiconductor structure according to claim 17, wherein a density of the first oxide layer is greater than that of the second oxide layer; or, a density of the first oxide layer is less than that of the second oxide layer.
20\. The semiconductor structure according to claim 17, wherein densities of the first oxide layer and the second oxide layer increase gradually from a top surface of the first oxide layer to a bottom surface of the second oxide layer; or, densities of the first oxide layer and the second oxide layer decrease gradually from a top surface of the first oxide layer to a bottom surface of the second oxide layer.

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Thakur, US 5,360,769.
Regarding Claim 1, Thakur teaches a forming method of a semiconductor structure, comprising:
placing a target structure in a reaction chamber (summary); and forming a first oxide layer 40 on the target structure 20, wherein the first oxide layer has a first thickness; and
forming a second oxide layer 50 under the first oxide layer 40, wherein the second oxide layer has a second thickness, and the first thickness is less than the second thickness with reference to Figs. 1 – 4 in the summary and under Detailed Description and Claims 15 and 16.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 3, 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thakur, US 5,360,769.
Regarding Claims 2 and 3, Thakur teaches wherein the forming a first oxide layer on the target structure comprises: continuously heating the target structure for a first duration to heat the target structure to a first temperature, and forming the first oxide layer on a surface of the target structure and wherein the forming a second oxide layer under the first oxide layer comprises: heating the target structure to a second temperature, maintaining the second temperature for a preset duration, and forming the second oxide layer under the first oxide layer, wherein the target structure is heated to the second temperature and the second temperature is maintained for a second duration under the “Summary of the Invention”.
Thakur fails to teach adjusting a pressure in the reaction chamber to a first pressure; and adjusting the pressure in the reaction chamber to a second pressure; and growing the two oxide layers at two pressures.
Therefore, it would have been obvious to one with ordinary skill in the art at the time of the invention that RTP used by Thakur will have a pressure within the chamber which can be considered as first and second pressures during two heating cycles.
Regarding Claim 16, Thakur teaches any suitable substrate for the oxide deposition for gate oxide, but fails to teach , wherein the target structure comprises a doped region, dopant ions are implanted in the doped region, and a temperature at which the dopant ions are activated and escape from the target structure is greater than the first temperature.
However, it would have been obvious to one with ordinary skill in the art at the time of the invention to modify Thakur and use a the target structure comprising a doped region, dopant ions are implanted in the doped region, and a temperature at which the dopant ions are activated and escape from the target structure is greater than the first temperature for the benefit of making a CMOS transistor wherein a doped substrate is used for fabrication by implanting dopant ions in the doped region  and thermally activated at high temperature. Therefore, any further thermal treatment on the substrate must be limited to lower temperature than the dopant activation temperature for the benefit of preserving the intended dopant profile for the device.
Regarding Claim 17, Thakur teaches  a semiconductor structure, a first oxide layer, wherein the first oxide layer covers a surface of the semiconductor structure, and the first oxide layer has a first thickness; and a second oxide layer, wherein the second oxide layer is located under the first oxide layer, the second oxide layer has a second thickness, and the first thickness is less than the second thickness as was described earlier in rejecting Claim 1.
Regarding substrate comprising: a doped region, wherein the doped region comprises dopant ions , limitations were described earlier in rejecting Claim 16.
Allowable Subject Matter
Claims 4 – 15 and 18 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.  Lee, US 2003/0211692 teaches a substrate with two silicon oxides of different thickness


NEXT OFFICE ACTION: DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s explanation of the instant invention in pointing the difference with the cited prior art was found to be persuasive.
Allowable Subject Matter
Claims 1 – 6, 8 – 17, 19 and 20 are now allowed.
The following is an examiner’s statement of reasons for allowance:
The reasons for allowing these claims are provide in the Applicant’s Arguments/Remarks (pages 6 and 7) filed February 09, 2025  The novel features of the claims are limitations wherein the first oxide layer has a first thickness and forming a second oxide layer under the first oxide layer, wherein the second oxide layer has a second thickness, and the first thickness is less than the second thickness wherein the first thickness is greater than 0.1 nm, and a sum of the first thickness and the second thickness is less than 3 nm. Furthermore, the art of record does not disclose or anticipate the above limitation in combination with other claim elements nor would it be obvious to modify the art of record so as to form a device including the above limitation.
Conclusion
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee.  Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”

CITED REFERENCE SUMMARIES: Ref US20020109281A1: Claims:
A board holder assembly, comprising: a base member, wherein said base member is configured for engaging a surface of a board; at least one lip member, wherein said at least one lip member emanates contiguously from said base member, and wherein said at least one lip member is configured for placement upon a support member of a structure; a first side wall and a second side wall emanating contiguously from said base member to form a substantially U-shaped channel for receiving said board therein; and a clamp associated with at least one of said first and second side walls for releasably securing said board in said substantially U-shaped channel.
a base member, wherein said base member is configured for engaging a surface of a board;
at least one lip member, wherein said at least one lip member emanates contiguously from said base member, and wherein said at least one lip member is configured for placement upon a support member of a structure;
a first side wall and a second side wall emanating contiguously from said base member to form a substantially U-shaped channel for receiving said board therein; and
a clamp associated with at least one of said first and second side walls for releasably securing said board in said substantially U-shaped channel.
The board holder assembly according to claim 1 , wherein said at least one lip member includes two lip members which emanate contiguously from opposite ends of said base member.
The board holder assembly according to claim 1 , wherein said first side wall includes a plurality of board engaging tabs which facilitate securement of said board.
The board holder assembly according to claim 1 , wherein said first side wall includes a plurality of board engaging tabs which facilitate securement of said board, and said second side wall includes a clamp for releasably securing said board in said substantially U-shaped channel.
The board holder assembly according to claim 1 , wherein said first side wall and said second side wall each include a clamp.
The board holder assembly according to claim 1 , wherein said first side wall and said second side wall each comprise a trapezoidal cross-section to enable a board hanger to be secured to said board and said support member of said structure while said board is positioned in said substantially U-shaped channel.
The board holder assembly according to claim 1 , wherein said first side wall and said second side wall each include an edge emanating at approximately 45 degrees from said base member to a top surface of their respective side walls which enable a board hanger to be secured to said board and said support member of said structure while said board is positioned in said substantially U-shaped channel.
The board holder assembly according to claim 1 , wherein said clamp consists of a lever clamp.
The board holder assembly according to claim 1 , wherein said assembly includes components fabricated from a material selected from the group consisting of steel, aluminum, metallic alloys, natural or synthetic plastics, and mixtures thereof.
A board holder device, comprising: a base member, wherein said base member is configured for engaging a surface of a board; a pair of lip members, wherein said lip members emanate contiguously from said base member, and wherein said lip members are configured for placement upon a support member of a structure; and a first side wall and a second side wall emanating contiguously from said base member to form a substantially U-shaped channel for receiving said board therein, wherein said first side wall includes a plurality of board engaging tabs, and said second side wall includes a lever clamp, which together cooperatively facilitate securement of said board within said substantially U-shaped channel.
a pair of lip members, wherein said lip members emanate contiguously from said base member, and wherein said lip members are configured for placement upon a support member of a structure; and
a first side wall and a second side wall emanating contiguously from said base member to form a substantially U-shaped channel for receiving said board therein, wherein said first side wall includes a plurality of board engaging tabs, and said second side wall includes a lever clamp, which together cooperatively facilitate securement of said board within said substantially U-shaped channel.
The board holder device according to claim 10 , wherein said lip members include a pair of lip members which emanate contiguously from opposite ends of said base member.
The board holder device according to claim 10 , wherein said first side wall and said second side wall each include a lever clamp.
The board holder device according to claim 10 , wherein said first side wall and said second side wall each comprise a trapezoidal cross-section to enable a board hanger to be secured to said board and said support member of said structure while said board is positioned in said substantially U-shaped channel.
The board holder device according to claim 10 , wherein said first side wall and said second side wall each include an edge emanating at approximately 45 degrees from said base member to a top surface of the respective side wall, which enables a board hanger to be secured to said board and said support member of said structure while said board is positioned in said U-shaped channel.
The board holder assembly according to claim 10 , wherein said assembly includes components fabricated from a material selected from the group consisting of steel, aluminum, metallic alloys, natural or synthetic plastics, and mixtures thereof.
A board holder assembly, consisting of: a base member, wherein said base member engages a surface of a board; at least one lip member, wherein said at least one lip member emanates contiguously from said base member, and wherein said at least one lip member is placed upon a support member of a structure; a first side wall and a second side wall emanating contiguously from said base member to form a substantially U-shaped channel having a board therein; and a lever clamp associated with at least one of said first and second side walls, which is releasably secured to said board in said substantially U-shaped channel.
a base member, wherein said base member engages a surface of a board;
at least one lip member, wherein said at least one lip member emanates contiguously from said base member, and wherein said at least one lip member is placed upon a support member of a structure;
a first side wall and a second side wall emanating contiguously from said base member to form a substantially U-shaped channel having a board therein; and
a lever clamp associated with at least one of said first and second side walls, which is releasably secured to said board in said substantially U-shaped channel.
The board holder assembly according to claim 16 , wherein said support member consists of a ledger board of a deck.
The board holder assembly according to claim 16 , wherein said support member consists of a ridge board of a roof frame.
The board holder assembly according to claim 16 , wherein said structure consists of a deck.
The board holder assembly according to claim 16 , wherein said structure consists of a roof frame.
Ref US20030211692: Claims:
1. A method of forming a nonvolatile memory device on a semiconductor substrate with a peripheral circuit region composed of a high voltage transistor region and a low voltage transistor region and with a cell array region, comprising: 
forming a cell gate insulating layer on the semiconductor substrate, wherein the cell gate insulating layer is composed of a lower insulating layer, a charge storage layer, and an upper insulating layer that are sequentially stacked;  forming a sacrificial pattern on the cell gate insulating layer to cover the cell array region; and  exposing the peripheral circuit region by etching the cell gate insulating layer in the peripheral circuit region using the sacrificial pattern as a sacrificial etch mask,  wherein the upper insulating layer and the sacrificial pattern have an etch selectivity with respect to each other.
2. The method as claimed in claim 1, wherein the lower insulating layer is made of a silicon oxide layer.
3. The method as claimed in claim 1, wherein the charge storage layer is made of a silicon nitride layer.
4. The method as claimed in claim 1, wherein the upper insulating layer is made of a metal oxide layer.
5. The method as claimed in claim 1, wherein the upper insulating layer is composed of one material selected from the group consisting of an aluminum oxide layer, a hafnium oxide layer, a hafnium aluminum oxide layer, and a hafnium silicon oxide layer.
6. The method as claimed in claim 1, wherein the upper insulating layer includes at least one impurity selected from the group consisting of elements from Group IV of the periodic table.
7. The method as claimed in claim 1, wherein the sacrificial pattern is composed of at least one material selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a polysilicon layer.
8. The method as claimed in claim 1, wherein forming the sacrificial pattern comprises: 
forming a sacrificial layer on the cell gate insulating layer;  forming a photoresist layer on the sacrificial layer;  patterning the photoresist layer to form a photoresist pattern exposing the sacrificial layer in the peripheral circuit region; and  etching the exposed sacrificial layer by using the photoresist pattern as an etch mask.
9. The method as claimed in claim 8, wherein the cell gate insulating layer in the peripheral circuit region is etched while the sacrificial layer is etched.
10. The method as claimed in claim 1, wherein etching the cell gate insulating layer in the peripheral circuit region comprises: 
etching the upper insulating layer;  etching the charge storage layer by using phosphoric acid; and  etching the lower insulating layer.
11. The method of claim 10, wherein etching the upper insulating layer comprises etching the upper insulation layer with LAL.
12. The method of claim 10, wherein etching the upper insulating layer comprises etching the upper insulation layer with sulphuric acid.
13. The method of claim 10, wherein etching the lower insulating layer comprises etching the lower insulating layer with LAL.
14. The method of claim 10, wherein etching the lower insulating layer comprises etching the lower insulating layer with fluoric acid.
15. The method as claimed in claim 10, wherein the lower insulating layer is etched using an isotropic etch method.
16. The method as claimed in claim 1, wherein etching the cell gate insulating layer comprises removing the sacrificial pattern using an etch recipe having an etch selectivity with respect to the upper insulating layer.
17. The method as claimed in claim 1, wherein the cell gate insulating layer is etched so that the sacrificial pattern remains over the upper insulating layer.
18. The method as claimed in claim 1, wherein the upper insulating layer is crystallized by a thermal process after the cell gate insulating layer is formed.
19. The method as claimed in claim 1, wherein the sacrificial pattern is made of a silicon oxide layer.
20. The method as claimed in claim 19, wherein etching the cell gate insulating layer comprises: 
successively etching the upper insulating layer and the charge storage layer using the sacrificial pattern as an etch mask until the lower insulating layer is exposed; and  etching the sacrificial pattern and the lower insulating layer.
21. The method as claimed in claim 1, wherein the sacrificial pattern is made of a silicon nitride layer.
22. The method as claimed in claim 21, wherein etching the cell gate insulating layer comprises: 
exposing the charge storage layer by etching the upper insulating layer using the sacrificial pattern as an etch mask;  exposing the upper insulating layer in the cell array region and the lower insulating layer in the peripheral circuit region by etching the sacrificial pattern and the charge storage layer; and  etching the lower insulating layer by using an etch recipe having an etch selectivity with respect to the exposed upper insulating layer.
23. The method as claimed in claim 1, wherein the sacrificial pattern is composed of a silicon oxide layer and a silicon nitride layer that are sequentially stacked.
24. The method as claimed in claim 23, wherein etching the cell gate insulating layer comprises: 
exposing the charge storage layer in the peripheral circuit region by etching the upper insulating layer using the sacrificial pattern as an etch mask;  exposing the silicon oxide layer in the cell array region and the lower insulating layer in the peripheral circuit region by etching the silicon nitride layer and the charge storage layer; and  etching the silicon oxide layer and the lower insulating layer.
25. The method as claimed in claim 1, wherein the sacrificial pattern is composed of a silicon nitride layer and a silicon oxide layer that are sequentially stacked.
26. The method as claimed in claim 25, wherein etching the cell gate insulating layer comprises: 
exposing the silicon nitride layer in the cell array region and the charge storage layer in the peripheral circuit region by etching the silicon oxide layer and the upper insulating layer;  exposing the upper insulating layer in the cell array region and the lower insulating layer in the peripheral circuit region by etching the silicon nitride layer and the charge storage layer; and  removing the lower insulating layer by using an etch recipe having an etch selectivity with respect to the upper insulating layer.
27. The method as claimed in claim 1, wherein the sacrificial pattern is composed of a lower silicon oxide layer, a silicon nitride layer, and an upper silicon oxide layer that are sequentially stacked.
28. The method as claimed in claim 27, wherein etching the cell gate insulating layer comprises: 
exposing the silicon nitride layer in the cell array region and the charge storage layer in the peripheral circuit region by etching the upper silicon oxide layer and the upper insulating layer;  exposing the lower silicon oxide layer in the cell array region and the lower insulating layer in the peripheral circuit region by etching the silicon nitride layer and the charge storage layer; and  etching the lower silicon oxide layer and the lower insulating layer.
29. The method as claimed in claim 1, further comprising forming a high voltage gate insulating pattern at the peripheral circuit region before the cell gate insulating layer is formed.
30. The method as claimed in claim 1, further comprising forming a high voltage gate insulating pattern at the high voltage transistor region before the cell gate insulating layer is formed.
31. The method as claimed in claim 1, further comprising forming a low voltage gate insulating layer at the peripheral circuit region after the peripheral circuit region is exposed.
32. The method as claimed in claim 1, further comprising forming a high voltage gate insulating pattern and a low voltage gate insulating layer at the semiconductor substrate in the high voltage transistor region and in the low voltage transistor region, respectively, after the peripheral circuit region is exposed.
33. The method as claimed in claim 32, wherein forming the high voltage gate insulating pattern and the low voltage gate insulating layer comprises: 
forming a high voltage gate insulating layer at the semiconductor substrate in the peripheral circuit region that is exposed;  patterning the high voltage gate insulating layer to form the high voltage gate insulating pattern exposing the semiconductor substrate in the low voltage transistor region; and  forming the low voltage gate insulating layer on the semiconductor substrate that is exposed in the low voltage transistor region.
34. The method as claimed in claim 1, further comprising forming a high voltage gate insulating pattern and a low voltage gate insulating layer at the semiconductor substrate in the high voltage transistor region and in the low voltage transistor region, respectively, before the cell gate insulating layer is formed.
35. The method as claimed in claim 34, wherein forming the high voltage gate insulating pattern and the low voltage gate insulating layer comprises: 
forming a high voltage gate insulating layer at the semiconductor substrate in the peripheral circuit region that is exposed;  patterning the high voltage gate insulating layer to form the high voltage gate insulating pattern exposing the semiconductor substrate in the low voltage transistor region; and  forming the low voltage gate insulating layer on the semiconductor substrate that is exposed in the low voltage transistor region.
Ref US5360769: Claims:
1. A method for fabricating a semiconductor wafers comprising the steps of:a) providing a substantially clean substrate in an RTP (Rapid Thermal Processing) chamber, said substrate having a surface, wherein said substrate is cleaned with at least one of NF3, GeH4, and H2 diluted with Ar-H2 ; b) forming a coating having a first thickness superjacent said surface by introducing a first gas and radiant energy in said RTP chamber; and c) forming a silicon dioxide layer having a second thickness superjacent said surface by introducing a second gas and energy.
2. A method for fabricating a semiconductor wafer, according to claim 1, wherein said silicon dioxide layer is disposed between said surface and said coating.
3. A method for fabricating a semiconductor wafer, according to claim 1, wherein step c) is performed in a furnace.
4. A method for fabricating a semiconductor wafer, according to claim 3, further comprising the step of:transferring said substrate between said chamber and said furnace, in-situ, thereby employing a load lock, between said forming a coating and said forming a silicon dioxide layer.
5. A method for fabricating a semiconductor wafer, according to claim 4, wherein said transferring is performed by an automated means.
6. A method for fabricating a semiconductor wafer, according to claim 5, wherein said automated means comprises a robotic handler.
7. A method for fabricating a semiconductor wafer, according to claim 1, wherein said energy of step b) generates a temperature substantially within the range of 850° C. to 1250° C. and is applied for approximately 5 to 30 seconds.
8. A method for fabricating a semiconductor wafer, comprising the steps of:providing a substantially clean substrate in a chamber, said substrate having a surface; forming a coating having a first thickness superjacent said surface by introducing a first gas and energy, said first gas comprising NF3 ; and forming a silicon dioxide layer having a second thickness superjacent said surface by introducing a second gas and energy.
9. A method for fabricating a semiconductor wafer, according to claim 8, wherein said first gas further comprises at least one of O2 and N2 O.
10. A method for fabricating a semiconductor wafer, according to claim 9, wherein said coating comprises silicon dioxide and SiF.
11. A method for fabricating a semiconductor wafer, according to claim 8, wherein said coating comprises Si-F.
12. A method for fabricating a semiconductor wafer, according to claim 10, wherein said method is performed at atmospheric pressure.
13. A method for fabricating a semiconductor wafer, according to claim 10, wherein said clean substrate is cleaned by exposing said substrate to a third gas at a temperature substantially within the range of 850° C. to 1250° C. for approximately 10 to 60 seconds.
14. A method for fabricating a semiconductor wafer, according to claim 13, wherein said third gas comprises at least one of NF3, GeH4, HF, and H2 diluted with Ar-H2.
15. A method for fabricating a semiconductor wafer, according to claim 10, wherein said first thi
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