Office Action 3: Notice of Allowance (2025-03-27)

CLAIMS:
In the Claims:

1\. (Currently Amended) A logic gate comprising at least two phase change memory - PCM - cells, said at least two PCM cells having a high resistance phase and a low resistance phase, said at least two PCM cells being connected at a common connection and further the logic gate having at least one gate input for an input logic state, wherein a logic output for the logic gate comprises a phase of an output one of said at least two phase change memory cells, the phase of the output one of said at least two phase change memory cells forming the logic output following provision of said input logic state at said gate input, the logic gate being configured to react to a set pulse and a reset pulse as logic input pulses, wherein the set pulse is configured to raise a temperature of the cell to a crystallization temperature and the reset pulse is configured to raise the temperature of the cell to a melting temperature, wherein the at least two PCM cells comprise three PCM cells, said three PCM cells being connected between respective inputs and said common connection, said common connection being connected to a resistance.

2\. (Original) The logic gate of claim 1, configured for a predetermined logic operation by switching said output one of said at least two PCM cells to a predetermined one of said high resistance and said low resistance phases.

3\. (Previously Presented) The logic gate of claim 1, configured for a predetermined logic operation by presetting said input logic state to a specified member of the group consisting of a set pulse and a reset pulse.

4\. (Original) The logic gate of claim 3, wherein said set pulse and said reset pulse each have a duration and a level, and wherein the duration of the set pulse is longer than the duration of the reset pulse and the level of the set pulse is lower than the level of the reset pulse.

5\. (Cancelled)

6\. (Previously Presented) The logic gate of claim 1, comprising two of said at least two PCM cells connected between a word line and respective bit lines, which said at least two PCM cells serve as inputs to the gate, a third PCM cell being connected between said word line and ground serving as the output for the gate.

7\. (Original) The logic gate of claim 6, wherein the output is preswitched to the low resistance phase, and wherein said input logic state is set to a reset pulse to provide a NOR or a NAND gate.

8\. (Original) The logic gate of clairn 6, wherein the output is preswitched to the high resistance phase, and the input logic pulse is set to a set pulse to provide an OR gate.

9\. (Cancelled)

10\. (Currently Amended) The logic gate of claim 9\_L wherein the output is preswitched to the low resistive state and the input logic pulse is set to a reset pulse, the gate thereby providing a NOT gate.
1\. (Currently Amended) The logic gate of claim 91,wherein the output is preswitched to the high resistive state and the input logic pulse is set to a set pulse, to provide a copy function.SVG {EMBED HERE} 0.110.04

12\. (Currently Amended) The logic gate of claim 9\_L wherein the output is preswitched to the low resistive state and the input logic pulse is set to a reset pulse.

13\. (Currently Amended) The logic gate of claim 9\_L wherein the output is preswitched to the high resistive state and the input logic pulse is set to a set pulse, thereby to provide an OR gate.

14\. (Currently Amended) The logic gate of claim 1, comprising two of said at least two PCM cells connected at aid common connection to a resistor.

15\. (Original) The logic gate of claim 14, wherein the input logic pulse is set to a reset pulse, to provide a NIMP function.

16\. (Original) The logic gate of claim 14, wherein the input logic pulse is set to a set pulse to provide \[MP or NOR functions.

17\. (Cancelled)

18\. (Currently Amended) The logic gate of claim 1,wherein the output is initialized to the low resistive state and the input logic pulse is set to a reset pulse, to provide NAND and NOR functionality.

19\. (Currently Amended) The logic gate of claim . 1, wherein the output is initialized to the high resistive state and the input logic pulse is set to a set pulse, to provide NAND, NOR and XOR functionality.

20\. (Currently Amended) The logic gate of claim 1,wherein the output is initialized to the high resistive state and the input logic pulse is set to a set pulse, to provide NIMP functionality.

21\. (Previously Presented) An electronic data storage device comprising phase change memory cells, some of said phase change memory cells comprising logic gates according to claim 1.

22\. (Original) An electronic memory block comprising phase change memory cells for memory storage and further phase change memory cells forming logic gates.

23\. (Currently Amended) A method of carrying out a logic function using at least two phase change memory (PCM)cells connected at a common connection and having predetermined set and reset pulses, the method comprising:
placing one of the memry-PCM cells in a predetermined one of first and second phases; and
selecting one of said predetermined set and reset pulses as a logic input pulse, wherein the set pulse is configured to raise a temperature of the cell to a crystallization temperature and the reset pulse is configured to raise the temperature of the cell to a melting temperature, wherein the at least two PCM cells comprise three PCM cells, and two of said three PCM cells are connected between respective inputs and said common connection, said common connection being connected to a resistance.

OFFICE ACTION:
DETAILED ACTION
EXAMINER’S AMENDMENT
An examiner’s amendment to the record appears below. Should the changes and/or additions be unacceptable to applicant, an amendment may be filed as provided by 37 CFR 1.312. To ensure consideration of such an amendment, it MUST be submitted no later than the payment of the issue fee.
Authorization for this examiner’s amendment was given in an interview with Darrel Hollis, Reg. No. 26,738 on 3/17/2025.
The application has been amended as follows:
IN THE CLAIMS:
Claim 22 is cancelled.
Allowable Subject Matter
Claims 1-4, 6-8, 10-16, 18-21, 23 are allowed. Specifically, the independent claims 1 and 23 are allowed over the prior arts. The dependent claims 2-4, 6-8, 10-16, 18-21 are allowed due to their dependencies to the said independent claim 1.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 1, the prior arts fail to teach or reasonably suggest  a logic gate comprising at least two phase change memory -PCM- cells, wherein the at least two PCM cells comprises three PCM cells, said three PCM cells being connected between respective inputs and said common connection, said common connection being connected to a resistance, in combination with the other limitations of the claim.
Regarding claim 23, this claim has substantially the same subject matter as that in claim 1. Therefore, claim 23 is allowed under the same rationale as claim 1 above.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee.  Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion

APPLICANT REBUTTAL: REMARKS
This application is a National Phase Application of PCT Patent Application No. PCT/IL2021/050403 having International filing date of April 7, 2021.
Reconsideration of the above-identified application in view of the amendments above and the remarks following is respectfully requested.
Claims 1 - 4 and 6 - 23 are in this Application, of which claims 1 - 16 and 20 - 23 were rejected. Claim 17 and its dependent claims were found to contain allowable subject matter. Claim 9 is cancelled herewith without prejudice, and claims 1, 10 - 14, 18 - 20 and 23 are amended herewith without prejudice.
Amendments To The Claims
The claims are amended to incorporate the allowable subject matter and to deal with informalities.
Claim Objections
Claim 17, now incorporated into claim 1, is amended to clearly clarify the three cells.
The features of claim 17 are likewise incorporated into claim 23.
The common node of claim 17 and the common connection of claim 1 are the same, and the claims are corrected accordingly.
Claim 9 is cancelled as being incompatible with the requirement in amended claim 1 to have three PCM cells.
Allowable Subject Matter
The features of claim 17 were found to be allowable by the Examiner and are now incorporated into claims 1 and 23.
Accordingly the claims are now believed to be allowable.
Conclusion