Office Action 1: Non-Final Rejection (2024-05-14)
Rejection types: 103 - Obviousness, Double Patenting

CLAIMS:
WHAT IS CLAIMED IS

1\. An alternating current (AC)/direct current (DC) voltage detection circuit, comprising:
a rising edge trigger circuit, including an input terminal and an output terminal, wherein the rising edge trigger circuit samples an operating voltage received by the input terminal with a preset clock period,the clock period is configured to enable the rising edge trigger circuit to sample M times to an AC voltage of a rated frequency at its rising edge, wherein M is a natural number, and
when an increase of the operating voltage at the rising edge of the operating voltage within the preset clock period is greater than a preset bias voltage, an output signal of the output terminal undergoes at least one target flip between a high level and a low level,
a detection and output circuit, connected to the output terminal of the rising edge trigger circuit, and configured to detect a change of the operating voltage and the target flip, wherein when the detection and output circuit detects that the output signal of the rising edge trigger circuit undergoes preset m target flips in M consecutive clock periods, the detection and output circuit generates an AC determination signal, where m is a natural number; and
a determination circuit to determine whether the operating voltage is higher than a preset voltage, wherein when the operating voltage is higher than the preset voltage, the determination circuit activates the detection and output circuit to detect the change of the operating voltage and the target flip.

2\. The AC/DC voltage detection circuit according to claim 1, wherein when the output signal of the output terminal undergoes less than m target flips at the rising edge of the operating voltage, the detection and output circuit generates a DC

determination signal.

3\. The AC/DC voltage detection circuit according to claim 1, wherein M is in a range of 15-25, and m is in a range of 8-12.

4\. The AC/DC voltage detection circuit according to claim 1, wherein a magnitude of the bias voltage is positively correlated with an amplitude of the operating voltage.

5\. The AC/DC voltage detection circuit according to claim 1, wherein the rising edge trigger circuit includes:
an adjustment circuit, including:an adjustment circuit input terminal to receive the operating voltage as an AC voltage,
a first adjustment circuit output terminal to output a first voltage, and
a second adjustment circuit output terminal to output a second voltage that is stepped; and
a comparator, including:a first comparator input terminal to receive the first voltage,
a second comparator input terminal to receive the second voltage, and
a comparator output terminal to output a comparison result of the first voltage and the second voltage, wherein the second voltage is different from the first voltage by the bias voltage at the beginning of the clock period, and
the second voltage does not drop by more than a first voltage drop in the clock period.

6\. The AC/DC voltage detection circuit according to claim 5, wherein the first voltage is lower than the second voltage at the beginning of the clock period; and
when an increase of the first voltage in the clock period exceeds the bias voltage, an

output of the comparator undergoes at least one of the target flips.

7\. The AC/DC voltage detection circuit according to claim 5, wherein the voltage adjustment circuit further includes:
a voltage bias circuit, configured to add the bias voltage to an input voltage of the voltage bias circuit; and
a step voltage generating circuit, configured to convert a voltage input to the step voltage generating circuit into a step voltage.

8\. The AC/DC voltage detection circuit according to claim 7, wherein the step voltage generating circuit includes:
a switch circuit;
a clock circuit, connected to the switch circuit and controlling the switch circuit to be disconnected or connected according to the clock period to generate the second voltage;
and a voltage holding circuit, connected to the switch circuit and holding the second voltage after the switch circuit is disconnected, such that the second voltage does not drop by more than the first voltage drop in the clock period.

9\. The AC/DC voltage detection circuit according to claim 8, wherein the voltage bias circuit includes at least one of a voltage-controlled current source, or a voltage-controlled voltage source;
the switch circuit includes at least one field-effect transistor (FET); and
the voltage holding circuit includes at least one capacitor.

10\. The AC/DC voltage detection circuit according to claim 7, wherein the first adjustment circuit output terminal is electrically connected to the adjustment circuit input terminal; and
the voltage bias circuit is connected in series with the step voltage generating circuit,

and the circuits in series are respectively connected to the adjustment circuit input terminal and the second adjustment circuit output terminal.

11\. The AC/DC voltage detection circuit according to claim 10, wherein the first comparator input terminal is a positive terminal of the comparator, the second comparator input terminal is a negative terminal of the comparator, and the bias voltage is a positive voltage; or the first comparator input terminal is a negative terminal of the comparator, the second comparator input terminal is a positive terminal of the comparator, and the bias voltage is a positive voltage.

12\. The AC/DC voltage detection circuit according to claim 7, wherein the voltage bias circuit is connected in series with the first adjustment circuit output terminal and the adjustment circuit input terminal; and
the step voltage generating circuit is connected in series with the adjustment circuit input terminal and the second adjustment circuit output terminal.

13\. The AC/DC voltage detection circuit according to claim 12, wherein the first comparator input terminal is a positive terminal of the comparator, the second comparator input terminal is a negative terminal of the comparator, and the bias voltage is a negative voltage; or the first comparator input terminal is a negative terminal of the comparator, the second comparator input terminal is a positive terminal of the comparator, and the bias voltage is a negative voltage.

14\. The AC/DC voltage detection circuit according to claim 1, further comprising:
a voltage divider circuit, wherein a terminal of the voltage divider circuit is connected to an input voltage,
another terminal of the voltage divider circuit is connected to a ground wire, and

the voltage divider circuit divides the input voltage into the operating voltage to be output.

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA  as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-14 of U.S. Patent No. US 11828777 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Instant claim 1 is anticipated by Claim 1 and 2 in US Patent no. US 11828777 B2.
Instant claim 2 is anticipated by Claim 1 in US Patent no. US 11828777 B2.
Instant claim 3-14 is anticipated by Claim 3-14 respectively in US Patent no. US 11828777 B2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moon (US20120105016A1) in view of Fujinaka (US 20070046245 A1).
Regarding claim 1 Regarding claim 1, Moon teaches An alternating current (AC)/direct current (DC) voltage detection circuit comprising (Fig. 2 shows an AC/DC voltage detection circuit):
a rising edge trigger circuit, including an input terminal and an output terminal ( In Fig. 2, circuit including sampler 400 (also in Fig. 3), reference voltage generator 600 (also in Fig 4), comparator 700 and power source cutoff detector 800 (also Fig. 5) are collectively viewed as the rising edge trigger circuit with V1 input to sampler 400 being an input terminal an comparator 700 output Vcomp being an output terminal) wherein
the rising edge trigger circuit samples an operating voltage received by the input terminal with a preset clock period (In Fig. 2, sampler 400 samples an operating voltage V1 received at the input terminal of sampler 400 with a preset clock period defined by CLK signal; also see Fig. 3 and paragraph 45, The sampler 400 samples the rectified AC signal V1 according to a period Tsampling of a clock signal CLK to generate a second sampling signal V.sub.S2),
the clock period is configured to enable the rising edge trigger circuit to sample M times to an AC voltage of a rated frequency at its rising edge, wherein M is a natural number (In, Fig. 2, TMAX; also see, e.g., Fig. 8 showing sampling of voltage V1 having a rated frequency, with V1 being sampled M times at its rising edge, with M being a natural number; in fig. 8, for example, in the first half-cycle V1 is sampled three times on the rising edge, and the second half-cycle V1 is sampled three times on the rising edge, and the third half-cycle is sampled three times on the rising edge))
when an increase of the operating voltage at the rising edge of the operating voltage within the preset clock period is greater than a preset bias voltage, an output signal of the output terminal undergoes at least one target flip between a high level and a low level (output signal Vcomp at the output terminal of the comparator 700 will undergo at least one target flip between a high level and a low level as the non-inverting input VS2 to comparator 700 changes relative to inverting input Vref of comparator 700; also see, e.g., Fig. 6 and paragraph 68, if the reference voltage Vref and the period Tsampling of the clock signal CLK are appropriately adjusted, the comparison signal Vcomp neither continually has a high level nor continually has a low level when the AC power source Vac is normal; also see, e.g., Fig. 8, as voltage V1 changes relative to Vref, Vcomp at output of comparator 700 will undergo at least one target flip between high and low levels);
a detection and output circuit, connected to the output terminal of the rising edge trigger circuit, and configured to detect a change of the operating voltage and the target flip (Fig. 2 power source cutoff detector 800, also in para [0058] As shown in FIG. 5, the power source cutoff detector 800 according to an embodiment of the present invention includes a shift register 810 and a gate unit 820. ), wherein when the detection and output circuit detects that the output signal of the rising edge trigger circuit undergoes preset m target flips in M consecutive clock periods, the detection and output circuit generates an AC determination signal, where m is a natural number ( From para [0058] and Fig. 5 showing power source cutoff detector 800; note that Moon utilizes an n-bit shift register 810 to store values of Vcomp output by the comparator 700; when all n bits of the n-bit shift register 810 have the same value, this condition is detected by gate unit 820 and indicates that power source Vac (Fig. 1) has been cutoff; as shown in Fig. 8, for example, when Vac is normal during the first three half-cycles the sampled values of V1 are such that the output of the comparator 700 (Fig. 2) will change because the sampled values of V1 change with respect to Vref; when AC cutoff occurs during the fourth half-cycle in Fig. 8 (top graph), the comparator 700 output Vcomp will stay high for a longer duration than usual because V1 does not transition below Vref; accordingly all bits of the n-bit shift register 810 will be populated by the same value over a number of consecutive sampling periods; this condition (e.g., all bits of n-bit register 810 being the same value) is detected by gate unit 820 which outputs Vac_off in response to this condition; as discussed above, in Fig. 8 V1 is sampled three times on the rising edge of the first three half-cycles so M may be considered to be three; as also shown in Fig. 8 when considered in light of the circuit of Fig. 2, the output of the comparator 700 will undergo at least one “flip” e.g., high to low or low to high, in three consecutive sample periods; in other words, one transition of the comparator 700 output will occur during the first three samples in Fig. 8, another transition will occur during the next three samples in Fig. 8, and so on; when these transitions occur power source cutoff detector 800 will indicate an AC determination signal (i.e. no Vac_off indication)).
However, Moon does not teach a determination circuit to determine whether the operating voltage is higher than a preset voltage, wherein when the operating voltage is higher than the preset voltage, the determination circuit activates the detection and output circuit to detect the change of the operating voltage and the target flip.
Fujinaka (US 20070046245 A1) teaches a determination circuit to determine whether the operating voltage is higher than a preset voltage, wherein when the operating voltage is higher than the preset voltage, the determination circuit activates the detection and output circuit to detect the change of the operating voltage and the target flip (para [0112] The comparator 16 compares the input signal that shows the detected current value with the signal showing the current target value, and resets the flip-flop 17 when the signal showing the detected current value is higher than the signal showing the current target value, and starts regenerative operation. The period in which the flip-flop 17 is reset and a current flowing in the winding 3 is reduced by the regenerative operation is called PWM OFF period). Herein examiner views current is directly proportional or related to voltage, examiner views the increase of the current as increasing the voltage, where the change in voltage is detected and the flip-flop is reset. Examine views the reset or change in flop-flop as the targeted condition or flip.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing of the invention to have incorporated Fujinaka (directed to detecting changing voltage and target flip) into Moon (directed to detecting AC voltage) for the purpose of checking if the supplied voltage is higher than the required voltage and the required flip.
Regarding claim 4, the combination of Moon and Fujinaka teach The AC/DC voltage detection circuit according to claim 1, Moon wherein a magnitude of the bias voltage is positively correlated with an amplitude of the operating voltage (In Fig. 2, Vref is based on the operating AC voltage. Thus, Vref magnitude is also positively related with the amplitude of the operating AC voltage).
Regarding claim 14, the combination of Moon and Fujinaka teach The AC/DC voltage detection circuit according to claim 1, further comprising: a voltage divider circuit, wherein a terminal of the voltage divider circuit is connected to an input voltage, another terminal of the voltage divider circuit is connected to a ground wire, and the voltage divider circuit divides the input voltage into the operating voltage to be output (In Fig. 2, circuit connected to the sampler with resistor R1 and R3 is viewed as the voltage divider circuit. The input voltage Vac is connected to the resistor R1 and resistor R2 is connected to the ground. The input voltage is divided by the divider circuit to the output voltage VS2).
Allowable Subject Matter
There is no prior art rejection for claim 2, 3, 5-13. Examiner cannot comment on their allowability until double patenting rejection is adequately addressed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tanaka (US4572973A) discusses detecting AC current in rotating device.
KUO (US 20090121739 A1) discusses AC detecting apparatus for detecting operating statues of an AC power.
Onodera (US 20170265000 A1) discusses DC detecting circuit in audio apparatus.

APPLICANT REBUTTAL: REMARKS
Claims 1-14 are pending. In this response, claim 1 has been amended; claim 2 has been canceled. The amendment is at least supported by para. [0031] of the filed Specification. No new matter has been added. The amendments are made without disclaimer of subject matter, and the Applicant reserves the right to pursue subject matter of any previously pending claim in a continuation or divisional application. No new matter was added.
Claim Re
j
ections Nonstatutor
V
Double Patenting
Claims 1-14 stand rejected on the ground of nonstatutory double patenting, as being allegedly unpatentable over claims 1-14 of US PAT. NO. US 11828777 (hereinafter the '877 patent). This rejection is respectfully traversed.
Applicant respectfully submits that since the present application is currently under examination, the claims thereof are subject to amendments. Therefore the double patenting rejection to claims 1-14 is premature and should be held in abeyance.
Further, since the amended claim 1 includes
"an volta
g
e divider circuit to
generate an operation voltage from a high voltage,"
which is not anticipated by any claim of the '877 patent, the nonstatutory double patenting rejection becomes moot.
Claim Re
j
ections under 35
USC §
Claims 1, 4, and 14 stand rejected under 35 USC § 103 as allegedly being
anticipated by US20120105016A1 (hereinafter referred to as Moon) in view of US 20070046245 (hereinafter referred to as Fujinaka).
Applicant disagrees with the rejections. However, in order to expedite the
prosecution of the present application, the allowable subject matter identified in claim 2 is incorporated in independent claim 1.
In light of the foregoing, the currently pending claims 1 and 3-14 are patentable in view of Moon and Fujinaka. Withdrawal of the rejections is respectfully requested.
Conclusion

NEXT OFFICE ACTION: DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on -05/20/2024- is in compliance with the provisions of 37 CFR 1.97.  Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 1, 3-14 objected to because of the following informalities:
Claim 1 is objected for minor informality. Claim 1 recites an voltage divider…. It should be recited as a voltage divider….
Appropriate correction is required.
Response to Arguments
Arguments and amendment filed on 08/13/2024 are considered. Applicant has amended claim 1. Claim 6 and 7 are amended for dependency to claim 1. Allowable claim 2 is included in claim 1. Claim 1 recites “a voltage divider circuit to generate an operation voltage from a high voltage”. Examiner views the claim 14 in U.S PAT No. 11828777B2 - “the voltage divider circuit divides the input voltage into the operating voltage to be output.”  From Fig. 1, the input voltage is high voltage (HV) which is divided by voltage divider 400 into operating voltage Vo. Therefore, the instant independent claim 1 is still anticipated by claims 1, 2 and 14 of U.S PAT No. 11828777B2. Similarly instant claim 3-14 is anticipated by 3-14 respectively in U.S PAT No. 11828777B2.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA  as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1, 3-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-14 of U.S. Patent No. US11828777B2. Although the claims at issue are not identical, they are not patentably distinct from each other because.
Instant claim 1 is anticipated by claim 1, 2 and 14 in US Patent no. US11828777B2.
Instant claim 3-14 is anticipated by claim 3-14 respectively in US Patent no. US11828777B2.
Allowable Subject Matter
There is no prior art rejection for claim 1, 3-14. However, Examiner cannot comment on their allowability until the double patenting rejection is adequately addressed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action.  Accordingly, THIS ACTION IS MADE FINAL.  See MPEP § 706.07(a).  Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action.  In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action.  In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.

CITED REFERENCE SUMMARIES: Ref US4572973A: Claims:
A circuit for detecting an AC drive current of a rotor driving supply source for a rotating anode X-ray tube comprising: a current transformer, magnetically coupled to and electrically insulated from the rotor driving supply source, for producing in an output circuit thereof, a first AC voltage signal that is a function of both an amplitude of the AC rotor driving current and a saturation characteristic of said transformer; saturation circuit means, connected to the current transformer output circuit and including at least first and second resistors series connected to each other, for providing a second AC voltage signal across one of said first and second resistors that is lower in magnitude than said first AC voltage signal; voltage clipper means, connected to said saturation circuit means, for limiting said second AC voltage signal to a first predetermined voltage level to provide an AC clipped voltage; a switching element, connected to said clipper means, operative in response to said AC clipped voltage exceeding a second predetermined voltage level that is lower than said first predetermined voltage level; and retriggerable monostable multivibrator means, connected to the switching element, for providing a first output state when said AC clipped voltage is at least equal to said second voltage level and a second output state when said AC clipped voltage falls below said second voltage level, the output of said multivibrator being an indicator of the AC drive current.
a current transformer, magnetically coupled to and electrically insulated from the rotor driving supply source, for producing in an output circuit thereof, a first AC voltage signal that is a function of both an amplitude of the AC rotor driving current and a saturation characteristic of said transformer;
saturation circuit means, connected to the current transformer output circuit and including at least first and second resistors series connected to each other, for providing a second AC voltage signal across one of said first and second resistors that is lower in magnitude than said first AC voltage signal;
voltage clipper means, connected to said saturation circuit means, for limiting said second AC voltage signal to a first predetermined voltage level to provide an AC clipped voltage;
a switching element, connected to said clipper means, operative in response to said AC clipped voltage exceeding a second predetermined voltage level that is lower than said first predetermined voltage level; and
retriggerable monostable multivibrator means, connected to the switching element, for providing a first output state when said AC clipped voltage is at least equal to said second voltage level and a second output state when said AC clipped voltage falls below said second voltage level, the output of said multivibrator being an indicator of the AC drive current.
A detection circuit according to claim 1 wherein said voltage clipper means comprises a Zener diode.
A detection circuit according to claim 1 wherein said switching element is a transistor.
Ref US20090121739A1: Claims:
An AC detecting apparatus for detecting operating states of an AC power supply comprising: a detecting circuit arranged to be connected to an AC power supply, the detecting circuit comprising a photocoupler having a luminous element with the anode connected to a live line of the AC power supply and the cathode connected to a neutral line of the AC power supply, and an optical receiving block with the cathode grounded and the anode connected to a first power source via a first resistor; and a processor comprising an interrupt terminal connected to the anode of the optical receiving block of the photocoupler, and an output terminal,
a detecting circuit arranged to be connected to an AC power supply, the detecting circuit comprising a photocoupler having a luminous element with the anode connected to a live line of the AC power supply and the cathode connected to a neutral line of the AC power supply, and an optical receiving block with the cathode grounded and the anode connected to a first power source via a first resistor; and
a processor comprising an interrupt terminal connected to the anode of the optical receiving block of the photocoupler, and an output terminal,
wherein, the detecting circuit detects the AC power supply to send a trigger signal to the processor for triggering a detecting program preinstalled in the processor to real-time analyze the operating states of the AC power supply, the processor outputs a result of the program via the output terminal.
The AC detecting apparatus as claimed in claim 1 , wherein the detecting program comprises steps of: providing a frequency generator to provide pulses to the processor; counting a first number of the pulses received from the frequency generator in half of a cycle of the AC power supply; counting a second number of the pulses received from the frequency generator in another half of the cycle of the power supply; and comparing a difference between the first and second numbers with a reference value to distinguish the operating state of the AC power supply.
providing a frequency generator to provide pulses to the processor;
counting a first number of the pulses received from the frequency generator in half of a cycle of the AC power supply;
counting a second number of the pulses received from the frequency generator in another half of the cycle of the power supply; and
comparing a difference between the first and second numbers with a reference value to distinguish the operating state of the AC power supply.
The AC detecting apparatus as claimed in claim 1 , wherein the output terminal of the processor is connected to a server for transmitting the result of the program.
The AC detecting apparatus as claimed in claim 1 , wherein the processor further comprises an enable terminal connected to the anode of the optical receiving block of the photocoupler, the processor is enable when the enable terminal is at a high level.
An AC detecting apparatus for detecting operating states of an AC power supply comprising: a detecting circuit arranged to be connected to an AC power supply, the detecting circuit comprising a photocoupler having a luminous element with the anode connected to a live line of the AC power supply and the cathode connected to a neutral line of the AC power supply, and an optical receiving block with the cathode grounded via a second resistor and the anode connected to a second power source; and a processor comprising an interrupt terminal connected to the cathode of the optical receiving block of the photocoupler, and an output terminal,
a detecting circuit arranged to be connected to an AC power supply, the detecting circuit comprising a photocoupler having a luminous element with the anode connected to a live line of the AC power supply and the cathode connected to a neutral line of the AC power supply, and an optical receiving block with the cathode grounded via a second resistor and the anode connected to a second power source; and
a processor comprising an interrupt terminal connected to the cathode of the optical receiving block of the photocoupler, and an output terminal,
wherein, the detecting circuit detects the AC power supply to send a trigger signal to the processor, and trigger the detecting program preinstalled in the processor to real-time analyze the operating states of the AC power supply, the processor outputs a result of the program via the output terminal.
The AC detecting apparatus as claimed in claim 5 , wherein the detecting program comprises steps of: providing a frequency generator to provide pulses to the processor; counting a first number of the pulses received from the frequency generator in half of a cycle of the AC power supply; counting a second number of the pulses received from the frequency generator in another half of the cycle of the power supply; and comparing a difference between the first and second numbers with a reference value to distinguish the operating state of the AC power supply.
The AC detecting apparatus as claimed in claim 5 , wherein the output terminal of the processor is connected to a server for transmitting the result of the program.
The AC detecting apparatus as claimed in claim 5 , wherein the processor further comprises an enable terminal connected to the cathode of the optical receiving block of the photocoupler, the processor is enable when the enable terminal is at a low level.
Ref US20170265000A1: Claims:
A DC detection circuit comprising: an OR circuit configured to generate a logical OR flag on the basis of a logical OR of values of X bits from a (most significant bit-1) th bit to a (most significant bit-X) th bit of PCM data to be input; an NAND circuit configured to generate an NAND flag on the basis of negative AND of values of X bits from the (most significant bit-1) th bit to the (most significant bit-X) th bit of the PCM data; and a counter configured to count up a counter value on the basis of the most significant bit and any one of the logical OR flag or NAND flag, and then output a DC detection flag if a counter value exceeds a predetermined set value.
an OR circuit configured to generate a logical OR flag on the basis of a logical OR of values of X bits from a (most significant bit-1) th bit to a (most significant bit-X) th bit of PCM data to be input;
an NAND circuit configured to generate an NAND flag on the basis of negative AND of values of X bits from the (most significant bit-1) th bit to the (most significant bit-X) th bit of the PCM data; and
a counter configured to count up a counter value on the basis of the most significant bit and any one of the logical OR flag or NAND flag, and then output a DC detection flag if a counter value exceeds a predetermined set value.
The DC detection circuit according to claim 1 , further comprising: a selector configured to select any one the logical OR flag or the NAND flag, and then output the selected flag as a DC flag on the basis of the most significant bit, wherein the counter counts up a counter value on the basis of the most significant bit and the DC flag.
a selector configured to select any one the logical OR flag or the NAND flag, and then output the selected flag as a DC flag on the basis of the most significant bit, wherein
the counter counts up a counter value on the basis of the most significant bit and the DC flag.
The DC detection circuit according to claim 1 , further comprising a register configured to hold the PCM data, wherein the OR circuit and the NAND circuit input the PCM data held by the register.
a register configured to hold the PCM data, wherein
the OR circuit and the NAND circuit input the PCM data held by the register.
The DC detection circuit according to claim 2 , wherein the counter counts up the counter value if the DC flag is a logical value â1â and the counter value is less than the predetermined set value, holds the counter value if the DC flag is the logical value â1â and the counter value is equal to or greater than the predetermined set value, and clears the counter value if the DC flag is a logical value â0â or if the value of the most significant bit is changed.
counts up the counter value if the DC flag is a logical value â1â and the counter value is less than the predetermined set value,
holds the counter value if the DC flag is the logical value â1â and the counter value is equal to or greater than the predetermined set value, and
clears the counter value if the DC flag is a logical value â0â or if the value of the most significant bit is changed.
A semiconductor apparatus comprising: a DC detection circuit comprising an OR circuit configured to generate a logical OR flag on the basis of a logical OR of values of X bits from a (most significant bit-1) th bit to a (most significant bit-X) th bit of PCM data to be input, an NAND circuit configured to generate an NAND flag on the basis of negative AND of values of X bits from the (most significant bit-1) th bit to the (most significant bit-X) th bit of the PCM data and a counter configured to count up a counter value on the basis of the most significant bit and. any one of the logical OR flag or NAND flag, and then output a DC detection flag if a counter value exceeds a predetermined set value; and an error control circuit configured to execute a function for protecting a load from an over current and over temperature due to DC data in response to the DC detection flag sent from the DC detection circuit, and then outputs a load protection flag.
a DC detection circuit comprising an OR circuit configured to generate a logical OR flag on the basis of a logical OR of values of X bits from a (most significant bit-1) th bit to a (most significant bit-X) th bit of PCM data to be input, an NAND circuit configured to generate an NAND flag on the basis of negative AND of values of X bits from the (most significant bit-1) th bit to the (most significant bit-X) th bit of the PCM data and a counter configured to count up a counter value on the basis of the most significant bit and. any one of the logical OR flag or NAND flag, and then output a DC detection flag if a counter value exceeds a predetermined set value; and
an error control circuit configured to execute a function for protecting a load from an over current and over temperature due to DC data in response to the DC detection flag sent from the DC detection circuit, and then outputs a load protection flag.
The semiconductor apparatus according to claim 5 , wherein the DC detection circuit further comprising a selector configured to select any one the logical OR flag or the NAND flag, and then output the selected flag as a DC flag on the basis of the most significant bit, wherein the counter counts up a counter value on the basis of the most significant bit and the DC flag.
the DC detection circuit further comprising a selector configured to select any one the logical OR flag or the NAND flag, and then output the selected flag as a DC flag on the basis of the most significant bit, wherein
The semiconductor apparatus according to claim 5 , wherein the DC detection circuit further comprising a register configured to hold the PCM data, and the OR circuit and the NAND circuit input the PCM data held by the register.
the DC detection circuit further comprising a register configured to hold the PCM data, and
The semiconductor apparatus according to claim 6 , wherein the counter counts up the counter value if the DC flag is a logical value â1â and the counter value is less than the predetermined set value, holds the counter value if the DC flag is the logical value â1â and the counter value is equal to or greater than the predetermined set value, and clears the counter value if the DC flag is a logical value â0â or if the value of the most significant bit is changed.
the counter counts up the counter value if the DC flag is a logical value â1â and the counter value is less than the predetermined set value, holds the counter value if the DC flag is the logical value â1â and the counter value is equal to or greater than the predetermined set value, and clears the counter value if the DC flag is a logical value â0â or if the value of the most significant bit is changed.
An audio signal output apparatus comprising: a digital signal processor configured to input PCM data; an oversampling filter connected to the digital signal processor; a digital/analog converter connected to the oversampling filter; a comparator connected to the digital/analog converter; a driver output stage connected to the comparator; a loudspeaker connected to the driver output stage; a DC detection circuit comprising an OR circuit configured to generate a logical OR flag on the basis of a logical OR of values of X bits from a (most significant bit-1) th bit to a (most significant bit-X) th bit of the PCM data, an NAND circuit configured to generate an NAND flag on the basis of negative AND of values of X bits from the (most significant bit-1) th bit to the (most significant bit-X) th bit of the POM data and a counter configured to count up a counter value on the basis of the most significant bit and any one of the logical OR flag or NAND flag, and then output a DC detection flag if a counter value exceeds a predetermined set value; and an error control circuit configured to execute a function for protecting a load from an over current and over temperature due to DC data in response to the DC detection flag sent from the DC detection circuit, and then outputs a load protection flag to the driver output stage.
a digital signal processor configured to input PCM data;
an oversampling filter connected to the digital signal processor;
a digital/analog converter connected to the oversampling filter;
a comparator connected to the digital/analog converter;
a driver output stage connected to the comparator;
a loudspeaker connected to the driver output stage;
a DC detection circuit comprising an OR circuit configured to generate a logical OR flag on the basis of a logical OR of values of X bits from a (most significant bit-1) th bit to a (most significant bit-X) th bit of the PCM data, an NAND circuit configured to generate an NAND flag on the basis of negative AND of values of X bits from the (most significant bit-1) th bit to the (most significant bit-X) th bit of the POM data and a counter configured to count up a counter value on the basis of the most significant bit and any one of the logical OR flag or NAND flag, and then output a DC detection flag if a counter value exceeds a predetermined set value; and
an error control circuit configured to execute a function for protecting a load from an over current and over temperature due to DC data in response to the DC detection flag sent from the DC detection circuit, and then outputs a load protection flag to the driver output stage.
The audio signal output apparatus according to claim 9 , wherein the DC detection circuit further comprising a selector configured to select any one the logical OR flag or the NAND flag, and then output the selected flag as a DC flag on the basis of the most significant bit, wherein the counter counts up a counter value on the basis of the most significant bit and the DC flag.
The audio signal output apparatus according to claim 9 , wherein the DC detection circuit further comprising a register configured to hold the PCM data, and the OR circuit and the NAND circuit input the PCM data held by the register.
The audio signal output apparatus according to claim 10 , wherein the counter counts up the counter value if the DC flag is a logical value â1â and the counter value is less than the predetermined set value, holds the counter value if the DC flag is the logical value â1â and the counter value is equal to or greater than the predetermined set value, and clears the counter value if the DC flag is a logical value â0â or if the value of the most significant bit is changed.
The audio signal output apparatus according to claim 9 , wherein each of the DC detection circuit and the error control circuit is configured as a stand-alone semiconductor device.
each of the DC detection circuit and the error control circuit is configured as a stand-alone semiconductor device.
The audio signal output apparatus according to claim 9 , wherein both of the DC detection circuit and the error control circuit are configured to be integrated into a semiconductor device.
both of the DC detection circuit and the error control circuit are configured to be integrated into a semiconductor device.
The audio signal output apparatus accord in to claim 9 , wherein both of the DC detection circuit and the error control circuit are configured to be integrated into a semiconductor device, with the digital signal processor, the oversampling filter, the digital/analog converter, and th
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