Office Action 2: Final Rejection (2024-06-21)
Rejection types: 101 - Patent-Eligible Subject Matter

CLAIMS:
In the Claims:

1\. (Currently Amended) A system for protecting a speculative execution processor, from side channel attacks, comprising a processing circuitry, adapted to:in a first time period performing a plurality of executions of a same code segment in a plurality of time intervals and measure an execution time of the code segment in each of the plurality of time intervals;
updating a time register to include a highest execution time measured for the plurality of time intervals;
storing speculative instructions in an internal cache memory which is inaccessible to read actions of an external processing unit;
in a second time period, performing a delayed copy, wherein in said delayed copy, copying only a committed portion of the executed code segment into another memory component which is accessible to read actions of the external processing unit wherein a delay time of said delayed copy is according to the highest execution time included in said time register;
wherein the first and second time periods are different and independent.

2\. (Cancelled)

3\. (Currently Amended) The system of claim1,wherein the processing circuitry is further adapted to:delay the copying only the committed portion of the executed code segment into the another memory component according to a value which is not correlated with the actual execution time measured.

4\. (Currently Amended) The system of claim 1, wherein a user annotates a beginning and nend of the code segment with dedicated instructions respectively.

5\. (Original) The system of claim 4, wherein the executed code segment annotated by the user is a single entry code segment.

6\. (Original) The system of claim 4, wherein the executed code segment annotated by the user is a multi-entry code segment.

7\. (Original) The system of claim 6, wherein the annotation of the multi-entry code segment is extended, according to a number of an entry.

8\. (Currently Amended) The system of claim 6, wherein in the multi entry code segment each entry is allocated in a table-like structure and each entry number is determined by using one or more hash functions that take an address of an instruction annotating the beginning of the code segment as a parameter.

9\. (Original) The system of claim 1, wherein the processing circuit is further adapted to add noise in conjunction with the execution of the code segment to increase a noise to signal ratio.

10\. (Original) The system of claim 1, wherein the processing circuitry is adapted to perform a double execution of the code segment.

11\. (Original) The system of claim 1, wherein the speculative instructions stored in the internal cache memory are load and store instructions.

12\. (Original) The system of claim 1, wherein the internal cache memory is virtually tagged.

13\. (Original) The system of claim 1, wherein the internal cache memory is exclusive so that data cannot be stored in the internal cache memory and into the another memory component at a same time.

14\. (Currently Amended) The system of claim 1, wherein the internal cache memory is cleaned at anend of a process.

15\. (Original) The system of claim 1, wherein the internal cache memory is dynamically partitioned among different threads.

16\. (Original) The system of claim 1, wherein the internal cache memory is a scratchpad memory.

17\. (Currently Amended) A method for protecting speculative execution processor, from side channel attacks, comprising:in a first time period performing an execution ofacode segment by storing speculative instructions in an internal cache memory which is inaccessible to read actions of an external processing unit;
measuring an execution time of the code segment in a plurality of time intervals;
updating a time register to include a highest execution time measured for the plurality of time intervals;
in a second time period, performing a delayed copy, wherein in said delayed copy, copying only a committed portion of the executed code segment into another memory component which is accessible to read actions of the external processing unite wherein a delay time of said delayed copy is according to the highest execution time included in said time register;
wherein the first and second time periods are different and independent.

18\. (Cancelled)

19\. (Currently Amended) A computer program product provided on a non- transitory computer readable storage medium storing instructions for performing a method for protecting speculative execution processor, from side channel attacks, comprising:in a first time period performing an executionof acode segment by storing speculative instructions in an internal cache memory which is inaccessible to read actions of an external processing unit;
measuiing an execution time of the code segment in a plurality of time intervals;
updating a time register to include a highest execution time measured for the plurality of time intervals;
in a second time period, performing a delayed copy, wherein in said delayed copy, copying only a committed portion of the executed code segment into another memory component which is accessible to read actions of the external processing unit, wherein a delay time of said delayed copy is according to the highest execution time included in said time register;
wherein the first and second time periods are different and independent.

20\. (Cancelled)

OFFICE ACTION:
DETAILED ACTION
This Final Office Action is in response to amendment filed on 02/21/2024. Claims 1, 3, 4, 8, 14, 17 and 19, filed on 02/21/2024, have been amended. Claims 2, 18 and 20 have been canceled. Claims 1, 3-17, and 19 remain pending in the application.
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments to the Abstract has overcome the objection previously set forth in the Non-Final Office Action mailed on 11/22/2023.
Applicant’s claims amendments has overcome the claims objections previously set forth in the Non-Final Office Action mailed on 11/22/2023.
Applicant’s claims amendments, in conjunction with the applicant’s remarks filed on 02/21/2024, has overcome the USC 103 rejections previously set forth in the Non-Final Office Action mailed on 11/22/2023.
Specification
The disclosure is objected to because of the following minor informalities: Page 1 lines 16-17 recites “When the tasks are really required the speed up is achieved…”, should read “When the tasks are really required, the speed up is achieved…”.
Appropriate correction is required.
Claim Objections
Claims 17 and 19 objected to because of the following minor informalities:
Claims 17 and 19 recite “in a first time period performing…”, should read “in a first time, period performing…”
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 19 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
Claim 19 recites in the preamble “A computer program product provided on a non-transitory computer readable storage medium storing instructions for performing a method …”. However, the body of claim 19 recites “measuring… updating… performing…”, which under the broadest reasonable interpretation are considered program per se.  Furthermore, the mere recitation that the “program product is provided on a non-transitory computer readable storage medium” does not mean that the a non-transitory computer readable storage medium is part of the claimed “computer program product”. Therefore claim 19 is non-statutory because it is directed towards program, per se. In order to overcome the above USC 101 rejection, examiner recommends amending claim 19 to recite “A computer program product comprising a non- transitory computer readable storage medium storing instructions for performing a method for protecting speculative execution processor, from side channel attacks…”
Allowable Subject Matter
Claims 1, 3-16 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Cited and relevant prior art of record:
Johnson et al. (US 20190114422 A1),
Klaiber et al. (US 7962909 B1),
Michalak et al. (US 20080046692 A1), and
Courtney (US 20180323960 A1).
Johnson discloses processor modifications that prevent the observation of the side effects of mispredicted speculative execution flows, the processor can make use of speculative execution after a branch or conditional load, but avoid performing any operation that could cause observable side-effects if the operation was mispredicted, Johnson further discloses recording the effects of one or more speculatively-executed instructions to the one or more speculation buffers, utilize speculative execution after a branch or conditional load, and avoids observable side-effects of memory loads during this speculative execution by buffering the results/effects of those loads into one or more speculation buffers. Klaiber discloses monitoring a processor's execution core to detect an end of an execution interval, and causes the processor to exit a guest at the end of the execution interval. Michalak discloses a processor may directly write the dynamic delay value to a coprocessor register, highly speculative instructions may incur a greater execution delay while less speculative instructions may incur a lesser delay, each instruction or set of instructions offloaded to the coprocessor may incur an execution delay based on their speculative nature. For example, highly speculative instructions may incur a greater execution delay while less speculative instructions may incur a lesser delay. Courtney discloses a method and apparatus for defending against a side-channel attack upon a data storage device, and further discloses that in response to a function call signal being generated to request execution of a given function, a timer circuit is initiated to count out a predetermined elapsed time interval. The overall duration of the elapsed time interval is selected based on empirical or adaptive measurements, or system specifications, regarding the maximum likely duration of the execution of the function.
While the above prior arts disclose the aforementioned concepts, however, none of the prior arts, individually or in reasonable combination, discloses all the limitations in the manner recited in the independent claims. Specifically, none of the prior art discloses “…in a first time period performing, an execution of a code segment by storing speculative instructions in an internal cache memory which is inaccessible to read actions of an external processing unit; measuring an execution time of the code segment in a plurality of time intervals; updating a time register to include a highest execution time measured for the plurality of time intervals; in a second time period, performing a delayed copy, wherein in said delayed copy, copying only a committed portion of the executed code segment into another memory component which is accessible to read actions of the external processing unite wherein a delay time of said delayed copy is according to the highest execution time included in said time register; wherein the first and second time periods are different and independent”. Therefore, the above limitations in conjunction with the remaining limitations of the independent claims render the above independent claims allowable.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action.  Accordingly, THIS ACTION IS MADE FINAL.  See MPEP § 706.07(a).  Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action.  In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action.  In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.

APPLICANT REBUTTAL: REMARKS
Reconsideration of the above-identified application in view of the amendments above and the remarks following is respectfully requested.
Claims 1-20 have been presented for examination.
The Specification has been objected to.
Claims 4, 8, 14, 17 and 19 have been objected to.
Claims 11, 11, 13-15, 17 and 19 have been rejected under 35 U.S.C § 102.
Claims 2-10, 12, 16, 18 and 20 have been rejected under 35 U.S.C § 103.
Claims 1, 3, 4, 8, 14, 17 and 19 have been amended herewith without prejudice.
Claims 2, 18 and 20 have been cancelled herewith without prejudice.
Specific
ati
on Ob
jections
The abstract of the disclosure is objected to because the abstract is written as a claim. The Examiner asserted that the abstract repeats claim 1 and that correction is required.
Applicant amended the abstract appropriately.
Claim
obj
ecti
ons
Claims 4, 8, 14, 17 and 19 are objected to. The Examiner listed several informalities related to these claims.
Applicant amended the claims appropriately.
Applicant notes that in referring to Claim 8, following the amendment to Claim 4, and since Claim 8 depends indirectly from Claim 4, no correction has been identified as needed for antecedence of the term "the beginning", as it refers to Claim 4.
U.S.
C.
#
3 Re
j
ecti
ons
Claims 1, 11, 13-15, 17 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Johnson et al. (US 20190114422 A1), hereinafter Johnson.
Claims 2, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 20190114422 A1), hereinafter Johnson, as stated in claims 1, 11, 13-
15, 17 and 19 above, and further in view of Klaiber et al. (US 7962909 B 1), hereinafter Klaiber, and Michalak et al. (US 20080046692 A1), hereinafter Michalak.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 20190114422 A1), hereinafter Johnson, in view of Klaiber et al. (US 7962909 B 1), hereinafter Klaiber, and Michalak et al. (US 20080046692 A1), hereinafter Michalak, as stated in claims 1, 2, 11, 13-15 and 17-20 above, and further in view of Mekkat et al. (US 20180285112 A1), hereinafter Mekkat.
Claims 4 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 20190114422 A1), hereinafter Johnson, as stated in claims 1, 11, 13- 15, 17 and 19 above, and further in view of Heller (US 20080288819 A1), hereinafter Heller.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 201901 14422 At), hereinafter Johnson, in view of Heller (US 20080288819 A1), hereinafter Heller, as stated in claims 1,4, 6-7, 11, 13-15, 17 and 19 above, and further in view of Cain (US 20100138571 A1), hereinafter Cain.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 20190114422 A1), hereinafter Johnson, in view of Heller et al. (US 20080288819 A1), hereinafter Heller, as stated in claims 1, 4, 6-8, 11, 13-15, 17 and 19 above, and further in view of Jacobson et al. (DE 112006001698 T5), hereinafter Jacobson.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 20190114422 A1), hereinafter Johnson, as stated in claims 1, 11, 13-15, 17 and 19 above, and further in view of Patel et al. (US 9378363 Bl), hereinafter Patel.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 20190114422 A1), hereinafter Johnson, as stated in claims 1, 11, 13-15, 17 and 19 above, and further in view of Atsushi et al. (JP H1196005 A), hereinafter Atsushi.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 20190114422 A1), hereinafter Johnson, as stated in claims 1, 11, 13-15, 17 and 19 above, and further in view of Boggs et al. (WO 2019005975 A1), hereinafter Boggs.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 20190114422 A1), hereinafter Johnson, as stated in claims 1, 11, 13-15, 17 and 19 above, and further in view of Christie et al. (US 6055650 A), hereinafter Christie.
As for Claim 1:
Applicant respectfully disagrees with the rejection of Claim 1.
In the Office Action, the Examiner asserted that Johnson anticipates Claim l as he allegedly teaches all claim limitations of Claim 1.
Applicant disagrees.
In particular, the Examiner stated that Johnson teaches "in a
fi
rst ti
m
e peri
od
performing an execution of a code segment in
a plurality of ti
m
e inte
rv
als"
(underlining and emphasis added by Applicant). The Examiner asserted that the structure in Johnson is "consistent" with the teachings of the application. The Examiner recited clauses from paragraph [0030] and [0033] of Johnson - "[0030] Lines 3-7; Initially, each microprocessor may include components to fetch, decode, and dispatch executable instructions for execution (e.g., an instruction fetcher 201, an instruction decoder 202, and an instruction dispatcher 203)...Typically, ...fetches a block of multiple execution instructions at a time.; [0033] Lines 1-3; Using this setup, a processor can continually fill a "pipeline," and execute instructions out-of-order and in parallel in this pipeline ".
Applicant contends that the above recitation merely describes common microprocessor structure and operation in out-of-order type of processing. Such common structure, being consistent with description of hardware structure described in the instant application, is not sufficient to assert that it teaches the claimed feature of performing an execution of a code in a plurality of time intervals during a first time period. The feature of repeated execution of the same code along a certain time period may be possible to be performed by the hardware of Johnson, but Johnson does not teach such feature. Definitely the combination of two time periods where in the first time period the code is executed multiple times, and in the second time period only a portion of this executed code which is committed is copied - this feature is not taught by Johnson.
Next, the Examiner stated that Johnson teaches "storing
s
p
eculative instructions
in an internal cache memory which is inaccessible to read actions of an external processing unit" (underlining added by Applicant). The Examiner noted that "[0075] Line 7; internal caches/buffers; [0118] Lines 8-13; the microprocessor can include first logic (e.g., circuitry and/or microcode) that records the effects of one or more speculatively-executed instructions to the one or more speculation buffers, and that records the effects of non-speculatively-executed instructions to the one or more conventional buffers".
Applicant argues that Johnson records
the effects of speculatively executed instructions
in speculation buffers. Applicant contends that
st
o
ring the effects
of the executed instructions does not teach storing
the speculative instructi
o
ns themselves
in an externally-non-accessible memory.
In light of the above arguments, Applicant respectfully submits that Claim 1 is not anticipated by Johnson and should be allowed.
However, in order to promote the examination, Applicant amended Claim 1 to include the subject matter of Claim 2.
Amended Claim 1 reads as follows, underlined by Applicant:
1.    A system for protecting a speculative execution processor, from side
channel attacks, comprising a processing circuitry, adapted to:
in afirst time period performing
a
p
lurality of executions
of a
sa
m
e
code
segment in a plurality of time intervals
and
m
eas
u
re an execution ti
m
e of the
code segment in each of the plurality of time intervals;
updating a time register to include a highest execution time measured
for the plurality of time intervals;
storing speculative instructions in an internal cache memory which is
inaccessible to read actions of an external processing unit;
in a second time period,
perf
ormin
g
a
d
ela
yed
copy, wherein in said
delayed copy,
copying only a committed portion of the executed code segment into another memory component which is accessible to read actions of the external processing
unit, wherein a delay time of said dela
y
ed co
p
y is according
to the highest execution time included in said time register;
wherein the first and second time periods are different and independent.
Basis for the amendment is the subject matter of Claim 2, which is incorporated into amended Claim 1. Claim 2 is now cancelled without prejudice.
In the Office Action, the Examiner rejected Claim 2 as allegedly being not patentable over Johnson, Klaiber and Michalak.
Applicant respectfully disagrees with the rejection of Claim 2.
At first, referring to Klaiber, Applicant contends that Klaiber does not teach measuring the execution time
of a same code multi
p
le times.
The Examiner asserted that Klaiber allegedly teaches "measure an execution time of the code segment in a plurality of time intervals". Applicant contends that Klaiber monitors execution time of a guest execution to limit it if needed. This does not teach the claim limitation "measure an execution time of th  code segment
in a
plu
rality of ti
m
e intervals".
The measurement of Klaiber is conducted for a completely different purpose, as the purpose of measuring the execution interval is for identifying when it exceeds a certain time limit, so that the executing guest may be interrupted. There is no teaching of measuring the execution time of multiple times execution of the same code, in order to identify its highest execution period.
Therefore, Klaiber does not teach this limitation.
Next, referring to Michalak. The Examiner stated that Michalak allegedly teaches "update a time register to include a
highest execution ti
m
e measured
for the plurality of time intervals" and
"delay
the copying only the committed portion of the executed code segment into the another memory component
according to the h
ig
hest execution time"
(underlining and emphasis added by Applicant).
Applicant contends that in Michalak, the delay determination mechanism is different and is not based on
highest executi
o
n time of the same code segment
as
measured
in multiple times executing the code segment, but on the "nature" of the speculative instructions.
Finally, referring to the combination asserted by the Examiner.
Applicant contends that the combination of Johnson, Klaiber and Michalak is impermissible hindsight-based combination, as there is no motivation for combining the references.
Applicant argues that Johnson, Klaiber and Michalak are each from a fundamentally different type of applications and the interpretation made in the Office Action to combine these references actually picks elements from one reference and detaches it out of its context. The three different applications are:
o Johnson - SPECULATIVE SIDE-CHANNEL ATTACK MITIGATIONS
by avoiding performing operations that could cause observable side effects
if the operation was mis predicted.
o Klaiber - LIMITING GUEST EXECUTION - time-based monitoring and
limiting guest execution.
o Michalak - METHOD
AND    APPARATUS
FOR   EXECUTING
PROCESSOR
INSTRUCTIONS BASED
ON   A  DYNAMICALLY
ALTERABLE DELAY.
Applicant contends that Johnson and Michalak use different approaches and there would be no technical reason to apply the delay of Michalak to the solution of Johnson, as Johnson mitigates side-channel attacks using a different approach - avoiding performing operations that could cause observable side effects if the operation was mis predicted. Applicant argues that applying Michalak's delay could only be done based on impermissible hindsight attempting to imitate the claimed invention.
Furthermore, Klaiber uses delay for a completely different application, not related to the problem solved by Johnson. The mere notion that Klaiber measures execution time of guest execution does not provide any reason to apply such measurement to Johnson's method, unless an impermissible attempt to imitate the claimed invention is done.
Therefore, Applicant respectfully submits that the combination of Johnson, Klaiber and Michalak does not teach the claim limitations of Claim 2, and is also an impermissible combination that should be dismissed.
As such, the subject matter of Claim 2 is new and non-obvious in view of Johnson, Klaiber and Michalak and therefore, amended Claim 1, which incorporates the subject matter of Claim 2, is not anticipated by Johnson, is new and non-obvious in view of Johnson, Klaiber and Michalak and should be allowed.
As for Claim 17:
Applicant respectfully disagrees with the rejection of Claim 17.
In the Office action, the Examiner stated that "claim 17 is directed to a method claim that recites a similar limitation as the system of claim 1. Therefore claimn 17 is rejected based on the same rational as claim 1 above".
Applicant submits that the arguments provided above against the rejection of Claim 1, apply, mutatis mutandis, against the rejection of Claim 17. Applicant respectfully submits that Claim 17 is not anticipated by Johnson and should be allowed.
However, similarly to Claim 1, Applicant amended Claim 17 and likewise, respectfully submits that Claim 17, at least in its amended form is not anticipated by Johnson, is new and non-obvious in view of Johnson, Klaiber and Michalak and should be allowed as well.
As for Claim 19:
Applicant respectfully disagrees with the rejection of Claim 19.
In the Office action, the Examiner stated that "claim 19 is directed to a computer program product claimn that recites a similar limitation as the system of claim 1. Therefore claim 19 is rejected based on the same rational as claim 1 above".
Applicant submits that the arguments provided above against the rejection of Claim 1, apply, mutatis mutandis, against the rejection of Claim 19. Applicant respectfully submits that Claim 19 is not anticipated by Johnson and should be allowed.
However, similarly to Claim 1, Applicant amended Claim 19 and likewise, respectfully submits that Claim 19, at least in its amended form is not anticipated by Johnson, is new and non-obvious in view of Johnson, Klaiber and Michalak and should be allowed as well.
As for Claim 10:
Applicant respectfully disagrees with the rejection of Claim 10.
In the Office Action, the Examiner asserted that lines 1-5 of paragraph [0015] of Atsushi allegedly teach "wherein the processing circuitry is adapted to perform a
double execution
of
t
he code se
g
ment"
(underlining and emphasis added by Applicant).
The Examiner recited the lines from Atsushi and underlined
"B
y
speculatively executing both the non-branch side and the non-branch side"
and
"such a
pro
cessin
g
method is referred to as "branch double execution".
Applicant is of the belief that the recitation is erroneous, and the translation from Japanese is:
"[0015] In order to achieve the above object, the present invention
effectively utilizes a thread execution unit on a parallel processing device having a plurality of thread execution units to branch instructions after a conditional branch instruction.
Both side and non-branch side are
sp
eculatively executed,
and when the conditional branch instruction is
confirmed, the execution on the wrong side is canceled,
so that it is possible to continue execution without the branch prediction being missed. Is achieved.
Hereinafter, such a processing method will be referred to as "branch
execution"."
Applicant acknowledges that Atsushi may teach "branch double execution" however, branch double execution does not refer to the
same code
but to two different segments of code - one segment is the non-branch side code segment and the other segment is the branch side code segment. According to Atsushi both code segments are executed and based on the actual result of the condition, one execution out of the two is cancelled.
As such - there is no double execution of a
same
code segment in Atsushi.
Therefore, Applicant respectfully submits that Claim 10 is new and non-obvious in view of Johnson and Atsushi and should be allowed and at least by virtue of its dependency from allowed amended Claim 1.
As for Claims 3-9 and I1-16:
Applicant respectfully submits that Claims 3-9 and 11-16 are allowable at least due to their dependency from allowed amended Claim 1.
Claims 2, 18 and 20 are cancelled herewith without prejudice.
Conclusion

NEXT OFFICE ACTION: DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgements
This communication is in response to
Application claim amendments filed on 08/21/2024, and
The amendments filed on 08/21/2024 have been entered.
The claims amendments overcome the objections and the USC 101 rejections previously set forth in the Office Action mailed on 06/21/2024.
Allowable Subject Matter
Claims 1, 3-17 and 19 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Cited and relevant prior art of record:
Johnson et al. (US 20190114422 A1),
Klaiber et al. (US 7962909 B1),
Michalak et al. (US 20080046692 A1), and
Courtney (US 20180323960 A1).
Johnson discloses processor modifications that prevent the observation of the side effects of mispredicted speculative execution flows, the processor can make use of speculative execution after a branch or conditional load, but avoid performing any operation that could cause observable side-effects if the operation was mispredicted, Johnson further discloses recording the effects of one or more speculatively-executed instructions to the one or more speculation buffers, utilize speculative execution after a branch or conditional load, and avoids observable side-effects of memory loads during this speculative execution by buffering the results/effects of those loads into one or more speculation buffers. Klaiber discloses monitoring a processor's execution core to detect an end of an execution interval, and causes the processor to exit a guest at the end of the execution interval. Michalak discloses a processor may directly write the dynamic delay value to a coprocessor register, highly speculative instructions may incur a greater execution delay while less speculative instructions may incur a lesser delay, each instruction or set of instructions offloaded to the coprocessor may incur an execution delay based on their speculative nature. For example, highly speculative instructions may incur a greater execution delay while less speculative instructions may incur a lesser delay. Courtney discloses a method and apparatus for defending against a side-channel attack upon a data storage device, and further discloses that in response to a function call signal being generated to request execution of a given function, a timer circuit is initiated to count out a predetermined elapsed time interval. The overall duration of the elapsed time interval is selected based on empirical or adaptive measurements, or system specifications, regarding the maximum likely duration of the execution of the function.
While the above prior arts disclose the aforementioned concepts, however, none of the prior arts, individually or in reasonable combination, discloses all the limitations in the manner recited in the independent claims. Specifically, none of the prior art discloses “…in a first time period performing, an execution of a code segment by storing speculative instructions in an internal cache memory which is inaccessible to read actions of an external processing unit; measuring an execution time of the code segment in a plurality of time intervals; updating a time register to include a highest execution time measured for the plurality of time intervals; in a second time period, performing a delayed copy, wherein in said delayed copy, copying only a committed portion of the executed code segment into another memory component which is accessible to read actions of the external processing unite wherein a delay time of said delayed copy is according to the highest execution time included in said time register; wherein the first and second time periods are different and independent”. Therefore, the above limitations in conjunction with the remaining limitations of the independent claims render the above independent claims allowable.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled Comments on Statement of Reasons for Allowance.
Conclusion

CITED REFERENCE SUMMARIES: Ref US20180323960A1: Claims:
A method of reducing leakage of side-channel information in a communication channel, comprising: initializing a timer circuit to denote an elapsed time interval of predetermined duration responsive to a function call by an initiator circuit; executing a selected cryptographic function upon input data to generate output data; temporarily storing the output data in a memory location prior to a conclusion of the elapsed time interval; receiving a notification from the timer circuit responsive to the conclusion of the elapsed time interval; and transferring the output data from the memory to the initiator circuit responsive to the notification from the timer circuit.
initializing a timer circuit to denote an elapsed time interval of predetermined duration responsive to a function call by an initiator circuit;
executing a selected cryptographic function upon input data to generate output data;
temporarily storing the output data in a memory location prior to a conclusion of the elapsed time interval;
receiving a notification from the timer circuit responsive to the conclusion of the elapsed time interval; and
transferring the output data from the memory to the initiator circuit responsive to the notification from the timer circuit.
The method of claim 1 , wherein the input data is a first set of input data, the output data is a first set of output data and a crypto engine circuit generates the first set of output data over a first interval of time having a first duration less than the predetermined duration, and wherein the initializing, using, temporarily storing, receiving and transferring steps are repeated for a different, second set of input data to generate a second set of output data over a second interval of time having a second duration less than the first duration.
The method of claim 2 , wherein the elapsed time interval denoted by the timer circuit has the same predetermined duration for both the first set of output data and the second set of output data so that both the first set of output data and the second set of output data are nominally received by the initiator circuit after the respective function calls by the initiator circuit by a common amount of elapsed time corresponding to the predetermined duration.
The method of claim 2 , wherein the elapsed time interval denoted by the timer circuit is a first elapsed time interval having a first overall duration during the generation of the first set of output data established responsive to a first random number, and the elapsed time interval denoted by the timer circuit is a second elapsed time interval having a different, second overall duration during the generation of the second set of output data established responsive to a different, second random number.
The method of claim 1 , wherein the timer circuit is initialized by supplying the timer circuit with an initial value, and the timer circuit operates to count up or down to a final value responsive to the initial value, the initial value corresponding to the predetermined duration of the elapsed time interval.
The method of claim 5 , wherein the same initial value is supplied to the timer circuit for the execution of the selected cryptographic function upon a plurality of different sets of input data.
The method of claim 1 , wherein a control circuit is configured to receive the function call, select a timer initialization value in response to the function call, and initialize the timer circuit using the timer initialization value.
The method of claim 1 , further comprising executing a second function during an interval of time during which the output data are temporarily stored in the memory location and prior to receiving the notification from the timer circuit at the conclusion of the elapsed time interval.
The method of claim 8 , wherein the selected cryptographic function is executed by a crypto engine circuit to generate the output data, and the second function is performed by the crypto engine circuit upon dummy data not associated with a function call to generate output data responsive to input data.
The method of claim 1 , wherein the input data are encrypted user data stored on a main memory of a data storage device, and the selected cryptographic function operates to decrypt the encrypted user data retrieved from the main memory responsive to a host access command received from a host device coupled to the data storage device.
The method of claim 1 , wherein the use of the timer circuit is configured to defeat a potential timing attack upon a data storage device, and the execution of the selected cryptographic function comprises use of a modulated clock rate at different frequencies during the generation of the output data to defeat a potential differential power analysis (DPA) attack upon the data storage device.
An apparatus comprising: an initiator circuit configured to issue a function call to perform a selected cryptographic function upon input data; a timer circuit configured to denote an elapsed time interval of predetermined duration responsive to an initialization value supplied responsive to the function call by the initiator circuit; a crypto engine circuit configured to execute the selected cryptographic function upon the input data to generate output data during the elapsed time interval; a memory configured to temporarily store the output data prior to a conclusion of the elapsed time interval; and a control circuit configured to receive a notification from the timer circuit responsive to the conclusion of the elapsed time interval, and to transfer the output data from the memory to the initiator circuit responsive to the notification from the timer circuit.
an initiator circuit configured to issue a function call to perform a selected cryptographic function upon input data;
a timer circuit configured to denote an elapsed time interval of predetermined duration responsive to an initialization value supplied responsive to the function call by the initiator circuit;
a crypto engine circuit configured to execute the selected cryptographic function upon the input data to generate output data during the elapsed time interval;
a memory configured to temporarily store the output data prior to a conclusion of the elapsed time interval; and
a control circuit configured to receive a notification from the timer circuit responsive to the conclusion of the elapsed time interval, and to transfer the output data from the memory to the initiator circuit responsive to the notification from the timer circuit.
The apparatus of claim 12 , wherein the control circuit is configured to supply the initialization value to the timer circuit responsive to receipt, by the control circuit, of the function call.
The apparatus of claim 13 , wherein the control circuit is further configured to issue the same initialization value to the timer circuit for each received function call from the initiator device for execution of the selected cryptographic function irrespective of the associated input data.
The apparatus of claim 12 , wherein the initiator circuit is a programmable processor having associated programming in a processor memory, and the function call is a software/firmware based command issued by the programmable processor.
The apparatus of claim 12 , wherein the elapsed time interval denoted by the timer circuit has the same predetermined duration for both a first set of output data and a second set of output data from the crypto engine circuit so that both the first set of output data and the second set of output data are nominally received by the initiator circuit after the respective function calls by the initiator circuit by a common amount of elapsed time corresponding to the predetermined duration.
The apparatus of claim 12 , wherein the control circuit is further configured to forward a request along with the input data to the crypto engine to execute the cryptographic function, to receive the output data from the crypto engine at a conclusion of the execution of the cryptographic function, and to place the received output data in the memory pending receipt of the notification from the timer circuit.
The apparatus of claim 17 , wherein the control circuit is further configured to forward a second request to the crypto engine to perform a different, second function during an interval of time during which the output data are temporarily stored in the memory and prior to receiving the notification from the timer circuit at the conclusion of the elapsed time interval.
The apparatus of claim 12 , characterized as a data storage device further comprising a main memory, wherein the input data are encrypted user data stored in the main memory, and the selected cryptographic function operates to decrypt the encrypted user data retrieved from the main memory responsive to a host access command received from a host device coupled to the data storage device.
The apparatus of claim 12 , further comprising a differential power attack (DPA) countermeasures circuit which supplies a modulated clock signal at different frequencies to the crypto engine circuit during the generation of the output data.
Ref US20190114422A1: Claims:
A microprocessor, comprising: a register file comprising a plurality of entries, each entry comprising a value and a flag, the microprocessor configured to: set the flag corresponding to any entry whose value (i) results from a memory load operation that has not yet been retired or cancelled, or (ii) results from a calculation that was derived from a register file entry whose corresponding flag was set; and clear the flag corresponding to any entry when the operation that generated the entry's value is retired; and a memory unit that is configured to hold any memory load operation that uses an address whose value is calculated based on a register file entry whose flag is set, unless all previous instructions have been retired or cancelled.
a register file comprising a plurality of entries, each entry comprising a value and a flag, the microprocessor configured to: set the flag corresponding to any entry whose value (i) results from a memory load operation that has not yet been retired or cancelled, or (ii) results from a calculation that was derived from a register file entry whose corresponding flag was set; and clear the flag corresponding to any entry when the operation that generated the entry's value is retired; and
set the flag corresponding to any entry whose value (i) results from a memory load operation that has not yet been retired or cancelled, or (ii) results from a calculation that was derived from a register file entry whose corresponding flag was set; and
clear the flag corresponding to any entry when the operation that generated the entry's value is retired; and
a memory unit that is configured to hold any memory load operation that uses an address whose value is calculated based on a register file entry whose flag is set, unless all previous instructions have been retired or cancelled.
The microprocessor of claim 1 , wherein setting a flag marks its corresponding entry as pending.
The microprocessor of claim 1 , wherein the memory unit continues a held memory load operation when all previous instructions have been retired.
The microprocessor of claim 1 , wherein the memory unit cancels a held memory load operation when all previous instructions have been cancelled.
The microprocessor of claim 1 , wherein the register file is also configured to invalidate any entry when the operation that generated the entry's value is cancelled.
The microprocessor of claim 1 , wherein the microprocessor tracks whether there are any unresolved branches, and the register file is also configured to clear all flags in the register file when there are no unresolved branches.
The microprocessor of claim 1 , wherein the microprocessor tracks whether there are any unresolved conditional loads, and register file is also configured to clear all flags in the register file when there are no unresolved conditional loads.
The microprocessor of claim 1 , wherein the microprocessor tracks a youngest parent branch or conditional load for each instruction, and holds execution of speculative memory loads that depend on one another while the youngest parent branch or conditional load has yet to resolve.
The microprocessor of claim 8 , wherein store-to-load forwarding that is internal to the microprocessor is permitted to execute, even when a speculative load operation depends on a previous speculative store operation while the youngest parent branch or conditional load has yet to resolve.
The microprocessor of claim 1 , wherein the microprocessor tracks branch state for each instruction, and updates the flag corresponding to entries modified by an instruction based on the branch state for the instruction.
The microprocessor of claim 8 , wherein updates to a branch target cache are deferred until after a branch instruction has retired.
The microprocessor of claim 1 , further comprising a mode bit that controls whether memory load operations are held based on register file flags.
A method, implemented at a microprocessor that includes (i) a register file comprising a plurality of entries, each entry comprising a value and a flag, and (ii) a memory unit, the method comprising: setting the flag corresponding to any entry whose value (i) results from a memory load operation that has not yet been retired or cancelled, or (ii) results from a calculation that was derived from a register file entry whose corresponding flag was set; clearing the flag corresponding to any entry when the operation that generated the entry's value is retired; and holding, in the memory unit, any memory load operation that uses an address whose value is calculated based on a register file entry whose flag is set, unless all previous instructions have been retired or cancelled.
setting the flag corresponding to any entry whose value (i) results from a memory load operation that has not yet been retired or cancelled, or (ii) results from a calculation that was derived from a register file entry whose corresponding flag was set;
clearing the flag corresponding to any entry when the operation that generated the entry's value is retired; and
holding, in the memory unit, any memory load operation that uses an address whose value is calculated based on a register file entry whose flag is set, unless all previous instructions have been retired or cancelled.
The method of claim 13 , wherein setting a flag marks its corresponding entry as pending.
The method of claim 13 , further comprising continuing a held memory load operation when all previous instructions have been retired.
The method of claim 13 , further comprising canceling a held memory load operation when all previous instructions have been cancelled.
The method of claim 13 , further comprising invalidating any register file entry when the operation that generated the entry's value is cancelled.
The method of claim 13 , further comprising: tracking whether there are any unresolved branches; and clearing all flags in the register file when there are no unresolved branches.
tracking whether there are any unresolved branches; and
clearing all flags in the register file when there are no unresolved branches.
The method of claim 13 , further comprising: tracking whether there are any unresolved conditional loads, and clearing all flags in the register file when there are no unresolved conditional loads.
tracking whether there are any unresolved conditional loads, and
clearing all flags in the register file when there are no unresolved conditional loads.
A processing unit comprising (i) a register file that includes a plurality of entries that each comprise a value and a flag, (ii) a memory unit, and (iii) control logic that configures the processing unit to: set the flag corresponding to any entry whose value (i) results from a memory load operation that has not yet been retired or cancelled, or (ii) results from a calculation that was derived from a register file entry whose corresponding flag was set; clear the flag corresponding to any entry when the operation that generated the entry's value is retired; and hold, in the memory unit, any memory load operation that uses an address whose value is calculated based on a register file entry whose flag is set, unless all previous instructions have been retired or cancelled.
set the flag corresponding to any entry whose value (i) results from a memory load operation that has not yet been retired or cancelled, or (ii) results from a calculation that was derived from a register file entry whose corresponding flag was set;
hold, in the memory unit, any memory load operation that uses an address whose value is calculated based on a register file entry whose flag is set, unless all previous instructions have been retired or cancelled.
Ref US20080046692A1: Claims:
A method of controlling instruction execution, comprising: determining a first delay value for a first set of one or more instructions; delaying execution of the first set of one or more instructions based on the first delay; determining a second delay value for a second set of one or more instructions; and delaying execution of the second set of one or more instructions based on the second delay;
determining a first delay value for a first set of one or more instructions;
delaying execution of the first set of one or more instructions based on the first delay;
determining a second delay value for a second set of one or more instructions; and
delaying execution of the second set of one or more instructions based on the second delay;
The method of claim 1 , further comprising associating individual ones of the delay values with the corresponding set of one or more instructions.
The method of claim 2 , wherein associating individual ones of the delay values with the corresponding set of one or more instructions comprises tagging each set of one or more instructions with the corresponding delay value.
The method of claim 1 , wherein the delay values are determined during at least one of code compile time, code load time, and code run time.
The method of claim 1 , wherein the delay values are determined based on an application associated with the corresponding set of instructions.
The method of claim 5 , wherein the delay values are determined based on processor resources available to the corresponding application.
The method of claim 1 , wherein the delay values are determined based on processor resources available to a corresponding application.
The method of claim 1 , wherein determining the delay values comprises: maintaining a history of speculative instruction execution; and determining the delay values based on the history of speculative instruction execution.
maintaining a history of speculative instruction execution; and
determining the delay values based on the history of speculative instruction execution.
The method of claim 8 , wherein maintaining a history of speculative instruction execution comprises tracking occurrences of execution pipeline flushes.
The method of claim 1 , wherein the delay values indicate at least one of full-speculative instruction execution, non-speculative instruction execution, full-speculative instruction execution after a number of instruction processing delay cycles, and partially-speculative instruction execution.
The method of claim 10 , wherein partially-speculative instruction execution comprises halting execution of each instruction at a specified stage until the corresponding instruction is committed.
The method of claim 1 , wherein determining the delay values comprises: processing individual ones of the sets of one or more instructions to ascertain the corresponding delay value; and directing storage of the delay values.
processing individual ones of the sets of one or more instructions to ascertain the correspond
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