Office Action 1: Non-Final Rejection (2024-12-26)
Rejection types: 102 - Lack of Novelty

CLAIMS:
Claims

\[Claim 1\] A device (1) for processing a pilot control signal (CP) having at least two modes: a continuous mode in which the pilot control signal (CP) comprises a continuous signal or an alternating mode in which the pilot control signal (CP) comprises an alternating PWM signal, and capable of generating a binary detection signal (SD), the state of which is an indication of the mode, characterized in that the device (1) comprises a voltage doubler (D) and a comparator (C).

\[Claim 2\] The device (1) as claimed in claim 1, in which the pilot control signal (CP) is as defined by the standard IEC 61851.

\[Claim 3\] The device (1) as claimed in either one of claims 1 and 2, in which the voltage doubler (D) is a Greinacher voltage doubler.

\[Claim 4\] The device (1) as claimed in claim 3, in which the Greinacher voltage doubler comprises a first capacitor (C2), of which a first terminal is connected to an input of the voltage doubler (D) and of the device (1) capable of receiving the pilot control signal (CP), a first diode (Dl), of which the anode is connected to ground (Gnd) and the cathode is connected to a second terminal of the first capacitor (C2), a second diode (D2), of which the anode is connected to the cathode of the first diode (Dl) and the cathode is connected to an output of the voltage doubler (D), a second capacitor (Cl), of which a first terminal is connected to the output of the voltage doubler (D) and a second terminal is connected to ground (Gnd), and a resistor (Rl), of which a first terminal is connected to the output of the voltage doubler (D) and a second terminal is connected to ground (Gnd).

\[Claim 5\] The device (1) as claimed in any one of claims 1 to 3, in which the comparator (C) comprises a Zener diode (Zl), of which the cathode is connected to the output of the voltage doubler (D) and to the input of the comparator (C).

\[Claim 6\] The device (1) as claimed in claim 5, in which the comparator (C) further comprises a first transistor (Ti) of NPN type, of which the base is connected to the anode of the Zener diode (Zi) and the emitter is connected to ground (Gnd), and a second transistor (T2) of PNP type, of which the base is connected to the collector of the first transistor (Ti), the emitter is connected to a supply voltage (V) and the collector is connected to the output of the comparator (C) and of the device (1) and generates the detection signal (SD).

\[Claim 7\] The application to waking up a computer for an electric vehicle, when the electric vehicle is connected to an active charging station using a processing device as claimed in one of the preceding claims.

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
1.	The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2.	The information disclosure statement (IDS) submitted on 07/13/22 has been considered by the examiner.
Priority
3.	Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
4.	The disclosure is objected to because of the following informalities: on the first line of paragraph [0009], the word subject should be changed to either --object-- or
--objective--, and also on this line, --to provide-- should be inserted after the word is. On the first line of paragraph [0023], the word --its-- should be inserted after at. On the penultimate line of paragraph [0028], the word In should be changed to --IN--. On line 8 of paragraph [0030], it appears that +V should be changed to -- +12V--, the reason being that figure 4 of the instant drawings shows that +12 V is supplied to the second transistor T2.
Appropriate correction is required.
Drawings
5.	The drawings are objected to because figures 1-3 of the instant drawings need to be provided with prior art labels.  Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
6.	The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakahara et al, U.S. Patent No. 5,229,818.
As to claim 1, Nakahara et al discloses, in figure 4,
a device (the combination of the voltage doubler constituted by capacitors C4 and C5, diodes D2 and D3, and resistor R4, together with comparator 16) for processing a pilot control signal (the pilot control signal is just intended use because it is not an integral component of the claimed device but rather the signal that is received by the claimed device, and therefore all of the recitations regarding the pilot control signal are similarly just intended use and as such cannot be relied upon to distinguish over Nakahara et al) having at least two modes: a continuous mode in which the pilot control signal comprises a continuous signal or an alternating mode in which the pilot control signal comprises an alternating PWM signal (as noted above, all of the recitations in claim 1 regarding the pilot control signal are just intended use and as such cannot be relied upon to distinguish over Nakahara et al) and capable of generating a binary detection signal (note that the output of comparator 16 is a binary detection signal), the state of which is an indication of the mode, the device comprising a voltage doubler and a comparator (as noted above, the voltage doubler and comparator can be read on the combination of the voltage doubler constituted by capacitors C4 and C5, diodes D2 and D3, and resistor R4, together with comparator 16).
As to claim 2, again the claimed pilot control signal and any details regarding this signal are just intended use and as such cannot be relied upon to distinguish over Nakahara et al.
As to claim 3, note that Nakahara et al's voltage doubler is a Greinacher voltage doubler.
As to claim 4, the claimed first capacitor reads on capacitor C5, the claimed first diode reads on diode D3, the claimed second diode reads on diode D2, the claimed second capacitor reads on capacitor C4, and the claimed resistor reads on resistor R4.
7.	Claims 1-3 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jinno et al, U.S. Patent Application Publication No. 2002/0008629.
As to claim 1, Jinno et al discloses, in figure 46,
a device (the combination of the voltage doubler constituted by capacitor C341, capacitor C342,  diode D341 and diode D342, together with comparator N1) for processing a pilot control signal (as noted above, the pilot control signal is just intended use because it is not an integral component of the claimed device, and therefore all of the recitations about the pilot control signal are similarly just intended use and as such cannot be relied upon to distinguish over Jinno et al) having at least two modes: a continuous mode in which the pilot control signal comprises a continuous signal or an alternating mode in which the pilot control signal comprises an alternating PWM signal (as noted above, all of the recitations in claim 1 regarding the pilot control signal are just intended use and as such cannot be relied upon to distinguish over Jinno et al), and capable of generating a binary detection signal (note that the output of comparator N1 is a binary detection signal), the state of which is an indication of the mode, the device comprising a voltage doubler and a comparator (as noted above, the voltage doubler can be read on the combination of the voltage doubler constituted by capacitor C341, capacitor C342, diode D341 and diode D342, and the comparator can be read on circuit N1)
As to claim 2, again the claimed pilot control signal and any details about this signal are just intended use and as such cannot be relied upon to distinguish over Jinno et al.
As to claim 3, note that Jinno et al's voltage doubler is a Greinacher voltage doubler.
As to claim 5, note that the cathode zener diode D343 is connected to the output of Jinno et al's voltage doubler and to the input of the comparator N1.
Allowable Subject Matter
8.	Claims 6 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior art of record, including Nakahara et al and Jinno et al, discloses or suggests the device of claim 5 with the further limitations that the comparator comprises a first transistor of NPN type, of which the base is connected to the anode of the zener diode and the emitter is connected to the ground, and a second transistor of PNP type, of which the base is connected to the collector of the first transistor, the emitter is connected to a supply voltage and the collector is connected to the output of the comparator and of the device and generates the detection signal, as recited in claim 6; nor does any of the prior art of record, including Nakahara et al and Jinno et al, disclose or suggest the details of claim 7, i.e., an application of waking up a computer for an electric vehicle, when the electric vehicle is connected to an active charging station using a processing device as claimed in independent claim 1.
Prior Art Not Relied Upon
9.	The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Note also figure 19 of Futsuhara et al which shows another example of a voltage doubler (voltage doubler REC1) which receives an oscillating pilot control signal and which has an output provided to the input of a comparator (comparator W1 by itself or in combination with circuit REC3). Also note figure 1D of Da which also shows a voltage doubler 14 which provides an output to comparator 15. Note further figure 1 of Chen and figure 3B of Sen et al which show further examples of a Greinacher voltage doubler which includes a pair of capacitors and a pair of diodes together with a resistor, as recited in claim 4.
Conclusion
10.


NEXT OFFICE ACTION: DETAILED ACTION
Response to Amendment
1.	Applicant's amendment filed on 01/23/25 has been received and entered in the case. Claims 6 and 7 are allowable over all of the prior art of record for the reasons indicated in the previous office action. However, because no arguments have been set forth by applicant against the previously applied prior art rejections based on Nakahara et al and Jinno et al, claims 1-5 remain rejected based on these two references, for the reasons set forth in the previous office action.
Claim Objections
2.	Claim 1 is objected to because of the following informalities:
On the first line of claim 1, a comma should be inserted after the word signal. Also in claim 1, the word --and-- should be inserted at the end of line 3, and note that the word and at the beginning of line 4 should be deleted.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
3.	The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakahara et al, U.S. Patent No. 5,229,818.
As to claim 1, Nakahara et al discloses, in figure 4,
a device (the combination of the voltage doubler constituted by capacitors C4 and C5, diodes D2 and D3, and resistor R4, together with comparator 16) for processing a pilot control signal (as indicated in the previous office action, the pilot control signal is just intended use because it is not an integral component of the claimed device, i.e., the pilot control signal is just what is received by the claimed device, and therefore all of the recitations regarding the pilot control signal are similarly just intended use and as such cannot be relied upon to distinguish over Nakahara et al), the device comprising
a voltage doubler (the voltage doubler formed by the combination of capacitors C4 and C5, diodes D2 and D3, and resistor R4); and
a comparator (comparator 16),
the pilot control signal having at least two modes: a continuous mode in which the pilot control signal comprises a continuous signal or an alternating mode in which the pilot control signal comprises an alternating PWM signal (as indicated above, all of the recitations in claim 1 regarding the pilot control signal are just intended use and as such cannot be relied upon to distinguish over Nakahara et al), and
the comparator outputs a binary detection signal (note that the output of comparator 16 is a binary detection signal) based on an input of the pilot control signal to the voltage doubler (as indicated above, all of the recitations in claim 1 regarding the pilot control signal are just intended use and as such cannot be relied upon to distinguish over Nakahara et al), a state of the binary detection signal being an indication of the mode of the pilot control signal (again, all of the recitations in claim 1 regarding the pilot control signal are just intended use and as such cannot be relied upon to distinguish over Nakahara et al).
As to claim 2, as noted above, the claimed pilot control signal and any details regarding this signal are just intended use and as such cannot be relied upon to distinguish over Nakahara et al.
As to claim 3, as indicated in the previous office action, Nakahara et al's voltage doubler is a Greinacher voltage doubler.
As to claim 4, as indicated in the previous office action, the claimed first capacitor reads on capacitor C5, the claimed first diode reads on diode D3, the claimed second diode reads on diode D2, the claimed second capacitor reads on capacitor C4, and the claimed resistor reads on resistor R4.
4.	Claims 1-3 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jinno et al, U. S. Patent Application Publication No. 2002/0008629.
As to claim 1, Jinno et al discloses, in figure 46,
a device (the combination of the voltage doubler constituted by capacitor C341, capacitor C342, diode D341 and diode D342, together with comparator N1) for processing a pilot control signal (as indicated in the previous office action, the pilot control signal is just intended use because it is not an integral component of the claimed device but rather the signal that is received by the claimed device, and therefore all of the recitations regarding the pilot control signal are similarly just intended use and as such cannot be relied upon to distinguish over Jinno et al), the device comprising
a voltage doubler (the voltage doubler formed by the combination of capacitor C341, capacitor C342, diode D341 and diode D342); and
a comparator (comparator N1),
the pilot control signal having at least two modes: a continuous mode in which the pilot control signal comprises a continuous signal or an alternating mode in which the pilot control signal comprises an alternating PWM signal (as indicated above, all of the recitations in claim 1 regarding the pilot control signal are just intended use and as such cannot be relied upon to distinguish over Jinno et al), and
the comparator outputs a binary detection signal (note that the output of comparator N1 is a binary detection signal) based on an input of the pilot control signal to the voltage doubler (as indicated above, all of the recitations in claim 1 regarding the pilot control signal are just intended use and as such cannot be relied upon to distinguish over Jinno et al), a state of the binary detection signal being an indication of the mode of the pilot control signal (as indicated above, all of the recitations in claim 1 regarding the pilot control signal are just intended use and as such cannot be relied upon to distinguish over Jinno et al).
As to claim 2, as indicated above, the claimed pilot control signal and any details regarding this signal are just intended use and as such cannot be relied upon to distinguish over Nakahara et al.
As to claim 3, as noted in the previous office action, Jinno et al's voltage doubler is a Greinacher voltage doubler.
As to claim 5, as noted in the previous office action, the cathode of zener diode D343 is connected to the output of Jinno et al's voltage doubler and to the input of the comparator N1.
Allowable Subject Matter
5.	Claims 6 and 7 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: claims 6 and 7 are allowed for the reasons indicated in the previous office action.
Action is Final
6.	THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Conclusion
7.

CITED REFERENCE SUMMARIES: Ref US20170300098A1: Claims:
A method, executable by a computing accessory, the method comprising: capturing a wifi signal from a computing device corresponding to the computing accessory; harvesting energy from the captured wifi signal; and powering the computing accessory based on the harvested energy.
capturing a wifi signal from a computing device corresponding to the computing accessory;
harvesting energy from the captured wifi signal; and
powering the computing accessory based on the harvested energy.
The method of claim 1 wherein capturing the wifi signal from the computing device corresponding to the computing accessory includes: tuning an antenna circuit, internal to the computing accessory, to capture energy from the wifi signal between 0.01 milliwatts and two milliwatts.
tuning an antenna circuit, internal to the computing accessory, to capture energy from the wifi signal between 0.01 milliwatts and two milliwatts.
The method of claim 1 further comprising: determining an amount of energy available, from the wifi signal, to tune a circuit within the computing accessory.
determining an amount of energy available, from the wifi signal, to tune a circuit within the computing accessory.
The method of claim 1 wherein the computing device transmits the wifi signal and an associated power between 50 milliwatts and 200 milliwatts.
The method of claim 1 wherein capturing the wifi signal from the corresponding computing device includes: forming a radiation pattern no greater than 90 degrees from the computing accessory to the computing device.
forming a radiation pattern no greater than 90 degrees from the computing accessory to the computing device.
A computing accessory comprising: an antenna module to capture a wifi signal from a corresponding computing device; a rectifying circuit to convert an analog power associated with the wifi signal from the antenna module to a direct current (DC) voltage; and a power management circuit to: supply the DC voltage to the computing accessory for operation of the computing accessory, wherein the DC voltage is a primary source of power for the computing accessory.
an antenna module to capture a wifi signal from a corresponding computing device;
a rectifying circuit to convert an analog power associated with the wifi signal from the antenna module to a direct current (DC) voltage; and
a power management circuit to: supply the DC voltage to the computing accessory for operation of the computing accessory, wherein the DC voltage is a primary source of power for the computing accessory.
supply the DC voltage to the computing accessory for operation of the computing accessory, wherein the DC voltage is a primary source of power for the computing accessory.
The computing accessory of claim 6 wherein the computing accessory is a mouse and the antenna module includes a mono-polar antenna located below a scroll wheel of the mouse.
The computing accessory of claim 6 wherein the corresponding computing device is a computer configured to receive input from the computing accessory.
The computing accessory of claim 6 wherein a distance between the computing accessory and the corresponding computing device is no greater than one meter for capturing the wifi signal.
The computing accessory of claim 6 comprising: a conditioning circuit to receive the DC voltage from the rectifying circuit and convert the DC voltage to a voltage for use by the computing accessory; and a battery module, internal to the computing accessory, to receive the voltage for use by the computing accessory, the voltage is the primary source of power for operation of the computing accessory.
a conditioning circuit to receive the DC voltage from the rectifying circuit and convert the DC voltage to a voltage for use by the computing accessory; and
a battery module, internal to the computing accessory, to receive the voltage for use by the computing accessory, the voltage is the primary source of power for operation of the computing accessory.
The computing accessory of claim 6 wherein the rectifying circuit includes at least two half-wave rectifiers to double the analog power for producing the DC voltage.
The computing accessory of claim 6 comprising: a tuning circuit to match impedance of the antenna module to an expected received power of the wifi signal between 0.01 milliwatts and two milliwatts.
a tuning circuit to match impedance of the antenna module to an expected received power of the wifi signal between 0.01 milliwatts and two milliwatts.
A non-transitory machine-readable storage medium comprising instructions that when executed by a processor cause a computing accessory to: capture a wifi signal at least 2.4 gigahertz (GHz) from a computing device corresponding to the computing accessory; convert an analog power extracted from the wifi signal to a direct current (DC) voltage; and utilize the DC voltage as a primary source of power for operation of the computing accessory.
capture a wifi signal at least 2.4 gigahertz (GHz) from a computing device corresponding to the computing accessory;
convert an analog power extracted from the wifi signal to a direct current (DC) voltage; and
utilize the DC voltage as a primary source of power for operation of the computing accessory.
The non-transitory machine-readable storage medium including the instructions of claim 13 wherein to capture the wifi signal at least 2.4 GHz from the computing device associated with the computing accessory includes instructions that when executed by the processor cause the computing accessory to: form a radiation pattern no greater than 90 degrees to the computing device; and tune a circuit by matching an impedance of an antenna to the analog power transmitted with the wifi signal between 50 milliwatts and 200 milliwatts.
form a radiation pattern no greater than 90 degrees to the computing device; and
tune a circuit by matching an impedance of an antenna to the analog power transmitted with the wifi signal between 50 milliwatts and 200 milliwatts.
A system comprising: a computing device to: determine a location of a computing accessory harvesting energy from a wifi signal; based on the determined location of the computing accessory, form a radiation pattern for focusing transmission of a wifi signal; and
a computing device to: determine a location of a computing accessory harvesting energy from a wifi signal; based on the determined location of the computing accessory, form a radiation pattern for focusing transmission of a wifi signal; and
determine a location of a computing accessory harvesting energy from a wifi signal;
based on the determined location of the computing accessory, form a radiation pattern for focusing transmission of a wifi signal; and
the computing accessory corresponding to the computing device to harvest energy from the wifi signal, wherein an amount of the harvested energy depends on the radiation pattern focused on the location of the computing accessory.
Ref US20160315478A1: Claims:
An electrical circuit for harvesting un-converted AC signals at the output of an AC-to-DC converter circuit, comprising: a DC blocking electrical circuit or circuit element in electrical communication with the output of the AC-to-DC converter circuit, the DC blocking electrical circuit or circuit element having an input and output; an impedance matching circuit or circuit element having an input and output, wherein the input of the impedance matching circuit or circuit element is in electrical communication with the output of the DC blocking electrical circuit or circuit element; a rectifying circuit or circuit element having an input and output, wherein the input of the rectifying circuit or circuit element is in electrical communication with the output of the impedance matching electrical circuit or circuit element; and an AC blocking circuit or circuit element having an input and output and wherein the input of the AC blocking circuit or circuit element is in electrical communication with the output of the AC-to-DC converter circuit for allowing direction of the un-converted AC signals to the DC blocking electrical circuit or circuit element.
a DC blocking electrical circuit or circuit element in electrical communication with the output of the AC-to-DC converter circuit, the DC blocking electrical circuit or circuit element having an input and output;
an impedance matching circuit or circuit element having an input and output, wherein the input of the impedance matching circuit or circuit element is in electrical communication with the output of the DC blocking electrical circuit or circuit element;
a rectifying circuit or circuit element having an input and output, wherein the input of the rectifying circuit or circuit element is in electrical communication with the output of the impedance matching electrical circuit or circuit element; and
an AC blocking circuit or circuit element having an input and output and wherein the input of the AC blocking circuit or circuit element is in electrical communication with the output of the AC-to-DC converter circuit for allowing direction of the un-converted AC signals to the DC blocking electrical circuit or circuit element.
An electrical circuit according to claim 1 , wherein the AC-to-DC converter circuit is a rectifier circuit and wherein the un-converted AC signals are un-rectified AC signals.
An electrical circuit according to claim 1 , wherein the output of the AC blocking circuit or circuit element is in electrical communication with the output of the rectifying circuit or circuit element, and wherein the output of the AC blocking circuit or circuit element and the output of the rectifying circuit or circuit element form the output of the electrical circuit for harvesting un-converted AC signals.
An electrical circuit according to claim 1 , wherein the un-converted AC signals are harmonic signals whose frequencies are multiples of the fundamental frequency.
An electrical circuit according to claim 1 , wherein one of the un-converted AC signals is an RF signal leaked to the output of the AC-to-DC converter circuit.
An electrical circuit according to claim 1 , wherein the DC blocking electrical circuit or circuit element is a capacitor.
An electrical circuit according to claim 1 , wherein the DC blocking electrical circuit or circuit element is a high-pass filter.
An electrical circuit according to claim 1 , wherein the AC blocking circuit or circuit element is an inductor.
An electrical circuit according to claim 1 , wherein the AC blocking circuit or circuit element is a low-pass filter.
An electrical circuit according to claim 1 , wherein the AC-to-DC converter circuit is a conventional rectifier circuit.
An electrical circuit according to claim 1 , wherein the AC blocking circuit or circuit element prevents fundamental and harmonic signals from being shorted to ground.
An electrical circuit according to claim 1 , further comprising a second electrical circuit for harvesting un-converted AC signals in series with the electrical circuit for harvesting un-converted AC signals.
An electrical circuit for harvesting un-converted AC signals at the output of a first AC-to-DC converter circuit, comprising: a DC blocking electrical circuit or circuit element in electrical communication with the output of the first AC-to-DC converter circuit, the DC blocking electrical circuit or circuit element having an input and output; an impedance matching circuit or circuit element having an input and output, wherein the input of the impedance matching circuit or circuit element is in electrical communication with the output of the DC blocking electrical circuit or circuit element; a second AC-to-DC converter circuit or circuit element having an input and output, wherein the input of the second AC-to-DC converter circuit or circuit element is in electrical communication with the output of the impedance matching electrical circuit or circuit element; and an AC blocking circuit or circuit element having an input and output, wherein the input of the AC blocking circuit or circuit element is in electrical communication with the output of the first AC-to-DC converter circuit for allowing direction of the un-converted AC signals to the DC blocking electrical circuit or circuit element.
a DC blocking electrical circuit or circuit element in electrical communication with the output of the first AC-to-DC converter circuit, the DC blocking electrical circuit or circuit element having an input and output;
a second AC-to-DC converter circuit or circuit element having an input and output, wherein the input of the second AC-to-DC converter circuit or circuit element is in electrical communication with the output of the impedance matching electrical circuit or circuit element; and
an AC blocking circuit or circuit element having an input and output, wherein the input of the AC blocking circuit or circuit element is in electrical communication with the output of the first AC-to-DC converter circuit for allowing direction of the un-converted AC signals to the DC blocking electrical circuit or circuit element.
An electrical circuit according to claim 13 , wherein the first and second AC-to-DC converter circuits are rectifier circuits and wherein the un-converted AC signals are un-rectified AC signals.
An electrical circuit according to claim 13 , wherein the output of the AC blocking circuit or circuit element is in electrical communication with the output of the second AC-to-DC converter circuit or circuit element, and wherein the output of the AC blocking circuit or circuit element and the output of the second AC-to-DC converter circuit or circuit element form the output of the electrical circuit for harvesting un-converted AC signals.
An electrical circuit according to claim 13 , wherein the AC blocking circuit or circuit element prevents fundamental and harmonic signals from being shorted to ground.
An electrical circuit according to claim 13 , further comprising a second electrical circuit for harvesting un-converted AC signals in series with the electrical circuit for harvesting un-converted AC signals.
An electrical circuit according to claim 13 , wherein the second AC-to-DC converter circuit or circuit element converts fundamental and harmonic signals to DC.
An electrical circuit according to claim 13 , wherein the impedance matching circuit or circuit element is configured to produce maximum DC output.
An electrical circuit for harvesting un-converted AC signals at the output of a first AC-to-DC converter circuit, comprising: a DC blocking electrical circuit or circuit element in electrical communication with the output of the first AC-to-DC converter circuit, the DC blocking electrical circuit or circuit element having an input and output; an impedance matching circuit or circuit element having an input and output, wherein the input of the impedance matching circuit or circuit element is in electrical communication with the output of the DC blocking electrical circuit or circuit element; a second AC-to-DC converter circuit or circuit element having an input and output, wherein the input of the second AC-to-DC converter circuit or circuit element is in electrical communication with the output of the impedance matching electrical circuit or circuit element; and wherein the output of the second AC-to-DC converter circuit or circuit element feeds into an input of the first AC-to-DC converter circuit to form a feedback loop.
wherein the output of the second AC-to-DC converter circuit or circuit element feeds into an input of the first AC-to-DC converter circuit to form a feedback loop.
An electrical circuit according to claim 20 , further comprising: an AC blocking circuit or circuit element having an input and output, wherein the input of the AC blocking circuit or circuit element is in electrical communication with the output of the first AC-to-DC converter circuit for allowing direction of the un-converted AC signals to the DC blocking electrical circuit or circuit element.
An electrical circuit according to claim 20 , wherein the first and second AC-to-DC converter circuits are rectifier circuits and wherein the un-converted AC signals are un-rectified AC signals.
An electrical circuit according to claim 20 , wherein the second AC-to-DC converter circuit or circuit element converts fundamental and harmonic signals to DC.
Ref US20100102512A1: Claims:
A shooting sequence controller comprising: a sequence controller comprising a control signal output, a signal input, the control signal output configured to send a target launch command; a microphone generating a signal in response to receiving an acoustic signal; a signal conditioning means, the signal conditioning means connected to the microphone; an analyzer connected to the signal conditioning means, the analyzer adapted to detect a gunshot, the analyzer adapted to detect a voice command, the analyzer configured to ignore ambient noise; and a first target launcher connected to the control signal output, whereby the sequence controller receives a voice command signal transmitted by the analyzer and sends the target launch command to the first target launcher to launch a first target.
a sequence controller comprising a control signal output, a signal input, the control signal output configured to send a target launch command;
a microphone generating a signal in response to receiving an acoustic signal;
a signal conditioning means, the signal conditioning means connected to the microphone;
an analyzer connected to the signal conditioning means, the analyzer adapted to detect a gunshot, the analyzer adapted to detect a voice command, the analyzer configured to ignore ambient noise; and
a first target launcher connected to the control signal output, whereby the sequence controller receives a voice command signal transmitted by the analyzer and sends the target launch command to the first target launcher to launch a first target.
The invention of claim 1 further comprising a shot counter in the sequence controller, the shot counter counting a number of gunshots detected by the analyzer.
The invention of claim 2 , further comprising a target timeout timer in the sequence controller, the target timeout timer initiated by the activation of the target launcher, the target timeout timer in a target timing state for a target timeout period, the shot counter counting gunshots detected by the analyzer, only when the target timeout timer is in the target timing state.
The invention of claim 1 wherein the analyzer further comprises circuitry to analyze the spectral energy distribution of incoming audio signals.
The invention of claim 1 , further comprising a plurality of microphones connected to the analyzer.
The invention of claim 3 , further comprising a shooting sequence of a plurality of shooting segments in the sequence controller, an index in the sequence controller to identify a current one of the plurality of shooting segments, the current one of the plurality of shooting segments initiated by the voice command, a means for terminating the current one of the plurality of shooting segments.
The invention of claim 6 , wherein the sequence controller further comprises a means for repeating the current one of the plurality of shooting segments if the gunshot is not detected during the target timing state.
The invention of claim 6 , further comprising a second target launcher connected to the control signal output, the current one of the plurality of shooting segments comprising a launch command selection chosen from the group consisting of: send a launch command to the first target launcher; send a launch command to the second target launcher; or send a launch output command to both target launchers.
The invention of claim 1 , further comprising a means for terminating the shooting sequence segment and a means for repeating the shooting sequence segment.
The invention of claim 1 , f
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