Office Action 2: Final Rejection (2024-10-22)
Rejection types: 103 - Obviousness

CLAIMS:
Listing of Claims:

This listing of claims will replace all prior versions, and listings, of claims in the application.

1\. (Currently Amended) A power stage comprising a control device and a power transistor connected to the control device in order to be driven by the control device, the control device comprising:a primary circuit and a secondary circuit, the primary circuit comprising:
a control module able to generate a control current it,
a primary circuit malfunction detector able to detect a malfunction of the primary circuit, wherein the primary circuit malfunction detector is configured to detect an overcurrent in the primary circuit,
a pulse transformer comprising a primary winding connected to the primary circuit, the pulse transformer comprising a secondary winding connected to the secondary circuit, magnetically coupled to the primary winding and able to generate, from the control current it, an induced pulse current im in the direction of the secondary circuit, the induced pulse current im making it possible to drive the power transistor, the secondary circuit comprising:
a power and fault detection controller, connected to the secondary winding of the pulse transformer and to the power transistor, able to detect a malfunction of the secondary circuit and/or of the power transistor,
the power and fault detection controller being able to communicate the malfunction of the secondary circuit and/or of the power transistor to the primary circuit malfunction detector.
2\. (Original) The power stage according to claim 1, wherein the power and fault detection controller communicates the malfunction of the secondary circuit and/or of the power transistor to the primary circuit malfunction detector only by way of the pulse transformer.

3\. (Original) The power stage according to claim 1, wherein the control module comprises an oscillator able to generate a predefined pulsed wave (Pulse) on the basis of a control signal (Sc) originating from outside the power stage and a full bridge, connected to the oscillator, able

to generate the control current it on the basis of the predefined pulsed wave (Pulse) in the direction of the primary winding of the pulse transformer.
4\. (Original) The power stage according to claim 3, wherein the full bridge is configured to synchronously generate the control current it on the basis of the external control signal (Sc) and/or the predefined pulsed wave (Pulse).
5\. (Original) The power stage according to claim 1, the secondary winding comprising two electrical terminals, the power and fault detection controller comprising an impedance R connected to the two electrical terminals of the secondary winding of the pulse transformer, the impedance R comprising an electrical resistance of less than 1000 ohms.
6\. Canceled.
7\. (Currently Amended) The power stage according to claim \[\[6\]\] 1, wherein the primary circuit malfunction detector is able to detect an opening fault in the primary circuit and/or a short-circuit fault in the primary circuit.
8\. (Original) The power stage according to claim 1, wherein the power and fault detection controller comprises a pulse detector able to detect a pulse fault in the induced pulse current im.
9\. (Original) The power stage according to claim 8, wherein the pulse detector is configured to rectify the induced pulse current im.

10\. (Original) The power stage according to claim 1, wherein the power and fault detection controller comprises a power transistor operation detector, able to detect at least one parameter of the power transistor causing non-nominal operation of the power transistor.

11\. (Original) The power stage according to claim 1, wherein the power and fault detection controller comprises a stop element able to short-circuit the pulse transformer on the basis of a fault detection.

12\. (Original) The power stage according to claim 1, comprising a power transistor driver able to generate a command for the power transistor based on the induced pulse current im.

13\. (Original) The power stage according to claim 1, wherein the primary circuit malfunction detector comprises a recorder able to record the malfunction of the primary circuit and/or the malfunction of the secondary circuit and/or of the power transistor.

14\. (Currently Amended) The power stage according to claim 12,wherein the power transistor driver comprises a command deactivator, configured to cancel the command for the power transistor when a primary circuit malfunction and/or secondary circuit malfunction and/or power transistor malfunction is detected.

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-5 and 7-14 are pending in this application.
Response to Amendment
Claims 1, 7, and 14 are amended. Claim 6 is canceled.
Response to Arguments
Applicant's arguments filed 10/08/2024 have been fully considered but they are not persuasive. Applicant argues that Rinehart et al. U.S. Patent No. 5,900,683 (hereinafter “Rinehart”) and Hara U.S. Patent Application 2020/0169179 (hereinafter “Hara”) do not teach “wherein the primary circuit malfunction detector is configured to detect an overcurrent in the primary circuit.” Specifically, the Applicant argues that Hara teaches detecting a current sensing abnormality, however this is not an overcurrent. However, Hara teaches the primary-side abnormality detection portion 15 detecting a current sensing abnormality and incomplete turn-off abnormality (refer to [0126]). The incomplete turn-off abnormality of Hara is described in [0129] and [0130]. Hara states that the “incomplete turn-off abnormality refers to a state in which the value of the current detection signal… is higher than a predetermined threshold although the switch transistor M1 is controlled to be turned off”. The current detection signal being higher than a threshold is an overcurrent. Therefore, Hara teaches wherein the primary circuit malfunction detector is configured to detect an overcurrent in the primary circuit (refer to [01216], [0129], and [0130]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA  35 U.S.C. 102 and 103 (or as subject to pre-AIA  35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA  to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 6, 7, 10, 12, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rinehart et al. U.S. Patent No. 5,900,683 (hereinafter “Rinehart”), and further in view of Hara U.S. Patent Application 2020/0169179 (hereinafter “Hara”).
Regarding claim 1, Rinehart teaches a power stage (refer to fig.1) comprising a control device (i.e. device 10)(fig.1) and a power transistor (i.e. transistor 14)(fig.1) connected to the control device (implicit) in order to be driven by the control device (refer to col. 2 lines 51-65), the control device comprising: a primary circuit (i.e. primary circuit 16)(fig.1) and a secondary circuit (i.e. secondary circuit 20)(fig.1), the primary circuit comprising: a control module (i.e. PWM Interface 26 and transformer driver/receiver 42)(fig.2) able to generate a control current it (refer to col. 4 lines 28-52), a primary circuit malfunction detector (i.e. fault decoder 44)(fig.2), a pulse transformer (i.e. high frequency pulse transformers 18)(fig.1) comprising a primary winding (i.e. primary side 22)(fig.1) connected to the primary circuit (implicit), the pulse transformer comprising a secondary winding (i.e. secondary side 24)(fig.1) connected to the secondary circuit (implicit), magnetically coupled to the primary winding (implicit) and able to generate, from the control current it, an induced pulse current im in the direction of the secondary circuit, the induced pulse current im making it possible to drive the power transistor (refer to col 5 lines 22-35), the secondary circuit comprising: a power and fault detection controller (refer to undervoltage detector 60, desaturation detector 66, overcurrent detectors 68, over-temperature detector 70, fault encoder 72, and transmitter 74)(fig.5), connected to the secondary winding of the pulse transformer and to the power transistor (implicit)(refer to fig.5), able to detect a malfunction of the secondary circuit and/or of the power transistor (implicit), the power and fault detection controller being able to communicate the malfunction of the secondary circuit and/or of the power transistor to the primary circuit malfunction detector (refer to fault encoder 72 and transmitter 74)(fig.5)(refer also to col. 6 line 66 to col. 7 line 36), however Rinehart does not teach the primary circuit malfunction detector able to detect a malfunction of the primary circuit, wherein the primary circuit malfunction detector is configured to detect an overcurrent in the primary circuit. However, Hara teaches the primary circuit malfunction detector able to detect a malfunction of the primary circuit (refer to primary-side abnormality detection portion 15)(fig.13)(refer also to [0125] and [0144]), wherein the primary circuit malfunction detector is configured to detect an overcurrent in the primary circuit (refer to [0126], [0129], and [0130]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the primary circuit malfunction detector of Rinehart to include the detection of malfunctions of the primary circuit of Hara to provide the advantage of protecting the primary circuit from malfunctions, thereby better protecting the entire circuit from damage due to malfunctions.
Regarding claim 2, Rinehart and Hara teach the power stage according to claim 1, wherein the power and fault detection controller communicates the malfunction of the secondary circuit and/or of the power transistor to the primary circuit malfunction detector only by way of the pulse transformer (refer to Rinehart col. 5 lines 35-49).
Regarding claim 7, Rinehart and Hara teach the power stage according to claim 6, wherein the short-circuit detector is able to detect an opening fault in the primary circuit and/or a short-circuit fault in the primary circuit (refer to Hara [0126], [0129], and [0130]).
Regarding claim 10, Rinehart and Hara teach the power stage according to claim 1, wherein the power and fault detection controller comprises a power transistor operation detector (refer to Rinehart overcurrent detectors 68 and over-temperature detector 70)(fig.5), able to detect at least one parameter of the power transistor causing non-nominal operation of the power transistor (refer to Rinehart overcurrent detectors 68 and over-temperature detector 70)(fig.5).
Regarding claim 12, Rinehart and Hara teach the power stage according to claim 1, comprising a power transistor driver (i.e. Rinehart amplifier 64)(fig.5) able to generate a command for the power transistor based on the induced pulse current im (implicit).
Regarding claim 14, Rinehart and Hara teach the power stage according to claim 1, wherein the power transistor driver comprises a command deactivator (refer to Rinehart claims 13 and 14), configured to cancel the command for the power transistor when a primary circuit malfunction and/or secondary circuit malfunction and/or power transistor malfunction is detected (refer to Rinehart claims 13 and 14).
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rinehart and Hara as applied to claim 1 above, and further in view of Ongaro U.S. Patent Application 2005/0062433 (hereinafter “Ongaro”).
Regarding claim 3, Rinehart and Hara teach the power stage according to claim 1, however they do not teach wherein the control module comprises an oscillator able to generate a predefined pulsed wave (Pulse) on the basis of a control signal (Sc) originating from outside the power stage and a full bridge, connected to the oscillator, able to generate the control current it on the basis of the predefined pulsed wave (Pulse) in the direction of the primary winding of the pulse transformer. However, Ongaro teaches wherein the control module comprises an oscillator (refer to [0044]) able to generate a predefined pulsed wave (Pulse) (implicit) on the basis of a control signal (Sc) originating from outside the power stage (refer to [0044]) and a full bridge (refer to [0044]), connected to the oscillator (refer to [0044]), able to generate the control current it on the basis of the predefined pulsed wave (Pulse) in the direction of the primary winding of the pulse transformer (refer to [0044]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power stage of Rinehart and Hara to include the oscillator and full bridge of Ongaro to provide the advantage of properly driving the primary winding.
Regarding claim 4, Rinehart, Hara, and Ongaro teach the power stage according to claim 3, wherein the full bridge is configured to synchronously generate the control current it on the basis of the external control signal (Sc) and/or the predefined pulsed wave (Pulse) (implicit).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rinehart and Hara.
Regarding claim 5, Rinehart and Hara teach the power stage according to claim 1, the secondary winding comprising two electrical terminals (implicit)(refer to Hara TM-2A and TM-2B)(fig.1), the power and fault detection controller comprising an impedance R (i.e. Hara capacitor C2)(fig.1) connected to the two electrical terminals of the secondary winding of the pulse transformer (implicit), however they do not teach the impedance R comprising an electrical resistance of less than 1000 ohms. However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have the impedance R comprising an electrical resistance of less than 1000 ohms, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art.  In re Aller, 105 USPQ 233. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power stage of Rinehart and Hara to include the impedance R comprising an electrical resistance of less than 1000 ohms to provide the advantage of preventing undue influence on the circuit while smoothing out noise.
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rinehart and Hara as applied to claim 1 above, and further in view of Tang et al. U.S. Patent Application 2020/0083813 (hereinafter “Tang”).
Regarding claim 8, Rinehart and Hara teach the power stage according to claim 1, however, they do not teach wherein the power and fault detection controller comprises a pulse detector able to detect a pulse fault in the induced pulse current im. However, Tang teaches wherein the power and fault detection controller comprises a pulse detector able to detect a pulse fault in the induced pulse current im (refer to [0054] and figure 4). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power stage of Rinehart and Tang to include the pulse detector of Tang to provide the advantage of using a common means to detect missing pulses.
Regarding claim 9, Rinehart, Hara, and Tang teach the power stage according to claim 8, wherein the pulse detector is configured to rectify the induced pulse current im (refer to Tang [0054] and figure 4).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rinehart and Hara as applied to claim 1 above, and further in view of Deng et al. Chinese Patent Document CN 101323310 B (hereinafter “Deng”).
Regarding claim 11, Rinehart and Hara teach the power stage according to claim 1, however they do not teach wherein the power and fault detection controller comprises a stop element able to short-circuit the pulse transformer on the basis of a fault detection. However, Deng teaches wherein the power and fault detection controller comprises a stop element able to short-circuit the pulse transformer on the basis of a fault detection (refer to [0064]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power stage of Rinehart and Hara to include the stop element of Deng to provide the advantage of quickly and reliably turning of the power transistor.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rinehart and Hara as applied to claim 1 above, and further in view of Cao et al. Chinese Patent Document CN 105262056 A (hereinafter “Cao”).
Regarding claim 13, Rinehart and Hara teach the power stage according to claim 1, however they do not teach wherein the primary circuit malfunction detector comprises a recorder able to record the malfunction of the primary circuit and/or the malfunction of the secondary circuit and/or of the power transistor. However, Cao teaches wherein the primary circuit malfunction detector comprises a recorder able to record the malfunction of the primary circuit and/or the malfunction of the secondary circuit and/or of the power transistor (refer to page 7). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power stage of Rinehart and Hara to include the recorder of Cao to provide the advantage of preventing operation of the power stage until the fault is cleared.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action.  Accordingly, THIS ACTION IS MADE FINAL.  See MPEP § 706.07(a).  Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action.  In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action.  In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.

APPLICANT REBUTTAL: REMARKS
Claims 1-5 and 7-14 are pending, with claim 1 being independent. Claim 6 has been cancelled.
Claims 1-5 and 7-14 stand rejected. Claims 1 and 4 are amended. Claim 3 is canceled. No new subject matter has been added.
Claim Rejections - 35 U.S.C. § 103
Claims 1, 2, 6, 7, 10, 12 and 14 stand rejected under 35 U.S.C. § 103 as being
unpatentable over U.S. Patent No. 5,900,683 (hereinafter "Rinehart") in view of U.S. Publication No. 2020/0169179 (hereinafter "Hara"). Office Action, at 3. In order for a combination of references to render a claim obvious under Section 103, the references together must teach or suggest each and every feature of the claims. Here, the cited combination of references does not teach or suggest all of the features of the claims.
Claim 1 has been amended to incorporate the features of dependent claim 3. Amended
claim 1 recites, in part, "a control module able to generate a control current it, wherein the control module comprises an oscillator able to generate a predefined pulsed wave based on a control signal originating from outside the power stage and a full bridge, connected to the oscillator, able to generate the control current it on the basis of the predefined pulsed wave in a direction of the primary winding of the pulse transformer." The cited combination of references does not teach or suggest these features of amended claim 1.
With respect to now-canceled dependent claim 3, the Office asserts that paragraph [0044] of U.S. Publication No. 2005/0062433 (hereinafter "Ongaro") discloses "wherein the control module comprises an oscillator able to generate a predefined pulsed wave (Pulse) on the basis of a control signal (Sc) originating from outside the power stage and a full bridge, connected to the oscillator, able to generate the control current it on the basis of the predefined pulsed wave (Pulse) in the direction of the primary winding of the pulse transformer." Office Action, at 6. But paragraph [0044] of Ongaro does not disclose "a control module able to generate a control current it, wherein the control module comprises an oscillator able to generate a predefined pulsed wave based on a control signal originating from outside the power stage and a full
bridge, connected to the oscillator, able to generate the control current it on the basis of the predefined pulsed wave in a direction of the primary winding of the pulse transformer," as claimed.
Ongaro describes an H-bridge-not a "full bridge," as claimed. An H-bridge is a full
bridge used in reverse. A full bridge is used as a rectifier and an H-bridge is used as an inverter (or oscillator). An H-bridge cannot be connected to an oscillator because the H-bridge already has the oscillator function. While paragraph [0044] of Ongaro does use both the term "H- bridge" and the term "oscillator," Ongaro does not disclose that the "H-bridge" and the "oscillator" can be used in combination with each other. Instead, paragraph [0044] of Ongaro explains that it is possible to use an oscillator as an H-bridge. In other words, Ongaro describes two alternatives: an H-bridge or an oscillator-but not both an H-bridge and an oscillator that are connected to each other. In fact, it would be strange to provide both an H-bridge AND an oscillator, as these two elements fulfill the same function-namely transforming a direct voltage (see VDC in Ongaro's Figure 1) into an alternative voltage available at the input of the two inductors LS.
Paragraph [0044] of Ongaro refers to an integrated circuit, UC3525. The Texas
Instrument documentation found in the datasheet accessible at
https://www.ti.com/product
/
UC3525A
provides information on the UC3525 integrated circuit. An oscillator (OSC) is shown in the block diagram on page 1 of the Texas Instrument documentation, and a complete diagram showing additional detail is shown on page 7. Paragraph [0044] explains that the UC3525 integrated circuit can be implemented to make an H bridge. Paragraph [0044] further describes that the UC3525 integrated circuit ensures the dead time function for an oscillator and more precisely: fulfilling the function of dead times insertion in a full bridge or in an H-bridge.
Ongaro's Figure 1 (reproduced below) represents an H bridge with its four transistors S 1 to S4:
lternative voltage
Paragraph [0044] of Ongaro describes that the circuits for inserting dead times are necessary for the control of transistors Si to S4. Technically, it is essential that the transistors Sl and S2 and the transistors S3 and S4 are not closed together in order to avoid any risk of short circuit of the VDC power supply. It is essential to provide a "dead time" between the time when Si is closed and the time when S2 is closed, and a "dead time" between the time when S3 is closed and the time when S4 is closed.
Because Ongaro does not disclose both an oscillator
and
a complete bridge, connected to the oscillator and receiving the signal generated by the oscillator, Ongaro does not disclose "a control module able to generate a control current it, wherein the control module comprises an oscillator able to generate a predefined pulsed wave based on a control signal originating from outside the power stage and a full bridge, connected to the oscillator, able to generate the control current it on the basis of the predefined pulsed wave in a direction of the primary winding of the pulse transformer," as claimed.
As such, amended independent claim 1 is patentable over the cited combination of
references. Because dependent claims 2, 7, 10, 12, and 14 depend, either directly or indirectly from amended independent claim 1, they too are patentable for the same reasons. Applicant therefore respectfully requests reconsideration and withdrawal of the § 103 rejection of claims 1, 2, 7, 10, 12 and 14.
Claims 3 and 4 stand rejected under 35 U.S.C. § 103 as being unpatentable over Rinehart in view of Hara and further in view of U.S. Publication No. 2005/0062433 (hereinafter "Ongaro"). Office Action, at 5. As described above, amended claim 1, which incorporates the
features of now-canceled claim 3, is patentable over the combination of Rinehart, Hara, and Ongaro. Because dependent claim 4 depends, either directly or indirectly from amended independent claim 1, it too is patentable for the same reasons. Applicant therefore respectfully requests reconsideration and withdrawal of the § 103 rejection of claim 4.
Claim 5 stands rejected under 35 U.S.C. § 103 as being unpatentable over Rinehart in view of Hara. Office Action, at 6. As described above, amended claim 1 is patentable over the combination of Rinehart, Hara, and Ongaro. Because dependent claim 5 depends, either directly or indirectly from amended independent claim 1, it too is patentable for the same reasons. Applicant therefore respectfully requests reconsideration and withdrawal of the § 103 rejection of claim 5.
Claims 8 and 9 stand rejected under 35 U.S.C. § 103 as being unpatentable over Rinehart in view of Hara and further in view of U.S. Publication No. 2020/0083813 (hereinafter "Tang"). Office Action, at 7. Tang does not cure the failure of Rinehart, Hara, and Ongaro to disclose or make obvious the subject matter of amended independent claim 1 from which claims 8 and 9 depend. Accordingly, for at least the reasons described above in connection with independent claim 1, Applicant respectfully requests reconsideration and withdrawal of the rejection of claims 8 and 9.
Claim 11 stands rejected under 35 U.S.C. § 103 as being unpatentable over Rinehart in view of Hara and further in view of CN Patent No. 101323310 B (hereinafter "Deng"). Office Action, at 7. Deng does not cure the failure of Rinehart, Hara, and Ongaro to disclose or make obvious the subject matter of amended independent claim 1 from which claim 11 depends. Accordingly, for at least the reasons described above in connection with independent claim 1, Applicant respectfully requests reconsideration and withdrawal of the rejection of claim 11.
Claim 13 stands rejected under 35 U.S.C. § 103 as being unpatentable over Rinehart in view of Hara and further in view of CN Publication No. 105262056 A (hereinafter "Cao"). Office Action, at 8. Cao does not cure the failure of Rinehart, Hara, and Ongaro to disclose or make obvious the subject matter of amended independent claim 1 from which claim 13 depends.
Accordingly, for at least the reasons described above in connection with independent claim 1, Applicant respectfully requests reconsideration and withdrawal of the rejection of claim 13.
CONCLUSION

NEXT OFFICE ACTION: DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 2, 4, 5, and 7-14 are pending in this application.
Response to Amendment
Claims 1 and 4 are amended. Claim 3 is canceled.
Response to Arguments
Applicant’s arguments, see Applicant Arguments/Remarks Made in an Amendment, filed 02/24/2025, with respect to claims 1, 2, 4, 5, and 7-14 have been fully considered and are persuasive.  The rejection of claims 1, 2, 4, 5, and 7-14 has been withdrawn.
Allowable Subject Matter
Claims 1, 2, 4, 5, and 7-14 are allowed.
The following is an examiner’s statement of reasons for allowance: Claims 1, 2, 4, 5, and 7-14 are allowable because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 1, especially wherein the control module comprises an oscillator able to generate a predefined pulsed wave based on a control signal originating from outside the power stage and a full bridge, connected to the oscillator, able to generate the control current it on the basis of the predefined pulsed wave in a direction of the primary winding of the pulse transformer. Claims 2, 4, 5, and 7-14 are allowed based on their dependency on claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee.  Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion

CITED REFERENCE SUMMARIES: Ref US20050062433A1: Claims:
A power supply system for liquid crystal monitors, characterized in that it includes at least a first DC/AC converter (FBS, HBS) operating at predetermined frequency and duty-cycles and being fed by at least a second DC/DC converter (FC, SC) which regulates the circuit voltage to feed a plurality of fluorescent lamps (L, L 1 , LN) in the monitor through a wiring harness which transmits at least an output sinusoidal signal (SG 1 , SG 2 , SG 3 ) from said first DC/AC converter (FBS, HBS) to the primary windings of a plurality of parallel connected piezoelectric transformers (PT, PT 1 , PT 2 , PTN, PT 2 N) which are connected with the fluorescent lamps (L, L 1 , LN).
A power supply system as claimed in claim 1 , characterized in that each fluorescent lamp (L, L 1 , LN) of the monitor is connected at least with a piezoelectric transformer (PT 1 , PT 2 ; PTN, PT 2 N; PT), wherein the primary windings of said transformers (PT 1 , PT 2 ; PTN, PT 2 N; PT) are series or parallel connected one with another and are connected with series-connected inductors (LS).
A power supply system as claimed in claim 1 , characterized in that said first converter (FBS) includes at least a piloting stage which is based on the control of pairs of MOSFET transistors (S 1 , S 2 , S 3 , S 4 ), on the diagonals of a dually fed H-bridge, through direct current generators (VDC).
A power supply system as claimed in claim 1 , characterized in that said first converter (FBS) employs two half-bridge inverters (HBI), the phases of which are rotated through 1800 with respect to each other.
A power supply system as claimed in claim 1 , characterized in that it includes a feedback circuit (F) having a controller (IC) for controlling the brightness emitted by the fluorescent lamps (L, L 1 , LN), said brightness control being performed by feedbacking a signal which is directly proportional to the brightness of said lamps (L, L 1 , LN), said signal being provided by at least a sensor (PR) associated with each lamp (L, L 1 , LN), the signals provided by said sensors (PR) being combined together by means of a controller (M).
A power supply system as claimed in claim 2 , characterized in that each fluorescent lamp (L 1 , LN) is piloted differentially by a pair of piezoelectric transformers (PT 1 , PT 2 ), said pairs of transformers (PT 1 , PT 2 ) being parallel connected with each other.
A power supply system as claimed in claim 6 , characterized in that said second DC/DC converter (FC) controlling a continuous input voltage (VIN) consists of a flyback converter which is voltage controlled at a predetermined sampling frequency.
A power supply system as claimed in claim 2 , characterized in that each fluorescent lamp (L) is connected with a single balanced transformer (PT) and said first converter (HBS) is a half-bridge converter.
A power supply system as claimed in claim 8 , characterized in that said second DC/DC converter (SC) is a SEPIC converter which operates within the whole range of input voltages (VIN).
Ref US20200169179A1: Claims:
An insulation-type DC/DC converter, configured to mutually insulate a secondary-side circuit disposed on a secondary side and a primary-side circuit disposed on a primary side of a power transformer and to perform switch-driving of a switch transistor connected to a primary-side winding of the power transformer, such that the secondary-side circuit obtains a secondary-side voltage from a primary-side voltage in the primary-side circuit; the insulation-type DC/DC converter comprising: a primary-side control portion, disposed at the primary side, controlling the switch transistor; a secondary-side control portion, disposed at the secondary side; and a communication transformer, implementing bi-directional communication between the primary-side control portion and the secondary-side control portion.
a primary-side control portion, disposed at the primary side, controlling the switch transistor;
a secondary-side control portion, disposed at the secondary side; and
a communication transformer, implementing bi-directional communication between the primary-side control portion and the secondary-side control portion.
The insulation-type DC/DC converter according to claim 1 , wherein the insulation-type DC/DC converter is an insulation synchronous rectification-type DC/DC converter; and the insulation-type DC/DC converter, controls a synchronous rectification transistor by the secondary-side control portion, wherein the synchronous rectification transistor is disposed at the secondary side so as to implement synchronous rectification, and transceives signals associated with turn-on and turn-off of the switch transistor between the primary-side control portion and the secondary-side control portion through the communication transformer.
the insulation-type DC/DC converter, controls a synchronous rectification transistor by the secondary-side control portion, wherein the synchronous rectification transistor is disposed at the secondary side so as to implement synchronous rectification, and transceives signals associated with turn-on and turn-off of the switch transistor between the primary-side control portion and the secondary-side control portion through the communication transformer.
The insulation-type DC/DC converter according to claim 2 , wherein: the primary-side control portion sends a predetermined first signal to the secondary-side control portion through the communication transformer when the switch transistor is turned on, and sends a predetermined second signal to the secondary-side control portion through the communication transformer when the switch transistor is turned off; and the secondary-side control portion controls turn-on/turn-off of the synchronous rectification transistor according to the predetermined first signal and the predetermined second signal received.
the primary-side control portion sends a predetermined first signal to the secondary-side control portion through the communication transformer when the switch transistor is turned on, and sends a predetermined second signal to the secondary-side control portion through the communication transformer when the switch transistor is turned off; and
the secondary-side control portion controls turn-on/turn-off of the synchronous rectification transistor according to the predetermined first signal and the predetermined second signal received.
The insulation-type DC/DC converter according to claim 3 , wherein: the secondary-side control portion is configured to send a predetermined first response signal to the primary-side control portion through the communication transformer in response to the predetermined first signal received, and to send a predetermined second response signal to the primary-side control portion through the communication transformer in response to the predetermined second signal received; and the primary-side control portion performs, upon not receiving the predetermined first response signal after having sent the predetermined first signal, or upon not receiving the predetermined second response signal after having sent the predetermined second signal, a predetermined communication error process, which includes a process of prohibiting setting the switch transistor to a turned-on state.
the secondary-side control portion is configured to send a predetermined first response signal to the primary-side control portion through the communication transformer in response to the predetermined first signal received, and to send a predetermined second response signal to the primary-side control portion through the communication transformer in response to the predetermined second signal received; and
the primary-side control portion performs, upon not receiving the predetermined first response signal after having sent the predetermined first signal, or upon not receiving the predetermined second response signal after having sent the predetermined second signal, a predetermined communication error process, which includes a process of prohibiting setting the switch transistor to a turned-on state.
The insulation-type DC/DC converter according to claim 2 , wherein: the secondary-side control portion is capable of sending a predetermined first signal and a predetermined second signal to the primary-side control portion through the communication transformer, wherein the first predetermined signal provides an instruction for turning on the switch transistor and the predetermined second signal provides an instruction for turning off the switch transistor; and the primary-side control portion turns on the switch transistor in response to the predetermined first signal received, and turns off the switch transistor in response to the predetermined second signal received.
the secondary-side control portion is capable of sending a predetermined first signal and a predetermined second signal to the primary-side control portion through the communication transformer, wherein the first predetermined signal provides an instruction for turning on the switch transistor and the predetermined second signal provides an instruction for turning off the switch transistor; and
the primary-side control portion turns on the switch transistor in response to the predetermined first signal received, and turns off the switch transistor in response to the predetermined second signal received.
The insulation-type DC/DC converter according to claim 5 , wherein: the primary-side control portion is configured to send a predetermined first response signal to the secondary-side control portion through the communication transformer in response to the predetermined first signal received, and to send a predetermined second response signal to the secondary-side control portion through the communication transformer in response to the predetermined second signal received; and the secondary-side control portion performs, upon not receiving the predetermined first response signal after having sent the predetermined first signal, or upon not receiving the predetermined second response signal after having sent the predetermined second signal, a predetermined communication error process, which includes a process of prohibiting setting the synchronous rectification transistor to a turned-on state.
the primary-side control portion is configured to send a predetermined first response signal to the secondary-side control portion through the communication transformer in response to the predetermined first signal received, and to send a predetermined second response signal to the secondary-side control portion through the communication transformer in response to the predetermined second signal received; and
the secondary-side control portion performs, upon not receiving the predetermined first response signal after having sent the predetermined first signal, or upon not receiving the predetermined second response signal after having sent the predetermined second signal, a predetermined communication error process, which includes a process of prohibiting setting the synchronous rectification transistor to a turned-on state.
The insulation-type DC/DC converter according to claim 1 , wherein: upon starting to power the primary-side control portion and activation of the primary-side control portion, an initial action is performed regardless of a value of the primary-side voltage, to perform switch-driving of the switch transistor; when the secondary-side voltage becomes a predetermined voltage and the secondary-side control portion is activated after the initial action is undertaken, predetermined handshake communication is performed between the primary-side control portion and the secondary-side control portion through the communication transformer, and a normal action is performed after the handshake communication is correctly completed, and switch-driving of the switch transistor is performed according to the secondary-side voltage.
upon starting to power the primary-side control portion and activation of the primary-side control portion, an initial action is performed regardless of a value of the primary-side voltage, to perform switch-driving of the switch transistor;
when the secondary-side voltage becomes a predetermined voltage and the secondary-side control portion is activated after the initial action is undertaken, predetermined handshake communication is performed between the primary-side control portion and the secondary-side control portion through the communication transformer, and
a normal action is performed after the handshake communication is correctly completed, and switch-driving of the switch transistor is performed according to the secondary-side voltage.
The insulation-type DC/DC converter according to claim 1 , wherein: the primary-side control portion comprises a primary-side abnormality detection portion for detecting whether predetermined abnormality exists in the primary-side circuit; and if the abnormality is detected in the primary-side circuit, switch-driving of the switch transistor is stopped, and a predetermined primary-side abnormality detection signal is sent to the secondary-side control portion through the communication transformer.
the primary-side control portion comprises a primary-side abnormality detection portion for detecting whether predetermined abnormality exists in the primary-side circuit; and
if the abnormality is detected in the primary-side circuit, switch-driving of the switch transistor is stopped, and a predetermined primary-side abnormality detection signal is sent to the secondary-side control portion through the communication transformer.
The insulation-type DC/DC converter according to claim 1 , wherein: the secondary-side control portion comprises a secondary-side abnormality detection portion for detecting whether predetermined abnormality exists in the secondary-side circuit; if the abnormality is detected in the secondary-side circuit, a predetermined secondary-side abnormality detection signal is sent to the primary-side control portion through the communication transformer, the primary-side control portion stops switch-driving of the switch transistor upon receiving the secondary-side abnormality detection signal.
the secondary-side control portion comprises a secondary-side abnormality detection portion for detecting whether predetermined abnormality exists in the secondary-side circuit;
if the abnormality is detected in the secondary-side circuit, a predetermined secondary-side abnormality detection signal is sent to the primary-side control portion through the communication transformer,
the primary-side control portion stops switch-driving of the switch transistor upon receiving the secondary-side abnormality detection signal.
The insulation-type DC/DC converter according to claim 1 , wherein when one control portion of the primary-side control portion and the secondary-side control portion sends a predetermined signal to the other control portion through the communication transformer and the other control portion receives the predetermined signal, the other control portion sends a signal to the one control portion through the communication transformer in response to the predetermined signal received.
An AC/DC converter, comprising: a rectification circuit, performing full-wave rectification on an AC voltage; a smoothing capacitor, smoothing the voltage having undergone full-wave rectification to generate a DC voltage; and the insulation-type DC/DC converter of claim 1 , thereby generating a DC secondary-side voltage from a primary-side voltage of the DC voltage as an output voltage.
a rectification circuit, performing full-wave rectification on an AC voltage;
a smoothing capacitor, smoothing the voltage having undergone full-wave rectification to generate a DC voltage; and
the insulation-type DC/DC converter of claim 1 , thereby generating a DC secondary-side voltage from a primary-side voltage of the DC voltage as an output voltage.
A power adapter, comprising: a plug, receiving an AC voltage; the AC/DC converter of claim 11 ; and a housing, accommodating the AC/DC converter.
a plug, receiving an AC voltage;
the AC/DC converter of claim 11 ; and
a housing, accommodating the AC/DC converter.
An electronic device, comprising: the AC/DC converter of claim 1 ; and a load device, driven by an output voltage of the AC/DC converter.
the AC/DC converter of claim 1 ; and
a load device, driven by an output voltage of the AC/DC converter.
Ref US20200083813A1: Claims:
A switched-mode power converter using an isolated topology for converting power from an input source into power for an output load, the switched-mode power converter comprising: a primary side including a power stage coupled to the input source and comprising one or more power switches; a transformer comprising a primary winding coupled to the power stage, and a secondary winding; and a secondary side including: a rectifier circuit coupled to the secondary winding and configured to provide a first rectified voltage at a first rectified voltage node, a filter circuit interposed between the first rectified voltage node and an output of the switched-mode power converter, the filter circuit configured to filter the first rectified voltage, thereby providing a filtered voltage at the output, and a secondary-side controller configured to: sense the first rectified voltage; detect, based upon the first rectified voltage sensed on the secondary side, a fault condition of the primary side; and generate a fault indication and/or modify operation of the switched-mode power converter responsive to said detection.
a primary side including a power stage coupled to the input source and comprising one or more power switches;
a transformer comprising a primary winding coupled to the power stage, and a secondary winding; and
a secondary side including: a rectifier circuit coupled to the secondary winding and configured to provide a first rectified voltage at a first rectified voltage node, a filter circuit interposed between the first rectified voltage node and an output of the switched-mode power converter, the filter circuit configured to filter the first rectified voltage, thereby providing a filtered voltage at the output, and a secondary-side controller configured to: sense the first rectified voltage; detect, based upon the first rectified voltage sensed on the secondary side, a fault condition of the primary side; and generate a fault indication and/or modify operation of the switched-mode power converter responsive to said detection.
a rectifier circuit coupled to the secondary winding and configured to provide a first rectified voltage at a first rectified voltage node,
a filter circuit interposed between the first rectified voltage node and an output of the switched-mode power converter, the filter circuit configured to filter the first rectified voltage, thereby providing a filtered voltage at the output, and
a secondary-side controller configured to: sense the first rectified voltage; detect, based upon the first rectified voltage sensed on the secondary side, a fault condition of the primary side; and generate a fault indication and/or modify operation of the switched-mode power converter responsive to said detection.
sense the first rectified voltage;
detect, based upon the first rectified voltage sensed on the secondary side, a fault condition of the primary side; and
generate a fault indication and/or modify operation of the switched-mode power converter responsive to said detection.
The switched-mode power converter of claim 1 , wherein the secondary-side controller is configured to estimate an input voltage of the input source based upon the sensed first rectified voltage.
The switched-mode power converter of claim 2 , wherein the fault condition is an undervoltage fault condition and wherein estimating the input voltage comprises: detecting a rectified volta
[Truncated to input limit]