Office Action 3: Non-Final Rejection (2024-06-05)
Rejection types: 102 - Lack of Novelty, 103 - Obviousness, 112 - Written Description/Enablement

CLAIMS:
Response to Office Action of February 7, 2024 AMENDMENTS TO THE CLAIMSPlease AMEND claims 1, 7, and 13 as shown below.

The following list of claims replaces any prior listing of claims:

1\. (Currently Amended) A chip package structure, comprising:
a glass substrate, wherein a first surface of the glass substrate has solder joints and a second surface of the glass substrate has substrate solder balls;
a routing layer, wherein the routing layer is located in the glass substrate and the solder joints are electrically connected to the substrate solder balls by using the routing layer; and
a plurality of dies, wherein each die has chip solder balls, is located on the first surface of the glass substrate, and the solder joints are bonded to the chip solder balls, wherein composition proportions of the glass substrate ensure that a coefficient of thermal expansion of each die of the plurality of dies substantially matches a coefficient of thermal expansion of the glass substrate.

2\. (Previously Presented) The chip package structure according to claim 1, wherein the glass substrate comprises a plurality of glass layers, there is at least one routing layer, and each routing layer is located between two adjacent glass layers.

3\. (Previously Presented) The chip package structure according to claim 1, wherein the first surface of the glass substrate has a groove, some dies of the plurality of dies are located in the groove, and other dies of the plurality of dies are located outside the groove.

4\. (Previously Presented) The chip package structure according to claim 3, wherein the groove comprises a groove bottom and n steps, the n steps are located on two sides of the groove bottom, n is a positive integer, some dies of the plurality of dies in the groove are located on the groove bottom, and the other dies of the plurality of dies are located on an upper surface of an fi step in the n steps, wherein i is set to a value from 1 to n.

5\. (Previously Presented) The chip package structure according to claim 4, wherein each step comprises a first sub-step and a second sub-step, the first sub-step and the second sub-step are respectively located on the two sides of the groove bottom in opposite positions and one end of each die on the upper surface of the ithstep islocated on an upper surface of the first sub-step, and the other end of each die is located on an upper surface of the second sub-step.

6\. (Previously Presented) The chip package structure according to claim 3, wherein one end of each die outside the groove is located on a first side of the groove, the other end of each die is located on a second side of the groove, and the first side and the second side of the groove are in opposite positions.

7\. (Currently Amended) A chip package structure preparation method comprising:

Response to Office Action of February 7, 2024 distributing a routing layer in a glass substrate;
disposing solder joints on a first surface of the glass substrate;
disposing substrate solder balls on a second surface of the glass substrate, wherein the solder joints are electrically connected to the substrate solder balls by using the routing layer;
disposing chip solder balls on a surface of each die of at least one die, wherein composition proportions of the glass substrate ensure that a coefficient of thermal expansion of each die substantially matches a coefficient of thermal expansion of the glass substrate;
fastening the at least one die to the first surface of the glass substrate; and
bonding the solder joints to the chip solder balls.

8\. (Previously Presented) The method according to claim 7, wherein the glass substrate comprises m glass layers, m is a positive integer greater than 1, and distributing the routing layer in the glass substrate further comprises:
distributing a copper layer on a surface of a k\* glass layer;
performing circuit printing on the copper layer to form the routing layer on the surface of the k\* glass layer; and
fastening a (k+1)\* glass layer to a surface of the routing layer to obtain the glass substrate with the routing layer distributed between the two adjacent glass layers, wherein k is set to a value from 1 to m-1.

9\. (Previously Presented) The method according to claim 7, wherein the first surface of the glass substrate has a groove, there are a plurality of dies, and the fastening of the at least one die to the first surface of the glass substrate further comprises:
fastening some dies of the plurality of dies in the groove; and fastening other dies of the plurality of dies outside the groove.

10\. (Previously Presented) The method according to claim 9, wherein the groove comprises a groove bottom and n steps, the n steps are located on two sides of the groove bottom, n is a positive integer, and fastening some dies of the plurality of dies in the groove further comprises:
fastening some dies of the plurality of dies on the groove bottom; and
fastening the other dies of the plurality of dies to an upper surface of an ith step in the n steps, wherein i is set to a value from 1 to n.

11\. (Previously Presented) The method according to claim 10, wherein each step comprises a first sub-step and a second sub-step, the first sub-step and the second sub-step are respectively located on the two sides of the groove bottom in opposite positions, fastening the other dies of the plurality of dies to the upper surface of the ith step in the n steps further comprises:
fastening one end of each die to an upper surface of the first sub-step of the ith step in the n steps; and
fastening the other end of each die to an upper surface of the second sub-step of the ithstep.

12\. (Previously Presented) The method according to claim 9, wherein the fastening of the other dies of the plurality of dies outside the groove comprises:
fastening one end of the die to a first side of the groove; and
fastening the other end of the die to a second side of the groove, wherein the first side and the second side of the groove are in opposite positions.

13\. (Currently Amended) An electronic device comprising a chip package structure, and the chip package structure comprises:
a glass substrate, wherein a first surface of the glass substrate has solder joints and a second surface of the glass substrate has substrate solder balls;
a routing layer, wherein the routing layer is located in the glass substrate and the solder joints are electrically connected to the substrate solder balls by using the routing layer; and
a plurality of dies, wherein each die has chip solder balls, is located on the first surface of the glass substrate, and the solder joints are bonded to the chip solder balls, wherein composition proportions of the glass substrate ensure that a coefficient of thermal expansion of each die of the plurality of dies substantially matches a coefficient of thermal expansion of the glass substrate.

14\. (Previously Presented) The electronic device according to claim 13, wherein the glass substrate comprises a plurality of glass layers, there is at least one routing layer, and each routing layer is located between two adjacent glass layers.

15\. (Previously Presented) The electronic device according to claim 13, wherein the first surface of the glass substrate has a groove, some dies of the plurality of dies are located in the groove, and other dies of the plurality of dies are located outside the groove.

16\. (Previously Presented) The electronic device according to claim 15, wherein the groove comprises a groove bottom and n steps, the n steps are located on two sides of the groove bottom, n is a positive integer, and some dies of the plurality of dies in the groove are located on the groove bottom, and the other dies of the plurality of dies are located on an upper surface of an fi\* step in the n steps, wherein i is set to a value from 1 to n.

17\. (Previously Presented) The electronic device according to claim 16, wherein each step comprises a first sub-step and a second sub-step, and the first sub-step and the second sub-step are respectively located on the two sides of the groove bottom in opposite positions, one end of each die on the upper surface of the fi step is located on an upper surface of the first sub-step, and the other end of each die is located on an upper surface of the second sub-step.

18\. (Previously Presented) The electronic device according to claim 15, wherein the one end of each die outside the groove is located on a first side of the groove, the other end of each die is located on a second side of the groove, and the first side of the groove and the second side of the groove are in opposite positions.

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA  35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA  35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 1, 7, and 13 recite a new limitation, “substantially matches”. The new limitation renders new matter situation because the original specification does not describe the limitation directly or inherently that would be understood by one of ordinary skill in the art. The specification instead discloses that by adjusting composition proportions of the glass so that the thermal expansion of the glass substrate is close to that of the die. This description does not mean that the TEC of elements actually substantially match (see the current specification paras [0038, 0083, 0123], for example.)
The following is a quotation of 35 U.S.C. 112(b):
(b)  CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA  35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 7, and 13 recite a new limitation, “substantially matches”, in lines 9, 8, and 10, respectively. The new limitation renders indefinite situation because the original specification does not describe the limitation directly or inherently that would be understood by one of ordinary skill in the art. The specification instead discloses that by adjusting composition proportions of the glass so that the thermal expansion of the glass substrate is close to that of the die. This description does not mean that the CTE of elements actually substantially match (see the current specification paras [0038, 0083, 0123], for example.) The phrase “substantially matches, therefore, is unclear since there is not an actual value that was mentioned to further limit a value or a range of the elements. The term matches may also mean the same. Thus, for the examination purposes, the office presumes the CTE of the elements as currently claimed is close in value, but not identical or the same.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA  35 U.S.C. 102 and 103 (or as subject to pre-AIA  35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA  to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7, and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Goida et al. (US 2016/0167951, newly cited, hereinafter, Goida.)
In regard to claims 1, 7, and 13, in figs. 1A-1B, for example, Goida discloses a chip package structure, or an integrated device package 1 (para [0028], comprising:
a glass substrate, or an interposer 6 (paras [0028 and 0031]), wherein a first surface of the glass substrate has solder joints (not shown, however, the surface of the substrate has connecting element to accommodate the electrical connection with elements 8 and routing 10 (paras [0030-0031]) and a second surface of the glass substrate has substrate solder balls 9 (para [0034]);
a routing layer 10, wherein the routing layer is located in the glass substrate and the solder joints are electrically connected to the substrate solder balls by using the routing layer; and
a plurality of dies 2/3 (para [0004], where more dies may be formed), wherein each die has chip solder balls 8 (para [0030]), is located on the first surface of the glass substrate, and the solder joints are bonded to the chip solder balls, wherein composition proportions of the glass substrate ensure that a coefficient of thermal expansion of each die of the plurality of dies substantially closely matches is close to a coefficient of thermal expansion of the glass substrate (para [0031].)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 8, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goida as applied to claim 1 above, and further in view of MASUKAWA et al. (US 2018/0277395, previously cited, hereinafter, Masukawa.)
Regarding claims 2 and 8, and 14, Goida discloses all of the claimed limitations as mentioned above. Eisherbini also further mentions that the substrate may be laminated substrate (para [0031]) wherein the routing layers formed inside the substrate, except, further shows the detail wherein each routing layer is located between two adjacent glass layers.
Masukawa, in figs. 1b and 4a-d, discloses an analogous semiconductor device including a glass substrate 101/280 (para [0039]), a cavity111 (para [0039]) in the substrate, and electrical contacts 112/113 (para [0039]) on both sides of the substrate, and routing elements are formed between layers, fig. 4a. Masukawa further teaches the substrate is also a laminated substrate (para [0063]), and the routing elements are formed in between in order to provide protection, support, and external connection. This is common in the art.
Therefore, it would have been obvious to one of ordinary skill in the art to use the laminate substrate as taught in order to provide protection, support, and external connection.
Furthermore, regarding claim 8, the combination of Goida and Matsukawa further discloses the routing layers comprises copper and the method of printing to form conductive traces (Masukawa’s para [0043] and para [0051].)
Claim(s) 3, 6, 9, 12, 15, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goida as applied to claim 1 above, and further in view of Kang (US 2004/0154164.)
In regard to claims 3, 6, 9, 12, 15 and 18, Goida discloses all of the claimed limitations as mentioned above and further discloses a groove in the substrate 6, and other dies of the plurality of dies are located outside the groove, except some dies of the plurality of dies are located in the groove.
Kang, in fig. 2, discloses an analogous device including a ceramic (glass) substrate 204 (para [0012]) including a groove with steps on both sides and bottom chip or semiconductor die 206 disposed in and on the bottom of the groove in order to create addition surface area in the package as a whole. This is common in the art. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the application was filed to include the die in the groove a taught in order to create addition surface area in the package as a whole.
Allowable Subject Matter
Claims 4-5, 8, 10-11, and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art do not show some dies of the plurality of dies in the groove are located on the groove bottom, and the other dies of the plurality of dies are located on an upper surface of an ith step in the n steps.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion

APPLICANT REBUTTAL: REMARKS
Favorable reconsideration of this Application, in light of the following discussion, is respectfully requested. Claims 1-18 were previously presented. Claims 1, 7, and 13 are amended. Accordingly, claims 1-18 are pending in the present Application. Applicant submits that upon entry of the present Response, claims 1-18 are in condition for allowance. Moreover, Applicant submits that no new matter has been introduced by the foregoing amendments.
Req
uest
for
Entry into AFCP 2.0
Applicant hereby requests entry into the After Final Consideration Pilot Program 2.0 (AFCP 2.0 Request) and has provided at least one non-broadening amendment into the independent claims in order to make the claims eligible for the program. Applicant respectfully requests that the Examiner contact Applicant's undersigned representative during prosecution to discuss the merits of the present application.
Prior Art Re
jections
The Office Action rejected claims 1, 3, 7, 9, 13, and 15 under 35 U.S.C. @ 102(a)(1) as anticipated by Pub. No. US2020/0364600 to Elsherbini et al. ("Elsherbini"), mistakenly listed as Eisherbini by the Examiner, and alleged "inherency."
The Office Action rejected claims 2, 8, and 14 under 35 U.S.C. @ 103 as unpatentable over Elsherbini in view of Pub. No. US2018/0277395 to Masukawa et al. ("Masukawa").
The Office Action rejected claims 4-6, 10-12, and 16-18 under 35 U.S.C. @ 103 as unpatentable over Elsherbini in view Pub. No. US2004/0154164 to Kang ("Kang").
Claim 1, as amended, recites: "wherein
composition proportions of
the
gl
ass substrate
ensure that a coefficient of thermal expansion of each die of the plurality of dies substantially matches a coefficient of thermal expansion of the glass substrate" (emphasis added). Similar subject matter appears in claims 7 and 13. In the Specification, paragraph [0004] discloses that coefficients of thermal expansion of most glass substrates are far greater than a coefficient of thermal expansion of a die. Paragraph [0038] discloses that "the coefficient of thermal expansion of the glass may be adjusted by adjusting
composition proportions of the
gl
ass
during glass
preparation, so that the coefficient of thermal expansion of the glass is close to the coefficient of thermal expansion of the die." Also see paragraph [0055].
The Office Action relied upon Elsherbini for both a glass substrate and a plurality of dies, citing paragraph [0040]. In paragraph [0056], Elsherbini discloses that because substrate 102 and dies 114 have
si
g
nificantl
y
different coefficients
of thermal expansion (CTE), Elsherbini adds a mold material 127 with an intermediate CTE between 114 and 102 to reduce stress.
Hence, Elsherbini teaches away from a coefficient of thermal expansion of each die of the plurality of dies being close to a coefficient of thermal expansion of the glass substrate because Elsherbini must add mold material 127 to compensate for differential thermal expansion of the packet substrate 102 and the dies 114 due to their significantly different CTEs.
The Office Action alleged that the die is also a semiconductor die that is made of similar martial as the currently claimed die. The Examiner further alleged that these materials would
inherently
have the similar CTEs as currently claimed and considered to be relatively close in value. As described below, the Examiner has improperly relied upon inherency.
In M.P.E.P. § 2112-IV, an Examiner must provide rationale or evidence to show inherency. The fact that a certain result or characteristic
may
occur or be present in the prior art is not sufficient to establish the inherency of that result or characteristic. See In re Rijckaert, 9 F.3d 1531, 1534 (Fed. Cir. 1993). In relying upon the theory of inherency, the examiner must provide a basis in fact and/or technical reasoning to reasonably support the determination that the allegedly inherent characteristic
necessarily
flows from the teachings of the applied prior art." Ex parte Levy, 17 USPQ2d 1461, 1464 (Bd. Pat. App. & Inter. 1990).
Here,
composition proportions of the
gl
ass substrate
ensure that a coefficient of thermal expansion of each die of the plurality of dies substantially matches a coefficient of thermal expansion of the glass substrate. Rather than implying that the claimed materials would
inherently
have similar CTEs, paragraph [0056] of Elsherbini discloses that package substrate 102 and dies 114 have significantly different CTEs. Elsherbini does not suggest or teach that
composition
proportions of the
gl
ass substrate
result in CTE matching with the dies. Accordingly, the Office Action did not establish a primafacie case of anticipation based upon Elsherbini.
Masukawa and Kang do not remedy the deficiencies of Elsherbini. Accordingly, claims 1, 7, and 13 are allowable over the references of record.
Claim 4 recites: "wherein the groove comprises a groove bottom and n steps, the n steps are located on two sides of the groove bottom,
n is a positive integer, some dies of the plurality of dies in the groove are located on the groove bottom, and the other dies of the plurality of dies are located on an upper surface of an i
t
h
step in the n steps, wherein i is set to a value from 1 to n"
(emphasis added). Similar subject matter appears in claim 10 and 16. Paragraph [0072] of the Specification provides support by disclosing that as shown in FIG. 7, some of the plurality of dies 3 are located on the groove bottom 161, some of the dies 3 are located on an upper surface of an ith step 162, and the other of the dies 3 are located outside the groove 16, where i is set to a value from 1 to n. For example, if n is 2, some of the dies 3 are located on an upper surface of a first step 162, and some of the dies 3 are located on an upper surface of a second step 162.
The Office Action summarily alleged that "Eisherbini [sic] discloses all of the claimed limitations," but failed to address all of the subject matter. "All words in a claim must be considered in judging the patentability of that claim against the prior art." See In re Wilson, 424 F.2d 1382, 1385, 165 USPQ 494,496 (CCPA 1970).
The Examiner further relied upon Kang for "n steps on both sides" but neglected to provide the articulated reasoning required to establish a prima facie case of obviousness. Moreover, the Office Action failed to address the recited subject matter of "n is a positive integer, some dies of the plurality of dies in the groove are located on the groove bottom, and the other dies of the plurality of dies are located on an upper surface of an ii step in the n steps, wherein i is set to a value from 1 to n." Hence, claims 4, 10, and 16 are separately allowable.
Claim 5 recites: "wherein each step comprises
a first sub-step and a second sub-step,
the first sub-step and the second sub-step are respectively located on the two sides of the groove bottom in opposite positions and one end of each die on the upper surface of the ii step is located on an upper surface of the first sub-step, and the other end of each die is located on an upper surface of the second sub-step" (emphasis added). Similar subject matter appears in claims 11 and 17. Paragraph [0073] of the Specification provides support by disclosing that as shown in FIG. 6, each step 162 includes a first sub-step 162-1 and a second sub-step 162-2, where the first sub-step 162- 1 is located on a first side of the groove bottom 161, and the second sub-step 162-2 is located on
a second side of the groove bottom 161.
The Office Action summarily alleged that it would have been obvious to one of ordinary skill in the art at the time of the application was filed to have additional steps or substeps. The Examiner failed to identify any substeps in either Eisherbini or Kang and did not show that each step comprises
a first sub-step and a second sub-step.
Hence, the Office Action did not present a primafacie case of obviousness and claims 5, 11, and 17 are separately allowable.
Claims 2-6 depend upon claim 1, claims 8-12 depend upon claim 7, and claims 14-18 depend upon claim 13. Thus, claims 2-6, 8-12, and 14-18 are allowable due to their respective dependencies upon allowable claims. Therefore, Applicant respectfully requests withdrawal of these rejections.
CONCLUSION

NEXT OFFICE ACTION: DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA  35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA  35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 1, 7, and 13 recite a new limitation, “a gap having a specific distance”. The new limitation renders new matter situation because the original specification does not describe the specific distance of the gap in detail directly or inherently that would be understood by one of ordinary skill in the art, i.e. a value that is associated with it. The specification merely discloses the limitation.
The following is a quotation of 35 U.S.C. 112(b):
(b)  CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA  35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 7, and 13 recite a new limitation, “a gap having a specific distance”, in lines 6, 8, and 7, respectively. The new limitation renders indefinite situation because the original specification does not describe the limitation directly or inherently that would be understood by one of ordinary skill in the art. The phrase ““a gap having a specific distance”, therefore, is unclear since there is not an actual value that was mentioned to further make it specific. Therefore, for the examination purposes, the office presumes a gap or a distance between dies may be considered to inherently have a function of separating/insulating the dies.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA  35 U.S.C. 102 and 103 (or as subject to pre-AIA  35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA  to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7, and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Goida et al. (US 2016/0167951, previously cited, hereinafter, Goida.)
In regard to claims 1, 7, and 13, in figs. 1A-1B, for example, Goida discloses a chip package structure, or an integrated device package 1 (para [0028], comprising:
a glass substrate, or an interposer 6 (paras [0028 and 0031]), wherein a first surface of the glass substrate has solder joints (not shown, however, the surface of the substrate has connecting element to accommodate the electrical connection with elements 8 and routing 10 (paras [0030-0031]) and a second surface of the glass substrate has substrate solder balls 9 (para [0034]);
a routing layer 10, wherein the routing layer is located in the glass substrate and the solder joints are electrically connected to the substrate solder balls by using the routing layer; and
a plurality of dies 2/3 (para [0004], where more dies may be formed), the dies are further being separated by a predetermined distance or space creating by element 6, for example, (see the 112 rejections above), wherein each die has chip solder balls 8 (para [0030]), is located on the first surface of the glass substrate, and the solder joints are bonded to the chip solder balls.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 8, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goida as applied to claim 1 above, and further in view of MASUKAWA et al. (US 2018/0277395, previously cited, hereinafter, Masukawa.)
Regarding claims 2 and 8, and 14, Goida discloses all of the claimed limitations as mentioned above. Eisherbini also further mentions that the substrate may be laminated substrate (para [0031]) wherein the routing layers formed inside the substrate, except, further shows the detail wherein each routing layer is located between two adjacent glass layers.
Masukawa, in figs. 1b and 4a-d, discloses an analogous semiconductor device including a glass substrate 101/280 (para [0039]), a cavity111 (para [0039]) in the substrate, and electrical contacts 112/113 (para [0039]) on both sides of the substrate, and routing elements are formed between layers, fig. 4a. Masukawa further teaches the substrate is also a laminated substrate (para [0063]), and the routing elements are formed in between in order to provide protection, support, and external connection. This is common in the art.
Therefore, it would have been obvious to one of ordinary skill in the art to use the laminate substrate as taught in order to provide protection, support, and external connection.
Furthermore, regarding claim 8, the combination of Goida and Matsukawa further discloses the routing layers comprises copper and the method of printing to form conductive traces (Masukawa’s para [0043] and para [0051].)
Claim(s) 3, 6, 9, 12, 15, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goida as applied to claim 1 above, and further in view of Kang (US 2004/0154164, previously cited.)
In regard to claims 3, 6, 9, 12, 15 and 18, Goida discloses all of the claimed limitations as mentioned above and further discloses a groove in the substrate 6, and other dies of the plurality of dies are located outside the groove, except some dies of the plurality of dies are located in the groove.
Kang, in fig. 2, discloses an analogous device including a ceramic (glass) substrate 204 (para [0012]) including a groove with steps on both sides and bottom chip or semiconductor die 206 disposed in and on the bottom of the groove in order to create addition surface area in the package as a whole. This is common in the art. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the application was filed to include the die in the groove a taught in order to create addition surface area in the package as a whole.
Allowable Subject Matter
Claims 4-5, 10-11, and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not show some dies of the plurality of dies in the groove are located on the groove bottom, and the other dies of the plurality of dies are located on an upper surface of an ith step in the n steps.
Response to Arguments
Applicant's arguments filed 8/27/24 have been fully considered but they are not persuasive. The Applicant argues the prior art does not disclose the newly added limitation, “a gap having a specific distance.” As mentioned in the 112 rejections above, this limitation is unclear since it was not clearly defined in the specification. Nevertheless, the dies 2 and 3 as disclosed by Goida in fact is separated by a distance that is created by elements 6, 8, and the interposer (figs. 1A and 1C, for example.) This distance is considered to a specific because it serves its purpose of creating a space for the elements 5 to be formed, for example. Therefore, the prior as disclosed indeed discloses the claimed limitation. Thus, the rejection is maintained.
Conclusion
THIS ACTION IS MADE FINAL.  Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action.  In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action.  In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.

CITED REFERENCE SUMMARIES: Ref US20210043528A1: Claims:
An electronic package assembly comprising: a glass substrate comprising: an upper glass cladding layer; a lower glass cladding layer; a glass core layer fused to the upper glass cladding layer and the lower glass cladding layer, wherein the upper glass cladding layer and the lower glass cladding layer have a higher etch rate in an etchant than the glass core layer; a first cavity positioned within one of the upper glass cladding layer or the lower glass cladding layer; and a second cavity positioned within one of the upper glass cladding layer or the lower glass cladding layer; a microprocessor positioned within the first cavity; and a micro-electronic component positioned within the second cavity.
a glass substrate comprising: an upper glass cladding layer; a lower glass cladding layer; a glass core layer fused to the upper glass cladding layer and the lower glass cladding layer, wherein the upper glass cladding layer and the lower glass cladding layer have a higher etch rate in an etchant than the glass core layer; a first cavity positioned within one of the upper glass cladding layer or the lower glass cladding layer; and a second cavity positioned within one of the upper glass cladding layer or the lower glass cladding layer;
an upper glass cladding layer;
a lower glass cladding layer;
a glass core layer fused to the upper glass cladding layer and the lower glass cladding layer, wherein the upper glass cladding layer and the lower glass cladding layer have a higher etch rate in an etchant than the glass core layer;
a first cavity positioned within one of the upper glass cladding layer or the lower glass cladding layer; and
a second cavity positioned within one of the upper glass cladding layer or the lower glass cladding layer;
a microprocessor positioned within the first cavity; and
a micro-electronic component positioned within the second cavity.
The electronic package assembly of claim 1 , wherein the upper glass cladding layer has a thickness that is different than a thickness of the lower glass cladding layer.
The electronic package assembly of claim 1 , wherein the micro-electronic component comprises a memory chip positioned within the second cavity.
The electronic package assembly of claim 3 , wherein the first cavity is positioned on the lower glass cladding layer.
The electronic package assembly of claim 3 , wherein the second cavity is positioned on the upper glass cladding layer.
The electronic package assembly of claim 3 , wherein the first cavity and the second cavity are positioned on the lower glass cladding layer.
The electronic package assembly of claim 3 , wherein the glass substrate further comprises a third cavity, and the electronic package assembly further comprises a second micro-electronic component positioned within the third cavity of the glass substrate.
The electronic package assembly of claim 7 , wherein the third cavity and the second cavity are positioned on the same glass cladding layer.
The electronic package assembly of claim 3 , further comprising: a thermal via extending through the glass substrate and thermally coupled to the microprocessor; and a heat spreader thermally coupled to the thermal via.
a thermal via extending through the glass substrate and thermally coupled to the microprocessor; and
a heat spreader thermally coupled to the thermal via.
The electronic package assembly of claim 1 , wherein the upper glass cladding layer and the lower glass cladding layer have a photosensitivity that is different than a photosensitivity of the glass core layer.
The electronic package assembly of claim 1 , further comprising: a plurality of solder bumps positioned on a single surface of the electronic package assembly; and a plurality of vias extending between the plurality of solder bumps and the microprocessor and between the plurality of solder bumps and the micro-electronic component.
a plurality of solder bumps positioned on a single surface of the electronic package assembly; and
a plurality of vias extending between the plurality of solder bumps and the microprocessor and between the plurality of solder bumps and the micro-electronic component.
A wafer-level electronic package assembly comprising: a glass substrate comprising: an upper glass cladding layer; a lower glass cladding layer; a glass core layer fused to the upper glass cladding layer and the lower glass cladding layer, wherein the upper glass cladding layer and the lower glass cladding layer have a higher etch rate in an etchant than the glass core layer; a plurality of first cavities positioned within one of the upper glass cladding layer or the lower glass cladding layer; and a plurality of second cavities positioned within one of the upper glass cladding layer or the lower glass cladding layer; a plurality of microprocessors positioned within the plurality of first cavities; and a plurality of micro-electronic components positioned within the plurality of second cavities.
a glass substrate comprising: an upper glass cladding layer; a lower glass cladding layer; a glass core layer fused to the upper glass cladding layer and the lower glass cladding layer, wherein the upper glass cladding layer and the lower glass cladding layer have a higher etch rate in an etchant than the glass core layer; a plurality of first cavities positioned within one of the upper glass cladding layer or the lower glass cladding layer; and a plurality of second cavities positioned within one of the upper glass cladding layer or the lower glass cladding layer;
a plurality of first cavities positioned within one of the upper glass cladding layer or the lower glass cladding layer; and
a plurality of second cavities positioned within one of the upper glass cladding layer or the lower glass cladding layer;
a plurality of microprocessors positioned within the plurality of first cavities; and
a plurality of micro-electronic components positioned within the plurality of second cavities.
The wafer-level electronic package assembly of claim 12 , further comprising: a plurality of solder bumps positioned on a single surface of the electronic package assembly; and a plurality of vias extending between the plurality of solder bumps and the plurality of microprocessors and between the plurality of solder bumps and the plurality of micro-electronic components.
a plurality of vias extending between the plurality of solder bumps and the plurality of microprocessors and between the plurality of solder bumps and the plurality of micro-electronic components.
The wafer-level electronic package assembly of claim 12 , further comprising a plurality of passive RF devices positioned on a top surface of the electronic package assembly.
The wafer-level electronic package assembly of claim 13 , wherein the upper glass cladding layer has a thickness that is different than a thickness of the lower glass cladding layer.
A method for forming an electronic package assembly, the method comprising: applying a mask to a surface of a glass substrate comprising a glass cladding layer fused to a glass core layer such that the mask is positioned on the glass cladding layer, the mask comprising one or more open regions at which the glass cladding layer remains uncovered by the mask, the glass cladding layer having a higher etch rate in an etchant than the glass core layer; exposing the glass substrate to the etchant, thereby selectively etching a portion of the glass cladding layer and forming one or more cavities in the glass substrate; and positioning a micro-electronic component within the one or more cavities of the glass substrate.
applying a mask to a surface of a glass substrate comprising a glass cladding layer fused to a glass core layer such that the mask is positioned on the glass cladding layer, the mask comprising one or more open regions at which the glass cladding layer remains uncovered by the mask, the glass cladding layer having a higher etch rate in an etchant than the glass core layer;
exposing the glass substrate to the etchant, thereby selectively etching a portion of the glass cladding layer and forming one or more cavities in the glass substrate; and
positioning a micro-electronic component within the one or more cavities of the glass substrate.
The method of claim 16 , wherein exposing the glass substrate to the etchant comprises selectively etching all of the glass cladding layer at the one or more open regions.
The method of claim 16 , wherein the glass cladding layer of the glass substrate is an upper glass cladding layer and the glass substrate further comprises a lower glass cladding layer fused to the glass core layer on a surface opposite the upper glass cladding layer, and the method further comprises applying the mask to a surface of the lower glass cladding layer, the mask comprising one or more open regions at which the lower glass cladding layer remains uncovered.
The method of claim 18 , wherein exposing the glass substrate to the etchant further comprises selectively etching a portion of the lower glass cladding layer and forming one or more cavities in the lower glass cladding layer.
The method of claim 18 , wherein exposing the glass substrate to the etchant comprises selectively etching all of the lower glass cladding layer at the one or more open regions.
Ref US20200343213A1: Claims:
An inertial sensor comprising: a support substrate; a sensor main body supported by the support substrate; and a bonding member that is located between the support substrate and the sensor main body and bonds the sensor main body to the support substrate, wherein the sensor main body includes a substrate bonded to the support substrate via the bonding member, and a capacitance-type sensor device provided at a side of the substrate opposite to the support substrate, the substrate has a side surface, a first principal surface facing the support substrate, and a recessed step section that is located between the side surface and the first principal surface and connects the side surface to the first principal surface, and the bonding member extends along the first principal surface and the step section.
a support substrate;
a sensor main body supported by the support substrate; and
a bonding member that is located between the support substrate and the sensor main body and bonds the sensor main body to the support substrate,
wherein the sensor main body includes a substrate bonded to the support substrate via the bonding member, and a capacitance-type sensor device provided at a side of the substrate opposite to the support substrate,
a substrate bonded to the support substrate via the bonding member, and
a capacitance-type sensor device provided at a side of the substrate opposite to the support substrate,
the substrate has a side surface, a first principal surface facing the support substrate, and a recessed step section that is located between the side surface and the first principal surface and connects the side surface to the first principal surface, and
the bonding member extends along the first principal surface and the step section.
The inertial sensor according to claim 1 , wherein the bonding member is not in contact with the side surface.
The inertial sensor according to claim 1 , wherein the substrate has a recess in a second principal surface that faces away from the first principal surface and is so located as to face the sensor device, with the recess so provided as to overlap with the sensor device in a plan view, and a bottom surface of the recess is shifted from the step section toward the second principal surface.
wherein the substrate has a recess in a second principal surface that faces away from the first principal surface and is so located as to face the sensor device, with the recess so provided as to overlap with the sensor device in a plan view, and
a bottom surface of the recess is shifted from the step section toward the second principal surface.
The inertial sensor according to claim 3 , wherein the step section is provided between the recess and the side surface in the plan view.
The inertial sensor according to claim 3 , wherein the step section overlaps with the bottom surface of the recess in the plan view.
The inertial sensor according to claim 3 , wherein a boundary between the second principal surface and the recess coincides with a boundary between the first principal surface and the step section in the plan view.
An electronic instrument comprising: the inertial sensor according to claim 1 ; and a control circuit that performs control based on a detection signal outputted from the inertial sensor.
the inertial sensor according to claim 1 ; and
a control circuit that performs control based on a detection signal outputted from the inertial sensor.
A vehicle comprising: the inertial sensor according to claim 1 ; and a control unit that performs control based on a detection signal outputted from the inertial sensor.
a control unit that performs control based on a detection signal outputted from the inertial sensor.
A method for manufacturing an inertial sensor, the method comprising: bonding a device substrate to a side of a substrate having a first principal surface and a second principal surface facing away from each other that is a side facing the second principal surface; forming a capacitance-type sensor device from the device substrate; bonding a lid to the second principal surface of the substrate to cover the sensor device; forming a recessed step section in a region between the first principal surface and a side surface of the substrate; and bonding the substrate to a support substrate via a bonding member, wherein in the bonding of the substrate to the support substrate, the substrate is so bonded to the support substrate that the bonding member extends along the first principal surface and the step section.
bonding a device substrate to a side of a substrate having a first principal surface and a second principal surface facing away from each other that is a side facing the second principal surface;
forming a capacitance-type sensor device from the device substrate;
bonding a lid to the second principal surface of the substrate to cover the sensor device;
forming a recessed step section in a region between the first principal surface and a side surface of the substrate; and
bonding the substrate to a support substrate via a bonding member,
wherein in the bonding of the substrate to the support substrate, the substrate is so bonded to the support substrate that the bonding member extends along the first principal surface and the step section.
The method for manufacturing an inertial sensor according to claim 9 , wherein the step section is formed by half dicing.
Ref US20160167951A1: Claims:
An integrated device package comprising: a first integrated device die; a second integrated device die; an interposer disposed between the first integrated device die and the second integrated device die such that the first integrated device die is mounted to and electrically coupled to a first side of the interposer and the second integrated device die is mounted to and electrically coupled to a second side of the interposer, the first side opposite the second side, wherein the interposer comprises a hole through at least the second side of the interposer, a first portion of the second integrated device die extending into the hole and a second portion of the second integrated device die disposed vertically and laterally outside the hole on the second side of the interposer.
a first integrated device die;
a second integrated device die;
an interposer disposed between the first integrated device die and the second integrated device die such that the first integrated device die is mounted to and electrically coupled to a first side of the interposer and the second integrated device die is mounted to and electrically coupled to a second side of the interposer, the first side opposite the second side,
wherein the interposer comprises a hole through at least the second side of the interposer, a first portion of the second integrated device die extending into the hole and a second portion of the second integrated device die disposed vertically and laterally outside the hole on the second side of the interposer.
The package of claim 1 , wherein the hole comprises a through hole through the interposer.
The package of claim 1 , wherein the hole comprises a recess formed partially through a thickness of the interposer.
An integrated device package comprising: a first integrated device die; a second integrated device die; an interposer disposed between the first integrated device die and the second integrated device die such that the first integrated device die is mounted to and electrically coupled to a first side of the interposer and the second integrated device die is mounted to and electrically coupled to a second side of the interposer, the first side opposite the second side, wherein the interposer comprises a hole through at least the second side of the interposer, a portion of the second integrated device die extending into the hole, wherein the second integrated device die comprises a microelectromechanical systems (MEMS) die, and wherein the portion of the second integrated device die extending into the hole comprises a cap disposed over a MEMS device of the MEMS die.
wherein the interposer comprises a hole through at least the second side of the interposer, a portion of the second integrated device die extending into the hole,
wherein the second integrated device die comprises a microelectromechanical systems (MEMS) die, and wherein the portion of the second integrated device die extending into the hole comprises a cap disposed over a MEMS device of the MEMS die.
The package of claim 4 , wherein the first integrated device die comprises a processor die.
The package of claim 1 , further comprising an electrical contact disposed on the first side or the second side of the interposer, the electrical contact configured to electrically connect to an external substrate, and wherein the electrical contact has a height that is greater than a thickness of at least one of the first integrated device die and the second integrated device die.
The package of claim 6 , wherein the electrical contact comprises a plurality of solder balls disposed on the first side of the interposer and wherein the height of the solder balls is greater than the thickness of the first integrated device die.
The package of claim 7 , wherein the solder balls are disposed around an outer perimeter of the first integrated device die such that a lowermost extent of the solder balls is positioned below a lowermost extent of the first integrated device die.
The package of claim 1 , wherein each of the first integrated device die and the second integrated device die is flip-chip mounted to the interposer.
The package of claim 1 , wherein the package is not encapsulated with a molding material.
A method of manufacturing an integrated device package, the method comprising: mounting and electrically coupling a first integrated device die to a first side of an interposer; inserting a first portion of a second integrated device die into a hole of the interposer; and mounting and electrically coupling the second integrated device die to a second side of the interposer that is opposite the first side such that a second portion of the second integrated device die is disposed vertically and laterally outside the hole on the second side of the interposer.
mounting and electrically coupling a first integrated device die to a first side of an interposer;
inserting a first portion of a second integrated device die into a hole of the interposer; and
mounting and electrically coupling the second integrated device die to a second side of the interposer that is opposite the first side such that a second portion of the second integrated device die is dispose
[Truncated to input limit]