Office Action 1: Non-Final Rejection (2024-08-29)
Rejection types: 102 - Lack of Novelty, 103 - Obviousness, 112 - Written Description/Enablement

CLAIMS:
CLAIMS

1\. A semiconductor structure, comprising a plurality of metal layers and a substrate, wherein the plurality of metal layers comprises a first metal layer, a second metal layer, and a third metal layer;
a plurality of virtual metal blocks and at least one signal line are disposed on the metal layers;
the virtual metal blocks on the metal layers are staggered in a direction perpendicular to the substrate;
a second distance between a projection of a target signal line on the substrate and a projection of a second virtual metal block on the substrate is greater than a first distance between the projection of the target signal line on the substrate and a projection of a first virtual metal block on the substrate; and the target signal line is located on the first metal layer;
a third distance between the projection of the target signal line on the substrate and a projection of a third virtual metal block on the substrate is greater than the first distance;
and the first virtual metal block is a virtual metal block, in the first metal layer, closest to the target signal line, the second virtual metal block is a virtual metal block, in the second metal layer, closest to the target signal line, and the third virtual metal block is a virtual metal block, in the third metal layer, closest to the target signal line.

2\. The semiconductor structure according to claim 1, wherein projections, on the substrate, of the virtual metal blocks on the plurality of metal layers does not overlap.

3\. The semiconductor structure according claim 2, wherein the virtual metal blocks on each metal layer are arranged in an array.
4\. The semiconductor structure according to claim 3, wherein a projection matrix, on the substrate, of the virtual metal blocks on the first metal layer and a projection matrix, on the substrate, of the virtual metal blocks on another metal layer are arranged to cross each other; and
the another metal layer is a metal layer other than the first metal layer.

5\. The semiconductor structure according to claim 4, wherein there is a projection, of one of the virtual metal blocks on the third metal layer, between projections of the virtual metal blocks on the first metal layer.

6\. The semiconductor structure according claim 5, wherein two adjacent virtual metal blocks on the first metal layer are in a same row.

7\. The semiconductor structure according to claim 6, wherein projections of two adjacent virtual metal blocks on the first metal layer are in contact with projections of the virtual metal blocks on the third metal layer.

8\. The semiconductor structure according to claim 4, wherein there is a projection, of one of the virtual metal blocks on the second metal layer, between projections of two adjacent virtual metal blocks on the third metal layer.

9\. The semiconductor structure according claim 8, wherein two adjacent virtual metal blocks on the third metal layer are in a same column.

10\. The semiconductor structure according to claim 9, wherein the projections of two adjacent virtual metal blocks on the third metal layer are in contact with projections of the virtual metal blocks on the second metal layer.

11\. The semiconductor structure according to claim 10, wherein the third distance is equal to the second distance.
12\. The semiconductor structure according to claim 1, wherein the second metal layer is higher than the first metal layer, and the third metal layer is higher than the second metal layer.

13\. The semiconductor structure according to claim 1, wherein the target signal line is arranged according to the at least one signal line and selected from the at least one signal line.

14\. The semiconductor structure according to claim 1, wherein the projections of the virtual metal blocks on the substrate are quadrilaterals.

15\. The semiconductor structure according to claim 1, wherein the signal line is used to transmit a clock signal. 15 16 17

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show virtual metal blocks of the metal layer Mn, virtual metal blocks of metal layer Mn+1 and virtual metal blocks of metal layer Mn+1 as described in the specification of pages 3-11. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because drawings of FIG.5-FIG.8 fail to include virtual metal blocks in consistent in shaded blocks for of each of metal layers Mn, Mn+1 & Mn+2 properly.  Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of informalities.  Appropriate correction is required.
►	Specification, lines 18 and 21 of page 6,  “above” (s) should change to “at” (see fig 7 for details)
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b)  CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA  35 U.S.C. 112, the applicant), regards as the invention.
►	With respect to claim 4,
Lines 3 & 4, it is not clear that “another metal layer”(s)  mean “the second metal layer” or “the third metal layer” or an addition different layer different to “the plurality of metal layers” cited on line 2 of claim 1.  Applicant is respectfully suggested to clarify and use appropriate consistent claimed language to define scope of claim.
►	With respect to claim 7,
It is not clear how projections of two adjacent metal blocks on the first metal contact layer are in contact with projections of the virtual metal blocks of the third metal layer (see fig 1 shows metal layers Mn, Mn+1 & Mn+2 are spaced apart from each other)
►	With respect to claim 8,
It is not clear “a projection, of one of the virtual metal blocks on the second metal layer, between projections of two adjacent virtual metal blocks on the third metal layer” (see fig 7, the metal layer Mn+2 above the metal layer Mn+1 and the metal layer Mn+1 above the metal layer Mn)
►	With respect to claim 10,
It is not clear how projections of two adjacent metal blocks on the third metal contact layer are in contact with projections of the virtual metal blocks of the second metal layer (see fig 1 shows metal layers Mn, Mn+1 & Mn+2 are spaced apart from each other)
►	With respect to claim 11,
It is not clear how the third distance can be equal to the second distance (see fig 7, the second metal layer Mn+1 is higher than the first meta l layer Mn, and the third metal layer Mn+1 is higher than the second metal layer Mn+1)
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 12-13 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Chiu et al (US 2011/0248404]
►	With respect to claim 1, Chiu et al (fig 5 shown below, text [0001]-[0024]) discloses the claimed semiconductor structure comprising:
a plurality of metal layers (28) and a substrate (12), wherein the plurality of metal layers comprises a first metal layer (28), a second metal layer (28), and a third metal layer (28);
a plurality of virtual metal blocks (28B) and at least one signal line (28A are disposed on the metal layers;
the virtual metal blocks (28B) on the metal layers are staggered in a direction perpendicular to the substrate (see fig 5);
a second distance between a projection of a target signal line on the substrate and a projection of a second virtual metal block on the substrate is greater than a first distance between the projection of the target signal line on the substrate and a projection of a first virtual metal block on the substrate; and the target signal line is located on the first metal layer(see fig 5);
a third distance between the projection of the target signal line on the substrate and a projection of a third virtual metal block on the substrate is greater than the first distance (see fig 5);
the first virtual metal block is a virtual metal block, in the first metal layer, closest to the target signal line, the second virtual metal block is a virtual metal block, in the second metal layer, closest to the target signal line, and the third virtual metal block is a virtual metal block, in the third metal layer, closest to the target signal line (see fig 5).
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►	With respect to claim 2, Chiu et al (fig 5) discloses wherein projections, on the substrate, of the virtual metal blocks on the plurality of metal layers does not overlap.
►	With respect to claim 3, Chiu et al (fig 5) discloses wherein the virtual metal blocks on each metal layer are arranged in an array.
►	With respect to claim 12, Chiu et al (fig 5) discloses wherein the second metal layer is higher than the first metal layer, and the third metal layer is higher than the second metal layer.
►	With respect to claim 13, Chiu et al (fig 5) discloses wherein the target signal line is arranged according to the at least one signal line and selected from the at least one signal line.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al (US 2011/0248404]
►	With respect to claim 14, the projections of the virtual metal blocks on the substrate being quadrilaterals are well-known in the art.  In addition, claimed shape of projections of the virtual metal blocks was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the planar surface of the entire upper surface of the layer of material would yield unexpected result.  See In re  Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).►	With respect to claim 15,  a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art.  If the prior art structure is capable of performing the intended use, then it meets the claim.
Conclusion


NEXT OFFICE ACTION: DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 1, 5-15 are allowed.
The following is an examiner’s statement of reasons for allowance:    Recorded Prior Art fails to disclose or suggest combination structure of semiconductor structure as characteristics in base claim 1 comprising  the virtual metal blocks on the metal layers are staggered in a direction perpendicular to the substrate;  the first virtual metal block is a virtual metal block, in the first metal layer, closest to the target signal line, the second virtual metal block is a virtual metal block, in the second metal layer, closest to the target signal line, and the third virtual metal block is a virtual metal block, in the third metal layer, closest to the target signal line; wherein projections, on the substrate, of the virtual metal blocks on the plurality of metal layers does not overlap;  wherein the virtual metal blocks on each metal layer are arranged in an array; wherein a projection matrix, on the substrate, of the virtual metal blocks on the first metal layer and a projection matrix, on the substrate, of the virtual metal blocks on the second metal layer are arranged to cross each other; and a projection matrix, on the substrate, of the virtual metal blocks on the first metal layer and a projection matrix, on the substrate, of the virtual metal blocks on the third metal layer are arranged to cross each other.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee.  Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”

CITED REFERENCE SUMMARIES: Ref US20110248404A1: Claims:
A device comprising: a semiconductor substrate comprising a front side and a backside; a through-substrate via (TSV) penetrating the semiconductor substrate; and a first dummy metal line on the backside of the semiconductor substrate.
a semiconductor substrate comprising a front side and a backside;
a through-substrate via (TSV) penetrating the semiconductor substrate; and
a first dummy metal line on the backside of the semiconductor substrate.
The device of claim 1 , wherein the first dummy metal line is electrically floating.
The device of claim 1 further comprising a dummy TSV penetrating the semiconductor substrate.
The device of claim 3 , wherein the first dummy metal line is electrically coupled to the dummy TSV.
The device of claim 4 further comprising a second dummy metal line on the front side of the semiconductor substrate, wherein the second dummy metal line is electrically coupled to the dummy TSV and the first dummy metal line.
The device of claim 4 further comprising: a plurality of dielectric layers on the backside of the semiconductor substrate; a plurality of dummy metal lines, with one of the plurality of dummy metal lines in each of the plurality of dielectric layers; and a plurality of dummy vias electrically coupled to the plurality of dummy metal lines, with the plurality of dummy metal lines, the plurality of dummy vias, and the dummy TSV forming an integrated metal structure.
a plurality of dielectric layers on the backside of the semiconductor substrate;
a plurality of dummy metal lines, with one of the plurality of dummy metal lines in each of the plurality of dielectric layers; and
a plurality of dummy vias electrically coupled to the plurality of dummy metal lines, with the plurality of dummy metal lines, the plurality of dummy vias, and the dummy TSV forming an integrated metal structure.
The device of claim 1 further comprising a bond pad on the backside of the semiconductor substrate, wherein the first dummy metal line is at a same level as the bond pad.
The device of claim 1 further comprising a dummy via on the backside of the semiconductor substrate and connected to the first dummy metal line.
A device comprising: a semiconductor substrate comprising a front side and a backside; an active circuit on the front side of the semiconductor substrate; a through-substrate via (TSV) penetrating the semiconductor substrate; a dummy TSV penetrating the semiconductor substrate; and a first dummy metal line on the backside of the semiconductor substrate and electrically coupled to the dummy TSV, wherein the first dummy metal line and the dummy TSV are electrically floating.
an active circuit on the front side of the semiconductor substrate;
a through-substrate via (TSV) penetrating the semiconductor substrate;
a dummy TSV penetrating the semiconductor substrate; and
a first dummy metal line on the backside of the semiconductor substrate and electrically coupled to the dummy TSV, wherein the first dummy metal line and the dummy TSV are electrically floating.
The device of claim 9 , wherein the first dummy metal line physically contacts the dummy TSV.
The device of claim 9 , wherein the semiconductor substrate is a portion of a chip, and wherein the device further comprises: a bond pad at a back surface of the chip; and a dummy metal feature at a same level as the bond pad.
a bond pad at a back surface of the chip; and
a dummy metal feature at a same level as the bond pad.
The device of claim 9 further comprising: a plurality of dielectric layers on the backside of the semiconductor substrate; and a plurality of dummy metal features, with each of the plurality of dielectric layers comprising one of the plurality of dummy metal features therein, and wherein the plurality of dummy metal features and the dummy TSV form an integrated metal structure.
a plurality of dielectric layers on the backside of the semiconductor substrate; and
a plurality of dummy metal features, with each of the plurality of dielectric layers comprising one of the plurality of dummy metal features therein, and wherein the plurality of dummy metal features and the dummy TSV form an integrated metal structure.
The device of claim 12 further comprising a plurality of dummy vias, each in one of the plurality of dielectric layers and contacting a respective one of the plurality of dummy metal features.
The device of claim 9 further comprising a second dummy metal line on the front side of the semiconductor substrate.
The device of claim 14 , wherein the second dummy metal line is electrically coupled to the dummy TSV and the first dummy metal line.
The device of claim 14 further comprising: a plurality of dielectric layers on the front side of the semiconductor substrate; and a plurality of dummy metal features, with each of the plurality of dielectric layers comprising one of the plurality of dummy metal features therein, wherein the plurality of dummy metal features is electrically coupled to the dummy TSV.
a plurality of dielectric layers on the front side of the semiconductor substrate; and
a plurality of dummy metal features, with each of the plurality of dielectric layers comprising one of the plurality of dummy metal features therein, wherein the plurality of dummy metal features is electrically coupled to the dummy TSV.
A device comprising: a semiconductor substrate comprising a front side and a backside; an active circuit on the front side of the semiconductor substrate; a through-substrate via (TSV) penetrating the semiconductor substrate; a dummy TSV penetrating the semiconductor substrate; a first plurality of dielectric layers on the backside of the semiconductor substrate; a first plurality of dummy metal features, with each of the first plurality of dielectric layers comprising one of the first plurality of dummy metal features therein; a second plurality of dielectric layers on the front side of the semiconductor substrate; and a second plurality of dummy metal features, with each of the second plurality of dielectric layers comprising one of the second plurality of dummy metal features therein, and wherein the first and the second plurality of dummy metal features and the dummy TSV form an integrated metal structure, and are electrically floating.
a dummy TSV penetrating the semiconductor substrate;
a first plurality of dielectric layers on the backside of the semiconductor substrate;
a first plurality of dummy metal features, with each of the first plurality of dielectric layers comprising one of the first plurality of dummy metal features therein;
a second plurality of dielectric layers on the front side of the semiconductor substrate; and
a second plurality of dummy metal features, with each of the second plurality of dielectric layers comprising one of the second plurality of dummy metal features therein, and wherein the first and the second plurality of dummy metal features and the dummy TSV form an integrated metal structure, and are electrically floating.
The device of claim 17 further comprising a bond pad on the backside of the semiconductor substrate, wherein one of the first plurality of dummy metal features is at a same level as the bond pad.
The device of claim 17 , wherein one of the first plurality of dummy metal features is a dummy via.
Ref US20140151832A1: Claims:
A semiconductor device, comprising: a semiconductor substrate having a main surface; a light receiving element region formed in said main surface of said semiconductor substrate, in which light receiving elements for performing photoelectric conversion are formed; a peripheral region formed outside said light receiving element region in said main surface of said semiconductor substrate for performing input/output of an electric signal from/to outside of said semiconductor substrate; a boundary region formed between said light receiving element region and said peripheral region as seen in plane; a plurality of signal lines arranged in said boundary region for performing input/output of electric signals between said light receiving element region and said peripheral region; and a conductive layer arranged in a layer different from each of the plurality of said signal lines, a relative position of said conductive layer as seen from each of the plurality of said signal lines is all identical, and said conductive layer is all arranged in an identical layer.
a semiconductor substrate having a main surface;
a light receiving element region formed in said main surface of said semiconductor substrate, in which light receiving elements for performing photoelectric conversion are formed;
a peripheral region formed outside said light receiving element region in said main surface of said semiconductor substrate for performing input/output of an electric signal from/to outside of said semiconductor substrate;
a boundary region formed between said light receiving element region and said peripheral region as seen in plane;
a plurality of signal lines arranged in said boundary region for performing input/output of electric signals between said light receiving element region and said peripheral region; and
a conductive layer arranged in a layer different from each of the plurality of said signal lines,
a relative position of said conductive layer as seen from each of the plurality of said signal lines is all identical, and said conductive layer is all arranged in an identical layer.
The semiconductor device according to claim 1 , wherein said conductive layer is arranged at a position overlapping with each of the plurality of said signal lines as seen in plane.
The semiconductor device according to claim 2 , wherein said conductive layer is composed of a one-piece layer overlapping with all of the plurality of said signal lines.
The semiconductor device according to claim 1 , wherein a fixed potential is applied to said conductive layer.
The semiconductor device according to claim 4 , further comprising another conductive layer on a side of said the plurality of signal lines opposite to a side thereof facing said conductive layer, wherein said other conductive layer is arranged in a layer different from each of the plurality of said signal lines and said conductive layer, a relative position of said other conductive layer as seen from each of the plurality of said signal lines is all identical, and said other conductive layer is all arranged in an identical layer, and the fixed potential is applied to both of said conductive layer and said other conductive layer.
said other conductive layer is arranged in a layer different from each of the plurality of said signal lines and said conductive layer,
a relative position of said other conductive layer as seen from each of the plurality of said signal lines is all identical, and said other conductive layer is all arranged in an identical layer, and
the fixed potential is applied to both of said conductive layer and said other conductive layer.
The semiconductor device according to claim 5 , wherein said conductive layer and said other conductive layer are conducted to each other by a plurality of penetrating conductive regions penetrating between said conductive layer and said other conductive layer, and said signal line is surrounded by said conductive layer, said other conductive layer, and a pair of said penetrating conductive regions located on both sides of said signal line relative to a direction intersecting with a direction in which said signal line extends, of the plurality of said penetrating conductive regions.
said conductive layer and said other conductive layer are conducted to each other by a plurality of penetrating conductive regions penetrating between said conductive layer and said other conductive layer, and
said signal line is surrounded by said conductive layer, said other conductive layer, and a pair of said penetrating conductive regions located on both sides of said signal line relative to a direction intersecting with a direction in which said signal line extends, of the plurality of said penetrating conductive regions.
The semiconductor device according to claim 1 , wherein a plurality of metal layers including said conductive layer are laminated in said light receiving element region and said peripheral region, the number of said metal layers laminated in said light receiving element region is smaller than the number of said metal layers laminated in said peripheral region, and said metal layer as an uppermost layer of said metal layers in said light receiving element region is thinner than said metal layer as an uppermost layer of said metal layers in said peripheral region.
a plurality of metal layers including said conductive layer are laminated in said light receiving element region and said peripheral region,
the number of said metal layers laminated in said light receiving element region is smaller than the number of said metal layers laminated in said peripheral region, and
said metal layer as an uppermost layer of said metal layers in said light receiving element region is thinner than said metal layer as an uppermost layer of said metal layers in said peripheral region.
Ref US20110248404: Claims:
1. A device comprising:
a semiconductor substrate comprising a front side and a backside; a through-substrate via (TSV) penetrating the semiconductor substrate; and a first dummy metal line on the backside of the semiconductor substrate.
2. The device of claim 1, wherein the first dummy metal line is electrically floating.
3. The device of claim 1 further comprising a dummy TSV penetrating the semiconductor substrate.
4. The device of claim 3, wherein the first dummy metal line is electrically coupled to the dummy TSV.
5. The device of claim 4 further comprising a second dummy metal line on the front side of the semiconductor substrate, wherein the second dummy metal line is electrically coupled to the dummy TSV and the first dummy metal line.
6. The device of claim 4 further comprising:
a plurality of dielectric layers on the backside of the semiconductor substrate;
a plurality of dummy metal lines, with one of the plurality of dummy metal lines in each of the plurality of dielectric layers; and
a plurality of dummy vias electrically coupled to the plurality of dummy metal lines, with the plurality of dummy metal lines, the plurality of dummy vias, and the dummy TSV forming an integrated metal structure.
7. The device of claim 1 further comprising a bond pad on the backside of the semiconductor substrate, wherein the first dummy metal line is at a same level as the bond pad.
8. The device of claim 1 further comprising a dummy via on the backside of the semiconductor substrate and connected to the first dummy metal line.
9. A device comprising:
a semiconductor substrate comprising a front side and a backside; an active circuit on the front side of the semiconductor substrate; a through-substrate via (TSV) penetrating the semiconductor substrate; a dummy TSV penetrating the semiconductor substrate; and a first dummy metal line on the backside of the semiconductor substrate and electrically coupled to the dummy TSV, wherein the first dummy metal line and the dummy TSV are electrically floating.
10. The device of claim 9, wherein the first dummy metal line physically contacts the dummy TSV.
11. The device of claim 9, wherein the semiconductor substrate is a portion of a chip, and wherein the device further comprises:
a bond pad at a back surface of the chip; and a dummy metal feature at a same level as the bond pad.
12. The device of claim 9 further comprising:
a plurality of dielectric layers on the backside of the semiconductor substrate; and
a plurality of dummy metal features, with each of the plurality of dielectric layers comprising one of the plurality of dummy metal features therein, and wherein the plurality of dummy metal features and the dummy TSV form an integrated metal structure.
13. The device of claim 12 further comprising a plurality of dummy vias, each in one of the plurality of dielectric layers and contacting a respective one of the plurality of dummy metal features.
14. The device of claim 9 further comprising a second dummy metal line on the front side of the semiconductor substrate.
15. The device of claim 14, wherein the second dummy metal line is electrically coupled to the dummy TSV and the first dummy metal line.
16. The device of claim 14 further comprising:
a plurality of dielectric layers on the front side of the semiconductor substrate; and
a plurality of dummy metal features, with each of the plurality of dielectric layers comprising one of the plurality of dummy metal features therein, wherein the plurality of dummy metal features is electrically coupled to the dummy TSV.
17. A device comprising:
a semiconductor substrate comprising a front side and a backside; an active circuit on the front side of the semiconductor substrate; a through-substrate via (TSV) penetrating the semiconductor substrate; a dummy TSV penetrating the semiconductor substrate; a first plurality of dielectric layers on the backside of the semiconductor substrate; a first plurality of dummy metal features, with each of the first plurality of dielectric layers comprising one of the first plurality of dummy metal features therein; a second plurality of dielectric layers on the front side of the semiconductor substrate; and a second plurality of dummy metal features, with each of the second plurality of dielectric layers comprising one of the second plurality of dummy metal features therein, and wherein the first and the second plurality of dummy metal features and the dummy TSV form an integrated metal structure, and are electrically floating.
18. The device of claim 17 further comprising a bond pad on the backside of the semiconductor substrate, wherein one of the first plurality of dummy metal features is at a same level as the bond pad.
19. The device of claim 17, wherein one of the first plurality of dummy metal features is a dummy via.