Office Action 2: Notice of Allowance (2025-04-24)

CLAIMS:
AMENDMENTS TO THE CLAIMS

This listing of claims will replace all prior versions, and listings, of claims in the application:

1\. (Currently Amended) A semiconductor device, comprising:a to-be-etched layer having a plurality of first regions and a plurality of second regions that are alternately arranged along a first direction,
wherein a first region of the plurality of first regions adjoins a second region of the plurality of second regions;SVG {EMBED HERE} 0.1030.147
a first mask layer on the plurality of first regions and the plurality of second regions of the to-be-etched layer;
a first trench enclosed by a mask sidewall spacer, the mask sidewall spacer and the first trench together penetrating the first mask layer over a first region of the plurality of first regions;
a plurality of second trenches formed in the plurality of second regions, wherein the mask sidewall spacer, that encloses the first trench, is sandwiched between adjacent second trenches along the first direction; and
along a second direction perpendicular to the first direction, the first mask layer is in contact with the plurality of second trenches and the mask sidewall spacer.

2\. (Currently Amended) The semiconductor device according to claim 1, wherein:SVG {EMBED HERE} 0.1430.407
the first mask layer is made of one or more of amorphous silicon, silicon nitride, or silicon

3\. (Currently Amended) The semiconductor device according to claim \[\[1\]\] 11, wherein:along a direction perpendicular to a top surface ofthe to-be-etched layer, a ratio between a height of the first mask layer and a height of the protruded portion of the mask sidewall spacer is in a range of approximately 1:4 to 4:1.

4\. (Original) The semiconductor device according to claim 1, wherein:a thickness of the mask sidewall spacer is in a range of approximately 5 nm - 20 nm.

5\. (Original) The semiconductor device according to claim 1, wherein:along a direction perpendicular to a top surface of the to-be-etched layer, a height of the mask sidewall spacer is in a range of approximately 30 nm - 80 nm.

6\. (Original) The semiconductor device according to claim 1, wherein:

the mask sidewall spacer is made of one or more of SiO2, SiN, TiO2, TiN, AIN, or AI2O3.

7\. (Original) The semiconductor device according to claim 1, further including:a bottom hard mask layer between the to-be-etched layer and the first mask layer.

8\. (Original) The semiconductor device according to claim 7, further including:a first adhesion layer between the to-be-etched layer and the bottom hard mask layer, and
a second adhesion layer between the bottom hard mask layer and the first mask layer.

9\. (Original) The semiconductor device according to claim 7, wherein:the first trench is further penetrating the bottom hard mask layer, and the second trench is further penetrating the bottom hard mask layer.

10\. (Original) The semiconductor device according to claim 9, further including:a first conductive layer formed in the first trench, and
a second conductive layer formed in the second trench.

11\. (Currently Amended) The semiconductor device according to claim 1, wherein:the mask sidewall spacer, that encloses the first trench, has a top surface higher than a top surface of the first mask layer, providing a protruded portion over the top surface of the first mask layer.
Application No.: 17/849,015

12\. (New) The semiconductor device according to claim 1, wherein:each second trench is enclosed by portions of the first mask layer and portions of the mask sidewall spacer.

13\. (New) The semiconductor device according to claim 1, wherein:along a second direction, the mask sidewall spacer is in contact with the first mask layer on both sides of the mask sidewall spacer.

14\. (New) The semiconductor device according to claim 1, wherein:the first mask layer containing doping ions.

15\. (New) The semiconductor device according to claim 1, wherein:the plurality of second trenches includes a first second-trench and a second second-trench, each separating the mask sidewall spacer from the first mask layer along the first direction, and
all first trenches are located between the first second-trench and the second second-trench along the first direction.

OFFICE ACTION:
DETAILED ACTION
Status of Claims
As of the amendment filed 2/18/25, claims 12-15 have been added, no claims have been canceled, and claims 1-3 and 11 have been amended. Therefore, claims 1-15 remain pending, with claim 1 being independent.
Drawings
The drawings were received on 2/18/25.  These drawings are accepted.
Allowable Subject Matter
Claims 1-15 are allowed. The following is an examiner’s statement of reasons for allowance: The prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper.
The prior art fails to teach a combination of all of the features in the claims. As to claim 1, Han (US 2016/0314983) teaches a semiconductor device (fig. 9), comprising: a to-be-etched layer (150) having a plurality of first regions and a plurality of second regions that are alternately arranged along a first direction (see fig. A below), wherein a first region (r1) of the plurality of first regions adjoins a second region (r2) of the plurality of second regions (see Fig. A below); a first mask layer (220/230a/200) on the plurality of first regions and the plurality of second regions of the to-be-etched layer (150); a first trench (t1) “enclosed” by a mask sidewall spacer (220a), the mask sidewall spacer (220a) and the first trench (t1) together penetrating the first mask layer (230a/220/200) over a first region (r1) of the plurality of first regions; a plurality of second trenches (t2) formed in the plurality of second regions, wherein the mask sidewall spacer (220a), that encloses the first trench (t1), is sandwiched between adjacent second trenches (t2) along the first direction; and along a second direction perpendicular to the first direction, the first mask layer (200/220/230) is in contact with the plurality of second trenches (t2).
Han does not teach the first mask layer (200/220/230) is in contact with the mask sidewall spacer (220a) along the second direction, nor does the sidewall spacer enclose the first trench. Han is silent as to what is happening in the second direction. However, as shown in fig. 4a of Srivastava (US 2020/0111677), typically what is happening in the second direction is the formation of a line (25) within the trench with a sidewall liner (26, which does not enclose the trench). That trench is formed spanning the entire length of the first mask layer in the second direction, thus the first mask layer would not be is in contact with the mask sidewall spacer in the second direction.
The remaining claims are allowed at least because they depend from allowed claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee.  Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 2/18/258 have been fully considered and are persuasive. The previous rejection is hereby withdrawn.
Conclusion
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APPLICANT REBUTTAL: REMARKS By this Amendment, Applicant amends claims 1-3 and 11, adds new claims 12-15. Support for the claim amendments and new claims can be found in the as-filed patent application, e.g., FIGS. 12-13, and corresponding paragraphs in the specification. No new matter has been added. Claims 1-15 remain pending in the application. In addition, as shown in the concurrently filed replacement sheet of the drawings, FIG. 12 has been amended to change the reference number "130" into 110a, as supported at least in FIG. 11 and paragraph [0064]. In the Office Action1, the Examiner objected to the drawings with respect to Claim 1; rejected Claim 1 under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the enablement requirement; rejected Claim 1-11 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention; rejected Claim(s) 1-2, 4-10 under 35 U.S.C. 103 as being unpatentable over Han Eun-Shoo. (US 2016/0314983 Al hereinafter "Han") in view of Jin Jisong (US 2020/0279739 Al hereinafter "Jin"); and rejected Claim 3,11 under 35 U.S.C. 103 as being unpatentable over Han Eun-Shoo in view of Jin Jisong as applied to claim 1 above, and further in view of Wang; Dongjiang et.al. (US 9111874 B2 hereinafter "Wang"). Applicant respectfully traverses the rejections. SVG {EMBED HERE} 0.562.20 er of statements reflecting characterizations of the related art and the such statement is identified herein, Applicants decline to automatically cterization in the Office Action. Drawing Obiections The drawings are objected to under 37 CFR 1.83(a) with respect to Claim 1 because "a second mask layer and second trenches are not shown in figures 12 and 13 as required by claim 1". Present OA: page 2. In response, the second mask layer has been cancelled from claims. Further, the Office is reminded that second trenches 160 are clearly shown in FIGS. 12-13 as filed. The objections to the drawings are therefore obviated. Claim Relections - 35 USC § 112(a) § 112(b) Applicant respectfully traverses the 112 rejections in the present office action. In view of amendments to claim 1, rejections under 35 U.S.C. 112 (a) and (b), are overcome. Withdrawal of claim rejection is respectfully requested. Claim Rejections - 35 USC § 103 Applicant respectfully traverses the 103 rejections in the present office action. However, to expedite the prosecution of this application, Applicant has amended independent claim 1 to further define the claimed invention. Applicant respectfully submits that the amended independent claim 1 and its dependent claims are allowable over the applied references. As indicated in the Common Ownership Statement included with this paper, both the present application and Jin were, not later than the effective filing date of the claimed invention in the present application, owned by SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, and SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION. Therefore, according to the exception set forth in 35 U.S.C. § 102(b)(2)(C), JIN is not prior art to the claimed invention of the present application. See also M.P.E.P. § 717.02(a). Hence, the rejection under of claims 1-11 based on 35 USC § 103 over JIN in combination with Han and/or Wang should be withdrawn. Therefore, Applicant respectfully requests that the Examiner reconsider and withdraw the rejection of claims 1-11 under 35 U.S.C. § 103. CONCLUSION For at least the above reasons, Applicant respectfully requests the Examiner's reconsideration of the application and timely allowance of the pending claims in this application. If the Examiner believes that a telephone conference would expedite prosecution of this application, please telephone the undersigned. Please grant any extensions of time required to enter this response and charge any additional required fees to Deposit Account 505213. Respectfully submitted, Anova Law Group, PLLC Dated: February 18, 2025 By SVG {EMBED HERE} 0.8432.82


CITED REFERENCE SUMMARIES: Ref US20200111677A1: Claims:
A method comprising: depositing a hardmask over an interlayer dielectric layer; forming a first mandrel and a second mandrel over the hardmask; depositing a conformal spacer layer over the first mandrel, the second mandrel, and the hardmask between the first mandrel and the second mandrel, forming a first planarizing layer over the first mandrel, the second mandrel, and the hardmask; patterning the first planarizing layer to form a first trench that exposes a first lengthwise portion of the conformal spacer layer between the first mandrel and the second mandrel, a second trench that exposes a second lengthwise portion of the conformal spacer layer between the first mandrel and the second mandrel, and a portion of the first planarizing layer that covers a third lengthwise portion of the conformal spacer layer between the first mandrel and the second mandrel; and after patterning the first planarizing layer, removing the first lengthwise portion and the second lengthwise portion of the conformal spacer layer with a first etching process to expose respective first portions of the hardmask along a non-mandrel line, wherein the third lengthwise portion of the conformal spacer layer is masked during the first etching process by the portion of the first planarizing layer, and the third lengthwise portion of the conformal spacer layer defines a non-mandrel etch mask.
depositing a hardmask over an interlayer dielectric layer;
forming a first mandrel and a second mandrel over the hardmask;
depositing a conformal spacer layer over the first mandrel, the second mandrel, and the hardmask between the first mandrel and the second mandrel,
forming a first planarizing layer over the first mandrel, the second mandrel, and the hardmask;
patterning the first planarizing layer to form a first trench that exposes a first lengthwise portion of the conformal spacer layer between the first mandrel and the second mandrel, a second trench that exposes a second lengthwise portion of the conformal spacer layer between the first mandrel and the second mandrel, and a portion of the first planarizing layer that covers a third lengthwise portion of the conformal spacer layer between the first mandrel and the second mandrel; and
after patterning the first planarizing layer, removing the first lengthwise portion and the second lengthwise portion of the conformal spacer layer with a first etching process to expose respective first portions of the hardmask along a non-mandrel line,
wherein the third lengthwise portion of the conformal spacer layer is masked during the first etching process by the portion of the first planarizing layer, and the third lengthwise portion of the conformal spacer layer defines a non-mandrel etch mask.
The method of claim 1 wherein the first etching process shapes the conformal spacer layer to form a first sidewall spacer that is arranged between the first mandrel and the first portions of the hardmask and a second sidewall spacer that is arranged between the second mandrel and the first portions of the hardmask.
The method of claim 2 further comprising: forming a cut in the first mandrel after the first sidewall spacer and the second sidewall spacer are formed.
forming a cut in the first mandrel after the first sidewall spacer and the second sidewall spacer are formed.
The method of claim 3 wherein patterning the first planarizing layer comprises: forming a first lithographically-patterned etch mask over the first planarizing layer; and etching the first planarizing layer with a second etching process and the first lithographically-patterned etch mask including openings that provide a pattern for the first trench and the second trench during the second etching process, wherein the cut is formed in the first mandrel using a second lithographically-patterned etch mask.
forming a first lithographically-patterned etch mask over the first planarizing layer; and
etching the first planarizing layer with a second etching process and the first lithographically-patterned etch mask including openings that provide a pattern for the first trench and the second trench during the second etching process,
wherein the cut is formed in the first mandrel using a second lithographically-patterned etch mask.
The method of claim 1 wherein patterning the first planarizing layer comprises: forming a lithographically-patterned etch mask over the first planarizing layer; and etching the first planarizing layer with a second etching process and the lithographically-patterned etch mask arranged over the first planarizing layer.
forming a lithographically-patterned etch mask over the first planarizing layer; and
etching the first planarizing layer with a second etching process and the lithographically-patterned etch mask arranged over the first planarizing layer.
The method of claim 5 wherein forming the lithographically-patterned etch mask over the first planarizing layer comprises: forming a lithography stack including a photoresist layer over the first planarizing layer; and patterning the lithography stack to include a first opening arranged over the first lengthwise portion of the conformal spacer layer and a second opening arranged over the second lengthwise portion of the conformal spacer layer, wherein the first opening is aligned with the first trench, and the second opening is aligned with the second trench.
forming a lithography stack including a photoresist layer over the first planarizing layer; and
patterning the lithography stack to include a first opening arranged over the first lengthwise portion of the conformal spacer layer and a second opening arranged over the second lengthwise portion of the conformal spacer layer,
wherein the first opening is aligned with the first trench, and the second opening is aligned with the second trench.
The method of claim 6 wherein the lithography stack is removed when the first planarizing layer is patterned.
The method of claim 6 wherein a hardmask layer is arranged between the lithography stack and the first planarizing layer, and the hardmask layer is patterned to include the first trench and the second trench before patterning the first planarizing layer.
The method of claim 1 further comprising: forming a second planarizing layer over the first mandrel, the second mandrel, and the hardmask; patterning the second planarizing layer to form a first trench that exposes a first lengthwise section of the first mandrel, a second trench that exposes a second lengthwise section of the first mandrel, and a portion of the second planarizing layer that covers a third lengthwise section of the first mandrel that is arranged between the first lengthwise section of the first mandrel and the second lengthwise section of the first mandrel; and after patterning the first planarizing layer, removing the first lengthwise section and the second lengthwise section of the first mandrel with a second etching process to define a pattern including a first mandrel line and a second mandrel line exposing respective second portions of the hardmask that are separated by a third portion of hardmask covered by the first lengthwise section of the first mandrel during the second etching process.
forming a second planarizing layer over the first mandrel, the second mandrel, and the hardmask;
patterning the second planarizing layer to form a first trench that exposes a first lengthwise section of the first mandrel, a second trench that exposes a second lengthwise section of the first mandrel, and a portion of the second planarizing layer that covers a third lengthwise section of the first mandrel that is arranged between the first lengthwise section of the first mandrel and the second lengthwise section of the first mandrel; and
after patterning the first planarizing layer, removing the first lengthwise section and the second lengthwise section of the first mandrel with a second etching process to define a pattern including a first mandrel line and a second mandrel line exposing respective second portions of the hardmask that are separated by a third portion of hardmask covered by the first lengthwise section of the first mandrel during the second etching process.
The method of claim 9 wherein the first etching process forms a first sidewall spacer between the first mandrel and the second portions of the hardmask and second sidewall spacer between the second mandrel and the second portions of the hardmask.
The method of claim 10 wherein the pattern includes the non-mandrel etch mask and the non-mandrel line arranged between the first sidewall spacer and the second sidewall spacer, and further comprising: transferring the pattern to the hardmask with a third etching process.
transferring the pattern to the hardmask with a third etching process.
The method of claim 11 further comprising: transferring the pattern from the hardmask to the interlayer dielectric layer; and forming a plurality of interconnects in the interlayer dielectric layer that are arranged with the pattern.
transferring the pattern from the hardmask to the interlayer dielectric layer; and
forming a plurality of interconnects in the interlayer dielectric layer that are arranged with the pattern.
The method of claim 10 wherein the first sidewall spacer and the second sidewall spacer have a thickness, and the first lengthwise section of the first mandrel and the second lengthwise section of the first mandrel are separated by a tip-to-tip spacing that is greater than twice the thickness.
The method of claim 9 wherein the first lengthwise section of the first mandrel and the second lengthwise section of the first mandrel are separated by a tip-to-tip spacing, and the non-mandrel etch mask has a length that is greater than the tip-to-tip spacing.
The method of claim 1 further comprising: before depositing the conformal spacer layer, removing a lengthwise section of the first mandrel to expose a third portion of the hardmask.
before depositing the conformal spacer layer, removing a lengthwise section of the first mandrel to expose a third portion of the hardmask.
The method of claim 15 wherein the conformal spacer layer covers the third portion of the hardmask.
The method of claim 16 wherein the first planarizing layer is patterned to include a third trench over the second lengthwise portion of the conformal spacer layer.
The method of claim 17 further comprising: before patterning the first planarizing layer, forming an etch mask over the first planarizing layer, wherein the etch mask includes an opening that is aligned with the third trench.
before patterning the first planarizing layer, forming an etch mask over the first planarizing layer,
wherein the etch mask includes an opening that is aligned with the third trench.
The method of claim 17 wherein the second lengthwise portion of the conformal spacer layer is removed by the first etching process, the first etching process shapes the conformal spacer layer to form a first sidewall spacer arranged between the first mandrel and the first portions of the hardmask and second sidewall spacer arranged between the second mandrel and the first portions of the hardmask, and the second lengthwise portion of the conformal spacer layer has a width that is greater than a thickness of the first sidewall spacer and the second sidewall spacer.
The method of claim 1 wherein the planarizing layer masks the first mandrel and the second mandrel during the first etching process.
Ref US20160314983: Claims:
1. A method of forming patterns of a semiconductor device, comprising:
sequentially forming first to third mask layers on a substrate, wherein the substrate includes a first region and a second region; etching the third mask layer formed in the first region to form a first mask pattern, wherein the first mask pattern includes a plurality of first mask elements, and etching the third mask layer formed in the second region to form a second mask pattern, wherein the second mask pattern includes a plurality of second mask elements; forming a first spacer film, wherein the first spacer film covers the second mask elements of the second mask pattern and wherein the first spacer film is not formed in the first region; forming a second spacer film, the second spacer film being disposed on the first spacer film to fully fill at least one trench between the second mask elements of the second mask pattern and being disposed on the first mask elements of the first mask pattern; removing portions of the first and second spacer films covering upper surfaces of the first and second mask elements of the first and second mask patterns to expose the upper surfaces of the first and second mask elements of the first and second mask patterns; etching the second mask layer to form a third mask pattern, wherein the third mask pattern includes a plurality of third mask elements; etching the first mask layer using the third mask elements of the third mask pattern to form a fourth mask pattern, wherein the fourth mask pattern includes a plurality of fourth mask elements; and etching the substrate using the fourth mask elements of the fourth mask pattern.
2. The method of claim 1, wherein forming the first spacer film comprises conformally covering at least one second mask element of the second mask pattern.
3. The method of claim 1, wherein the first mask layer comprises two layers.
4. The method of claim 1, wherein forming the first spacer film comprises forming the first spacer film covering the first mask elements of the first mask pattern and the second mask elements of the second mask pattern, forming a block mask layer in the second region to at least partially cover the first spacer film, and removing the first spacer film disposed in the first region.
5. The method of claim 1, wherein a first distance between neighboring second mask elements of the second mask pattern is equal to or less than double a sum of a thickness of the first spacer film and a thickness of the second spacer film.
6. The method of claim 1, wherein a first pitch of a first mask element, from among the plurality of first mask elements of the first mask pattern, and a second pitch of a second mask element, from among the plurality of the second mask elements of the second mask pattern, are equal.
7. The method of claim 1, wherein a first mask element, from among the plurality of first mask elements of the first mask pattern, has a first width, and a second mask element, from among the plurality of second mask elements of the second mask pattern, has a second width, and wherein the first width and the second width are not equal.
8. The method of claim 1, wherein a thickness of the first spacer film is greater than a thickness of the second spacer film.
9. The method of claim 1, wherein etching the substrate comprises forming a plurality of fins, wherein a first distance between neighboring fins from among the plurality of fins formed in the first region is shorter than a second distance between neighboring fins from among the plurality of fins formed in the second region.
10. A method of forming patterns of a semiconductor device, comprising:
forming a mask layer on a target layer, wherein the target layer includes a first region and a second region; etching the mask layer formed in the first region to form a first mask pattern, wherein the first mask pattern includes a plurality of first mask elements, wherein at least one first mask element of the first mask pattern has a first width, and wherein the at least one first mask element of the first mask pattern is spaced apart from a proximate first mask element of the first mask pattern by a first distance; etching the mask layer formed in the second region to form a second mask pattern, wherein the second mask pattern includes a plurality of second mask elements, wherein at least one second mask element has a second width, wherein the second width and the first width are not equal, and wherein the at least one second mask element of the second mask pattern is spaced apart from a proximate second mask element of the second mask pattern by a second distance; forming a first spacer film, wherein the first spacer film covers the second mask elements of the second mask pattern, and wherein the first spacer film is not formed in the first region; forming a second spacer film, wherein the second spacer film is disposed on the first spacer film to fully fill at least one trench between the second mask elements of the second mask pattern, and wherein the second spacer film covers the first mask elements of the first mask pattern; removing portions of the first and second spacer films covering upper surfaces of the first and second mask elements of the first and second mask patterns to expose the upper surfaces of the first and second mask elements of the first and second mask patterns; and etching the target layer.
11. The method of claim 10, wherein a thickness of the first spacer film is greater than a thickness of the second spacer film.
12. The method of claim 10, wherein the second distance between the at least one second mask element of the second mask pattern and the proximate second mask element of the second mask pattern is equal to or less than double a sum of a thickness of the first spacer film and a thickness of the second spacer film.
13. The method of claim 10, wherein a first pitch of a first mask element, from among the plurality of first mask elements of the first mask pattern, and a second pitch of a second mask element, from among the plurality of second mask elements of the second mask pattern, are equal.
14. A method of forming patterns of a semiconductor device, comprising:
sequentially forming first to third mask layers on a substrate, wherein the substrate includes a first region and a second region; etching the third mask layer formed in the first region to form a first mask pattern, wherein the first mask pattern includes a plurality of first mask elements, and etching the third mask layer formed in the second region to form a second mask pattern, wherein the second mask pattern includes a plurality of second mask elements; forming a first spacer film, wherein the first spacer film covers the second mask elements of the second mask pattern and wherein the first spacer film is not formed in the first region; forming a second spacer film, wherein the second spacer film is disposed on the first spacer film, wherein the second spacer film fully fills at least one trench between the second mask elements of the second mask pattern, wherein the second spacer film is disposed on the first mask elements of the first mask pattern; removing portions of the first spacer film and portions of the second spacer film to expose upper surfaces of the first mask elements of the first mask pattern and upper surfaces of the second mask elements of the second mask pattern; etching the second mask layer to form a third mask pattern, wherein the third mask pattern includes a plurality of third mask elements; forming a third spacer film, wherein the third spacer film covers the third mask elements of the third mask pattern; removing portions of the third spacer film to expose upper surfaces of the third mask elements of the third mask pattern; etching the first mask layer to form a fourth mask pattern, wherein the fourth mask pattern includes a plurality of fourth mask elements; and etching the substrate to form a plurality of fins.
15. The method of claim 14, wherein at least one distance between adjacent second mask elements of the second mask pattern is equal to or less than double a sum of a thickness of the first spacer film and a thickness of the second spacer film.
16. The method of claim 14, wherein at least one pitch of a fin formed in the first region is different from at least one pitch of a fin formed in the second region.
17. The method of claim 14, wherein forming the first spacer film comprises con
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