Office Action 2: Notice of Allowance (2025-03-11)

CLAIMS:
In the Claims:

1\. (Currently Amended) A method of manufacturing a semiconductor device, the method comprising:performing one or more grinding processes on a backside surface of a device wafer to thin the device wafer from a first thickness to a second thickness, wherein performing the one or more grinding processes on the backside surface of the device wafer to thin the device wafer from the first thickness to the second thickness comprises performing a first grinding process and a second grinding process;
performing a first chemical mechanical polish (CMP) process on the backside surface of the device wafer to thin the device wafer from the second thickness to a third thickness; \[\[and\]\] performing a second CMP process on the backside surface of the device wafer to selectively remove device wafer material that is disposed over an active device area of the semiconductor device, wherein a removal rate of the device wafer material is a function of depth;
and adjusting at least one first grinding parameter during the performance of the first grinding process based on a first total thickness variation (TTV), the at least one first grinding parameter comprising a revolutions per minute (rpm) of a spindle in a grinding tool or a wheel type used in the grinding tool.
2\. (Original) The method of claim 1, further comprising bonding a carrier wafer to the device wafer prior to performing the one or more grinding processes.
3\. (Original) The method of claim 2, wherein the carrier wafer is made of silicon, quartz, or glass.
4\. (Original) The method of claim 1, wherein the device wafer comprises:
the active device area disposed at a frontside surface of the device wafer;
a first isolation region disposed at the frontside surface of the device wafer and adjacent to a first edge of the active device area; and

a second isolation region disposed at the frontside surface of the device wafer and adjacent to a second edge of the active device area.

5\. (Original) The method of claim 4, wherein performing the second CMP process on the backside surface of the device wafer to selectively remove bulk device wafer material that is disposed over the active device area of the semiconductor device produces a trench between the first isolation region and the second isolation region and exposes a backside surface of the active device area.

6\. (Original) The method of claim 5, wherein the trench has a depth of approximately one hundred nanometers.

7\. (Original) The method of claim 5, further comprising forming a mold compound in the trench.

8\. (Original) The method of claim 7, wherein the mold compound is thermally conductive and is included in a heat transfer path for the semiconductor device.

9\. (Currently Amended) The method of claim \[\[1\]\] 7, further comprising:bonding a carrier wafer to the device wafer prior to performing the one or more grinding processes; and
removing the carrier wafer after forming the mold compound in the trench.

10\. (Original) The method of claim 1, wherein the device wafer is a silicon wafer.

11\. (Original) The method of claim 1, wherein the first thickness is approximately seven hundred and twenty-five micrometers and the second thickness is approximately five micrometers.

12\. (Original) The method of claim 1, wherein the third thickness is approximately two hundred and fifty nanometers.

13 - 15. (Cancelled)1414

16\. (Currently Amended) The method of claim \[\[13\]\] SVG {EMBED HERE} 0.140.117 further comprising adjusting at least one second grinding parameter during theperformance of the second grinding process based on a second TTV, the at least one second grinding parameter comprising the rpm of \[\[a\]\] thespindle in \[\[a\]\] thegrinding tool, \[\[a\]\] thewheel type used in the grinding tool, an rpm of a stage of the grinding tool, or a tilt of the stage of the grinding tool.

17\. (Currently Amended) The method of claim 1, wherein performing the first CMP process on the backside surface of the device wafer further comprises adjusting at least one CMP parameter based on a thickness profile for the device wafer, the at least oneCMP parameter comprising the thickness profile of the device wafer or a slurry flow rate.

18\. (Currently Amended) The method of claim 1, wherein performing the first CMP process on the backside surface of the device wafer further comprises adjusting at least one CMP parameter based on a thickness profile for the device wafer, the at least oneCMP parameter comprising a rpmof a polish head of a polishing tool or an rpm of a platen of the polishing tool.

19\. (Currently Amended) The method of claim 1, wherein performing the first CMP process on the backside surface of the device wafer further comprises adjusting at least one CMP parameter based on a thickness profile for the device wafer, the at least oneCMP parameter comprising at least one zonal pressure of a polish head of a polishing tool.

20\. (New) A method of manufacturing a semiconductor device, the method comprising:performing one or more grinding processes on a backside surface of a device wafer to thin the device wafer from a first thickness to a second thickness, wherein performing the one or more grinding processes on the backside surface of the device wafer to thin the device wafer

from the first thickness to the second thickness comprises performing a first grinding process and a second grinding process;performing a first chemical mechanical polish (CMP) process on the backside surface of the device wafer to thin the device wafer from the second thickness to a third thickness;
performing a second CMP process on the backside surface of the device wafer to selectively remove device wafer material that is disposed over an active device area of the semiconductor device, wherein a removal rate of the device wafer material is a function of depth;
and adjusting at least one first grinding parameter during the performance of the first grinding process based on a first total thickness variation (TTV), the at least one first grinding parameter comprising a revolutions per minute (rpm) of a stage of the grinding tool or a tilt of the stage of the grinding tool.

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The amendment filed on 02/18/25 has been acknowledged and entered. By this amendment claims 13-15 are cancelled and claims 1-12 and 16-20 are pending in the application.
Reasons for Allowance
Claims 1-12 and 16-20 are allowed.
The following is an examiner's statement of reasons for allowance:
The prior art of record neither anticipates nor renders obvious all the limitations in the base claims 1 and 20. Specifically, the combination of a method of manufacturing a semiconductor device, the method comprising: performing the one or more grinding processes on the backside surface of the device wafer to thin the device wafer from the first thickness to the second thickness comprises performing a first grinding process and a second grinding process; performing a first chemical mechanical polish (CMP) process on the backside surface of the device wafer to thin the device wafer from the second thickness to a third thickness; performing a second CMP process on the backside surface of the device wafer to selectively remove device wafer material that is disposed over an active device area of the semiconductor device, wherein a removal rate of the device wafer material is a function of depth; and adjusting at least one first grinding parameter during the performance of the first grinding process based on a first total thickness variation (TTV), the at least one first grinding parameter comprising a revolutions per minute (rpm) of a spindle in a grinding tool or a wheel type used in the grinding tool.
The dependent claims being further limiting and definite are also allowable.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee.  Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”

APPLICANT REBUTTAL: REMARKS
Applicant has carefully reviewed the Office Action mailed December 2, 2024 and offers the following remarks to accompany the above amendments.
Status of the Claims
Claims 1-19 were previously pending. Claims 13-15 have been presently cancelled.
Claims 1, 9 and 16-19 have been amended. Claim 20 is newly added. No new matter has been added. Accordingly, claims 1-12 and claims 16-20 are pending.
Allowable Subject Matter
Applicant thanks the Examiner for indicating that claims 14-16 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Applicant has amended claim 1 to incorporate the features of claim 14 and intervening claim 13. Claims 13 and 14 have been cancelled. Therefore, claim 1 is now allowable. Claim 20 is new. Claim 20 includes the features of claim 1 prior to amendment, claim 15 (which is now cancelled), and intervening claim 13 (which has also been cancelled, as mentioned above). Therefore, claim 20 is also allowable.
Rejection Under 35 U.S.C. § 103 - Schmidt and Chung
Claims 1-7, 9-12, and 17-19 stand rejected under 35 U.S.C. § 103 as being unpatentable over U.S. Patent Application Publication No. 2021/0249503 Al to Schmidt et al. (hereinafter "Schmidt") in view of U.S. Patent Application Publication No. 2020/0094369 Al to Chung et al. (hereinafter "Chung"). Applicant respectfully traverses. Under § 103, "obviousness requires a suggestion of all limitations in a claim." Thus, in order to reject a claim under § 103, for each limitation of the claim, the Patent Office must show that the limitation is taught or suggested by the cited prior art references or would have otherwise been suggested to one of ordinary skill in the art at the time of the invention.
1 CFMT, Inc. v. Yieldup Intern. Corp., 349 F.3d 1333, 1342 (Fed. Cir. 2003) (citing In re Royka, 490 F.2d 981, 985 (CCPA 1974) (emphasis added)).
As mentioned above, the features of claim 14 and intervening claim 13 have been
incorporated into claim 1 and, therefore, independent claim 1 is now allowable. Therefore, the rejection of claim 1 is now moot.
Claims 2-7, 9-12, and 17-19 depend directly or indirectly from claim 1. As such, since claim 1 is allowable, claims 2-7, 9-12, and 17-19 are also allowable for at least the same reasons. However, Applicant reserves the right to further address the rejections of claims 2-7, 9-12, and 17-19 in the future, if desired.
Rejection Under 35 U.S.C. § 103 - Schmidt, Chung, and Wan
Claim 8 stands rejected under 35 U.S.C. § 103 as being unpatentable over Schmidt in
view of Chung and in further view of U.S. Patent Application Publication No. 2020/0098666 Al to Wan et al. (hereinafter "Wan"). Applicant respectfully traverses. The standards for obviousness are set forth above.
Claim 8 depends directly or indirectly from claim 1. As discussed above, Schmidt and Chung fail to disclose or suggest all of the features of claim 1. Wan fails to correct the deficiencies of Schmidt and Chung. As such, claim 1 is allowable over the combination of Schmidt, Chung, and Wan and claim 8 is allowable at least by virtue of its dependency from claim 1. However, Applicant reserves the right to further address the rejection of claim 8 in the future, if needed.
Rejection Under 35 U.S.C. § 103 - Schmidt, Chung, and Chang
Claim 13 stands rejected under 35 U.S.C. § 103 as being unpatentable over Schmidt in view of Chung and in further view of Chinese Patent Application Publication No. 1295762-C to Chang (hereinafter "Chang"). Applicant respectfully traverses. The standards for obviousness are set forth above.
Claim 13 has been presently cancelled. Therefore, the rejection of claim 13 is now moot.
Conclusion