Office Action 1: Non-Final Rejection (2024-11-20)
Rejection types: 103 - Obviousness, 112 - Written Description/Enablement

CLAIMS:
What is claimed is:

1\. A semiconductor device, comprising:
a to-be-etched layer having a plurality of first regions and a plurality of second regions that are alternately arranged along a first direction, wherein a first region of the plurality of first regions adjoins a second region of the plurality of second regions, and the second region includes a second trench region;
a first mask layer on the plurality of first regions and the plurality of second regions of the to-be-etched layer;
a second mask layer on the first mask layer;
a first trench penetrating the first mask layer and the second mask layer over a first region of the plurality of first regions;
a mask sidewall spacer on sidewall surfaces of the first trench; and
second trenches over the plurality of second trench regions of the plurality of second regions, wherein a sidewall surface of the second trench exposes a corresponding mask sidewall spacer of an adjacent first trench.

2\. The semiconductor device according to claim 1, wherein:
the first mask layer is made of one or more of amorphous silicon, silicon nitride, or
silicon oxide; and
the second mask layer is made of one or more of amorphous silicon, silicon nitride, or
silicon oxide.

3\. The semiconductor device according to claim 1, wherein:
a ratio between a thickness of the first mask layer and a thickness of the second mask layer is in a range of approximately 1:4 to 4:1.

4\. The semiconductor device according to claim 1, wherein:
a thickness of the mask sidewall spacer is in a range of approximately 5 nm - 20 nm.

5\. The semiconductor device according to claim 1, wherein:
along a direction perpendicular to a top surface of the to-be-etched layer, a height of the mask sidewall spacer is in a range of approximately 30 nm - 80 nm.

6\. The semiconductor device according to claim 1, wherein:
the mask sidewall spacer is made of one or more of SiO2, SiN, TiO2, TiN, AlN, or
A1203.

7\. The semiconductor device according to claim 1, further including:
a bottom hard mask layer between the to-be-etched layer and the first mask layer.

8\. The semiconductor device according to claim 7, further including:
a first adhesion layer between the to-be-etched layer and the bottom hard mask layer, and a second adhesion layer between the bottom hard mask layer and the first mask layer.

9\. The semiconductor device according to claim 7, wherein:
the first trench is further penetrating the bottom hard mask layer, and the second trench is further penetrating the bottom hard mask layer.

10\. The semiconductor device according to claim 9, further including:
a first conductive layer formed in the first trench, and
a second conductive layer formed in the second trench.

11\. The semiconductor device according to claim 1, wherein:
the mask sidewall spacer has a top surface higher than a top surface of the first mask layer. -22- -23- -24-

OFFICE ACTION:
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a).  The drawings must show every feature of the invention specified in the claims.  Therefore, the elements listed must be shown or the feature(s) canceled from the claim(s).  No new matter should be entered. A second mask layer and second trenches are not shown in figures 12 and 13 as required by claim 1. Therefore, the claimed structure is not proficient for a semiconductor device.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL. The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA  35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement.  The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 1 requires a structure that includes “a second mask layer on the first mask layer” and “second trenches over the plurality of second trench regions.”  However, Applicant’s disclosure teaches that the second trenches cannot be formed without removing the second mask layer. As such, one of skill in the art would not have been enabled to make and/or use the invention since it does not appear possible to have a structure with the claimed second mask layer and the second trench regions.
Claims 2-11 are rejected for failure to comply with the enablement requirement because of their dependence from claim 1.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b)  CONCLUSION. The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA  35 U.S.C. 112, the applicant regards as the invention.
Claim 1 recites the limitation and second trenches over the plurality of second trench regions of the plurality of second regions in line 12.  There is insufficient antecedent basis for this limitation in the claim.
Claims 2-11 are indefinite because of their dependence on indefinite claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han Eun-Shoo. (US 2016/0314983 A1 hereinafter “Han”) in view of Jin Jisong (US 2020/0279739 A1 hereinafter “Jin”),
Regarding claim 1 (e.g., fig. 9), Han teaches, a semiconductor device, comprising: a to-be-etched layer (110) having a plurality of first regions (A1) and a plurality of second regions (A2) that are alternately arranged along a first direction (X direction), wherein a first region (A1) of the plurality of first regions (A1) adjoins a second region (A2) of the plurality of second regions (A2), and the second region includes a second trench region (Par.0079); a first mask layer (140; hereinafter “second mask layer”) on the plurality of first regions (A1) and the plurality of second regions (A2) of the to-be-etched layer (110); a second mask layer (160; hereinafter “third mask layer”) on the first mask layer (140; hereinafter” second mask layer”).
Han is silent as to explicitly teaching a semiconductor device, comprising: a first trench penetrating the first mask layer and the second mask layer over a first region of the plurality of first regions; a mask sidewall spacer on sidewall surfaces of the first trench; and second trenches over the plurality of second trench regions of the plurality of second regions, wherein a sidewall surface of the second trench exposes a corresponding mask sidewall spacer of an adjacent first trench.
Jin teaches (e.g., Fig. 4-5) a semiconductor device, comprising: a first trench (121) penetrating the first mask layer (140 of Han; hereinafter “second mask layer”) and the second mask layer (160 of Han; hereinafter “third mask layer”) over a first region of the plurality of first regions (A01); a mask sidewall spacer (130) on sidewall surfaces of the first trench (121); and second trenches (150) over the plurality of second trench regions (A02) of the plurality of second regions (A02), wherein a sidewall surface of the second trench (150; Par. 0019) exposes a corresponding mask sidewall spacer (130) of an adjacent first trench (121).
It would have been obvious to one of the ordinary skills in the art at the time the application was effectively filed to use the side wall spacer and trenches as taught by Jin in the device of Han in order to have the predictable result of being able to use and customize a first/Second mask layer elements within the semiconductor device.
Regarding claim 2. Han in view of Jin teaches a semiconductor device according to claim 1, (Paragraph above).
Han does not teach wherein the first mask layer is made of one or more of amorphous silicon, silicon nitride, or silicon oxide; and the second mask layer is made of one or more of amorphous silicon, silicon nitride, or silicon oxide.
However, Jin teaches wherein the first mask layer is made of one or more of amorphous silicon, silicon nitride, or silicon oxide (Par0032); and the second mask layer is made of one or more of amorphous silicon, silicon nitride, or silicon oxide (Par0032).
It would have been obvious to one of the ordinary skills in the art at the time the application was effectively filed to use one or more of the materials in the result of making first mask and second mask layer as taught by Jin in the device of Han in order to have the predictable result of being able to use and customize material of a first/Second mask layer elements.
Regarding claim 4, Han in view of Jin teaches the semiconductor device according to claim 1, (Paragraph above).
Han does not teach wherein a thickness of the mask sidewall spacer is in a range of approximately 5 nm - 20 nm.
However, Jin teaches wherein a thickness of the mask sidewall spacer (130 of Jin; hereinafter “thickness of the sidewall film”) is in a range of approximately 5 nm - 20 nm (Jin; Par0045).
It would have been obvious to one of the ordinary skills in the art at the time the application was effectively filed to use of the mask sidewall spacer in the thickness range of approximately 30-80 nm as taught by Jin in the device of Han in order to have the predictable result to use customized elements of the mask layers within the semiconductor device.
Regarding claim 5. Han in view of Jin teaches the semiconductor device according to claim 1, (Paragraph above).
Han does not teach wherein along a direction perpendicular to a top surface of the to-be-etched layer, a height of the mask sidewall spacer is in a range of approximately 30 nm - 80 nm.
However, Jin teaches wherein along a direction perpendicular to a top surface of the to-be-etched layer (110 of Han; hereinafter “substrate”), a height of the mask sidewall spacer (130) is in a range of approximately 30 nm - 80 nm (Jin; Par0075).
It would have been obvious to one of the ordinary skills in the art at the time the application was effectively filed to use of the mask sidewall spacer in the height range of approximately 30-80 nm as taught by Jin in the device of Han in order to have the predictable result to use an element to-be-etched layer (substrate) in the semiconductor device.
Regarding claim 6, Han in view of Jin teaches the semiconductor device according to claim 1, (Paragraph above).
Han does not teach wherein the mask sidewall spacer is made of one or more of SiO2, SiN, TiO2, TiN, AlN, or Al203.
Jin teaches wherein the mask sidewall spacer is made of one or more of SiO2, SiN, TiO2, TiN, AlN, or Al203 (Par0066).
It would have been obvious to one of the ordinary skills in the art at the time the application was effectively filed to use of the mask sidewall spacer made of one or more of SiO2, SiN, TiO2, TiN, AlN, or Al203 as taught by Jin in the device of Han in order to have the predictable result to use an element first and second mask layer in the semiconductor device.
Regarding claim 7, Han in view of Jin teaches the semiconductor device according to claim 1, (Paragraph above).
However, Han teaches further including a bottom hard mask layer (120 of Han; hereinafter “bottom hard mask layer”) between the to-be-etched layer (110 of Han) and the first mask layer (140 of Han; hereinafter” second mask layer”).
Regarding claim 8 Han in view of Jin teaches the semiconductor device according to claim 7, (Paragraph above).
Han does not teach further including a first adhesion layer between the to-be-etched layer and the bottom hard mask layer and a second adhesion layer between the bottom hard mask layer and the first mask layer.
However, Jin teaches further including a first adhesion layer (not illustrated; Par.0035 of Jin) between the to-be-etched layer (110 of Han) and the bottom hard mask layer (120 of Han; hereinafter “bottom hard mask layer”; Fig.15), and a second adhesion layer (not illustrated; Par.0035 of Jin) between the bottom hard mask layer (120 of Han; hereinafter “bottom hard mask layer”; Fig.15) and the first mask layer (140 of Han; hereinafter” second mask layer”; Fig.10).
It would have been obvious to one of the ordinary skills in the art at the time the application was effectively filed to use a first and second adhesion layer in between to be-etched layer, bottom hard mask layer, and the first mask layer as taught by Jin in the device of Han in order to have the predictable result of being able to use elements of mask layers in a semiconductor device.
Regarding claim 9. Han in view of Jin teaches the semiconductor device according to claim 7, (Paragraph above).
However, Han further teaches (e.g., 15-16) wherein the first trench is further penetrating the bottom hard mask layer, (120 of Han; hereinafter “bottom hard mask layer”) and the second trench is further penetrating the bottom hard mask layer (120 of Han; hereinafter “bottom hard mask layer”).
Regarding claim 10 Han in view of Jin teaches the semiconductor device according to claim 9, (Paragraph above).
Han reference does not teach further including a first conductive layer formed in the first trench and a second conductive layer formed in the second trench.
However, Jin teaches further including a first conductive layer (Par0114 of Jin) formed in the first trench (121 of Jin), and a second conductive layer (Par0114 of Jin) formed in the second trench (150 of Jin).
It would have been obvious to one of the ordinary skills in the art at the time the application was effectively filed to use a first and second conductive layer in formation of first and second trench as taught by Jin in the device of Han in order to have the predictable result of being able to use an element of mask layers in a semiconductor device.
Claim 3,11 are rejected under 35 U.S.C. 103 as being unpatentable over Han Eun-Shoo in view of Jin Jisong as applied to claim 1 above, and further in view of Wang; Dongjiang et.al. (US 9111874 B2 hereinafter “Wang”),
Regarding claim 3. Han in view of Jin disclose the semiconductor device of claim 1 (Paragraph above).
Han in view of Jin do not teach a ratio between a thickness of the first mask layer and a thickness of the second mask layer is in a range of approximately (1:4 to 4:1).
Wang teaches wherein a ratio between a thickness of the first mask layer (120 of Wang; Par. 25) and a thickness of the second mask layer (130 of Wang; Par. 25) is in a range of approximately (1:4 to 4:1).
It would have been obvious to one of the ordinary skills in the art at the time the application was effectively filed to use a thickness of the first mask layer and the second mask layer in the range of approximately (1:4 to 4:1) as taught by Wang and to use sidewall spacer and trenches as taught by Jin in the device of Han in order to have a predictable result to use of a first and second mask layer in the semiconductor device.
Regarding claim 11. Han in view of Jin teaches, the semiconductor device according to claim 1, (Paragraph above).
Han in view of Jin references do not teach wherein the mask sidewall spacer has a top surface higher than a top surface of the first mask layer.
However, Wang teaches wherein the mask sidewall spacer has a top surface higher than a top surface of the first mask layer (Par.45).
It would have been obvious to one of the ordinary skills in the art at the time the application was effectively filed to use the mask sidewall spacer top surface higher than a top surface of the first mask layer as taught by Wang and to use sidewall spacer and trenches as taught by Jin in the device of Han in order to have a predictable result to use an element of a mask layer, a sidewall spacer and a trench in the semiconductor device.
Conclusion

APPLICANT REBUTTAL: REMARKS By this Amendment, Applicant amends claims 1-3 and 11, adds new claims 12-15. Support for the claim amendments and new claims can be found in the as-filed patent application, e.g., FIGS. 12-13, and corresponding paragraphs in the specification. No new matter has been added. Claims 1-15 remain pending in the application. In addition, as shown in the concurrently filed replacement sheet of the drawings, FIG. 12 has been amended to change the reference number "130" into 110a, as supported at least in FIG. 11 and paragraph [0064]. In the Office Action1, the Examiner objected to the drawings with respect to Claim 1; rejected Claim 1 under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the enablement requirement; rejected Claim 1-11 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention; rejected Claim(s) 1-2, 4-10 under 35 U.S.C. 103 as being unpatentable over Han Eun-Shoo. (US 2016/0314983 Al hereinafter "Han") in view of Jin Jisong (US 2020/0279739 Al hereinafter "Jin"); and rejected Claim 3,11 under 35 U.S.C. 103 as being unpatentable over Han Eun-Shoo in view of Jin Jisong as applied to claim 1 above, and further in view of Wang; Dongjiang et.al. (US 9111874 B2 hereinafter "Wang"). Applicant respectfully traverses the rejections. SVG {EMBED HERE} 0.562.20 er of statements reflecting characterizations of the related art and the such statement is identified herein, Applicants decline to automatically cterization in the Office Action. Drawing Obiections The drawings are objected to under 37 CFR 1.83(a) with respect to Claim 1 because "a second mask layer and second trenches are not shown in figures 12 and 13 as required by claim 1". Present OA: page 2. In response, the second mask layer has been cancelled from claims. Further, the Office is reminded that second trenches 160 are clearly shown in FIGS. 12-13 as filed. The objections to the drawings are therefore obviated. Claim Relections - 35 USC § 112(a) § 112(b) Applicant respectfully traverses the 112 rejections in the present office action. In view of amendments to claim 1, rejections under 35 U.S.C. 112 (a) and (b), are overcome. Withdrawal of claim rejection is respectfully requested. Claim Rejections - 35 USC § 103 Applicant respectfully traverses the 103 rejections in the present office action. However, to expedite the prosecution of this application, Applicant has amended independent claim 1 to further define the claimed invention. Applicant respectfully submits that the amended independent claim 1 and its dependent claims are allowable over the applied references. As indicated in the Common Ownership Statement included with this paper, both the present application and Jin were, not later than the effective filing date of the claimed invention in the present application, owned by SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, and SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION. Therefore, according to the exception set forth in 35 U.S.C. § 102(b)(2)(C), JIN is not prior art to the claimed invention of the present application. See also M.P.E.P. § 717.02(a). Hence, the rejection under of claims 1-11 based on 35 USC § 103 over JIN in combination with Han and/or Wang should be withdrawn. Therefore, Applicant respectfully requests that the Examiner reconsider and withdraw the rejection of claims 1-11 under 35 U.S.C. § 103. CONCLUSION For at least the above reasons, Applicant respectfully requests the Examiner's reconsideration of the application and timely allowance of the pending claims in this application. If the Examiner believes that a telephone conference would expedite prosecution of this application, please telephone the undersigned. Please grant any extensions of time required to enter this response and charge any additional required fees to Deposit Account 505213. Respectfully submitted, Anova Law Group, PLLC Dated: February 18, 2025 By SVG {EMBED HERE} 0.8432.82

NEXT OFFICE ACTION: DETAILED ACTION
Status of Claims
As of the amendment filed 2/18/25, claims 12-15 have been added, no claims have been canceled, and claims 1-3 and 11 have been amended. Therefore, claims 1-15 remain pending, with claim 1 being independent.
Drawings
The drawings were received on 2/18/25.  These drawings are accepted.
Allowable Subject Matter
Claims 1-15 are allowed. The following is an examiner’s statement of reasons for allowance: The prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper.
The prior art fails to teach a combination of all of the features in the claims. As to claim 1, Han (US 2016/0314983) teaches a semiconductor device (fig. 9), comprising: a to-be-etched layer (150) having a plurality of first regions and a plurality of second regions that are alternately arranged along a first direction (see fig. A below), wherein a first region (r1) of the plurality of first regions adjoins a second region (r2) of the plurality of second regions (see Fig. A below); a first mask layer (220/230a/200) on the plurality of first regions and the plurality of second regions of the to-be-etched layer (150); a first trench (t1) “enclosed” by a mask sidewall spacer (220a), the mask sidewall spacer (220a) and the first trench (t1) together penetrating the first mask layer (230a/220/200) over a first region (r1) of the plurality of first regions; a plurality of second trenches (t2) formed in the plurality of second regions, wherein the mask sidewall spacer (220a), that encloses the first trench (t1), is sandwiched between adjacent second trenches (t2) along the first direction; and along a second direction perpendicular to the first direction, the first mask layer (200/220/230) is in contact with the plurality of second trenches (t2).
Han does not teach the first mask layer (200/220/230) is in contact with the mask sidewall spacer (220a) along the second direction, nor does the sidewall spacer enclose the first trench. Han is silent as to what is happening in the second direction. However, as shown in fig. 4a of Srivastava (US 2020/0111677), typically what is happening in the second direction is the formation of a line (25) within the trench with a sidewall liner (26, which does not enclose the trench). That trench is formed spanning the entire length of the first mask layer in the second direction, thus the first mask layer would not be is in contact with the mask sidewall spacer in the second direction.
The remaining claims are allowed at least because they depend from allowed claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee.  Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 2/18/258 have been fully considered and are persuasive. The previous rejection is hereby withdrawn.
Conclusion
Any response to this Office Action should be faxed to (571) 273-8300 or mailed to:
Commissioner for Patents
P.O. Box 1450
Alexandria, VA 22313-1450
Hand-Delivered responses should be brought to:
Customer Service Window
Randolph Building
401 Dulany Street
Alexandria, VA 22313

CITED REFERENCE SUMMARIES: Ref US20160314983A1: Claims:
A method of forming patterns of a semiconductor device, comprising: sequentially forming first to third mask layers on a substrate, wherein the substrate includes a first region and a second region; etching the third mask layer formed in the first region to form a first mask pattern, wherein the first mask pattern includes a plurality of first mask elements, and etching the third mask layer formed in the second region to form a second mask pattern, wherein the second mask pattern includes a plurality of second mask elements; forming a first spacer film, wherein the first spacer film covers the second mask elements of the second mask pattern and wherein the first spacer film is not formed in the first region; forming a second spacer film, the second spacer film being disposed on the first spacer film to fully fill at least one trench between the second mask elements of the second mask pattern and being disposed on the first mask elements of the first mask pattern; removing portions of the first and second spacer films covering upper surfaces of the first and second mask elements of the first and second mask patterns to expose the upper surfaces of the first and second mask elements of the first and second mask patterns; etching the second mask layer to form a third mask pattern, wherein the third mask pattern includes a plurality of third mask elements; etching the first mask layer using the third mask elements of the third mask pattern to form a fourth mask pattern, wherein the fourth mask pattern includes a plurality of fourth mask elements; and etching the substrate using the fourth mask elements of the fourth mask pattern. 2. The method of claim 1, wherein forming the first spacer film comprises conformally covering at least one second mask element of the second mask pattern. 3. The method of claim 1, wherein the first mask layer comprises two layers. 4. The method of claim 1, wherein forming the first spacer film comprises forming the first spacer film covering the first mask elements of the first mask pattern and the second mask elements of the second mask pattern, forming a block mask layer in the second region to at least partially cover the first spacer film, and removing the first spacer film disposed in the first region. 5. The method of claim 1, wherein a first distance between neighboring second mask elements of the second mask pattern is equal to or less than double a sum of a thickness of the first spacer film and a thickness of the second spacer film. 6. The method of claim 1, wherein a first pitch of a first mask element, from among the plurality of first mask elements of the first mask pattern, and a second pitch of a second mask element, from among the plurality of the second mask elements of the second mask pattern, are equal. 7. The method of claim 1, wherein a first mask element, from among the plurality of first mask elements of the first mask pattern, has a first width, and a second mask element, from among the plurality of second mask elements of the second mask pattern, has a second width, and wherein the first width and the second width are not equal. 8. The method of claim 1, wherein a thickness of the first spacer film is greater than a thickness of the second spacer film. 9. The method of claim 1, wherein etching the substrate comprises forming a plurality of fins, wherein a first distance between neighboring fins from among the plurality of fins formed in the first region is shorter than a second distance between neighboring fins from among the plurality of fins formed in the second region. 10. A method of forming patterns of a semiconductor device, comprising: forming a mask layer on a target layer, wherein the target layer includes a first region and a second region; etching the mask layer formed in the first region to form a first mask pattern, wherein the first mask pattern includes a plurality of first mask elements, wherein at least one first mask element of the first mask pattern has a first width, and wherein the at least one first mask element of the first mask pattern is spaced apart from a proximate first mask element of the first mask pattern by a first distance; etching the mask layer formed in the second region to form a second mask pattern, wherein the second mask pattern includes a plurality of second mask elements, wherein at least one second mask element has a second width, wherein the second width and the first width are not equal, and wherein the at least one second mask element of the second mask pattern is spaced apart from a proximate second mask element of the second mask pattern by a second distance; forming a first spacer film, wherein the first spacer film covers the second mask elements of the second mask pattern, and wherein the first spacer film is not formed in the first region; forming a second spacer film, wherein the second spacer film is disposed on the first spacer film to fully fill at least one trench between the second mask elements of the second mask pattern, and wherein the second spacer film covers the first mask elements of the first mask pattern; removing portions of the first and second spacer films covering upper surfaces of the first and second mask elements of the first and second mask patterns to expose the upper surfaces of the first and second mask elements of the first and second mask patterns; and etching the target layer. 11. The method of claim 10, wherein a thickness of the first spacer film is greater than a thickness of the second spacer film. 12. The method of claim 10, wherein the second distance between the at least one second mask element of the second mask pattern and the proximate second mask element of the second mask pattern is equal to or less than double a sum of a thickness of the first spacer film and a thickness of the second spacer film. 13. The method of claim 10, wherein a first pitch of a first mask element, from among the plurality of first mask elements of the first mask pattern, and a second pitch of a second mask element, from among the plurality of second mask elements of the second mask pattern, are equal. 14. A method of forming patterns of a semiconductor device, comprising: sequentially forming first to third mask layers on a substrate, wherein the substrate includes a first region and a second region; etching the third mask layer formed in the first region to form a first mask pattern, wherein the first mask pattern includes a plurality of first mask elements, and etching the third mask layer formed in the second region to form a second mask pattern, wherein the second mask pattern includes a plurality of second mask elements; forming a first spacer film, wherein the first spacer film covers the second mask elements of the second mask pattern and wherein the first spacer film is not formed in the first region; forming a second spacer film, wherein the second spacer film is disposed on the first spacer film, wherein the second spacer film fully fills at least one trench between the second mask elements of the second mask pattern, wherein the second spacer film is disposed on the first mask elements of the first mask pattern; removing portions of the first spacer film and portions of the second spacer film to expose upper surfaces of the first mask elements of the first mask pattern and upper surfaces of the second mask elements of the second mask pattern; etching the second mask layer to form a third mask pattern, wherein the third mask pattern includes a plurality of third mask elements; forming a third spacer film, wherein the third spacer film covers the third mask elements of the third mask pattern; removing portions of the third spacer film to expose upper surfaces of the third mask elements of the third mask pattern; etching the first mask layer to form a fourth mask pattern, wherein the fourth mask pattern includes a plurality of fourth mask elements; and etching the substrate to form a plurality of fins. 15. The method of claim 14, wherein at least one distance between adjacent second mask elements of the second mask pattern is equal to or less than double a sum of a thickness of the first spacer film and a thickness of the second spacer film. 16. The method of claim 14, wherein at least one pitch of a fin formed in the first region is different from at least one pitch of a fin formed in the second region. 17. The method of claim 14, wherein forming the first spacer film comprises conformally covering at least one second mask element of the second mask pattern. 18. The method of claim 14, wherein the first mask layer comprises two layers. 19. The method of claim 14, wherein forming the first spacer film comprises forming the first spacer film covering the first mask elements of the first mask pattern and the second mask elements of the second mask pattern, forming a block mask layer in the second region to cover the first spacer film, and removing the first spacer film disposed in the first region. 20. The method of claim 14, wherein a thickness of the first spacer film is greater than a thickness of the second spacer film. 21. The method of claim 14, wherein a first mask element, from among the plurality of first mask elements of the first mask pattern, has a first width, and a second mask element, from among the plurality of second mask elements of the second mask pattern has a second width, and wherein the first width and the second width are not equal. 22. The method of claim 14, wherein a first pitch of a first fin, from among the plurality of fins in the first region, is equal to a second pitch of a second fin, from among the plurality of fins in the second region. 23. The method of claim 14, wherein forming the third spacer film comprises conformally covering at least one third mask element of the third mask pattern.
A method of forming patterns of a semiconductor device, comprising: sequentially forming first to third mask layers on a substrate, wherein the substrate includes a first region and a second region; etching the third mask layer formed in the first region to form a first mask pattern, wherein the first mask pattern includes a plurality of first mask elements, and etching the third mask layer formed in the second region to form a second mask pattern, wherein the second mask pattern includes a plurality of second mask elements; forming a first spacer film, wherein the first spacer film covers the second mask elements of the second mask pattern and wherein the first spacer film is not formed in the first region; forming a second spacer film, the second spacer film being disposed on the first spacer film to fully fill at least one trench between the second mask elements of the second mask pattern and being disposed on the first mask elements of the first mask pattern; removing portions of the first and second spacer films covering upper surfaces of the first and second mask elements of the first and second mask patterns to expose the upper surfaces of the first and second mask elements of the first and second mask patterns; etching the second mask layer to form a third mask pattern, wherein the third mask pattern includes a plurality of third mask elements; etching the first mask layer using the third mask elements of the third mask pattern to form a fourth mask pattern, wherein the fourth mask pattern includes a plurality of fourth mask elements; and etching the substrate using the fourth mask elements of the fourth mask pattern.
The method of claim 1, wherein forming the first spacer film comprises conformally covering at least one second mask element of the second mask pattern.
The method of claim 1, wherein the first mask layer comprises two layers.
The method of claim 1, wherein forming the first spacer film comprises forming the first spacer film covering the first mask elements of the first mask pattern and the second mask elements of the second mask pattern, forming a block mask layer in the second region to at least partially cover the first spacer film, and removing the first spacer film disposed in the first region.
The method of claim 1, wherein a first distance between neighboring second mask elements of the second mask pattern is equal to or less than double a sum of a thickness of the first spacer film and a thickness of the second spacer film.
The method of claim 1, wherein a first pitch of a first mask element, from among the plurality of first mask elements of the first mask pattern, and a second pitch of a second mask element, from among the plurality of the second mask elements of the second mask pattern, are equal.
The method of claim 1, wherein a first mask element, from among the plurality of first mask elements of the first mask pattern, has a first width, and a second mask element, from among the plurality of second mask elements of the second mask pattern, has a second width, and wherein the first width and the second width are not equal.
The method of claim 1, wherein a thickness of the first spacer film is greater than a thickness of the second spacer film.
The method of claim 1, wherein etching the substrate comprises forming a plurality of fins, wherein a first distance between neighboring fins from among the plurality of fins formed in the first region is shorter than a second distance between neighboring fins from among the plurality of fins formed in the second region.
A method of forming patterns of a semiconductor device, comprising: forming a mask layer on a target layer, wherein the target layer includes a first region and a second region; etching the mask layer formed in the first region to form a first mask pattern, wherein the first mask pattern includes a plurality of first mask elements, wherein at least one first mask element of the first mask pattern has a first width, and wherein the at least one first mask element of the first mask pattern is spaced apart from a proximate first mask element of the first mask pattern by a first distance; etching the mask layer formed in the second region to form a second mask pattern, wherein the second mask pattern includes a plurality of second mask elements, wherein at least one second mask element has a second width, wherein the second width and the first width are not equal, and wherein the at least one second mask element of the second mask pattern is spaced apart from a proximate second mask element of the second mask pattern by a second distance; forming a first spacer film, wherein the first spacer film covers the second mask elements of the second mask pattern, and wherein the first spacer film is not formed in the first region; forming a second spacer film, wherein the second spacer film is disposed on the first spacer film to fully fill at least one trench between the second mask elements of the second mask pattern, and wherein the second spacer film covers the first mask elements of the first mask pattern; removing portions of the first and second spacer films covering upper surfaces of the first and second mask elements of the first and second mask patterns to expose the upper surfaces of the first and second mask elements of the first and second mask patterns; and etching the target layer.
The method of claim 10, wherein a thickness of the first spacer film is greater than a thickness of the second spacer film.
The method of claim 10, wherein the second distance between the at least one second mask element of the second mask pattern and the proximate second mask element of the second mask pattern is equal to or less than double a sum of a thickness of the first spacer film and a thickness of the second spacer film.
The method of claim 10, wherein a first pitch of a first mask element, from among the plurality of first mask elements of the first mask pattern, and a second pitch of a second mask element, from among the plurality of second mask elements of the second mask pattern, are equal.
A method of forming patterns of a semiconductor device, comprising: sequentially forming first to third mask layers on a substrate, wherein the substrate includes a first region and a second region; etching the third mask layer formed in the first region to form a first mask pattern, wherein the first mask pattern includes a plurality of first mask elements, and etching the third mask layer formed in the second region to form a second mask pattern, wherein the second mask pattern includes a plurality of second mask elements; forming a first spacer film, wherein the first spacer film covers the second mask elements of the second mask pattern and wherein the first spacer film is not formed in the first region; forming a second spacer film, wherein the second spacer film is disposed on the first spacer film, wherein the second spacer film fully fills at least one trench between the second mask elements of the second mask pattern, wherein the second spacer film is disposed on the first mask elements of the first mask pattern; removing portions of the first spacer film and portions of the second spacer film to expose upper surfaces of the first mask elements of the first mask pattern and upper surfaces of the second mask elements of the second mask pattern; etching the second mask layer to form a third mask pattern, wherein the third mask pattern includes a plurality of third mask elements; forming a third spacer film, wherein the third spacer film covers the third mask elements of the third mask pattern; removing portions of the third spacer film to expose upper surfaces of the third mask elements of the third mask pattern; etching the first mask layer to form a fourth mask pattern, wherein the fourth mask pattern includes a plurality of fourth mask elements; and etching the substrate to form a plurality of fins.
The method of claim 14, wherein at least one distance between adjacent second mask elements of the second mask pattern is equal to or less than double a sum of a thickness of the first spacer film and a thickness of the second spacer film.
The method of claim 14, wherein at least one pitch of a fin formed in the first region is different from at least one pitch of a fin formed in the second region.
The method of claim 14, wherein forming the first spacer film comprises conformally covering at least one second mask element of the second mask pattern.
The method of claim 14, wherein the first mask layer comprises two layers.
The method of claim 14, wherein forming the first spacer film comprises forming the first spacer film covering the first mask elements of the first mask pattern and the second mask elements of the second mask pattern, forming a block mask layer in the second region to cover the first spacer film, and removing the first spacer film disposed in the first region.
The method of claim 14, wherein a thickness of the first spacer film is greater than a thickness of the second spacer film.
The method of claim 14, wherein a first mask element, from among the plurality of first mask elements of the first mask pattern, has a first width, and a second mask element, from among the plurality of second mask elements of the second mask pattern has a second width, and wherein the first width and the second width are not equal.
The method of claim 14, wherein a first pitch of a first fin, from among the plurality of fins in the first region, is equal to a second pitch of a second fin, from among the plurality of fins in the second region.
The method of claim 14, wherein forming the third spacer film comprises conformally covering at least one third mask element of the third mask pattern.
Ref US20200279739A1: Claims:
A method for fabricating a semiconductor device, comprising: providing a to-be-etched layer, including a plurality of first regions and a plurality of second regions arranged alternately along a first direction, wherein for a first region of the plurality of first regions adjacent to a second region of the plurality of second regions, the first region and 
[Truncated to input limit]