Office Action 3: Notice of Allowance (2024-09-05)

CLAIMS:
In the Claims:

1\. (Previously Presented) A system for protecting a speculative execution processor, from side channel attacks, comprising a processing circuitry, adapted to:in a first time period, performing a plurality of executions of a same code segment in a plurality of time intervals and measure an execution time of the code segment in each of the plurality of time intervals;
updating a time register to include a highest execution time measured for the plurality of time intervals;
storing speculative instructions in an internal cache memory which is inaccessible to read actions of an external processing unit;
in a second time period, performing a delayed copy, wherein in said delayed copy, copying only a committed portion of the executed code segment into another memory component which is accessible to read actions of the external processing unit, wherein a delay time of said delayed copy is according to the highest execution time included in said time register;
wherein the first and second time periods are different and independent.

2\. (Cancelled)

3\. (Previously Presented) The system of claim 1, wherein the processing circuitry is further adapted to:delay the copying only the committed portion of the executed code segment into the another memory component according to a value which is not correlated with the actual execution time measured.

4\. (Previously Presented) The system of claim 1, wherein a user annotates a beginning and an end of the code segment with dedicated instructions respectively.

5\. (Original) The system of claim 4, wherein the executed code segment annotated by the user is a single entry code segment.

6\. (Original) The system of claim 4, wherein the executed code segment annotated by the user is a multi-entry code segment.

7\. (Original) The system of claim 6, wherein the annotation of the multi-entry code segment is extended, according to a number of an entry.

8\. (Previously Presented) The system of claim 6, wherein in the multi entry code segment each entry is allocated in a table-like structure and each entry number is determined by using one or more hash functions that take an address of an instruction annotating the beginning of the code segment as a parameter.

9\. (Original) The system of claim 1, wherein the processing circuit is further adapted to add noise in conjunction with the execution of the code segment to increase a noise to signal ratio.

10\. (Original) The system of claim 1, wherein the processing circuitry is adapted to perform a double execution of the code segment.

11\. (Original) The system of claim 1, wherein the speculative instructions stored in the internal cache memory are load and store instructions.

12\. (Original) The system of claim 1, wherein the internal cache memory is virtually tagged.

13\. (Original) The system of claim 1, wherein the internal cache memory is exclusive so that data cannot be stored in the internal cache memory and into the another memory component at a same time.

14\. (Previously Presented) The system of claim 1, wherein the internal cache memory is cleaned at an end of a process.

15\. (Oiginal) The system of claim 1, wherein the internal cache memory is dynamically partitioned among different threads.

16\. (Original) The system of claim 1, wherein the internal cache memory is a scratchpad memory.

17\. (Currently Amended) A method for protecting speculative execution processor, from side channel attacks, comprising:in a first time period, performing an execution of a code segment by storing speculative instructions in an internal cache memory which is inaccessible to read actions of an external processing unit;
measuring an execution time of the code segment in a plurality of time intervals;
updating a time register to include a highest execution time measured for the plurality of time intervals;
in a second time period, performing a delayed copy, wherein in said delayed copy, copying only a committed portion of the executed code segment into another memory component which is accessible to read actions of the external processing unit, wherein a delay time of said delayed copy is according to the highest execution time included in said time register;
wherein the first and second time periods are different and independent.

18\. (Cancelled)

19\. (Currently Amended) A computer program product comprisinga non- transitory computer readable storage medium storing instructions for performing a method for protecting speculative execution processor, from side channel attacks, comprising:in a first time period, performing an execution of a code segment by storing speculative instructions in an internal cache memory which is inaccessible to read actions of an external processing unit;
measuring an execution time of the code segment in a plurality of time intervals;

updating a time register to include a highest execution time measured for the plurality of time intervals;
in a second time period, performing a delayed copy, wherein in said delayed copy, copying only a committed portion of the executed code segment into another memory component which is accessible to read actions of the external processing unit, wherein a delay time of said delayed copy is according to the highest execution time included in said time register;
wherein the first and second time periods are different and independent.

20\. (Cancelled)

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgements
This communication is in response to
Application claim amendments filed on 08/21/2024, and
The amendments filed on 08/21/2024 have been entered.
The claims amendments overcome the objections and the USC 101 rejections previously set forth in the Office Action mailed on 06/21/2024.
Allowable Subject Matter
Claims 1, 3-17 and 19 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Cited and relevant prior art of record:
Johnson et al. (US 20190114422 A1),
Klaiber et al. (US 7962909 B1),
Michalak et al. (US 20080046692 A1), and
Courtney (US 20180323960 A1).
Johnson discloses processor modifications that prevent the observation of the side effects of mispredicted speculative execution flows, the processor can make use of speculative execution after a branch or conditional load, but avoid performing any operation that could cause observable side-effects if the operation was mispredicted, Johnson further discloses recording the effects of one or more speculatively-executed instructions to the one or more speculation buffers, utilize speculative execution after a branch or conditional load, and avoids observable side-effects of memory loads during this speculative execution by buffering the results/effects of those loads into one or more speculation buffers. Klaiber discloses monitoring a processor's execution core to detect an end of an execution interval, and causes the processor to exit a guest at the end of the execution interval. Michalak discloses a processor may directly write the dynamic delay value to a coprocessor register, highly speculative instructions may incur a greater execution delay while less speculative instructions may incur a lesser delay, each instruction or set of instructions offloaded to the coprocessor may incur an execution delay based on their speculative nature. For example, highly speculative instructions may incur a greater execution delay while less speculative instructions may incur a lesser delay. Courtney discloses a method and apparatus for defending against a side-channel attack upon a data storage device, and further discloses that in response to a function call signal being generated to request execution of a given function, a timer circuit is initiated to count out a predetermined elapsed time interval. The overall duration of the elapsed time interval is selected based on empirical or adaptive measurements, or system specifications, regarding the maximum likely duration of the execution of the function.
While the above prior arts disclose the aforementioned concepts, however, none of the prior arts, individually or in reasonable combination, discloses all the limitations in the manner recited in the independent claims. Specifically, none of the prior art discloses “…in a first time period performing, an execution of a code segment by storing speculative instructions in an internal cache memory which is inaccessible to read actions of an external processing unit; measuring an execution time of the code segment in a plurality of time intervals; updating a time register to include a highest execution time measured for the plurality of time intervals; in a second time period, performing a delayed copy, wherein in said delayed copy, copying only a committed portion of the executed code segment into another memory component which is accessible to read actions of the external processing unite wherein a delay time of said delayed copy is according to the highest execution time included in said time register; wherein the first and second time periods are different and independent”. Therefore, the above limitations in conjunction with the remaining limitations of the independent claims render the above independent claims allowable.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled Comments on Statement of Reasons for Allowance.
Conclusion

APPLICANT REBUTTAL: REMARKS
Reconsideration of the above-identified application in view of the amendments above and the remarks following is respectfully requested.
Claims 1, 3-7, and 19-20 have been presented for examination.
Claims 1, 3-16 are allowed.
Specification
The disclosure is objected to because page 1 lines 16-17 recites "When the tasks are really required the speed up is achieved ... ", should read "When the tasks are really required.i. the speed up is achieved ... ". Applicant amended the specification accordingly.
Claim Objections
Claims 17 and 19 objected to because of minor informalities. Applicant amended the claims to remove the referred to informalities.
Claim Rejections - 35 USC &S 101
Claim 19 is rejected under 35 U.S.C. 101 because the claimed invention is
directed to non-statutory subject matter. In order to overcome the above USC 101 rejection, examiner recommended amending claim 19 to recite "A computer program product comprising a non- transitory computer readable storage medium". Applicant amended the claims accordingly.
Conclusion


CITED REFERENCE SUMMARIES: Ref US20190114422A1: Claims:
A microprocessor, comprising: a register file comprising a plurality of entries, each entry comprising a value and a flag, the microprocessor configured to: set the flag corresponding to any entry whose value (i) results from a memory load operation that has not yet been retired or cancelled, or (ii) results from a calculation that was derived from a register file entry whose corresponding flag was set; and clear the flag corresponding to any entry when the operation that generated the entry's value is retired; and a memory unit that is configured to hold any memory load operation that uses an address whose value is calculated based on a register file entry whose flag is set, unless all previous instructions have been retired or cancelled.
a register file comprising a plurality of entries, each entry comprising a value and a flag, the microprocessor configured to: set the flag corresponding to any entry whose value (i) results from a memory load operation that has not yet been retired or cancelled, or (ii) results from a calculation that was derived from a register file entry whose corresponding flag was set; and clear the flag corresponding to any entry when the operation that generated the entry's value is retired; and
set the flag corresponding to any entry whose value (i) results from a memory load operation that has not yet been retired or cancelled, or (ii) results from a calculation that was derived from a register file entry whose corresponding flag was set; and
clear the flag corresponding to any entry when the operation that generated the entry's value is retired; and
a memory unit that is configured to hold any memory load operation that uses an address whose value is calculated based on a register file entry whose flag is set, unless all previous instructions have been retired or cancelled.
The microprocessor of claim 1 , wherein setting a flag marks its corresponding entry as pending.
The microprocessor of claim 1 , wherein the memory unit continues a held memory load operation when all previous instructions have been retired.
The microprocessor of claim 1 , wherein the memory unit cancels a held memory load operation when all previous instructions have been cancelled.
The microprocessor of claim 1 , wherein the register file is also configured to invalidate any entry when the operation that generated the entry's value is cancelled.
The microprocessor of claim 1 , wherein the microprocessor tracks whether there are any unresolved branches, and the register file is also configured to clear all flags in the register file when there are no unresolved branches.
The microprocessor of claim 1 , wherein the microprocessor tracks whether there are any unresolved conditional loads, and register file is also configured to clear all flags in the register file when there are no unresolved conditional loads.
The microprocessor of claim 1 , wherein the microprocessor tracks a youngest parent branch or conditional load for each instruction, and holds execution of speculative memory loads that depend on one another while the youngest parent branch or conditional load has yet to resolve.
The microprocessor of claim 8 , wherein store-to-load forwarding that is internal to the microprocessor is permitted to execute, even when a speculative load operation depends on a previous speculative store operation while the youngest parent branch or conditional load has yet to resolve.
The microprocessor of claim 1 , wherein the microprocessor tracks branch state for each instruction, and updates the flag corresponding to entries modified by an instruction based on the branch state for the instruction.
The microprocessor of claim 8 , wherein updates to a branch target cache are deferred until after a branch instruction has retired.
The microprocessor of claim 1 , further comprising a mode bit that controls whether memory load operations are held based on register file flags.
A method, implemented at a microprocessor that includes (i) a register file comprising a plurality of entries, each entry comprising a value and a flag, and (ii) a memory unit, the method comprising: setting the flag corresponding to any entry whose value (i) results from a memory load operation that has not yet been retired or cancelled, or (ii) results from a calculation that was derived from a register file entry whose corresponding flag was set; clearing the flag corresponding to any entry when the operation that generated the entry's value is retired; and holding, in the memory unit, any memory load operation that uses an address whose value is calculated based on a register file entry whose flag is set, unless all previous instructions have been retired or cancelled.
setting the flag corresponding to any entry whose value (i) results from a memory load operation that has not yet been retired or cancelled, or (ii) results from a calculation that was derived from a register file entry whose corresponding flag was set;
clearing the flag corresponding to any entry when the operation that generated the entry's value is retired; and
holding, in the memory unit, any memory load operation that uses an address whose value is calculated based on a register file entry whose flag is set, unless all previous instructions have been retired or cancelled.
The method of claim 13 , wherein setting a flag marks its corresponding entry as pending.
The method of claim 13 , further comprising continuing a held memory load operation when all previous instructions have been retired.
The method of claim 13 , further comprising canceling a held memory load operation when all previous instructions have been cancelled.
The method of claim 13 , further comprising invalidating any register file entry when the operation that generated the entry's value is cancelled.
The method of claim 13 , further comprising: tracking whether there are any unresolved branches; and clearing all flags in the register file when there are no unresolved branches.
tracking whether there are any unresolved branches; and
clearing all flags in the register file when there are no unresolved branches.
The method of claim 13 , further comprising: tracking whether there are any unresolved conditional loads, and clearing all flags in the register file when there are no unresolved conditional loads.
tracking whether there are any unresolved conditional loads, and
clearing all flags in the register file when there are no unresolved conditional loads.
A processing unit comprising (i) a register file that includes a plurality of entries that each comprise a value and a flag, (ii) a memory unit, and (iii) control logic that configures the processing unit to: set the flag corresponding to any entry whose value (i) results from a memory load operation that has not yet been retired or cancelled, or (ii) results from a calculation that was derived from a register file entry whose corresponding flag was set; clear the flag corresponding to any entry when the operation that generated the entry's value is retired; and hold, in the memory unit, any memory load operation that uses an address whose value is calculated based on a register file entry whose flag is set, unless all previous instructions have been retired or cancelled.
set the flag corresponding to any entry whose value (i) results from a memory load operation that has not yet been retired or cancelled, or (ii) results from a calculation that was derived from a register file entry whose corresponding flag was set;
hold, in the memory unit, any memory load operation that uses an address whose value is calculated based on a register file entry whose flag is set, unless all previous instructions have been retired or cancelled.
Ref US20080046692A1: Claims:
A method of controlling instruction execution, comprising: determining a first delay value for a first set of one or more instructions; delaying execution of the first set of one or more instructions based on the first delay; determining a second delay value for a second set of one or more instructions; and delaying execution of the second set of one or more instructions based on the second delay;
determining a first delay value for a first set of one or more instructions;
delaying execution of the first set of one or more instructions based on the first delay;
determining a second delay value for a second set of one or more instructions; and
delaying execution of the second set of one or more instructions based on the second delay;
The method of claim 1 , further comprising associating individual ones of the delay values with the corresponding set of one or more instructions.
The method of claim 2 , wherein associating individual ones of the delay values with the corresponding set of one or more instructions comprises tagging each set of one or more instructions with the corresponding delay value.
The method of claim 1 , wherein the delay values are determined during at least one of code compile time, code load time, and code run time.
The method of claim 1 , wherein the delay values are determined based on an application associated with the corresponding set of instructions.
The method of claim 5 , wherein the delay values are determined based on processor resources available to the corresponding application.
The method of claim 1 , wherein the delay values are determined based on processor resources available to a corresponding application.
The method of claim 1 , wherein determining the delay values comprises: maintaining a history of speculative instruction execution; and determining the delay values based on the history of speculative instruction execution.
maintaining a history of speculative instruction execution; and
determining the delay values based on the history of speculative instruction execution.
The method of claim 8 , wherein maintaining a history of speculative instruction execution comprises tracking occurrences of execution pipeline flushes.
The method of claim 1 , wherein the delay values indicate at least one of full-speculative instruction execution, non-speculative instruction execution, full-speculative instruction execution after a number of instruction processing delay cycles, and partially-speculative instruction execution.
The method of claim 10 , wherein partially-speculative instruction execution comprises halting execution of each instruction at a specified stage until the corresponding instruction is committed.
The method of claim 1 , wherein determining the delay values comprises: processing individual ones of the sets of one or more instructions to ascertain the corresponding delay value; and directing storage of the delay values.
processing individual ones of the sets of one or more instructions to ascertain the corresponding delay value; and
directing storage of the delay values.
The method of claim 12 , wherein delaying execution of individual ones of the sets of one or more instructions based on the corresponding delay value comprises: retrieving the delay values from the register; delaying execution of individual ones of the sets of one or more instructions based on the corresponding retrieved delay value; and directing storage of results of executing the sets of instructions.
retrieving the delay values from the register;
delaying execution of individual ones of the sets of one or more instructions based on the corresponding retrieved delay value; and
directing storage of results of executing the sets of instructions.
The method of claim 13 , wherein directing storage of results of executing the sets of instructions comprises temporarily storing results from uncommitted instructions associated with one or more of the sets of instructions.
The method of claim 14 , further comprising updating the architected state with results associated with at least one of the sets of one or more instructions that are committed.
The method of claim 14 , further comprising clearing the results associated with uncommitted instructions in response to an execution pipeline flush condition.
The method of claim 16 , wherein the execution pipeline flush condition corresponds to at least one of a branch misprediction error, an exception, a trap, an interrupt, and a fault.
A processing apparatus, comprising: a delay determination unit configured to determine a first delay value for a first set of one or more instructions and a second delay value for a second set of one or more instructions; and a processing unit configured to delay execution of the first set of one or more instructions based on the first delay and delay execution of the second set of one or more instructions based on the second delay.
a delay determination unit configured to determine a first delay value for a first set of one or more instructions and a second delay value for a second set of one or more instructions; and
a processing unit configured to delay execution of the first set of one or more instructions based on the first delay and delay execution of the second set of one or more instructions based on the second delay.
The processing apparatus of claim 18 , wherein the processing unit is further configured to associate individual ones of the delay values with the corresponding set of one or more instructions.
The processing apparatus of claim 19 , wherein the processing unit is configured to associate individual ones of the delay values with the corresponding set of one or more instructions by tagging each set of one or more instructions with the corresponding delay value.
The processing apparatus of claim 18 , wherein the delay determination unit is configured to determine the delay values during at least one of code compile time, code load time, and code run time.
The processing apparatus of claim 18 , wherein the delay determination unit is configured to determine the delay values based on an application associated with the corresponding set of one or more instructions.
The processing apparatus of claim 22 , wherein the delay determination unit is configured to determine the delay values based on processor resources available to the corresponding application.
The processing apparatus of claim 18 , wherein the delay determination unit is configured to determine the delay values based on processor resources available to a corresponding application.
The processing apparatus of claim 18 , wherein the delay determination unit is configured to determine the delay values by maintaining a history of speculative instruction execution and determining the delay values based on the history of speculative instruction execution.
The processing apparatus of claim 25 , wherein the delay determination unit is configured to maintain a history of speculative instruction execution by tracking occurrences of execution pipeline flushes.
The processing apparatus of claim 18 , wherein the delay values indicate at least one of full-speculative instruction execution, non-speculative instruction execution, full-speculative instruction execution after a number of instruction processing delay cycles, and partially-speculative instruction execution.
The processing apparatus of claim 27 , wherein partially-speculative instruction execution comprises halting execution of each instruction at a specified stage until the corresponding instruction is committed.
The processing apparatus of claim 18 , wherein the delay determination unit is configured to determine the delay values by processing individual ones of the sets of one or more instructions to ascertain the corresponding delay value and directing storage of the values in a register.
The processing apparatus of claim 29 , wherein the processing unit is configured to delay execution of individual ones of the sets of one or more instructions based on the corresponding delay value by retrieving the delay values from the register, delaying execution of individual ones of the sets of one or more instructions based on the corresponding retrieved delay value and directing storage of results of executing the sets of instructions.
The processing apparatus of claim 30 , wherein the processing unit is configured to direct storage of results of executing the sets of instructions by temporarily storing results of uncommitted instructions associated with one or more of the sets of instructions.
The processing apparatus of claim 31 , wherein the processing unit is further configured to update the architected state with the results associated with at least one of the sets of one or more instructions that are committed.
The processing apparatus of claim 31 , wherein the processing unit is further configured to clear the results associated with uncommitted instructions in response to an execution pipeline flush condition.
The processing apparatus of claim 33 , wherein the execution pipeline flush condition corresponds to at least one of a branch misprediction error, an exception, a trap, an interrupt, and a fault.
A method of imposing instruction execution delay in a coprocessor, comprising: delaying execution of incoming instructions according to a delay value received from an associated processor; and changing an amount of delay imposed on subsequent incoming instructions responsive to receiving a new delay value from the associated processor.
delaying execution of incoming instructions according to a delay value received from an associated processor; and
changing an amount of delay imposed on subsequent incoming instructions responsive to receiving a new delay value from the associated processor.
A computer program product for altering instruction execution delay in a processor, comprising: program code for determining a first delay value for a first set of one or more instructions and a second delay value for a second set of one or more instructions based on one or more applications executed by the processor; and program code for providing the delay values to the processor.
program code for determining a first delay value for a first set of one or more instructions and a second delay value for a second set of one or more instructions based on one or more applications executed by the processor; and
program code for providing the delay values to the processor.
Ref US20180323960A1: Claims:
A method of reducing leakage of side-channel information in a communication channel, comprising: initializing a timer circuit to denote an elapsed time interval of predetermined duration responsive to a function call by an initiator circuit; executing a selected cryptographic function upon input data to generate output data; temporarily storing the output data in a memory location prior to a conclusion of the elapsed time interval; receiving a notification from the timer circuit responsive to the conclusion of the elapsed time interval; and transferring the output data from the memory to the initiator circuit responsive to the notification from the timer circuit.
initializing a timer circuit to denote an elapsed time interval of predetermined duration responsive to a function call by an initiator circuit;
executing a selected cryptographic function upon input data to generate output data;
temporarily storing the output data in a memory location prior to a conclusion of the elapsed time interval;
receiving a notification from the timer circuit responsive to the conclusion of the elapsed time interval; and
transferring the output data from the memory to the initiator circuit responsive to the notification from the timer circuit.
The method of claim 1 , wherein the input data is a first set of input data, the output data is a first set of output data and a crypto engine circuit generates the first set of output data over a first interval of time having a first duration less than the predetermined duration, and wherein the initializing, using, temporarily storing, receiving and transferring steps are repeated for a different, second set of input data to generate a second set of output data over a second interv
[Truncated to input limit]