Office Action 2: Notice of Allowance (2025-04-30)

CLAIMS:
IN THE CLAIMS:

Please find below a listing of all pending claims. The statuses of the claims are set forth in parentheses. For those currently amended claims, underlined emphasis indicates insertions and emphasis (and/or double brackets) indicates deletions.

1\. (Currently Amended) A wiring board comprising:
a first interconnect structure including a plurality of first interconnect layers, and a plurality of insulating layers having a photosensitive resin as a main component thereof; and
an encapsulating resin layer having a non-photosensitive thermosetting resin as a main component thereof, laminated on an uppermost first insulating layer of the plurality of first insulating layers, wherein:
an uppermost first interconnect layer of the plurality of first interconnect layers includes a pad protruding from the uppermost first insulating layer,
the encapsulating resin layer exposes an upper surface of the pad, and covers at least a portion of a side surface of the pad, and at least a portion of side surfaces of the plurality of first insulating layers,
a thickness of the pad from an upper surface of the first interconnect structure to the upper surface of the pad is greater than or equal to a thickness of the encapsulating resin layer from the upper surface of the first interconnect structure to an upper surface of the encapsulating resin layer,the encapsulating resin layer fills a slit extending from an upper surface of the uppermost first insulating layer and stops at an interface between a lower surface of the uppermost first insulating layer and an upper surface of a second uppermost first insulating layer adjacent to the uppermost first insulating layer, andSVG {EMBED HERE} 0.1130.04
the pad is configured to receive a semiconductor chip to be mounted thereon.

2\. (Original) The wiring board as claimed in claim 1, wherein the encapsulating resin layer covers an entirety of the side surfaces of the plurality of first insulating layers.

3\. (Canceled)

4\. (Currently Amended) The wiring board as claimed in claim \[\[3\]\] 1, wherein the slit surrounds an area where the semiconductor chip is to be mounted.

5\. (Original) The wiring board as claimed in claim 1, further comprising:
a second interconnect structure including a second interconnect layer, and a second insulating layer having a non-photosensitive thermosetting resin as a main component thereof, wherein the first interconnect structure is laminated on the second interconnect structure, and
the encapsulating resin layer covers an upper surface of the second interconnect structure.

6\. (Currently Amended) The wiring board as claimed in claim 5, wherein \[\[a\]\] the thickness of the encapsulating resin layer is greater than a thickness of the second insulating layer from a lower surface of the second insulating layer to an upper surface of the second insulating layer.

7\. (Original) The wiring board as claimed in claim 5, wherein the second interconnect layer of the second interconnect structure is exposed at a lower surface of the second insulating layer,
the second interconnect structure includes a via interconnect penetrating the second insulating layer and electrically connecting to the second interconnect layer, and
a lowermost first interconnect layer of the plurality of first interconnect layers of the first interconnect structure is directly bonded to a top end surface of the via interconnect through a seed layer.

8\. (Currently Amended) The wiring board as claimed in claim 5, wherein a thermal expansion coefficient of the encapsulating resin layer is lower than a thermal expansion coefficient of each first insulating layer of the plurality of first insulating layers, and2

the thermal expansion coefficient of the encapsulating resin layer is equal to a thermal expansion coefficient of the second insulating layer.

9\. (Original) A semiconductor device comprising:
a base board;
the wiring board according to claim 1, mounted on the base board; and
the semiconductor chip mounted on the wiring board.

10\. (New) The wiring board as claimed in claim 1, further comprising:
a second interconnect structure provided on a lower surface of the first interconnect structure, wherein:
the second interconnect structure includes low-density interconnect layers having an interconnect density lower than an interconnect density of each of high-density interconnect layers of the first interconnect structure,
the encapsulating resin layer is provided on an upper surface of the second interconnect structure so as to cover the upper surface and a side surface of the first interconnect structure, and
the encapsulating resin layer surrounds the first interconnect structure in a plan view viewed from above in a direction perpendicular to the upper surface of the first interconnect structure.3

OFFICE ACTION:
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to an Office action mailed on 01/30/2025 (01-30-25 OA), the Applicant substantively amended claims 1, 6 and 8 and added new claim 10 on 04/15/2025 (04-15-25 Response).
The Applicant also amended the title in the 04-15-25 Response.
Currently, claims 1, 2 and 4-10 are pending.
Information Disclosure Statement
The Applicant submitted an information disclosure statement (IDS) on 02/12/2025 (02-12-25 IDS) after the 01-30-25 OA.  Since the Applicant has met the provisions of 37 CFR 1.97, the 02-12-25 IDS is in compliance and is being considered by the examiner.
Response to Arguments
Applicant's amendment to the title has overcome the objection to the Specification set forth on page 2 under line item number 1 of the 01-30-25 OA.
Applicant's amendments to claim 8 have overcome the 35 U.S.C. 112(b) rejection of claim 8 set forth starting on page 3 under line item number 2 of the 01-30-25 OA.
Applicant's amendments to the independent claim 1 have overcome the 35 U.S.C. 102(a)(1) rejection of claims 1-9 as being anticipated by Baek set forth starting on page 5 under line item number 3 of the 01-30-25 OA.
Allowable Subject Matter
Claims 1, 2 and 4-10 are allowed.
The following is an examiner’s statement of reasons for allowance:
Independent claim 1 is allowed, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 1, a thickness of the pad from an upper surface of the first interconnect structure to the upper surface of the pad is greater than or equal to a thickness of the encapsulating resin layer from the upper surface of the first interconnect structure to an upper surface of the encapsulating resin layer,
the encapsulating resin layer fills a slit extending from an upper surface of the uppermost first insulating layer and stops at an interface between a lower surface of the uppermost first insulating layer and an upper surface of a second uppermost first insulating layer adjacent to the uppermost first insulating layer.
Claims 2, 4-8 and 10 are allowed, because they depend from the allowed independent claim 1.
Independent claim 9 is allowed, because it refers to the allowed independent claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee.  Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion

APPLICANT REBUTTAL: REMARKS
Favorable reconsideration of this application is respectfully requested in view of the foregoing amendments and the following remarks.
Claim 3 is canceled without prejudice or disclaimer of the subject matter contained therein.  New claim 10 is added.  Claims 1, 2, and 4-10 are pending in the present application, of which claim 1 is independent.  Claims 1, 4, 6, and 8 are amended by the present response.
Noted - Priority Document Received by USPTO
The indication that the certified copy of the priority document has been received by the USPTO is noted with appreciation.
Noted - Drawings Approved
The indication that the Drawings submitted on August 3, 2022 have been approved is noted with appreciation.
Noted - IDS Considered
The indication that the Information Disclosure Statement (IDS) as filed on August 3, 2022 and references listed therein have been considered is noted with appreciation.
An IDS was filed on February 12, 2025.  Official consideration of this IDS is hereby respectfully requested.
Objection to the Specification
The title of the invention is objected to as not being descriptive.
By the foregoing amendments, the title of the invention has been amended to be more clearly indicative of the invention to which the claims are directed.  Accordingly, withdrawal of the objection to the specification is respectfully requested.
Claim Rejection Under 35 U.S.C. §112
Claim 8 is rejected under 35 U.S.C. §112(b) as being indefinite.
By the foregoing amendments, claim 8 is amended to delete the term “approximately”, so as to more particularly point out and distinctly claim its subject matter.  Accordingly, withdrawal of the rejection is respectfully requested.
Claim Rejection Under 35 U.S.C. §102
Claims 1-9 are rejected under 35 U.S.C. §102(a)(1) as being anticipated by Baek et al. (US 2018/0053732 A1, hereinafter “Baek”).
Independent Claim
:
As an example, independent claim 1 is amended to recite, among other things, “a thickness of the pad from an upper surface of the first interconnect structure to the upper surface of the pad is greater than or equal to a thickness of the encapsulating resin layer from the upper surface of the first interconnect structure to an upper surface of the encapsulating resin layer” and “the encapsulating resin layer fills a slit extending from an upper surface of the uppermost first insulating layer and stops at an interface between a lower surface of the uppermost first insulating layer and an upper surface of a second uppermost first insulating layer adjacent to the uppermost first insulating layer”.  As will be explained below, these features of amended independent claim 1 are distinctions over Baek.
The Office Action at pages 5-6 alleges that Baek at Fig. 14 discloses a semiconductor package having all of the claimed features of independent claim 1.  However, a redistribution layer 112c has a thickness is smaller than a thickness of an encapsulant 130.  In other words, the thickness of the redistribution layer 112c is not greater than or equal to the thickness of the encapsulant.  Further, the encapsulant 130 fills a slit SL as indicated in annotated Fig. 14 of Baek, but the slit SL extends through both a second insulating layer 111b and a first insulating layer 111a illustrated in Fig. 9 of Baek.  That is, the slit SL extends from an upper surface of the second insulating layer 111b, but the slit SL does not stop at an interface between a lower surface of the insulating layer 111b and an upper surface of the first insulating layer 111a.
Hence, Baek does not disclose, among other things, “a thickness of the pad from an upper surface of the first interconnect structure to the upper surface of the pad is greater than or equal to a thickness of the encapsulating resin layer from the upper surface of the first interconnect structure to an upper surface of the encapsulating resin layer” and “the encapsulating resin layer fills a slit extending from an upper surface of the uppermost first insulating layer and stops at an interface between a lower surface of the uppermost first insulating layer and an upper surface of a second uppermost first insulating layer adjacent to the uppermost first insulating layer”, as is recited in amended independent claim 1.
Anticipation requires the presence in a single prior art reference disclosure of each and every element of the claimed invention, arranged as in the claim.  In view of the distinctions of amended independent claim 1 noted above, at least one claimed element is not present in Baek.  Hence, Baek does not anticipate amended independent claim 1.
Again, claim 3 is canceled.  Claims 2 and 4-9 ultimately depend from amended independent claim 1, and so at least similarly distinguish over Baek.  Hence, Baek does not anticipate claims 2 and 4-9.
In view of the foregoing discussion, the rejection of claims 1, 2, and 4-9 is overcome.  Accordingly, withdrawal of the rejection is respectfully requested.
Unaddressed Features
Inasmuch as the dependent claims are allowable for at least the same reasons as the claim(s) from which they depend, further remarks regarding the asserted relationship between any of the claims and the cited references are not necessary in view of their allowability.  Applicant’s silence as to the Office Action’s comments is not indicative of being in acquiescence to the stated grounds of rejection.
New Claims
Again, new claim 10 is added.  As for new claim 10, not argued above, the following comments are provided.
New claim 10 depends from amended independent claim 1, and so at least similarly distinguishes over the art of record.
Conclusion


CITED REFERENCE SUMMARIES: Ref US20170352628A: [content unavailable]
Ref JP2017220543: Claims:
A single first insulating layer made of a non-photosensitive resin with a reinforcing material; A laminate in which a wiring layer and an insulating layer are laminated on one surface of the first insulating layer; An external connection pad formed on the other surface of the first insulating layer; A through-wiring penetrating the first insulating layer, The central position of the reinforcing material is unevenly distributed on one surface side of the first insulating layer from the central position in the thickness direction of the first insulating layer, One end surface of the through wiring is exposed from one surface of the first insulating layer and connected to the wiring layer, The other end surface of the through wiring is exposed at a position recessed from the other surface of the first insulating layer, and a first recess is formed in which the other end surface of the through wiring forms a bottom surface and the first insulating layer forms an inner surface. And Only the external connection pad is formed on the other surface of the first insulating layer, The external connection pad is formed along the bottom surface and the inner surface of the first recess, and extends from the inner surface to the other surface of the first insulating layer located around the first recess, A wiring board in which a second recess recessed toward the through wiring is formed inside a portion of the external connection pad that extends to the other surface of the first insulating layer.
The wiring board according to claim 1, wherein one surface of the first insulating layer and one end surface of the through wiring are flush with each other.
The insulating layer constituting the laminate is made of a photosensitive resin, The wiring board according to claim 1, wherein the wiring layer constituting the laminated body is a fine wiring layer.
4. The wiring board according to claim 1, wherein one surface of the first insulating layer is smoother than the other surface of the first insulating layer. 5.
The wiring board according to any one of claims 1 to 4, wherein a center position of the reinforcing material is located at a center in a thickness direction of a portion where the first insulating layer and the stacked body are combined.
6. The wiring according to claim 1, wherein a side surface of the through wiring, an inner side surface of the first recess of the first insulating layer, and the other surface of the first insulating layer are roughened surfaces. substrate.
The wiring board according to any one of claims 1 to 6, A semiconductor chip mounted on the laminate and connected to the uppermost wiring layer of the laminate; And a sealing resin which is formed on the stacked body and seals the semiconductor chip.
A step of laminating a metal layer and a through wiring on one surface of the support; A single-layer first insulating layer made of a non-photosensitive resin provided with a reinforcing material is formed on one surface of the support so as to cover the side surface of the metal layer and one end surface and side surface of the through wiring. Process, One surface of the first insulating layer is polished to expose one end surface of the through wiring from the one surface of the first insulating layer, and the central position of the reinforcing material is set in the thickness direction of the first insulating layer. A step of unevenly distributing on one surface side of the first insulating layer with respect to the center position of Forming a laminate in which a wiring layer and an insulating layer are laminated on one surface of the first insulating layer; Removing the support; The metal layer is removed, the other end surface of the through wiring is exposed at a position recessed from the other surface of the first insulating layer, the other end surface of the through wiring forms a bottom surface, and the first insulating layer forms an inner surface. Forming a first recess formed; Forming an external connection pad on the other surface of the first insulating layer, In the step of forming the external connection pad, Only the external connection pad is formed on the other surface of the first insulating layer, The external connection pad is formed along the bottom surface and the inner surface of the first recess, and extends from the inner surface to the other surface of the first insulating layer located around the first recess, A method of manufacturing a wiring board, wherein a second recess recessed toward the through wiring is formed inside a portion of the external connection pad that extends to the other surface of the first insulating layer.
Between the step of laminating the through wiring and the step of forming the first insulating layer on one surface of the support, Roughening one surface of the support, the side surface of the metal layer, and one end surface and the side surface of the through wiring, The wiring board according to claim 8, wherein in the step of removing the support, the unevenness formed on one surface of the support in the roughening step is transferred to the other surface of the first insulating layer. Production method.
In the manufacturing method of the wiring board according to claim 8 or 9, During the step of removing the support from the step of forming the laminate, Mounting a semiconductor chip connected to the uppermost wiring layer of the laminate on the laminate; Forming a sealing resin for sealing the semiconductor chip on the stacked body.