Office Action 1: Non-Final Rejection (2025-01-30)
Rejection types: 102 - Lack of Novelty, 112 - Written Description/Enablement

CLAIMS:
CLAIMS What is claimed is:
1\. A wiring board comprising: a first interconnect structure including a plurality of first interconnect layers, and a plurality of insulating layers having a photosensitive resin as a main component thereof; and an encapsulating resin layer having a non-photosensitive thermosetting resin as a main component thereof, laminated on an uppermost first insulating layer of the plurality of first insulating layers, wherein an uppermost first interconnect layer of the plurality of first interconnect layers includes a pad protruding from the uppermost first insulating layer, the encapsulating resin layer exposes an upper surface of the pad, and covers at least a portion of a side surface of the pad, and at least a portion of side surfaces of the plurality of first insulating layers, and the pad is configured to receive a semiconductor chip to be mounted thereon.
2\. The wiring board as claimed in claim 1, wherein the encapsulating resin layer covers an entirety of the side surfaces of the plurality of first insulating layers.
3\. The wiring board as claimed in claim 1, wherein a slit, filled with the encapsulating resin layer, is formed in an upper surface of the uppermost first insulating layer.
4\. The wiring board as claimed in claim 3, wherein the slit surrounds an area where the semiconductor chip is to be mounted.
5\. The wiring board as claimed in claim 1, further comprising: a second interconnect structure including a second interconnect layer, and a second insulating layer having a non-photosensitive thermosetting resin as a main component thereof, wherein the first interconnect structure is laminated on the second interconnect structure, and the encapsulating resin layer covers an upper surface of the second interconnect structure.
6\. The wiring board as claimed in claim 5, wherein a thickness of the encapsulating resin layer, from an upper surface of the uppermost first insulating layer to an upper surface of the encapsulating resin layer, is greater than a thickness of the second insulating layer.
7\. The wiring board as claimed in claim 5, wherein the second interconnect layer of the second interconnect structure is exposed at a lower surface of the second insulating layer, the second interconnect structure includes a via interconnect penetrating the second insulating layer and electrically connecting to the second interconnect layer, and a lowermost first interconnect layer of the plurality of first interconnect layers of the first interconnect structure is directly bonded to a top end surface of the via interconnect through a seed layer.
8\. The wiring board as claimed in claim 5, wherein a thermal expansion coefficient of the encapsulating resin layer is lower than a thermal expansion coefficient of each first insulating layer of the plurality of first insulating layers, and the thermal expansion coefficient of the encapsulating resin layer is approximately equal to a thermal expansion coefficient of the second insulating layer.
9\. A semiconductor device comprising: a base board; the wiring board according to claim 1, mounted on the base board; and the semiconductor chip mounted on the wiring board.

OFFICE ACTION:
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Currently, claims 1-8 are pending and examined below.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement (IDS)
The information disclosure statement submitted on 08/03/2022 (08-03-22 IDS) is in compliance with the provisions of 37 CFR 1.97.  Accordingly, the 08-03-22 IDS is being considered by the examiner.
Specification
The specification is objected to, because the title of the invention is not descriptive.  A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:  WIRING BOARD AND SEMICONDUCTOR DEVICE EACH HAVING NON-PHOTOSENSITIVE THERMOSETTING ENCAPSULATING RESIN LAYER OVER FIRST INTERCONNECT PHOTOSENSTIVE RESIN LAYER.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b)  CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA  the applicant regards as the invention.
Section 2173.02.I. of the MPEP provides the following guidance on how pre-issuance claims under examination are construed differently than patented claims:
Patented claims are not given the broadest reasonable interpretation during court proceedings involving infringement and validity, and can be interpreted based on a fully developed prosecution record. While absolute precision is unattainable in patented claims, the definiteness requirement mandates clarity. Nautilus, Inc. v. Biosig Instruments, Inc., 527 U.S. __, 134 S. Ct. 2120, 2129, 110 USPQ2d 1688, 1693 (2014). A court will not find a patented claim indefinite unless the claim interpreted in light of the specification and the prosecution history fails to inform those skilled in the art about the scope of the invention with reasonable certainty. Id. at 1689.
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The Office does not interpret claims when examining patent applications in the same manner as the courts. In re Packard, 751 F.3d 1307, 1312, 110 USPQ2d 1785, 1788 (Fed. Cir. 2014); In re Morris, 127 F.3d 1048, 1054, 44 USPQ2d 1023, 1028 (Fed. Cir. 1997); In re Zletz, 893 F.2d 319, 321-22 (Fed. Cir. 1989). The Office construes claims by giving them their broadest reasonable interpretation during prosecution in an effort to establish a clear record of what the applicant intends to claim. Such claim construction during prosecution may effectively result in a lower threshold for ambiguity than a court's determination. Packard, 751 F.3d at 1323-24, 110 USPQ2d at 1796-97 (Plager, J., concurring). However, applicant has the ability to amend the claims during prosecution to ensure that the meaning of the language is clear and definite prior to issuance or provide a persuasive explanation (with evidence as necessary) that a person of ordinary skill in the art would not consider the claim language unclear. In re Buszard, 504 F.3d 1364, 1366 (Fed. Cir. 2007)( claims are given their broadest reasonable interpretation during prosecution to facilitate sharpening and clarifying the claims at the application stage); see also In re Yamamoto, 740 F.2d 1569, 1571 (Fed. Cir. 1984); In re Zletz, 893 F.2d 319, 322, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989).
Here, claim 8 is indefinite, because the term approximately in approximately equal is a relative and subject term that casts a zone of uncertainty around the term equal.   The term has not been defined by the Applicant, so its plain meaning controls. However, its dictionary meaning is also relative and the term has not attained a customary meaning so as to clearly define the metes and bounds of what would constitute something to be approximate.  What one would consider to be Approximately the same may not be to another.
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2018/0053732 A1 to Baek et al. (Baek).
Fig. 14 of Baek has been annotated to support the rejection below:
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Regarding independent claim 1, Baek teaches a wiring board (see Fig. 14 for example) comprising:
a first interconnect structure 110a (para [0087] - The first connection member 110) including a plurality of first interconnect layers 113a, 113b (para [0095] - signal vias 113a and 113b may be exposed.), and a plurality of insulating layers 111a, 111b (para [0090] - For example, a material including an inorganic filler and an insulating resin may be used as materials of the insulating layers 111a and 111b. For example...a resin including a photoimagable dielectric (PID) resin...may be used.) having a photosensitive resin (PID) as a main component thereof; and
an encapsulating resin layer 130 (para [0094] - For example, an insulating material may be used in the encapsulant 130. In this case, the insulating material may be a thermosetting resin such as an epoxy resin...) having a non-photosensitive thermosetting resin as a main component thereof, laminated on an uppermost first insulating layer 111a of the plurality of first insulating layers 111a, 111b, wherein
an uppermost first interconnect layer 113b of the plurality of first interconnect layers includes a pad 112c (para [0120] discloses distribution layer 112c) protruding from the uppermost first insulating layer 111a,
the encapsulating resin layer 130 exposes an upper surface of the pad 112c, and covers at least a portion of a side surface of the pad 112c (see Fig. 14), and at least a portion of side surfaces of the plurality of first insulating layers 111a, 111b, and
the pad 112c is configured to receive a semiconductor chip 240 to be mounted thereon (Fig. 14 shows a memory package with memory 240 electrically connected to the pad 112c).
Regarding claim 2, Baek teaches the encapsulating resin layer 130 that covers an entirety of the side surfaces of the plurality of first insulating layers 111a, 111b.
Regarding claim 3, Baek teaches a slit SL, filled with the encapsulating resin layer 130, is formed in an upper surface of the uppermost first insulating layer 111a.
Regarding claim 4, Baek teaches the slit SL that surrounds an area where the semiconductor chip 240 is to be mounted.
Regarding claim 5, Baek teaches a second interconnect structure 140, 150 (para [0083] - second connection member 140; para [0100] - Alternatively, an insulating resin that may not include a core material, but include a filler, for example, ABF, including an inorganic filler and an epoxy resin, may be used as the material of the passivation layer 150.) including a second interconnect layer 142 (para [0081] - a redistribution layer 142) or 142, 160 (para [0101] - An under-bump metal layer 160), and a second insulating layer 150, 141 having a non-photosensitive thermosetting resin 150 (ABF, including an inorganic filler and an epoxy resin) as a main component thereof, wherein
the first interconnect structure 110 that is laminated on the second interconnect structure 140, 150, and
the encapsulating resin layer 130 covers an upper surface of the second interconnect structure 140, 150.
Regarding claim 6, Baek teaches a thickness of the encapsulating resin layer 130, from an upper surface of the uppermost first insulating layer 111a to an upper surface of the encapsulating resin layer 130, is greater than a thickness of the second insulating layer 150 (see Fig. 14).
Regarding claim 7, Baek teaches the second interconnect layer 142, 160 of the second interconnect structure 140, 150 that is exposed at a lower surface of the second insulating layer 150, 141,
the second interconnect structure 140, 150 includes a via interconnect 143 penetrating the second insulating layer 150, 141 and electrically connecting to the second interconnect layer 142, 160, and
a lowermost first interconnect layer 113a of the plurality of first interconnect layers 113a, 113b is directed bonded to a top end surface of the via interconnect 143 through a seed layer 114a (para [0120] discloses redistribution layer 114a.).
Regarding claim 8, in light of the indefiniteness issue present in claim 8, Baek teaches a thermal expansion coefficient of the encapsulating resin layer 130 is lower than a thermal expansion coefficient of each first insulating layer of the plurality of first insulating layers 111a, 111b (Since Baek teaches all of the structural limitations claim 8, the wiring board of Baek is reasonably capable of having the property or characteristics as claimed above.), and
the thermal expansion coefficient of the encapsulating resin layer 130 is approximately equal to a thermal expansion coefficient of the second insulating layer 150, 141 (para [0100] - In this case, the passivation layer 150 may have a relatively low coefficient of thermal expansion (CTE), and may be utilized to control the warpage.).
Regarding independent claim 9, Baek teaches a base board 2500 (para [0066] - main board 2500; see Fig. 14; see also Figs. 5, 6 and 8 for example);
the wiring board according to claim 1 (see rejection of claim 1 as above), mounted on the base board 2500 (para [0102] - For example, the fan-out semiconductor package 100A may be mounted on the main board of the electronic device...); and
the semiconductor chip 240 mounted on the wiring board.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2018/0174994 A1 to Choi et al.
Pub. No. US 2015/0084206 A1 to Lin
Pub. No. US 2014/0102777 A1 to Chen et al.


NEXT OFFICE ACTION: Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to an Office action mailed on 01/30/2025 (01-30-25 OA), the Applicant substantively amended claims 1, 6 and 8 and added new claim 10 on 04/15/2025 (04-15-25 Response).
The Applicant also amended the title in the 04-15-25 Response.
Currently, claims 1, 2 and 4-10 are pending.
Information Disclosure Statement
The Applicant submitted an information disclosure statement (IDS) on 02/12/2025 (02-12-25 IDS) after the 01-30-25 OA.  Since the Applicant has met the provisions of 37 CFR 1.97, the 02-12-25 IDS is in compliance and is being considered by the examiner.
Response to Arguments
Applicant's amendment to the title has overcome the objection to the Specification set forth on page 2 under line item number 1 of the 01-30-25 OA.
Applicant's amendments to claim 8 have overcome the 35 U.S.C. 112(b) rejection of claim 8 set forth starting on page 3 under line item number 2 of the 01-30-25 OA.
Applicant's amendments to the independent claim 1 have overcome the 35 U.S.C. 102(a)(1) rejection of claims 1-9 as being anticipated by Baek set forth starting on page 5 under line item number 3 of the 01-30-25 OA.
Allowable Subject Matter
Claims 1, 2 and 4-10 are allowed.
The following is an examiner’s statement of reasons for allowance:
Independent claim 1 is allowed, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 1, a thickness of the pad from an upper surface of the first interconnect structure to the upper surface of the pad is greater than or equal to a thickness of the encapsulating resin layer from the upper surface of the first interconnect structure to an upper surface of the encapsulating resin layer,
the encapsulating resin layer fills a slit extending from an upper surface of the uppermost first insulating layer and stops at an interface between a lower surface of the uppermost first insulating layer and an upper surface of a second uppermost first insulating layer adjacent to the uppermost first insulating layer.
Claims 2, 4-8 and 10 are allowed, because they depend from the allowed independent claim 1.
Independent claim 9 is allowed, because it refers to the allowed independent claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee.  Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion

CITED REFERENCE SUMMARIES: Ref US20180053732A1: Claims:
A fan-out semiconductor package, comprising: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface with connection pads disposed thereon and an inactive surface opposite the active surface; an encapsulant encapsulating at least a portion of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip, wherein the first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, the redistribution layer of the first connection member includes a signal pattern and a ground pattern, and the first connection member includes a plurality of dummy vias connected to the ground pattern and surrounding the semiconductor chip.
a first connection member having a through-hole;
a semiconductor chip disposed in the through-hole of the first connection member and having an active surface with connection pads disposed thereon and an inactive surface opposite the active surface;
an encapsulant encapsulating at least a portion of the first connection member and the inactive surface of the semiconductor chip; and
a second connection member disposed on the first connection member and the active surface of the semiconductor chip, wherein the first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, the redistribution layer of the first connection member includes a signal pattern and a ground pattern, and the first connection member includes a plurality of dummy vias connected to the ground pattern and surrounding the semiconductor chip.
the first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip,
the redistribution layer of the first connection member includes a signal pattern and a ground pattern, and
the first connection member includes a plurality of dummy vias connected to the ground pattern and surrounding the semiconductor chip.
The fan-out semiconductor package of claim 1 , further comprising a metal layer disposed on the encapsulant and covering at least a portion of the inactive surface of the semiconductor chip, wherein the metal layer is connected to the plurality of dummy vias.
wherein the metal layer is connected to the plurality of dummy vias.
The fan-out semiconductor package of claim 1 , wherein the first connection member includes a plurality of signal vias connected to the signal pattern.
The fan-out semiconductor package of claim 3 , wherein the plurality of dummy vias are disposed along an outer edge of the first connection member and surround the plurality of signal vias.
The fan-out semiconductor package of claim 3 , wherein the plurality of dummy vias are disposed along an inner edge of the first connection member and are surrounded by the plurality of signal vias.
The fan-out semiconductor package of claim 1 , wherein the plurality of dummy vias are spaced apart from each other by a predetermined interval.
The fan-out semiconductor package of claim 6 , wherein the plurality of dummy vias are connected to each other by a plurality of line vias.
The fan-out semiconductor package of claim 1 , wherein the plurality of dummy vias overlap each other.
The fan-out semiconductor package of claim 3 , further comprising a memory package disposed on the encapsulant and electrically connected to the plurality of signal vias.
The fan-out semiconductor package of claim 1 , wherein the first connection member includes a first insulating layer, a first redistribution layer in contact with the second connection member and embedded in the first insulating layer, and a second redistribution layer disposed on a surface of the first insulating layer opposite a surface of the first insulating layer having the first redistribution layer embedded therein, and the plurality of dummy vias include first dummy vias penetrating through the first insulating layer.
the plurality of dummy vias include first dummy vias penetrating through the first insulating layer.
The fan-out semiconductor package of claim 10 , wherein the first connection member further includes a second insulating layer disposed on the first insulating layer and covering the second redistribution layer and a third redistribution layer disposed on the second insulating layer, and the plurality of dummy vias further include second dummy vias penetrating through the second insulating layer.
the plurality of dummy vias further include second dummy vias penetrating through the second insulating layer.
The fan-out semiconductor package of claim 10 , wherein a distance between the redistribution layer of the second connection member and the first redistribution layer is greater than a distance between the redistribution layer of the second connection member and the connection pad of the semiconductor chip.
The fan-out semiconductor package of claim 1 , wherein the first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer, and the plurality of dummy vias include first and second dummy vias respectively penetrating through the first and second insulating layers.
the plurality of dummy vias include first and second dummy vias respectively penetrating through the first and second insulating layers.
The fan-out semiconductor package of claim 13 , wherein the first connection member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and a fourth redistribution layer disposed on the third insulating layer, and the plurality of dummy vias include first, second, and third dummy vias respectively penetrating through the first, second, and third insulating layers.
the plurality of dummy vias include first, second, and third dummy vias respectively penetrating through the first, second, and third insulating layers.
The fan-out semiconductor package of claim 13 , wherein a thickness of the first insulating layer is greater than a thickness of the second insulating layer.
A fan-out semiconductor package, comprising: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface with connection pads disposed thereon and an inactive surface opposite the active surface; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip, wherein the first connection member includes a plurality of signal vias and a plurality of dummy vias, and the plurality of dummy vias surround the plurality of signal vias or are surrounded by the plurality of signal vias.
a semiconductor chip disposed in the through-hole of the first connection member and having an active surface with connection pads disposed thereon and an inactive surface opposite the active surface; and
a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip, wherein the first connection member includes a plurality of signal vias and a plurality of dummy vias, and the plurality of dummy vias surround the plurality of signal vias or are surrounded by the plurality of signal vias.
the first connection member includes a plurality of signal vias and a plurality of dummy vias, and
the plurality of dummy vias surround the plurality of signal vias or are surrounded by the plurality of signal vias.
Ref US20180174994A1: Claims:
A fan-out semiconductor package comprising: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip, wherein the first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, the second connection member includes a coil pattern layer electrically connected to the connection pads of the semiconductor chip, and at least one of the first connection member and the second connection member includes a first dummy pattern layer.
a first connection member having a through-hole;
a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and
a second connection member disposed on the first connection member and the active surface of the semiconductor chip,
wherein the first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip,
the second connection member includes a coil pattern layer electrically connected to the connection pads of the semiconductor chip, and
at least one of the first connection member and the second connection member includes a first dummy pattern layer.
The fan-out semiconductor package of claim 1 , wherein the first dummy pattern layer is disposed above or below the coil pattern layer.
The fan-out semiconductor package of claim 1 , wherein at least a portion of the first dummy pattern layer is formed in the first connection member.
The fan-out semiconductor package of claim 2 , wherein the first dummy pattern layer is formed directly above or directly below the coil pattern layer.
The fan-out semiconductor package of claim 1 , wherein the first dummy pattern layer is electrically insulated from the coil pattern layer.
The fan-out semiconductor package of claim 1 , wherein the second connection member includes a second dummy pattern layer formed at a central portion of the coil pattern layer.
The fan-out semiconductor package of claim 6 , wherein the second dummy pattern layer is electrically insulated from the coil pattern layer.
The fan-out semiconductor package of claim 1 , wherein the coil pattern layer is formed in only a specific region of the first connection member.
The fan-out semiconductor package of claim 1 , wherein the first connection member includes a first insulating layer, a first redistribution layer in contact with the second connection member and embedded in a first surface of the first insulating layer, and a second redistribution layer disposed on a second surface of the first insulating layer opposing the first surface of the first insulating layer.
The fan-out semiconductor package of claim 9 , wherein the first connection member further includes a second insulating layer disposed on the first insulating layer and covering the second redistribution layer and a third redistribution layer disposed on the second insulating layer.
The fan-out semiconductor package of claim 9 , wherein a lower surface of the first redistribution layer has a step with respect to a lower surface of the first insulating layer.
The fan-out semiconductor package of claim 1 , wherein the first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer.
The fan-out semiconductor package of claim 12 , wherein the first connection member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and a fourth redistribution layer disposed on the third insulating layer.
The fan-out semiconductor package of claim 12 , wherein the first insulating layer has a thickness greater than that of the second insulating layer.
A fan-out semiconductor package comprising: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip, wherein the first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the second connection member includes a coil pattern layer electrically connected to the connection pads of the semiconductor chip and a first dummy pattern layer formed at a central portion of the coil pattern layer.
wherein the first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and
the second connection member includes a coil pattern layer electrically connected to the connection pads of the semiconductor chip and a first dummy pattern layer formed at a central portion of the coil pattern layer.
The fan-out semiconductor package of claim 15 , wherein at least one of the first connection member and the second connection member includes a second dummy pattern layer formed above or below the coil pattern layer.
The fan-out semiconductor package of claim 16 , wherein at least a portion of the second dummy pattern layer is formed in the first connection member.
Ref US20150084206A1: Claims:
A method of making a semiconductor device, comprising: providing a semiconductor die; disposing a first encapsulant over the semiconductor die; forming a first conductive layer including a plurality of first conductive traces over the semiconductor die and the first encapsulant; disposing a second encapsulant over the semiconductor die; and forming a second conductive layer including a plurality of second conductive traces over the first conductive layer and the second encapsulant, wherein a distance between the second conductive traces is greater than a distance between the first conductive traces.
providing a semiconductor die;
disposing a first encapsulant over the semiconductor die;
forming a first conductive layer including a plurality of first conductive traces over the semiconductor die and the first encapsulant;
disposing a second encapsulant over the semiconductor die; and
forming a second conductive layer including a plurality of second conductive traces over the first conductive layer and the second encapsulant, wherein a distance between the second conductive traces is greater than a distance between the first conductive traces.
The method of claim 1 , further including disposing a plurality of conductive vias adjacent to the semiconductor die.
The method of claim 1 , further including disposing a passive device adjacent to the semiconductor die.
The method of claim 1 , further including disposing a plurality of conductive vias adjacent to the first encapsulant.
The method of claim 1 , further including: forming a first insulating layer over the semiconductor die and the first encapsulant; and forming a second insulating layer over the first conductive layer and the second encapsulant.
forming a first insulating layer over the semiconductor die and the first encapsulant; and
forming a second insulating layer over the first conductive layer and the second encapsulant.
The method of claim 5 , further including forming the second insulating layer including a composite material comprising a fiber.
A method of making a semiconductor device, comprising: providing a semiconductor die; forming a first conductive layer including a plurality of first conductive traces over the semiconductor die; providing a build-up interconnect structure including a second conductive layer comprising a plurality of second conductive traces, wherein a distance between the second conductive traces is greater than or similar to a distance between the first conductive traces; and disposing the semiconductor die over the build-up interconnect structure.
forming a first conductive layer including a plurality of first conductive traces over the semiconductor die;
providing a build-up interconnect structure including a second conductive layer comprising a plurality of second conductive traces, wherein a distance between the second conductive traces is greater than or similar to a distance between the first conductive traces; and
disposing the semiconductor die over the build-up interconnect structure.
The method of claim 7 , further including disposing a passive device adjacent to the semiconductor die.
The method of claim 7 , further including disposing a plurality of interconnect structures between the first conductive layer and the build-up interconnect structure.
The method of claim 7 , further including: depositing a first encapsulant over the semiconductor die; disposing a passive device adjacent to the first encapsulant; and depositing a second encapsulant over the first encapsulant and the passive device.
depositing a first encapsulant over the semiconductor die;
disposing a passive device adjacent to the first encapsulant; and
depositing a second encapsulant over the first encapsulant and the passive device.
The method of claim 7 , further including: depositing a first encapsulant over the semiconductor die; and disposing a conductive via adjacent to the first encapsulant.
depositing a first encapsulant over the semiconductor die; and
disposing a conductive via adjacent to the first encapsulant.
The method of claim 7 , further including providing the build-up interconnect structure including an insulating layer.
The method of claim 12 , further including forming the insulating layer of the build-up interconnect structure including a composite material comprising a fiber.
A semiconductor device, comprising: a first interconnect structure including a first conductive layer comprising a plurality of first conductive traces; a second interconnect structure including a second conductive layer comprising a plurality of second conductive traces disposed over the first interconnect structure, wherein a distance between the first conductive traces is greater than or similar to a distance between the second conductive traces; and a first semiconductor die disposed over the second interconnect structure.
a first interconnect structure including a first conductive layer comprising a plurality of first conductive traces;
a second interconnect structure including a second conductive layer comprising a plurality of second conductive traces disposed over the first interconnect structure, wherein a distance between the first conductive traces is greater than or similar to a distance between the second cond
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