Office Action 2: Notice of Allowance (2025-05-07)

CLAIMS:
AMENDMENTS TO THE CLAIMS

This listing of claims will replace all prior versions, and listings of claims in the application.

Listing of Claims:

1\. (Currently Amended) A semiconductor structure, comprising a stacked structure, wherein the stacked structure comprises a plurality of stacked semiconductor dies, and each of the semiconductor dies comprises:

at least one first auxiliary through electrode and a plurality of connection through electrodes
each of the semiconductor dies comprises a first through electrode set and a second through electrode set, each of the through electrode sets comprises the plurality of connection through electrodes, the connection through electrodes in the first through electrode set are first through electrodes, the connection through electrodes in the second through electrode set are second through electrodes; in one of the semiconductor dies, the first through electrodes and the second through electrodes are alternately arranged around the at least one first auxiliary through electrode;
the first through electrodes on each of the semiconductor dies are connected to each other to form a transmission path groups, transmission paths in the transmission path group are first transmission paths;

the second through electrodes on each of the semiconductor dies are connected to each other to form another transmission path group, transmission paths in another transmission path group are second transmission paths;
wherein each of the first transmission paths is a spiral path extending spirally along a first direction; and
each of the second transmission paths is a spiral path extending spirally along a second direction, and the second direction is opposite to the first direction.

2\. (Canceled)

3\. (Currently Amended) The semiconductor structure according to claim 1, wherein
 each of the connection through electrodes in \[\[a\]\] the same first through electrode set are respectively located on different transmission paths; and each of the connection through electrodes in the second through electrode set are respectively located on different transmission paths.

4-7. (Canceled)56

8\. (Currently Amended) The semiconductor structure according to claim \[\[6\]\] 1, wherein each of the semiconductor dies comprise a plurality of first through electrode sets and a plurality of second through electrode sets in a one- to-one correspondence with the plurality of first through electrode sets, each of the first through electrode sets and a corresponding second through electrode set form a through unit, and a plurality of the through units are arranged in an array.

9\. (Currently Amended) The semiconductor structure according to claim \[\[8\]\] 1 wherein each of the transmission paths formed by the corresponding first through electrode set and second through electrode set in each of the semiconductor dies is used for a connection to a same signal source.

10\. (Currently Amended) The semiconductor structure according to claim \[\[6\]\] 1, wherein the first through electrode sets comprises four first through electrodes, the second through electrode sets comprises four second through electrodes, and the four first through electrodes and the four second through electrodes are alternately arranged around one first auxiliary through electrode to form a through unit in a 3x3 array.

11.(Currently Amended) The semiconductor structure according to claim 1, wherein the first auxiliary through electrodes in all of the semiconductor dies are connected together and grounded.

12\. (Canceled)

13\. (Currently Amended) The semiconductor structure according to claim 1, wherein the semiconductor structure comprises a buffer layer provided below the stacked structure, the buffer layer comprises a plurality of transfer through electrodes , and the plurality of transfer through electrodes are respectively connected to the transmission paths.

14\. (Canceled)

15\. (Currently Amended) The semiconductor structure according to claim 13, wherein the buffer layer comprises a second auxiliary through electrode , the first auxiliary through electrodes in all of the semiconductor dies are connected together and connected to the second auxiliary through electrode, and one end of the second auxiliary through electrode facing away from the stacked structure is provided with a ground terminal.

OFFICE ACTION:
DETAILED ACTION
This application, 17/80,7759, attorney docket 107033-1451142(056800US), filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to Changxin Memory Technologies, Inc., and  is a continuation of PCT/CN2022/091871, filed 05/10/2022 which  claims foreign priority to Chinese application 202210208256.6, filed 03/03/2022.  Claims 1, 3, 8-11, 13 and 15 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Applicant has incorporated the limitations from claim 7 into independent claim 1 and correctly argues that the amendment renders claim 1 and its dependents allowable.  Applicant has amended claim 1 to delete the limitations rejected in the previous office action under 112a and identified as missing from the drawings.  Applicant has cancelled claims 4, 5, 12 and 14 rendering the §112b rejections moot.
Allowable Subject Matter
Claims 1, 3, 8-11, 13 and 15 are allowed.
The following is an examiner’s statement of reasons for allowance:
As for claim 1, The prior art does not teach or make obvious a stack of semiconductor dies with alternating sets of through electrodes that are vertically connected in a “spiral patterns” that spiral in opposing directions, as shown in figure 8, and also includes a central  auxiliary electrode set.
Dependent claims include the novel electrode configuration of claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee.  Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion

APPLICANT REBUTTAL: REMARKS/ARGUMENTS
Upon entry of the present amendment, claims 1, 3, 8-10, 13, and 15 will be pending in
this application. Claims 1, 3, 8-10, 13, and 15 have been amended, and claims 2, 4-7, 12, and 14 have been canceled. Support can be found in, for example, paragraphs [0049]-[0063] and original claims of the Present Application. No new matter is added. Based on the following remarks, Applicant respectfully requests reconsideration and allowance of the pending claims.
Claim Rejections under -
35 U
.S.
C.
$
Claims 1-15 are rejected under 35 U.S.C. §112(a) as allegedly failing to comply with the enablement requirement. OA, pp. 2-3.
In an effort to expedite prosecution and without conceding to the merits of the rejections, Applicant has deleted "a first base" and "channel" recited in these claims, rendering these rejections moot.
Further, claims 1-15 are rejected under 35 U.S.C. § 112(b) as allegedly being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. OA, pp. 3-4.
In an effort to expedite prosecution and without conceding to the merits of the rejections, Applicant has amended claims 1, 3, and 6 and canceled claims 4-5, 12, and 14, thereby obviating the pending rejections.
Drawin
gs
The drawings are objected to under 37 CFR 1.83(a). OA, p. 4.
As explained above, Applicant has amended/canceled claims, and "a first base," "a second base," and "channel" are no longer recited in the claims.
Therefore, Applicant respectfully requests withdrawal of the pending objections.
Allowable Sub
j
ect Matte
r
Claim 7 is allowable. OA, pp. 11-12.
Applicant appreciates the Examiner's indicating of the allowability of claim 7.
Claim Re
j
ections under -
35 U
.
S.C.
X
Claims 1-6 and 8-15 are stand rejected under 35 U.S.C. § 102 as allegedly being anticipated by US 2015/0236003 to Konno et al.
In an effort to expedite prosecution and without conceding the priority of the pending rejections, Applicant has amended claim 1 to incorporate the elements recited in the
allowable claim 7
and any intervening claims.
It appears that Konno fails to disclose at least that "wherein each of the first transmission paths is a spiral path extending spirally along a first direction; and each of the second transmission paths is a spiral path extending spirally along a second direction, and the second direction is opposite to the first direction" in the manner recited in claim 1. Therefore, claim 1 and its dependent claims are in condition for allowance.
Accordingly, withdrawal of the rejections under 35 U.S.C. § 102 is respectfully requested.
CONCLUSION


CITED REFERENCE SUMMARIES: Ref CN2022091871: Claims:
A semiconductor structure, comprising a stack structure, the stack structure comprising a plurality of semiconductor dies stacked, each of the semiconductor dies comprising: first substrate; a channel disposed on the first substrate; at least one first auxiliary through-electrode and a plurality of connection through-electrodes penetrating through the first substrate, wherein at least one of the first auxiliary through-electrodes is surrounded by a plurality of connection through-electrodes; Wherein, the connection through electrodes of the adjacent semiconductor dies are connected through the first electrical connection structure to form a plurality of mutually isolated transmission paths, and each of the transmission paths is connected to at least one through at least one connection through electrode thereon. the channel.
The semiconductor structure according to claim 1, wherein, in one of the semiconductor dies, the plurality of connection through electrodes form at least one through electrode ring, and at least one of the first through electrode rings is arranged in each of the through electrode rings. Auxiliary feedthrough electrodes.
The semiconductor structure according to claim 1, wherein each of the semiconductor dies is provided with at least two channels and at least two through-electrode groups, and each of the through-electrode groups includes a plurality of the connection through-electrodes , the connection through-electrodes in at least two through-electrode groups are alternately arranged around at least one of the first auxiliary through-electrodes; The plurality of mutually isolated transmission paths form at least two transmission path groups, and each connecting through electrode in the same through electrode group is located on a different transmission path in the same transmission path group.
The semiconductor structure according to claim 3, wherein the positions of the channels on each of the semiconductor dies correspond to each other, and each of the transmission paths in the same transmission path group corresponds to the positions on each of the semiconductor dies channel connections.
The semiconductor structure according to claim 4, wherein the positions of the through-connection electrodes connected to the channels corresponding to the positions are in a one-to-one correspondence.
The semiconductor structure of claim 3 , wherein the at least two channels on each of the semiconductor dies include a first channel and a second channel, and the at least two sets of through electrodes on each of the semiconductor dies include A first through-electrode group and a second through-electrode group, the connection through-electrodes in the first through-electrode group are first through-electrodes, and the connection through-electrodes in the second through-electrode group are second through-electrodes; In one of the semiconductor dies, the first through-electrodes and the second through-electrodes are alternately arranged around at least one of the first auxiliary through-electrodes; The first through electrodes on each of the semiconductor dies are connected to form a transmission path group, the transmission paths in the transmission path group are first transmission paths, and each of the first transmission paths is connected to one of the first channels; The second through electrodes on each of the semiconductor dies are connected to form one transmission path group, the transmission paths in the transmission path group are second transmission paths, and each second transmission path is connected to one second channel.
The semiconductor structure according to claim 6, wherein each of the first transmission paths is a helical path extending helically along a first direction; Each of the second transmission paths is a helical path extending helically along a second direction, the second direction being opposite to the first direction.
The semiconductor structure according to claim 6, wherein said at least two channels on each of said semiconductor dies include a plurality of said first channels and a plurality of said first channels corresponding one-to-one to said plurality of said first channels. In the second channel, at least two through electrode groups on each of the semiconductor dies include a plurality of first through electrode groups and a plurality of second through electrode groups corresponding to the plurality of first through electrode groups. Each of the first through-electrode group and the corresponding second through-electrode group form a through-through unit, and a plurality of through-through units are arranged in an array.
The semiconductor structure according to claim 8, wherein each transmission path formed by the corresponding first through electrode group and the second through electrode group in each of the semiconductor dies is used to connect to the same signal source.
The semiconductor structure according to any one of claims 6 to 9, wherein one of the first through electrode groups includes four of the first through electrodes, and one of the second through electrode groups includes four of the second through electrodes. The through electrodes, the four first through electrodes and the four second through electrodes are alternately arranged around one of the first auxiliary through electrodes to form a through unit in a 3×3 array.
The semiconductor structure according to any one of claims 1 to 9, wherein the first auxiliary through electrodes in each of the semiconductor dies are connected together through a second electrical connection structure and grounded.
The semiconductor structure according to claim 11, wherein the positions of the first auxiliary through electrodes in each of the semiconductor dies correspond to each other.
The semiconductor structure according to any one of claims 1 to 9, wherein the semiconductor structure includes a buffer layer disposed under the stack structure, the buffer layer includes a second base body and a plurality of layers penetrating through the second base body. a transfer through electrode, and the plurality of transfer through electrodes are respectively connected to a plurality of the transmission paths.
The semiconductor structure according to claim 13, wherein said plurality of semiconductor dies form at least two groups of semiconductor dies, the semiconductor dies in each group of semiconductor dies correspond one-to-one, and each of said transmission paths It is connected with the channels on the corresponding semiconductor dies in each of the groups of semiconductor dies.
The semiconductor structure according to claim 13, wherein the buffer layer includes a second auxiliary through electrode penetrating through the second substrate, and the first auxiliary through electrodes in each of the semiconductor dies are electrically connected through a second The structures are connected together and connected to the second auxiliary through-electrode, and an end of the second auxiliary through-electrode away from the stack structure is provided with a ground terminal.