Office Action 1: Notice of Allowance (2025-05-08)

CLAIMS:
What is claimed is:

1\. An electronic circuit, comprising:
an event detector logic circuit;
a computing device; and
a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit,
wherein the event detector logic circuit is configured to:
receive a plurality of output signals from the plurality of IC chips,
generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, the data output signal generated such that the data is included in the data output signal independently of a presence and polarity of any static output signals of the plurality of output signals, and
transmit the data output signal to the computing device.
2\. The electronic circuit of claim 1, wherein the event detector logic circuit comprises an XOR logic element configured to:
perform a combined XOR operation on the plurality of output signals; and
transmit, as the data output signal, an output of the combined XOR operation to the computing device.
3\. The electronic circuit of claim 1, wherein the event detector logic circuit is configured to detect whether the plurality of output signals include data or are static.
4\. The electronic circuit of claim 1, wherein the event detector logic circuit is configured to generate the data output signal such that the data output signal indicates changes in the plurality of output signals.

5\. The electronic circuit of claim 4, wherein the event detector logic circuit is configured to generate the data output signal such that the data output signal indicates bit- to-bit changes in the plurality of output signals.
6\. The electronic circuit of claim 1, wherein the event detector logic circuit is configured to generate the data output signal such that a presence of bit-to-bit changes in the data output signal is independent of the presence and polarity of any static output signals of the plurality of output signals.
7\. The electronic circuit of claim 1, wherein the event detector logic circuit is configured to generate the data output signal such that a polarity of the data output signal is based on the presence and polarity of any static output signals of the plurality of output signals.
8\. The electronic circuit of claim 1, wherein the data in the data output signal is encoded as a plurality of bits, and
wherein the event detector logic circuit is configured to generate the data output signal such that a polarity of the plurality of bits is based on the presence and polarity of any static output signals of the plurality of output signals.
9\. The electronic circuit of claim 1, wherein the computing device is configured to:
determine a polarity of the data output signal; and
extract the data from the data output signal based on the determined polarity.

10\. The electronic circuit of claim 1, comprising a plurality of isolation resistors electrically connected between a signal input of each of the plurality of IC chips and the at least one control bus.

11\. The electronic circuit of claim 1, comprising:a power supply configured to provide a supply voltage to a power input of each of the plurality of IC chips; and

a plurality of isolation resistors electrically connected between the power input of each of the plurality of IC chips and the power supply.

12\. The electronic circuit of claim 1, wherein the computing device is configured to identify a predetermined non-static signal in the data output signal.

13\. The electronic circuit of claim 1, wherein an IC chip of the plurality of IC chips comprises at least one processor unit configured to perform one or more mathematical computations, andwherein the IC chip is configured to generate an output signal based on the one or more mathematical computations and forward the output signal to the event detector logic circuit as one of the plurality of output signals.

14\. The electronic circuit of claim 13, wherein the one or more mathematical computations comprise cryptographic hash computations, andwherein the output signal comprises an indication of a result of the cryptographic hash computations.

15\. The electronic circuit of claim 13, wherein the IC chip is configured to automatically generate and forward the output signal in response to determining that the one or more mathematical computations satisfy an objective.

16\. A method, comprising:performing computations using a plurality of integrated circuit (IC) chips;
transmitting, in parallel, a plurality of output signals of the plurality of IC chips to an event detector logic circuit;
generating, by the event detector logic circuit, a data output signal that includes data obtained from a first output signal of the plurality of output signals, such that the data is included in the data output signal independently of a presence and polarity of any static output signals of the plurality of output signals; and
transmitting the data output signal to a computing device.

17\. The method of claim 16, wherein generating the data output signal comprises performing a combined XOR operation on the plurality of output signals, wherein the data output signal comprises an output of the combined XOR operation.

18\. The method of claim 16, comprising detecting, by the event detection logic circuit, whether the plurality of output signals include data or are static.

19\. The method of claim 16, comprising generating the data output signal such that the data output signal indicates changes in the plurality of output signals.

20\. The method of claim 19, comprising generating the data output signal such that the data output signal indicates bit-to-bit changes in the plurality of output signals.

21\. The method of claim 16, comprising generating the data output signal such that a presence of bit-to-bit changes in the data output signal is independent of the presence and polarity of any static output signals of the plurality of output signals.

22\. The method of claim 16, comprising generating the data output signal such that a polarity of the data output signal is based on the presence and polarity of any static output signals of the plurality of output signals.

23\. The method of claim 16, comprising generating the data output signal such that:the data in the data output signal is encoded as a plurality of bits, and
a polarity of the plurality of bits is based on the presence and polarity of any static output signals of the plurality of output signals.

24\. The method of claim 16, comprising:determining, by the computing device, a polarity of the data output signal; and
extracting, by the computing device, the data from the data output signal based on the determined polarity.

25\. The method of claim 16, comprising electrically isolating a signal input of each of the plurality of IC chips from other IC chips using a plurality of isolation resistors electrically connected between the plurality of IC chips and at least one control bus.

26\. The method of claim 16, comprising:providing a supply voltage to a power input of each of the plurality of IC chips;
and electrically isolating the power input of each of the plurality of IC chips from other IC chips using a plurality of isolation resistors on power transmission paths providing the supply voltage.

27\. The method of claim 16, comprising:performing, by an IC chip of the plurality of IC chips, one or more mathematical computations;
generating, by the IC chip, an output signal based on the one or more mathematical computations; and
forwarding, by the IC chip, the output signal to the event detector logic circuit, as one of the plurality of output signals.

28\. The method of claim 27, wherein the one or more mathematical computations comprise cryptographic hash computations, andwherein the output signal comprises an indication of a result of the cryptographic hash computations.

29\. The method of claim 27, comprising automatically generating and forwarding the output signal in response to determining that the one or more mathematical computations satisfy an objective.

30\. An electronic circuit, comprising:

a plurality of integrated circuit (IC) chips that are electrically connected in parallel between (i) at least one control bus configured to provide input signals and (ii) circuitry configured to receive output signals from the plurality of IC chips;
a power supply configured to provide a supply voltage to a power input of each of the plurality of IC chips; and
a plurality of isolation resistors electrically connected between at least one of:
(i) a signal input of each of the plurality of IC chips and the at least one control bus, or (ii) the power input of each of the plurality of IC chips and the power supply.

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/10/25 is being considered by the examiner.
Allowable Subject Matter
The following is an examiner’s statement of reasons for allowance:
With respect to claim 1, in combination with other limitations of the claim, the cited prior art fails to teach “receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, the data output signal generated such that the data is included in the data output signal independently of a presence and polarity of any static output signals of the plurality of output signals, and transmit the data output signal to the computing device” structurally and functionally interconnected with other limitations as required by claim 1, nor would it have been obvious to one of ordinary skill in the art to do so.
Claims 2-15 are allowed as being dependent on claim 1.
With respect to claim 16, in combination with other limitations of the claim, the cited prior art fails to teach “a data output signal that includes data obtained from a first output signal of the plurality of output signals, such that the data is included in the data output signal independently of a presence and polarity of any static output signals of the plurality of output signals; and transmitting the data output signal to a computing device” structurally and functionally interconnected with other limitations as required by claim 16, nor would it have been obvious to one of ordinary skill in the art to do so.
Claims 17-29 are allowed as being dependent on claim 16.
With respect to claim 30, in combination with other limitations of the claim, the cited prior art fails to teach “a plurality of isolation resistors electrically connected between at least one of: (i) a signal input of each of the plurality of IC chips and the at least one control bus, or (ii) the power input of each of the plurality of IC chips and the power supply” structurally and functionally interconnected with other limitations as required by claim 30, nor would it have been obvious to one of ordinary skill in the art to do so.
Claims 1-30 are allowed.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee.  Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion



CITED REFERENCE SUMMARIES: Ref US7012443B2: Claims:
A system which tests a plurality of devices in parallel, the system comprising: a plurality of devices under test, said devices arranged in rows and columns; a plurality of input/output signal channels connected in common to input/output signal pins of the devices under test, all input/output signal pins of devices in each row being connect to the same input/output signal channel, a plurality of chip selection signal channels which provide chip selection signals to the devices under test to specify one output data among output data to be output through the commonly connected input/output signal channels, each chip selection signal channel being connected to all the devices under test in one column; a DC channel connected in common with an inverted clock signal pin and a reference voltage pin of the devices under test; and test equipment which tests the devices under test through the input/output signal channels and the chip selection signal channels.
a plurality of devices under test, said devices arranged in rows and columns;
a plurality of input/output signal channels connected in common to input/output signal pins of the devices under test, all input/output signal pins of devices in each row being connect to the same input/output signal channel,
a plurality of chip selection signal channels which provide chip selection signals to the devices under test to specify one output data among output data to be output through the commonly connected input/output signal channels, each chip selection signal channel being connected to all the devices under test in one column;
a DC channel connected in common with an inverted clock signal pin and a reference voltage pin of the devices under test; and
test equipment which tests the devices under test through the input/output signal channels and the chip selection signal channels.
The system of claim 1 , wherein the devices under test are memory devices.
The system of claim 1 , wherein one of the input/output pins is directly connected to the input/output signal channel and other input/output pin is shorted with the directly connected pin.
The system of claim 3 , wherein the directly connected pin and the pin shorted with the directly connected pin are individually included in different devices under test.
The system of claim 1 , wherein the number of input/output signal channels is less than or equal to half the number of input/output signal pins of one device under test.
The system of claim 1 , wherein the DC channel is connected in common to the inverted clock signal pins and the reference voltage pins of devices under test that are connected in common to the same input/output signal channel.
The system of claim 1 , wherein the number of the chip selection channels is dependent on the number of the devices under test which are connected in common to the input/output signal channels.
The system of claim 1 , further comprising second devices under test which are connected in common to the chip selection channels but not connected in common to the commonly connected input/output signal channels.
A method of testing a plurality of devices under test, said devices having an inverted clock signal pin and a reference voltage pin, comprising: preparing at least two devices under test having input/output signal pins connected in common to an input/output signal channel, said devices having chip selection signal pins connected to respective chip selection signal channels, which provide chip selection signals used to select output data from one of the devices under test, and a DC channel connected in common to said inverted clock signal pin and to said reference voltage pin; and reading through the commonly connected input/output signal channel the output data of the device under test selected by the chip selection signal.
preparing at least two devices under test having input/output signal pins connected in common to an input/output signal channel, said devices having chip selection signal pins connected to respective chip selection signal channels, which provide chip selection signals used to select output data from one of the devices under test, and a DC channel connected in common to said inverted clock signal pin and to said reference voltage pin; and
reading through the commonly connected input/output signal channel the output data of the device under test selected by the chip selection signal.
The method of claim 9 , wherein the preparation step includes directly connecting one of the input/output signal pins to the input/output signal channel and shortening the other pin with the directly connected pin.
The method of claim 10 , wherein the directly connected pin and the shorted pin are individually included in different devices under test.
The method of claim 9 , wherein the preparation step further includes commonly connecting a DC channel which supplies DC current to inverted clock signal pins and reference voltage pins of the devices under test.
The method of claim 12 , wherein the DC channel is connected in common to only the inverted clock signal pins and the reference voltage pins of the devices under test that are connected in common to the input/output signal channel.
The method of claim 9 , further comprising introducing second devices under test which are connected in common to the chip selection signal channel but not connected in common to the commonly connected input/output signal channel.
The method of claim 14 , wherein the reading step includes reading via an input/output signal channel different from the commonly connected input/output signal channel output data specified by the chip selection signals, from the second devices under test.
The method of claim 9 , wherein the chip selection signals enable output data other than the selected output data, among output data connected to the commonly connected input/output signal channel, to a high impedance state, so that only the selected output data are outputted to the commonly connected input/output signal channel.
The method of claim 9 , further comprising commonly performing a write operation at the devices under test, before the reading step.
A method of testing a plurality of devices under test (DUTs) which have input/output pins, inverted clock signal pins, reference voltage pins, and chip selection signal pins using test equipment which includes signal channels, comprising: connecting in common the input/output signal pins of at least two DUTs and connecting said commonly connected pins to a first channel with is used as an input/output signal channel; connecting said chip selection signal pins to channels used as chip selection channels, which provides chip selection signals to select output data from one of said DUTs; connecting a DC channel to said inverted clock signal pins and to said reference voltage pins, and reading through the commonly connected input/output signal channel the output data of the device under test selected by the chip selection channels.
connecting in common the input/output signal pins of at least two DUTs and connecting said commonly connected pins to a first channel with is used as an input/output signal channel;
connecting said chip selection signal pins to channels used as chip selection channels, which provides chip selection signals to select output data from one of said DUTs;
connecting a DC channel to said inverted clock signal pins and to said reference voltage pins, and
reading through the commonly connected input/output signal channel the output data of the device under test selected by the chip selection channels.
A method of testing a plurality of devices under test (DUTs) wherein at least two of said DUTs have input/output signal pins connected in common to an input/output signal channel, said DUTs have chip selection signal pins connected to respective chip selection signal channels which provide chip selection signals used to select output data from one of the devices under test, and a DC channel connected in common to an inverted clock signal pin and a reference voltage pin; said method comprising: selecting one of said DUTs by a chip selection signal on said chip selection channels, activating said DC channel, and reading through the commonly connected input/output signal channel the output data of the device under test selected by said chip selection signal.
selecting one of said DUTs by a chip selection signal on said chip selection channels,
activating said DC channel, and
reading through the commonly connected input/output signal channel the output data of the device under test selected by said chip selection signal.
The method of claim 19 , wherein the input/output signal pins of one DUT is directly connected to the input/output signal channel and the input/output signal pins of a second DUT are shorted the input/output signal pins of the directly connected DUT.
The method of claim 19 , including commonly connecting a DC channel which supplies DC current to inverted clock signal pins and reference voltage pins of the DUTs.
The method of claim 21 , wherein the DC channel is connected in common to only the inverted clock signal pins and the reference voltage pins of the DUTs that are connected in common to the input/output signal channel.
The method of claim 19 , further comprising introducing a second DUT which is connected in common to the chip selection signal channel but not connected in common to the commonly connected input/output signal channel.
The method of claim 23 , wherein the reading step includes reading via an input/output signal channel different from the commonly connected input/output signal channel output data specified by the chip selection signals, from the second DUT.
The method of claim 19 , wherein the chip selection signals enable output data other than the selected output data to a high impedance state, so that only the selected output data are outputted to the commonly connected input/output signal channel.
The method of claim 19 , further comprising commonly performing a write operation to the DUTs, before the reading step.
Ref US7350108B1: Claims:
A device for transporting integrated circuit chips and for testing said integrated circuit chips during said transporting, said device comprising: an in-transit box adapted to transport said integrated circuit chips; a plurality of test boxes mounted in said in-transit box; a plurality of test boards mounted in each one of said test boxes and adapted to test said integrated circuit chips during said transporting of said integrated circuit chips; and a power supply in each of said test boxes, connected to each of said test boards, and adapted to supply power to said test boards during said transporting and said testing of said integrated circuit chips, wherein each of said test boards comprises: multiple sockets adapted to hold and electrically connect to multiple integrated circuit chips; and testing circuitry electrically connected to said sockets for testing said multiple integrated circuit chips.
an in-transit box adapted to transport said integrated circuit chips;
a plurality of test boxes mounted in said in-transit box;
a plurality of test boards mounted in each one of said test boxes and adapted to test said integrated circuit chips during said transporting of said integrated circuit chips; and
a power supply in each of said test boxes, connected to each of said test boards, and adapted to supply power to said test boards during said transporting and said testing of said integrated circuit chips,
wherein each of said test boards comprises: multiple sockets adapted to hold and electrically connect to multiple integrated circuit chips; and testing circuitry electrically connected to said sockets for testing said multiple integrated circuit chips.
multiple sockets adapted to hold and electrically connect to multiple integrated circuit chips; and
testing circuitry electrically connected to said sockets for testing said multiple integrated circuit chips.
The device in claim 1 , all the limitations of which are incorporated herein by reference, wherein each of said test boards includes visual test failure indicators, such that one of said visual test failure indicators is adjacent each of said sockets.
The device in claim 1 , all the limitations of which are incorporated herein by reference, wherein for each test box said power supply comprises a power bus electrically connected between said test boards and one of a battery in said test box and a separate power supply in said in-transit box.
The device in claim 1 , all the limitations of which are incorporated herein by reference, wherein each of said test boards includes a memory adapted to store test results.
The device in claim 1 , all the limitations of which are incorporated herein by reference, wherein each of said test boards includes a known good integrated circuit chip.
The device in claim 5 , all the limitations of which are incorporated herein by reference, wherein each of said test boards includes comparators electrically connected to said sockets.
The device in claim 6 , all the limitations of which are incorporated herein by reference, wherein said testing circuitry is adapted to supply identical test patterns to said integrated circuit chips to be tested and to said known good integrated circuit chip, and wherein said comparators compare an output generated by said known good integrated circuit chip with outputs generated by said integrated circuit chips to be tested to identify defective integrated circuit chips.
wherein said comparators compare an output generated by said known good integrated circuit chip with outputs generated by said integrated circuit chips to be tested to identify defective integrated circuit chips.
The device in claim 7 , all the limitations of which are incorporated herein by reference, wherein said comparators are in parallel to one another such that all comparisons performed by said comparators are made simultaneously.
A device for transporting application specific integrated circuit (ASIC) chips and for testing said application specific integrated circuit (ASIC) chips during said transporting, said device comprising: an in-transit box adapted to transport ASIC chips; a plurality of test boxes mounted in said in-transit box; a plurality of test boards mounted in each one of said test boxes and adapted to test said ASIC chips during said transporting of said ASIC chips; and a power supply in each of said test boxes, connected to each of said test boards, and adapted to supply power to said test boards during said transporting and said testing of said ASIC chips, wherein each of said test boards comprises: multiple sockets adapted to hold and electrically connect to multiple ASIC chips; and testing circuitry electrically connected to said sockets for testing said multiple ASIC chips, wherein said testing circuitry includes comparators arranged in parallel and electrically connected to said sockets, such that said testing circuitry tests all of said multiple ASIC chips simultaneously, and wherein said testing circuitry identifies a defective ASIC chip as one having a different output when compared to outputs of the other ASIC chips, when all of said multiple ASIC chips are supplied with identical inputs.
an in-transit box adapted to transport ASIC chips;
a plurality of test boards mounted in each one of said test boxes and adapted to test said ASIC chips during said transporting of said ASIC chips; and
a power supply in each of said test boxes, connected to each of said test boards, and adapted to supply power to said test boards during said transporting and said testing of said ASIC chips,
wherein each of said test boards comprises:
multiple sockets adapted to hold and electrically connect to multiple ASIC chips; and
testing circuitry electrically connected to said sockets for testing said multiple ASIC chips, wherein said testing circuitry includes comparators arranged in parallel and electrically connected to said sockets, such that said testing circuitry tests all of said multiple ASIC chips simultaneously, and
wherein said testing circuitry identifies a defective ASIC chip as one having a different output when compared to outputs of the other ASIC chips, when all of said multiple ASIC chips are supplied with identical inputs.
The device in claim, 9 all the limitations of which are incorporated herein by reference, wherein all of said multiple ASIC chips have an identical design.
The device in claim 9 , all the limitations of which are incorporated herein by reference, wherein each of said test boards includes visual test failure indicators, such that one of said visual test failure indicators is adjacent each of said sockets.
The device in claim 9 , all the limitations of which are incorporated herein by reference, wherein for each test box said power supply comprises a power bus electrically connected between said test boards and one of a battery in said test box and a separate power supply in said in-transit box.
The device in claim 9 , all the limitations of which are incorporated herein by reference, wherein each of said test boards includes a memory adapted to store test results.
The device in claim 9 , all the limitations of which are incorporated herein by reference, wherein each of said test boards includes a known good integrated circuit chip.
The device in claim 14 , all the limitations of which are incorporated herein by reference, wherein all of said comparators are connected to said known good integrated circuit chip such that any ASIC chips that produce an output different than the output produced by said known good integrated circuit chip is identified as a defective ASIC chip.
The device in claim 9 , all the limitations of which are incorporated herein by reference, wherein by comparing whether outputs of all ASIC chips are identical, said testing circuitry does not require a specific proper output that a given input should produce for the specific design of ASIC chip being tested.
Ref US20080191728A1: Claims:
An isolation circuit, comprising: a first transistor having a source connected to a first terminal, wherein the first terminal connects a supply voltage to the source of the first transistor; a register connected to the drain of the first transistor; a second transistor in parallel with a resistor, a gate of the second transistor is connected to an output of the register and a source of the second transistor is connected to the first terminal; and wherein a drain of the second transistor is connected to a second terminal, and wherein the second transistor has a state that depends on whether the register is loaded.
a first transistor having a source connected to a first terminal, wherein the first terminal connects a supply voltage to the source of the first transistor;
a register connected to the drain of the first transistor;
a second transistor in parallel with a resistor, a gate of the second transistor is connected to an output of the register and a source of the second transistor is connected to the first terminal; and
wherein a drain of the second transistor is connected to a second terminal, and wherein the second transistor has a state that depends on whether the register is loaded.
The isolation circuit of claim 1 , wherein the first terminal is a supply voltage pad of a semiconductor die.
The isolation circuit of claim 1 , wherein the isolation circuit is located on an unsingulated semiconductor die.
The isolation circuit of claim 3 , wherein the second terminal is connected to testing circuitry.
The isolation circuit of claim 4 , wherein the testing circuitry includes at least one of: built in self stress (BISS) circuitry; and built in self test (BIST) circuitry.
built in self stress (BISS) circuitry; and
built in self test (BIST) circuitry.
The isolation circuit of claim 1 , wherein a short at the first terminal prevents the register 
[Truncated to input limit]