Office Action 1: Non-Final Rejection (2024-12-26)
Rejection types: 102 - Lack of Novelty, 103 - Obviousness

CLAIMS:
Listing of Claims

The following listing of the claims replaces all prior versions and listings of claims in the application as filed or submitted in any previous amendment:

AMENDMENT TO THE CLAIMS

1\. - 18. (Cancelled)217

19\. (New) Pre-conditioning circuitry for pre-conditioning a capacitor of a circuit to support a change in operation of the circuit, wherein the pre-conditioning circuitry is configured to apply a voltage, current or charge directly to the capacitor prior to the change in operation of the circuit to reduce a settling time of the circuit following the change in operation of the circuit.

20\. (New) The pre-conditioning circuitry of claim 19, wherein the pre-conditioning circuitry is configured to apply the voltage, current or charge directly to the capacitor to pre-charge the capacitor to a predefined level of charge prior to the change in operation of the circuit.

21\. (New) The pre-conditioning circuitry of claim 19, wherein the pre-conditioning circuitry is configured to output a first voltage to a first circuit node and to output a second voltage to a second circuit node to pre-charge the capacitor prior to the change in operation of the circuit.

22\. (New) The pre-conditioning circuitry of claim 21, wherein the pre-conditioning circuitry is configured to control a first pre-conditioning switch to selectively output the first voltage to the first circuit node and to control a second pre-conditioning switch to selectively output the second voltage to the second circuit node.

23\. (New) The pre-conditioning circuitry of claim 20, wherein the predefined level of charge is higher than is theoretically required to achieve a given settling time.

24\. (New) The pre-conditioning circuitry of claim 23, wherein the predefined level of charge includes an additional amount of charge to compensate for charge redistribution from the capacitor to a parasitic capacitance, an intrinsic capacitance or an explicit capacitance of the circuit.

25\. (New) The pre-conditioning circuitry of claim 19, wherein the capacitor is a Miller capacitor.

26\. (New) The pre-conditioning circuitry of claim 19, wherein the circuit is an amplifier circuit configured such that, in use of the amplifier circuit, the capacitor provides frequency compensation for the amplifier circuit.

27\. (New) Pre-conditioning circuitry according to claim 19, wherein the change in operation of the circuit is in response to start-up of the circuit.

28\. (New) An integrated circuit comprising pre-conditioning circuitry according to claim 19.

29\. (New) A host device comprising pre-conditioning circuitry according to claim 19.

30\. (New) A host device according to claim 29, wherein the host device comprises a laptop, notebook, netbook or tablet computer, a gaming device, a games console, a controller for a games console, a virtual reality (VR) or augmented reality (AR) device, a mobile telephone, a portable audio player, a portable device, an accessory device for use with a laptop, notebook, netbook or tablet computer, a gaming device, a games console a VR or AR device, a mobile telephone, a portable audio player or other portable device.

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 19, 20 and 25-29 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim (U.S. Patent 11,086,343 cited in the Information Disclosure Statement filed January 31, 2024).
Claim 19: Kim teaches pre-conditioning circuitry (Figure 1) for pre-conditioning a capacitor of a circuit to support a change in operation of the circuit (column 2 lines 1-10), wherein the pre-conditioning circuitry is configured to apply a voltage, current or charge (output of 180, 190 and 192) directly to the capacitor (at node VCC directly connected to 140) prior to the change in operation of the circuit (standby to active mode; column 2 lines 1-10) to reduce a settling time of the circuit following the change in operation of the circuit (improves the wake-up response of the regulator; column 2 lines 1-10).
Claim 20: Kim further teaches that the pre-conditioning circuitry is configured to apply the voltage, current or charge directly to the capacitor (to node VCC directly connected to 140) to pre-charge the capacitor to a predefined level of charge prior to the change in operation of the circuit (column 6 lines 26-30).
Claim 25: Kim further teaches that the capacitor is a Miller capacitor (column 3 lines 26-27).
Claim 26: Kim further teaches that the circuit is an amplifier circuit (amplifier 130) configured such that, in use of the amplifier circuit, the capacitor provides frequency compensation for the amplifier circuit (via compensation capacitor 140).
Claim 27: Kim further teaches that the change in operation of the circuit is in response to start-up of the circuit (standby to active; column 2 lines 1-10).
Claim 28: Kim further teaches an integrated circuit comprising pre-conditioning circuitry according to claim 19 (Figure 1; column 1 lines 8-10).
Claim 29: Kim further teaches a host device comprising pre-conditioning circuitry according to claim 19 (memory device; column 1 lines 14-26).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Zhan et al. (U.S. Patent 11,082,047 cited in the Information Disclosure Statement filed January 31, 2024, hereafter Zhan).
Claim 30: Kim teaches the limitations of claim 29 above. Kim does not specifically teach that the host device comprises a laptop, notebook, netbook or tablet computer, a gaming device, a games console, a controller for a games console, a virtual reality (VR) or augmented reality (AR) device, a mobile telephone, a portable audio player, a portable device, an accessory device for use with a laptop, notebook, netbook or tablet computer, a gaming device, a games console a VR or AR device, a mobile telephone, a portable audio player or other portable device.
Zhan teaches the use of low dropout linear voltage regulator (LDO) in portable consumer devices such as mobile phones, laptops and music players (column 1 lines 23-35).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the host devices taught by Zhan when employing the memory device of Kim to provide highly responsive, efficient and low-cost power management (column 1 lines 23-25 of Zhan).
Allowable Subject Matter
Claims 21-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 21, the prior art does not fairly teach or suggest that the pre-conditioning circuitry is configured to output a first voltage to a first circuit node and to output a second voltage to a second circuit node to pre-charge the capacitor prior to the change in operation of the circuit.
Regarding claim 23, the prior art does not fairly teach or suggest that the predefined level of charge is higher than is theoretically required to achieve a given settling time.
Claims 22 and 24 are objected to merely for being dependent from claims 21 and 23.
Conclusion

APPLICANT REBUTTAL: ATTORNEY DOCKET
PATENT APPLICATION
REMARKS
Claims 19-30 were pending and examined. Applicant has amended Claim 19 and cancelled, without waiver or prejudice, Claim 21. Claims 19, 20, and 22-30 remain pending. Any amendment not specifically referenced with respect to a statutory ground of rejection is not made for any purpose related to patentability.
Allowable Sub
j
ect Matter
Applicant appreciates the Examiner's indication that Claims 21-24 would be allowable if rewritten in independent form to include the limitations of their respective base and intervening claims. To that end, Applicant has amended independent Claim 19 to include the features of now- cancelled Claim 21.
Thus, Claim 19 is allowable. Given that Claim 22-24 depend from Claim 19, Claims 22- 24 are also allowable.  Accordingly, Applicant respectfully requests reconsideration and withdrawal of the objections to Claims 22-24, and full allowance of Claims 22-24.
Rej
ections under 35 U.S.C.
&
102(a)(2) and 103
Claims 19, 20, and 25-29 were rejected under 35 U.S.C. §102(a)(2) as allegedly anticipated by Kim, U.S. Patent No. 11086343 (hereinafter, "Kim").
Claim 30 was rejected under 35 U.S.C. §103 as allegedly unpatentable over Kim in view of Zhan et al., U.S. Patent No. 11082047 (hereinafter, "Zhan").
While Applicant makes no concessions regarding the rejections under 35 U.S.C. §§ 102 and 103, as set forth above, Applicant has amended Claim 19 to include the subject matter of original, now-cancelled Claim 21, which the Examiner held to recite allowable subject matter. Accordingly, amended Claim 19 is allowable. Given that Claims 20 and 25-30 depend from Claim 19, Applicant submits that Claims 20 and 25-30 are also allowable. Accordingly, Applicant respectfully requests reconsideration and withdrawal of the rejections under 35 U.S.C. §§ 102 and 103, and full allowance of Claims 19, 20, and 25-30, as amended.
ATTORNEY DOCKET
PATENT APPLICATION
CONCLUSION

NEXT OFFICE ACTION: DETAILED ACTION
Allowable Subject Matter
Claims 19, 20 and 22-30 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 19, the prior art does not fairly teach or suggest that the pre-conditioning circuitry is configured to output a first voltage to a first circuit node and to output a second voltage to a second circuit node to pre-charge the capacitor prior to the change in operation of the circuit in combination with the limitations of claim 19.
Claims 20 and 22-30 are allowed merely for being dependent on claim 19.
Kim (U.S. Patent 11,086,343 cited in the Information Disclosure Statement filed January 31, 2024) teaches pre-conditioning circuitry (Figure 1) for pre-conditioning a capacitor (Cc) to support a change in operation of the circuit (column 2 lines 1-10). Kim does not specifically teach outputting a first voltage to a first circuit node and to output a second voltage to a second circuit node to pre-charge the capacitor prior to the change in operation of the circuit.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee.  Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion

CITED REFERENCE SUMMARIES: Ref US4698743: Claims:
A resonance inverter comprising: a resonance capacitor; an inductor connected in parallel with said resonance capacitor, to form a parallel resonant circuit; at least two semiconductor switches provided between said resonance capacitor and said DC power source, to control the charge/discharge of said capacitor; and control means to alternately render conductive said semiconductor switches, with a certain lead phase difference with respect to the peak point of a peak value of the voltage across said resonance capacitor; said control means including: reference voltage generating means for generating the peak value of the voltage across said resonance capacitor, and producing a reference voltage, which is lower than said peak value, but proportional to said peak value; comparing means for comparing said reference voltage and said capacitor terminal voltage, and producing pulses with a predetermined lead phase difference with respect to said terminal voltage; and switch drive means for generating trigger pulses to render said switches conductive in response to the output pulse from said comparing means.
a resonance capacitor;
an inductor connected in parallel with said resonance capacitor, to form a parallel resonant circuit;
at least two semiconductor switches provided between said resonance capacitor and said DC power source, to control the charge/discharge of said capacitor; and
control means to alternately render conductive said semiconductor switches, with a certain lead phase difference with respect to the peak point of a peak value of the voltage across said resonance capacitor;
said control means including:
reference voltage generating means for generating the peak value of the voltage across said resonance capacitor, and producing a reference voltage, which is lower than said peak value, but proportional to said peak value;
comparing means for comparing said reference voltage and said capacitor terminal voltage, and producing pulses with a predetermined lead phase difference with respect to said terminal voltage; and
switch drive means for generating trigger pulses to render said switches conductive in response to the output pulse from said comparing means.
A resonance inverter according to claim 1, in which said reference voltage generating means includes a peak hold circuit for holding said peak voltage, and attenuating means for attenuating said peak voltage held by said peak hold circuit.
A resonance inverter according to claim 2, in which said attenuating means is a voltage divider.
A resonance inverter according to claim 1, in which said control means comprises peak detecting means for detecting the peak value of said capacitor terminal voltage, pulse generating means for generating pulses with a predetermined lead phase angle with respect to the peak point of said terminal voltage on the basis of the detection results from said peak detecting means, switch drive means for generating trigger pulses to render conductive said switches in response to the output of said pulse generating means.
A resonance inverter according to claim 1, in which said semiconductor switches are thyristors.
A resonance inverter according to claim 1, in which said semiconductor switches are two semiconductor switches forming a push-pull inverter in which said switches are selectively conducted, to apply an inverse voltage from said DC power source to said resonance capacitor.
A resonance inverter according to claim 1, in which said semiconductor switches are four semiconductor switches connected in a bridge fashion to form a bridge inverter.
A resonance inverter according to claim 1, in which said inductor includes inductance of an output transformer for supplying the output to a load.
A resonance inverter according to claim 1, further comprising a choke coil connected in series to the DC power source.
Ref US11625055B2: Claims:
A linear regulator, comprising: a pass device coupled between an input voltage level and an output node; a voltage divider circuit for generating a feedback voltage that depends on an output voltage at the output node; and an operational amplifier for controlling the pass device, the operational amplifier receiving the feedback voltage and a reference voltage at its inputs, wherein the operational amplifier comprises: an input stage that receives the feedback voltage and the reference voltage at its inputs; an amplifier stage that receives an output of the input stage at its input; a current injection circuit for sourcing current into an intermediate node between the input stage and the amplifier stage, or sinking a current from the intermediate node; and a Miller capacitance that is formed between the intermediate node and the output node, wherein the current injection circuit is for compensating for current flowing through the Miller capacitance, wherein the voltage divider circuit comprises a variable resistance element that is arranged such that varying a resistance of the variable resistance element changes a divider ratio of the voltage divider circuit, and wherein the current injection circuit and the variable resistance element operate under control of the same control signal.
a pass device coupled between an input voltage level and an output node;
a voltage divider circuit for generating a feedback voltage that depends on an output voltage at the output node; and
an operational amplifier for controlling the pass device, the operational amplifier receiving the feedback voltage and a reference voltage at its inputs,
wherein the operational amplifier comprises:
an input stage that receives the feedback voltage and the reference voltage at its inputs;
an amplifier stage that receives an output of the input stage at its input;
a current injection circuit for sourcing current into an intermediate node between the input stage and the amplifier stage, or sinking a current from the intermediate node; and
a Miller capacitance that is formed between the intermediate node and the output node,
wherein the current injection circuit is for compensating for current flowing through the Miller capacitance,
wherein the voltage divider circuit comprises a variable resistance element that is arranged such that varying a resistance of the variable resistance element changes a divider ratio of the voltage divider circuit, and
wherein the current injection circuit and the variable resistance element operate under control of the same control signal.
The linear regulator according to claim 1 , wherein the current injection circuit comprises a controllable current source for sourcing a current into the intermediate node and/or a controllable current sink for sinking a current from the intermediate node.
The linear regulator according to claim 2 , wherein the controllable current source and the controllable current sink are iDACs.
The linear regulator according to claim 1 , wherein the voltage divider circuit has a variable divider ratio; and wherein the current injection circuit is jointly controlled with the voltage divider circuit.
wherein the current injection circuit is jointly controlled with the voltage divider circuit.
The linear regulator according to claim 1 , wherein the current injection circuit and the variable resistance element are jointly controlled such that the current injection circuit sources current to the intermediate node when the divider ratio is increased.
The linear regulator according to claim 1 , wherein the current injection circuit and the variable resistance element are jointly controlled such that the current injection circuit sinks current from the intermediate node when the divider ratio is decreased.
The linear regulator according to claim 1 , wherein the current injection circuit is controlled in such manner that it sinks current from the intermediate node during ramp-up of the output voltage.
The linear regulator according to claim 1 , wherein the current injection circuit is controlled in such manner that it sources current to the intermediate node during ramp-down of the output voltage.
A method of operating a linear regulator, wherein the linear regulator comprises: a pass device coupled between an input voltage level and an output node; a voltage divider circuit for generating a feedback voltage that depends on an output voltage at the output node; and an operational amplifier for controlling the pass device, wherein the operational amplifier receives the feedback voltage and a reference voltage at its inputs and comprises: an input stage that receives the feedback voltage and the reference voltage at its inputs, an amplifier stage that receives an output of the input stage at its input, and a Miller capacitance that is formed between an intermediate node between the input stage and the amplifier stage and the output node, the method comprising: sourcing a current into the intermediate node, or sinking a current from the intermediate node, for compensating for current flowing through the Miller capacitance, wherein the voltage divider circuit comprises a variable resistance element that is arranged such that varying a resistance of the variable resistance element changes a divider ratio of the voltage divider circuit, and the method further comprising: operating the variable resistance element and a current injection circuit for sourcing or sinking of the current under control of the same control signal.
an operational amplifier for controlling the pass device, wherein the operational amplifier receives the feedback voltage and a reference voltage at its inputs and comprises: an input stage that receives the feedback voltage and the reference voltage at its inputs, an amplifier stage that receives an output of the input stage at its input, and a Miller capacitance that is formed between an intermediate node between the input stage and the amplifier stage and the output node,
the method comprising:
sourcing a current into the intermediate node, or sinking a current from the intermediate node, for compensating for current flowing through the Miller capacitance,
the method further comprising:
operating the variable resistance element and a current injection circuit for sourcing or sinking of the current under control of the same control signal.
The method according to claim 9 , wherein the current is sourced into the intermediate node by a controllable current source for sourcing the current into the intermediate node and/or the current is sunk from the intermediate node by a controllable current sink for sinking the current from the intermediate node.
The method according to claim 10 , wherein the controllable current source and the controllable current sink are iDACs.
The method according to claim 9 , wherein the voltage divider circuit has a variable divider ratio; and the method comprises: jointly controlling the voltage divider circuit and a current injection circuit for sourcing or sinking of the current.
the method comprises:
jointly controlling the voltage divider circuit and a current injection circuit for sourcing or sinking of the current.
The method according to claim 9 , comprising: sourcing current to the intermediate node when the divider ratio is increased.
sourcing current to the intermediate node when the divider ratio is increased.
The method according to claim 9 , comprising: sinking current from the intermediate node when the divider ratio is decreased.
sinking current from the intermediate node when the divider ratio is decreased.
Ref US11082047B2: Claims:
A low dropout linear voltage regulator, comprising: an error amplifier, a power transistor, a dynamic Miller compensation network and a controller, wherein a source of the power transistor is connected to a power source, a gate of the power transistor is connected to an output terminal of the error amplifier, and a drain of the power transistor is connected to an output terminal of the low dropout linear voltage regulator; a first terminal of the dynamic Miller compensation network is connected to the output terminal of the error amplifier, a second terminal of the dynamic Miller compensation network is connected to the output terminal of the low dropout linear voltage regulator; a first terminal of the controller is connected to the gate of the power transistor, and a second terminal of the controller is connected to a third terminal of the dynamic Miller compensation network; the dynamic Miller compensation network comprises a first resistance-capacitance branch and at least one second resistance-capacitance branch, and the first resistance-capacitance branch is connected in parallel with the at least one second resistance-capacitance branch, wherein the first resistance-capacitance branch comprises a first resistor and a first capacitor connected in series, and each of the at least one second resistance-capacitance branch comprises a second resistor and a second capacitor connected in series; and the controller is configured to detect a current at the output terminal of the low dropout linear voltage regulator and generate one or more control signals according to the current to control connection and disconnection of each of the at least one second resistance-capacitance branch in the dynamic Miller compensation network.
wherein a source of the power transistor is connected to a power source, a gate of the power transistor is connected to an output terminal of the error amplifier, and a drain of the power transistor is connected to an output terminal of the low dropout linear voltage regulator;
a first terminal of the dynamic Miller compensation network is connected to the output terminal of the error amplifier, a second terminal of the dynamic Miller compensation network is connected to the output terminal of the low dropout linear voltage regulator; a first terminal of the controller is connected to the gate of the power transistor, and a second terminal of the controller is connected to a third terminal of the dynamic Miller compensation network;
the dynamic Miller compensation network comprises a first resistance-capacitance branch and at least one second resistance-capacitance branch, and the first resistance-capacitance branch is connected in parallel with the at least one second resistance-capacitance branch, wherein the first resistance-capacitance branch comprises a first resistor and a first capacitor connected in series, and each of the at least one second resistance-capacitance branch comprises a second resistor and a second capacitor connected in series; and
the controller is configured to detect a current at the output terminal of the low dropout linear voltage regulator and generate one or more control signals according to the current to control connection and disconnection of each of the at least one second resistance-capacitance branch in the dynamic Miller compensation network.
The low dropout linear voltage regulator according to claim 1 , further comprising: a first feedback resistor and a second feedback resistor, wherein a first terminal of the first feedback resistor and a first terminal of the second feedback resistor are connected to each other and are connected to a positive input terminal of the error amplifier, a second terminal of the first feedback resistor is connected to the output terminal of the low dropout linear voltage regulator, and a second terminal of the second feedback resistor is grounded.
The low dropout linear voltage regulator according to claim 2 , further comprising a zero generator having a third resistor and a zero generator switch, wherein the third resistor is connected in series with the first resistor and the first capacitor separately after being connected in parallel with the zero generator switch, and a control signal for the zero generator switch and any control signal for the dynamic Miller compensation network are out-of-phase.
The low dropout linear voltage regulator according to claim 2 , further comprising: at least one gain amplifier, wherein the at least one gain amplifier is in one-to-one correspondence with the at least one second resistance-capacitance branch, wherein the second resistor in each of the at least one second resistance-capacitance branch is connected in parallel with a corresponding one of the at least one gain amplifier.
wherein the second resistor in each of the at least one second resistance-capacitance branch is connected in parallel with a corresponding one of the at least one gain amplifier.
The low dropout linear voltage regulator according to claim 4 , further comprising a zero generator having a third resistor and a zero generator switch, wherein the third resistor is connected in series with the first resistor and the first capacitor separately after being connected in parallel with the zero generator switch, and a control signal for the zero generator switch and any control signal for the dynamic Miller compensation network are out-of-phase.
The low dropout linear voltage regulator according to claim 4 , wherein the at least one gain amplifier has a gain of 1.
The low dropout linear voltage regulator according to claim 6 , further comprising a zero generator having a third resistor and a zero generator switch, wherein the third resistor is connected in series with the first resistor and the first capacitor separately after being connected in parallel with the zero generator switch, and a control signal for the zero generator switch and any control signal for the dynamic Miller compensation network are out-of-phase.
The low dropout linear voltage regulator according to claim 4 , further comprising: a secondary amplifier, wherein the secondary amplifier is connected in series with the error amplifier and the power transistor, wherein a first terminal of the secondary amplifier is connected to the output terminal of the error amplifier, and a second terminal of the secondary amplifier is connected to the gate of the power transistor.
The low dropout linear voltage regulator according to claim 8 , further comprising a zero generator having a third resistor and a zero generator switch, wherein the third resistor is connected in series with the first resistor and the first capacitor separately after being connected in parallel with the zero generator switch, and a control signal for the zero generator switch and any control signal for the dynamic Miller compensation network are out-of-phase.
The low dropout linear voltage regulator according to claim 8 , wherein the secondary amplifier is a voltage buffer.
The low dropout linear voltage regulator according to claim 10 , further comprising a zero generator having a third resistor and a zero generator switch, wherein the third resistor is connected in series with the first resistor and the first capacitor separately after being connected in parallel with the zero generator switch, and a control signal for the zero generator switch and any control signal for the dynamic Miller compensation network are out-of-phase.
The low dropout linear voltage regulator according to claim 10 , wherein the voltage buffer comprises a first insulated gate transistor, a second insulated gate transistor, a third insulated gate transistor, a fourth insulated gate transistor, a fifth insulated gate transistor, a sixth insulated gate transistor and a seventh insulated gate transistor, wherein a gate of the seventh insulated gate transistor is connected to a gate of the sixth insulated gate transistor, a source of the seventh insulated gate transistor is connected to a source of the second insulated gate transistor, a source of the first insulated gate transistor and a drain of the sixth insulated gate transistor separately, a drain of the seventh insulated gate transistor is connected to an output terminal of the voltage buffer and a gate of the second insulated gate transistor separately; and a source of the sixth insulated gate transistor is connected to a source of the fif
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