Office Action 1: Non-Final Rejection (2023-08-17)
Rejection types: 102 - Lack of Novelty, 103 - Obviousness

CLAIMS:
LIST OF CURRENT CLAIMS

1\. (Currently Amended) A chip package structure, omprising:
a glass substrate, wherein a first surface of the glass substrate has solder joints and a second surface of the glass substrate has substrate solder balls; (-), a routing layer, wherein the routing layer is located in the glass substrate and the solder joints are electrically connected to the substrate solder balls by using the routing layer; , and
a plurality of dies, wherein
ach die has chip solder balls, is located on the first surface of the glass substrate , and the solder joints are bonded to the chip solder balls .

2\. (Currently Amended) The chip package structure according to claim 1, wherein the glass substrate comprises a plurality of glass layers,\_ there is at least one routing layer (-, and each routing layer (- is located between two adjacent glass layers .

3\. (Currently Amended) The chip package structure according to claim 1, wherein the first surface of the glass substrate has a groove some dies of the plurality of dies are located in the groove (16), and ther dies of the plurality of dies are located outside the groove .

4\. (Currently Amended) The chip package structure according to claim 3, wherein the groove comprises a groove bottom and n steps,\_ the n steps are located on two sides of the groove bottom n is a positive integer, some dies of the plurality of dies in the groove are located on the groove bottom , and the other dies of the plurality of dies are located on an upper surface of an ith ste in the n steps , wherein i is set to a value from 1 to n.
5\. (Currently Amended) The chip package structure according to claim 4, wherein each step comprises a first sub-ste and a second sub-step the first sub-step and the second sub-ste are respectively located on the two sides of the groove bottom in opposite positionsi and one end of ach die on the upper surface of the ith ste is located on an upper surface of the first sub-ste, and the other end of the each die is located on an upper surface of the second sub-ste.

6\. (Currently Amended) The chip package structure according to claim 3, wherein one end of ach die outside the groove is located on a first side of the groove , the other end of ach die is located on a second side of the groove , and the first side and the second side of the groove are in opposite positions.

7\. (Currently Amended) A chip package structure preparation method comprising :
distributing a routing layer in a glass substrate; disposing solder joints on a first surface of the glass substrate;
disposing substrate solder balls on a second surface of the glass substrate , wherein the solder joints are electrically connected to the substrate solder balls by using the routing layer ;
disposing chip solder balls on a surface of each die of at least one die ;
fastening the at least one die to the first surface of the glass substrate; and
bonding the solder joints to the chip solder balls .

8\. (Currently Amended) The method according to claim 7, wherein the glass substrate comprises m glass layers , and m is a positive integer greater than 1 and the distributing -a the routing layer in -a the glass substrate further comprises:
distributing a copper layer on a surface of a kth glass layers
performing circuit printing on the copper layer to form the routing layer on the surface of the kth glass layer ; and
fastening a (k+1)th glass layer to a surface of the routing layer to obtain the glass substrate with the routing layer distributed between the two adjacent glass layers , wherein k is set to a value from 1 to m-1.
9\. (Currently Amended) The method according to claim 7, wherein the first surface of the glass substrate has a groove, there are a plurality of dies, and the fastening of the at least one die to the first surface of the glass substrate further comprises:
fastening some dies of the plurality of dies in the groove; and
fastening ther dies of the plurality of dies outside the groove .

10\. (Currently Amended) The method according to claim 9, wherein the groove comprises a groove bottom and n steps , the n steps are located on two sides of the groove bottom , wherein n is a positive integer; and the fastening some dies of the plurality of dies in the groove further comprises:
fastening some dies of the plurality of dies on the groove bottom ; and
fastening the other dies of the plurality of dies to an upper surface of an ith step in the n steps , wherein i is set to a value from 1 to n.

11\. (Currently Amended) The method according to claim 10, wherein each ste comprises a first sub-step and a second sub-ste, and the first sub-ste and the second sub-ste are respectively located on the two sides of the groove bottom in opposite positions, and the fastening the other dies of the plurality of dies to an upper surface of an ith ste in the n steps further comprises:
fastening one end of the each die to an upper surface of the first sub-ste of the ith step in the n steps; and
fastening the other end o each die to an upper surface of the second sub-ste of the i' step .

12\. (Currently Amended) The method according to claim 9, wherein the fastening of the other dies of the plurality of dies outside the groove comprises:
fastening one end of the die to a first side of the groove; and
fastening the other end of the die to a second side of the groove , wherein the first side and the second side of the groove are in opposite positions.

13\. (Currently Amended) An electronic device comprising a chip package structure, and the chip package structure comprises:
a glass substrate, wherein a first surface of the glass substrate has solder joints and a second surface of the glass substrate has substrate solder balls; a routing layer, wherein the routing layer is located in the glass substrate and the solder joints are electrically connected to the substrate solder balls by using the routing layer; and
a plurality of dies, wherein
ach die has chip solder balls is located on the first surface of the glass substrate , and the solder joints are bonded to the chip solder balls .

14\. (Currently Amended) The electronic device according to claim 13, wherein the glass substrate comprises a plurality of glass layers\_ there is at least one routing layer -2, and each routing layer 2 is located between two adjacent glass layers .

15\. (Currently Amended) The electronic device according to claim 13, wherein the first surface of the glass substrate has a groove , some dies of the plurality of dies are located in the groove , and the other dies of the plurality of dies are located outside the groove .

16\. (Currently Amended) The electronic device according to claim 15, wherein the groove comprises a groove bottom and n steps the n steps are located on two sides of the groove bottom n is a positive integer; and some dies of the plurality of dies in the groove are located on the groove bottom , and the other dies of the plurality of dies are located on an upper surface of an ith ste in the n steps , wherein i is set to a value from 1 to n.

17\. (Currently Amended) The electronic device according to claim 16, wherein each step comprises a first sub-ste and a second sub-ste, and the first sub-step and the second sub-ste are respectively located on the two sides of the groove bottom in opposite positions, one end of the each die on the upper surface of the ith ste is located on an upper surface of the first sub-ste, and the other end of the each die is located on an upper surface of the second sub-ste.
18\. (Currently Amended) The electronic device according to claim 15, wherein the one end of he each die outside the groove is located on a first side of the groove , the other end of ach die is located on a second side of the groove , and the first side of the groove and the second side of the groove are in opposite positions.
5 6 7 8 9

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA  35 U.S.C. 102 and 103 (or as subject to pre-AIA  35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA  to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 7, 9, 13, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eisherbini et al. (US 2020/0364600, hereinafter, Eisherbini.)
In regard to claims 1, 7, and 13, in fig. 1, Eisherbini discloses a chip package structure, comprising:
a glass substrate (para [0040]), wherein a first surface of the glass substrate has solder joints, or contact, 146 (para [0040]) and a second surface of the glass substrate has substrate solder balls 137 (para [0055]);
a routing layer, wherein the routing layer is located in the glass substrate and the solder joints are electrically connected to the substrate solder balls by using the routing layer, fig. 1; and
a plurality of dies 114 (para [0040]), wherein each die has chip solder balls is located on the first surface of the glass substrate, and the solder joints are bonded to the chip solder balls.
Regarding claims 3 and 9, and 15, wherein the first surface of the glass substrate has a groove, or recess, 108 (para [0040]), some dies of the plurality of dies are located in the groove, and other dies of the plurality of dies are located outside the groove. Fig. 6.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 8, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eisherbini as applied to claim 1 above, and further in view of MASUKAWA et al. (US 2018/0277395, hereinafter, Masukawa.)
Regarding claims 2 and 8, 14, Eisherbini discloses all of the claimed limitations as mentioned above. Eisherbini also further mentions that the substrate may be formed of multiple layers (para [0041]) wherein the routing layers formed inside the substrate, except, wherein each routing layer is located between two adjacent glass layers.
Masukawa, in figs. 1b and 4a-d, discloses an analogous semiconductor device including a glass substrate 101/280 (para [0039]), a cavity111 (para [0039]) in the substrate, and electrical contacts 112/113 (para [0039]) on both sides of the substrate, and routing elements are formed between layers, fig. 4a. Masukawa further teaches the substrate is a laminated substrate (para [0063]), and the routing elements are formed in between in order to provide protection, support, and external connection. This is common in the art.
Therefore, it would have been obvious to one of ordinary skill in the art to use the laminate substrate as taught in order to provide protection, support, and external connection.
Furthermore, regarding claim 8, the combination of Eisherbini and Matsukawa further discloses the routing layers comprises copper and the method of printing to form conductive traces (Eisherbini’s para [0048] and Matsukawa’s para [0051].)
Claim(s) 4-6, 10-12, and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eisherbini as applied to claims 1 and 3 above, and further in view of Kang (US 2004/0154164.)
In regard to claims 4 and 5, and 10-11, 16-17, Eisherbini discloses all of the claimed limitations as mentioned above. Eisherbini also further discloses n steps located on the side of the groove (fig. 7), except on both sides.
Kang, in fig. 2, discloses an analogous device including a ceramic (glass) substrate 204 (para [0012]). The substrate further includes n steps on both sides in order to provide additional connection to additional die. Thus, is common in the art.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the application was filed to have additional steps or substeps as taught in order to create additional contact area.
Regarding claims 6, 12, and 18, Kang further discloses wherein one end of each die outside the groove is located on a first side of the groove, the other end of each die is located on a second side of the groove, and the first side and the second side of the groove are in opposite positions. Fig. 2.
Conclusion


NEXT OFFICE ACTION: DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA  35 U.S.C. 102 and 103 (or as subject to pre-AIA  35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA  to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 7, 9, 13, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eisherbini et al. (US 2020/0364600, previously cited hereinafter, Eisherbini.)
In regard to claims 1, 7, and 13, in fig. 1, Eisherbini discloses a chip package structure, comprising:
a glass substrate (para [0040]), wherein a first surface of the glass substrate has solder joints, or contact, 146 (para [0040]) and a second surface of the glass substrate has substrate solder balls 137 (para [0055]);
a routing layer, wherein the routing layer is located in the glass substrate and the solder joints are electrically connected to the substrate solder balls by using the routing layer, fig. 1; and
a plurality of dies 114 (para [0040]), wherein each die has chip solder balls is located on the first surface of the glass substrate, and the solder joints are bonded to the chip solder balls, and wherein a coefficient of thermal expansion of each die of the plurality of dies is close to a coefficient of thermal expansion of the glass substrate. The CTE of the element is close because the substrate is made of glass and the die is made from semiconductor materials. This is known to one of ordinary skill in the art.
Regarding claims 3 and 9, and 15, wherein the first surface of the glass substrate has a groove, or recess, 108 (para [0040]), some dies of the plurality of dies are located in the groove, and other dies of the plurality of dies are located outside the groove. Fig. 6.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 8, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eisherbini as applied to claim 1 above, and further in view of MASUKAWA et al. (US 2018/0277395, previously cited, hereinafter, Masukawa.)
Regarding claims 2 and 8, 14, Eisherbini discloses all of the claimed limitations as mentioned above. Eisherbini also further mentions that the substrate may be formed of multiple layers (para [0041]) wherein the routing layers formed inside the substrate, except, wherein each routing layer is located between two adjacent glass layers.
Masukawa, in figs. 1b and 4a-d, discloses an analogous semiconductor device including a glass substrate 101/280 (para [0039]), a cavity111 (para [0039]) in the substrate, and electrical contacts 112/113 (para [0039]) on both sides of the substrate, and routing elements are formed between layers, fig. 4a. Masukawa further teaches the substrate is a laminated substrate (para [0063]), and the routing elements are formed in between in order to provide protection, support, and external connection. This is common in the art.
Therefore, it would have been obvious to one of ordinary skill in the art to use the laminate substrate as taught in order to provide protection, support, and external connection.
Furthermore, regarding claim 8, the combination of Eisherbini and Matsukawa further discloses the routing layers comprises copper and the method of printing to form conductive traces (Eisherbini’s para [0048] and Matsukawa’s para [0051].)
Claim(s) 4-6, 10-12, and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eisherbini as applied to claims 1 and 3 above, and further in view of Kang (US 2004/0154164.)
In regard to claims 4 and 5, and 10-11, 16-17, Eisherbini discloses all of the claimed limitations as mentioned above. Eisherbini also further discloses n steps located on the side of the groove (fig. 7), except on both sides.
Kang, in fig. 2, discloses an analogous device including a ceramic (glass) substrate 204 (para [0012]). The substrate further includes n steps on both sides in order to provide additional connection to additional die. Thus, is common in the art.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the application was filed to have additional steps or substeps as taught in order to create additional contact area.
Regarding claims 6, 12, and 18, Kang further discloses wherein one end of each die outside the groove is located on a first side of the groove, the other end of each die is located on a second side of the groove, and the first side and the second side of the groove are in opposite positions. Fig. 2.
Response to Arguments
Applicant's arguments filed 11/14/23 have been fully considered but they are not persuasive. The Applicant argues that the cited art, Elsherbini, does not disclose the newly added claimed limitation, wherein a coefficient of thermal expansion (CTE) of each die of the plurality of dies is close to a coefficient of thermal expansion of the glass substrate, by reasoning that the cited reference is teaching away from the newly added claimed limitation (see the remarks’ pages 8-9.) The Examiner respectfully disagrees. In fact the term “close” limitation is vague and broad in light if the specification. Thus, without a specific range it is not clear how close is a close value. The cited reference, Elsherbini, discloses an analogous semiconductor package. The substrate of the package is made of glass that is the same material of the substrate as currently claimed (para [0041].) And the die is also a semiconductor die that is made of similar martial as the currently claimed die, semiconductor materials, for example (para [0040].) Therefore, these materials would inherently have the similar CTEs as currently claimed and considered to be relatively close in value. It is known to one of ordinary skill in the art. Therefore, the prior art indeed discloses all of the claimed limitations as discussed above and the rejection remains the same.
Conclusion
THIS ACTION IS MADE FINAL.  Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action.  In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action.  In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.

CITED REFERENCE SUMMARIES: Ref US20040154164A1: [content unavailable]
Ref US20150279756A1: Claims:
- 22 . (canceled)
A starting substrate for MEMS engineering comprising a thin glass wafer having silicon vias, wherein the silicon is doped to increase conductivity, such that a resistance of down to 1Î© is provided.
The substrate according to claim 23 , wherein the vias comprise a metal coating to provide highly conductive connections through the glass.
The substrate according to claim 23 , which has a pitch via-to-via of 100-500 Î¼m.
The substrate according to claim 23 , wherein the metal coating comprises a member of the group consisting of copper (Cu), Au, Ag, Pt and Ru, or combinations such as alloys thereof.
The substrate according to claim 23 , wherein the silicon vias further comprise a diffusion barrier for preventing metal diffusion into the silicon, the diffusion barrier being a layer of an element from the group consisting of Ni, W, Ti, TiN, Ni, Ru, and Ta or alloys thereof.
The substrate according to claim 23 , wherein the metal coating is provided by a method selected from a method which is a member of the group consisting of plating, both electroplating and electroless plating, deposition of metal by physical techniques (PVD), chemical methods (CVD), ALD, evaporation, deposition from solutions.
A device, comprising a silicon substrate ( 100 ; 200 ) having a cavity ( 102 ) in which a MEMS component ( 104 ) is accommodated, and a cap wafer ( 300 ) made of a material having a low dielectric constant, preferably glass, said cap wafer having through substrate vias of metal, said cap wafer being bonded to the silicon substrate.
The device according to claim 29 , wherein the cap wafer comprises a depression ( 109 ) for accommodating movements of said MEMS component ( 104 ).
The device according to claim 29 , wherein the MEMS component ( 104 ) is monolithically integrated in a substrate ( 200 ) provided between the silicon substrate ( 100 ) and the cap wafer ( 300 ), and wherein the cap wafer comprises a depression ( 109 ) for accommodating movements of said MEMS component ( 104 ).
Ref US20230189442A1: Claims:
A microelectronic board, comprising: a board substrate, wherein the board substrate has a first thickness between a first surface and a second surface opposite from the first surface; a recess into the first surface of the board substrate, wherein the recess comprises a third surface between the first surface and the second surface, and wherein the board substrate has a second thickness between the third surface and the second surface; and a voltage regulator (VR) module attached to the third surface.
a board substrate, wherein the board substrate has a first thickness between a first surface and a second surface opposite from the first surface;
a recess into the first surface of the board substrate, wherein the recess comprises a third surface between the first surface and the second surface, and wherein the board substrate has a second thickness between the third surface and the second surface; and
a voltage regulator (VR) module attached to the third surface.
The microelectronic board of claim 1 , wherein the VR module comprises one or more inductors.
The microelectronic board of claim 1 , further comprising: a plurality of conductive layers embedded in the board substrate, and wherein the recess passes through at least one of the plurality of conductive layers.
a plurality of conductive layers embedded in the board substrate, and wherein the recess passes through at least one of the plurality of conductive layers.
The microelectronic board of claim 3 , wherein the plurality of conductive layers comprises at least five conductive layers, and wherein the recess passes through at least three conductive layers.
The microelectronic board of claim 1 , further comprising: a capacitor attached to the third surface.
a capacitor attached to the third surface.
The microelectronic board of claim 1 , further comprising: a fill material that fills the recess, wherein the fill material is thermally conductive.
a fill material that fills the recess, wherein the fill material is thermally conductive.
The microelectronic board of claim 6 , wherein the VR module is fully embedded in the fill material.
The microelectronic board of claim 1 , wherein the first thickness is approximately 3.0 mm or greater.
The microelectronic board of claim 8 , wherein the second thickness is approximately 1.0 mm or less.
The microelectronic board of claim 1 , wherein the first surface of the board substrate is a backside surface, and wherein the second surface is configured to receive an electronic package.
An electronic system, comprising: a board with a first surface and a second surface opposite from the first surface, and a recess into the first surface; a voltage regulator (VR) module in the recess; a package substrate attached to the second surface of the board; and a die attached to the package substrate.
a board with a first surface and a second surface opposite from the first surface, and a recess into the first surface;
a voltage regulator (VR) module in the recess;
a package substrate attached to the second surface of the board; and
a die attached to the package substrate.
The electronic system of claim 11 , wherein the package substrate is attached to the board with a socket.
The electronic system of claim 11 , wherein the package substrate is attached to the board with a ball grid array (BGA).
The electronic system of claim 11 , further comprising: capacitors on a surface of the package substrate facing the board.
capacitors on a surface of the package substrate facing the board.
The electronic system of claim 11 , wherein the package substrate is attached to the second surface of the board with a full grid array.
The electronic system of claim 11 , further comprising: a capacitor in the recess.
a capacitor in the recess.
The electronic system of claim 11 , further comprising: a fill material that fills the recess, wherein the fill material is thermally conductive.
The electronic system of claim 17 , wherein the VR module is embedded by the fill material.
An electronic system, comprising: a microelectronic board, wherein the microelectronic board comprises: a board substrate, wherein the board substrate has a first thickness between a first surface and a second surface opposite from the first surface; a recess into the first surface of the board substrate, wherein the recess comprises a third surface between the first surface and the second surface, and wherein the board substrate has a second thickness between the third surface and the second surface; and a voltage regulator (VR) module attached to the third surface; a package substrate attached to the second surface of the board substrate; and a die attached to the package substrate.
a microelectronic board, wherein the microelectronic board comprises: a board substrate, wherein the board substrate has a first thickness between a first surface and a second surface opposite from the first surface; a recess into the first surface of the board substrate, wherein the recess comprises a third surface between the first surface and the second surface, and wherein the board substrate has a second thickness between the third surface and the second surface; and a voltage regulator (VR) module attached to the third surface;
a voltage regulator (VR) module attached to the third surface;
a package substrate attached to the second surface of the board substrate; and
The electronic system of claim 19 , further comprising: a fill material that fills the recess, wherein the fill material is thermally conductive, and wherein the fill material embeds the VR module.
a fill material that fills the recess, wherein the fill material is thermally conductive, and wherein the fill material embeds the VR module.
Ref US20220130741A1: Claims:
A package, comprising: a substrate having a first region comprising a number N of metallization layers and a second region comprising a number M of metallization layers, where M is less than N; a passive component disposed within the second region on a first surface of the substrate; and a die disposed within the second region on a second surface of the substrate opposite the first surface of the substrate, the die being electrically coupled to the passive component by at least one of the number M of metallization layers within the second region.
a substrate having a first region comprising a number N of metallization layers and a second region comprising a number M of metallization layers, where M is less than N;
a passive component disposed within the second region on a first surface of the substrate; and
a die disposed within the second region on a second surface of the substrate opposite the first surface of the substrate, the die being electrically coupled to the passive component by at least one of the number M of metallization layers within the second region.
The package of claim 1 , wherein the first region has a first thickness T 1 and the second region has a second thickness T 2 less than T 1 .
The package of claim 1 , wherein M=1.
The package of claim 1 , wherein M>1.
The package of claim 1 , wherein the die is electrically coupled to the package using a die-to-wafer connection.
The package of claim 1 , wherein the die is part of a flip-chip package.
The package of claim 1 , wherein the passive component comprises a line-side component.
The package of claim 7 , wherein the line-side component comprises a line-side capacitor, resistor, or inductor.
The package of claim 1 , wherein the metallization layers comprise copper.
The package of claim 1 , wherein the substrate comprises pre-preg (PPG).
The package of claim 1 , wherein at least one metallization layer comprises a redistribution layer.
A method for fabricating a package, the method comprising: providing a substrate having a first region comprising a number N of metallization layers and a second region comprising a number M of metallization layers, where M is less than N; providing a passive component disposed within the second region on a first surface of the substrate; and providing a die disposed within the second region on a second surface of the substrate opposite the first surface of the substrate, the die being electrically coupled to the passive component by at least one of the number M of metallization layers within the second region.
providing a substrate having a first region comprising a number N of metallization layers and a second region comprising a number M of metallization layers, where M is less than N;
providing a passive component disposed within the second region on a first surface of the substrate; and
providing a die disposed within the second region on a second surface of the substrate opposite the first surface of the substrate, the die being electrically coupled to the passive component by at least one of the number M of metallization layers within the second region.
The method of claim 12 , wherein the first region has a first thickness T 1 and the second region has a second thickness T 2 less than T 1 .
The method of claim 12 , wherein M=1.
The method of claim 12 , wherein M>1.
The method of claim 12 , wherein the die is electrically coupled to the package using a die-to-wafer connection.
The method of claim 12 , wherein the die is part of a flip-chip package.
The method of claim 12 , wherein the passive component comprises a line-side component.
The method of claim 18 , wherein the line-side component comprises a line-side capacitor, resistor, or inductor.
The method of claim 12 , wherein the metallization layers comprise copper.
The method of claim 12 , wherein the substrate comprises pre-preg (PPG).
The method of claim 12 , wherein at least one metallization layer comprises a redistribution layer.
Ref US20200273839A1: Claims:
A microelectronic assembly, comprising: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, first conductive contacts at the first surface of the second die, and second conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second conductive contacts of the second die are not coupled to conductive contacts at the second surface of the first die, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is contained within a footprint of the second die.
a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and
a second die having a first surface and an opposing second surface, first conductive contacts at the first surface of the second die, and second conductive contacts at the first surface of the second die;
wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second conductive contacts of the second die are not coupled to conductive contacts at the second surface of the first die, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is contained within a footprint of the second die.
The microelectronic assembly of claim 1 , wherein the first die has a thickness between 10 microns and 30 microns.
The microelectronic assembly of claim 1 , wherein the second die has a thickness between 50 microns and 750 microns.
The microelectronic assembly of claim 1 , wherein the first die is a central processing unit or a graphics processing unit, and the second die includes a memory device.
The microelectronic assembly of claim 1 , wherein the first die includes a silicon die substrate and the second die includes a non-silicon die substrate.
The microelectronic assembly of claim 1 , wherein the second die includes power delivery switches or radio frequency switches.
The microelectronic assembly of claim 1 , wherein the second die includes a III-V material.
A microelectronic assembly, comprising: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die;
a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die;
wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.
The microelectronic assembly of claim 8 , wherein the interconnects are metal-to-metal interconnects.
The microelectronic assembly of claim 8 , wherein the interconnects include an anisotropic conductive material.
The microelectronic assembly of claim 8 , wherein a distance from the first surface of the second die to the first surface of the first die is less that a height of the second conductive contacts of the second die.
The microelectronic assembly of claim 8 , wherein a distance from the first surface of the second die to the first surface of the first die is more than a height of the second conductive contacts of the second die.
The microelectronic assembly of claim 8 , wherein the interconnects are first interconnects, the second die further includes second conductive contacts at the first surface of the second die, and the microelectronic assembly further includes: a package substrate, wherein the first conductive contacts of the first die are coupled to conductive contacts of the package substrate with second interconnects, and the second conductive contacts of the second die are coupled to conductive contacts of the package substrate with third interconnects.
a package substrate, wherein the first conductive contacts of the first die are coupled to conductive contacts of the package substrate with second interconnects, and the second conductive contacts of the second die are coupled to conductive contacts of the package substrate with third interconnects.
The microelectronic assembly of claim 13 , wherein the package substrate includes a recess, and the first die is at least partially in the recess.
The microelectronic assembly of claim 13 , wherein the package substrate includes an embedded bridge, and at least some of the first conductive contacts of the first die or the second conductive contacts of the second die are coupled to conductive contacts of the embedded bridge.
The microelectronic assembly of claim 15 , further comprising: a third die having at least some conductive contacts coupled to conductive contacts of the embedded bridge by fourth interconnects.
a third die having at least some conductive contacts coupled to conductive contacts of the embedded bridge by fourth interconnects.
A method of manufacturing a microelectronic assembly, comprising: coupling a first surface of a first die to a carrier, wherein the first die has the first surface and an opposing second surface, the first die has first conductive contacts are at the first surface of the first die, and the first die has second conductive contacts at the second surface of the first die; forming interconnects between the second conductive contacts of the first die and first conductive contacts of a second die, wherein the second die has a first surface and an opposing second surface, the second die has first conductive contacts at the first surface of the second die, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is contained within a footprint of the second die; and after forming the interconnects, removing the carrier.
coupling a first surface of a first die to a carrier, wherein the first die has the first surface and an opposing second surface, the first die has first conductive contacts are at the first surface of the first die, and the first die has second conductive contacts at the second surface of the first die;
forming interconnects between the second conductive contacts of the first die and first conductive contacts of a second die, wherein the second die has a first surface and an opposing second surface, the second die has first conductive contacts at the first surface of the second die, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is contained within a footprint of the second die; and
after forming the interconnects, removing the carrier.
The method of claim 17 , wherein the second die is one of a plurality of second dies included in a wafer when forming the interconnects.
The method of claim 17 , wherein the second die is a packaged die when forming the interconnects.
The method of claim 17 , wherein the second die is an unpackaged die when forming the interconnects.
The method of claim 17 , wherein the interconnects are first interconnects, the second die further includes second conductive contacts at the first surface of the second die, and the method further includes: forming second interconnects between the first conductive contacts of the first die and con
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