Office Action 4: Final Rejection (2024-11-25)
Rejection types: 102 - Lack of Novelty, 103 - Obviousness, 112 - Written Description/Enablement

CLAIMS:
AMENDMENTS TO THE CLAIMSPlease AMEND claims 1, 7, 9, and 13 as shown below.

The following list of claims replaces any prior listing of claims:

1\. (Currently Amended) A chip package structure; comprising:
a glass substrate, wherein a first surface of the glass substrate has solder joints and a second surface of the glass substrate has substrate solder balls;
a routing layer, wherein the routing layer is located in the glass substrate and the solder joints are electrically connected to the substrate solder balls by using the routing layer; and
a plurality of dies, wherein a gap having a specific distance is defined between vertically adjacent dies of the plurality of dies, each die has chip solder balls, is located on the first surface of the glass substrate, and the solder joints are bonded to the chip solder balls.

2\. (Previously Presented) The chip package structure according to claim 1, wherein the glass substrate comprises a plurality of glass layers, there is at least one routing layer, and each routing layer is located between two adjacent glass layers.

3\. (Previously Presented) The chip package structure according to claim 1, wherein the first surface of the glass substrate has a groove, some dies of the plurality of dies are located in the groove, and other dies of the plurality of dies are located outside the groove.

4\. (Previously Presented) The chip package structure according to claim 3, wherein the groove comprises a groove bottom and n steps, the n steps are located on two sides of the groove bottom, n is a positive integer, some dies of the plurality of dies in the groove are located on the groove bottom, and the other dies of the plurality of dies are located on an upper surface of an fi step in the n steps, wherein i is set to a value from 1 to n.

5\. (Previously Presented) The chip package structure according to claim 4, wherein each step comprises a first sub-step and a second sub-step, the first sub-step and the second sub-step are respectively located on the two sides of the groove bottom in opposite positions and one end of each die on the upper surface of the ithstep islocated on an upper surface of the first sub-step, and the other end of each die is located on an upper surface of the second sub-step.

6\. (Previously Presented) The chip package structure according to claim 3, wherein one end of each die outside the groove is located on a first side of the groove, the other end of each die is located on a second side of the groove, and the first side and the second side of the groove are in opposite positions.

7\. (Currently Amended) A method comprising:
distributing a routing layer in a glass substrate;
disposing solder joints on a first surface of the glass substrate;
disposing substrate solder balls on a second surface of the glass substrate, wherein the solder joints are electrically connected to the substrate solder balls by using the routing layer;

disposing chip solder balls on a surface of each die of a plurality of dies ;
fastening the plurality of dies to the first surface of the glass substrate, wherein a gap having a specific distance is defined between vertically adjacent dies of the plurality of dies;
and bonding the solder joints to the chip solder balls.

8\. (Previously Presented) The method according to claim 7, wherein the glass substrate comprises m glass layers, m is a positive integer greater than 1, and distributing the routing layer in the glass substrate further comprises:
distributing a copper layer on a surface of a k\* glass layer;
performing circuit printing on the copper layer to form the routing layer on the surface of the k\* glass layer; and
fastening a (k+1)\* glass layer to a surface of the routing layer to obtain the glass substrate with the routing layer distributed between the two adjacent glass layers, wherein k is set to a value from 1 to m-1.

9\. (Currently Amended) The method according to claim 7, wherein the first surface of the glass substrate has a groove and the fastening of the plurality of dies to the first surface of the glass substrate further comprises:
fastening some dies of the plurality of dies in the groove; and

fastening other dies of the plurality of dies outside the groove.

10\. (Previously Presented) The method according to claim 9, wherein the groove comprises a groove bottom and n steps, the n steps are located on two sides of the groove bottom, n is a positive integer, and fastening some dies of the plurality of dies in the groove further comprises:
fastening some dies of the plurality of dies on the groove bottom; and
fastening the other dies of the plurality of dies to an upper surface of an ith step in the n steps, wherein i is set to a value from 1 to n.

11\. (Previously Presented) The method according to claim 10, wherein each step comprises a first sub-step and a second sub-step, the first sub-step and the second sub-step are respectively located on the two sides of the groove bottom in opposite positions, fastening the other dies of the plurality of dies to the upper surface of the ith step in the n steps further comprises:
fastening one end of each die to an upper surface of the first sub-step of the ith step in the n steps; and
fastening the other end of each die to an upper surface of the second sub-step of the ithstep.

12\. (Previously Presented) The method according to claim 9, wherein the fastening of the other dies of the plurality of dies outside the groove comprises:
fastening one end of the die to a first side of the groove; and
fastening the other end of the die to a second side of the groove, wherein the first side and the second side of the groove are in opposite positions.

13\. (Currently Amended) An electronic device comprising a chip package structure, and the chip package structure comprises:
a glass substrate, wherein a first surface of the glass substrate has solder joints and a second surface of the glass substrate has substrate solder balls;
a routing layer, wherein the routing layer is located in the glass substrate and the solder joints are electrically connected to the substrate solder balls by using the routing layer; and
a plurality of dies, wherein a gap having a specific distance is defined between vertically adjacent dies of the plurality of dies, each die has chip solder balls, is located on the first surface of the glass substrate, and the solder joints are bonded to the chip solder balls.

14\. (Previously Presented) The electronic device according to claim 13, wherein the glass substrate comprises a plurality of glass layers, there is at least one routing layer, and each routing layer is located between two adjacent glass layers.

15\. (Previously Presented) The electronic device according to claim 13, wherein the first surface of the glass substrate has a groove, some dies of the plurality of dies are located in the groove, and other dies of the plurality of dies are located outside the groove.

16\. (Previously Presented) The electronic device according to claim 15, wherein the groove comprises a groove bottom and n steps, the n steps are located on two sides of the groove bottom, n is a positive integer, and some dies of the plurality of dies in the groove are located on the groove

bottom, and the other dies of the plurality of dies are located on an upper surface of an fi\* step in the n steps, wherein i is set to a value from 1 to n.

17\. (Previously Presented) The electronic device according to claim 16, wherein each step comprises a first sub-step and a second sub-step, and the first sub-step and the second sub-step are respectively located on the two sides of the groove bottom in opposite positions, one end of each die on the upper surface of the fi step is located on an upper surface of the first sub-step, and the other end of each die is located on an upper surface of the second sub-step.

18\. (Previously Presented) The electronic device according to claim 15, wherein the one end of each die outside the groove is located on a first side of the groove, the other end of each die is located on a second side of the groove, and the first side of the groove and the second side of the groove are in opposite positions.

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA  35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA  35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 1, 7, and 13 recite a new limitation, “a gap having a specific distance”. The new limitation renders new matter situation because the original specification does not describe the specific distance of the gap in detail directly or inherently that would be understood by one of ordinary skill in the art, i.e. a value that is associated with it. The specification merely discloses the limitation.
The following is a quotation of 35 U.S.C. 112(b):
(b)  CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA  35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 7, and 13 recite a new limitation, “a gap having a specific distance”, in lines 6, 8, and 7, respectively. The new limitation renders indefinite situation because the original specification does not describe the limitation directly or inherently that would be understood by one of ordinary skill in the art. The phrase ““a gap having a specific distance”, therefore, is unclear since there is not an actual value that was mentioned to further make it specific. Therefore, for the examination purposes, the office presumes a gap or a distance between dies may be considered to inherently have a function of separating/insulating the dies.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA  35 U.S.C. 102 and 103 (or as subject to pre-AIA  35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA  to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7, and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Goida et al. (US 2016/0167951, previously cited, hereinafter, Goida.)
In regard to claims 1, 7, and 13, in figs. 1A-1B, for example, Goida discloses a chip package structure, or an integrated device package 1 (para [0028], comprising:
a glass substrate, or an interposer 6 (paras [0028 and 0031]), wherein a first surface of the glass substrate has solder joints (not shown, however, the surface of the substrate has connecting element to accommodate the electrical connection with elements 8 and routing 10 (paras [0030-0031]) and a second surface of the glass substrate has substrate solder balls 9 (para [0034]);
a routing layer 10, wherein the routing layer is located in the glass substrate and the solder joints are electrically connected to the substrate solder balls by using the routing layer; and
a plurality of dies 2/3 (para [0004], where more dies may be formed), the dies are further being separated by a predetermined distance or space creating by element 6, for example, (see the 112 rejections above), wherein each die has chip solder balls 8 (para [0030]), is located on the first surface of the glass substrate, and the solder joints are bonded to the chip solder balls.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 8, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goida as applied to claim 1 above, and further in view of MASUKAWA et al. (US 2018/0277395, previously cited, hereinafter, Masukawa.)
Regarding claims 2 and 8, and 14, Goida discloses all of the claimed limitations as mentioned above. Eisherbini also further mentions that the substrate may be laminated substrate (para [0031]) wherein the routing layers formed inside the substrate, except, further shows the detail wherein each routing layer is located between two adjacent glass layers.
Masukawa, in figs. 1b and 4a-d, discloses an analogous semiconductor device including a glass substrate 101/280 (para [0039]), a cavity111 (para [0039]) in the substrate, and electrical contacts 112/113 (para [0039]) on both sides of the substrate, and routing elements are formed between layers, fig. 4a. Masukawa further teaches the substrate is also a laminated substrate (para [0063]), and the routing elements are formed in between in order to provide protection, support, and external connection. This is common in the art.
Therefore, it would have been obvious to one of ordinary skill in the art to use the laminate substrate as taught in order to provide protection, support, and external connection.
Furthermore, regarding claim 8, the combination of Goida and Matsukawa further discloses the routing layers comprises copper and the method of printing to form conductive traces (Masukawa’s para [0043] and para [0051].)
Claim(s) 3, 6, 9, 12, 15, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goida as applied to claim 1 above, and further in view of Kang (US 2004/0154164, previously cited.)
In regard to claims 3, 6, 9, 12, 15 and 18, Goida discloses all of the claimed limitations as mentioned above and further discloses a groove in the substrate 6, and other dies of the plurality of dies are located outside the groove, except some dies of the plurality of dies are located in the groove.
Kang, in fig. 2, discloses an analogous device including a ceramic (glass) substrate 204 (para [0012]) including a groove with steps on both sides and bottom chip or semiconductor die 206 disposed in and on the bottom of the groove in order to create addition surface area in the package as a whole. This is common in the art. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the application was filed to include the die in the groove a taught in order to create addition surface area in the package as a whole.
Allowable Subject Matter
Claims 4-5, 10-11, and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not show some dies of the plurality of dies in the groove are located on the groove bottom, and the other dies of the plurality of dies are located on an upper surface of an ith step in the n steps.
Response to Arguments
Applicant's arguments filed 8/27/24 have been fully considered but they are not persuasive. The Applicant argues the prior art does not disclose the newly added limitation, “a gap having a specific distance.” As mentioned in the 112 rejections above, this limitation is unclear since it was not clearly defined in the specification. Nevertheless, the dies 2 and 3 as disclosed by Goida in fact is separated by a distance that is created by elements 6, 8, and the interposer (figs. 1A and 1C, for example.) This distance is considered to a specific because it serves its purpose of creating a space for the elements 5 to be formed, for example. Therefore, the prior as disclosed indeed discloses the claimed limitation. Thus, the rejection is maintained.
Conclusion
THIS ACTION IS MADE FINAL.  Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action.  In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action.  In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.

APPLICANT REBUTTAL: REMARKS
Favorable reconsideration of this Application, in light of the following discussion, is respectfully requested. Claims 1-18 were previously presented. Claims 1, 7, 8, and 13 are amended. Claims 2 and 14 are canceled without prejudice or disclaimer. Accordingly, claims 1, 3-13, and 15-18 are pending in the present Application. Applicant submits that upon entry of the present Response, claims 1, 3-13, and 15-18 are in condition for allowance. Moreover, the Applicant submits that no new matter has been introduced by the foregoing amendments.
Allowable Subject Matter
The Office Action objected to claims 4, 5, 10, 11, 16, and 17 for depending upon a rejected base claim but indicated that they would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Applicant acknowledges with appreciation the indication of allowable subject matter.
Re
jections under 35 U.S.C.
§
112(b)
The Office Action rejected claims 1-18 under 35 U.S.C. § 112(b) or 35 U.S.C. § 112, second paragraph as indefinite. Applicant hereby amends these claims so that no further rejection on that basis is anticipated. If, however, the Examiner disagrees, the Examiner is invited to telephone the undersigned who will be happy to work with the Examiner in a joint effort to derive mutually acceptable language.
Re
jection under 35 U.S.C.
§
112(a)
The Office Action rejected claims 1-18 were rejected under 35 U.S.C. § 112(a) or 35 U.S.C. § 112, first paragraph as failing to comply with the written description requirement. Applicant hereby deletes the "specific distance" subject matter cited by the Examiner and respectfully requests withdrawal of these rejection.
Prior Art Rejections
The Office Action rejected claims 1, 7, and 13 under 35 U.S.C. § 102(a)(1) as anticipated by Pub. No. US2016/0167951 to Goida et al. ("Goida").
The Office Action rejected claims 2, 8, and 14 under 35 U.S.C. § 103 as unpatentable over God in view of Pub. No. US2018/0277395 to Masukawa et al. ("Masukawa").
The Office Action rejected claims 3, 6, 9, 12, 15, and 18 under 35 U.S.C. § 103 as unpatentable over Goida in view of Pub. No. US2004/0154164 to Kang ("Kang").
Claim 1, as amended, recites: "a plurality of routing layers, wherein each routing layer is distributed between two adjacent glass layers" (emphasis added). Similar subject matter appears in claims 7 and 13. Paragraph [0065], for example, provides support by disclosing that "a plurality of routing layers 2 may alternatively be distributed between two adjacent glass layers 15. For example, two or more routing layers 2 are stacked and located between two adjacent glass layers 15." This is a modified version of subject matter from claims 2 and 14.
The Office Action conceded that Goida did not disclose this subject matter. To remedy this deficiency, the Examiner cited paragraph [0039] of Masukawa for a glass substrate. Masukawa actually discloses a ceramic substrate 101 and a green sheet laminate 280. Masukawa does not suggest or teach a plurality of routing layers, wherein each routing layer is distributed between two adjacent glass layers, so Masukawa does not remedy Goida's deficiencies.
The other references of record do not remedy Goida's deficiencies. Accordingly, claims 1, 7, and 13 are allowable over the references of record. Claims 2, 3, and 6 depend upon claim 1. Claims 8, 9, and 12 depend upon claim 7. Claims 14, 15, and 18 depend upon claim 13. Thus, claims 2, 3, 6, 8, 9, 12, 14, 15, and 18 are allowable due to their respective dependencies upon allowable claims. Therefore, Applicant respectfully requests withdrawal of these rejections.
CONCLUSION

NEXT OFFICE ACTION: DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 1, 3-13, and 15-18 are allowed.
The following is an examiner’s statement of reasons for allowance:
The arguments and amendments filed on 1/15/25 placed the claims in condition for allowance (see the remarks’ pages 1-3.)
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee.  Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion

CITED REFERENCE SUMMARIES: Ref US20160167951: Claims:
1. An integrated device package comprising:
a first integrated device die; a second integrated device die; an interposer disposed between the first integrated device die and the second integrated device die such that the first integrated device die is mounted to and electrically coupled to a first side of the interposer and the second integrated device die is mounted to and electrically coupled to a second side of the interposer, the first side opposite the second side, wherein the interposer comprises a hole through at least the second side of the interposer, a first portion of the second integrated device die extending into the hole and a second portion of the second integrated device die disposed vertically and laterally outside the hole on the second side of the interposer.
2. The package of claim 1, wherein the hole comprises a through hole through the interposer.
3. The package of claim 1, wherein the hole comprises a recess formed partially through a thickness of the interposer.
4. An integrated device package comprising:
a first integrated device die; a second integrated device die; an interposer disposed between the first integrated device die and the second integrated device die such that the first integrated device die is mounted to and electrically coupled to a first side of the interposer and the second integrated device die is mounted to and electrically coupled to a second side of the interposer, the first side opposite the second side, wherein the interposer comprises a hole through at least the second side of the interposer, a portion of the second integrated device die extending into the hole, wherein the second integrated device die comprises a microelectromechanical systems (MEMS) die, and wherein the portion of the second integrated device die extending into the hole comprises a cap disposed over a MEMS device of the MEMS die.
5. The package of claim 4, wherein the first integrated device die comprises a processor die.
6. The package of claim 1, further comprising an electrical contact disposed on the first side or the second side of the interposer, the electrical contact configured to electrically connect to an external substrate, and wherein the electrical contact has a height that is greater than a thickness of at least one of the first integrated device die and the second integrated device die.
7. The package of claim 6, wherein the electrical contact comprises a plurality of solder balls disposed on the first side of the interposer and wherein the height of the solder balls is greater than the thickness of the first integrated device die.
8. The package of claim 7, wherein the solder balls are disposed around an outer perimeter of the first integrated device die such that a lowermost extent of the solder balls is positioned below a lowermost extent of the first integrated device die.
9. The package of claim 1, wherein each of the first integrated device die and the second integrated device die is flip-chip mounted to the interposer.
10. The package of claim 1, wherein the package is not encapsulated with a molding material.
11. (canceled)
12. (canceled)
13. (canceled)
14. (canceled)
15. (canceled)
16. (canceled)
17. (canceled)
18. A method of manufacturing an integrated device package, the method comprising:
mounting and electrically coupling a first integrated device die to a first side of an interposer; inserting a first portion of a second integrated device die into a hole of the interposer; and mounting and electrically coupling the second integrated device die to a second side of the interposer that is opposite the first side such that a second portion of the second integrated device die is disposed vertically and laterally outside the hole on the second side of the interposer.
19. The method of claim 18, wherein the first integrated device die comprises a processor die, and wherein the second integrated device die comprises a microelectromechanical systems (MEMS) die.
20. The method of claim 18, further comprising a plurality of electrical contacts disposed on the first side of the interposer, wherein a height of the electrical contacts is greater than a thickness of the first integrated device die.
21. The package of claim 1, wherein the second integrated device die comprises a microelectromechanical systems (MEMS) die, and wherein the first portion of the second integrated device die extending into the hole comprises a cap disposed over a MEMS device of the MEMS die.
22. The package of claim 21, wherein the first integrated device die comprises a processor die.
23. The package of claim 1, wherein the second portion of the second integrated device die is wider than the hole.
24. The package of claim 23, further comprising a plurality of electrical contacts disposed between and electrically connecting the second integrated device die and the interposer, the electrical contacts disposed on an outer region of the second portion which surrounds the hole.
25. The package of claim 1, wherein the hole has a major dimension in a lateral direction in a range of 1 mm to 5 mm.
26. The package of claim 1, wherein the first portion of the second integrated device die is spaced from and does not contact the first integrated device die.
27. The package of claim 1, wherein the interposer comprises a through-silicon via (TSV) to provide electrical communication between the first integrated device die and the second integrated device die.
Ref US20180277395: Claims:
1. A method of producing a multi-layer ceramic substrate, the method comprising the steps of:
(A) preparing a first ceramic green sheet with a thermal expansion layer arranged thereon, and at least one second ceramic green sheet with no thermal expansion layer arranged thereon; (B) laminating the first and second ceramic green sheets with the thermal expansion layer sandwiched therebetween, thereby obtaining a green sheet laminate; (C) pressure-bonding together the first ceramic green sheet and the at least one second ceramic green sheet of the green sheet laminate; (D) heating and thereby expanding the thermal expansion layer at least in a thickness direction in the pressure-bonded green sheet laminate; (E) extracting a portion of the green sheet laminate that has been displaced by the expansion of the thermal expansion layer, thereby forming a cavity in the green sheet laminate; and (F) sintering the green sheet laminate with the cavity formed therein.
2. The method of producing a multi-layer ceramic substrate according to claim 1, wherein in the step (D), the thermal expansion layer is held at a temperature higher than a temperature for pressure-bonding in the step (C).
3. The method of producing a multi-layer ceramic substrate according to claim 1, wherein the thermal expansion layer includes a thermal expansion material whose thickness increases by a factor of 2 or more by being heated.
4. The method of producing a multi-layer ceramic substrate according to claim 1, wherein the thermal expansion layer is a layer of a paste including thermally-expansive microcapsules made of a thermoplastic resin that encapsulate a hydrocarbon that is in liquid form at normal temperature.
5. The method of producing a multi-layer ceramic substrate according to claim 1, further comprising, between the step (C) and the step (D), a step of forming, in the green sheet laminate, a groove that has a depth of the cavity of the green sheet laminate and defines an outline of the cavity.
6. The method of producing a multi-layer ceramic substrate according to claim 1, wherein the thermal expansion layer is removed in the step (E).
7. The method of producing a multi-layer ceramic substrate according to claim 1, wherein:
in the step (A), a third ceramic green sheet with another thermal expansion layer arranged thereon is prepared in a region different from the first ceramic green sheet; in the step (B), the first to third ceramic green sheets are laminated together so that the thermal expansion layers are sandwiched therebetween, thereby obtaining the green sheet laminate; in the step (D), the other thermal expansion layer is heated to be expanded at least in the thickness direction; and in the step (E), a portion of the green sheet laminate that has been displaced by the expansion of the other thermal expansion layer is extracted.
8. The method of producing a multi-layer ceramic substrate according to claim 1, further comprising, between the step (E) and the step (F), a step (G) of removing a binder from the green sheet laminate.
9. The method of producing a multi-layer ceramic substrate according to claim 8, wherein in the step (D), the thermal expansion layer is held at a temperature that is higher than a temperature for pressure-bonding in the step (C) and lower than a temperature for binder removing in the step (G).
10. The method of producing a multi-layer ceramic substrate according to claim 1, wherein in the step (A), at least one of the first ceramic green sheet and the second ceramic green sheet includes a pattern to be internal wiring, an inductor, a condenser, a stripline or an internal resistor.
11. The method of producing a multi-layer ceramic substrate according to claim 1, wherein in the step (A), the first ceramic green sheet further includes a conductor pattern located between the thermal expansion layer and the first ceramic green sheet.
12. The method of producing a multi-layer ceramic substrate according to claim 1, wherein in the step (A), at least one of the first ceramic green sheet and the second ceramic green sheet further includes a via hole and a conductive paste that fills the via hole.
Ref US20040154164: Claims:
1. A ceramic packaging method employing a flip-chip bonding, comprising the steps of: 
(a) forming a gold bump on a chip bond pad in a wafer;  (b) dividing the wafer into a plurality of chips by a die sawing;  (c) aligning a Cu pattern and the gold bump on a ceramic package and adhering a bottom chip to the ceramic package through the Cu pattern and the gold bump;  (d) adhering a top chip to the bottom chip by using an adhesive, thereby forming a bottom/top chip structure of the bottom and top chip;  (e) electrically connecting the chip bond pad to the bottom chip and the chip bond pad to the top chip by interconnecting the bottom and the top chips; and  (f) encapsulating interconnected portions of the bottom and the top chips.
2. The method of claim 1, wherein a heat emitter is installed on a bottom portion of the ceramic package in order to emit heat generated from the bottom and the top chip.
3. The method of claim 1, wherein a groove is formed on the Cu pattern so that the gold bump is safely attached thereto.
4. The method of claim 1, wherein the adhesive is an epoxy or a polymide tape.
5. The method of claim 1, wherein a flip-chip bonding is carried out with respect to the top chip.
6. The method of claim 1, wherein the bottom and the top chip are electrically interconnected to each other by the Cu pattern.
7. The method of claim 1, wherein the interconnected portions are encapsulated by an epoxy resin.