Office Action 2: Notice of Allowance (2025-03-06)

CLAIMS:
AMENDMENTS TO THE CLAIMS

1\. (Currently Amended) A semiconductor structure, comprising a plurality of metal layers and a substrate, wherein the plurality of metal layers comprises a first metal layer, a second metal layer, and a third metal layer;
a plurality of virtual metal blocks and at least one signal line are disposed on the metal layers;
the virtual metal blocks on the metal layers are staggered in a direction perpendicular to the substrate;
a second distance between a projection of a target signal line on the substrate and a projection of a second virtual metal block on the substrate is greater than a first distance between the projection of the target signal line on the substrate and a projection of a first virtual metal block on the substrate; and the target signal line is located on the first metal layer;
a third distance between the projection of the target signal line on the substrate and a projection of a third virtual metal block on the substrate is greater than the first distance; and
the first virtual metal block is a virtual metal block, in the first metal layer, closest to the target signal line, the second virtual metal block is a virtual metal block, in the second metal layer, closest to the target signal line, and the third virtual metal block is a virtual metal block, in the third metal layer, closest to the target signal line;
wherein projections, on the substrate, of the virtual metal blocks on the plurality of metal layers does not overlap;
wherein the virtual metal blocks on each metal layer are arranged in an array;
wherein a projection matrix, on the substrate, of the virtual metal blocks on the first metal layer and a projection matrix, on the substrate, of the virtual metal blocks on the second metal layer are arranged to cross each other; and
a projection matrix, on the substrate, of the virtual metal blocks on the first metal layer and a projection matrix, on the substrate, of the virtual metal blocks on the third metal layer are arranged to cross each other.

2\. - 4. (Cancelled)33

5\. (Currently Amended) The semiconductor structure according to claim \[\[4\]\]1, wherein there is a projection, of one of the virtual metal blocks on the third metal layer, between projections of the virtual metal blocks on the first metal layer.

6\. (Original) The semiconductor structure according claim 5, wherein two adjacent virtual metal blocks on the first metal layer are in a same row.

7\. (Currently Amended) The semiconductor structure according to claim 6, wherein projections, on the substrate, of two adjacent virtual metal blocks on the first metal layer are in contact with projections, on the substrate, of the virtual metal blocks on the third metal layer.

8\. (Currently Amended) The semiconductor structure according to claim \[\[4\]\]1, wherein there is a projection, on the substrate, of one of the virtual metal blocks on the second metal layer, between projections, on the substrate, of two adjacent virtual metal blocks on the third metal layer.

9\. (Original) The semiconductor structure according claim 8, wherein two adjacent virtual metal blocks on the third metal layer are in a same column.

10\. (Currently Amended) The semiconductor structure according to claim 9, wherein the projections, on the substrate, of two adjacent virtual metal blocks
on the third metal layer are in contact with projections, on the substrate, of the virtual metal blocks on the second metal layer.

11\. (Original) The semiconductor structure according to claim 10, wherein the third distance is equal to the second distance.

12\. (Original) The semiconductor structure according to claim 1, wherein the second metal layer is higher than the first metal layer, and the third metal layer is higher than the second metal layer.

13\. (Original) The semiconductor structure according to claim 1, wherein the target signal line is arranged according to the at least one signal line and selected from the at least one signal line.

14\. (Original) The semiconductor structure according to claim 1, wherein the projections of the virtual metal blocks on the substrate are quadrilaterals.

15\. (Original) The semiconductor structure according to claim 1, wherein the signal line is used to transmit a clock signal.

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 1, 5-15 are allowed.
The following is an examiner’s statement of reasons for allowance:    Recorded Prior Art fails to disclose or suggest combination structure of semiconductor structure as characteristics in base claim 1 comprising  the virtual metal blocks on the metal layers are staggered in a direction perpendicular to the substrate;  the first virtual metal block is a virtual metal block, in the first metal layer, closest to the target signal line, the second virtual metal block is a virtual metal block, in the second metal layer, closest to the target signal line, and the third virtual metal block is a virtual metal block, in the third metal layer, closest to the target signal line; wherein projections, on the substrate, of the virtual metal blocks on the plurality of metal layers does not overlap;  wherein the virtual metal blocks on each metal layer are arranged in an array; wherein a projection matrix, on the substrate, of the virtual metal blocks on the first metal layer and a projection matrix, on the substrate, of the virtual metal blocks on the second metal layer are arranged to cross each other; and a projection matrix, on the substrate, of the virtual metal blocks on the first metal layer and a projection matrix, on the substrate, of the virtual metal blocks on the third metal layer are arranged to cross each other.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee.  Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”

APPLICANT REBUTTAL: REMARKS
In the non-final Office Action, the Examiner took the following actions:
I.   objected to drawings and specification;
II.  rejected claims 4-11 under 35 U.S.C. § 112(b) as allegedly being indefinite; III.  rejected claims 1-3 and 12-13 under 35 U.S.C.
§ 102(a)(1) and 102(a)(2) as being anticipated by Chiu et al [US20110248404] IV.  rejected claims 14 and 15 under 35 U.S.C. § 103 as being unpatentable by Chiu et al [US20110248404]
By way of this Amendment and Reply, Applicant amends claims 1, 5, 7,
8 and 10 for clarification purposes and/or to correct informalities. Support for these amendments can be found in the original specification of this application. Claims 2-4 are cancelled without prejudice or disclaimer.
No new matter is added.
I.   Objection to the Drawings and Specification
The objections to the drawings are addressed by submitting set of drawings again, which were wrongly presented in the USPTO system but correctly filed by the applicant.
Line 18 and 21 of page 6 in specification, "above" has been changed to "at".
Accordingly, Applicant respectfully requests withdrawal of the objections.
II.  The Rejection under 35 U.S.C. § 112(b)
Claims 4-11 were rejected as allegedly being indefinite.
As indicated above, without acquiescing on the merits of the rejections, claims 1, 5, 7, 8 and 10 are amended to address the Examiner's concerns.
For claim 4, the Examiner asserts that it is not clear that "another metal layer"(s) mean "the second metal layer" or "the third metal layer" or an addition different layer different to "the plurality of metal layers". Applicant replaced the "another metal layer" with "the second metal layer" and "the third metal layer" separately, and rewrote the features in original claim 4 when incorporating it to claim 1, to make it clear.
For claims 7, 8 and 10, the Examiner asserts that it is not clear about the limitations of the projections. Applicant added "on the substrate" after the projections to make it clearer.
For claim 11, the Examiner asserts that it is not clear how the third distance can be equal to the second distance, because in Fig 7, the second metal layer Mn+1 is higher than the first metal layer Mn, and the third metal layer Mn+2 is higher than the second metal layer Mn+1. Applicant respectfully disagrees, because claim 1 defines that "a second distance between a projection of a target signal line on the substrate and a projection of a second virtual metal block on the substrate" and "a third distance between the projection of the target signal line on the substrate and a projection of a third virtual metal block on the substrate". Since both the second distance and the third distance are about the projections on the substrate, which are on the same plane, so the features in claim 11 is clear.
Accordingly, Applicant respectfully requests withdrawal of the rejections.
III.  Rejections under 35 U.S.C. § 102(a) and 35 U.S.C. § 103
In the office action dated 08/29/2024, claims 1-3 and 12-13 were rejected under 35 U.S.C. § 102(a)(1) and 102(a)(2) as being anticipated by Chiu et al
[US20110248404], and claims 14-15 were rejected under 35 U.S.C. § 103 as being unpatentable by Chiu et al [US201 10248404].
Without acquiescing on the merits of the rejections, claim 1 has been amended to incorporate subject matter of previously recited in claim 4 and intervening claims 2-3.
Claim 1 and its dependent claims are thus patentable over the references at least in their amended form.
Accordingly, Applicant respectfully requests withdrawal of the rejections.
Concluding Remarks
Applicant believes that this Amendment and Reply is fully responsive to all outstanding issues and places the present application in condition for allowance. If this belief is incorrect, or other issues arise, the Examiner is encouraged to contact the Applicant at the telephone number listed below. No fee is due. However, if fees are necessary, such as in the event that an extension of time (EOT) becomes necessary, such EOT is requested and the USPTO is authorized to charge any extra fees due to the deposit account no. 506020.
Respectfully submitted,