Office Action 3: Non-Final Rejection (2024-12-03)
Rejection types: 103 - Obviousness

CLAIMS:
AMENDMENTS TO THE CLAIMS

1\. (Previously Presented) A method for forming a wide band gap semiconductor device, the method comprising:forming a gate insulation layer on a wide band gap semiconductor substrate;
performing a first annealing process during which the gate insulation layer is annealed using at least a first reactive gas species;
performing a second annealing process separate from the first annealing process and during which the gate insulation layer is annealed using at least a second reactive gas species; and
annealing the gate insulation layer in an inert gas atmosphere,
wherein the first reactive gas species differs from the second reactive gas species,
wherein the first annealing process is performed in a reactive gas atmosphere comprising at least 0.1 vol% of the first reactive gas species and at most 0.1 vol% of the second reactive gas species,
wherein the second annealing process is performed in a reactive gas atmosphere comprising at least 0.1 vol% of the second reactive gas species and at most 0.1 vol% of the first reactive gas species.
2\. (Cancelled)
3\. (Cancelled)
4\. (Original) The method of claim 1, wherein the first reactive gas species is one of nitric oxide, nitrous oxide, hydrogen, ammonia, hydrogen peroxide, nitric acid, water vapor,

phosphoryl chloride, and oxygen, and wherein the second reactive gas species is another one of nitric oxide, nitrous oxide, hydrogen, ammonia, hydrogen peroxide, nitric acid, water vapor, phosphoryl chloride, and oxygen.

5\. (Previously Presented) The method of claim 1, further comprising:diluting the first reactive gas species with an inert gas so that a volume percent of the first reactive gas species is at least lvol% and at most SOvol%, and wherein the first reactive gas species is nitric oxide.

6\. (Previously Presented) The method of claim 1, further comprising:diluting the second reactive gas species with an inert gas so that a volume percent of the second reactive gas species is at least 0.lvol% and at most lOvol%, and wherein the second reactive gas species is ammonia.

7\. (Cancelled)

8\. (Previously Presented) The method of claim 1, wherein the annealing of the gate insulation layer in the inert gas atmosphere comprises:heating the gate insulation layer in the inert gas atmosphere at a temperature lower than 1200°C to reduce a hydrogen concentration within the gate insulation layer.

9\. (Original) The method of claim 8, wherein the first reactive gas species and/or the second reactive gas species comprises at least one of nitric oxide and ammonia, and wherein a

volume percent of the first reactive gas species and/or the second reactive gas species is at least 0.lvol%.

10\. (Previously Presented) The method of claim 8, wherein the first reactive gas species and/or the second reactive gas species comprises at least 5vol% nitric oxide, wherein the inert gas atmosphere comprises at least 90% nitrogen, and wherein a duration of the annealing in the inert gas atmosphere is shorter than a duration of the annealing in the first reactive gas species and/or the second reactive gas species.

11\. (Original) The method of claim 8, wherein the inert gas atmosphere has a concentration of oxygen of at most 0.5vol%.

12\. (Original) The method of claim 8, wherein a duration of each annealing of the gate insulation layer is at least 10 minutes and at most 600 minutes.

13\. (Original) The method of claim 8, wherein an annealing temperature of each annealing of the gate insulation layer is at least 600°C and at most 1200°C.

14\. (Previously Presented) The method of claim 1, further comprising:before the gate insulation layer is annealed, heating the gate insulation layer in an inert gas atmosphere at a temperature of at least 950°C.

15\. (Previously Presented) The method of claim 1, further comprising:
 the gate insulation layer is annealed, forming a gate electrode on the gate insulation layer.

16\. (Original) The method of claim 15, wherein the gate electrode is a gate trench electrode that extends from a surface of the wide band gap semiconductor substrate into the wide band gap semiconductor substrate.

17\. (Original) The method of claim 1, wherein the wide band gap semiconductor substrate is a silicon carbide substrate.

18\. (Original) The method of claim 1, wherein the gate insulation layer is a silicon dioxide layer.

19\. (Cancelled)

20\. (Previously Presented) A method for forming a wide band gap semiconductor device, the method comprising:forming a gate insulation layer on a wide band gap semiconductor substrate;
annealing the gate insulation layer in a reactive gas atmosphere that comprises at least a reactive gas species in an annealing tool;
after annealing the gate insulation layer in the reactive gas atmosphere, annealing the gate insulation layer in an inert gas atmosphere without exposing the gate insulation layer to the atmosphere outside the annealing tool; and

after annealing the gate insulation layer in the inert gas atmosphere, forming a gate electrode on the gate insulation layer,
wherein the gate electrode is a gate trench electrode that extends from a surface of the wide band gap semiconductor substrate into the wide band gap semiconductor substrate,
wherein the reactive gas species comprises at least one of nitric oxide and ammonia,
wherein a volume percent of the reactive gas species is at least 0.1 vol%.

21\. (Previously Presented) The method of claim 20, wherein the reactive gas species comprises at least 5 vol% nitric oxide and the inert gas atmosphere comprises at least 90 % nitrogen, and wherein a duration of the annealing in the inert gas atmosphere is shorter than a duration of the annealing in the reactive gas species.

22\. (Previously Presented) The method of claim 20, wherein the inert gas atmosphere has a concentration of oxygen of at most 0.5 vol%.

23\. (Previously Presented) The method of claim 20, wherein a duration of the annealing of the gate insulation layer in the reactive gas atmosphere is at least 10 minutes and at most 600 minutes.

24\. (Previously Presented) The method of claim 20, wherein an annealing temperature of the annealing of the gate insulation layer in the reactive gas atmosphere and/or in the inert gas atmosphere is at least 600 °C and at most 1200 °C.


25\. (Previously Presented) The method of claim 20, further comprising:before annealing of the gate insulation layer, heating the gate insulation layer in an inert gas atmosphere at a temperature of at least 950 °C.

26\. (Previously Presented) The method of claim 20, wherein the wide band gap semiconductor substrate is a silicon carbide substrate.

27\. (Previously Presented) The method of claim 20, wherein the gate insulation layer is a silicon dioxide layer.

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 8-13, 15, 17, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2004010625 (Das et al).
Concerning claim 1, Das discloses a method for forming a wide band gap semiconductor device (Abstract), the method comprising: forming a . . . insulation layer on a wide band gap semiconductor substrate ([0031], note that the substrate is SiC substrate); performing a first annealing process  ([0031], note that a NO anneal can be performed after the formation of the SiO2 layer and the examiner is relying on that embodiment for purposes of examination) during which the gate insulation layer is annealed using at least a first reactive gas species ([0041], note the first reactive species is NO); performing a second annealing process  ([0031]) separate from the first annealing process and during which the gate insulation layer is annealed using at least a second reactive gas species ([0035], note that the second reactive species is NH3); and annealing the gate insulation layer in an inert gas atmosphere ([0043], note that several different inert gases are disclosed as being suitable for use in the inert anneal, the examiner is relying on the inert anneal to consist of only N2 gas for purposes of examination), wherein the first reactive gas species differs from the second reactive gas species ([0035] and [0041], note the first reactive gas species is NO and the second reactive gas species is NH3) , wherein the first annealing process is performed in a reactive gas atmosphere comprising at least 0.1 vol% of the first reactive gas species and at most 0.1 vol% of the second reactive gas species ([0041], the reactive gas species is disclosed as being NO and no other gases are disclosed as being supplied to the substrate during this anneal process, therefore the examiner is interpreting the gas to contain 100% NO (the first reactive species) and 0% NH3 which satisfies this limitation), wherein the second annealing process is performed in a reactive gas atmosphere comprising at least 0.1 vol% of the second reactive gas species and at most 0.1 vol% of the first reactive gas species ([0035], note that there are several different nitriding atmospheres disclosed, but for purposes of examination the examiner is interpreting that the reactive gas species is NH3 and no other gases are supplied to the substrate during this anneal process, therefore the reactive gas  contains 100% NH3 (the second reactive species) and 0% NO which satisfies this limitation.).
Das does not explicitly disclose that the insulating layer formed is a gate insulating layer. However, Das discloses examples in which the SiO2 layer formed on the SiC substrate is suitable for use in MOSFET devices as a gate oxide ([0054]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form the SiO2 as a gate insulating layer because of its known suitability for use in MOSFET devices as a gate oxide as disclosed by Das.
Continuing to claim 4, Das discloses wherein the first reactive gas species is one of nitric oxide, nitrous oxide, hydrogen, ammonia, hydrogen peroxide, nitric acid, water vapor, phosphoryl chloride, and oxygen ([0041], note the first reactive species is nitric oxide), and wherein the second reactive gas species is another one of  nitric oxide, nitrous oxide, hydrogen, ammonia, hydrogen peroxide, nitric acid, water vapor, phosphoryl chloride, and oxygen ([0035], note the second reactive species is ammonia).
Considering claim 8, Das discloses wherein the annealing of the gate insulation layer in the inert gas atmosphere comprises: heating the gate insulation layer in the inert gas atmosphere at a temperature lower than 1200°C to reduce a hydrogen concentration within the gate insulation layer ([0041], note that the inert anneal is described in US 20020102358 [0009] which has been incorporated in its entirety by reference).
Referring to claim 9, Das discloses wherein the first reactive gas species and/or the second reactive gas species comprises at least one of nitric oxide and ammonia , and wherein a volume percent of the first reactive gas species and/or the second reactive gas species is at least 0.1 vol% ([0041], the reactive gas species is disclosed as being NO and no other gases are disclosed as being supplied to the substrate during this anneal process, therefore the examiner is interpreting the gas to contain 100% NO (the first reactive species) and 0% NH3 which satisfies this limitation and [0035], note that there are several different nitriding atmospheres disclosed, but for purposes of examination the examiner is interpreting that the reactive gas species is NH3 and no other gases are supplied to the substrate during this anneal process, therefore the reactive gas  contains 100% NH3 (the second reactive species) and 0% NO which satisfies this limitation).
Pertaining to claim 10, Das discloses wherein the first reactive gas species and/or the second reactive gas species comprises at least 5 vol% nitric oxide ([0041], the reactive gas species is disclosed as being NO and no other gases are disclosed as being supplied to the substrate during this anneal process, therefore the examiner is interpreting the gas to contain 100% NO (the first reactive species) and 0% NH3 which satisfies this limitation), wherein the inert gas atmosphere comprises at least 90% nitrogen ([0043], note that several different inert gases are disclosed as being suitable for use in the inert anneal, the examiner is relying on the inert anneal to consist of only N2 gas for purposes of examination), and wherein a duration of the annealing in the  inert gas atmosphere is shorter than a duration of the annealing in the first reactive gas species and/or the second reactive gas species ([0035], [0041], and [0043], note that the duration of the inert anneal is preferably 30 minutes which is the duration the examiner is relying on for purposes of examination, while the duration of the first anneal with the first reactive species is 3 hours ).
As to claim 11, Das discloses wherein the inert gas atmosphere has a concentration   of oxygen of at most 0.5vol% ([0043], note that several different inert gases are disclosed as being suitable for use in the inert anneal, the examiner is relying on the inert anneal to consist of only N2 gas for purposes of examination and therefore the oxygen concentration is 0%).
Concerning claim 12, Das discloses wherein a duration of each annealing of the gate   insulation layer is at least 10 minutes and at most 600 minutes ([0038]. [0041], and [0043], not the examiner is relying on the longer duration (i.e. 3 hours for the second anneal)).
Continuing to claim 13, Das discloses wherein an annealing temperature of each annealing of the gate insulation layer is at least 600°C and at most 1200°C ([0038], [0041], [0043], note that the inert anneal is described in US 20020102358 [0009] which has been incorporated in its entirety by reference).
Considering claim 15, Das discloses further comprising after the gate insulation layer is annealed, forming a gate electrode on the gate insulation layer ([0054], note that the annealing is done before the substrate is further processed).
Referring to claim 17, Das discloses wherein the wide band gap semiconductor substrate is a silicon carbide substrate ([0031]).
Regarding claim 18, Das discloses wherein the gate insulation layer is a silicon dioxide layer ([0035]).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2004010625 (Das et al) as applied to claim 1 above, and further in view of US 20150214047 (Hama et al).
According to claim 16, Das discloses forming a gate.
Das does not disclose wherein the gate electrode is a gate trench electrode that extends from a surface of the wide band gap semiconductor substrate into the wide band gap semiconductor substrate. However, Hama discloses forming a gate insulating film on a silicon carbide substrate and performing an annealing process. A trench gate electrode is formed in the substrate. (Fig. 23). In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). See MPEP 2144.04 IV B. Therefore, absent evidence that configuration of the gate is significant it would have been an obvious change in shape based on device design as disclosed by Hama.
Claim(s) 20-24, 26, and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2004010625 (Das et al) in view of US 20150214047 (Hama et al).
Pertaining to claim 20, Das a method for forming a wide band gap semiconductor device (Abstract), the method comprising: forming a . . . insulation layer on a wide band gap semiconductor substrate ([0031], note that the substrate is SiC substrate); annealing the gate insulation layer in a reactive gas atmosphere that comprises at least a reactive gas species in an annealing tool ([0031], note that a NO anneal can be performed after the formation of the SiO2 layer and the examiner is relying on that embodiment for purposes of examination); after annealing the gate insulation layer in the reactive gas atmosphere, annealing the gate insulation layer in an inert gas atmosphere without exposing the gate insulation layer to the atmosphere outside the annealing tool ([0043]) . . . wherein the reactive gas species comprises at least one of nitric oxide and ammonia,  wherein a volume percent of the reactive gas species is at least 0.1 vol% ([0041], the reactive gas species is disclosed as being NO and no other gases are disclosed as being supplied to the substrate during this anneal process, therefore the examiner is interpreting the gas to contain 100% NO which satisfies this limitation).
Das does not specifically disclose that the insulating layer formed is a gate insulating layer, or after annealing the gate insulation layer in the inert gas atmosphere, forming a gate electrode on the gate insulation layer, wherein the gate electrode is a gate trench electrode that extends from a surface of the wide band gap semiconductor substrate into the wide band gap semiconductor substrate. However, Das discloses examples in which the SiO2 layer formed on the SiC substrate is suitable for use in MOSFET devices as a gate oxide ([0054]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form the SiO2 as a gate insulating layer because of its known suitability for use in MOSFET devices as a gate oxide as disclosed by Das.
Additionally, Hama discloses forming a gate insulating film on a silicon carbide substrate and performing an annealing process. A trench gate electrode is formed in the substrate. (Fig. 23). In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). See MPEP 2144.04 IV B. Therefore, absent evidence that configuration of the gate is significant it would have been an obvious change in shape based on device design as disclosed by Hama.
As to claim 21, Das in view of Hama discloses wherein the first reactive gas species and/or the second reactive gas species comprises at least 5 vol% nitric oxide (Das [0041], the reactive gas species is disclosed as being NO and no other gases are disclosed as being supplied to the substrate during this anneal process, therefore the examiner is interpreting the gas to contain 100% NO which satisfies this limitation), wherein the inert gas atmosphere comprises at least 90% nitrogen (Das [0043], note that several different inert gases are disclosed as being suitable for use in the inert anneal, the examiner is relying on the inert anneal to consist of only N2 gas for purposes of examination), and wherein a duration of the annealing in the  inert gas atmosphere is shorter than a duration of the annealing in the first reactive gas species and/or the second reactive gas species (Das [0035], [0041], and [0043], note that the duration of the inert anneal is preferably 30 minutes which is the duration the examiner is relying on for purposes of examination, while the duration of the first anneal with the first reactive species is 3 hours ).
Concerning claim 22, Das in view of Hama discloses wherein the inert gas atmosphere has a concentration   of oxygen of at most 0.5vol% (Das [0043], note that several different inert gases are disclosed as being suitable for use in the inert anneal, the examiner is relying on the inert anneal to consist of only N2 gas for purposes of examination and therefore the oxygen concentration is 0%).
Continuing to claim 23, Das in view of Hama discloses wherein a duration of each annealing of the gate   insulation layer is at least 10 minutes and at most 600 minutes (Das [0038]. [0041], and [0043], not the examiner is relying on the longer duration (i.e. 3 hours for the second anneal)).
Considering claim 24, Das in view of Hama discloses wherein an annealing temperature of each annealing of the gate insulation layer is at least 600°C and at most 1200°C (Das [0038], [0041], [0043], note that the inert anneal is described in US 20020102358 [0009] which has been incorporated in its entirety by reference).
Referring to claim 26, Das in view of Hama discloses wherein the wide band gap semiconductor substrate is a silicon carbide substrate (Das [0031]).
Regarding claim 27, Das in view of Hama discloses wherein the gate insulation layer is a silicon dioxide layer (Das [0035]).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2004010625 (Das et al) as applied to claim 1 above, and further in view of US 20080026553 (Chua et al).
Pertaining to claim 14, Das discloses that the gate insulating layer is annealed.
Das does not disclose before the gate insulation layer is annealed heating the gate insulation layer in an inert gas atmosphere at a temperature of at least 950°C. Chua discloses an annealing treatment performed on the silicon oxide insulating layer in an inert atmosphere (note that the chamber is purged with Nitrogen and then an annealing treatment follows the purge and therefore the annealing is done in the purged nitrogen atmosphere) for a duration of 1 second to about 180 seconds ([0044] and [0046]). Chua discloses that process will increase quality and uniformity of the insulating layer ([0007]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to perform the annealing in an inert comprising nitrogen for the duration before the annealing of the gate insulation layer in order to improve quality and uniformity of the insulating layer as disclosed by Chua.
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2004010625 (Das et al) in view of US 20150214047 (Hama et al) as applied to claim 20 above, and further in view of US 20080026553 (Chua et al).
As to claim 25, Das in view of Hama discloses the gate insulating layer is annealed.
Das in view of Hama does not disclose before the gate insulation layer is annealed heating the gate insulation layer in an inert gas atmosphere at a temperature of at least 950°C. Chua discloses an annealing treatment performed on the silicon oxide insulating layer in an inert atmosphere (note that the chamber is purged with Nitrogen and then an annealing treatment follows the purge and therefore the annealing is done in the purged nitrogen atmosphere) for a duration of 1 second to about 180 seconds ([0044] and [0046]). Chua discloses that process will increase quality and uniformity of the insulating layer ([0007]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to perform the annealing in an inert comprising nitrogen for the duration before the annealing of the gate insulation layer in order to improve quality and uniformity of the insulating layer as disclosed by Chua.
Allowable Subject Matter
Claims 5 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:  Claims 5 and 6 disclose respectively, further comprising: diluting the first reactive gas species with an inert gas so that a volume percent of the first   reactive gas species is at least 1 vol% and at most 50 vol%, and wherein the first reactive gas species is nitric oxide and
further comprising: diluting the second reactive gas species with an inert gas so that a volume percent of the second reactive gas species is at least 0.1 vol% and at most 10 vol%, and wherein the second reactive gas species is ammonia. These limitations in combination with the other limitations as set forth in the claims are neither taught nor suggested in the prior art.
Applicant’s arguments, see the response, filed 07/30/24, with respect to the rejection(s) of claim(s) 1, 4-6, 8-18, ands 20-27 under 103 have been fully considered and are persuasive.  Therefore, the rejection has been withdrawn.  However, upon further consideration, a new ground(s) of rejection is made in view of US 2004010625 (Das et al).
Conclusion

APPLICANT REBUTTAL: REMARKS Claims 1, 4-6, 8-18 and 20-27 were pending at the time of the Final Office Action dated May 2, 2024. Claims 1, 4-6, 8-18 and 20-27 stand rejected. Applicant respectfully submits that the present application is in condition for allowance at least for the reasons explained below. Claim Rejections Claims 1, 4, 8, 11-13, 15, 17, and 18 stand finally rejected under 35 U.S.C. §103 as being unpatentable over the DesOrmeaux reference (US 9,945,030) in view of the Makifuchi reference (US 2016/0126092). The remaining claims stand finally rejected under 35 U.S.C. § 103 as being unpatentable over the DesOrmeaux reference in view of the Makifuchi reference, and further in view of one or more additional references. All claim rejections are in clear error at least for the following reasons. Claims 1, 4-6, and 8-18 Claim 1 recites in part forming a gate insulation layer on a wide band gap semiconductor substrate. (Emphasis added). In the context of semiconductor devices, a gate insulation layer forms part of a gate structure used to influence channel mobility of the device.1 As explained in paragraphs [0023]-[27] of the present application, using at least two different reactive gas species for annealing the gate insulation layer reduces the number of point defects along the interface between the semiconductor substrate and the gate insulation layer, which in turn yields a higher inversion channel mobility and reduced on-resistance. Clearly, claim 1 is directed to the processing of gate insulation layers and not just any type of insulation layer. i See paragraph [0027] of the specification. The Final Office Action concluded that the DesOrmeaux reference discloses forming a gate insulation layer, at col. 5 lines 1-5.2 This finding is in clear error. Column 5 lines 1-6 of the DesOrmeaux reference is reproduced immediately below in its entirety. 5 PECVD silicon oxide becomes more compressive followingz thermal anneal (FIG, 5). Also., the tensile stress of a ther- mally annealed film can be increased relative to a film that is not so annealed. A.nnealing increases the stability of the film, i.e., the films are under tensile stress for a SVG {EMBED HERE} 0.4530.49 period 5 of time relative to the fil that is not so ann The cited section of the DesOrmeaux reference makes no mention of forming a gate insulation layer. Indeed, the DesOrmeaux reference is silent regarding gate insulation layers. Instead, the DesOrmeaux reference is directed to a "free-standing" membrane which has at least a portion of two surfaces of the film that are exposed and not in contact with another solid material, including the semiconductor substrate.3 DesOrmeaux's free-standing membrane is under tensile stress so that it remains substantially flat with optical intensity uniformity, which is beneficial since the film is intended for imaging applications such as cell imaging and electron microscopy.4 Clearly, DesOrmeaux's free-standing membrane is not a gate insulation layer. 2 See page 2 of the Final Office Action. 3 See columns 3 and 4 and Figure 10 of DesOrmeaux which shows such a free-standing membrane havingat least a portion of two surfaces of the film that are exposed and not in contact with the underlying Si wafeSVG {EMBED HERE} 0.0630.047er. 4 See col. 3, line 4 to col. 4, line 33; col. 6, lines 46-50 of DesOrmeaux. Furthermore, the Final Office Action concluded that the DesOrmeaux reference discloses annealing the alleged gate insulation layer using first and second reactive gas species.5 This finding also is in clear error. The DesOrmeaux reference teaches a single annealing process for the free-standing membrane, using a single gas atmosphere. Particularly, the DesOrmeaux reference teaches thermal annealing of films "in an atmosphere comprising nitrogen, in an atmosphere comprising hydrogen and an inert gas (e.g., hydrogen and nitrogen a forming gas atmosphere), or in a hydrogen gas atmosphere."6 (Emphasis added) That is, DesOrmeaux's thermal annealing atmosphere comprises nitrogen or hydrogen and an inert gas or a hydrogen gas.7 Hence, the DesOrmeaux reference does not teach or suggest annealing the free-standing membrane using two different reactive gas species. Regarding the Makifuchi reference, Makifuchi teaches a post oxidation annealing (POA) of gate insulating film 18 that includes a heat treatment performed for 30 minutes at 1000 degrees C in an atmosphere including H2 and H20. According to the Makifuchi reference, the H20 concentration in the H20 and H2 atmosphere "is set to be 73% and the flow ratio of H2 to 02 is adjusted. Heating is performed in a nitrogen atmosphere while cooling is performed in a hydrogen atmosphere, and before cooling, a hydrogen atmosphere is maintained for 30 minutes."8 Alternatively, the Makifuchi reference teaches forming gate insulating film 18 by "thermal oxynitriding for 120 minutes at 1300 degrees C in an atmosphere having a nitrous oxide s See pages 2-3 of the Final Office Action. 6 See col. 5, lines 7-23 of DesOrmeaux. ? See also col. 1, lines 44-46 and col. 3, lines 7-12 of DesOrmeaux. 8 See paragraph [0068] of Makifuchi. to nitrogen flow ratio of 1:5," "thermal oxynitriding for 90 minutes at 1250 degrees C in a nitric oxide atmosphere," a "30-minute heat treatment at 1000 degrees C. in an atmosphere including oxygen and water by a pyrogenic scheme," or "forming a deposited film by a CVD method using silane."9 None of the POA approaches disclosed in the Makifuchi reference for gate insulating film 18 involve performing a first annealing process during which the gate insulation layer is annealed using at least a first reactive gas species and performing a second annealing process separate from the first annealing process and during which the gate insulation layer is annealed using at least a second reactive gas species different from the first reactive gas species. Instead, a single annealing process using a single reactive gas atmosphere is employed in the Makifuchi reference for the POA of gate insulating film 18, as explained above. Accordingly, none of the POA approaches disclosed in the Makifuchi reference for gate insulating film 18 correspond to the annealing operation recited in pending claim 1. The Makifuchi reference also fails to disclose the claimed vol% relationships for the first and second annealing processes recited in claim 1. Regarding the combination of the DesOrmeaux and Makifuchi references, the Final Office Action gives the following reason as the motivation to combine the references: "to reduce interface state density in silicon carbide semiconductor devices."10 As noted above, paragraphs [0023]-[27] of the present application explain the importance reducing the number of point defects along the interface between a semiconductor substrate and a gate insulation layer (i.e., 9 See paragraphs [0077]-[80] of Makifuchi. 10 See page 4 of the Final Office Action. higher inversion channel mobility and reduced on-resistance). However, as explained above, the DesOrmeaux reference is silent regarding gate insulation layers. Instead, the DesOrmeaux reference is concerned with films used in imaging applications such as cell imaging and electron microscopy. Hence, DesOrmeaux's annealing process is designed to yield a free- standing membrane that is under tensile stress with little or no wrinkles.1 There is no indication in the DesOrmeaux reference that DesOrmeaux's free-standing membrane suffers from the interface state density issues addressed in the Makifuchi reference or that interface state density is even a concern. Absent such evidence, which is unsurprising since the DesOrmeaux reference is not concerned with gate insulation layers, the Office's position on obviousness lacks rational underpinning.2 Claims 20-27 Regarding the rejections of claim 20-27, the DesOrmeaux reference is silent regarding gate insulation layers, as explained above. Also, there is no indication in the DesOrmeaux reference that DesOrmeaux's free-standing membrane suffers from the interface state density issues addressed in the Makifuchi reference or that interface state density is even a concern. Accordingly, the rejections of claims 20-27 are in clear error and should be reversed at least for the analogous reasons explained above in connection with claims 1, 4-6, and 8-18. " See col. 2, lines 29-52 and col. 4, lines 21-29 of DesOrmeaux. 12 See KSR Int 'l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007) and In re Kahn, 441 F.3d 977, 988, 78 USPQ2d 1329, 1336 (Fed. Cir. 2006). Conclusion The present application should be in condition for allowance in view of the amendments and/or remarks made herein. Action to such effect is respectfully requested. The Examiner is encouraged to contact the undersigned at 919-948-3390 if any outstanding matters can be readily addressed by a phone call. Respectfully submitted, Murphy, Bilak & Homiller, PLLC/Mark R. Bilak, Reg. No. 47,423/Dated: June 7, 2024 SVG {EMBED HERE} 0.182.417 Registration No.: 47,423PO Box 1959 Cary, NC 27512-1959 Telephone: 919-948-3390

NEXT OFFICE ACTION: Reasons for Allowance
The following is an examiner’s statement of reasons for allowance: Claims 1 and 28 recite the limitations  diluting the first reactive gas species with an inert gas so that a volume percent of the first reactive gas species is at least 1 vol% and at most 50 vol%, and wherein the first reactive gas species is nitric oxide and diluting the second reactive gas species with an inert gas so that a volume percent of the second reactive gas species is at least 0.1 vol% and at most 10 vol%, and wherein the second reactive gas species is ammonia, respectively. The closest prior art references US 20040101625 and US 20020102358  neither alone nor in combination disclose or suggest these limitations in combination with the other limitations as set forth in the claims, respectively. Claims 4, 6, 8-18, and 29-36 depend from these claims respectively.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee.  Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion

CITED REFERENCE SUMMARIES: Ref US20040101625A1: [content unavailable]
Ref US20020102358A1: [content unavailable]
Ref US2004010625: Claims:
A method for the synchronous transfer of data from a data source to a receiving device comprising a link layer portion having a predetermined status for receiving the data and a physical layer portion with different operating frequency, the method comprising the following steps: detecting the predetermined status of the link layer portion; generating patterns responding to the predetermined status of the link layer portion on the physical layer portion; and returning the patterns to the data source from the physical layer portion to indicate that the receiving device is ready to receive data.
detecting the predetermined status of the link layer portion;
generating patterns responding to the predetermined status of the link layer portion on the physical layer portion; and
returning the patterns to the data source from the physical layer portion to indicate that the receiving device is ready to receive data.
The method as claimed in claim 1, wherein the link layer portion transfers parallel data to the physical layer portion.
The method as claimed in claim 1, wherein the physical layer portion transfers serial data to the receiving device.
An interface device for the synchronous transfer of data over serial ATA, comprising: a link layer portion for receiving the data from a device; a status monitor for detecting the status of the link layer portion; a fix pattern generator for providing primitive formats responding to the status of the link layer portion; and a physical layer controller for directly returning the primitive formats to the device without receiving the primitive formats to the link layer portion.
a link layer portion for receiving the data from a device;
a status monitor for detecting the status of the link layer portion;
a fix pattern generator for providing primitive formats responding to the status of the link layer portion; and
a physical layer controller for directly returning the primitive formats to the device without receiving the primitive formats to the link layer portion.
An interface device for the synchronous transfer of data over serial ATA, comprising: a data source for providing the data; and a device for receiving the data from the data source and returning confirmation that the data is received, then entering an idle state without waiting for a command from the data source after returning the confirmation to the data source a predetermined number of times.
a data source for providing the data; and
a device for receiving the data from the data source and returning confirmation that the data is received, then entering an idle state without waiting for a command from the data source after returning the confirmation to the data source a predetermined number of times.
The interface device as claimed in claim 5, wherein the data source transfers serial data to the receiving device.
The interface device as claimed in claim 5, wherein the predetermined number of times is at least two.
Ref US20020102358: Claims:
1. A method of forming an insulator in a silicon carbide electronic device, comprising: 
fabricating a nitrided oxide layer on a layer of silicon carbide; and  annealing the nitrided oxide layer in an environment containing hydrogen.
2. The method according to claim 1, wherein the silicon carbide layer comprises 4H polytype silicon carbide.
3. The method according to claim 1, wherein the silicon carbide layer comprises a silicon carbide layer on a non-silicon carbide substrate.
4. The method according to claim 1, wherein the silicon carbide layer comprises a portion of a silicon carbide substrate.
5. The method of claim 1, wherein the step of fabricating a nitrided oxide layer comprises at least one of forming the oxide layer in at least one of nitric oxide and nitrous oxide and annealing an existing oxide layer in at least one of nitric oxide and nitrous oxide.
6. The method of claim 1, wherein the step of fabricating a nitrided oxide layer comprises the steps of: 
fabricating an oxide layer; and  fabricating a nitride layer on the oxide layer so as to nitridate the oxide layer on which the nitride layer is fabricated.
7. The method of claim 6, wherein the step of annealing the oxide layer in an environment containing hydrogen is provided substantially concurrently with the step of fabricating the nitride layer so that the step of fabricating a nitride layer on the oxide layer comprises fabricating a nitride layer on the oxide layer so as to nitridate and hydrogenate the oxide layer on which the nitride layer is fabricated.
8. The method of claim 1, wherein the step of annealing the oxide layer comprises heating the oxide layer to a temperature of greater than about 400° C. in a hydrogen containing environment as part of another processing step.
9. The method of claim 1, wherein the step of annealing the oxide layer comprises annealing the oxide layer at a temperature of greater than about 400° C. in a hydrogen containing environment.
10. The method of claim 1, wherein the step of annealing the oxide layer comprises annealing the oxide layer at a temperature of less than about 900° C. in a hydrogen containing environment.
11. The method of claim 1, wherein the step of annealing the oxide layer comprises annealing the oxide layer at a temperature of between about 400° C. and about 1000° C. in a hydrogen containing environment.
12. The method of claim 1, wherein the step of annealing the oxide layer comprises annealing the oxide layer at a temperature of between about 400° C. and about 800° C. in a hydrogen containing environment.
13. The method of claim 1, further comprising the step of performing subsequent high temperature processing steps in a hydrogen containing environment.
14. The method of claim 1, wherein the step of annealing is preceded by the step of forming metallization for a semiconductor device associated with the oxide layer.
15. The method of claim 14, wherein the step of annealing the oxide layer comprises annealing the oxide layer at a temperature of less than about 900° C. in a hydrogen containing environment.
16. The method of claim 15, wherein the step of annealing the oxide layer comprises a contact anneal.
17. The method of claim 1, wherein the step of annealing comprises annealing the oxide layer in forming gas having about 4% hydrogen and 96% inert gases.
18. The method of claim 1 further comprising forming a silicon carbide metal oxide semiconductor device having the oxide layer as a gate oxide of the metal oxide semiconductor device.
19. The method of claim 1, wherein the step of annealing the oxide layer is carried out for at least about 2 minutes.
20. A method of fabricating an oxide layer on a silicon carbide layer, comprising: 
nitriding the oxide layer on the silicon carbide layer with at least one of nitric oxide and nitrous oxide; and  annealing the nitrided oxide layer at a temperature of between about 400° C about 900° C. in a hydrogen containing environment for at least about 2 minutes.
Ref US20150214047: Claims:
1. A method for manufacturing a semiconductor device, comprising the steps of:
(a1) preparing a silicon carbide substrate; (b1) forming a source/drain region in the silicon carbide substrate; (c1) forming a first insulating film over the top surface of the silicon carbide substrate; (d1) carrying out a first heat treatment accompanied by nitration on the first insulating film and the silicon carbide substrate in a first gas atmosphere; (e1) after the step (d1), carrying out a second heat treatment on the first insulating film and the silicon carbide substrate in a second gas atmosphere which is an inert gas, and (f1) after the step (e1), forming a gate electrode through the first insulating film over the silicon carbide substrate, wherein the gate electrode, the first insulating film and the source/drain region include a field effect transistor.
2. The method for manufacturing a semiconductor device according to claim 1 which further comprises the step of:
(e2) after the step (e1) and before the step (f1), exposing the first insulating film and the silicon carbide substrate to the atmosphere.
3. The method for manufacturing a semiconductor device according to claim 1,
wherein a third heat treatment is carried out on the silicon carbide substrate to form the first insulating film over the top surface of the silicon carbide substrate in the step (c1).
4. The method for manufacturing a semiconductor device according to claim 3,
wherein the third heat treatment is carried out in an atmosphere containing at least one selected from oxygen and vapor.
5. The method for manufacturing a semiconductor device according to claim 1,
wherein the first insulating film is formed by using an ALD or CVD method in the step (c1).
6. The method for manufacturing a semiconductor device according to claim 1, wherein the step (c1) has the substeps of:
(c2) carrying out a fourth heat treatment on the silicon carbide substrate to form a second insulating film over the top surface of the silicon carbide substrate, and (c3) forming a third insulating film over the second insulating film by using an ALD or CVD method to form the first insulating film including the second insulating film and the third insulating film.
7. The method for manufacturing a semiconductor device according to claim 6 which further comprises the step of:
(c4) after the step (c2) and before the step (c3), carrying out a fifth heat treatment accompanied by nitration on the second insulating film and the silicon carbide substrate in a third gas atmosphere.
8. The method for manufacturing a semiconductor device according to claim 1,
wherein the first gas contains at least one selected from dinitrogen monoxide, nitrogen monoxide and ammonia gases.
9. The method for manufacturing a semiconductor device according to claim 2,
wherein the first insulating film and the silicon carbide substrate having a temperature of 700° C. or lower are exposed to the atmosphere in the step (e2).
10. The method for manufacturing a semiconductor device according to claim 1,
wherein the second gas contains at least one selected from nitrogen, argon and helium gases.
11. The method for manufacturing a semiconductor device according to claim 1,
wherein the second heat treatment is carried out at 850° C. or higher.
12. The method for manufacturing a semiconductor device according to claim 1 which further comprises the step of:
(a2) after the step (a1) and before the step (b1), forming a groove in the main surface of the silicon carbide substrate,
wherein the gate electrode is formed in the groove in the step (f1).
Ref US20080026553: Claims:
1. A method for forming gate dielectric layers on a substrate, comprising:
forming a silicon oxide layer on a substrate; plasma treating the silicon oxide layer; depositing a silicon nitride layer on the silicon oxide layer by an ALD process; and thermal annealing the substrate.
2. The method of claim 1, wherein the step of plasma treating the silicon oxide layer further comprises:
flowing an inert gas into a plasma treatment chamber; and forming a plasma by the inert gas.
3. The method of claim 2, wherein the step of flowing the inert gas further comprises:
flowing the inert gas between about 50 sccm and about 750 sccm into the plasma treatment chamber.
4. The method of claim 2, wherein the step of forming a plasma further comprises:
applying a RF power between about 500 Watts and about 3000 Watts.
5. The method of claim 2, wherein the inert gas is selected from a group consisting of Ar, He, Ne, Xe, and the combination thereof.
6. The method of claim 2, wherein the inert gas is a nitrogen containing gas.
7. The method of claim 6, wherein the treated silicon oxide layer treated by the nitrogen containing gas has a nitrogen concentration between about 0.2 E15 atoms/cm2 to about 1 E15 atoms/cm2.
8. The method of claim 1, further comprising:
precleaning the substrate prior to forming the silicon oxide layer.
9. The method of claim 1, wherein the step of forming the silicon oxide layer, further comprises:
forming the silicon oxide layer with a thickness less than 15 Å.
10. The method of claim 1, wherein depositing the silicon nitride layer further comprises:
depositing the silicon nitride with a thickness less than 15 Å.
11. The method of claim 1, wherein the step of depositing the silicon nitride layer further comprises:
alternatively flowing a silicon containing gas and a nitrogen containing gas into an ALD chamber.
12. The method of claim 11, wherein the step of flowing further comprises:
flowing the silicon containing gas into the ALD chamber between about 5 sccm and about 500 sccm; and flowing the nitrogen containing gas into the ALD chamber between about 1000 sccm and about 5000 sccm.
13. The method of claim 11, wherein the nitrogen containing gas is at least one of NH3, N2, N2H4 or N2O.
14. The method of claim 11, wherein the silicon containing gas is at least one of SiH4, Si2H6, dichlorosilane (DCS), tetrachlorosilane (TCS) or hexachlorodisilane (HCD).
15. The method of claim 1, wherein the silicon oxide layer and the silicon nitride layer form a gate dielectric layer.
16. The method of claim 1, wherein the step of plasma treating the silicon oxide layer further comprises:
creating nucleation sites on the treated silicon oxide layer.
17. A method for forming gate dielectric layers on a substrate, comprising:
precleaning a substrate; forming a silicon oxide layer on the substrate; plasma treating the silicon oxide layer; depositing a silicon nitride layer on the silicon oxide layer by an ALD process; and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer form a gate dielectric layer.
18. The method of claim 17, wherein the plasma treating the silicon oxide layer further comprises:
creating nucleation sites on the treated silicon oxide layer.
19. The method of claim 17, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 Å.
20. A method for forming a gate structure, comprising:
precleaning a substrate; forming a silicon oxide layer on the substrate; plasma treating the silicon oxide layer; depositing a silicon nitride layer on the silicon oxide layer by an ALD process; thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 Å and forms a gate dielectric; forming a gate electrode on the gate dielectric; and forming source and drain regions in the substrate proximate the gate electrode.