Office Action 1: Non-Final Rejection (2024-05-10)
Rejection types: 103 - Obviousness, 112 - Written Description/Enablement

CLAIMS:
CLAIMS

1\. A power stage comprising a control device and a power transistor connected to the control device in order to be driven by the control device, the control device comprising:
a primary circuit and a secondary circuit, the primary circuit comprising:
a control module able to generate a control current it, a primary circuit malfunction detector able to detect a malfunction of the primary circuit, a pulse transformer comprising a primary winding connected to the primary circuit, the pulse transformer comprising a secondary winding connected to the secondary circuit, magnetically coupled to the primary winding and able to generate, from the control current it, an induced pulse current im in the direction of the secondary circuit, the induced pulse current im making it possible to drive the power transistor, the secondary circuit comprising:
a power and fault detection controller, connected to the secondary winding of the pulse transformer and to the power transistor, able to detect a malfunction of the secondary circuit and/or of the power transistor, the power and fault detection controller being able to communicate the malfunction of the secondary circuit and/or of the power transistor to the primary circuit malfunction detector.

2\. The power stage according to claim 1, wherein the power and fault detection controller communicates the malfunction of the secondary circuit and/or of the power transistor to the primary circuit malfunction detector only by way of the pulse transformer.

3\. The power stage according to claim 1, wherein the control module comprises an oscillator able to generate a predefined pulsed wave (Pulse) on the basis of a control signal (Sc) originating from outside the power stage and a full bridge, connected to the oscillator, able to generate the control current it on the basis of the predefined pulsed wave (Pulse) in the direction of the primary winding of the pulse transformer.

4\. The power stage according to claim 3, wherein the full bridge is configured to synchronously generate the control current it on the basis of the external control signal (Sc) and/or the predefined pulsed wave (Pulse).

5\. The power stage according to claim 1, the secondary winding comprising two electrical terminals, the power and fault detection controller comprising an impedance R connected to the two electrical terminals of the secondary winding of the pulse transformer, the impedance R comprising an electrical resistance of less than 1000 ohms.

6\. The power stage according to claim 1, wherein the primary circuit malfunction detector comprises a short-circuit detector, the short-circuit detector being able to detect an overcurrent in the primary circuit.

7\. The power stage according to claim 6, wherein the short-circuit detector is able to detect an opening fault in the primary circuit and/or a short-circuit fault in the primary circuit.

8\. The power stage according to claim 1, wherein the power and fault detection controller comprises a pulse detector able to detect a pulse fault in the induced pulse current im.

9\. The power stage according to claim 8, wherein the pulse detector is configured to rectify the induced pulse current im

10\. The power stage according to claim 1, wherein the power and fault detection controller comprises a power transistor operation detector, able to detect at least one parameter of the power transistor causing non-nominal operation of the power transistor.

11\. The power stage according to claim 1, wherein the power and fault detection controller comprises a stop element able to short-circuit the pulse transformer on the basis of a fault detection.

12\. The power stage according to claim 1, comprising a power transistor driver able to generate a command for the power transistor based on the induced pulse current im

13\. The power stage according to claim 1, wherein the primary circuit malfunction detector comprises a recorder able to record the malfunction of the primary circuit and/or the malfunction of the secondary circuit and/or of the power transistor.

14\. The power stage according to claim 1, wherein the current driver comprises a command deactivator, configured to cancel the command for the power transistor when a primary circuit malfunction and/or secondary circuit malfunction and/or power transistor malfunction is detected.

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-14 are pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 07/13/2022 is/are in compliance with the provisions of 37 C.F.R. § 1.97.  Accordingly, the IDS has/have been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b)  CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 recites the limitation current driver in line 1 of the claim.  There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “current driver” is interpreted to mean the “secondary circuit”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA  35 U.S.C. 102 and 103 (or as subject to pre-AIA  35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA  to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 6, 7, 10, 12, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rinehart et al. U.S. Patent No. 5,900,683 (hereinafter “Rinehart”), and further in view of Hara U.S. Patent Application 2020/0169179 (hereinafter “Hara”).
Regarding claim 1, Rinehart teaches a power stage (refer to fig.1) comprising a control device (i.e. device 10)(fig.1) and a power transistor (i.e. transistor 14)(fig.1) connected to the control device (implicit) in order to be driven by the control device (refer to col. 2 lines 51-65), the control device comprising: a primary circuit (i.e. primary circuit 16)(fig.1) and a secondary circuit (i.e. secondary circuit 20)(fig.1), the primary circuit comprising: a control module (i.e. PWM Interface 26 and transformer driver/receiver 42)(fig.2) able to generate a control current it (refer to col. 4 lines 28-52), a primary circuit malfunction detector (i.e. fault decoder 44)(fig.2), a pulse transformer (i.e. high frequency pulse transformers 18)(fig.1) comprising a primary winding (i.e. primary side 22)(fig.1) connected to the primary circuit (implicit), the pulse transformer comprising a secondary winding (i.e. secondary side 24)(fig.1) connected to the secondary circuit (implicit), magnetically coupled to the primary winding (implicit) and able to generate, from the control current it, an induced pulse current im in the direction of the secondary circuit, the induced pulse current im making it possible to drive the power transistor (refer to col 5 lines 22-35), the secondary circuit comprising: a power and fault detection controller (refer to undervoltage detector 60, desaturation detector 66, overcurrent detectors 68, over-temperature detector 70, fault encoder 72, and transmitter 74)(fig.5), connected to the secondary winding of the pulse transformer and to the power transistor (implicit)(refer to fig.5), able to detect a malfunction of the secondary circuit and/or of the power transistor (implicit), the power and fault detection controller being able to communicate the malfunction of the secondary circuit and/or of the power transistor to the primary circuit malfunction detector (refer to fault encoder 72 and transmitter 74)(fig.5)(refer also to col. 6 line 66 to col. 7 line 36), however Rinehart does not teach the primary circuit malfunction detector able to detect a malfunction of the primary circuit. However, Hara teaches the primary circuit malfunction detector able to detect a malfunction of the primary circuit (refer to primary-side abnormality detection portion 15)(fig.13)(refer also to [0125] and [0144]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the primary circuit malfunction detector of Rinehart to include the detection of malfunctions of the primary circuit of Hara to provide the advantage of protecting the primary circuit from malfunctions, thereby better protecting the entire circuit from damage due to malfunctions.
Regarding claim 2, Rinehart and Hara teach the power stage according to claim 1, wherein the power and fault detection controller communicates the malfunction of the secondary circuit and/or of the power transistor to the primary circuit malfunction detector only by way of the pulse transformer (refer to Rinehart col. 5 lines 35-49).
Regarding claim 6, Rinehart and Hara teach the power stage according to claim 1, wherein the primary circuit malfunction detector comprises a short-circuit detector (refer to Hara [0126] and [0129]), the short-circuit detector being able to detect an overcurrent in the primary circuit (refer to Hara [0126] and [0129]).
Regarding claim 7, Rinehart and Hara teach the power stage according to claim 6, wherein the short-circuit detector is able to detect an opening fault in the primary circuit and/or a short-circuit fault in the primary circuit (refer to Hara [0126] and [0129]).
Regarding claim 10, Rinehart and Hara teach the power stage according to claim 1, wherein the power and fault detection controller comprises a power transistor operation detector (refer to Rinehart overcurrent detectors 68 and over-temperature detector 70)(fig.5), able to detect at least one parameter of the power transistor causing non-nominal operation of the power transistor (refer to Rinehart overcurrent detectors 68 and over-temperature detector 70)(fig.5).
Regarding claim 12, Rinehart and Hara teach the power stage according to claim 1, comprising a power transistor driver (i.e. Rinehart amplifier 64)(fig.5) able to generate a command for the power transistor based on the induced pulse current im (implicit).
Regarding claim 14, Rinehart and Hara teach the power stage according to claim 1, wherein the current driver comprises a command deactivator (refer to Rinehart claims 13 and 14), configured to cancel the command for the power transistor when a primary circuit malfunction and/or secondary circuit malfunction and/or power transistor malfunction is detected (refer to Rinehart claims 13 and 14).
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rinehart and Hara as applied to claim 1 above, and further in view of Ongaro U.S. Patent Application 2005/0062433 (hereinafter “Ongaro”).
Regarding claim 3, Rinehart and Hara teach the power stage according to claim 1, however they do not teach wherein the control module comprises an oscillator able to generate a predefined pulsed wave (Pulse) on the basis of a control signal (Sc) originating from outside the power stage and a full bridge, connected to the oscillator, able to generate the control current it on the basis of the predefined pulsed wave (Pulse) in the direction of the primary winding of the pulse transformer. However, Ongaro teaches wherein the control module comprises an oscillator (refer to [0044]) able to generate a predefined pulsed wave (Pulse) (implicit) on the basis of a control signal (Sc) originating from outside the power stage (refer to [0044]) and a full bridge (refer to [0044]), connected to the oscillator (refer to [0044]), able to generate the control current it on the basis of the predefined pulsed wave (Pulse) in the direction of the primary winding of the pulse transformer (refer to [0044]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power stage of Rinehart and Hara to include the oscillator and full bridge of Ongaro to provide the advantage of properly driving the primary winding.
Regarding claim 4, Rinehart, Hara, and Ongaro teach the power stage according to claim 3, wherein the full bridge is configured to synchronously generate the control current it on the basis of the external control signal (Sc) and/or the predefined pulsed wave (Pulse) (implicit).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rinehart and Hara.
Regarding claim 5, Rinehart and Hara teach the power stage according to claim 1, the secondary winding comprising two electrical terminals (implicit)(refer to Hara TM-2A and TM-2B)(fig.1), the power and fault detection controller comprising an impedance R (i.e. Hara capacitor C2)(fig.1) connected to the two electrical terminals of the secondary winding of the pulse transformer (implicit), however they do not teach the impedance R comprising an electrical resistance of less than 1000 ohms. However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have the impedance R comprising an electrical resistance of less than 1000 ohms, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art.  In re Aller, 105 USPQ 233. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power stage of Rinehart and Hara to include the impedance R comprising an electrical resistance of less than 1000 ohms to provide the advantage of preventing undue influence on the circuit while smoothing out noise.
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rinehart and Hara as applied to claim 1 above, and further in view of Tang et al. U.S. Patent Application 2020/0083813 (hereinafter “Tang”).
Regarding claim 8, Rinehart and Hara teach the power stage according to claim 1, however, they do not teach wherein the power and fault detection controller comprises a pulse detector able to detect a pulse fault in the induced pulse current im. However, Tang teaches wherein the power and fault detection controller comprises a pulse detector able to detect a pulse fault in the induced pulse current im (refer to [0054] and figure 4). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power stage of Rinehart and Tang to include the pulse detector of Tang to provide the advantage of using a common means to detect missing pulses.
Regarding claim 9, Rinehart, Hara, and Tang teach the power stage according to claim 8, wherein the pulse detector is configured to rectify the induced pulse current im (refer to Tang [0054] and figure 4).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rinehart and Hara as applied to claim 1 above, and further in view of Deng et al. Chinese Patent Document CN 101323310 B (hereinafter “Deng”).
Regarding claim 11, Rinehart and Hara teach the power stage according to claim 1, however they do not teach wherein the power and fault detection controller comprises a stop element able to short-circuit the pulse transformer on the basis of a fault detection. However, Deng teaches wherein the power and fault detection controller comprises a stop element able to short-circuit the pulse transformer on the basis of a fault detection (refer to [0064]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power stage of Rinehart and Hara to include the stop element of Deng to provide the advantage of quickly and reliably turning of the power transistor.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rinehart and Hara as applied to claim 1 above, and further in view of Cao et al. Chinese Patent Document CN 105262056 A (hereinafter “Cao”).
Regarding claim 13, Rinehart and Hara teach the power stage according to claim 1, however they do not teach wherein the primary circuit malfunction detector comprises a recorder able to record the malfunction of the primary circuit and/or the malfunction of the secondary circuit and/or of the power transistor. However, Cao teaches wherein the primary circuit malfunction detector comprises a recorder able to record the malfunction of the primary circuit and/or the malfunction of the secondary circuit and/or of the power transistor (refer to page 7). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power stage of Rinehart and Hara to include the recorder of Cao to provide the advantage of preventing operation of the power stage until the fault is cleared.
Conclusion


NEXT OFFICE ACTION: DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-5 and 7-14 are pending in this application.
Response to Amendment
Claims 1, 7, and 14 are amended. Claim 6 is canceled.
Response to Arguments
Applicant's arguments filed 10/08/2024 have been fully considered but they are not persuasive. Applicant argues that Rinehart et al. U.S. Patent No. 5,900,683 (hereinafter “Rinehart”) and Hara U.S. Patent Application 2020/0169179 (hereinafter “Hara”) do not teach “wherein the primary circuit malfunction detector is configured to detect an overcurrent in the primary circuit.” Specifically, the Applicant argues that Hara teaches detecting a current sensing abnormality, however this is not an overcurrent. However, Hara teaches the primary-side abnormality detection portion 15 detecting a current sensing abnormality and incomplete turn-off abnormality (refer to [0126]). The incomplete turn-off abnormality of Hara is described in [0129] and [0130]. Hara states that the “incomplete turn-off abnormality refers to a state in which the value of the current detection signal… is higher than a predetermined threshold although the switch transistor M1 is controlled to be turned off”. The current detection signal being higher than a threshold is an overcurrent. Therefore, Hara teaches wherein the primary circuit malfunction detector is configured to detect an overcurrent in the primary circuit (refer to [01216], [0129], and [0130]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA  35 U.S.C. 102 and 103 (or as subject to pre-AIA  35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA  to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 6, 7, 10, 12, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rinehart et al. U.S. Patent No. 5,900,683 (hereinafter “Rinehart”), and further in view of Hara U.S. Patent Application 2020/0169179 (hereinafter “Hara”).
Regarding claim 1, Rinehart teaches a power stage (refer to fig.1) comprising a control device (i.e. device 10)(fig.1) and a power transistor (i.e. transistor 14)(fig.1) connected to the control device (implicit) in order to be driven by the control device (refer to col. 2 lines 51-65), the control device comprising: a primary circuit (i.e. primary circuit 16)(fig.1) and a secondary circuit (i.e. secondary circuit 20)(fig.1), the primary circuit comprising: a control module (i.e. PWM Interface 26 and transformer driver/receiver 42)(fig.2) able to generate a control current it (refer to col. 4 lines 28-52), a primary circuit malfunction detector (i.e. fault decoder 44)(fig.2), a pulse transformer (i.e. high frequency pulse transformers 18)(fig.1) comprising a primary winding (i.e. primary side 22)(fig.1) connected to the primary circuit (implicit), the pulse transformer comprising a secondary winding (i.e. secondary side 24)(fig.1) connected to the secondary circuit (implicit), magnetically coupled to the primary winding (implicit) and able to generate, from the control current it, an induced pulse current im in the direction of the secondary circuit, the induced pulse current im making it possible to drive the power transistor (refer to col 5 lines 22-35), the secondary circuit comprising: a power and fault detection controller (refer to undervoltage detector 60, desaturation detector 66, overcurrent detectors 68, over-temperature detector 70, fault encoder 72, and transmitter 74)(fig.5), connected to the secondary winding of the pulse transformer and to the power transistor (implicit)(refer to fig.5), able to detect a malfunction of the secondary circuit and/or of the power transistor (implicit), the power and fault detection controller being able to communicate the malfunction of the secondary circuit and/or of the power transistor to the primary circuit malfunction detector (refer to fault encoder 72 and transmitter 74)(fig.5)(refer also to col. 6 line 66 to col. 7 line 36), however Rinehart does not teach the primary circuit malfunction detector able to detect a malfunction of the primary circuit, wherein the primary circuit malfunction detector is configured to detect an overcurrent in the primary circuit. However, Hara teaches the primary circuit malfunction detector able to detect a malfunction of the primary circuit (refer to primary-side abnormality detection portion 15)(fig.13)(refer also to [0125] and [0144]), wherein the primary circuit malfunction detector is configured to detect an overcurrent in the primary circuit (refer to [0126], [0129], and [0130]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the primary circuit malfunction detector of Rinehart to include the detection of malfunctions of the primary circuit of Hara to provide the advantage of protecting the primary circuit from malfunctions, thereby better protecting the entire circuit from damage due to malfunctions.
Regarding claim 2, Rinehart and Hara teach the power stage according to claim 1, wherein the power and fault detection controller communicates the malfunction of the secondary circuit and/or of the power transistor to the primary circuit malfunction detector only by way of the pulse transformer (refer to Rinehart col. 5 lines 35-49).
Regarding claim 7, Rinehart and Hara teach the power stage according to claim 6, wherein the short-circuit detector is able to detect an opening fault in the primary circuit and/or a short-circuit fault in the primary circuit (refer to Hara [0126], [0129], and [0130]).
Regarding claim 10, Rinehart and Hara teach the power stage according to claim 1, wherein the power and fault detection controller comprises a power transistor operation detector (refer to Rinehart overcurrent detectors 68 and over-temperature detector 70)(fig.5), able to detect at least one parameter of the power transistor causing non-nominal operation of the power transistor (refer to Rinehart overcurrent detectors 68 and over-temperature detector 70)(fig.5).
Regarding claim 12, Rinehart and Hara teach the power stage according to claim 1, comprising a power transistor driver (i.e. Rinehart amplifier 64)(fig.5) able to generate a command for the power transistor based on the induced pulse current im (implicit).
Regarding claim 14, Rinehart and Hara teach the power stage according to claim 1, wherein the power transistor driver comprises a command deactivator (refer to Rinehart claims 13 and 14), configured to cancel the command for the power transistor when a primary circuit malfunction and/or secondary circuit malfunction and/or power transistor malfunction is detected (refer to Rinehart claims 13 and 14).
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rinehart and Hara as applied to claim 1 above, and further in view of Ongaro U.S. Patent Application 2005/0062433 (hereinafter “Ongaro”).
Regarding claim 3, Rinehart and Hara teach the power stage according to claim 1, however they do not teach wherein the control module comprises an oscillator able to generate a predefined pulsed wave (Pulse) on the basis of a control signal (Sc) originating from outside the power stage and a full bridge, connected to the oscillator, able to generate the control current it on the basis of the predefined pulsed wave (Pulse) in the direction of the primary winding of the pulse transformer. However, Ongaro teaches wherein the control module comprises an oscillator (refer to [0044]) able to generate a predefined pulsed wave (Pulse) (implicit) on the basis of a control signal (Sc) originating from outside the power stage (refer to [0044]) and a full bridge (refer to [0044]), connected to the oscillator (refer to [0044]), able to generate the control current it on the basis of the predefined pulsed wave (Pulse) in the direction of the primary winding of the pulse transformer (refer to [0044]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power stage of Rinehart and Hara to include the oscillator and full bridge of Ongaro to provide the advantage of properly driving the primary winding.
Regarding claim 4, Rinehart, Hara, and Ongaro teach the power stage according to claim 3, wherein the full bridge is configured to synchronously generate the control current it on the basis of the external control signal (Sc) and/or the predefined pulsed wave (Pulse) (implicit).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rinehart and Hara.
Regarding claim 5, Rinehart and Hara teach the power stage according to claim 1, the secondary winding comprising two electrical terminals (implicit)(refer to Hara TM-2A and TM-2B)(fig.1), the power and fault detection controller comprising an impedance R (i.e. Hara capacitor C2)(fig.1) connected to the two electrical terminals of the secondary winding of the pulse transformer (implicit), however they do not teach the impedance R comprising an electrical resistance of less than 1000 ohms. However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have the impedance R comprising an electrical resistance of less than 1000 ohms, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art.  In re Aller, 105 USPQ 233. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power stage of Rinehart and Hara to include the impedance R comprising an electrical resistance of less than 1000 ohms to provide the advantage of preventing undue influence on the circuit while smoothing out noise.
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rinehart and Hara as applied to claim 1 above, and further in view of Tang et al. U.S. Patent Application 2020/0083813 (hereinafter “Tang”).
Regarding claim 8, Rinehart and Hara teach the power stage according to claim 1, however, they do not teach wherein the power and fault detection controller comprises a pulse detector able to detect a pulse fault in the induced pulse current im. However, Tang teaches wherein the power and fault detection controller comprises a pulse detector able to detect a pulse fault in the induced pulse current im (refer to [0054] and figure 4). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power stage of Rinehart and Tang to include the pulse detector of Tang to provide the advantage of using a common means to detect missing pulses.
Regarding claim 9, Rinehart, Hara, and Tang teach the power stage according to claim 8, wherein the pulse detector is configured to rectify the induced pulse current im (refer to Tang [0054] and figure 4).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rinehart and Hara as applied to claim 1 above, and further in view of Deng et al. Chinese Patent Document CN 101323310 B (hereinafter “Deng”).
Regarding claim 11, Rinehart and Hara teach the power stage according to claim 1, however they do not teach wherein the power and fault detection controller comprises a stop element able to short-circuit the pulse transformer on the basis of a fault detection. However, Deng teaches wherein the power and fault detection controller comprises a stop element able to short-circuit the pulse transformer on the basis of a fault detection (refer to [0064]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power stage of Rinehart and Hara to include the stop element of Deng to provide the advantage of quickly and reliably turning of the power transistor.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rinehart and Hara as applied to claim 1 above, and further in view of Cao et al. Chinese Patent Document CN 105262056 A (hereinafter “Cao”).
Regarding claim 13, Rinehart and Hara teach the power stage according to claim 1, however they do not teach wherein the primary circuit malfunction detector comprises a recorder able to record the malfunction of the primary circuit and/or the malfunction of the secondary circuit and/or of the power transistor. However, Cao teaches wherein the primary circuit malfunction detector comprises a recorder able to record the malfunction of the primary circuit and/or the malfunction of the secondary circuit and/or of the power transistor (refer to page 7). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power stage of Rinehart and Hara to include the recorder of Cao to provide the advantage of preventing operation of the power stage until the fault is cleared.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action.  Accordingly, THIS ACTION IS MADE FINAL.  See MPEP § 706.07(a).  Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action.  In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action.  In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.

CITED REFERENCE SUMMARIES: Ref US20200083813A1: Claims:
A switched-mode power converter using an isolated topology for converting power from an input source into power for an output load, the switched-mode power converter comprising: a primary side including a power stage coupled to the input source and comprising one or more power switches; a transformer comprising a primary winding coupled to the power stage, and a secondary winding; and a secondary side including: a rectifier circuit coupled to the secondary winding and configured to provide a first rectified voltage at a first rectified voltage node, a filter circuit interposed between the first rectified voltage node and an output of the switched-mode power converter, the filter circuit configured to filter the first rectified voltage, thereby providing a filtered voltage at the output, and a secondary-side controller configured to: sense the first rectified voltage; detect, based upon the first rectified voltage sensed on the secondary side, a fault condition of the primary side; and generate a fault indication and/or modify operation of the switched-mode power converter responsive to said detection.
a primary side including a power stage coupled to the input source and comprising one or more power switches;
a transformer comprising a primary winding coupled to the power stage, and a secondary winding; and
a secondary side including: a rectifier circuit coupled to the secondary winding and configured to provide a first rectified voltage at a first rectified voltage node, a filter circuit interposed between the first rectified voltage node and an output of the switched-mode power converter, the filter circuit configured to filter the first rectified voltage, thereby providing a filtered voltage at the output, and a secondary-side controller configured to: sense the first rectified voltage; detect, based upon the first rectified voltage sensed on the secondary side, a fault condition of the primary side; and generate a fault indication and/or modify operation of the switched-mode power converter responsive to said detection.
a rectifier circuit coupled to the secondary winding and configured to provide a first rectified voltage at a first rectified voltage node,
a filter circuit interposed between the first rectified voltage node and an output of the switched-mode power converter, the filter circuit configured to filter the first rectified voltage, thereby providing a filtered voltage at the output, and
a secondary-side controller configured to: sense the first rectified voltage; detect, based upon the first rectified voltage sensed on the secondary side, a fault condition of the primary side; and generate a fault indication and/or modify operation of the switched-mode power converter responsive to said detection.
sense the first rectified voltage;
detect, based upon the first rectified voltage sensed on the secondary side, a fault condition of the primary side; and
generate a fault indication and/or modify operation of the switched-mode power converter responsive to said detection.
The switched-mode power converter of claim 1 , wherein the secondary-side controller is configured to estimate an input voltage of the input source based upon the sensed first rectified voltage.
The switched-mode power converter of claim 2 , wherein the fault condition is an undervoltage fault condition and wherein estimating the input voltage comprises: detecting a rectified voltage pulse based upon voltage measurements of the sensed first rectified voltage; determining a representative voltage amplitude for the rectified voltage pulse based on the voltage measurements; and estimating the input voltage based upon the representative voltage amplitude,
detecting a rectified voltage pulse based upon voltage measurements of the sensed first rectified voltage;
determining a representative voltage amplitude for the rectified voltage pulse based on the voltage measurements; and
estimating the input voltage based upon the representative voltage amplitude,
and wherein the secondary-side controller is further configured to: detect, responsive to determining that the estimated input voltage is lower than an undervoltage threshold, the undervoltage fault condition.
detect, responsive to determining that the estimated input voltage is lower than an undervoltage threshold, the undervoltage fault condition.
The switched-mode power converter of claim 2 , wherein the fault condition is an overvoltage fault condition and wherein estimating the input voltage comprises: detecting a rectified voltage pulse based upon voltage measurements of the sensed first rectified voltage; determining a representative voltage amplitude for the rectified voltage pulse based on the voltage measurements; and estimating the input voltage based upon the representative voltage amplitude,
and wherein the secondary-side controller is further configured to: detect, responsive to determining that the estimated input voltage is higher than an overvoltage threshold, the overvoltage fault condition.
detect, responsive to determining that the estimated input voltage is higher than an overvoltage threshold, the overvoltage fault condition.
The switched-mode power converter of claim 1 , wherein the fault condition is a missing-pulse fault condition and wherein the secondary-side controller is configured to: generate control signals directing the one or more power switches to apply a primary-side voltage pulse across the primary winding of the transformer; determine, based upon the sensed first rectified voltage, whether the generated control signals and the associated primary-side voltage pulse produced a corresponding rectified voltage pulse at the first rectified voltage node; and detect, responsive to determining that no corresponding rectified voltage pulse was produced, the missing-pulse fault condition.
generate control signals directing the one or more power switches to apply a primary-side voltage pulse across the primary winding of the transformer;
determine, based upon the sensed first rectified voltage, whether the generated control signals and the associated primary-side voltage pulse produced a corresponding rectified voltage pulse at the first rectified voltage node; and
detect, responsive to determining that no corresponding rectified voltage pulse was produced, the missing-pulse fault condition.
The switched-mode power converter of claim 1 , wherein the fault condition is a voltage-asymmetry fault condition and wherein the secondary-side controller is configured to: generate control signals directing the one or more power switches to apply a first primary-side voltage pulse across the primary winding of the transformer, wherein the first primary-side voltage pulse has a first polarity; detect, based on the sensed rectified voltage, a first rectified voltage pulse corresponding to the first primary-side voltage pulse, the first rectified pulse having a first voltage amplitude; generate control signals directing the one or more power switches to apply a second primary-side voltage pulse across the primary winding of the transformer, wherein the second primary-side voltage pulse has a second polarity that is opposite to the first polarity; detect, based on the sensed rectified voltage, a second rectified voltage pulse corresponding to the second primary-side voltage pulse, the second rectified voltage pulse having a second voltage amplitude; determine that a difference between the first and second voltage amplitudes exceeds a voltage difference threshold; and detect, responsive to said determination, the voltage-asymmetry fault indication.
generate control signals directing the one or more power switches to apply a first primary-side voltage pulse across the primary winding of the transformer, wherein the first primary-side voltage pulse has a first polarity;
detect, based on the sensed rectified voltage, a first rectified voltage pulse corresponding to the first primary-side voltage pulse, the first rectified pulse having a first voltage amplitude;
generate control signals directing the one or more power switches to apply a second primary-side voltage pulse across the primary winding of the transformer, wherein the second primary-side voltage pulse has a second polarity that is opposite to the first polarity;
detect, based on the sensed rectified voltage, a second rectified voltage pulse corresponding to the second primary-side voltage pulse, the second rectified voltage pulse having a second voltage amplitude;
determine that a difference between the first and second voltage amplitudes exceeds a voltage difference threshold; and
detect, responsive to said determination, the voltage-asymmetry fault indication.
The switched-mode power converter of claim 1 , wherein the fault indication is a pulse-interval fault indication and wherein the secondary-side controller is configured to: generate control signals directing the one or more power switches to apply a first primary-side voltage pulse, having a first pulse interval, across the primary winding of the transformer; determine, based on the sensed rectified voltage, a first rectified voltage pulse interval corresponding to the first pulse interval; detect that the first rectified voltage pulse interval is outside of an acceptable interval range, wherein the acceptable interval range is based upon the first pulse interval; and detect, responsive to said determination, the pulse-interval fault indication.
generate control signals directing the one or more power switches to apply a first primary-side voltage pulse, having a first pulse interval, across the primary winding of the transformer;
determine, based on the sensed rectified voltage, a first rectified voltage pulse interval corresponding to the first pulse interval;
detect that the first rectified voltage pulse interval is outside of an acceptable interval range, wherein the acceptable interval range is based upon the first pulse interval; and
detect, responsive to said determination, the pulse-interval fault indication.
The switched-mode power converter of claim 1 , wherein the secondary-side controller is configured to: generate, during a start-up interval in which the switched-mode power converter operates in a start-up operational mode, control signals directing the one or more power switches to apply primary-side voltage pulses to the primary winding of the transformer; detect, based on the sensed first rectified voltage, rectified voltage pulses; suppress fault indications based on the first rectified voltage pulses during the start-up interval; convert from the start-up operational mode to a normal operational mode, responsive to detecting that a first of the rectified voltage pulses comprises a voltage amplitude, a rectified pulse interval, or both a voltage amplitude and a rectified pulse interval that indicate the normal operational mode may commence; and subsequent to converting to the normal operational mode, ceasing the suppression of the fault indications.
generate, during a start-up interval in which the switched-mode power converter operates in a start-up operational mode, control signals directing the one or more power switches to apply primary-side voltage pulses to the primary winding of the transformer;
detect, based on the sensed first rectified voltage, rectified voltage pulses;
suppress fault indications based on the first rectified voltage pulses during the start-up interval;
convert from the start-up operational mode to a normal operational mode, responsive to detecting that a first of the rectified voltage pulses comprises a voltage amplitude, a rectified pulse interval, or both a voltage amplitude and a rectified pulse interval that indicate the normal operational mode may commence; and
subsequent to converting to the normal operational mode, ceasing the suppression of the fault indications.
The switched-mode power converter of claim 1 , wherein the detected fault condition indicates an unsafe operating condition of the switched-mode power converter; and wherein the secondary-side controller is configured to, responsive to detection of the fault condition, disable generation of switch control signals for controlling the one or more power switches.
wherein the detected fault condition indicates an unsafe operating condition of the switched-mode power converter; and
wherein the secondary-side controller is configured to, responsive to detection of the fault condition, disable generation of switch control signals for controlling the one or more power switches.
The switched-mode power converter of claim 1 , wherein the detected fault condition indicates that operation of the switched-mode power converter may proceed with an altered operation; and wherein the secondary-side controller is configured to, responsive to detection of the fault condition, alter an operational mode for generating switch control signals for controlling the one or more power switches.
wherein the detected fault condition indicates that operation of the switched-mode power converter may proceed with an altered operation; and
wherein the secondary-side controller is configured to, responsive to detection of the fault condition, alter an operational mode for generating switch control signals for controlling the one or more power switches.
The switched-mode power converter of claim 1 , wherein the secondary-side controller is configured to: provide the generated fault indication to an output of the secondary-side controller.
provide the generated fault indication to an output of the secondary-side controller.
An electronic system comprising: an input power source; an output load; a switched-mode power converter using an isolated topology for converting power from the input power source into power for the output load, the switched-mode power converter comprising: a power stage coupled to the input source and comprising one or more power switches; a transformer comprising a primary winding coupled to the power stage, and a secondary winding; a rectifier circuit coupled to the secondary winding and configured to provide a first rectified voltage at a first rectified voltage node; a filter circuit interposed between the first rectified voltage node and an output of the switched-mode power converter, and configured to filter the first rectified voltage, thereby providing a filtered voltage at the output; and a secondary-side controller configured to: sense the first rectified voltage; detect a fault condition within the switched-mode power converter based upon the sensed first rectified voltage; and generate a fault indication responsive to said detection; a system manager configured to: input the fault indication; and responsive to determining that the fault indication indicates an unsafe operating condition or a condition likely to damage the electronic system, shut down the switched-mode power converter.
an input power source;
a switched-mode power converter using an isolated topology for converting power from the input power source into power for the output load, the switched-mode power converter comprising: a power stage coupled to the input source and comprising one or more power switches; a transformer comprising a primary winding coupled to the power stage, and a secondary winding; a rectifier circuit coupled to the secondary winding and configured to provide a first rectified voltage at a first rectified voltage node; a filter circuit interposed between the first rectified voltage node and an output of the switched-mode power converter, and configured to filter the first rectified voltage, thereby providing a filtered voltage at the output; and a secondary-side controller configured to: sense the first rectified voltage; detect a fault condition within the switched-mode power converter based upon the sensed first rectified voltage; and generate a fault indication responsive to said detection;
a power stage coupled to the input source and comprising one or more power switches;
a transformer comprising a primary winding coupled to the power stage, and a secondary winding;
a rectifier circuit coupled to the secondary winding and configured to provide a first rectified voltage at a first rectified voltage node;
a filter circuit interposed between the first rectified voltage node and an output of the switched-mode power converter, and configured to filter the first rectified voltage, thereby providing a filtered voltage at the output; and
a secondary-side controller configured to: sense the first rectified voltage; detect a fault condition within the switched-mode power converter based upon the sensed first rectified voltage; and generate a fault indication responsive to said detection;
detect a fault condition within the switched-mode power converter based upon the sensed first rectified voltage; and
generate a fault indication responsive to said detection;
a system manager configured to: input the fault indication; and responsive to determining that the fault indication indicates an unsafe operating condition or a condition likely to damage the electronic system, shut down the switched-mode power converter.
input the fault indication; and
responsive to determining that the fault indication indicates an unsafe operating condition or a condition likely to damage the electronic system, shut down the switched-mode power converter.
The electronic system of claim 12 , wherein the system manager is configured to: responsive to determining that the fault indication is a warning signal, alter an operational mode for generating switch control signals for controlling the one or more power switches.
responsive to determining that the fault indication is a warning signal, alter an operational mode for generating switch control signals for controlling the one or more power switches.
A method within an isolated switched-mode power converter for converting power from an input source into power for an output load, wherein the power converter comprises a primary side including a power stage coupled to the input source and comprising one or more power switches, a transformer comprising a primary winding coupled to the power stage and a secondary winding, and a secondary side including a rectifier circuit coupled to the secondary winding and configured to provide a first rectified voltage at a first rectified voltage node, a filter circuit interposed between the first rectified voltage node and an output of the switched-mode power converter, the method comprising: sensing the first rectified voltage; detecting, based upon the first rectified voltage sensed on the secondary side, a fault condition of the primary side; and generating a fault indication and/or modifying operation of the switched-mode power converter responsive to said detecting.
sensing the first rectified voltage;
detecting, based upon the first rectified voltage sensed on the secondary side, a fault condition of the primary side; and
generating a fault indication and/or modifying operation of the switched-mode power converter responsive to said detecting.
The method of claim 14 , further comprising: estimating an input voltage of the input source based upon the sensed first rectified voltage.
estimating an input voltage of the input source based upon the sensed first rectified voltage.
The method of claim 15 , wherein the fault condition is an undervoltage fault indication, and wherein estimating the input voltage comprises: detecting a rectified voltage pulse based upon voltage measurements of the sensed first rectified voltage; determining a representative voltage amplitude for the rectified voltage pulse based on the voltage measurements; and estimating the input voltage based upon the representative voltage amplitude,
wherein the method further comprises: detecting, responsive to determining that the estimated input voltage is lower than an undervoltage threshold, the undervoltage fault condition.

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