Office Action 1: Non-Final Rejection (2023-11-22)
Rejection types: 102 - Lack of Novelty, 103 - Obviousness

CLAIMS:
WHAT IS CLAIMED IS:

1\. A system for protecting a speculative execution processor, from side channel attacks, comprising a processing circuitry, adapted to:
in a first time period performing an execution of a code segment in a plurality of time intervals;
storing speculative instructions in an internal cache memory which is inaccessible to read actions of an external processing unit;
in a second time period copying only a committed portion of the executed code segment into another memory component which is accessible to read actions of the external processing unit;
wherein the first and second time periods are different and independent.

2\. The system of claim 1, wherein the processing circuitry is further adapted to:
measure an execution time of the code segment in a plurality of time intervals;
update a time register to include a highest execution time measured for the plurality of time intervals; and
delay the copying only the committed portion of the executed code segment into the another memory component according to the highest execution time.

3\. The system of claim 2, wherein the processing circuitry is further adapted to:
delay the copying only the committed portion of the executed code segment into the another memory component according to a value which is not correlated with the actual execution time measured.

4\. The system of claim 1, wherein a user annotates the beginning and the end of the code segment with dedicated instructions respectively.

5\. The system of claim 4, wherein the executed code segment annotated by the user is a single entry code segment.

6\. The system of claim 4, wherein the executed code segment annotated by the user is a multi- entry code segment.

7\. The system of claim 6, wherein the annotation of the multi-entry code segment is extended, according to a number of an entry.

8\. The system of claim 6, wherein in the multi entry code segment each entry is allocated in a table-like structure and each entry number is determined by using one or more hash functions that take an address of the instruction annotating the beginning of the protected code segment as a parameter.

9\. The system of claim 1, wherein the processing circuit is further adapted to add noise in conjunction with the execution of the code segment to increase a noise to signal ratio.

10\. The system of claim 1, wherein the processing circuitry is adapted to perform a double execution of the code segment.

11\. The system of claim 1, wherein the speculative instructions stored in the internal cache memory are load and store instructions.

12\. The system of claim 1, wherein the internal cache memory is virtually tagged.

13\. The system of claim 1, wherein the internal cache memory is exclusive so that data cannot be stored in the internal cache memory and into the another memory component at a same time.

14\. The system of claim 1, wherein the internal cache memory is cleaned at the end of a process.

15\. The system of claim 1, wherein the internal cache memory is dynamically partitioned among different threads.

16\. The system of claim 1, wherein the internal cache memory is a scratchpad memory.

17\. A method for protecting speculative execution processor, from side channel attacks, comprising:
in a first time period performing an execution a code segment by storing speculative instructions in an internal cache memory which is inaccessible to read actions of an external processing unit; in a second time period copying only a committed portion of the executed code segment into another memory component which is accessible to read actions of the external processing unit;
wherein the first and second time periods are different and independent.

18\. The method of claim 17, further comprising:
measuring an execution time of the code segment in a plurality of time intervals;
updating a time register to include a highest execution time measured for the plurality of time intervals; and
delaying the copying only the committed portion of the executed code segment into the another memory component according to the highest execution time.

19\. A computer program product provided on a non-transitory computer readable storage medium storing instructions for performing a method for protecting speculative execution processor, from side channel attacks, comprising:
in a first time period performing an execution a code segment by storing speculative instructions in an internal cache memory which is inaccessible to read actions of an external processing unit;
in a second time period copying only a committed portion of the executed code segment into another memory component which is accessible to read actions of the external processing unit;
wherein the first and second time periods are different and independent.

20\. The method performed by the computer program product of claim 19, further comprising:
measuring an execution time of the code segment in a plurality of time intervals;
updating a time register to include a highest execution time measured for the plurality of time intervals; and
delaying the copying only the committed portion of the executed code segment into the another memory component according to the highest execution time.

OFFICE ACTION:
DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, field on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to application filed on 12/15/2021. In the application, claims 1-20 are examined and pending.
Specification
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
The abstract of the disclosure is objected to because the abstract is written as a claim. It repeats claim 1.  Correction is required.  See MPEP § 608.01(b).
Claim Objections
Claims 4, 8, 14, 17 and 19 are objected to because of the following informalities:
Claim 4 recites on line 1- “the beginning and the end.”
There is insufficient antecedent basis for this limitation in the claim. For examination purposes, “the beginning and the end” will be interpreted as “a beginning and an end.” To overcome this objection, “the beginning and the end” could be changed to “a beginning and an end,” for example.
Claim 8 recites on line 3- “the instruction annotating.” There is insufficient antecedent basis for this limitation in the claim. For examination purposes, “the instruction annotating” will be interpreted as “a instruction annotating.” To overcome this objection, “the instruction annotating” could be changed to “a instruction annotating,” for example.
Claim 8 recites on line 3- “the beginning.” There is insufficient antecedent basis for this limitation in the claim. For examination purposes, “the beginning” will be interpreted as “a beginning.” To overcome this objection, “the beginning” could be changed to “a beginning,” for example.
Claim 8 recites on line 3- “the protected code segment.” There is insufficient antecedent basis for this limitation in the claim. For examination purposes, “the protected code segment” will be interpreted as “an protected code segment.” To overcome this objection, “the protected code segment” could be changed to “an protected code segment,” for example.
Claim 14 recites on line 1- “the end of a process.” There is insufficient antecedent basis for this limitation in the claim. For examination purposes, “the end of a process” will be interpreted as “an end of a process.” To overcome this objection, “the end of a process” could be changed to “an end of a process,” for example.
In claim 17, on line 3, the limitation “an execution a code segment” should state “an execution of a code segment.”
In claim 19, on line 4, the limitation “an execution a code segment” should state “an execution of a code segment.”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA  35 U.S.C. 102 and 103 (or as subject to pre-AIA  35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA  to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
5.	The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 11, 13-15, 17 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Johnson et al. (US 20190114422 A1).
Regarding claim 1, Johnson teaches a system for protecting a speculative execution processor, from side channel attacks, comprising a processing circuitry, ([0021] Lines 1-20; At least some embodiments described herein are directed to processor modifications that prevent the observation of the side effects of mispredicted speculative execution flows…….. As such, the processor can make use of speculative execution after a branch or conditional load, but avoid performing any operation that could cause observable side-effects if the operation was mispredicted.) adapted to:
in a first time period performing an execution of a code segment in a plurality of time intervals ([0030] Lines 3-7; Initially, each microprocessor may include components to fetch, decode, and dispatch executable instructions for execution (e.g., an instruction fetcher 201, an instruction decoder 202, and an instruction dispatcher 203)…Typically, …fetches a block of multiple execution instructions at a time.; [0033] Lines 1-3; Using this setup, a processor can continually fill a “pipeline,” and execute instructions out-of-order and in parallel in this pipeline.; This is consistent with the teachings of the applicant’s disclosure paragraph: Page 17 Lines 19-20; “an execution time of the code segment is measured in a plurality of time intervals (each time the code segment is executed).”);
storing speculative instructions in an internal cache memory which is inaccessible to read actions of an external processing unit ([0075] Line 7; internal caches/buffers;  [0118] Lines 8-13; the microprocessor can include first logic (e.g., circuitry and/or microcode) that records the effects of one or more speculatively-executed instructions to the one or more speculation buffers, and that records the effects of non-speculatively-executed instructions to the one or more conventional buffers (e.g., per flowchart 800).; [0124] Lines 1-6; the embodiments described herein enable a processor to utilize speculative execution after a branch or conditional load, and avoids observable side-effects of memory loads during this speculative execution by buffering the results/effects of those loads into one or more speculation buffers.);
in a second time period copying only a committed portion of the executed code segment into another memory component which is accessible to read actions of the external processing unit ([0031] Lines 1-6; The instruction decoder 202 decodes each fetched instruction, and typically breaks it into a plurality of smaller micro-operations for processing by various execution units 204. The instruction dispatcher 203 then dispatches these micro-operations to the appropriate execution unit 204, which independently performs its respective tasks.; [0034] Lines 1-3; As the execution units 204 complete the micro-operations, the results of these operations flow into a retire unit 208.; [0040] Lines 4-5; the retire unit 208 does not commit any results unless they should be committed.;  [0103] and [0104] Lines 1-12; In some implementations, once at least one instruction retires, any speculative data cache 714a entries referenced by that instruction are eligible to be “promoted” or “committed” into the L1 data cache 712a [examiner interprets the copying/storing of instructions into the L1 data cache 712a once retired as a second time period ], as these data references are no longer speculative……. In some implementations, a speculative data cache 714a can be considered as a strictly “read only” cache);
wherein the first and second time periods are different and independent ([0030] Lines 3-7; Initially, each microprocessor may include components to fetch, decode, and dispatch executable instructions for execution (e.g., an instruction fetcher 201, an instruction decoder 202, and an instruction dispatcher 203).; [0034] Lines 1-5; As the execution units 204 complete the micro-operations, the results of these operations flow into a retire unit 208. Based on these results, the retire unit 208 determines how to ensure that the instructions (fetched by the instruction fetcher 201) complete in the correct order.; [0031] Lines 1-6; The instruction decoder 202 decodes each fetched instruction, and typically breaks it into a plurality of smaller micro-operations for processing by various execution units 204. The instruction dispatcher 203 then dispatches these micro-operations to the appropriate execution unit 204, which independently performs its respective tasks.).
Regarding claim 11, Johnson teaches the system of claim 1, wherein the speculative instructions stored in the internal cache memory are load and store instructions ([0062] Lines 1-5; These mechanisms ensure that speculative operations can proceed out-of-order following a branch, but that no speculative load may depend on another speculative load (except for store-to-load forwarding hits) when the youngest parent branch is still speculative and has yet to resolve.; [0118] Lines 8-13; the microprocessor can include first logic (e.g., circuitry and/or microcode) that records the effects of one or more speculatively-executed instructions to the one or more speculation buffers, and that records the effects of non-speculatively-executed instructions to the one or more conventional buffers (e.g., per flowchart 800).).
Regarding claim 13, Johnson teaches the system of claim 1, wherein the internal cache memory is exclusive so that data cannot be stored in the internal cache memory and into the another memory component at a same time ([0062] Lines 1-5; In addition to filling cache hierarchies from the “inside out” to avoid observable side effects, some embodiments utilize the processor's CCP to ensure that speculative operations cause no observable side-effects (e.g., a change in CCP state for a cache line) when another processor/core uses the cache line in a shared cache scenario. In other words, when performing speculative operations, some embodiments ensure that another core's view of the CCP state of a cache line remains uninterrupted until these speculative operations are ready to be committed. The particular manner in which this is accomplished may vary depending on the CCP being used. For example, if another core has a needed cache line as “modified” or “exclusive” then speculative operation may be held until it is the oldest operation in the machine. This ensures that execution of the speculative operation will not cause a state changing operation on the CCP. To illustrate, during execution of a speculative instruction, a first processing element (e.g., physical or logical core) may able to fill a speculation buffer (e.g., a data cache), by performing a cache probe according to a CCP to obtain data from a second processing element. However, this instruction may be held (such that speculation buffer is not filled) if that cache probe would result in a cache state change in a cache (e.g., a data cache) used by the second processing element).
Regarding claim 14, Johnson teaches the system of claim 1, wherein the internal cache memory is cleaned at the end of a process ([0122] Lines 1-10; In these implementations, the microprocessor can include second logic (e.g., circuitry and/or microcode) that (i) commits the recorded effects from the one or more speculation buffers to the one or more conventional buffers when the one or more speculatively-executed instructions that generated the effects are committed, and that (ii) discards the effects from the one or more speculation buffers when the one or more speculatively-executed instructions are cancelled (e.g., per flowchart 900).).
Regarding claim 15, Johnson teaches the system of claim 1, wherein the internal cache memory is dynamically partitioned among different threads (Johnson (US 20190114422 A1): [0122] Lines 1-10; In some implementations, the one or more speculation buffers include a first speculation buffer that is used by first speculatively-executed instructions from a first context, and a second speculation buffer that is used by second speculatively-executed instructions from a second context. These contexts could comprise different threads, different processes, different security contexts, and the like. In these implementations, the first speculation buffer could be a first segment of a buffer, and the second speculation buffer could be a second segment of the buffer.).
Regarding claim 17, claim 17 is directed to a method claim that recites a similar limitation as the system of claim 1. Therefore claim 17 is rejected based on the same rational as claim 1 above.
Regarding claim 19, claim 19 is directed to a computer program product claim that recites a similar limitation as the system of claim 1. Therefore claim 19 is rejected based on the same rational as claim 1 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the
claimed invention is not identically disclosed as set forth in section 102, if the
differences between the claimed invention and the prior art are such that the
claimed invention as a whole would have been obvious before the effective filing
date of the claimed invention to a person having ordinary skill in the art to which
the claimed invention pertains. Patentability shall not be negated by the manner
in which the invention was made.
The factual inquiries for establishing a background for determining obviousness
under 35 U.S.C. 103 are summarized as follows:
Determining the scope and contents of the prior art.
Ascertaining the differences between the prior art and the claims at issue.
Resolving the level of ordinary skill in the pertinent art.
Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 20190114422 A1) as stated in claims 1, 11, 13-15, 17 and 19 above, and further in view of Klaiber et al. (US 7962909 B1) and Michalak et al. (US 20080046692 A1).
Regarding claim 2, Johnson teaches the system of claim 1.
However, Johnson does not explicitly teach wherein the processing circuitry is further adapted to:
measure an execution time of the code segment in a plurality of time intervals;
update a time register to include a highest execution time measured for the plurality of time intervals; and
delay the copying only the committed portion of the executed code segment into the another memory component according to the highest execution time.
Klaiber teaches wherein the processing circuitry is further adapted to:
measure an execution time of the code segment in a plurality of time intervals (Col 5 Lines 38-54; The guest limit circuit may monitor the processor's execution core to detect an end of the execution interval, and may cause the processor to exit the guest at the end of the execution interval. As used herein, an execution interval refers to any period allocated for the guest to execute. The guest may exit during the execution interval if an intercept is detected. However, if the guest is still executing at the end of the execution interval (i.e. no intercepts have been detected), the guest limit circuit may cause the guest to exit (e.g. similar to exiting due to an intercept). The execution interval may be measured in any desired fashion. For example, the execution interval may be a period of time (e.g. real time, or measured in terms of processor clock cycles). The execution interval may be defined by a number of detections of a given event or events in the processor. For example, the event may be the execution of an instruction (and thus the execution interval may be defined by the number of guest instructions executed).)
Klaiber (Limiting guest execution) is a similar application to Johnson. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Johnson to incorporate the teachings of Klaiber by incorporating measuring an execution time of the code segment in a plurality of time intervals. Measuring the execution time will allow a user to be aware of when the guest actually begins execution in the processor. Additionally, it may closely monitor operation of the processor's execution core during guest execution, which may permit accurate detection of events that define the execution interval for the guest.
However, Johnson, in view of Klaiber, does not explicitly teach update a time register to include a highest execution time measured for the plurality of time intervals; and
delay the copying only the committed portion of the executed code segment into the another memory component according to the highest execution time.
Michalak teaches update a time register to include a highest execution time measured for the plurality of time intervals ([0122] Lines 11-14; [0033] Lines 18-23; In response to the instruction, the main processor 12 may directly write the dynamic delay value to the coprocessor register 30.; [0022] Lines 20-23; For example, highly speculative instructions may incur a greater execution delay while less speculative instructions may incur a lesser delay.); and
delay the copying only the committed portion of the executed code segment into the another memory component according to the highest execution time ([0122] Lines 1-7; [0022] Lines 18-23; As such, each instruction or set of instructions offloaded to the coprocessor 14 may incur an execution delay based on their speculative nature. For example, highly speculative instructions may incur a greater execution delay while less speculative instructions may incur a lesser delay.; [0035] Lines 4-11; When an instruction or set of instructions are offloaded to the coprocessor 14, the delay determination unit 16 accesses the history table 50 to determine whether the instruction(s) are more or less likely to be committed by the main processor 12. The more speculative the instruction(s), the greater the delay assigned to the instruction(s). The converse holds true for less speculative instructions.; [0025] Lines 23-26; the coprocessor 14 may store temporary results generated by it until the producing instructions are committed, at which time the register file 19 is updated.).
Michalak (Executing processor instructions based on a dynamically alterable delay) is a similar application to Johnson, in view of Klaiber. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Johnson, in view of Klaiber, to incorporate the teachings of Michalak by allowing highly speculative instructions may incur a greater execution delay. Increasing the delay so that instructions are not executed until first committed by the main processor will help in reducing power consumption.
Regarding claim 18, claim 18 is directed to a method claim that recites a similar limitation as the system of claim 2. Therefore claim 18 is rejected based on the same rational as claim 2 above.
Regarding claim 20, claim 20 is directed to a method claim that recites a similar limitation as the system of claim 2. Therefore claim 20 is rejected based on the same rational as claim 2 above.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 20190114422 A1), in view of Klaiber et al. (US 7962909 B1) and Michalak et al. (US 20080046692 A1), as stated in claims 1, 2, 11, 13-15 and 17-20 above, and further in view of Mekkat et al. (US 20180285112 A1).
Regarding claim 3, Johnson, in view of Klaiber and Michalak, teaches the system of claim 2.
However, Johnson, in view of Klaiber and Michalak, does not explicitly teach wherein the processing circuitry is further adapted to: delay the copying only the committed portion of the executed code segment into the another memory component according to a value which is not correlated with the actual execution time measured.
Mekkat teaches wherein the processing circuitry is further adapted to: delay the copying only the committed portion of the executed code segment into the another memory component according to a value which is not correlated with the actual execution time measured (For an instruction modifying a memory location, the processor may support delayed instruction reclamation by storing the speculative memory state value in a buffer under the local commit mode. The instruction reclamation is delayed as compared to reclamation without atomicity. Storing in the buffer may delay the commit to the transactional memory until the occurrence of a global commit event.; Col 2-3 Line 66 to Line 3 of Col 3; The code may include region boundaries that define point of time in execution where the processor state (memory and register) are correct [examiner interprets defining a point of time in execution where the processor state are correct as the actual execution time measured] and can be made visible to external world (other processors).; Col 2 Lines 30-41; The atomicity of a transaction including the execution of two or more instructions guarantees that the transaction completes or has no effect on the storage device (i.e., aborted transaction does not change the content in the storage). To achieve the atomicity for the execution of a set of instructions associated with a transaction, the system may need to create a checkpoint that captures the starting state of the system (including memory state values and register state values). Register and memory state values may define correct data values for corresponding registers and memory locations when the state of the microprocessor was known to be correct (non-speculative).).
Mekkat (To achieve the atomicity for the execution of a set of instructions associated with a transaction.) is a similar application to Johnson, in view of Klaiber and Michalak. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Johnson, in view of Klaiber and Michalak, to incorporate the teachings of Mekkat by incorporating delaying the copying only the committed portion of the executed code segment into the another memory component according to a value which is not correlated with the actual execution time measured. This will allow the system to be implemented to roll back to the checkpoint responsive to detecting a rollback event occurred during the transaction. The rollback guarantees that a failed transaction does not affect the state values of the system.
Claims 4 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 20190114422 A1) as stated in claims 1, 11, 13-15, 17 and 19 above, and further in view of Heller (US 20080288819 A1).
Regarding claim 4, Johnson teaches the system of claim 1.
However, Johnson does not explicitly teach wherein a user annotates the beginning and the end of the code segment with dedicated instructions respectively.
Heller teaches wherein a user annotates the beginning and the end of the code segment with dedicated instructions respectively ([0058] Lines 3-19; “The preferred embodiment of the invention uses a BEGIN_AIG instruction to indicate the beginning of an AIG and an END_AIG instruction to indicate the end of an AIG. BEGIN_AIG and END_AIG are marking code in the form of instructions representing any chosen equivalent function instruction or other suitable method of identification of a function marks the beginning and end of a group of instructions. These alternatives for marking code can be used. The instructions or marks may be inserted in the code explicitly by programmers in a high level language or added by compilers or translators as implementations of high level locking functions. The instructions or marks may be added by a library function call or be included by a special event in a runtime environment. The instructions or marks may be generated by firmware, hardware or a combination of both as a response to decoding a particular sequence of instructions or receiving a special command to enter a new mode of execution.).
Heller (A method of fast detection of potential conflicts between multiple transactions.) is a similar application to Johnson. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Johnson to incorporate the teachings of Heller by incorporating a user annotates the beginning and the end of the code segment with dedicated instructions. The instructions or marks may be inserted in the code as implementations of high level locking functions. This locking level makes these storage engines more suitable for read-only, read-mostly, or single-user applications.
Regarding claim 6, Johnson teaches the system of claim 4.
However, Johnson does not explicitly teach wherein the executed code segment annotated by the user is a multi- entry code segment.
Heller teaches wherein the executed code segment annotated by the user is a multi- entry code segment ([0058] Lines 10-14; The instructions or marks may be inserted in the code explicitly by programmers in a high level language or added by compilers or translators as implementations of high level locking functions.; [0059] Lines 1-6; The preferred embodiment identifies the beginning of an AIG after decoding of an instruction (800). If it is determined that a BEGIN_AIG instruction has been decoded (805) the processor enters a new MILLICODE MODE (815) and begins execution of millicode routines which have been written to support transactional memory execution.  [0064] Lines 1-8; “it will be seen that the current invention uses an Address History Table (950) that is part of a multithreaded microprocessor (900) that has been designed for support of transactional memory and which uses millicode for the execution of complex instructions. The preferred embodiment uses a microprocessor that supports simultaneous multithreading (SMT) but other forms of multithreading such as hardware multithreading (HMT) may be used.” This is consistent with the teachings of the applicant’s disclosure paragraph: Page 14 Lines 30-31; “Support for multiple entries is needed primarily for multiple nested secure regions or to support multi-threaded applications.”).
Heller (A method of fast detection of potential conflicts between multiple transactions.) is a similar application to Johnson. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Johnson to incorporate the teachings of Heller by incorporating the executed code segment annotated by the user is a multi- entry code segment. Having a multi- entry code segment allows for the early setup of the code segments into entries and quick execution of the required code.
Regarding claim 7, Johnson teaches the system of claim 6.
However, Johnson does not explicitly teach wherein the annotation of the multi-entry code segment is extended, according to a number of an entry.
Heller teaches wherein the annotation of the multi-entry code segment is extended, according to a number of an entry ([0056] Lines 3-5; Each BEGIN_AIG special instruction (FIG. 7) statement causes the system to create a Transaction Table (230); [0056] Lines 22-28; The current invention can also be extended to include a combined Transaction Table that includes entries from both the inner AIG (Instruction B0, Instruction B1) and the outer AIG (Instruction A0, Instruction A1, Instruction A2). This Combined Transaction Table may be used in place of the individual Transaction Tables or in addition to the individual Transaction Tables. This is consistent with the teachings of the applicant’s disclosure paragraph: Page 2 Lines 24-25; “the multi entry code segment each entry is allocated in a table-like structure.”).
Heller (A method of fast detection of potential conflicts between multiple transactions.) is a similar application to Johnson. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Johnson to incorporate the teachings of Heller by incorporating the multi-entry code segment is extended, according to a number of an entry. The extension can include many additional hardware features that can be added to the invention to speed the processing of the Transaction Table manipulations.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 20190114422 A1), in view of Heller (US 20080288819 A1), as stated in claims 1,4, 6-7, 11, 13-15, 17 and 19 above, and further in view of Cain (US 20100138571 A1).
Regarding claim 8, Johnson, in view of Heller, teaches the system of claim 6.
However, Johnson, in view of Heller, does not explicitly teach wherein in the multi entry code segment each entry is allocated in a table-like structure and each entry number is determined by using one or more hash functions that take an address of the instruction annotating the beginning of the protected code segment as a parameter.
Cain teaches wherein in the multi entry code segment each entry is allocated in a table-like structure and each entry number is determined by using one or more hash functions that take an address of the instruction annotating the beginning of the protected code segment as a parameter ([0030] Lines 1-9; In the software portion 200, each of the multiple threads 220-1, . . . , 220-n can include multiple transactions. As shown in this figure, thread 220-1 includes transactions 2201 and 2202, and thread 220-n includes transactions 2203, 2204 and 2205. Threads 220-1, . . . , 220-n can belong to the same process or different threads.; [0045] Lines 1-14; In sharing buffer management system 100A shown in FIG. 2, predictor module 210 can have a two-level software hash table recording the latest N times of data size information for each transaction, e.g., transaction ID. The two-level hash table is designed with lock-free characteristics. The first level of the hash table is indexed by thread IDs, and the second level is indexed by transaction start addresses. The two-level structure of this hash table ensures that each thread has its private hash table, which avoids lock/unlock operations at the time of updating history information. The insert and delete operations for first-level entries can lock/unlock the hash table. Such actions are performed much less frequently than for updating the history information since they are only needed in case of thread creation and retirement.; [0039] Lines 2-5; In a program, each of the transactions 220-1, . . . , 220-n is marked by transaction_begin( ) a transaction begin runtime function, and transaction_end( ) a transaction end runtime functions.).
Cain (a new dynamic sharing buffer scheme in hardware transactional memory systems.) is a similar application to Johnson, in view of Heller. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Johnson, in view of Heller, to incorporate the teachings of Heller by incorporating each entry is allocated in a table-like structure and each entry number is determined by using one or more hash functions that take an address of the instruction annotating the beginning of the protected code segment as a parameter. Having a table- like structure can shift complexity from the hardware to the software almost without performance loss. The new sharing management solution can dynamically allocate resources for multiple transactions.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 20190114422 A1), in view of Heller et al. (US 20080288819 A1), as stated in claims 1, 4, 6-8, 11, 13-15, 17 and 19 above, and further in view of Jacobson et al. (DE 112006001698 T5).
Regarding claim 5, Johnson, in view of Heller, teaches the system of claim 4. Furthermore, Heller teaches wherein the executed code segment annotated by the user is a Heller: [0058] Lines 10-14; The instructions or marks may be inserted in the code explicitly by programmers in a high level language or added by compilers or translators as implementations of high level locking functions.; [0059] Lines 1-6; The preferred embodiment identifies the beginning of an AIG after decoding of an instruction (800). If it is determined that a BEGIN_AIG instruction has been decoded (805) the processor enters a new MILLICODE MODE (815) and begins execution of millicode routines which have been written to support transactional memory execution.  [0064] Lines 1-8; “it will be seen that the current invention uses an Address History Table (950) that is part of a multithreaded microprocessor (900) that has been designed for support of transactional memory and which uses millicode for the execution of complex instructions. The preferred embodiment uses a microprocessor that supports simultaneous multithreading (SMT) but other forms of multithreading such as hardware multithreading (HMT) may be used.” This is consistent with the teachings of the applicant’s disclosure paragraph: Page 14 Lines 30-31; “Support for multiple entries is needed primarily for multiple nested secure regions or to support multi-threaded applications.”).
However, Johnson, in view of Heller, does not explicitly teach “a single entry code segment” being annotated by a user.
Jacobson teaches “a single entry code segment” being annotated by a user ([0044] Lines 1-8; In at least one other embodiment, an instruction set may be provided by the processor 200 supported will have explicit architectural marking instructions. This means that the instruction set for the processor 200 includes a Begin Monitor instruction that can be arranged by the programmer at the beginning of the atomic block, Similarly, the instruction set may be for the processor 200 may also include a Stop Monitor instruction which may be arranged by the programmer after the last instruction of the atomic block In at least one embodiment, a single instruction may be used to manipulate a control register to provide both the Begin Monitor and the Begin Monitor.StopMonitor to execute instructions.; [0032] Line 3; Every core 104 can be either a single-threaded or multi-threaded processor.).
Jacobson (Primitives to enhance thread-level speculation) is a similar application to Johnson, in view of Heller. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Johnson, in view of Heller, to incorporate the teachings of Jacobson  by incorporating the executed code segment annotated by the user is a single entry code segment. It would have been prima facie obvious to one skilled in the art to use a single entry code segment instead of a multi entry code segment. Having a single thread reduces the overhead of thread communication. Which works faster because all tasks using the same shared memory and no need for communication.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 20190114422 A1) as stated in claims 1, 11, 13-15, 17 and 19 above, and further in view of Patel et al. (US 9378363 B1).
Regarding claim 9, Johnson teaches the system of claim 1.
However, Johnson does not explicitly teach wherein the processing circuit is further adapted to add noise in conjunction with the execution of the code segment to increase a noise to signal ratio.
Patel teaches wherein the processing circuit is further adapted to add noise in conjunction with the execution of the code segment to increase a noise to signal ratio (Col 4 Lines 3-12; techniques are described for injecting noise in the timer value, so that an attacker from the malicious virtual machine cannot reliably use the time stamp counter to observe the response time of the shared hardware resources on the processor. According to one exemplary technique, in response to a request for a timer value by instructions executing from within a virtual machine, a virtual timer value is received instead of the hardware timer value. The virtual timer value may be derived using at least the timer value and a random value.; Col 11 Lines 22-24; The difference between the access time needed to discern the micro-architectural state of the processor may be referred to as “D.”; Col 12 Lines 53-61; Noise tolerance determinator 1010 may allow for a greater amount (or bits) of noise to be injected, while maintaining monotonicity, since the noise is accumulated and the variance in the noise cannot cause the noise in one timer value request to undercut the timer value presented in the previous request for the timer value. Therefore, in certain implementations, noise tolerance determinator 1010 may indicate the desired number of bits to around log.sub.2(D), where D may be greater than Z.; Col 13 Lines 13-16; By configuring D and B, a significant increase in D (i.e. significant occlusion of observability by the attacker) can be expected while maintaining relatively normal behavior for the system overall.).
Patel (Techniques are described for injecting noise in the timer value, so that an attacker from the malicious task, such as a virtual machine, cannot reliably use the time stamp counter to observe the response time of the shared hardware resources on the processor.) is a similar application to Johnson. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Johnson to incorporate the teachings of Patel by adding noise in conjunction with the execution of the code segment to increase a noise to signal ratio. Adding noise will prevent an attacker from using the time stamp counter to observe the response time of the shared hardware resources on the processor.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 20190114422 A1) as stated in claims 1, 11, 13-15, 17 and 19 above, and further in view of Atsushi et al. (JP H1196005 A).
Regarding claim 10, Johnson teaches the system of claim 1.
However, Johnson does not explicitly teach wherein the processing circuitry is adapted to perform a double execution of the code segment.
Atsushi teaches wherein the processing circuitry is adapted to perform a double execution of the code segment ([0015] Lines 1-5; In order to achieve the above-mentioned object, the present invention effectively utilizes a thread execution unit on a parallel processing device having a plurality of thread execution units to branch an instruction after a conditional branch instruction. By speculatively executing both the non-branch side and the non-branch side, and canceling the execution on the wrong side when the conditional branch instruction is determined, it is possible to continue execution without substantially deviating the branch prediction and improve performance Is to achieve. Hereinafter, such a processing method is referred to as “branch double execution”.).
Atsushi (To achieve improvement in performance by executing instructions after a condition branching instruction on both a branch side and a non-branch side in the manner of timing and canceling the execution on the side of an error at the time point when the condition branching instruction is fixed.) is a similar application to Johnson. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Johnson to incorporate the teachings of Atsushi by incorporating a processing circuitry that is adapted to perform a double execution of the code segment. This enables high-speed execution of a branch instruction that is difficult to predict, and at the same time enables effective use of the thread execution unit in a portion of the program where parallel execution is difficult.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 20190114422 A1) as stated in claims 1, 11, 13-15, 17 and 19 above, and further in view of Boggs et al. (WO 2019005975 A1).
Regarding claim 12, Johnson teaches the system of claim 1.
However, Johnson does not explicitly teach wherein the internal cache memory is virtually tagged.
Boggs teaches wherein the internal cache memory is virtually tagged (Boggs (WO 2019005975 A1): [0044] Lines 7-9; Note that even though the LI Data and LI Code caches 110, 112 are virtually tagged, accesses still have to be verified with the physical addresses translated using information from page tables 114.;  [0056] Lines 1-3; values requested by speculative execution would be retrieved from memory and stored in the LI cache 110, 112 irrespective of the privilege level of the application.).
Boggs (Speculative execution cannot access and expose a memory location that is speculatively inaccessible.) is a similar application to Johnson. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Johnson to incorporate the teachings of Boggs by allowing the internal cache memory to be virtually tagged. Virtual addressing also permits different processes for example to have the same views of their respective private virtual address spaces while sharing a common physical address space in a secure way.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 20190114422 A1) as stated in claims 1, 11, 13-15, 17 and 19 above, and further in view of Christie et al. (US 6055650 A).
Regarding claim 16, Johnson teaches the system of claim 1.
However, Johnson does not explicitly teach wherein the internal cache memory is a scratchpad memory.
Christie teaches wherein the internal cache memory is a scratchpad memory (Christie (US 6055650 A): Col 9 Lines 48-51; “Instruction results are stored into register file 24 by reorder buffer 22 in program order. Storing the results of an instruction and deleting the instruction from reorder buffer 22 is referred to as retiring the instruction.; Col 10 Lines 39-46; Phase change monitor 26 determines whether or not a switch from user mode to supervisor mode is detected (decision block 60). Supervisor mode is generally used by the operating system, while user mode is generally used by the application programs. In supervisor mode, access to certain protected processor resources (such as control and configuration registers) may be permitted.”  This is consistent with the teachings of the applicant’s disclosure paragraph: Page 12 Lines 7-9; “the internal cache memory may be implemented by a scratchpad memory, which is a memory that is managed by a user as a client device, rather than being managed by hardware.”).
Christie (Processor configured to detect program phase changes and to adapt thereto) is a similar application to Johnson. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Johnson to incorporate the teachings of Christie by allowing the internal cache memory to be scratchpad memory. This will provide the system a fast and low power memory while having the ability to shut down certain side-channels by placing sensitive data in the scratchpad.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Vincent (EP 3557471 A1 ) teaches power rail noise monitoring to detect attempted security tampering or side channel attacks.
van Dijk (US 8909967 B1) teaches a technique for secure computation.


NEXT OFFICE ACTION: DETAILED ACTION
This Final Office Action is in response to amendment filed on 02/21/2024. Claims 1, 3, 4, 8, 14, 17 and 19, filed on 02/21/2024, have been amended. Claims 2, 18 and 20 have been canceled. Claims 1, 3-17, and 19 remain pending in the application.
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments to the Abstract has overcome the objection previously set forth in the Non-Final Office Action mailed on 11/22/2023.
Applicant’s claims amendments has overcome the claims objections previously set forth in the Non-Final Office Action mailed on 11/22/2023.
Applicant’s claims amendments, in conjunction with the applicant’s remarks filed on 02/21/2024, has overcome the USC 103 rejections previously set forth in the Non-Final Office Action mailed on 11/22/2023.
Specification
The disclosure is objected to because of the following minor informalities: Page 1 lines 16-17 recites “When the tasks are really required the speed up is achieved…”, should read “When the tasks are really required, the speed up is achieved…”.
Appropriate correction is required.
Claim Objections
Claims 17 and 19 objected to because of the following minor informalities:
Claims 17 and 19 recite “in a first time period performing…”, should read “in a first time, period performing…”
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 19 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
Claim 19 recites in the preamble “A computer program product provided on a non-transitory computer readable storage medium storing instructions for performing a method …”. However, the body of claim 19 recites “measuring… updating… performing…”, which under the broadest reasonable interpretation are considered program per se.  Furthermore, the mere recitation that the “program product is provided on a non-transitory computer readable storage medium” does not mean that the a non-transitory computer readable storage medium is part of the claimed “computer program product”. Therefore claim 19 is non-statutory because it is directed towards program, per se. In order to overcome the above USC 101 rejection, examiner recommends amending claim 19 to recite “A computer program product comprising a non- transitory computer readable storage medium storing instructions for performing a method for protecting speculative execution processor, from side channel attacks…”
Allowable Subject Matter
Claims 1, 3-16 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Cited and relevant prior art of record:
Johnson et al. (US 20190114422 A1),
Klaiber et al. (US 7962909 B1),
Michalak et al. (US 20080046692 A1), and
Courtney (US 20180323960 A1).
Johnson discloses processor modifications that prevent the observation of the side effects of mispredicted speculative execution flows, the processor can make use of speculative execution after a branch or conditional load, but avoid performing any operation that could cause observable side-effects if the operation was mispredicted, Johnson further discloses recording the effects of one or more speculatively-executed instructions to the one or more speculation buffers, utilize speculative execution after a branch or conditional load, and avoids observable side-effects of memory loads during this speculative execution by buffering the results/effects of those loads into one or more speculation buffers. Klaiber discloses monitoring a processor's execution core to detect an end of an execution interval, and causes the processor to exit a guest at the end of the execution interval. Michalak discloses a processor may directly write the dynamic delay value to a coprocessor register, highly speculative instructions may incur a greater execution delay while less speculative instructions may incur a lesser delay, each instruction or set of instructions offloaded to the coprocessor may incur an execution delay based on their speculative nature. For example, highly speculative instructions may incur a greater execution delay while less speculative instructions may incur a lesser delay. Courtney discloses a method and apparatus for defending against a side-channel attack upon a data storage device, and further discloses that in response to a function call signal being generated to request execution of a given function, a timer circuit is initiated to count out a predetermined elapsed time interval. The overall duration of the elapsed time interval is selected based on empirical or adaptive measurements, or system specifications, regarding the maximum likely duration of the execution of the function.
While the above prior arts disclose the aforementioned concepts, however, none of the prior arts, individually or in reasonable combination, discloses all the limitations in the manner recited in the independent claims. Specifically, none of the prior art discloses “…in a first time period performing, an execution of a code segment by storing speculative instructions in an internal cache memory which is inaccessible to read actions of an external processing unit; measuring an execution time of the code segment in a plurality of time intervals; updating a time register to include a highest execution time measured for the plurality of time intervals; in a second time period, performing a delayed copy, wherein in said delayed copy, copying only a committed portion of the executed code segment into another memory component which is accessible to read actions of the external processing unite wherein a delay time of said delayed copy is according to the highest execution time included in said time register; wherein the first and second time periods are different and independent”. Therefore, the above limitations in conjunction with the remaining limitations of the independent claims render the above independent claims allowable.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action.  Accordingly, THIS ACTION IS MADE FINAL.  See MPEP § 706.07(a).  Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action.  In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action.  In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.

CITED REFERENCE SUMMARIES: Ref US6055650A: Claims:
A processor comprising: one or more processor resources; a phase change monitor coupled to said processor resources, wherein said phase change monitor is configured to detect a phase change in a program being executed by monitoring said processor resources, wherein at least one of said processor resources provides a hit/miss indication to said phase change monitor, wherein said phase change monitor is configured to detect said phase change responsive to said indication; and a prefetch unit coupled to said phase change monitor, wherein said prefetch unit is configured to selectively prefetch responsive to said phase change monitor.
one or more processor resources;
a phase change monitor coupled to said processor resources, wherein said phase change monitor is configured to detect a phase change in a program being executed by monitoring said processor resources, wherein at least one of said processor resources provides a hit/miss indication to said phase change monitor, wherein said phase change monitor is configured to detect said phase change responsive to said indication; and
a prefetch unit coupled to said phase change monitor, wherein said prefetch unit is configured to selectively prefetch responsive to said phase change monitor.
The processor as recited in claim 1 wherein said phase change monitor is configured to cause said prefetch unit to disable a current prefetch upon detecting said phase change.
The processor as recited in claim 1 wherein said phase change monitor is configured to cause said prefetch unit to enable a prefetch corresponding to a phase being entered upon detection of said phase change.
The processor as recited in claim 1 wherein said one or more processor resources comprises a decode unit configured to decode instructions, and wherein said phase change monitor is configured to detect said phase change upon a frequency of floating point instructions decoded by said decode unit crossing a predetermined threshold value.
The processor as recited in claim 1 wherein said one or more processor resources comprises a decode unit configured to decode instructions, and wherein said phase change monitor is configured to detect said phase change upon a frequency of multimedia instructions decoded by said decode unit crossing a predetermined threshold value.
The processor as recited in claim 1 wherein said one or more processor resources comprises a translation lookaside buffer configured to translate addresses to physical addresses, and wherein said phase change monitor is configured to detect said phase change upon a miss rate experienced by said translation lookaside buffer exceeding a predetermined threshold value.
The processor as recited in claim 1 wherein said one or more processor resources comprises a cache configured to store cache lines of memory, and wherein said phase change monitor is configured to detect said phase change upon a miss rate experienced by said cache exceeding a predetermined threshold value.
The processor as recited in claim 1 wherein said one or more processor resources comprises a reorder buffer configured to store speculative instruction results, and wherein said phase change monitor is configured to detect said phase change upon a number of entries within said reorder buffer reserved for said speculative instruction results exceeding a predetermined threshold value.
The processor as recited in claim 1 wherein said one or more processor resources comprises a reorder buffer configured to receive branch misprediction indications upon execution of branch instructions which are mispredicted, and wherein said phase change monitor is configured to detect said phase change upon a rate of said branch misprediction indications exceeding a predetermined threshold value.
The processor as recited in claim 1 wherein said one or more processor resources comprises a decode unit configured to decode instructions, and wherein said phase change monitor is configured to detect said phase change upon a frequency of branch instructions having a negative displacement decoded by said decode unit exceeding a predetermined threshold value.
The processor as recited in claim 1 wherein said phase change unit is configured to detect a first change in a processor mode from user to supervisor, and wherein said phase change unit is configured to suspend monitoring said processor resources and prefetching responsive to said first change.
The processor as recited in claim 11 wherein said phase change unit is configured to detect a second change in said processor mode from supervisor to user, and wherein said phase change unit is configured to resume monitoring said processor resources and prefetching responsive to said second change.
A method for prefetching in a processor executing a program, comprising: monitoring one or more processor resources, wherein at least one of said processor resources provide a hit/miss indication, wherein said hit/miss indication is used to detect a phase change in said program; and selectively enabling a prefetch responsive to said phase change.
monitoring one or more processor resources, wherein at least one of said processor resources provide a hit/miss indication, wherein said hit/miss indication is used to detect a phase change in said program; and
selectively enabling a prefetch responsive to said phase change.
The method as recited in claim 13 further comprising disabling a previously enabled prefetch responsive to said phase change.
The method as recited in claim 13 further comprising: detecting a switch from user mode to supervisor mode within said processor; and suspending said monitoring and said selectively enabling responsive to said detecting.
detecting a switch from user mode to supervisor mode within said processor; and
suspending said monitoring and said selectively enabling responsive to said detecting.
The method as recited in claim 13 further comprising: detecting a switch from supervisor mode to user mode within said processor; and resuming said monitoring and said selectively enabling responsive to said detecting.
detecting a switch from supervisor mode to user mode within said processor; and
resuming said monitoring and said selectively enabling responsive to said detecting.
A computer system comprising: a processor configured to execute a program, wherein said processor is configured to monitor one or more processor resources to detect a phase change in said program, wherein at least one of said processor resources provides a hit/miss indication to said processor, wherein said processor is configured to detect said phase change from said indication, wherein said processor is configured to selectively prefetch responsive to detecting said phase change; a memory coupled to said processor, wherein said memory is configured to store instructions and data for access by said processor; and an input/output (I/O) device coupled to said processor, wherein said I/O device is configured to communicate between said computer system and a second computer system coupled to said I/O device.
a processor configured to execute a program, wherein said processor is configured to monitor one or more processor resources to detect a phase change in said program, wherein at least one of said processor resources provides a hit/miss indication to said processor, wherein said processor is configured to detect said phase change from said indication, wherein said processor is configured to selectively prefetch responsive to detecting said phase change;
a memory coupled to said processor, wherein said memory is configured to store instructions and data for access by said processor; and
an input/output (I/O) device coupled to said processor, wherein said I/O device is configured to communicate between said computer system and a second computer system coupled to said I/O device.
The computer system as recited in claim 17 further comprising a second processor coupled to said memory and to said I/O device, wherein said second processor is configured to execute said program, and wherein said second processor is configured to monitor one or more processor resources to detect said phase change in said program, and wherein said second processor is configured to selectively prefetch responsive to detecting said phase change.
Ref US20080046692A1: Claims:
A method of controlling instruction execution, comprising: determining a first delay value for a first set of one or more instructions; delaying execution of the first set of one or more instructions based on the first delay; determining a second delay value for a second set of one or more instructions; and delaying execution of the second set of one or more instructions based on the second delay;
determining a first delay value for a first set of one or more instructions;
delaying execution of the first set of one or more instructions based on the first delay;
determining a second delay value for a second set of one or more instructions; and
delaying execution of the second set of one or more instructions based on the second delay;
The method of claim 1 , further comprising associating individual ones of the delay values with the corresponding set of one or more instructions.
The method of claim 2 , wherein associating individual ones of the delay values with the corresponding set of one or more instructions comprises tagging each set of one or more instructions with the corresponding delay value.
The method of claim 1 , wherein the delay values are determined during at least one of code compile time, code load time, and code run time.
The method of claim 1 , wherein the delay values are determined based on an application associated with the corresponding set of instructions.
The method of claim 5 , wherein the delay values are determined based on processor resources available to the corresponding application.
The method of claim 1 , wherein the delay values are determined based on processor resources available to a corresponding application.
The method of claim 1 , wherein determining the delay values comprises: maintaining a history of speculative instruction execution; and determining the delay values based on the history of speculative instruction execution.
maintaining a history of speculative instruction execution; and
determining the delay values based on the history of speculative instruction execution.
The method of claim 8 , wherein maintaining a history of speculative instruction execution comprises tracking occurrences of execution pipeline flushes.
The method of claim 1 , wherein the delay values indicate at least one of full-speculative instruction execution, non-speculative instruction execution, full-speculative instruction execution after a number of instruction processing delay cycles, and partially-speculative instruction execution.
The method of claim 10 , wherein partially-speculative instruction execution comprises halting execution of each instruction at a specified stage until the corresponding instruction is committed.
The method of claim 1 , wherein determining the delay values comprises: processing individual ones of the sets of one or more instructions to ascertain the corresponding delay value; and directing storage of the delay values.
processing individual ones of the sets of one or more instructions to ascertain the corresponding delay value; and
directing storage of the delay values.
The method of claim 12 , wherein delaying execution of individual ones of the sets of one or more instructions based on the corresponding delay value comprises: retrieving the delay values from the register; delaying execution of individual ones of the sets of one or more instructions based on the corresponding retrieved delay value; and directing storage of results of executing the sets of instructions.
retrieving the delay values from the register;
delaying execution of individual ones of the sets of one or more instructions based on the corresponding retrieved delay value; and
directing storage of results of executing the sets of instructions.
The method of claim 13 , wherein directing storage of results of executing the sets of instructions comprises temporarily storing results from uncommitted instructions associated with one or more of the sets of instructions.
The method of claim 14 , further comprising updating the architected state with results associated with at least one of the sets of one or more instructions that are committed.
The method of claim 14 , further comprising clearing the results associated with uncommitted instructions in response to an execution pipeline flush condition.
The method of claim 16 , wherein the execution pipeline flush condition corresponds to at least one of a branch misprediction error, an exception, a trap, an interrupt, and a fault.
A processing apparatus, comprising: a delay determination unit configured to determine a first delay value for a first set of one or more instructions and a second delay value for a second set of one or more instructions; and a processing unit configured to delay execution of the first set of one or more instructions based on the first delay and delay execution of the second set of one or more instructions based on the second delay.
a delay determination unit configured to determine a first delay value for a first set of one or more instructions and a second delay value for a second set of one or more instructions; and
a processing unit configured to delay execution of the first set of one or more instructions based on the first delay and delay execution of the second set of one or more instructions based on the second delay.
The processing apparatus of claim 18 , wherein the processing unit is further configured to associate individual ones of the delay values with the corresponding set of one or more instructions.
The processing apparatus of claim 19 , wherein the processing unit is configured to associate individual ones of the delay values with the corresponding set of one or more instructions by tagging each set of one or more instructions with the corresponding delay value.
The processing apparatus of claim 18 , wherein the delay determination unit is configured to determine the delay values during at least one of code compile time, code load time, and code run time.
The processing apparatus of claim 18 , wherein the delay determination unit is configured to determine the delay values based on an application associated with the corresponding set of one or more instructions.
The processing apparatus of claim 22 , wherein the delay determination unit is configured to determine the delay values based on processor resources available to the corresponding application.
The processing apparatus of claim 18 , wherein the delay determination unit is configured to determine the delay values based on processor resources available to a corresponding application.
The processing apparatus of claim 18 , wherein the delay determination unit is configured to determine the delay values by maintaining a history of speculative instruction execution and determining the delay values based on the history of speculative instruction execution.
The processing apparatus of claim 25 , wherein the delay determination unit is configured to maintain a history of speculative instruction execution by tracking occurrences of execution pipeline flushes.
The processing apparatus of claim 18 , wherein the delay values indicate at least one of full-speculative instruction execution, non-speculative instruction execution, full-speculative instruction execution after a number of instruction processing delay cycles, and partially-speculative instruction execution.
The processing apparatus of claim 27 , wherein partially-speculative instruction execution comprises halting execution of each instruction at a specified stage until the corresponding instruction is committed.
The processing apparatus of claim 18 , wherein the delay determination unit is configured to determine the delay values by processing individual ones of the sets of one or more instructions to ascertain the corresponding delay value and directing storage of the values in a register.
The processing apparatus of claim 29 , wherein the processing unit is configured to delay execution of individual ones of the sets of one or more instructions based on the corresponding delay value by retrieving the delay values from the register, delaying execution of individual ones of the sets of one or more instructions based on the corresponding retrieved delay value and directing storage of results of executing the sets of instructions.
The processing apparatus of claim 30 , wherein the processing unit is configured to direct storage of results of executing the sets of instructions by temporarily storing results of uncommitted instructions associated with one or more of the sets of instructions.
The processing apparatus of claim 31 , wherein the processing unit is further configured to update the architected state with the results associated with at least one of the sets of one or more instructions that are committed.
The processing apparatus of claim 31 , wherein the processing unit is further configured to clear the results associated with uncommitted instructions in response to an execution pipeline flush condition.
The processing apparatus of claim 33 , wherein the execution pipeline flush condition corresponds to at least one of a branch misprediction error, an exception, a trap, an interrupt, and a fault.
A method of imposing instruction execution delay in a coprocessor, comprising: delaying execution of incoming instructions according to a delay value received from an associated processor; and changing an amount of delay imposed on subsequent incoming instructions responsive to receiving a new delay value from the associated processor.
delaying execution of incoming instructions according to a delay value received from an associated processor; and
changing an amount of delay imposed on subsequent incoming instructions responsive to receiving a new delay value from the associated processor.
A computer program product for altering instruction execution delay in a processor, comprising: program code for determining a first delay value for a first set of one or more instructions and a second delay value for a second set of one or more instructions based on one or more applications executed by the processor; and program code for providing the delay values to the processor.
program code for determining a first delay value for a first set of one or more instructions and a second delay value for a second set of one or more instructions based on one or more applications executed by the processor; and
program code for providing the delay values to the processor.
Ref US20080288819A1: Claims:
A method for use for transaction processing on a computing system for managing memory access to a shared transactional memory location for transaction data of a first thread, the method comprising the steps of: decoding marking code for a string of instructions for execution on a processor of said computing system and determining whether said marking code marks the beginning of an active atomic instruction group (AIG) of instructions associated with a transaction of a thread, (the marks are made by insertion in the code explicitly by programmers in a high level language, added by compliers or translators as implementations of high level locking functions, added by a library call, included by a special even at runtime) (The instructions or marks may be generated by firmware, hardware or a combination of both as a response to decoding a particular sequence of instructions or receiving a special command to enter a new mode of execution.) when it is determined that the marking code marks the beginning of an active instruction group (AIG) of instructions associated with a transaction of a thread, said processor enters a millicode mode an
[Truncated to input limit]