class LeChiffreConfig extends Config(new WithLeChiffre ++ new DefaultConfig)


|${fields.map(a => s"${a.serialize(tab + "  ")}").mkString("\n")}"""


case class ScanFieldBindingException(msg: String) extends Exception(msg)


case class Cycle(width: Int) extends ScanField


case class Difficulty(width: Int) extends ScanField with ProbabilityBind


class StuckAtInjectorWithId(bitWidth: Int, val scanId: String) extends StuckAtInjector(bitWidth) with ChiffreInjector


|${injectors.map{ case (k, v) => s"${tab}  ${v.name}, ${k.module.name}, ${slaveIn(k).module.name}.${slaveIn(k).name}, ${slaveOut(k).module.name}.${slaveOut(k).name}"}.mkString("\n")}


  behavior of "Chiffree Injectee annotation"

  it should "emit an annotation" in {
    val circuit = ChiselStage.elaborate(new DummyInjectee)


Driver(() => new StuckAtInjector(8)) { dut => new StuckAtTester(dut) }


                                 |<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN"
                                 | "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">


private def onMod(mod:   DefModule): DefModule = mod.map(onStmt)


  def render: String = {
    s"""$absoluteName [shape="circle" style="filled" BGCOLOR="#C0C0C0" label="$value"]
     """.stripMargin
  }


override val absoluteName: String = s"op_${name}_${PrimOpNode.hash}"


  val targets: Seq[PhaseManager.PhaseDependency] = Seq(
    Dependency[CheckPhase],
    Dependency[GetFirrtlCircuitPhase],


override def prerequisites = Seq(Dependency[OptionallyBuildTargetDirPhase])


throw new DiagrammerException(s"Error: Target dir ${targetDir} exists and is not a directory")


override def optionalPrerequisites = Seq.empty


            val result = Some(Block(block.stmts.flatMap { substatement =>
              removeGenStatement(substatement)
            }))


) ++ (if (showPrintfs) { Seq(ShowPrintfsAnnotation) }


    }
    is (PE_states('e_PE_ACTIVATION_FUNCTION)) {
      reqAf()


  // the number of expected writes.
  assert(!Vec((0 until transactionTableNumEntries * 2).map(
    i => (state(i).valid &&


  def apply(epb: Int, pes: Int, cache: Int): Int = {
    var x = epb << (6 + 4);
    x = x | pes << 4;
    x = x | cache;
    x}


abstract class XFilesTests(implicit p: Parameters) extends XFilesTester {
  // New Transaction


override def cloneType = new QueueIOAf(gen, entries).asInstanceOf[this.type]


when (io.we(i))                    { mem(io.addr(i))  := io.din(i)        }


def index(j: Int): (Int, Int) = (elementWidth*(j+1) - 1, elementWidth * j)


  override def cloneType = new SRAMElementCounterResp (
    sramDepth = sramDepth).asInstanceOf[this.type]


  val id_pc       = Output(UInt(WLEN.W))
  val id_pc_4     = Output(UInt(WLEN.W))


object InstCache extends App {
  chisel3.Driver.execute(args, () => new InstCache)
}


object PC extends App {
  chisel3.Driver.execute(args, () => new PC)
}


  iotesters.Driver.execute((Array("--is-verbose")), () => new ALU) {
    c => new ALU_Test(c)
  }


    poke(c.io.addr_input, addr)
    poke(c.io.record, record)
    peek(c.io.front)


  iotesters.Driver.execute(Array("--backend-name", "verilator"), () => new Datapath) {
    c => new Datapath_Test(c)
  }


  iotesters.Driver.execute(Array("--backend-name", "-verilator"), () => new ID_EX_Register) {
    c => new ID_EX_Register_Test(c)
  }


  iotesters.Driver.execute(Array("--is-verbose"), () => new ImmGen) {
    c => new ImmGen_Test(c)
  }


  iotesters.Driver.execute(Array("--is-verbose"), () => new Tile){
    c => new Tile_Test(c)
  }


def apply(Pipelined: Boolean = false): InvMixColumns = Module(new InvMixColumns(Pipelined))


def apply(Pipelined: Boolean = false): MixColumns = Module(new MixColumns(Pipelined))


    if (backendNames.contains("verilator")) {
      iotesters.Driver.execute(


          "--backend-name", "firrtl", "--generate-vcd-output", "on"), () => new ShiftRows) {
        c => new ShiftRowsUnitTester(c)
      } should be(true)


object GCDRepl extends App {
  iotesters.Driver.executeFirrtlRepl(args, () => new GCD)
}


      iotesters.Driver.execute(
        Array("--target-dir", "test_run_dir/" + dir + "_firrtl_test", "--top-name", dir,
          "--backend-name", "firrtl", "--generate-vcd-output", "on"), () => new LFSR) {


val csr_set_x = withClock(io.active_clk){RegNext(csr_set_d, init=0.B)}


class dec_ib_ctl_IO extends Bundle with param{
  val ifu_ib = Flipped(new aln_ib)
  val ib_exu = Flipped(new ib_exu)
  val dbg_ib = new dbg_ib


def pattern(y : List[Int]) = (0 until y.size).map(i=> if(y(i)>=0 & y(i)!='z') io.dec_csr_rdaddr_d(y(i)) else if(y(i)<0) !io.dec_csr_rdaddr_d(y(i).abs) else !io.dec_csr_rdaddr_d(0)).reduce(_&_)


fifo_error_bus   := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_error_bus_en(i), 1.U, fifo_error_bus(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))


    val reg_wr_addr    = Output(UInt(7.W))
    val reg_en         = Output(UInt(1.W))
    val reg_wr_en      = Output(UInt(1.W))


    val		exu_div_wren			    = Output(UInt(1.W))                          // Divide write enable to GPR
    //debug


val pat_b = (0 until y.size).map(i=> if(y(i)>=0) m_ff(y(i)) else !m_ff(y(i).abs)).reduce(_&_)


dec_tlu_force_halt_bus_q := withClock(io.free_clk) {RegNext(dec_tlu_force_halt_bus_ns, 0.U)}


withClock(io.lsu_stbuf_c1_clk){ RdPtr := RegEnable(NxtRdPtr, 0.U, RdPtrEn)}


        case _ => {
            exportVerilog(() => new nagicore.loongarch.nscscc2024.Core)
        }


    if(GlobalConfg.SIM){
        import nagicore.unit.DPIC_PERF_PIPE
        val perf_pipe_if = Module(new DPIC_PERF_PIPE())
        perf_pipe_if.io.clk := clock
        perf_pipe_if.io.rst := reset


    val wordData = if(XLEN == 64) Mux(addr(2), rdata_raw(63, 32), rdata_raw(31, 0))
                    else rdata_raw(31, 0)


    val is2 = issue_buffer.io.rdatas(1)
    val data_hazard = (is1.rc === is2.ra || is1.rc === is2.rb) && is1.rc =/= 0.U
    // 只双发is2是ALU类，且无数据冒险的指令
    val issue_double =
        Flags.is(is2.instr_type, CtrlFlags.InstrType.alu) &&


        case DIVU_IMP.radix2 => {
            /* ref: https://github.com/MaZirui2001/LAdataBitsR-pipeline-scala */


    val wen     = Input(Vec(wchannel, Bool()))
    val waddr   = Input(Vec(wchannel, UInt(addrBits.W)))


    val rdatas = RegEnable(VecInit.tabulate(ways){ i =>
            VecInit.tabulate(num_word){ j =>
                data_bank_io(i)(j).dout
            }
        }, pipego_reg)


val addr_word_reg = if(len_word!=0) addr_reg(len_word+len_byte-1, len_byte) else 0.U


slaveFn = { s => s.copy(payloadBits=srcBits) }


(Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n")


val arFIFOMap = WireInit(VecInit(Seq.fill(endId) { true.B }))


def getNodesOut(ls: Seq[String]): Seq[Option[Int]] = getNodes(ls, outNodeMapping)


val states = Reg(MixedVec(cParam.virtualChannelParams.map { u => new OutputState(u.bufferSize) }))


val in_alloc = Wire(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))


override def getNPrios(src: ChannelRoutingInfo): Int = maxVCs


} .getOrElse { TLAtomicAutomata(arithmetic = pa.arithmetic) })


      val wrap = (value === (n-1).U)
      Mux(wrap, 0.U, value + 1.U)
    }


    (new ArgsParser).getConfig(args.toSeq) match {
      case Some(config) => generate(config)
      case None =>
    }


case Addw => s"${emitExprWrap(p.args(0))}.addw(${emitExprWrap(p.args(1))})"


def serialize: String = s"if (${wrEn.serialize} && ${wrMask.serialize}) $memName[${wrAddr.serialize}] = ${wrData.serialize}"


  def apply(g: Graph, excludeSet: Set[NodeID] = Set()): ArrayBuffer[NodeID] = {
    val worker = new MFFC(g)
    excludeSet foreach { id => worker.mffc(id) = Excluded }
    val mffc = worker.findMFFCs()


def stmtsOrdered(): Seq[Statement] = collectValidStmts(TopologicalSort(this).toSeq)


          val eName = primE.args.head match { case w: WRef => w.name }
          if ((addSigs.contains(eName)) && (primE.consts.head == 1) && (bitWidth(primE.tpe) == 64))
            Seq((tName, eName))
          else Seq()
        }


val portNames = (m.ports map { _.name }).toSet


  def run(c: Circuit): Circuit = {
    val modulesx = c.modules.map {
      case m: ExtModule => m
      case m: Module => simpBitsModule(m)
    }


val memsWithWrites = memsToReplace filter { _.writers.nonEmpty }


     val resultState = firrtlCompiler.execute(CircuitState(circuit, Seq()))
     val CorrectReader = Source.fromURL(getClass.getResource("/ReplacedRsvdKey_correct.fir"))
     val correctString = CorrectReader.getLines().mkString("\n")
     assert(correctString == resultState.circuit.serialize)


      instSLTU  -> Mux(io.src1.asUInt < io.src2.asUInt, 1.U(XLen.W), 0.U(XLen.W)),
      instSLTIU -> Mux(io.src1.asUInt < io.imm.asUInt, 1.U(XLen.W), 0.U(XLen.W)),
      instSLL   -> (io.src1 << io.src2(5, 0))(63, 0),
      instSRL   -> (io.src1 >> io.src2(5, 0)),


  protected val imm       = exReg.imm
  protected val wen       = exReg.wen
  protected val rs1       = exReg.inst(19, 15)


    } else {
      val done = RegNext(Mux(io.flush, false.B, en), false.B)
      val bits = RegEnable(data, en)
      generatePipe(done, bits, latency - 1)
    }


class CacheReqIO extends Bundle with InstConfig {
  val addr = UInt(XLen.W)
  val data = UInt(XLen.W) // for write
  val mask = UInt((XLen / 8).W) // for write
}


  val taken  = Output(Bool()) // is prev branch taken
  val idx    = Output(UInt(GHRLen.W)) // prev idx of PHT(GHRLen)


  val globalEn = Output(Bool())
  val fetch    = Flipped(new IFIO)
  val ld       = Flipped(new LDIO)
  val sd       = Flipped(new SDIO)
}


class IFIO extends Bundle with IOConfig {
  val en   = Output(Bool())
  val addr = Output(UInt(XLen.W))
  val data = Input(UInt(InstLen.W))
}


  val addr = Output(UInt(XLen.W))
  val data = Output(UInt(XLen.W))


class WBDATAIO extends Bundle with IOConfig {
  val wen   = Output(Bool())
  val wdest = Output(UInt(RegfileLen.W))
  val data  = Output(UInt(XLen.W))
}


def less(src1: UInt, src2: UInt, sign: Bool): Bool = Mux(sign, src1.asSInt < src2.asSInt, src1 < src2)


//split vs2Data into SEW width vectors
    for(i <- 0 until E8Depth)    io.vs2e.e8(i)      := io.vs2Data(8*(i+1)-1, 8*i)
    for(i <- 0 until E16Depth)   io.vs2e.e16(i)     := io.vs2Data(16*(i+1)-1, 16*i)
    for(i <- 0 until E32Depth)   io.vs2e.e32(i)     := io.vs2Data(32*(i+1)-1, 32*i)


def op_is(ops: UInt*) = ops.toList.map(x => {op === x}).reduceLeft(_ || _)


  for(i <- 0 until f16Depth) {
    io.vFSgnJOut.f16(i) := MuxCase(Cat(io.vsrc1f.f16(i)(16), io.vsrc2f.f16(i)(15,0)),
                            Array((io.fsgnjFun === FSgnJFun_Not) -> Cat(~io.vsrc1f.f16(i)(16), io.vsrc2f.f16(i)(15,0)),
                                  (io.fsgnjFun === FSgnJFun_Xor) -> Cat(io.vsrc1f.f16(i)(16) ^ io.vsrc2f.f16(i)(16), io.vsrc2f.f16(i)(15,0))))
  }


def F64ToS1: UInt = FType.S.recode(Mux(io.fromXData1(63,32).andR, io.fromXData1(31,0), qNaN32))


override def cloneType = new VPUFPUResponse(FLEN).asInstanceOf[this.type]


object VPUVerilog extends App with CustomConfig {
  chisel3.Driver.execute(args, () => new VPU_64V64E1L(customConfig, tagBits, addrBits))
}


def VLXH_V (vde: String,  rs1: String = rs1, vs2e: String = vs2e, vm: String = "1") = ("000"+"111"+vm+vs2e   +rs1+"101"+vde+"0000111", "VLXH_V     ")


    when ( io.fnct3 === 0.U ) {
        io.br_taken :=  io.arg_x === io.arg_y        // Branch taken if arg_x is equal to arg_y
    }.elsewhen ( io.fnct3 === 1.U ) {


class LM_IO_Interface_ImmdValGen extends Bundle {
  val instr = Input(UInt(32.W))    // 32-bit instruction input
  val pc_in = Input(SInt(32.W))    // 32-bit signed program counter input
  val immd_se = Output(UInt(32.W)) // 32-bit signed immediate output
}


        val output = Output(SInt(4.W))
    })


            test(new Adder(32)){c=>
            c.io.in_0.poke(12.U)
            c.io.in_1.poke(4.U)
        c.clock.step(100)}


            c.clock.step(5)

            // Expect that the output bits should be 4.


       test(new OneShotTimerModule()){c =>
         c.clock.step(10)
      }


       test(new BranchControl()){c =>
         c.io.fnct3.poke(1.U)              // Set input signals for the BranchControl module
         c.io.branch.poke(1.B)
         c.io.arg_x.poke(1.U)
         c.io.arg_y.poke(0.U)


if (bytes(bytes.length - 1).length < 4) bytes(bytes.length - 1) = Array(0, 0, 0, 0)


case None => throw CRVException(s"Something went wrong in the distribution selection of ${_var.toString}")


    override def disable(): Unit = {
      crvc.disable()
    }


def >(that: Event): Bool = superCycle > that.superCycle || (superCycle === that.superCycle) && cycle > that.cycle


case class PriorityQueueParameters(size: Int, order: Int, superCycleWidth: Int, cycleWidth: Int, referenceIdWidth: Int)


val candidates = Seq.tabulate(values.length)(i => if (cyclicMins.contains(i)) normals(i) else Int.MaxValue)


val tnumber = if(IsUnitTest) { 10 } else { 5000 }


chisel3.iotesters.Driver(() => new AXI4StreamTimeAdapaterTestModule) { new AXI4StreamTimeAdapterTester(_) } should be (true)


    def unsignedBigInt(i: BigInt): BigInt = if (i < 0) {
      (BigInt(2) << proto.getWidth) + i
    } else {


if (w) g else Seq.fill(g.length)(false) })


    adjustableShiftRegister.io.deq.ready := adjustableShiftRegister.io.count >= depth && en

    Mux(adjustableShiftRegister.io.deq.fire(), adjustableShiftRegister.io.deq.bits, resetData)


val delays = (1 to nStages).map { n >> _ }


    when (count + 1.U === size.U) {
      nextCount := 0.U
    }


def apply[V](in: Seq[V], func: (V, V) => V): V = {


    it should s"work for n = $i" in {
      ShifterTester(i) should be (true)
    }


if (cyclesWaiting >= maxCyclesWait) { expect(false, "waited for input too long") }


def apply()(implicit p: Parameters) = new AXI4ChannelAW(new AXI4BundleAW)


throw new IllegalArgumentException(s"unsupported CHI data width: ${width}")


abstract class AbstractCHILinkActiveManager extends Module


s"max maximum link credit count is ${CHI_MAX_REASONABLE_LINK_CREDIT_COUNT}, but ${paramMaxCount} configured")


class AddressableReadWritePort(val addressWidth: Int, val dataWidth: Int) extends Bundle {

    // Write Port
    val w   = new AddressableWritePort(addressWidth, dataWidth)


    // Write Port
    val en      = Input(Bool())
    val addr    = Input(UInt(addressWidth.W))
    val data    = Input(UInt(dataWidth.W))


def BVec(n: Int): Vec[Bool] = Vec(n, boolean.B)


s"[debug] Registering instance ${i.name} of ${i.module} for AsyncReset Propagation"


      case _ =>
        trace(e, s"Cannot convert expression ${e.serialize} to Literal")
        None
    }


            case (UnknownFlow, SinkFlow) =>
              wasInferredSink += (r.serialize)
              debug(e, s" > Recording that ${r.serialize} was used as sink")


      |wire              post_out_b;
      |
      |assign post_out_u1 = inst_out_u1;
      |assign post_out_u2 = inst_out_u2;
      |assign post_out_u3 = inst_out_u3;


      """.stripMargin
    )
    debug(result)
    result should containStr ("class Test() extends RawModule {")
    result should containStr ("val lhsc = Wire(Vec(32, Bool()))")


    result should containStr ("val TRUC = 32")
    result should containStr ("val CALC = TRUC")


  it should "properly remove concats or use Cat" in {
    val result = emitInModule(s"""
      |// might containStr more than the RAM due to moves


class FpuReq()(implicit p: Parameters) extends BoomBundle


class BrResolutionInfo(implicit p: Parameters) extends BoomBundle


class FpPipeline(implicit p: Parameters) extends BoomModule with tile.HasFPUParameters


if (!float) io.map_resps(i).prs3 := DontCare


class BIMMeta(implicit p: Parameters) extends BoomBundle()(p)


when (reset_idx === (nSets-1).U) { doing_reset := false.B }


  addResource("/vsrc/predictor_harness.v")
  addResource("/csrc/predictor_sw.cc")
}


val com_map_table = RegInit(VecInit((0 until numLregs) map { i => i.U(pregSz.W) }))


override val desiredName = s"Parallel_${decodeWidth}_f${favor}_FindOne"


  io.leds(1) :=   io.switches(0) & io.switches(1)   // AND
  io.leds(2) :=   io.switches(0) | io.switches(1)   // OR
  io.leds(3) := ~(io.switches(0) & io.switches(1))  // NAND


  // Inequality operator is "=/=".
  io.not_5 := io.a =/= 5.U


object LeftShifter extends App {
  chisel3.Driver.execute(args, () => new LeftShifter)
}


    mux2.io.selector := selector
    mux2.io.in_0 := in_0
    mux2.io.in_1 := in_1
    mux2.io.out


val fullAdders = VecInit(Seq.fill(n){ Module(new FullAdder).io })


object SRLatch extends App {
  chisel3.Driver.execute(args, () => new SRLatch)
}


    val set = Input(Bool())
    val reset = Input(Bool())


  val cathodes = Output(UInt(7.W))
  /** For decimal point. It lights when it is 0, and goes out when it is 1.  */


      when (io.charData.valid) {
        state := sRomRead
        yInChar := 0.U
      }


        } .otherwise {
          sendCount := sendCount + 1.U
        }


io.leds(6) := ~(io.switches(0) ^ io.switches(1))  // NXOR


object Mux4 extends App {
  chisel3.Driver.execute(args, () => new Mux4())
}


object FullAdder extends App {
  chisel3.Driver.execute(args, () => new FullAdder)
}


val fullAdders = VecInit(Seq.fill(4){ Module(new FullAdder).io }) // [注意]ioを渡している


  mux1.io.in_0 := io.in(1)
  mux1.io.in_1 := io.in(0)


val adderLsbs = Cat(for (i <- (n - 2) to 0 by -1) yield { adders(i).sum(0) })


object DLatch extends App {
  chisel3.Driver.execute(args, () => new DLatch)
}


object Stopwatch extends App {
  chisel3.Driver.execute(args, () => new Stopwatch)
}


    val rxData = Input(Bool())
    val txData = Output(Bool())
    val rts = Output(Bool())
    val cts = Input(Bool())


    val d = Input(Bool())
    val pulse = Output(Bool())


val in1 = Flipped(Decoupled(UInt(8.W))) //ready-> output , valid->input


    when(io.mask(3)){
         data(3):=io.dataIn(3)
    }.otherwise{


    when(io.sel===0.U){
        io.x:=io.a + io.b
    }.elsewhen(io.sel===1.U){


        test(new resetcounter(5)){c=>
        c.clock.step(20)
        c.io.result.expect(0.B)

        }


class mux2test  extends FreeSpec with ChiselScalatestTester {


    "ALU Test" in {
        test(new ALU()){c=>
        c.io.in_A.poke(4.U)
        c.io.in_B.poke(5.U)
        c.io.alu_Op.poke(4.U)


        test(new Adder5(32)){c=>
        c.io.in0.poke(2.U)
        c.io.in1.poke(2.U)


    "NAND Gate Test" in {
        test(new NAND()){c=>
        c.io.a.poke(8.S)
        c.io.b.poke(15.S)


        c.io.b.poke(-15.S)
        c.io.c.poke(2.S)
        c.clock.step(1)
        c.io.sum.expect(-5.S)
        c.io.cout.expect(0.S)


        test(new halfadder()){c=>
        c.io.a.poke(8.S)


case object ClockTapKey extends Field[Boolean](true)


class MegaBoomV4Config extends Config(
  new boom.v4.common.WithNMegaBooms(1) ++                           // mega boom config
  new chipyard.config.WithSystemBusWidth(128) ++
  new chipyard.config.AbstractConfig)


case object MultiRoCCKey extends Field[Map[Int, Seq[Parameters => LazyRoCC]]](Map.empty[Int, Seq[Parameters => LazyRoCC]])


  class Impl extends LazyRawModuleImp(this) with DontTouch {
    // Your custom non-rocketchip-soc stuff here
  }


override def parent = Some(ResourceAnchors.cpus)


    override def describe(resources: ResourceBindings): Description = {
      val Description(name, mapping) = super.describe(resources)
      Description(name, mapping)
    }


case object HarnessBinderClockFrequencyKey extends Field[Double](100.0) // MHz


class UnitTestSuite(implicit p: Parameters) extends freechips.rocketchip.unittest.UnitTestSuite {
  ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader)
}


it should s"select a reference of ${expected} MHz for ${freqStr} MHz" in {


assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})


def castC(x: TLBundleC) = { val ret = Wire(out.c.bits); ret <> x; ret }


class IntBlockDuringReset(stretchResetCycles: Int = 0)(implicit p: Parameters) extends LazyModule


override def desiredName = s"IntXbar_i${intnode.in.size}_o${intnode.out.size}"


    val debounced = withClockAndReset(slowIn.clock, causes) {
      AsyncResetReg(incremented, 0, increment, Some("debounce"))
    }


def busView: TLEdge = xbar.node.edges.in.head


val io_axi4 = InModuleBody { node.makeIOs() }


dFn = { p => p.base.v1copy(minLatency = 1) },


class CoreMonitorBundle(val xLen: Int, val fLen: Int) extends Bundle with Clocked {
  val excpt = Bool()
  val priv_mode = UInt(width = 3.W)
  val hartid = UInt(width = xLen.W)
  val timer = UInt(width = 32.W)


    mem.suggestName(name)

    val granWidth = data match {


def inPrevState(s: BigInt): ir.Expression = Utils.eq(prevState, ir.UIntLiteral(s, ir.IntWidth(regWidth)))


val windowsfFile = s"${fFile.toString()}.win"


if (JNAUtils.isWindows) { "verilator_bin" }


def detail = s"(up: $upPeriod, down: $downPeriod)"


class PlusArgReaderWrapper(expected: Int) extends Module {
  val reader = Module(new PlusArgReader)
  val msg = s"Expected $expected, got %x.\n" // this works around the fact that s".." is forbidden in the assert
  assert(reader.io.out === expected.U, msg, reader.io.out)
}


io.enq.ready := emptyBits.reduce { _ || _ } // any empties?


    } else {
      computeGcdResultsAndCycles(b, a % b, depth + 1)
    }


    "should work with Treadle" in {
      test(new SecondClock).runPeekPoke(new SecondClockTester(_))
    }


private def testDirFiles(): Seq[os.Path] = os.list(targetDir).filter(os.isFile)


  def execute(args: Array[String], mod: => chisel3.RawModule, firtoolOpts: Array[String]) = {
    val annotations = firtoolOpts.map(FirtoolOption.apply).toSeq

    (new XiangShanStage).execute(args, ChiselGeneratorAnnotation(() => mod) +: annotations)
  }


XSDebug(func === ALUOpType.lui32addw, p"[alu] func lui32w: add_src1=${Hexadecimal(addModule.io.srcw)} add_src2=${Hexadecimal(addModule.io.src(1)(31,0))} addres=${Hexadecimal(addw)}\n")


object CSRField55Bits extends CSREnum with CSRMacroApply


  val redirectValid = io.out.bits.res.redirect.get.valid
  redirectValid := io.in.valid && !jumpDataModule.io.isAuipc
  redirect := 0.U.asTypeOf(redirect)
  redirect.level := RedirectLevel.flushAfter


s"writePorts: ${backendParams.getIntExuRCWriteSize} + ${backendParams.getMemExuRCWriteSize}")


    when (io.lsu.resp.fire) {
      state := s_invalid
    }


VecInit((0 until size / freeWidth).map(i => { input(freeWidth * i + rem) })).asUInt


val l1_stride_ratio_const = Constantin.createRecord(s"l1_stride_ratio${p(XSCoreParamsKey).HartId}", initValue = 2)