OpenRaiser/Intern-Atlas huggingface dataset:
Numerical removal of water-vapor effects from THz-TDS measurements
Venue: arXiv cs.CE 2007
Year: 2007

One source of disturbance in a pulsed T-ray signal is attributed to ambient water vapor. Water molecules in the gas phase selectively absorb T-rays at discrete frequencies corresponding to their molecular rotational transitions. This results in prominent resonances spread over the T-ray spectrum, and in the time domain the T-ray signal is observed as fluctuations after the main pulse. These effects are generally undesired, since they may mask critical spectroscopic data. So, ambient water vapor is commonly removed from the T-ray path by using a closed chamber during the measurement. Yet, in some applications a closed chamber is not applicable. This situation, therefore, motivates the need for another method to reduce these unwanted artifacts. This paper presents a study on a computational means to address the problem. Initially, a complex frequency response of water vapor is modeled from a spectroscopic catalog. Using a deconvolution technique, together with fine tuning of the strength of each resonance, parts of the water-vapor response are removed from a measured T-ray signal, with minimal signal distortion.
Testing D-Sequences for their Randomness
Venue: arXiv cs.CR 2007
Year: 2007

This paper examines the randomness of d-sequences, which are decimal sequences to an arbitrary base. Our motivation is to check their suitability for application to cryptography, spread-spectrum systems and use as pseudorandom sequence.
Frequency Analysis of Decoupling Capacitors for Three Voltage Supplies in SoC
Venue: arXiv cs.AR 2007
Year: 2007

Reduction in power consumption has become a major criterion of design in modern ICs. One such scheme to reduce power consumption by an IC is the use of multiple power supplies for critical and non-critical paths. To maintain the impedance of a power distribution system below a specified level, multiple decoupling capacitors are placed at different levels of power grid hierarchy. This paper describes about three-voltage supply power distribution systems. The noise at one power supply can propagate to the other power supply, causing power and signal integrity problems in the overall system. Effects such as anti-resonance and remedies for these effects are studied. Impedance of the three-voltage supply power distribution system is calculated in terms of RLC-model of decoupling capacitors. Further the obtained impedance depends on the frequency; hence brief frequency analysis of impedance is done.
A quick search method for audio signals based on a piecewise linear representation of feature trajectories
Venue: arXiv cs.MM 2007
Year: 2007

This paper presents a new method for a quick similarity-based search through long unlabeled audio streams to detect and locate audio clips provided by users. The method involves feature-dimension reduction based on a piecewise linear representation of a sequential feature trajectory extracted from a long audio stream. Two techniques enable us to obtain a piecewise linear representation: the dynamic segmentation of feature trajectories and the segment-based Karhunen-Lóeve (KL) transform. The proposed search method guarantees the same search results as the search method without the proposed feature-dimension reduction method in principle. Experiment results indicate significant improvements in search speed. For example the proposed method reduced the total search time to approximately 1/12 that of previous methods and detected queries in approximately 0.3 seconds from a 200-hour audio database.
Analysis of a Mixed Strategy for Multiple Relay Networks
Venue: arXiv cs.IT 2007
Year: 2007

In their landmark paper Cover and El Gamal proposed different coding strategies for the relay channel with a single relay supporting a communication pair. These strategies are the decode-and-forward and compress-and-forward approach, as well as a general lower bound on the capacity of a relay network which relies on the mixed application of the previous two strategies. So far, only parts of their work - the decode-and-forward and the compress-and-forward strategy - have been applied to networks with multiple relays. This paper derives a mixed strategy for multiple relay networks using a combined approach of partial decode-and-forward with N +1 levels and the ideas of successive refinement with different side information at the receivers. After describing the protocol structure, we present the achievable rates for the discrete memoryless relay channel as well as Gaussian multiple relay networks. Using these results we compare the mixed strategy with some special cases, e. g., multilevel decode-and-forward, distributed compress-and-forward and a mixed approach where one relay node operates in decode-and-forward and the other in compress-and-forward mode.
Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip
Venue: arXiv cs.AR 2007
Year: 2007

We have presented an optimal buffer sizing and buffer insertion methodology which uses stochastic models of the architecture and Continuous Time Markov Decision Processes CTMDPs. Such a methodology is useful in managing the scarce buffer resources available on chip as compared to network based data communication which can have large buffer space. The modeling of this problem in terms of a CT-MDP framework lead to a nonlinear formulation due to usage of bridges in the bus architecture. We present a methodology to split the problem into several smaller though linear systems and we then solve these subsystems.
Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip
Venue: arXiv cs.AR 2007
Year: 2007

In this paper is proposed a technique to integrate and simulate a dynamic memory in a multiprocessor framework based on C/C++/SystemC. Using host machine's memory management capabilities, dynamic data processing is supported without compromising speed and accuracy of the simulation. A first prototype in a shared memory context is presented.
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction
Venue: arXiv cs.AR 2007
Year: 2007

Assessing IC manufacturing process fluctuations and their impacts on IC interconnect performance has become unavoidable for modern DSM designs. However, the construction of parametric interconnect models is often hampered by the rapid increase in computational cost and model complexity. In this paper we present an efficient yet accurate parametric model order reduction algorithm for addressing the variability of IC interconnect performance. The efficiency of the approach lies in a novel combination of low-rank matrix approximation and multi-parameter moment matching. The complexity of the proposed parametric model order reduction is as low as that of a standard Krylov subspace method when applied to a nominal system. Under the projection-based framework, our algorithm also preserves the passivity of the resulting parametric models.
A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck
Venue: arXiv cs.AR 2007
Year: 2007

The memory subsystem has always been a bottleneck in performance as well as significant power contributor in memory intensive applications. Many researchers have presented multi-layered memory hierarchies as a means to design energy and performance efficient systems. However, most of the previous work do not explore trade-offs systematically. We fill this gap by proposing a formalized technique that takes into consideration data reuse, limited lifetime of the arrays of an application and application specific prefetching opportunities, and performs a thorough trade-off exploration for different memory layer sizes. This technique has been implemented on a prototype tool, which was tested successfully using nine real-life applications of industrial relevance. Following this approach we have able to reduce execution time up to 60%, and energy consumption up to 70%.
Compositional Memory Systems for Multimedia Communicating Tasks
Venue: arXiv cs.AR 2007
Year: 2007

Conventional cache models are not suited for real-time parallel processing because tasks may flush each other's data out of the cache in an unpredictable manner. In this way the system is not compositional so the overall performance is difficult to predict and the integration of new tasks expensive. This paper proposes a new method that imposes compositionality to the system?s performance and makes different memory hierarchy optimizations possible for multimedia communicating tasks when running on embedded multiprocessor architectures. The method is based on a cache allocation strategy that assigns sets of the unified cache exclusively to tasks and to the communication buffers. We also analytically formulate the problem and describe a method to compute the cache partitioning ratio for optimizing the throughput and the consumed power. When applied to a multiprocessor with memory hierarchy our technique delivers also performance gain. Compared to the shared cache case, for an application consisting of two jpeg decoders and one edge detection algorithm 5 times less misses are experienced and for an mpeg2 decoder 6.5 times less misses are experienced.
Bright-Field AAPSM Conflict Detection and Correction
Venue: arXiv cs.AR 2007
Year: 2007

As feature sizes shrink, it will be necessary to use AAPSM (Alternating-Aperture Phase Shift Masking) to image critical features, especially on the polysilicon layer. This imposes additional constraints on the layouts beyond traditional design rules. Of particular note is the requirement that all critical features be flanked by opposite-phase shifters, while the shifters obey minimum width and spacing requirements. A layout is called phase-assignable if it satisfies this requirement. If a layout is not phase-assignable, the phase conflicts have to removed to enable the use of AAPSM for the layout. Previous work has sought to detect a suitable set of phase Conflicts to be removed, as well as correct them. The contribution of this paper are the following: (1) a new approach to detect a minimal set of phase conflicts (also referred to as AAPSM conflicts), which when corrected will produce a phase-assignable layout; (2) a novel layout modification scheme for correcting these AAPSM conflicts. The proposed approach for conflict detection shows significant improvements in the quality of results and runtime for real industrial circuits, when compared to previous methods. To the best of our knowledge, this is the first time layout modification results are presented for bright-field AAPSM. Our experiments show that the percentage area increase for making a layout phase-assignable ranges from 0.7-11.8%.
New Perspectives and Opportunities From the Wild West of Microelectronic Biochips
Venue: arXiv cs.AR 2007
Year: 2007

Application of Microelectronic to bioanalysis is an emerging field which holds great promise. From the standpoint of electronic and system design, biochips imply a radical change of perspective, since new, completely different constraints emerge while other usual constraints can be relaxed. While electronic parts of the system can rely on the usual established design-flow, fluidic and packaging design, calls for a new approach which relies significantly on experiments. We hereby make some general considerations based on our experience in the development of biochips for cell analysis.
Evolutionary Optimization in Code-Based Test Compression
Venue: arXiv cs.AR 2007
Year: 2007

We provide a general formulation for the code-based test compression problem with fixed-length input blocks and propose a solution approach based on Evolutionary Algorithms. In contrast to existing code-based methods, we allow unspecified values in matching vectors, which allows encoding of arbitrary test sets using a relatively small number of code-words. Experimental results for both stuck-at and path delay fault test sets for ISCAS circuits demonstrate an improvement compared to existing techniques.
CMOS-Based Biosensor Arrays
Venue: arXiv cs.AR 2007
Year: 2007

CMOS-based sensor array chips provide new and attractive features as compared to today's standard tools for medical, diagnostic, and biotechnical applications. Examples for molecule- and cell-based approaches and related circuit design issues are discussed.
Reliable System Specification for Self-Checking Data-Paths
Venue: arXiv cs.AR 2007
Year: 2007

The design of reliable circuits has received a lot of attention in the past, leading to the definition of several design techniques introducing fault detection and fault tolerance properties in systems for critical applications/environments. Such design methodologies tackled the problem at different abstraction levels, from switch-level to logic, RT level, and more recently to system level. Aim of this paper is to introduce a novel system-level technique based on the redefinition of the operators functionality in the system specification. This technique provides reliability properties to the system data path, transparently with respect to the designer. Feasibility, fault coverage, performance degradation and overheads are investigated on a FIR circuit.
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Venue: arXiv cs.AR 2007
Year: 2007

Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and consider parameters like test time, index time, abort-on-fail, and contact yield. Conventional multi-site testing requires sufficient ATE resources, such as ATE channels, to allow to test multiple SOCs in parallel. In this paper, we design and optimize on-chip DfT, in order to maximize the test throughput for a given SOC and ATE. The on-chip DfT consists of an E-RPCT wrapper, and, for modular SOCs, module wrappers and TAMs. We present experimental results for a Philips SOC and several ITC'02 SOC Test Benchmarks.
A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures
Venue: arXiv cs.PL 2007
Year: 2007

The aggressive application of scalar replacement to array references substantially reduces the number of memory operations at the expense of a possibly very large number of registers. In this paper we describe a register allocation algorithm that assigns registers to scalar replaced array references along the critical paths of a computation, in many cases exploiting the opportunity for concurrent memory accesses. Experimental results, for a set of image/signal processing code kernels, reveal that the proposed algorithm leads to a substantial reduction of the number of execution cycles for the corresponding hardware implementation on a contemporary Field-Programmable-Gate-Array (FPGA) when compared to other greedy allocation algorithms, in some cases, using even fewer number of registers.
Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach
Venue: arXiv cs.AR 2007
Year: 2007

In this paper, we present a methodology for customized communication architecture synthesis that matches the communication requirements of the target application. This is an important problem, particularly for network-based implementations of complex applications. Our approach is based on using frequently encountered generic communication primitives as an alphabet capable of characterizing any given communication pattern. The proposed algorithm searches through the entire design space for a solution that minimizes the system total energy consumption, while satisfying the other design constraints. Compared to the standard mesh architecture, the customized architecture generated by the newly proposed approach shows about 36% throughput increase and 51% reduction in the energy required to encrypt 128 bits of data with a standard encryption algorithm.
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?
Venue: arXiv cs.AR 2007
Year: 2007

This special session adresses the problems that designers face when implementing analog and digital circuits in nanometer technologies. An introductory embedded tutorial will give an overview of the design problems at hand : the leakage power and process variability and their implications for digital circuits and memories, and the reducing supply voltages, the design productivity and signal integrity problems for embedded analog blocks. Next, a panel of experts from both industrial semiconductor houses and design companies, EDA vendors and research institutes will present and discuss with the audience their opinions on whether the design road ends at marker "65nm" or not.
HEBS: Histogram Equalization for Backlight Scaling
Venue: arXiv cs.OH 2007
Year: 2007

In this paper, a method is proposed for finding a pixel transformation function that maximizes backlight dimming while maintaining a pre-specified image distortion level for a liquid crystal display. This is achieved by finding a pixel transformation function, which maps the original image histogram to a new histogram with lower dynamic range. Next the contrast of the transformed image is enhanced so as to compensate for brightness loss that would arise from backlight dimming. The proposed approach relies on an accurate definition of the image distortion which takes into account both the pixel value differences and a model of the human visual system and is amenable to highly efficient hardware realization. Experimental results show that the histogram equalization for backlight scaling method results in about 45% power saving with an effective distortion rate of 5% and 65% power saving for a 20% distortion rate. This is significantly higher power savings compared to previously reported backlight dimming approaches.
An Accurate SER Estimation Method Based on Propagation Probability
Venue: arXiv cs.AR 2007
Year: 2007

In this paper, we present an accurate but very fast soft error rate (SER) estimation technique for digital circuits based on error propagation probability (EPP) computation. Experiments results and comparison of the results with the random simulation technique show that our proposed method is on average within 6% of the random simulation method and four to five orders of magnitude faster.
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
Venue: arXiv cs.AR 2007
Year: 2007

Nanometer circuits are becoming increasingly susceptible to soft-errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and supply/threshold voltage scaling reduces noise margins. It is becoming crucial to add soft-error tolerance estimation and optimization to the design flow to handle the increasing susceptibility. The first part of this paper presents a tool for accurate soft-error tolerance analysis of nanometer circuits (ASERTA) that can be used to estimate the soft-error tolerance of nanometer circuits consisting of millions of gates. The tolerance estimates generated by the tool match SPICE generated estimates closely while taking orders of magnitude less computation time. The second part of the paper presents a tool for soft-error tolerance optimization of nanometer circuits (SERTOPT) using the tolerance estimates generated by ASERTA. The tool finds optimal sizes, channel lengths, supply voltages and threshold voltages to be assigned to gates in a combinational circuit such that the soft-error tolerance is increased while meeting the timing constraint. Experiments on ISCAS'85 benchmark circuits showed that soft-error rate of the optimized circuit decreased by as much as 47% with marginal increase in circuit delay.
Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits
Venue: arXiv cs.NE 2007
Year: 2007

This issue discusses the fault-trajectory approach suitability for fault diagnosis on analog networks. Recent works have shown promising results concerning a method based on this concept for ATPG for diagnosing faults on analog networks. Such method relies on evolutionary techniques, where a generic algorithm (GA) is coded to generate a set of optimum frequencies capable to disclose faults.
Energy-Aware Routing for E-Textile Applications
Venue: arXiv cs.AR 2007
Year: 2007

As the scale of electronic devices shrinks, "electronic textiles" (e-textiles) will make possible a wide variety of novel applications which are currently unfeasible. Due to the wearability concerns, low-power techniques are critical for e-textile applications. In this paper, we address the issue of the energy-aware routing for e-textile platforms and propose an efficient algorithm to solve it. The platform we consider consists of dedicated components for e-textiles, including computational modules, dedicated transmission lines and thin-film batteries on fiber substrates. Furthermore, we derive an analytical upper bound for the achievable number of jobs completed over all possible routing strategies. From a practical standpoint, for the Advanced Encryption Standard (AES) cipher, the routing technique we propose achieves about fifty percent of this analytical upper bound. Moreover, compared to the non-energy-aware counterpart, our routing technique increases the number of encryption jobs completed by one order of magnitude.
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique
Venue: arXiv cs.AR 2007
Year: 2007

Complex applications implemented as Systems on Chip (SoCs) demand extensive use of system level modeling and validation. Their implementation gathers a large number of complex IP cores and advanced interconnection schemes, such as hierarchical bus architectures or networks on chip (NoCs). Modeling applications involves capturing its computation and communication characteristics. Previously proposed communication weighted models (CWM) consider only the application communication aspects. This work proposes a communication dependence and computation model (CDCM) that can simultaneously consider both aspects of an application. It presents a solution to the problem of mapping applications on regular NoCs while considering execution time and energy consumption. The use of CDCM is shown to provide estimated average reductions of 40% in execution time, and 20% in energy consumption, for current technologies.
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC
Venue: arXiv cs.OS 2007
Year: 2007

This paper presents the methodology and the modeling constructs we have developed to capture the real time aspects of RTOS simulation models in a System Level Design Language (SLDL) like SystemC. We describe these constructs and show how they are used to build a simulation model of an RTOS kernel targeting the $μ$-ITRON OS specification standard.
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL
Venue: arXiv cs.AR 2007
Year: 2007

This paper describes two research projects that develop new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially available components to keep costs low, yet achieves performance characteristics comparable to (and in some ways exceeding) more expensive ATE. A common CMOS FPGA-based logic core provides flexibility, adaptability, and communication with controlling computers while customized positive emitter-coupled logic (PECL) achieves multi-gigahertz data rates with about $\pm$25ps timing accuracy.