OpenRaiser/Intern-Atlas huggingface dataset:
A Survey on Software Engineering Practices in Brazilian Startups
Venue: arXiv cs.SE 2021
Year: 2021

Today's significant technological advancement allows early-stage software startups to build and launch innovative products quickly on the market. However, many of them die in the early years of their path due to market conditions, ignorance of customer needs, lack of resources, or focus, such as the misuse of well-established practices. The study's motivation is to analyze software engineering practices in startups from a practitioner's perspective. Our objective was to identify practices and tools the startups employ in their daily routines. We carried out an expert survey study with 140 software developers involved in software startups from different domains. The results show that startups in the initial and validation phases select practices and tools on an ad-hoc basis and based on the development team's prior knowledge. When they move into the growth phase, they recognize that they could have adopted better practices beforehand to support product scaling with a more mature team. The results also indicated that support tools are selected based on their integration with other tools and their ability to automate operational activities.
Groot: An Event-graph-based Approach for Root Cause Analysis in Industrial Settings
Venue: arXiv cs.SE 2021
Year: 2021

For large-scale distributed systems, it's crucial to efficiently diagnose the root causes of incidents to maintain high system availability. The recent development of microservice architecture brings three major challenges (i.e., operation, system scale, and monitoring complexities) to root cause analysis (RCA) in industrial settings. To tackle these challenges, in this paper, we present Groot, an event-graph-based approach for RCA. Groot constructs a real-time causality graph based on events that summarize various types of metrics, logs, and activities in the system under analysis. Moreover, to incorporate domain knowledge from site reliability engineering (SRE) engineers, Groot can be customized with user-defined events and domain-specific rules. Currently, Groot supports RCA among 5,000 real production services and is actively used by the SRE teamin a global e-commerce system serving more than 185 million active buyers per year. Over 15 months, we collect a data setcontaining labeled root causes of 952 real production incidents for evaluation. The evaluation results show that Groot is able to achieve 95% top-3 accuracy and 78% top-1 accuracy. To share our experience in deploying and adopting RCA in industrial settings, we conduct survey to show that users of Grootfindit helpful and easy to use. We also share the lessons learnedfrom deploying and adopting Grootto solve RCA problems inproduction environments.
Penalty-based Numerical Representation of Rigid Body Interactions with Applications to Simulation of Robotic Grasping
Venue: arXiv cs.RO 2021
Year: 2021

This paper presents a novel approach to numerically describe the interactions between rigid bodies, with a special focus on robotic grasping. Some of the more common approaches used to address such issues rely on satisfaction of a set of strict constraints, descriptive of the expected physical reality of such interactions in practice. However, application of constraint-based methods in a numerical setting may lead to problematic configurations in which, for instance, volumes occupied by distinct bodies may overlap. Such situations lying beyond the range of admissible configurations for constraint-based methods, their occurrence typically results in non-meaningful simulation outcomes. We propose a method which acknowledges the possibility of such occurrences while demoting their occurrence. This is pursued through the use of a penalty-based approach, and draws on notions of mechanical impedance to infer apposite reaction forces. Results of numerical simulations illustrate efficacy of the proposed approach.
Developing a Compressed Object Detection Model based on YOLOv4 for Deployment on Embedded GPU Platform of Autonomous System
Venue: arXiv cs.CV 2021
Year: 2021

Latest CNN-based object detection models are quite accurate but require a high-performance GPU to run in real-time. They still are heavy in terms of memory size and speed for an embedded system with limited memory space. Since the object detection for autonomous system is run on an embedded processor, it is preferable to compress the detection network as light as possible while preserving the detection accuracy. There are several popular lightweight detection models but their accuracy is too low for safe driving applications. Therefore, this paper proposes a new object detection model, referred as YOffleNet, which is compressed at a high ratio while minimizing the accuracy loss for real-time and safe driving application on an autonomous system. The backbone network architecture is based on YOLOv4, but we could compress the network greatly by replacing the high-calculation-load CSP DenseNet with the lighter modules of ShuffleNet. Experiments with KITTI dataset showed that the proposed YOffleNet is compressed by 4.7 times than the YOLOv4-s that could achieve as fast as 46 FPS on an embedded GPU system(NVIDIA Jetson AGX Xavier). Compared to the high compression ratio, the accuracy is reduced slightly to 85.8% mAP, that is only 2.6% lower than YOLOv4-s. Thus, the proposed network showed a high potential to be deployed on the embedded system of the autonomous system for the real-time and accurate object detection applications.
An efficient reverse-lookup table based strategy for solving the synonym and cache coherence problem in virtually indexed, virtually tagged caches
Venue: arXiv cs.AR 2021
Year: 2021

Virtually indexed and virtually tagged (VIVT) caches are an attractive option for micro-processor level-1 caches, because of their fast response time and because they are cheaper to implement than more complex caches such as virtually-indexed physical-tagged (VIPT) caches. The level-1 VIVT cache becomes even simpler to construct if it is implemented as a direct-mapped cache (VIVT-DM cache). However, VIVT and VIVT-DM caches have some drawbacks. When the number of sets in the cache is larger than the smallest page size, there is a possibility of synonyms (two or more virtual addresses mapped to the same physical address) existing in the cache. Further, maintenance of cache coherence across multiple processors requires a physical to virtual translation mechanism in the hardware. We describe a simple, efficient reverse lookup table based approach to address the synonym and the coherence problems in VIVT (both set associative and direct-mapped) caches. In particular, the proposed scheme does not disturb the critical memory access paths in a typical micro-processor, and requires a low overhead for its implementation. We have implemented and validated the scheme in the AJIT 32-bit microprocessor core (an implementation of the SPARC-V8 ISA) and the implementation uses approximately 2% of the gates and 5.3% of the memory bits in the processor core.
SSPU-Net: Self-Supervised Point Cloud Upsampling via Differentiable Rendering
Venue: arXiv cs.CV 2021
Year: 2021

Point clouds obtained from 3D sensors are usually sparse. Existing methods mainly focus on upsampling sparse point clouds in a supervised manner by using dense ground truth point clouds. In this paper, we propose a self-supervised point cloud upsampling network (SSPU-Net) to generate dense point clouds without using ground truth. To achieve this, we exploit the consistency between the input sparse point cloud and generated dense point cloud for the shapes and rendered images. Specifically, we first propose a neighbor expansion unit (NEU) to upsample the sparse point clouds, where the local geometric structures of the sparse point clouds are exploited to learn weights for point interpolation. Then, we develop a differentiable point cloud rendering unit (DRU) as an end-to-end module in our network to render the point cloud into multi-view images. Finally, we formulate a shape-consistent loss and an image-consistent loss to train the network so that the shapes of the sparse and dense point clouds are as consistent as possible. Extensive results on the CAD and scanned datasets demonstrate that our method can achieve impressive results in a self-supervised manner. Code is available at https://github.com/fpthink/SSPU-Net.
Modeling and Analysis of mMTC Traffic in 5G Base Stations
Venue: arXiv cs.NI 2021
Year: 2021

Massive Machine-Type Communications (mMTC) are one of the three types of services that should be supported by 5G networks. These are distinguished by the need to serve a large number of devices which are characterized by nonintensive traffic and low energy consumption. While the sporadic nature of the mMTC traffic does not pose an exertion to efficient network operation, multiplexing the traffic from a large number of these devices within the cell certainly does. Therefore, planning carefully the network resources for this traffic is of paramount importance. To do this, the statistics of the traffic pattern that arrives at the base station should be known. To this end, in this paper, we derive the distribution of the inter-arrival times of the traffic at the base station from a general number of mMTC users within the cell, assuming a generic distribution of the traffic pattern by individual users. We validate our results on traces. Results show that adding more mMTC users in the cell increases the variability of the traffic pattern at the base station almost linearly, which is not the case with increasing the traffic generation rates.
Elements of Differential Geometry in Lean: A Report for Mathematicians
Venue: arXiv cs.LO 2021
Year: 2021

We report on our experience formalizing differential geometry with mathlib, the Lean mathematical library. Our account is geared towards geometers with no knowledge of type theory, but eager to learn more about the formalization of mathematics and maybe curious enough to give Lean a try in the future. To this effect, we stress the possibly surprising difference between the formalization and its pen-and-paper counterpart arising from Lean's treatment of equality. Our three case studies are Lie groups, vector bundles and the Lie algebra of a Lie group.
Webots.HPC: A Parallel Robotics Simulation Pipeline for Autonomous Vehicles on High Performance Computing
Venue: arXiv cs.DC 2021
Year: 2021

In the rapidly evolving and maturing field of robotics, computer simulation has become an invaluable tool in the design process. Webots, a state-of-the-art robotics simulator, is often the software of choice for robotics research. Even so, Webots simulations are often run on personal and lab computers. For projects that would benefit from an aggregated output dataset from thousands of simulation runs, there is no standard recourse; this project sets out to mitigate this by developing a formalized parallel pipeline for running sequences of Webots simulations on powerful HPC resources. Such a pipeline would allow researchers to generate massive datasets from their simulations, opening the door for potential machine learning applications and decision tool development. We have developed a pipeline capable of running Webots simulations both headlessly and in GUI-enabled mode over an SSH X11 server, with simulation execution occurring remotely on HPC compute nodes. Additionally, simulations can be run in sequence, with a batch job being distributed across an arbitrary number of computing nodes and each node having multiple instances running in parallel. The implemented distribution and parallelization are extremely effective, with a 100\% simulation completion rate after 12 hours of runs. Overall, this pipeline is very capable and can be used to extend existing projects or serve as a platform for new robotics simulation endeavors.
On the Success Probability of Three Detectors for the Box-Constrained Integer Linear Model
Venue: arXiv cs.IT 2021
Year: 2021

This paper is concerned with detecting an integer parameter vector inside a box from a linear model that is corrupted with a noise vector following the Gaussian distribution. One of the commonly used detectors is the maximum likelihood detector, which is obtained by solving a box-constrained integer least squares problem, that is NP-hard. Two other popular detectors are the box-constrained rounding and Babai detectors due to their high efficiency of implementation. In this paper, we first present formulas for the success probabilities (the probabilities of correct detection) of these three detectors for two different situations: the integer parameter vector is deterministic and is uniformly distributed over the constraint box. Then, we give two simple examples to respectively show that the success probability of the box-constrained rounding detector can be larger than that of the box-constrained Babai detector and the latter can be larger than the success probability of the maximum likelihood detector when the parameter vector is deterministic, and prove that the success probability of the box-constrained rounding detector is always not larger than that of the box-constrained Babai detector when the parameter vector is uniformly distributed over the constraint box. Some relations between the results for the box constrained and ordinary cases are presented, and two bounds on the success probability of the maximum likelihood detector, which can easily be computed, are developed. Finally, simulation results are provided to illustrate our main theoretical findings.
BigGraphVis: Leveraging Streaming Algorithms and GPU Acceleration for Visualizing Big Graphs
Venue: arXiv cs.DC 2021
Year: 2021

Graph layouts are key to exploring massive graphs. An enormous number of nodes and edges do not allow network analysis software to produce meaningful visualization of the pervasive networks. Long computation time, memory and display limitations encircle the software's ability to explore massive graphs. This paper introduces BigGraphVis, a new parallel graph visualization method that uses GPU parallel processing and community detection algorithm to visualize graph communities. We combine parallelized streaming community detection algorithm and probabilistic data structure to leverage parallel processing of Graphics Processing Unit (GPU). To the best of our knowledge, this is the first attempt to combine the power of streaming algorithms coupled with GPU computing to tackle big graph visualization challenges. Our method extracts community information in a few passes on the edge list, and renders the community structures using the ForceAtlas2 algorithm. Our experiment with massive real-life graphs indicates that about 70 to 95 percent speedup can be achieved by visualizing graph communities, and the visualization appears to be meaningful and reliable. The biggest graph that we examined contains above 3 million nodes and 34 million edges, and the layout computation took about five minutes. We also observed that the BigGraphVis coloring strategy can be successfully applied to produce a more informative ForceAtlas2 layout.
Learning Maritime Obstacle Detection from Weak Annotations by Scaffolding
Venue: arXiv cs.CV 2021
Year: 2021

Coastal water autonomous boats rely on robust perception methods for obstacle detection and timely collision avoidance. The current state-of-the-art is based on deep segmentation networks trained on large datasets. Per-pixel ground truth labeling of such datasets, however, is labor-intensive and expensive. We observe that far less information is required for practical obstacle avoidance - the location of water edge on static obstacles like shore and approximate location and bounds of dynamic obstacles in the water is sufficient to plan a reaction. We propose a new scaffolding learning regime (SLR) that allows training obstacle detection segmentation networks only from such weak annotations, thus significantly reducing the cost of ground-truth labeling. Experiments show that maritime obstacle segmentation networks trained using SLR substantially outperform the same networks trained with dense ground truth labels. Thus accuracy is not sacrificed for labelling simplicity but is in fact improved, which is a remarkable result.
Efficient On-Chip Multicast Routing based on Dynamic Partition Merging
Venue: arXiv cs.NI 2021
Year: 2021

Networks-on-chips (NoCs) have become the mainstream communication infrastructure for chip multiprocessors (CMPs) and many-core systems. The commonly used parallel applications and emerging machine learning-based applications involve a significant amount of collective communication patterns. In CMP applications, multicast is widely used in multithreaded programs and protocols for barrier/clock synchronization and cache coherence. Multicast routing plays an important role on the system performance of a CMP. Existing partition-based multicast routing algorithms all use static destination set partition strategy which lacks the global view of path optimization. In this paper, we propose an efficient Dynamic Partition Merging (DPM)-based multicast routing algorithm. The proposed algorithm divides the multicast destination set into partitions dynamically by comparing the routing cost of different partition merging options and selecting the merged partitions with lower cost. The simulation results of synthetic traffic and PARSEC benchmark applications confirm that the proposed algorithm outperforms the existing path-based routing algorithms. The proposed algorithm is able to improve up to 23\% in average packet latency and 14\% in power consumption against the existing multipath routing algorithm when tested in PARSEC benchmark workloads.
FLASH: Fast Neural Architecture Search with Hardware Optimization
Venue: arXiv cs.CV 2021
Year: 2021

Neural architecture search (NAS) is a promising technique to design efficient and high-performance deep neural networks (DNNs). As the performance requirements of ML applications grow continuously, the hardware accelerators start playing a central role in DNN design. This trend makes NAS even more complicated and time-consuming for most real applications. This paper proposes FLASH, a very fast NAS methodology that co-optimizes the DNN accuracy and performance on a real hardware platform. As the main theoretical contribution, we first propose the NN-Degree, an analytical metric to quantify the topological characteristics of DNNs with skip connections (e.g., DenseNets, ResNets, Wide-ResNets, and MobileNets). The newly proposed NN-Degree allows us to do training-free NAS within one second and build an accuracy predictor by training as few as 25 samples out of a vast search space with more than 63 billion configurations. Second, by performing inference on the target hardware, we fine-tune and validate our analytical models to estimate the latency, area, and energy consumption of various DNN architectures while executing standard ML datasets. Third, we construct a hierarchical algorithm based on simplicial homology global optimization (SHGO) to optimize the model-architecture co-design process, while considering the area, latency, and energy consumption of the target hardware. We demonstrate that, compared to the state-of-the-art NAS approaches, our proposed hierarchical SHGO-based algorithm enables more than four orders of magnitude speedup (specifically, the execution time of the proposed algorithm is about 0.1 seconds). Finally, our experimental evaluations show that FLASH is easily transferable to different hardware architectures, thus enabling us to do NAS on a Raspberry Pi-3B processor in less than 3 seconds.
Accelerating Markov Random Field Inference with Uncertainty Quantification
Venue: arXiv cs.AR 2021
Year: 2021

Statistical machine learning has widespread application in various domains. These methods include probabilistic algorithms, such as Markov Chain Monte-Carlo (MCMC), which rely on generating random numbers from probability distributions. These algorithms are computationally expensive on conventional processors, yet their statistical properties, namely interpretability and uncertainty quantification (UQ) compared to deep learning, make them an attractive alternative approach. Therefore, hardware specialization can be adopted to address the shortcomings of conventional processors in running these applications. In this paper, we propose a high-throughput accelerator for Markov Random Field (MRF) inference, a powerful model for representing a wide range of applications, using MCMC with Gibbs sampling. We propose a tiled architecture which takes advantage of near-memory computing, and memory optimizations tailored to the semantics of MRF. Additionally, we propose a novel hybrid on-chip/off-chip memory system and logging scheme to efficiently support UQ. This memory system design is not specific to MRF models and is applicable to applications using probabilistic algorithms. In addition, it dramatically reduces off-chip memory bandwidth requirements. We implemented an FPGA prototype of our proposed architecture using high-level synthesis tools and achieved 146MHz frequency for an accelerator with 32 function units on an Intel Arria 10 FPGA. Compared to prior work on FPGA, our accelerator achieves 26X speedup. Furthermore, our proposed memory system and logging scheme to support UQ reduces off-chip bandwidth by 71% for two applications. ASIC analysis in 15nm shows our design with 2048 function units running at 3GHz outperforms GPU implementations of motion estimation and stereo vision on Nvidia RTX2080Ti by 120X-210X, occupying only 7.7% of the area.
Several classes of bent functions over finite fields
Venue: arXiv cs.IT 2021
Year: 2021

Let $\mathbb{F}_{p^{n}}$ be the finite field with $p^n$ elements and $\operatorname{Tr}(\cdot)$ be the trace function from $\mathbb{F}_{p^{n}}$ to $\mathbb{F}_{p}$, where $p$ is a prime and $n$ is an integer. Inspired by the works of Mesnager (IEEE Trans. Inf. Theory 60(7): 4397-4407, 2014) and Tang et al. (IEEE Trans. Inf. Theory 63(10): 6149-6157, 2017), we study a class of bent functions of the form $f(x)=g(x)+F(\operatorname{Tr}(u_1x),\operatorname{Tr}(u_2x),\cdots,\operatorname{Tr}(u_τx))$, where $g(x)$ is a function from $\mathbb{F}_{p^{n}}$ to $\mathbb{F}_{p}$, $τ\geq2$ is an integer, $F(x_1,\cdots,x_n)$ is a reduced polynomial in $\mathbb{F}_{p}[x_1,\cdots,x_n]$ and $u_i\in \mathbb{F}^{*}_{p^n}$ for $1\leq i \leq τ$. As a consequence, we obtain a generic result on the Walsh transform of $f(x)$ and characterize the bentness of $f(x)$ when $g(x)$ is bent for $p=2$ and $p>2$ respectively. Our results generalize some earlier works. In addition, we study the construction of bent functions $f(x)$ when $g(x)$ is not bent for the first time and present a class of bent functions from non-bent Gold functions.
Performance Analysis of a Two-Hop Relaying LoRa System
Venue: arXiv cs.IT 2021
Year: 2021

The conventional LoRa system is not able to sustain long-range communication over fading channels. To resolve the challenging issue, this paper investigates a two-hop opportunistic amplify-and-forward relaying LoRa system. Based on the best relay-selection protocol, the analytical and asymptotic bit error rate (BER), achievable diversity order, coverage probability, and throughput of the proposed system are derived over the Nakagamim fading channel. Simulative and numerical results show that although the proposed system reduces the throughput compared to the conventional LoRa system, it can significantly improve BER and coverage probability. Hence, the proposed system can be considered as a promising platform for low-power, long-range and highly reliable wireless-communication applications.