# Computer Architecture Lab/WS2007/Project HB Lab1
## Instruction Sets of 3 chosen Microcontrollers
### MOS Technology 6502

The MOS Technology 6502 is an 8-bit microprocessor with a 16-bit address bus and is known as the first CPU (1975) with a 1-step instruction pipeline.

#### Registers

The next table shows all registers of the 6502:
| Abbrev. | Description | Width |
| PC | Program counter | 16 bit |
| AC | Accumulator | 8 bit |
| X | Index Register | 8 bit |
| Y | Index Register | 8 bit |
| SR | Status Register | 8 bit |
| PC | Stack Pointer | 8 bit |

#### Status Register Flags

The following table contains all status flags used for arithmetical operations and branch decisions:
| Abbrev. | Description |
| N | Negative |
| V | Overflow |
| B | Break |
| D | Decimal (use BCD for arithmetics) |
| I | Interrupt (IRQ disable) |
| Z | Zero |
| C | Carry |

#### Instruction Set

The instruction set is grouped into compare, stack, jump, memory, transfer and arithmetic operations. In total the processor supports 56 instructions. The instructions are of 16 bit width and have different execution times, in the range of 1 to 6 cycles.
* Compare Operations
The compare instructions set or clear three of the status flags (Carry, Zero, and Negative) that can be tested with branch instructions, without altering the contents of the operand. There are three types of compare instructions, see the next table. The compare instructions subtract (without carry) an immediate value or the contents of a memory location from the addressed register, but do not save the result in the register. The only indications of the results are the states of the three status flags: Negative (N), Zero (Z), and Carry (C). The combination of these three flags indicate whether the register contents are less than, equal to (the same as), or greater than the operand "data" (the immediate value or contents of the addressed memory location.
* Stack Operations
The processor stack has a 8 bit range and is top down accessed via LIFO principle. The instruction set provides storing and loading of the accumulator and the status register.
* Jump Operations
The jump instructions push the actual program counter (PC) to the stack and set the PC to a new value. If the jump goes to a interrupt routine, then additionally the status register is pushed to stack, too. The return instructions are then the reversal of the jump instructions.
* Memory Operations
Memory instructions allow the data exchange between the processors registers (index registers and the accumulator) and external memory. Additionally the content of the data sources is checked if its value is negative or zero and the status register is set, accordingly.
* Transfer Operations
These instructions enables the data exchange between the processors registers and also allows the accessing of particular stack addresses. Additionally the content of the data sources is checked if its value is negative or zero and the status register is set, accordingly.
* Status Register Operations
For the direct access of the status register.
* Arithmetic & Logical Operations
The arithmetic instructions set or clear four of the status flags (Carry, Zero, Overflow and Negative). Usually the operants of an instruction is a register and a memory address. Therefore for some of the supported operation the instruction set provides two different instructions, one for the operation on the index register and one for the operation on the accumulator.
* Branch Operations
Branch instructions increment (either +1 or +2) the PC as a function of the status register.
| Arithmetic & Logical Instructions ADC .... add with carry AND .... and (with accumulator) ASL .... arithmetic hift left BIT .... bit test DEC .... decrement DEX .... decrement X DEY .... decrement Y EOR .... exclusive or (with accumulator) INC .... increment INX .... increment X INY .... increment Y ROL .... rotate left ROR .... rotate right LSR .... logical shift right ORA .... or with accumulator SBC .... subtract with carry Jump Instructions JMP .... jump JSR .... jump subroutine RTI .... return from interrupt RTS .... return from subroutine Status Register Instructions CLC .... clear carry CLD .... clear decimal CLI .... clear interrupt disable CLV .... clear overflow SEC .... set carry SED .... set decimal SEI .... set interrupt disable Stack Instructions PHA .... push accumulator PHP .... push processor status (SR) PLA .... pull accumulator PLP .... pull processor status (SR) | Branch Instructions BCC .... branch on carry clear BCS .... branch on carry set BEQ .... branch on equal (zero set) BMI .... branch on minus (negative set) BNE .... branch on not equal (zero clear) BPL .... branch on plus (negative clear) BRK .... interrupt BVC .... branch on overflow clear BVS .... branch on overflow set Compare Instructions CMP .... compare (with accumulator) CPX .... compare with X CPY .... compare with Y Memory Instructions LDA .... Load Accumulator with Memory STA .... store accumulator LDY .... load X LDY .... load Y STX .... store X STY .... store Y Transfer Instructions TAX .... transfer accumulator to X TAY .... transfer accumulator to Y TSX .... transfer stack pointer to X TXA .... transfer X to accumulator TXS .... transfer X to stack pointer TYA .... transfer Y to accumulator |

### Motorola 68000

The Motorola 68000 is a 16-bit Microcontroller running with 8 MHz and CISC instruction set. All internal registers are 32-bit wide, the external address-bus has a 16-bit length, the external data bus 24-bit. The 68k Series was used in high-end computers (also the first Macintosh used a 68k) in the 1980s and later as controllers of numerous systems.

#### ISA Characteristics

| Characteristic | |
| ISA-Class | Register-Memory |
| Instruction-Set length | 16 bit |
| # Instructions | 56 |
| Data-Register length | 32 bit |
| # Data-Register | 8 |
| Address-Register length | 32 bit |
| # Address-Register | 8 |
Special about the address registers is the register A7 which is used for the Stack-Pointer. In addition to the 8 data- and 8 address registers the 68000 has a status register with these flags:
| Abbrev. | Description |
| 0 | Unused |
| 0 | Unused |
| 0 | Unused |
| X | Extend, is used like the carry bit in chain arithmetic but is not reset at most operations |
| N | Negative |
| Z | Zero |
| V | Overflow |
| C | Carry |
The instruction set was defined to enable almost full orthogonality -> addresses may be written in every way for almost all commands. In general, the 68000 shows no special instructions worth mentioning. Arithmetic operations (ADD, SUB, MUL), jump-, interrupt- and register commands are available. Latter supports no direct load/store commands.

### ARM

ARM stands for Advanced RISC Machine and is a 32 bit RISC architecture. Its the leading in 32 bit RISC CPUs and is found in nearly all modern mobile electronics. The most recent version is ARMv7M but all the newer versions of ARM include several different ISA for different applications. We will look at the original ARMv5 which has a 32bit instruction set and a 32bit address space.

#### Registers

These are all the registers of an ARM:
| Description | Width |
| Program counter | 32 bit |
| Current program status register | 32 bit |
| 5 dedicated saved program status registers | 32 bit |
| 30 General purpose register where 15 can be used at a time, the rest is used for exception handling | 32 bit |

#### Status Register Flags

The following table contains all status flags used for arithmetical operations and branch decisions:
| Abbrev. | Description |
| N | Negative |
| V | Overflow |
| Z | Zero |
| C | Carry |
| [19:0] | 20 reserved bits |
| I | Disable IRQ |
| F | Disable FIQ |
| T | Thumb(16bit) or ARM mode |
| M[4:0] | processor mode |

#### ISA Characteristics

All instructions have a length of 32 bit and are word aligned. Therefore the PC (r15) bits [1:0] are zero. R14 is also used to store the return address when branching. The instructions are pipelined. Branch instructions can jump up to 24 bit offset. At arithmetic/logic instructions one operant is always a register, the other is either an immediate value or a register value (optionally shifted). There is an additional multiplication instruction that can multiply 32 bit numbers with a 64 bit result. Load and store instructions can be offset addressed, pre-index or post-index addressed. More advanced functions are STM/LDM which block-transfer the GP-registers to or from the memory and SWP which exchanges the values in a register with a memory location. SWP allows atomic update of semaphores.