# Computer Architecture Lab/SS2013/Group3/Assignment2
## BraveMIPS Instruction Set Architecture
### BraveMIPS Instruction Set Format

The format of the 32bit MIPS I processor is kept:
| Type | -31-                format (bits)                -0- | -31-                format (bits)                -0- | -31-                format (bits)                -0- | -31-                format (bits)                -0- | -31-                format (bits)                -0- | -31-                format (bits)                -0- |
| R | opcode (6) | rs (5) | rt (5) | rd (5) | shamt (5) | funct (6) |
| I | opcode (6) | rs (5) | rt (5) | immediate (16) | immediate (16) | immediate (16) |
| J | opcode (6) | address (26) | address (26) | address (26) | address (26) | address (26) |
(same as on Wikipedia Page)

### BraveMIPS Instruction Set

The instruction set is focused on integer-based instructions and it essentially consists of a subset of the MIPS Instruction Set (see the full set on Wikipedia, section "Integer"). Other instructions might be added as project progresses.
| Category | Name | Instruction syntax | Meaning | Format/opcode/funct | Format/opcode/funct | Format/opcode/funct | Notes/Encoding |
| Arithmetic | Add | add $d,$s,$t | $d = $s + $t | R | 0 | 20$_{16}$ | adds two registers, executes a trap on overflow 000000ss sssttttt ddddd--- --100000 |
| Arithmetic | Subtract | sub $d,$s,$t | $d = $s - $t | R | 0 | 22$_{16}$ | subtracts two registers, executes a trap on overflow 000000ss sssttttt ddddd--- --100010 |
| Arithmetic | Add immediate | addi $t,$s,C | $t = $s + C (signed) | I | 8$_{16}$ | - | Used to add sign-extended constants (and also to copy one register to another: addi $1, $2, 0), executes a trap on overflow 001000ss sssttttt CCCCCCCC CCCCCCCC |
| Arithmetic | Multiply | mult $s,$t | LO = (($s * $t) << 32) >> 32; HI = ($s * $t) >> 32; | R | 0 | 18$_{16}$ | Multiplies two registers and puts the 64-bit result in two special memory spots - LO and HI. Alternatively, one could say the result of this operation is: (int HI,int LO) = (64-bit) $s * $t . See mfhi and mflo for accessing LO and HI regs. |
| Arithmetic | Divide | div $s, $t | LO = $s / $t HI = $s % $t | R | 0 | 1A$_{16}$ | Divides two registers and puts the 32-bit integer result in LO and the remainder in HI. |
| Data Transfer | Load word | lw $t,C($s) | $t = Memory[$s + C] | I | 23$_{16}$ | - | loads the word stored from: MEM[$s+C] and the following 3 bytes. |
| Data Transfer | Store word | sw $t,C($s) | Memory[$s + C] = $t | I | 2B$_{16}$ | - | stores a word into: MEM[$s+C] and the following 3 bytes. The order of the operands is a large source of confusion. |
| Logical | And | and $d,$s,$t | $d = $s & $t | R | 0 | 24$_{16}$ | Bitwise operation and 000000ss sssttttt ddddd--- --100100 |
| Logical | And immediate | andi $t,$s,C | $t = $s & C | I | C$_{16}$ | - | Leftmost 16 bits are padded with 0's 001100ss sssttttt CCCCCCCC CCCCCCCC |
| Logical | Or | or $d,$s,$t | $d = $s | $t | R | 0 | 25$_{16}$ | Bitwise or |
| Logical | Or immediate | ori $t,$s,C | $t = $s | C | I | D$_{16}$ | - | Leftmost 16 bits are padded with 0's |
| Logical | Exclusive or | xor $d,$s,$t | $d = $s ^ $t | R | 0 | 26$_{16}$ | |
| Logical | Nor | nor $d,$s,$t | $d = ~ ($s | $t) | R | 0 | 27$_{16}$ | Bitwise nor |
| Logical | Set on less than | slt $d,$s,$t | $d = ($s < $t) | R | 0 | 2A$_{16}$ | Tests if one register is less than another. |
| Logical | Set on less than immediate | slti $t,$s,C | $t = ($s < C) | I | A$_{16}$ | - | Tests if one register is less than a constant. |
| Bitwise Shift | Shift left logical | sll $d,$t,shamt | $d = $t << shamt | R | 0 | 0 | shifts shamt number of bits to the left (multiplies by $2^{shamt}$) |
| Bitwise Shift | Shift right logical | srl $d,$t,shamt | $d = $t >> shamt | R | 0 | 2$_{16}$ | shifts shamt number of bits to the right - zeros are shifted in (divides by $2^{shamt}$). Note that this instruction only works as division of a two's complement number if the value is positive. |
| Conditional branch | Branch on equal | beq $s,$t,C | if ($s == $t) go to PC+4+4*C | I | 4$_{16}$ | - | Goes to the instruction at the specified address if two registers are equal. 000100ss sssttttt CCCCCCCC CCCCCCCC |
| Conditional branch | Branch on not equal | bne $s,$t,C | if ($s != $t) go to PC+4+4*C | I | 5$_{16}$ | - | Goes to the instruction at the specified address if two registers are not equal. |
| Unconditional jump | Jump | j C | PC = PC+4[31:28] . C*4 | J | 2$_{16}$ | - | Unconditionally jumps to the instruction at the specified address. |
| Unconditional jump | Jump register | jr $s | goto address $s | R | 0 | 8$_{16}$ | Jumps to the address contained in the specified register |

### BraveMIPS Assembler

The assembler is based around JFlex and CUP (Java implementations of a lexer and parser). Until now I have successfully "compiled" the lexer file, whose source is found here: /assembler/jflex/bravemips_scanner.l I still need to get the CUP-specific syntax to run and integrate the two.
NOTE: in the worst case scenario, I might implement a pure Java String manipulation-based assembler (if I will have problems with JFlex and CUP).