# Computer Architecture Lab/Winter2006/PolzerJahn/Design
## SISP - Processor details & instruction set
### Basic data

* 16bit RISC CPU
* 16 internal registers
* von Neumann architecture
* 16bit address bus
* 32bit external data bus
* two instruction widths (16 bit, 32bit)
* External memory: 128 kB
* Connection to a PC: standard serial interface (RS-232)
* Number format: little endian
* Signed arithmetic (two's complement)

### Instruction set

Note: Instructions which take up 32 bit have an opcode higher than or equal to 0x20.
* Basic operations:
| Instruction | Operation | Opcode | Description |
| NOP | | 0x00 | No operation |
| MOV rA, rB | rA <- rB | 0x01 | Copy the contents of one register to another. |
* Logical operations:
| Instruction | Operation | Opcode | Description |
| AND rA, rB | rA <- rA AND rB | 0x02 | And conjunction of two registers |
| OR rA, rB | rA <- rA OR rB | 0x03 | Or conjunction of two registers |
| NOT rA | rA <- NOT rA | 0x04 | Logically inverts the contents of a register |
| XOR rA, rB | rA <- rA XOR rB | 0x05 | Xor conjunction of two registers |
* Arithmetic operations:
| Instruction | Operation | Opcode | Description |
| ADD rA, rB | rA <- rA + rB | 0x06 | Sum of two registers |
| ADC rA, rB | rA <- rA + rB | 0x13 | Sum of two registers (uses carry) |
| SUB rA, rB | rA <- rA - rB | 0x07 | Difference of two registers |
| SBB rA, rB | rA <- rA + rB | 0x14 | Difference of two registers (uses carry) |
| INC rA | rA <- rA + 1 | 0x08 | Increments the contents of a register |
| DEC rA | rA <- rA - 1 | 0x09 | Decrements the contents of a register |
| NEG rA | rA <- -rA | 0x15 | Negates the contents of a register |
* Shift operations:
| Instruction | Operation | Opcode | Description |
| SHL rA | rA <- rA << 1 | 0x0A | Shift left. Shifts the contents of a register to left by one bit, the right most bit is set to zero, the left most bit is stored in the carry flag |
| SHR rA | rA <- rA >> 1 | 0x0B | Shift right. Shifts the contents of a register to right by one bit, the left most bit is set to zero, the right most bit is stored in the carry flag |
| ASL rA | rA <- rA << 1 | 0x16 | Arithmetic shift left. Shifts the contents of a register to left by one bit, preserves sign, the left most bit is stored in the carry flag |
| ASR rA | rA <- rA >> 1 | 0x17 | Arithmetic shift right. Shifts the contents of a register to right by one bit, preserves sign, the right most bit is stored in the carry flag |
| ROL rA | rA <- rA << 1 | 0x0C | Rotate left through carry. Rotates the contents of a register to left by one bit, the right most bit is set to the value of carry, the left most bit is stored in the carry flag |
| ROR rA | rA <- rA >> 1 | 0x0D | Rotate right through carry. Rotates the contents of a register to right by one bit, the left most bit is set to the value of the carry, the right most bit is stored in the carry flag |
* Compare operations:
| Instruction | Operation | Opcode | Description |
| CMP rA, rB | | 0x0E | Compares the contents of two registers |
* Input/output operations:
| Instruction | Operation | Opcode | Description |
| LDC rA, <IMM> | rA <- IMM | 0x20 | Loads a constant value into a register |
| LD rA, rB | rA <- MEM(rB) | 0x0F | Loads a value using indirect addressing from the memory to a register |
| ST rA, rB | MEM(rB) <- rA | 0x10 | Stores the contents of a register into the memory using indirect addressing |
| INP rA, PORT | rA <- PORT | 0x11 | Reads a value from an I/O Port |
| OUTP rA, PORT | PORT <- rA | 0x12 | Writes a value to an I/O Port |
| LDIP rA | rA <- IP + 1 | 0x19 | Loads the address of the next instruction into the register. |
* Jump operations:
| Instruction | Opcode | Description |
| JMP <ADDR> | 0x21 | Unconditional jump (target defined by second instruction word) |
| JMPR rA | 0x18 | Unconditional jump (target defined by the contents of rA) |
| JZ <ADDR> | 0x22 | Jump if zero. The instruction pointer is set to the defiend address, if the zero flag is set. Otherwise the execution continues with the next instruction. |
| JNZ <ADDR> | 0x23 | Jump if not zero. The instruction pointer is set to the defiend address, if the zero flag is not set. Otherwise the execution continues with the next instruction. |
| JL <ADDR> | 0x24 | Jump if lesser. The instruction pointer is set to the defiend address, if the lesser flag is set. Otherwise the execution continues with the next instruction. |
| JNL <ADDR> | 0x25 | Jump if not lesser. The instruction pointer is set to the defiend address, if the lesser flag is not set. Otherwise the execution continues with the next instruction. |
| JG <ADDR> | 0x26 | Jump if greater. The instruction pointer is set to the defiend address, if the greater flag is set. Otherwise the execution continues with the next instruction. |
| JNG <ADDR> | 0x27 | Jump if not greater. The instruction pointer is set to the defiend address, if the greater flag is not set. Otherwise the execution continues with the next instruction. |

### Flags

| Name | Changed by | Default | Description |
| Zero | AND, OR, NOT, XOR, ADD, SUB, INC, DEC, CMP | 0 | If the result of an ALU operation is zero, this flag is set to 1. If the result is not zero the flag is set to 0. |
| Lesser | CMP | 0 | This flag is set to 1 if the contents of the first register is lesser than the contents of the second one, otherwise it is set to 0. |
| Greater | CMP | 0 | This flag is set to 1 if the contents of the first register is greater than the contents of the second one, otherwise it is set to 0. |
| Carry | ADD, SUB, INC, DEC, SHL, SHR, ROL, ROR | 0 | This flag is set, if a operation creates an overflow or underflow. |

### Instruction format

* Standard Instruction
8-bit Opcode, two 4-bit register numbers
| Bits | 0-7 | 0-7 | 8-11 | 12-15 |
| Content | OPCODE | OPCODE | (REG1) | (REG2 / PORT) |
* Extended instruction
8-bit Opcode, 4-bit register number (optional), 16 bit immediate value
| Bits | 0-7 | 0-7 | 8-11 | 12-15 | 16-31 | 16-31 | 16-31 | 16-31 |
| Content | OPCODE | OPCODE | (REG) | Reserved | IMM | IMM | IMM | IMM |

### Pipeline

SIPS uses a four stage pipeline:
* fetch
* decode
* execute
* write back
This file contains a detailed graphical description of each stage.