# Computer Architecture Lab

This course is a hands-on introduction into computer architecture. The main target is to build a simple, pipelined microprocessor and run it in an FPGA. This course is associated with a real course at the Technical University of Denmark.
Martin Schoeberl

## The Challenge

In this course you will design and develop extensions to the T-CREST time-predictable multicore processor and implement it in an FPGA.

### The Rules

There are only two rules for your design:
* The design has to be pipelined
* The design has to run in an FPGA
Everything else is up to you. Be creative!

### Additional Pages

* Projects
* Spring 2022
* Patmos at GitHub

#### Older Pages

* FPGA Hello World Example
* HOWTO
* Processor Project

### Grading

The lab work and the project are part of the final grade.
Following points are given for individual parts:
* Instruction Set (RISC-V and comparison): 20 points
* FPGA Design Flow: 5 points
* Chisel UART example: 5 points
* Project design and implementation: 50 points
* Project documentation (academic research paper style, maximum 8 pages): 20 points

## Assignments

Several assignments will help you to get started. We will start on a weekly basis and loosen it up at the end when the main activity is your project.
As a first action add a template for your project and your name at the
Student page.

### Week 1-2: Instruction Set Comparison

* Describe the RISC-V, Patmos, and a third processor's instruction set (summary)
* Compare these three ISAs against each other
* About 2-3 pages A4
* Deadline: Su 20/2/2022 @23:59

### Week 1: FPGA Design Flow

To get started using an FPGA start with following small projects:
A Simple Blinking LED
Use the Chisel examples repository and the flow as described in the Chisel slides:
* https://github.com/schoeberl/chisel-examples
* https://github.com/schoeberl/chisel-book/wiki
The FPGA Hello World Example describes the FPGA design flow with Quartus.

### Week 2: Combinational Circuits in Chisel (Simulation)

We adapt the lab for the remote/home office learning
* Lab 2 from the Chisel lab: https://github.com/schoeberl/chisel-lab/tree/master/lab2

### Week 2: UART in Chisel (FPGA)

UART Output
A UART will enable you to communicate between a PC and your processor. Therefore, this is our first real Chisel/VHDL example. For this experiment, connect a serial cable between the FPGA board and the serial port on your PC. Start a terminal program (gtkterm on Linux or Hyperterm on Windows) with baud rate 115200 and no handshake.
Extend the blinking LED example with a UART and write 0 and 1 to the serial line when the LED is off and on.
The Chisel code for the UART transmit is available as part of the Chisel examples at To simplify your design use an additional buffer as shown in the Sender example:
The VHDL code for a UART is available here: sc_uart.vhd and fifo.vhd. The UART is connected via the SimpCon interface.
With the slow output of characters (two per second) you can just write the data to the UART transmit register.
Extend the example by writing repeated numbers 0-9 as fast as the baud rate allows. In this case you have to extend your state machine to poll the UART status to check if the transmit buffer is free.
UART Input (optional)
Implement a state machine that receives characters from the UART. Switch the LED on and off with two different commands received on the serial line.
ModelSim UART print out (optional, not with Chisel)
There is a faster simulation version of the UART available that prints the output to the ModelSim console: sim_sc_uart.vhd.
Having mastered this UART examples gives you a great tool to debug your processor design. The UART output will probably be the only way to communicate with your processor.
For further tips see HOWTO.

### Week 3: Chisel Exercises (Simulation)

Exercises from Chisel lab3: https://github.com/schoeberl/chisel-lab/tree/master/lab3

### Week 3: Chisel Exercises (FPGA)

Continue with Chisel exercises (UART, ALU example, project from scratch)

### Week 4: Chisel Testing

Exercises from the Verify lab: https://github.com/chiselverify/class2020/tree/master/lab1 and https://github.com/chiselverify/class2020/tree/master/lab2

### Week 5: Patmos Exercise

Explore Patmos with the provided VM.
Exercise document: Getting Started with Patmos section in the Patmos Reference Handbook

### Week 7: Present Project Idea

A brief presentation of your project idea and the plan how to execute the idea.

### Documentation

A conference-style paper on their project, two-column format, maximum of 8 pages

### Demonstration

You will present your initial project idea at the project start and the finished project in the last week (presentation and demonstration).

## Hardware

To implement your design you can use any decent FPGA board. A serial interface (UART) will help for debugging. If you need more memory than the few KB on-chip the board should contain memory chips connected to the FPGA. I suggest using a board with SRAMs as they are easy to connect to the processor.

## Students Katleho

Add yourself to this list for this semester. It is strongly suggested for the students from DTU.
Spring 2022
The former student pages:
Spring 2021
Winter 2020
Spring 2020
Spring 2019
Spring 2018
Spring 2017
Spring 2016
Spring 2015
Spring 2014
Spring 2013
Spring 2012
Spring 2011
Winter 2008
Winter 2007
Winter 2006
Summer 2006