# Computer Architecture Lab/SS2013/GROUP1 LAB1

The three ISA reviewed are Motorola DSP56000, ARM and Microchip PIC which is followed by a comparison.

## Motorola DSP56000

The DSP56000, introduced in 1986, were the first microprocessor to implement the DSP56K ISA. The DSP56000 were mainly used for audio processing hence were able to perform fast multiplications and additions and also featured dual data-paths for parallel stereo audio processing. Due to its popularity a full C-Compiler has been released for architecture.

### Features

* 24bit fixed instruction- and data-width.
* Local SRAM
* Harvard Architecture with One instruction- and two data-memories.
* Three stage pipeline (IF, ID, EX).
* 62 instruction mnemonics

### Registers

* Two 24-bit registers for each path, that in "extended mode" could be concatenated to a single 48-bit register.
* 8 address Registers.

### ALU

The ALU was implemented as a load / store architecture with the aforementioned registers. It also featured two 56-bit accumulators for fast (Single Cycle) Multiply-Accumulate (MAC) instructions.

### Instruction Set

There are six types of instruction :
* Arithmetic
* Logical
* Bit Manipulative
* Loop
* Move
* Program Control
Many of these instruction are executed in dedicated units allowing for parallel execution, e.g. the Multiply-Accumulate can be executed while executing a parallel move on data in a single instruction cycle (2 clock cycles).
They are in general organized as follows :
Instructions format
| 23 DATA BUS MOVEMENT 8 | 7 OPCODE 0 |
Where the data bus movements can specify parallel moves from memory while executing the opcode. E.g. subtracting register Y from accumulator A and storing the result back in Y has the 8-bit opcode :
* 0 1 1 0 0 0 0 0
Where e.g. moving the contents of accumlator B into register X has the 16-bit code :
* 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0
So to perform the subtraction and moving in parallel the instruction becomes :
| 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 | 0 1 1 0 0 0 0 0 |
Although not all instructions can be defined using just 8-bit, so these are extended into the data-bus segment and decoded accordingly. In total 30 of the 62 instroction mnemonics can execute the parallel data moves in a single instruction cycle. The remaining 32 either extend the instruction to 48-bit by considering the following instruction as an extension, or can simply not perform parallel data-movements while executing their instruction - which can be the case of e.g. bit-manipulative instructions that modifies data-words in memory, hence needs at most 24 bits for just specifying the memory address.

### references

* DSP56000 Family User Manual

## ARM

The ARM is the most used 32-bit RISC architecture. One proof is that we can find it in almost all the modern mobile devices.
As RISC architecture, ARM adopt a uniform and fixed length of instruction fields to simplify instruction decode. Moreover, adopt a load/store architecture where data-processing operations only operate on register contents. It also adopts a simple addressing mode where all load/store addresses are determined from register contents and instruction fields only.
The ARM architecture add features to the basic RISC architecture that allow ARM processors to achieve a good balance of high performance, small code size, low power consumption, and small silicon area. Some of these features are the control over the Arithmetic Logic Unit (ALU) and shifter in most data-processing instructions, auto-increment and auto-decrement addressing modes to optimize program loops as well as conditional execution of almost all instructions to maximize execution throughput.

### Registers

The ARM processor has a total of 37 registers which are divided into:
* 31 general-purpose registers.
* 6 status registers.
The visible registers for the programmer are:
* 15 general-purpose registers
* 2 status registers
* Program counter register

### Instruction Set

The processor has to evaluate flags, before executing the instruction, to know if the instruction has to be executed or not. These flags are given by the Current Program Status Register (CSPR) and they are:
* zero (Z)
* carry / borrow / extend (C)
* overflow (V)
* negative / less than (N)
The ARM instruction set can be divided into six broad classes of instruction:
* Branch instructions.
* Data-processing instructions.
* Status register transfer instructions.
* Load and store instructions.
* Coprocessor instructions.
* Exception-generating instructions.