# Computer Architecture Lab/WS2008/Group2/Documentation
## Members of Group 2, Sweet16

* Franz-Josef Katzdobler, 0425195
* Daniel Reichhard, 0025792
* Stefan Resch, 0425306
* Matthias Wenzl, 0425388

## Instruction Set

| Mnemonic | Operation | Opcode | Opcode | Opcode | Opcode | Opcode | Opcode | Opcode | Opcode | Opcode | Opcode | Opcode | Opcode | Opcode | Opcode | Opcode | Opcode | Flags |
| NOP | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | C,Z |
| ADD | r1 := r1 + r2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | r2 | r2 | r2 | r2 | r1 | r1 | r1 | r1 | C,O,Z |
| SUB | r1 := r1 - r2 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | r2 | r2 | r2 | r2 | r1 | r1 | r1 | r1 | C,O,Z |
| MUL | r1 := r1 * r2 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | r2 | r2 | r2 | r2 | r1 | r1 | r1 | r1 | Z |
| AND | r1 := r1 and r2 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | r2 | r2 | r2 | r2 | r1 | r1 | r1 | r1 | Z |
| OR | r1 := r1 or r2 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | r2 | r2 | r2 | r2 | r1 | r1 | r1 | r1 | Z |
| XOR | r1 := r1 xor r2 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | r2 | r2 | r2 | r2 | r1 | r1 | r1 | r1 | Z |
| NOT | r1 := r1 not r2 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | r2 | r2 | r2 | r2 | r1 | r1 | r1 | r1 | Z |
| SHL | r1 := r1 << r2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | r2 | r2 | r2 | r2 | r1 | r1 | r1 | r1 | Z |
| SHR | r1 := r1 >> r2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | r2 | r2 | r2 | r2 | r1 | r1 | r1 | r1 | Z |
| SLA | r1 := r1 << r2 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | r2 | r2 | r2 | r2 | r1 | r1 | r1 | r1 | O,Z |
| SRA | r1 := r1 >> r2 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | r2 | r2 | r2 | r2 | r1 | r1 | r1 | r1 | Z |
| MOV | r1 := r2 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | r2 | r2 | r2 | r2 | r1 | r1 | r1 | r1 | Z |
| LD | r1 := mem(r2) | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | r2 | r2 | r2 | r2 | r1 | r1 | r1 | r1 | Z |
| ST | mem(r1) := r2 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | r2 | r2 | r2 | r2 | r1 | r1 | r1 | r1 | |
| PUSH | stack(sp) := r1 , sp := sp + 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | r1 | r1 | r1 | r1 | |
| POP | sp := sp - 1, r1 := stack(sp) | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | r1 | r1 | r1 | r1 | Z |
| RETI | pc := intret | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | |
| FSR | r1 := status_register | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | r1 | r1 | r1 | r1 | |
| JMP | pc := r1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | r1 | r1 | r1 | r1 | |
| CALL | reg15 := pc+1; pc := r1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | r1 | r1 | r1 | r1 | |
| RET | pc := r15 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |

## Assembler

The man page:
Assembler program for illustration:

## Pipelining

The pipeline itself consists of 4 Stages:
* Fetch
* Decode
* Execute
* Memory Stage
You can see the functional description [here].
The interaction with the buttons, leds and all kinds of memories is managed by a memory interface unit. Following memory mapping is applied:
| Memory | Begin | Begin | Begin | Begin | End | End | End | End |
| ROM | 0 | 0 | 0 | 0 | 0 | 0 | E | 0 |
| SPREGS | 0 | 0 | E | 1 | 0 | 0 | F | F |
| Program Space | 0 | 1 | 0 | 0 | F | F | F | F |
| UART ADDR | 0 | 0 | E | 1 | 0 | 0 | E | 1 |
| UART Read Data | 0 | 0 | E | 2 | 0 | 0 | E | 2 |
| UART Write Data | 0 | 0 | E | 3 | 0 | 0 | E | 3 |
| UART Control | 0 | 0 | E | 4 | 0 | 0 | E | 4 |