# Computer Architecture Lab/Winter2006/PolzerJahn/ThreeMicroDiscussion
## Abstract

This document was written for the lecture LU Computer Architecture at the Vienna University of Technology. The aim of this document is to compare three different processor architectures regarding their instruction set and their design.
We have chosen the following three architectures:
* Intel 8bit micro processor platform (Representative: 8088)
* Atmel Atmega 8bit micro controller family (Representative: Atmega128)
* Motorola 68k family (Representative: 68008)

## Comparison of the design
### 8088, 68008

Those two processors are based on the von Neumann architecture. This architecture uses a common program and data memory. The advantage is that fewer pins are needed on the package with the disadvantage of the so called von Neumann bottleneck.
The problem is that there can be a conflict while accessing the memory. This happens if the processor wants to access the data memory while loading an instruction.
Further on both processors are members of the CISC family. Their philosophy is to support multiple versions of each instruction. Each version uses different operands (registers, intermediates or memory).
This results in a big dispersion of the instructions execution time.

### Atmega128

This processor is based on the Harvard architecture. The advantage of this architecture is that there are dedicated program and data memories. Because of this the bottleneck of the von Neumann architecture is avoided.
The Atmega128 is member of the RISC processor family. This family is also known as load/store architecture. The base idea of it is that there are only a few versions of each instruction. Normally the instructions can only applied on registers. Additional there is a load and a store instruction to read and write the register values to the memory.
Because of this architecture the spreading of the instructions execution time is smaller than the one of CISC processors. Further on each instruction has a very short execution time (normally one clock cycle). But there are much more instructions needed to produce the same result as a CISC processor.
A RISC processor normally has a lot of data registers. They are needed because of the instruction's operand limitations.

## Instruction set analysis
### 8088

The Intel 8088 is based on the 8086 as a low-cost-chip, like Celeron today. The prefetch queue was reduced to 4 instead of 6 bytes. It was introduced 1979 and used in the original IBM PC.
The length of an instruction is between one and four bytes long. The first byte contains the operation code and flags. The following bytes contain the operands (register, memory address (different addressing schemes)).
The instructions are sorted to the following groups:
* Arithmetic
* Logic
* String manipulation
* Control (Comparison and jumps)
* Processor control (e.g. clearing the flags)
For further details take a look at home.comcast.net/~fbui/intel.html

### Atmega128

The length of an instruction is 16 or 32 bit. The first 16 bit contain the opcode and the operands. If a memory location is used literally then the second 16 bits are used as well.
The instructions are sorted to the following groups:
* Arithmetic
* Logic & Bit manipulation
* Transfer
* Control (Comparison and jumps)
For further details take a look at the Atmel Homepage

### 68008

The 68008 belongs to the 68k family of Motorola. It is narrowed to the 68000 with a smaller address-bus and data-bus. See the details in the summary-table. The instructions are divided into operations and address modes. Almost all address modes are available for almost all instructions. The minimal instruction size is 16bit. A lot of instructions need extra words to be appended for addresses, address-mode bits, etc. So an instruction consist of at least one word, but some have as many as 11 words. The first word is called "simple effective address operation word" which specifies the length of the instruction, the effective addressing mode, and the operation to be performed. The other words are called "brief and full extension words" which are specifying the instruction and operands.
* SINGLE EFFECTIVE ADDRESS OPERATION WORD (ONE WORD, SPECIFIES OPERATION AND MODES)
* SPECIAL OPERAND SPECIFIERS (IF ANY, ONE OR TWO WORDS)
* IMMEDIATE OPERAND OR SOURCE EFFECTIVE ADDRESS EXTENSION (IF ANY, ONE TO SIX WORDS)
* DESTINATION EFFECTIVE ADDRESS EXTENSION (IF ANY, ONE TO SIX WORDS)
The 68008 provides 14 different address modes and instructions are sorted to the following groups:
* Arithmetic
* Logic & Bit manipulation
* Multiprocessing control
* Flow of control
For further details take a look at the Freescale Homepage

## Summary

| | 8088 | ATmega128 | 68008 |
| Architecture | CISC | RISC | CISC |
| Memory architecture | von Neumann | Harvard | von Neumann |
| Internal data bus width | 16 | 8 | 32 |
| External data bus width | 8 | 8 | 8 |
| # of data registers | 4 (AX, BX, CX, DX) | 32 (r0-r31) Six of them can be combined to three 16bit registers (X, Y, Z) | 8 (D0 - D7) |
| # of other registers | 4 16bit segment registers (CS, DS, SS, ES) 16bit stack pointer (SP) 16bit instruction pointer (IP) 2 16bit index registers (SI, DI) 16bit base pointer register (BP) | 66 device registers (mainly used to configure or access hardware resources) | 7 address register (A0-A6) 2 32bit stack pointers (A7+ A7') 32bit program counter (PC) |
| # Flags | 9 | 7 | 7 |
| Instruction length | 1, 2, 3 or 4 byte | 2 or 4 byte | 1 - 11 word |
| # instructions | 90 | 100 | 54 |
| # instruction variations | 188 | 133 | 86 |
| Minimum execution time | 2 | 1 | ? |
| Maximum execution time | 190 | 4 | ? |
| Mean instruction execution time (Not average execution time!) ${\frac {\sum _{Instructions}Cycles/Instruction}{Number\ of\ the\ processor's\ instructions}}$ | 21.8 | 1.6 | ? |
| Pipeline | 4 byte prefetch queue (fetch, decode) | single level (fetch, decode) | single level (fetch, decode) |
| Address bus width | 20 | 16 | 20 (DIP version) 22 (PLCC version) |
| Package | DIP40 QFP56 | TQFG64 QFN/MFL64 | DIP48 PLCC52 |
| Interrupts | 256 (38 reserved) interrupt vectors including: 1 non maskable external interrupt 1 maskable external interrupt | 35 interrupt vectors including: 8 external interrupts 1 external reset interrupt 26 interrupts to handle non processor hardware (like timer or ADC) | 4 external interrupts (DIP version) 8 external interrupts (PLCC version) |
| Other features (non processor features) | | Multiple timers On chip memory (RAM, EEPROM, FLASH) SPI USART ADC 7x 8-Bit I/O | |