OpenLLM-France/wikimedia huggingface dataset:
# Handbook of Management Scales/Process control
## Process control (alpha = 0.8459)
### Items

* Processes in our plant are designed to be "fool proof".
* A large percent of the equipment or processes on the shop floor are currently under statistical quality control.
* We make extensive use of statistical techniques to reduce variance in processes.

### Source

* Flynn et al. (1994): A framework for quality management research and an associated measurement instrument. Journal of Operations Management, Vol. 11, No. 4, pp. 339-366.

## Process control (alpha = 0.79/0.81)
### Items

* My pay increases and other tangible rewards depend on how well I follow sales procedures.
* My pay increases and other tangible rewards depend on my knowledge of selling procedures.
* My immediate supervisor monitors the extent to which I follow established procedures.
* My immediate supervisor evaluates procedures we use to accomplish the task of selling.
* My immediate supervisor modifies the procedures if desired results are not obtained.
* Primary weight in evaluating salespersons' performance is placed on sales behavior.

### Source

* Atuahene-Gima/Li (2002): When does trust matter? Antecedents and contingent effects of supervisee trust on performance in selling new products in China and the United States. Journal of Marketing, Vol. 66, No. 3, pp. 61-81. Adapted from Jaworski/MacInnis (1989).

### Related Scales

* New service development process focus
* Process management
# Handbook of Management Scales/Power
## Power (CR = 0.75)
### Description

Hofstede's five cultural factors are reconceptualized as ten personal cultural orientations: independence, interdependence, power, social inequality, masculinity, gender equality, risk aversion, ambiguity intolerance, tradition, and prudence. A new 40-item scale is developed to measure these personal cultural orientations. Much effort has been invested in ensuring validity, reliability, and cross-cultural measurement equivalence of the new scale.

### Definition

Power represents the extent to which individuals accept differences in the power wielded by various members in any organization.

### Items

* I easily conform to the wishes of someone in a higher position than mine. (0.72)
* It is difficult for me to refuse a request if someone senior asks me. (0.68)
* I tend to follow orders without asking any questions. (0.67)
* I find it hard to disagree with authority figures. (0.65)

### Source

* Sharma (2010): Measuring Personal Cultural Orientations: Scale Development and Validation. Journal of the Academy of Marketing Science, Vol. 38, No. 6, pp. 787–806
# Handbook of Management Scales/Private benefit, competition
## Private benefit$_{competition}$ (AVE = 0.65; CR = 0.94)
### Description

The author (1) adopts a coopetition-based approach in theoretically conceptualizing value creation in interfirm alliances as a construct consisting of three dimensions: common benefit, private benefit$_{cooperation}$, private benefit$_{competition}$ and (2), based on data collected in India, empirically validates a scale to measure these dimensions.

### Definition

Private benefits refer to gains realized by each alliance partner individually. Private benefit$_{competition}$ is defined as a value created by the focal firm by competing against its alliance partner to outperform it in activities, which are directly linked to the alliance-related activities but take place beyond the alliance boundary (Burt, 1991; Kumar, 2010; Rai, 201_).

### Items

In this relationship, we have been able to create more value because:
* … our capabilities for leveraging jointly developed processes are better than the partner. (0.83)
* … our capabilities of leveraging jointly developed technology are better than the partner. (0.82)
* … our capabilities of marketing jointly developed products and services are better than the partner. (0.77)
* … our capabilities for leveraging jointly developed intellectual property are better than the partner. (0.89)
* … the new product and services jointly developed by us has opened up new market opportunities and customer base. (0.62)
* … our capabilities to differentiate the product and services jointly developed by us are better than the partner. (0.79)

### Source

* Rai (201_): A Co-opetition-Based Approach to Value Creation in Interfirm Alliances: Construction of a Measure and Examination of Its Psychometric Properties. Journal of Management, Vol. __, No. __, pp. __-__.

### Related Scales

* Alliance performance
* Value creation in interfirm alliances: common benefit, private benefit$_{cooperation}$, private benefit$_{competition}$
# Handbook of Management Scales/Private benefit, cooperation
## Private benefit$_{cooperation}$ (AVE = 0.58; CR = 0.88)
### Description

The author (1) adopts a coopetition-based approach in theoretically conceptualizing value creation in interfirm alliances as a construct consisting of three dimensions: common benefit, private benefit$_{cooperation}$, private benefit$_{competition}$ and (2), based on data collected in India, empirically validates a scale to measure these dimensions.

### Definition

Private benefits refer to gains realized by each alliance partner individually. Private benefit$_{cooperation}$ is defined as private benefits that accrue to a firm as a result of cooperative behavior among the alliance partners (Rai, 201_).

### Items

Because of this relationship, our firm has:
* … used the competencies acquired from the partner to create value by improving its existing competencies. (0.72)
* … used the new ideas and skills acquired from the partner to create value by improving its products and services. (0.79)
* … used the R&D skills acquired from the partner to create value by engaging in greater innovation. (0.77)
* … used the consumer insights acquired from the partner to create value by leveraging its market position. (0.70)
* … used the knowledge of systems and processes acquired from the partner to create value by enhancing its organizational effectiveness. (0.82)

### Source

* Rai (201_): A Co-opetition-Based Approach to Value Creation in Interfirm Alliances: Construction of a Measure and Examination of Its Psychometric Properties. Journal of Management, Vol. __, No. __, pp. __-__.

### Related Scales

* Alliance performance
* Value creation in interfirm alliances: common benefit, private benefit$_{cooperation}$, private benefit$_{competition}$
# Microprocessor Design/Microcode

RISC units are typically faster and more efficient than CISC units. For this reason, many CISC processors have complicated instruction decoders that actually convert the CISC machine code into a RISC-like set of internal instructions known as microcodes. These microcodes are then fed into the internal core of the processor, which is based on the RISC design.
The most common way to implement memory-memory architecture CPUs (even with single-chip microprocessors, not just wire-wrapped machines) uses a small "control store" ROM. The output data bits of the control store are latched in the microinstruction register (reminiscent of the way instructions fetched from RAM are latched in the instruction register). The clock signal determining the cycle time of the system primarily clocks the microinstruction register. The bits stored in the microinstruction register directly control everything that goes on in the CPU. (In some processors, the microinstruction register is the only thing connected to the clock signal. Later we will discuss "pipelining", a technique involving pipeline registers connected to the clock signal).
Some of the bits in the microinstruction register do nothing but drive some of the address bits of the control store. Those bits -- that sub-field of the pipeline register -- is sometimes called the "microprogram counter", even though it is merely a latch -- typically the control store is programmed such that those bits increment on every clock cycle, and reset to zero when a new instruction is loaded into the instruction register. The instruction register directly drives some of the address lines of the control store ROM. A few more address lines of the control store ROM are driven by status bits such as the Z flag and the C flag.
Some CPUs, such as the ECOMIPS, the Intel Core 2 and the Intel Xeon, use "writable microcode" -- rather than storing the microcode in ROM or hard-wired logic, the microcode is stored in a RAM called a Writable Control Store or WCS.

## Further Reading

* "Viktor's Amazing 4-bit Processor" has microcode that he says *could* have been implemented with about 90 diodes in a traditional diode matrix; but instead he implemented microcode with a Flash memory chip he can re-program in-circuit using manual switches.
* MT15 by Dieter Mueller uses transistors instead of diodes in a big AND-OR PLA (programmable logic array) matrix to implement the microcode.

## References

* ↑ US Patent 5050073. "Microinstruction execution system for reducing execution time for calculating microinstruction". 1987.
* ↑ Jonathan G. Campbell. "The Central Processing Unit (CPU)" 2000.
* ↑ Patrick R. Schaumont. "A Practical Introduction to Hardware/Software Codesign". 2010.
* ↑ Govindarajalu. "Computer Architecture and Organization: Design Principles and Applications". 2004.
* ↑ B. Govindarajalu. "Computer Architecture and Organization, 2E" 2010.
* ↑ "ECOMIPS: An Economic MIPS CPU Design on FPGA" by Xizhi Li and Tiecai Li
* ↑ Wikipedia: microcode#Writable_control_stores
# Microprocessor Design/Multiply and Divide Blocks
## Multiply and Divide Problems

Multiplication and Division operations are significantly more complicated than addition or subtraction operations. This additional complexity leads to more hardware, more complicated hardware, and longer processing time.
In hardware, multiplication and division are performed by a series of sequential additions and arithmetic shifts. for this reason, it is imperative that we have efficient adders and shifters at our disposal.
Multipliers and dividers are composed of shifters and adders. It is typically not possible, or not desirable to use the main adder and shifter units of the ALU, so a microprocessor will typically have multiple ALU units (a primary unit for addition and subtraction, and units embedded in the multiplication and division units). These are other good reasons why our ALU and shifters need to be small and fast.

## Multiplication Algorithms
### Wallace tree

The Wallace tree, a specialized structure for performing multiplication, has been called one of the most important advances in computing.
A Wallace tree using many identical 3:2 compressors (aka full adders), such as the TI 74x275 chip, or the TI 74x183 chip, is one popular way to implement single-cycle multiplication. The datasheets for the TI 74x261 and 74x284 describe some practical details of implementing multiplication with a Wallace tree. The Dadda multiplier uses the same 3:2 compressors in a slightly more efficient arrangement.

## Multiply and Accumulate

Multiply and accumulate (MAC) operations perform a multiplication and an addition in a single instruction. For instance, the instruction:
Would perform the operation:
This is valuable for math-intensive processors, such as graphics processors and DSPs.
An MAC tends to have a long critical path, so if your processor has an MAC operation it is probably possible to include other complicated arithmetic operations.
In a processor with an accumulator architecture, MAC operations will use the accumulator as the destination register, so the instruction:
Will perform the operation:

### Fused Multiply-Add

A fused multiply-add operation is a floating-point operation that is similar to the MAC. However, in the fused operation, the floating-point values are not rounded between the multiply and the add, they are rounded afterwards. For more information about floating-point rounding, see Floating Point.
* ↑ DTACK Grounded, The Journal of Simple 68000/16081 Systems Issue # 29 - March 1984 p. 6.
# Microprocessor Design/Multi Cycle Processors

Single-cycle processors suffer from poor speed performance. Control and data signals must propagate completely through the processor in a single cycle, which means that cycle times need to be long, and many parts of the hardware tend to be dormant for much of the cycle.

## Multi-Cycle Stages

Multi-cycle processors break up the instruction into its fundamental parts, and executes each part of the instruction in a different clock cycle. Since signals have less distance to travel in a single cycle, the cycle times can be sped up considerably.
Typically, an instruction is executed over at least 5 cycles, which are named as such:

### IF

    Fetch the instruction from memory

### ID

    Decode the instruction, and generate the necessary control signals

### EX

    Feed the necessary control signals into the ALU and produce a result

### MEM

    Read from memory, if specified

### WB

    Write the result back to the register file or to memory.
This is just a textbook example, and modern processors tend to use much more steps than this to execute an instruction.
Example: MicroChip PIC16 Microcontroller
The PIC Microcontroller, manufactured by MicroChip Technology Inc, is a family of embedded microcontrollers. The PIC units vary, but execute an instruction every 2-4 clock cycles. All instructions typically execute in the same number of cycles, except for branch instructions.

## Hardware Reuse

The primary benefit to a multicycle design is to be able to share hardware elements, specifically the ALU, among various tasks. In a multicycle processor, a single ALU can be used to update the instruction pointer (in the IF cycle), perform the operation (in the EX cycle), and calculate a necessary memory address (in the MEM cycle). Multicycle processors also allow computers that have a single memory unit, instead of the two separate instruction and data memory units of the traditional harvard machine. This is because the instructions are loaded on one cycle, and the data memory is interfaced on another cycle.
Multi-cycle processors are typically used in applications where resources are at a premium, and speed is not as important.
# Microprocessor Design/Optimizations

Once the microprocessor is designed, there is typically a large amount of room for that design to be made more efficient through optimization. The control unit specifically can be subject to logical minimizations.
As the specific requirements of each component are understood better, through simulation and prototyping, the clock speed of the system can be increased to reduce waste.
The most common operations, memory loads, memory stores, and basic arithmetic can be laid out in such a way that they can be performed quickly and easily.
The word "optimization" is likely a misnomer because it is unlikely that the best possible solution will ever be found to the complex problems that arise during microcontroller or microprocessor design. However, there are typically ways to make things better, even if they can't be made optimal.
# Microprocessor Design/Out Of Order Execution

In a superscalar or similar processor design, there are multiple execution units that can be used to process pieces of data simultaneously. However, these execution units are not always used at the same time, and some processing power is lost. Sometimes, it is possible to feed instructions to all the execution units if we take the instructions out of their original order. Out of order execution (OOOE) is when a processor is capable of executing instructions out of their original order, in an attempt to do more work in parallel, and execute programs more quickly.
The Tomasulo scheduling algorithm is a OOOE algorithm that supports function units with variable latency, including data-dependent latency.

## Hazards

OOOE comes with some significant hazards, and the hazard detection units in these processors are not trivial. The dependencies of all instructions need to be determined, and instructions cannot execute before or at the same time as instructions on which they are dependent.

## Example: Intel Hyperthreading

Hyperthreading is the name for a technology developed by Intel for use in the Pentium 4 chip. Hyperthreading works by duplicating some architectural components of the processor, such as the status flags, the control registers, and the general purpose registers. Hyperthreading does not, however, duplicate any of the execution units.
In a hyperthreaded system, it appears to the operating system that there are two separate processors, when there is only one processor. The OOOE engine feeds instructions from the two separate execution threads to the execution cores, to try and keep all of the cores simultaneously busy. In general hyperthreading increases performance, although in some instances this additional complexity actually decreased performance.
* ↑ Daniel Kröning. "Design and Evaluation of a RISC Processor with a Tomasulo Scheduler". Section "2.2 The Tomasulo Scheduling Algorithm". 1999.
# Handbook of Management Scales/Risk aversion
## Risk aversion (CR = 0.81)
### Description

Hofstede's five cultural factors are reconceptualized as ten personal cultural orientations: independence, interdependence, power, social inequality, masculinity, gender equality, risk aversion, ambiguity intolerance, tradition, and prudence. A new 40-item scale is developed to measure these personal cultural orientations. Much effort has been invested in ensuring validity, reliability, and cross-cultural measurement equivalence of the new scale.

### Definition

Risk aversion is the extent to which people are reluctant to take risk or make risky decisions.

### Items

* I tend to avoid talking to strangers. (0.83)
* I prefer a routine way of life to an unpredictable one full of change. (0.79)
* I would not describe myself as a risk-taker. (0.77)
* I do not like taking too many chances to avoid making a mistake. (0.75)

### Source

* Sharma (2010): Measuring Personal Cultural Orientations: Scale Development and Validation. Journal of the Academy of Marketing Science, Vol. 38, No. 6, pp. 787–806

## Related Scales

* Firm risk preference
* Risk taking
# Handbook of Management Scales/Role model
## Role model (alpha = 0.86)
### Description

Drawing on social support theory and using data from two samples of lower wage workers, the authors develop and validate a measure of family supportive supervisor behaviors (FSSB). FSSB is conceptualized as a multidimensional superordinate construct with four subordinate dimensions: emotional support, instrumental support, role modeling behaviors, and creative work-family management. Results from multilevel confirmatory factor analyses and multilevel regression analyses provide evidence of construct, criterion-related, and incremental validity.

### Definition

Family supportive supervisor behaviors are defined as behaviors exhibited by supervisors that are supportive of families.
Role modeling behaviors refers to supervisors demonstrating how to integrate work and family through modeling behaviors on the job. Here, role modeling can be defined as the extent to which supervisors provide examples of strategies and behaviors that employees believe will lead to desirable work-life outcomes.

### Items

* My supervisor is a good role model for work and nonwork balance.
* My supervisor demonstrates effective behaviors in how to juggle work and nonwork balance.
* My supervisor demonstrates how a person can jointly be successful on and off the job.

### Source

* Hammer et al. (2009): Development and Validation of a Multidimensional Measure of Family Supportive Supervisor Behaviors (FSSB). Journal of Management, Vol. 35, No. 4, pp. 837-856.
# Handbook of Management Scales/Schedule flexibility
## Schedule flexibility (alpha = 0.78)
### Description

The authors develop and validate a 16-item measure of i-deals negotiated by job incumbents across four content domains: task and work responsibilities, schedule flexibility, location flexibility and financial incentives.

### Definition

Idiosyncratic deals (i-deals) are "mutually beneficial, personalized agreements of a nonstandard nature that are negotiated between individual employees and their employers".
The schedule flexibility dimension is associated with when employees do their jobs.

### Items

* My supervisor considers my personal needs when making my work schedule. (0.83)
* At my request, my supervisor has accommodated my off-the-job demands when assigning my work hours. (0.75)
* Outside of formal leave and sick time, my supervisor has allowed me to take time off to attend to non-work-related issues. (0.61)

### Source

* Rosen et al. (2013): Let’s Make a Deal: Development and Validation of the Ex Post I-Deals Scale. Journal of Management, Vol. 39, No. 3, pp. 709–742

### Comments

The scale was tested across three samples; it can, thus, be assumed that it is valid and reliable.
# Handbook of Management Scales/Robustness
## Robustness (alpha = 0.87, CR = 0.87)
### Description

Two dimensions of resilience were identified: agility and robustness.

### Definition

Robustness is defined as the ability of a supply chain to resist change without adapting its initial stable configuration (Wieland/Wallenburg, 2012).

### Items

To what extent do the statements apply to your supply chain? (1 – strongly disagree; 7 – strongly agree):
* For a long time, our supply chain retains the same stable situation as it had before changes occur. (0.71)
* When changes occur, our supply chain grants us much time to consider a reasonable reaction. (0.73)
* Without adaptations being necessary, our supply chain performs well over a wide variety of possible scenarios. (0.92)
* For a long time, our supply chain is able to carry out its functions despite some damage done to it. (0.80)

### Source

* Wieland/Wallenburg (2013): The Influence of Relational Competencies on Supply Chain Resilience: A Relational View. International Journal of Physical Distribution & Logistics Management, Vol. 42, No. 4, pp. 300-320.

### Related Scales

* Agility
# Handbook of Management Scales/Role ambiguity
## Role ambiguity (alpha = 0.93/0.87)
### Items

* I am not sure how much service I should provide to customers.
* I am not sure which specific company strengths I should present.
* I am not sure which product benefits I should highlight to customers.
* I am not sure how I am expected to handle customer objections.
* I am not sure how I am expected to handle unusual customer problems and situations.
* I am not sure how I am expected to interact with customers.

### Source

* Atuahene-Gima/Li (2002): When does trust matter? Antecedents and contingent effects of supervisee trust on performance in selling new products in China and the United States. Journal of Marketing, Vol. 66, No. 3, pp. 61-81. Previously used by Singh/Rhoads (1991).