# 360 Assembly/Branch Instructions

The branch instructions for the 360 Series mainframe computer come in two types: instructions which branch where a return address is provided (such as a subroutine call) and one-way branches where no return address is provided.
All branch instructions come in 3 forms: No Branch At all, otherwise known as No-Operation or NO-OP, Conditional Branch, and Unconditional Branch
In the examples below, it is presumed that R0,R1,R14,R15 are labels "equated" to the equivalent registers in these examples (0, 1, 14 and 15, respectively) to provide a cross reference listing. The examples would function equally well without the R prefixes, but it is common practice for programmers to use a label equated to each of the numbers, because references to registers do not show up in the cross-reference listing, but references to symbols do.

## Branch with return address provided

The following instructions provide a branch to another address, where a register is provided to store the address of the instruction following the branch to provide a means to return to the calling point.
The following instructions are available for all models of the 360 series: 360, 370, 390, 390/ESA and z/System. :
| * BAL - Branch And Link | * BALR - Branch and Link Register |
| The following instructions are available only on 370 and above: 370, 390, 390/ESA and z/System. ||
| * BAS - Branch And Save | * BASR - Branch and Save Register |

## Branch without return

The following instructions are available for all models of the 360 series, including the 360, 370, 390 and z/System.
| * BC - Branch on Condition$^{[1]}$ | * BCR - Branch on Condition Register$^{[1]}$ | * BCT - Branch on CounT | * BCTR - Branch on CounT Register |
$^{[1]}$ Extended mnemonics provide condition tests, including BR and B for unconditional branch; BNO, BE, BNE, BH, BL and BM, among others

## Examples

The general use of these is explained below.

### No Branch

Certain types of branch instructions are treated as a no branch, or no-operation (NO-OP). Generally they involve the use of Register 0 or a mask value of 0. These are:
* Register branch targeting Register 0
* Register to storage branch (regardless of mask) where the Index register is 0
* Register to storage branch where the mask is 0

### Unconditional branch

An unconditional branch instruction causes the Program location counter (PSW) to be set to the address specified in the register or the register plus a 12-bit offset, or the register & offset plus the value of an additional "index" register.
The branch does not occur, and is treated as a no-op, for a BR instruction using register 0. The branch does not occur, and is treated as an instruction to load the address of the following instruction into the left register, if the right register in a BALR instruction is 0. No conditional branch - including unconditional branch - will occur if the index register is 0.
These instructions may be one of the following types:-
* Register to register (RR)
* Storage (RS)
* Indexed (RX)

### Conditional branch

A conditional branch instruction causes the location counter in the PSW to be set to the address specified in the register or the register plus a 12-bit offset, if a condition is satisfied (and the register is not 0). There are two types, condition by mask and condition by index.
Conditional branches may be one of the following types:-
* Condition by mask, Storage (RS)
* Condition by index, storage (RX)
* Condition by Index, Register (RR)

## Branch Table (technique)

A branch table is a literally a set of contiguous unconditional branch instructions which are of equal length (usually 4 bytes), that are used to very efficiently branch directly to one of this set, using an index. This index is often generated from some source input value that may itself be non-sequential as in the example below. This method is considerably faster than using either a binary search or sequential table lookup for example. Lookups involve compare instructions and a subsequent conditional branch. Only 5 instructions are used in the example (2 of which are unconditional branch) that perform the following:-
* 1. Validate the input (translates any input values, other than A,S,M,D, to a null index value)
* 2. Translate the input value (using an INSERT CHARACTER (IC) instruction with an index) to one of 0,4,8,12 or 16 (the index). Earlier versions of this technique used (TR) & (IC) instructions, which was 4-5 times slower than using two (IC) instructions).
* 3. Branch unconditionally to the appropriate unconditional branch instruction using the index - a zero value results in branching to an error routine. (unconditional branches do not rely on previous character or numeric comparison instructions)
    Example Consider an input variable that is a single byte character in the range A-Z , where specific values such as A,S,M,D decide the processing logic within the program. In this case A=Add,S=Subtract,M=Multiply and D=Divide.
In the following two examples, the time taken to perform validity and go to the appropriate label is fixed, irrespective of the number of different valid one byte input characters.

### Example using a table of branch instructions
#### Example using a table of 2-byte offsets

Another very similar technique to the above branch table can be used. Instead of a table of branch instructions, a table of absolute or relative addresses (offsets) can be built by the Assembler. This requires just one extra instruction but increases the branch range to 64K without need for additional base register coverage and halves the size of the Table.
An alternative method of defining TABLE2 above, letting the Assembler automate the placement of the index bytes, is as follows (example shown for "A" and "D" only for brevity).

#### Example using a table of 4-byte absolute addresses

A table of absolute addresses can be built by the Assembler. This requires just one extra instruction but increases the branch range to 2 gigabytes (i.e. the whole address space for 31 bit processors).

## 370 and zSystem Instructions

The following branch instructions are available in the 370 and zSeries machines—To be added later--
* 360 Assembly Instructions
* Branch — Data Transfer — Control Flow — Arithmetic — Logic — Shift and Rotate — Other

## See also

* Wikipedia Index (information technology)

## External links

* System/360 Instruction Timing Information
360 Assembly Language :
| 360 Family | Introduction · Basic FAQ · 360 Family · 360 Architecture |
| 360 Instruction Set | 360 Instructions · Branch Instructions · Data Transfer Instructions · Control Flow Instructions · Arithmetic Instructions · Logic Instructions · Shift and Rotate Instructions · Priveleged Instructions · Other Instructions |
| Syntaxes and Assemblers | 360 Assemblers· Pseudo Instructions |
| Instruction Extensions | Floating Point · High-Level Languages |