# SPARC Assembly/Condition Codes & Branching
## The Binary Number System

The binary (base two) system is the number system that computers use to represent the data stored in them. In contrast with the base ten system that we are used to, which uses numbers 0-9 to represent all possible real numbers, the binary system uses only numbers 0-1. For example, the number 2112 is represented as a binary number is 100001000000, the number 3 is 11, and as you might suspect, the number 0 is still just 0.
It may seem that choosing to represent numbers in this way only introduces unnecessary hassle and complexity that impedes usability, but actually the opposite is true. The reason computer engineers chose to use this relatively unfamiliar number system is that it is much simpler to implement and represent using computer circuitry, and thus makes the creation of more elaborate computer components much simpler than it would be if a higher base system was used.

## Binary Arithmetic

Even though it may seem the contrary, binary numbers can be used just as base ten numbers can. You can add them, subtract them, multiply them, divide them, square them, and so on. For now, more information can be found here.

## Two's Complement

While adding two numbers in Binary may be trivial, the subtraction of even the smallest of values is much more complicated. Fortunately the Two's complement rule allows for a binary subtraction to be converted into an addition operation which is easier to perform.
Take the following example:

## Condition Codes

Condition Code Registers are special flags (bits) contained the condition code register (CCR) that are used to record information about condition code (<opcode>cc) instructions so that branching decisions may be made by a program. As discussed above, the context of whether a number is signed or unsigned will imply very different results when it is used in calculation. As such, SPARC uses different sets of CCR's to manage signed and unsigned data.

### Signed Condition Codes

For signed numbers, SPARC uses three of the three condition codes- the Z, N, and V bits - to regulate conditional branching:
      * Z: This flag keeps track of whether the result of a calculation of a condition code instruction was zero or not. If the result is zero it is set to 1, if not it is set to 0. For example,
* mov 4, %l1 !move 4 into %l1
* subcc %l1, 4, %g0 !subtract 4 from %l1
             would set the Z register to 1, but
* mov 4, %l1 !move 4 into %l1
* subcc %l1, 3, %g0 !subtract 3 from %l1
             would set it to zero.
      * N: This flag keeps track of whether the result of a calculation of a signed condition code instruction was negative or not. if the result is negative it is set to 1, if not it is set to 0. For example,
* mov 4, %l1 !move 4 into %l1
* subcc %l1, 5, %g0 !subtract 5 from %l1
             would set the N register to 1, but
* mov 4, %l1 !move 4 into %l1
* subcc %l1, 3, %g0 !subtract 3 from %l1
             would set it to zero.
      * V: This flag keeps track of whether the result of a signed calculation is too large to be held by a 32 bit (or possibly 64 bit) register. If the result is too large it is set to 1, if not it is set to 0.