# Electronics/CMOS
## CMOS

CMOS stands for Complementary Metal-Oxide-Semiconductor. Metal-Oxide-Semiconductor refers to the construction method of the component Field-Effect Transistors (MOSFETs), and Complementary means that CMOS uses both n-type (nMOS) and p-type (pMOS) transistors. Older designs had used only n-type transistors, and are referred to as NMOS logic.
n-type MOSFETs are active (conductive) when their input voltage is high, while p-type MOSFETs are active when their input voltage is low.
All CMOS gates are arranged in two parts: the pull-up network (PUN), built from p-type transistors and connect to source; and the pull-down network (PDN), built from n-type transistors and connected to ground (also called drain). The two parts are logical duals of each other, so that if the PUN is active, then the PDN is inactive, and vice-versa. In this way there can never be a direct path between source and ground (in any steady state).
The biggest advantage of CMOS over NMOS is that CMOS has a rapid change from both hi-to-low and from low-to-hi. NMOS transitions only slowly from low-to-hi (because it uses a resistor in place of a PUN), and since overall circuit speed must take into account the worst case, NMOS circuits must be much slower.

## Logic Gates
### NOT

The simplest CMOS circuit: the NOT gate, or inverter. Although uncomplicated, it demonstrates the basic structure of a CMOS gate; a series of inputs (in this case, one) which are connected to the transistors, the PUN (consisting of a single p-type transistor) connected to source, the PDN (consisting of a single n-type transistor) connected to ground, and the output which is fed from both the PUN and PDN.
When the input voltage is high, the p-type transistor will be inactive, and the n-type transistor will be active. This creates a connection between ground and the gate output, pulling the gate's output to low. Conversely, when the input voltage is low, the p-type transistor will be active instead, creating a connection between the output and source, pulling the gate's output to high.
| Input | Output |
| 0 | 1 |
| 1 | 0 |

### NAND

The PUN for NAND consists of a pair of p-type transistors in parallel, one with the A input feeding it and one with the B input feeding it. Therefore the PUN is active, and the output of the gate is high, as long as either of these inputs is low.
The PDN for NAND consists of a pair of n-type transistors in series, also each fed by one of the two inputs. Therefore the PDN is active, and the output of the gate is low, only if both of the inputs are high.it uses the logic a bar(OR)b bar
| Input 1 | Input 2 | Output |
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |

### AND

A CMOS AND gate is constructed by driving a NOT gate from the output of a NAND gate.
| Input 1 | Input 2 | Output |
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |

### NOR

"Upside down" relative to the NAND gate, the NOR gate is made from a PUN of two p-type transistors in series and a PDN of two n-type transistors in parallel.
| Input 1 | Input 2 | Output |
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |

### OR

As AND is to NAND, OR is to NOR. CMOS OR is constructed by feeding the output of NOR to a NOT gate.
| Input 1 | Input 2 | Output |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |

### XNOR

To build an XNOR gate, first we will need easy access to the inverted inputs. This is accomplished with a pair of NOT gates. The original inputs are A and B, and their inverted forms we will call NOT-A and NOT-B. Both the PUN and PDN are made of four of the appropriate type of transistor, in two parallel sets, of series of two transistors each. In the PUN there is one series fed by A and B and the other is fed by NOT-A and NOT-B; in the PDN one series is fed by A and NOT-B and the other is fed by NOT-A and B.
All told, this takes 12 transistors (4 in the PUN, 4 in the PDN, and 2 for each inverter). There are more efficient designs for the XNOR circuit, but they require a more detailed analysis than we will go into here. Instead of serving as an example of an actual XNOR design, this section should instead help to suggest the methods one could use to generate a CMOS circuit for any arbitrary boolean function.
| Input 1 | Input 2 | Output |
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |

### XOR

If you've been following along, you may guess that an XOR gate is made by attaching a NOT onto the end of the XNOR; while this will produce a correct circuit, it is not the most correct (or efficient) circuit. Instead, we could use the same 12 transistors and simply shuffle around the wires. This is left as an exercise for the reader. it uses the logic a.b bar(OR) a bar.b
| Input 1 | Input 2 | Output |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |