OpenLLM-France/wikimedia huggingface dataset:
# Modern C++: The Good Parts/Number crunching

The machine in front of you is really just a very fancy calculator, so let's make it calculate.

## Explanation

So first we have a std::string variable named "input" and two int variables named "a" and "b". An int is an integer or whole number, so it can't have a decimal point.
Important: The = (equals sign) does not mean equality. In C++ it's the assignment operator; it puts the value on the right into the variable on the left, overwriting any previous value of that variable.
std::stoi is a function, and the name stands for string to int. It takes a string (in this case, the value of input) and converts it to an integer. If this isn't possible, or you enter a very large number, the program will crash and you'll probably see something about an "unhandled exception". How to prevent this issue will be addressed a few chapters later.
You can read about std::stoi at cplusplus.com or cppreference.com. It has some friends, too.
The multiplication operator in C++ is * (asterisk). Division is / (forward slash).
Try entering 3.14 as one of the integers. Oops! std::stoi finds the valid integer 3 and ignores the invalid input after it. You'll get the same result for 3sdjgh. The next few chapters should allow you to write a better integer parser.

## Exercises

* Modify the above program so it accepts decimal points (floating-point numbers or float values). Hint: Check the links on this page.

## Vocabulary
### int

    an integer or "whole number". Cannot represent fractions.

### assignment operator

    puts the value on the right into the variable on the left, overwriting any previous value of that variable. Syntax: =

### function

    a named piece of code. More on these later.

### float

    a floating-point number or "decimal number". (That last one is a little confusing.) Can represent some fractions.
# Modern C++: The Good Parts/Switching things up

In the previous chapter, you received your first assignment: to write a simple calculator. At the time, if statements were your only way to make a decision; this chapter introduces the switch statement, which works similarly to the if statement but is more suited to problems like the calculator.

## Code

Here's a calculator built around a switch statement:

## Explanation

std::stof is similar to std::stoi, except it converts to float.
input[0] is the first character in the string input. Anytime you see square brackets with a number (or variable) between them, the number is zero-based. This means that what people normally call the "first" character is at index 0, the "second" is at index 1, and so forth.
The switch statement has exactly the same effect as the if-else chain you wrote for your own calculator. Notice that every case label has a matching break statement; be careful that this is true of any switch statement you write, because otherwise you might get some very surprising behavior. Specifically, without a break statement, control will flow right past any labels, causing the logic under them to be executed in multiple cases.

## Exercises

* Explore what happens when you divide one int by another, and how that differs from doing the same with two floats, and an int and a float. Discuss your findings with your instructor.

## Vocabulary
### switch statement

    uses its expression to select which case label to jump to.
# Modern C++: The Good Parts/The world's response

Now, let's allow the world to return the greeting.

## Explanation

We have a few new things here.
std::string means that input is a string variable. A variable is a named place in memory to store information. Since it's named, you can refer to it again and again, to put something there or to see what's already there. And as a string variable it can store text - and only text. Other kinds of variables exist, and we'll cover some of those in the next chapter.
// is a line comment, which means everything after it on the same line will be ignored by the compiler.
std::cin has an arrow that points in the opposite direction from the arrows of std::cout, because information is flowing in the opposite direction.
After "The world says: ", there's another arrow, and then another. This just appends more text to the output.

## Exercises

* Extend the conversation between your program and the "world". Don't bother with whether the program is responding correctly to what is typed.

## Vocabulary
### variable

    a named place in memory to store information.

### line comment

    causes the compiler to ignore the rest of a line. Syntax: //
# Modern Greek/A1/Exercises/Lesson 1

Welcome to the exercises related to Lesson 02.2.
Click "▼" to check your answers.

## Hello!

How would you respond to:

## How are you?

Arrange the following in best to worst.

## Greetings

Translate the following Greek sentences into English:
Translate the following English sentences into Greek:

## Dialogue

Try translating the following dialogue:

## Next steps

* If you would like, review this lesson: Lesson 1
* Otherwise, continue to the next lesson: Lesson 2
Contents Lesson 1 • Lesson 2 • Lesson 3 • Lesson 4 • Lesson 5 • Lesson 6 • Lesson 7 • Lesson 8 • Lesson 9 • Lesson 10 Vocab 1 • Vocab 2 • Vocab 3 • Vocab 4 • Vocab 5 • Vocab 6 • Vocab 7 • Vocab 8 • Vocab 9 Alphabet • Grammar Credits
# Test Bench Design

The purpose of a good test bench is to create an accurate, automated, and controlled environment to test a digital logic design in. Increased accuracy in a test bench allows the nuances of the design functionality to be verified, tested, and debugged with the help and visibility of a simulator. Automation in a test bench allows design changes to be tested quickly and easily and provides the facilities for easy regression testing to help obtain design confidence. The control provided by a test bench allows the testing of particular corner cases that are hard to create in a lab setting and allows the concentration of testing a particular part of a design.
The main disadvantage of test bench testing is speed. Simulating digital logic designs often requires the use of complicated hardware models for microcontrollers and communication interfaces. These situations often come up in high bandwidth applications (video). Since test bench design can often take as long (or longer) than the design itself, the ability to scale your test data and test bench to test part of a design are often necessary evils depending on the schedule and budgeting constraints of a project.

## "Ideal" Testbenches

The figure below shows a block diagram of an “ideal” test bench (if one was designing with unlimited budget, time, and has perfect specifications for the design).
In this design, the “testbench” itself is merely a module without any external interfaces that instantiates the many modules that make up the modules that do the actual testing. The wrapper testbench and all the testing modules that make up the test bench (everything except the design to be tested) are often collectively referred to as a testbench. Often instantiated in a test bench wrapper is the design to be tested, external interface models, test data generators, signal verification modules, and a control module that controls the external interface modules and reports information to the user.
Ideally, the only interfaces to the design under test are the external interface models. This allows the design to be controlled and communicated with as it would be when implemented on an actual chip on a circuit card. Although cumbersome sometimes, this allows interface and control issues in a design to be identified and corrected earlier in the design process and with the help of a simulator for debugging.
# Programmable Logic/SystemC

This page of the Programmable Logic book is a stub. You can help by expanding it.

#### SystemC

* System C Library
* System C Data Types
* System C Library
* System C Operators
* System C Functions
* Object Oriented Design
* Dynamic Memory Allocation
# Programmable Logic/Programmable Hardware

This page is going to discuss what exactly programmable hardware is.

## VLSI

VLSI stands for "Very-Large-Scale Integration", and is the term for a number of different chip architectures that are integrated (many components on a single chip), and are usable for a variety of different purposes. Some more modern chips are referred to as ULSI (U = "Ultra"), but VLSI and ULSI are essentially the same thing.
VLSI (Very Large Scale Integration) refers to integrated circuits with over approximately one hundred thousand transistors. Currently chips with many millions of transistors are sometimes referred to as ULSI (Ultra Large Scale Integration), however the complexity of the designs are approximately the same as VLSI.

## Basic process technology types

| Name | Description |
| Antifuse | One-time programmable. CMOS. |
| EEPROM | Electrically Erasable Programmable Read-Only Memory technology. Can be erased, even in plastic packages. Some, but not all, EEPROM devices can be in-system programmed. CMOS. |
| EPROM | Erasable Programmable Read-Only Memory technology. Usually one-time programmable in production because of plastic packaging. Windowed devices can be erased with ultraviolet (UV) light. CMOS. |
| Flash | Flash-erase EPROM technology. Can be erased, even in plastic packages. Some, but not all, flash devices can be in-system programmed. Usually, a flash cell is smaller than an equivalent EEPROM cell and is therefore less expensive to manufacture. CMOS. |
| Fuse | One-time programmable. Bipolar. |
| SRAM | based on static memory technology. In-system programmable and re-programmable. Requires external boot devices. CMOS. |
# Programmable Logic/Tools
## Design

* XILINX Vivado
* XILINX ISE WebPACK (Discontinued - Legacy software)

## Simulation

* Icarus Verilog (Wikipedia article)
* ModelSim
* XILINX ISE WebPACK

## Synthesis

* XILINX ISE WebPACK

## Implementation

* XILINX ISE WebPACK
# Programmable Logic/Terminology
## Acronyms Used in this Book

| Acronym | Expansion |
| CPLD | Complex Programmable Logic Device |
| FPGA | Field Programmable Gate Array |
| FPOA | Field Programmable Object Array |
| GAL | Generic Array Logic |
| HDL | Hardware Description Language |
| ILA | Integrated Logic Analyzer |
| IP | Intellectual Property |
| JTAG | Joint Test Action Group |
| PAL | Programmable Array Logic |
| PLD | Programmable Logic Device |
| RTL | Register Transfer Level |
| VHDL | VHSIC Hardware Description Language |
| VHSIC | Very High Speed Integrated Circuit |
# Programmable Logic/Timing and Synchronization

In microprocessor-based software systems, instructions are performed sequentially. Each instruction is allowed to complete before the following instruction may begin. Even in situations where this is not strictly the case, such as pipelined and superscalar processors, the changes to this pattern are transparent to the programmer and can essentially be ignored.
In programmable logic, however, this is the case. Instructions can neither be expected to occur in a particular timeframe, nor in a particular order. Verilog and VHDL both contain constructs to force certain synchonization, although these constructs may carry with them a performance penalty.
Typically, a hardware design should have a clock signal that all the various modules have access to. Actions that occur in response to the clock signal are known as synchronous, and actions that occur without the clock signal are known as asynchronous. Furthermore, through the use of clock multipliers, different modules in a design can be moving at different speeds. Needless to say, timing and synchronization can be very important problems to solve for a hardware designer.
# Pro Engineer/Drawing Repeat Regions - Report Symbols

http://communities.ptc.com/message/251390#251390 (external link)
see http://communities.ptc.com/message/247301#247301 (external link)
Alternate listing (they need to be combined into a single table.)
# Pro Engineer/Drawings

* Pro Engineer/Drawings - Drawing Programs
* Pro Engineer/Drawings - Dimensions
* Pro Engineer/Drawings - Drawing Configuration aka setup, *.dtl
* Pro Engineer/Drawings - Formats
* Pro Engineer/Drawings - Notes
* Pro Engineer/Drawings - Repeat Regions
* Pro Engineer/Drawings - Symbols
* Pro Engineer/Drawings - Tables
* Pro Engineer/Drawings - Views
# Pro Engineer/Drawing Repeat Regions - Relations - Examples

* Repeat Region Relation Example: Replacing characters in parameters
* Convert String to Number using Relations
# Pro Engineer/Detail FAQ
## FAQ - Detail

How do I display PCD centrelines for radial pattern holes? In detail mode - Advanced, Setup, Modify Val. Find the entry RADIAL_PATTERN_AXIS_CIRCLE and set the value to YES File, Exit and repaint the screen to see changes. Note: This only works for pattern of holes defined using the radial type holes, where the dimension type is set to diameter when created not radius.
How do I change the size of datum points? In detail mode - Advanced, Setup, Modify Val. Find the entry DATUM_POINT_SIZE and set the value (value is in inches) e.g. 3 is 3 inches not 3 mm File, Exit and repaint the screen to see changes.
How do I change the shape of datum points? In detail mode - Advanced, Setup, Modify Val. Find the entry DATUM_POINT_SIZE and set the value to one of the following CROSS, DOT, CIRCLE, TRIANGLE, or SQUARE. File, Exit and repaint the screen to see changes.
How do you blank items on layers in assemblies/parts in the drawing? Assuming the assemblies use default layers or the features to blank are on layers. Create a layer in the drawing with exactly the same name. When it is blanked it will effectively blank all features on the chosen layers in all components in the assembly.
How do include symbols in notes? Create the note as normal at the location where the note is required type &sym(name) where name is the name of the symbol. You will need retrieve the symbol so it is part of the drawing before this will work.
How do I create a PLUS-PLUS tolerance? Use Modify, Value pick the negative tolerance and add a minus sign in front of the value e.g 0.2 becomes -0.2 hit enter and Pro/Engineer will now show a plus-plus tolerance. This is because Pro/Engineer stores the integer as a positive value and applies a negative value to it, making the tolerance value negative creates a positive (two negatives = a positive).
What are the curly brackets that appear when editing notes? A typical note will appear as below when editing
{0: First line of note}
{1: Second line of note}
The brackets and number control the text formatting. If you delete the number or the colon then the text line will return to default text formatting values.
# Pro Engineer/Family Table Tips

Name Features
Name features/ dimensions used on family tables. This makes the family table easier to understand and modify.
Automatic Suppression
Suppressing a feature or component using family table will suppress all children automatically.
Create features in instances
Creating features in an instance will automatically suppress the feature/ component in the generic and add the items to the family table.
Don't use the generic as an instance
Create an instance for each model required e.g one for casting, one for machining: avoid creating one instance (machining) and then using the generic as the casting instance.
Tolerances can be added to family table
Display tolerances, Family Table, Add Item, Dimension pick the required dimension and the tolerance figures.
Add parameters instead of dimensions
Adding parameters to the family table instead of dimension enable you to drive many dimensions/ features from a single column in the family table. e.g. a bolt family with different bolt heads, the thickness of the head can be driven by one parameter (head_thickness) instead of adding a dimension for each type of bolt head. Each bolt head thickness dimension has the relation d**=head_thickness.
Patterns
Complex features such as patterns can be added either by adding individual pattern dimensions or by adding pattern tables to the family table.
Reduce generic part load time
If a feature/component is only used in a few instances suppress that feature/component in the generic to reduce load/regeneration times. Generic assemblies could have all components suppressed in the generic. Parts can also have all features suppressed in the generic. Features and components are then added at the instance level.
Create the family table at the end
Each instance has to be regenerated after certain operations, this can cause long regenerations. Complete the majority of features before constructing the family table.
Verify
Always verify a family table before saving to Intralink. Intralink will issue a warning if instances are not verified
Don't leave default values in family table
Fill in all values do not leave * (the * denotes the value will be the same as the generic) in the family table otherwise instances may change unintentionally when the generic is modified.
Reorder Features
Reorder the features that change via the family table to be as late as possible in the model tree - this will improve performance and regeneration.
# Pro Engineer/Create Features/Revolve

Revolve is a command which revolves an entity about an axis to form a 3D object or model. Model can either be surface model or solid model. For example - If you revolve a line around an axis parallel to it at some distance apart(say x) it will form a cylinder of radius 'x'.
# Pro Engineer/Drawing Repeat Regions - Relations

Pro Engineer/Drawing Repeat Regions - Relations - Examples
# Pro Engineer/Design Intent
## Why Learn Design Intent?

Pro/Engineer [also: Solidworks & Autodesk:Inventor] is a parametric modeler. That means that features can be related to one another in a number of different ways. These relationships govern how the model will behave when changed. Design intent is the careful control of these relationships so that they correctly govern the intended behavior of the model. With good design intent, models can be updated almost effortlessly. Changes made to one aspect of a model propagate appropriately through the model, assembly, and drawing. With poor design intent, features may update inappropriately, or fail.
Design intent builds intelligence into the model.

## Ways to control design intent
### Part model references

The first way to control design intent in a Pro/Engineer model is simply to select references appropriately when modeling a part. Except for the default datum plane, every feature must reference something else. You create a reference when you choose a sketching plane or any sketcher reference.

#### Reference stable features for stability

* Use datum planes as a baseline. Solid features may change. For instance, a hole referencing an edge may fail when a round or chamfer is created on that edge. A hole referencing a face may fail when a draft is created on that face.
* When using solid features as references, choose more stable features. That is, reference faces before edges and edges, when necessary, before vertices.
* Create a base feature with the basic shape of a part. Use its features
* Use the model tree and Insert Here functionality to control feature order.
* Features can only reference other features that occur earlier in the model tree. Features cannot reference subsequent features.

#### Model for design intent

* When choosing references, ask how the model might change. Should a hole stay centered on the part? Should it remain a fixed distance from some face or edge? Should it move with an associated feature, such as a boss?
* Consider the full range of possible changes. Will a drastic change in a dimension make a sketch impossible to resolve, for instance by turning it inside-out?
# Programming Languages/Domain-specific Languages
## Domain-Specific Languages

[TODO: Talk about w:SQL, w:Lex, w:Yacc, and answer why these languages are so commonly used, even though general purpose languages can do the same.]
# Programming Languages/Imperative Languages
## Imperative Languages
### Some common examples

    C, Algol family of languages, Pascal.

### More on "Imperative programming"

    in wikibooks and in wikipedia.
# Programming Languages/Syntax Specification

There are two ways to describe a language: by its syntax or by its semantics. The syntax of a language is a set of rules that defines what strings of characters (sentence or statements) belong to this language; the semantics of a language describe the meaning of a given statement.

## Specifying the Syntax of Programming Languages
### Lexemes and Tokens

For a language, one can decompose a statement into a string of lexemes, the indecomposable building blocks of a language. For example, the following w:Perl statement:
contains lexemes: do, {, sleep, 1, ;, }, while, (, ++, $i, <, 10, ) and ;.
Lexemes can be grouped into categories. Such a category is called a token.

### Context-Free Grammars

* Backus-Naur Form(BNF)
* Arithmetic grammar
* Unary negation (~)

### Parse Trees

* Parse tree of complex formula using exponents, et cetera

### Extended Backus-Naur Form

Extended Backus-Naur Form is intended to be a precise method for specifying the syntax of a language. It is a metalanguage, in that it is a language used to describe languages. It is also commonly seen employed in command usage or help documents.
The complete documentation on EBNF is to be found here: .
The basic elements of a language would be described using EBNF terminal symbols, which are then grouped together into logical higher-level expressions of the overall language using nonterminal symbols. Terminal symbols specify actual valid character patterns used to represent things like the proper syntax for variable names in the language, or for representing numbers. Nonterminal symbols group the different possible representations of a given thing (say, numerical constants in decimal, hexadecimal or scientific notation format) into a single logical thing ([Numerical_Constant]). Ultimately, by building up the various syntactical elements and expressing the ways in which they may be combined, one ends up with a symbol representing a program in the language in question.
A couple of examples are to be found in the man pages for the awk utility.
(excerpts are from )
First, its usage:
    awk [ -F fs ] [ -v var=value ] [ 'prog' | -f progfile ] [ file ... ]
The items in square brackets are an example of EBNF and denote an optional parameter to use on the awk command line.
Secondly, the usage detail section is partially specified in EBNF.
In the example below, words such as 'pattern', 'action', 'expression' and 'statement' are EBNF nonterminal symbols.
A pattern-action statement has the form
A missing { action } means print the line; a missing pattern always matches. Pattern-action statements are separated by newlines or semicolons.
An action is a sequence of statements. A statement can be one of the following:
Statements are terminated by semicolons, newlines or right braces.
Entire languages can also be documented in EBNF. The link below documents the ANSI definition of C++, and many parts of this document are written in EBNF.
# Programming Languages/Logical Languages
## Logical Languages

Logic programming languages such as Prolog state and query relations. The specifics of how these queries are answered is up to the implementation and its theorem prover, but typically take the form of some sort of unification.