# Embedded Systems/ARM Assembly Language

ARM Instruction Set Format :
| Instruction | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADC | Cond | Cond | Cond | Cond | 0 | 0 | I | 0 | 1 | 0 | 1 | S | Rn | Rn | Rn | Rn | Rd | Rd | Rd | Rd | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand |
| ADD | Cond | Cond | Cond | Cond | 0 | 0 | I | 0 | 1 | 0 | 0 | S | Rn | Rn | Rn | Rn | Rd | Rd | Rd | Rd | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand |
| AND | Cond | Cond | Cond | Cond | 0 | 0 | I | 0 | 0 | 0 | 0 | S | Rn | Rn | Rn | Rn | Rd | Rd | Rd | Rd | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand |
| B, BL | Cond | Cond | Cond | Cond | 1 | 0 | 1 | L | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 |
| BIC | Cond | Cond | Cond | Cond | 0 | 0 | I | 1 | 1 | 1 | 0 | S | Rn | Rn | Rn | Rn | Rd | Rd | Rd | Rd | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand |
| BKPT | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | immed | immed | immed | immed | immed | immed | immed | immed | immed | immed | immed | immed | 0 | 1 | 1 | 1 | immed | immed | immed | immed |
| BLX (1) | 1 | 1 | 1 | 1 | 1 | 0 | 1 | H | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 | signed_immed_24 |
| BLX (2) | Cond | Cond | Cond | Cond | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | SBO | SBO | SBO | SBO | SBO | SBO | SBO | SBO | SBO | SBO | SBO | SBO | 0 | 0 | 1 | 1 | Rm | Rm | Rm | Rm |
| BX | Cond | Cond | Cond | Cond | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | SBO | SBO | SBO | SBO | SBO | SBO | SBO | SBO | SBO | SBO | SBO | SBO | 0 | 0 | 0 | 1 | Rm | Rm | Rm | Rm |
| CDP | Cond | Cond | Cond | Cond | 1 | 1 | 1 | 0 | opcode_1 | opcode_1 | opcode_1 | opcode_1 | CRn | CRn | CRn | CRn | CRd | CRd | CRd | CRd | cp_num | cp_num | cp_num | cp_num | opcode_2 | opcode_2 | opcode_2 | 0 | CRm | CRm | CRm | CRm |
| CLZ | Cond | Cond | Cond | Cond | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | SBO | SBO | SBO | SBO | Rd | Rd | Rd | Rd | SBO | SBO | SBO | SBO | 0 | 0 | 0 | 1 | Rm | Rm | Rm | Rm |
| CMN | Cond | Cond | Cond | Cond | 0 | 0 | I | 1 | 0 | 1 | 1 | S | Rn | Rn | Rn | Rn | SBZ | SBZ | SBZ | SBZ | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand |
| CMP | Cond | Cond | Cond | Cond | 0 | 0 | I | 1 | 0 | 1 | 0 | S | Rn | Rn | Rn | Rn | SBZ | SBZ | SBZ | SBZ | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand | shifter operand |
| LDC | Cond | Cond | Cond | Cond | 1 | 1 | 0 | P | U | N | W | 1 | Rn | Rn | Rn | Rn | CRd | CRd | CRd | CRd | cp_num | cp_num | cp_num | cp_num | 8_bit_word_offset | 8_bit_word_offset | 8_bit_word_offset | 8_bit_word_offset | 8_bit_word_offset | 8_bit_word_offset | 8_bit_word_offset | 8_bit_word_offset |
| LDM (1) | Cond | Cond | Cond | Cond | 1 | 0 | 0 | P | U | 0 | W | 1 | Rn | Rn | Rn | Rn | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list |
| LDM (2) | Cond | Cond | Cond | Cond | 1 | 0 | 0 | P | U | 1 | 0 | 1 | Rn | Rn | Rn | Rn | 0 | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list |
| LDM (3) | Cond | Cond | Cond | Cond | 1 | 0 | 0 | P | U | 1 | W | 1 | Rn | Rn | Rn | Rn | 1 | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list | register_list |
| LDR | Cond | Cond | Cond | Cond | 0 | 1 | I | P | U | 0 | W | 1 | Rn | Rn | Rn | Rn | Rd | Rd | Rd | Rd | addr_mode | addr_mode | addr_mode | addr_mode | addr_mode | addr_mode | addr_mode | addr_mode | addr_mode | addr_mode | addr_mode | addr_mode |
We go into more detail on how to use ARM assembly language in ARM Microprocessors.