# Embedded Systems/ARM Instructions

ARM Instruction Set Format :
| Instruction Type | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Branch and Branch with Link | Cond | Cond | Cond | Cond | 1 | 0 | 1 | L | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset |
| Branch and Branch with Link and eXchange | Cond | Cond | Cond | Cond | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | L | 1 | Rm | Rm | Rm | Rm |
| Branch and Branch with Link and eXchange | 1 | 1 | 1 | 1 | 1 | 0 | 1 | H | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset | 24-bit signed word offset |
| Software Interrupt (SWI) | Cond | Cond | Cond | Cond | 1 | 1 | 1 | 1 | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate | 24-bit (interpreted) immediate |
| Data Processing Instructions | Cond | Cond | Cond | Cond | 0 | 0 | I | opcode | opcode | opcode | opcode | S | Rn | Rn | Rn | Rn | Rd | Rd | Rd | Rd | operand2 | operand2 | operand2 | operand2 | operand2 | operand2 | operand2 | operand2 | operand2 | operand2 | operand2 | operand2 |
| Multiply Instructions | Cond | Cond | Cond | Cond | 0 | 0 | 0 | 0 | mul | mul | mul | S | Rd/RdHi | Rd/RdHi | Rd/RdHi | Rd/RdHi | Rn/RdLo | Rn/RdLo | Rn/RdLo | Rn/RdLo | Rs | Rs | Rs | Rs | 1 | 0 | 0 | 1 | Rm | Rm | Rm | Rm |
| Count Leading Zeros | Cond | Cond | Cond | Cond | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | Rd | Rd | Rd | Rd | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Rm | Rm | Rm | Rm |
| Data Transfer Instructions | Cond | Cond | Cond | Cond | 0 | 1 | I | P | U | B | W | L | Rn | Rn | Rn | Rn | Rd | Rd | Rd | Rd | operand2 | operand2 | operand2 | operand2 | operand2 | operand2 | operand2 | operand2 | operand2 | operand2 | operand2 | operand2 |
| Data Transfer Instructions | Cond | Cond | Cond | Cond | 0 | 0 | 0 | P | U | I | W | L | Rn | Rn | Rn | Rn | Rd | Rd | Rd | Rd | offsetH | offsetH | offsetH | offsetH | 1 | S | H | 1 | offsetL | offsetL | offsetL | offsetL |
| Multiple Register Transfer Instructions | Cond | Cond | Cond | Cond | 1 | 0 | 0 | P | U | S | W | L | Rn | Rn | Rn | Rn | register list | register list | register list | register list | register list | register list | register list | register list | register list | register list | register list | register list | register list | register list | register list | register list |
| Swap Memory and Register Instruction | Cond | Cond | Cond | Cond | 0 | 0 | 0 | 1 | 0 | B | 0 | 0 | Rn | Rn | Rn | Rn | Rd | Rd | Rd | Rd | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | Rm | Rm | Rm | Rm |
| Status Register <=> General Register Transfer Instructions | Cond | Cond | Cond | Cond | 0 | 0 | 0 | 1 | 0 | R | 0 | 0 | 1 | 1 | 1 | 1 | Rd | Rd | Rd | Rd | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Status Register <=> General Register Transfer Instructions | Cond | Cond | Cond | Cond | 0 | 0 | I | 1 | 0 | R | 1 | 0 | field | field | field | field | 1 | 1 | 1 | 1 | operand | operand | operand | operand | operand | operand | operand | operand | operand | operand | operand | operand |
| Coprocessor Data Operations | Cond | Cond | Cond | Cond | 1 | 1 | 1 | 0 | Cop1 | Cop1 | Cop1 | Cop1 | CRn | CRn | CRn | CRn | CRd | CRd | CRd | CRd | CP# | CP# | CP# | CP# | Cop2 | Cop2 | Cop2 | 0 | CRm | CRm | CRm | CRm |
| Coprocessor Data Transfers | Cond | Cond | Cond | Cond | 1 | 1 | 0 | P | U | N | W | L | Rn | Rn | Rn | Rn | CRd | CRd | CRd | CRd | CP# | CP# | CP# | CP# | 8-bit offset | 8-bit offset | 8-bit offset | 8-bit offset | 8-bit offset | 8-bit offset | 8-bit offset | 8-bit offset |
| Coprocessor Register Transfers | Cond | Cond | Cond | Cond | 1 | 1 | 1 | 0 | Cop1 | Cop1 | Cop1 | L | CRn | CRn | CRn | CRn | Rd | Rd | Rd | Rd | CP# | CP# | CP# | CP# | Cop2 | Cop2 | Cop2 | 1 | CRm | CRm | CRm | CRm |
| Breakpoint Instruction | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | x | x | x | x | x | x | x | x | x | x | x | x | 0 | 1 | 1 | 1 | x | x | x | x |
We go into more detail on how to use ARM instructions in ARM Microprocessors.