# Electronics/Flip Flops
## Flip Flop

A flip-flop is a device very like a latch in that it is a bistable multivibrator, having two states and a feedback path that allows it to store a bit of information. The difference between a latch and a flip-flop is that a latch is asynchronous, and the outputs can change as soon as the inputs do (or at least after a small propagation delay). A flip-flop, on the other hand, is edge-triggered and only changes state when a control signal goes from high to low or low to high. This distinction is relatively recent and is not formal, with many authorities still referring to flip-flops as latches and vice versa, but it is a helpful distinction to make for the sake of clarity.
There are several different types of flip-flop each with its own uses and peculiarities. The four main types of flip-flop are : SR, JK, D, and T.

### SR Latch

An SR latch (Set/Reset) is an asynchronous device: it works independently of control signals and relies only on the state of the S and R inputs. In the image we can see that an SR latch can be created with two NOR gates that have a cross-feedback loop. SR latches can also be made from NAND gates, but the inputs are swapped and negated. In this case, it is sometimes called an SR latch.
| S | R | Q | Q |
| 0 | 0 | Latch | Latch |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | Metastable | Metastable |
When a high is applied to the Set line of an SR latch, the Q output goes high (and Q low). The feedback mechanism, however, means that the Q output will remain high, even when the S input goes low again. This is how the latch serves as a memory device. Conversely, a high input on the Reset line will drive the Q output low (and Q high), effectively resetting the latch's "memory". When both inputs are low, the latch "latches" – it remains in its previously set or reset state.
When both inputs are high at once, however, there is a problem: it is being told to simultaneously produce a high Q and a low Q. This produces a "race condition" within the circuit - whichever gate succeeds in changing first will feedback to the other and assert itself. Ideally, both gates are identical and this is "metastable", and the device will be in an undefined state for an indefinite period. In real life, due to manufacturing methods, one gate will always win, but it's impossible to tell which it will be for a particular device from an assembly line. The state of S = R = 1 is therefore "illegal" and should never be entered.
When the device is powered up, a similar condition occurs, because both outputs, Q and Q, are low. Again, the device will quickly exit the metastable state due to differences between the two gates, but it's impossible to predict which of Q and Q will end up high. To avoid spurious actions, you should always set SR latch to a known initial state before using them - you must not assume that they will initialize to a low state.
Characteristic table :
| S | R | Q$_{next}$ | Comment |
| 0 | 0 | 0 | Hold state |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | Metastable | Metastable |
Excitation table :
| Q | Q$_{next}$ | S | R |
| 0 | 0 | 0 | X |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | X | 0 |

## Gated Latches
### Gated SR latch

In some situations it may be desirable to dictate when the latch can and cannot latch (change value). The gated SR latch is a simple extension of the SR latch which provides an Enable line which must be driven high before data can be latched. Even though a control line is now required, the SR latch is not synchronous, because the inputs can change the output even in the middle of an enable pulse - i.e. if the input keeps changing while the Enable pin is high, the output will keep changing until the Enable pin goes to low.
When the Enable pin input is low, the outputs from the AND gates must also be low, leaving the Q and Q outputs latched to the previous data. Only when the enable input is high can the state of the latch change, as shown in the truth table. When the enable line is high (asserted), a gated SR latch is identical in operation to an SR latch.
The Enable line is sometimes a clock signal, but is usually a read or write strobe.
    EnableSR QQ 000Latch 001Latch 010Latch 011Latch 100Latch 10101 11010 111Metastable

### Gated D latch

The D latch (D for "data") or transparent latch is a simple extension of the gated SR latch that removes the possibility of invalid input states.
Since the gated SR latch allows us to latch the output without using the S or R inputs, we can remove one of the inputs by driving both the Set and Reset inputs with a complementary driver: we remove one input and automatically make it the inverse of the remaining input.
The D latch outputs the D input whenever the Enable line is high, otherwise the output is whatever the D input was when the Enable input was last high. This is why it is also known as a transparent latch: when Enable is asserted, the D input propagates directly through the latch as if it wasn’t there.
    EnableD QQ 00Latch 01Latch 1001 1110
D latches are often used in I/O ports of integrated circuits and are available as discrete devices, often multiply packaged. An example is the 74HC75, part of the 7400 series of ICs, containing four separate D latches.

## Clock - Controlled Flip Flops
### D flip-flop

The D flip-flop is the edge-triggered variant of the transparent latch. On the rising (usually, although falling or negative edge triggering is equally possible) edge of the clock, the value of the D input at that moment is expressed at the output. The output can only change at the clock edge: if the input changes at other times, the output will be unaffected.
D flip-flops are by far the most common type of flip-flops and some devices (for example some FPGAs) are made entirely from D flip-flops. They are also commonly used for shift-registers and input synchronisation.
    ClockDQ$_{next}$Comment 00Express D at Q 11Express D at Q OtherwiseXQ$_{prev}$Hold state

### JK Flip-flop

The JK flip-flop is a simple enhancement of the SR flip-flop where the state J=K=1 is not forbidden. It works just like a SR FF where J is serving as set input and K serving as reset. The only difference is that for the formerly “forbidden” combination J=K=1 this flip-flop now performs an action: it inverts its state. As the behavior of the JK flip-flop is completely predictable under all conditions, this is the preferred type of flip-flop for most logic circuit designs. But there is still a problem i.e. both the outputs are same when one tests the circuit practically. This is because of the internal toggling on every propagation elapse completion. The main remedy is going for master-slave jk flip-flop, this ff overrides the self(internal) recurring toggling through the pulsed clocking feature incorporated.
Characteristic table :
| J | K | Q$_{next}$ | Comment |
| 0 | 0 | Q$_{prev}$ | Hold state |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | Q$_{prev}$ | Toggle |
Excitation table :
| Q | Q$_{next}$ | J | K | Comment |
| 0 | 0 | 0 | X | Hold state |
| 0 | 1 | 1 | X | Set |
| 1 | 0 | X | 1 | Reset |
| 1 | 1 | X | 0 | Hold state |

### T flip-flops

A T flip-flop is a device which swaps or "toggles" state every time it is triggered if the T input is asserted, otherwise it holds the current output. This behavior is described by the characteristic equation:
       $Q_{next}=T\oplus Q=T{\overline {Q}}+{\overline {T}}Q$
and can be described either of the following tables:
Characteristic table :
| T | Q | Q$_{next}$ | Comment |
| 0 | 0 | 0 | Hold state |
| 0 | 1 | 1 | Hold state |
| 1 | 0 | 1 | Toggle |
| 1 | 1 | 0 | Toggle |
Excitation table :
| Q | Q$_{next}$ | T |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
When T is held high, the toggle flip-flop divides the clock frequency by two; that is, if clock frequency is 4 MHz, the output frequency obtained from the flip-flop will be 2 MHz. This 'divide-by' feature has application in various types of digital counters. A T flip-flop can also be built using a JK flip-flop (J & K pins are connected together and act as T) or D flip-flop (T input and Q$_{prev}$ are connected to the D input through an XOR gate).