# 10 nm process

In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the "10 nanometer process" as the MOSFET technology node following the "14 nm" node.
Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit; neither gate length, metal pitch or gate pitch on a "10nm" device is ten nanometers. For example, GlobalFoundries' "7 nm" processes are dimensionally similar to Intel's "10 nm" process. TSMC and Samsung's "10 nm" processes are somewhere between Intel's "14 nm" and "10 nm" processes in transistor density. The transistor density (number of transistors per square millimetre) is more important than transistor size, since smaller transistors no longer necessarily mean improved performance, or an increase in the number of transistors.
All production "10 nm" processes are based on FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology that is a non-planar evolution of planar silicon CMOS technology. Samsung first started their production of "10 nm-class" chips in 2013 for their multi-level cell (MLC) flash memory chips, followed by their SoCs using their 10 nm process in 2016. TSMC began commercial production of "10 nm" chips in 2016, and Intel later began production of "10 nm" chips in 2018.

## Background

The ITRS's original naming of this technology node was "11 nm". According to the 2007 edition of the roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM was projected to be 11 nm.
In 2008, Pat Gelsinger, at the time serving as Intel's Chief Technology Officer, said that Intel saw a 'clear way' towards the "10 nm" node.
In 2011, Samsung announced plans to introduce the "10 nm" process the following year. In 2012, Samsung announced eMMC flash memory chips that are produced using the "10 nm" process.
As of 2018, "10 nm" as it was generally understood was only in high-volume production at Samsung. GlobalFoundries had skipped "10 nm", Intel had not yet started high-volume "10 nm" production, due to yield issues, and TSMC had considered "10 nm" to be a short-lived node, mainly dedicated to processors for Apple during 2017–2018, moving on to "7 nm" in 2018.
There is also a distinction to be made between "10 nm" as marketed by foundries and "10 nm" as marketed by DRAM companies.

## Technology production history

In April 2013, Samsung announced that it had begun mass production of multi-level cell (MLC) flash memory chips using a "10 nm-class" process, which, according to Tom's Hardware, Samsung defined as "a process technology node somewhere between 10-nm and 20-nm". On 17 October 2016, Samsung Electronics announced mass production of SoC chips at "10 nm". The technology's main announced challenge at that time had been triple patterning for its metal layer.
TSMC began commercial production of "10 nm" chips in early 2016, before moving onto mass production in early 2017.
On 21 April 2017, Samsung started shipping their Galaxy S8 smartphone, which used the company's version of the "10 nm" processor. On 12 June 2017, Apple delivered second-generation iPad Pro tablets powered with TSMC-produced Apple A10X chips using the "10 nm" FinFET process.
On 12 September 2017, Apple announced the Apple A11, a 64-bit ARM-based system on a chip, manufactured by TSMC using a "10 nm" FinFET process, containing 4.3 billion transistors on a die of 87.66 mm$^2$.
In April 2018, Intel announced a delay in volume production of "10 nm" mainstream CPUs until sometime in 2019. In July, the exact time was further pinned down to the holiday season. In the meantime, however, they did release a low-power "10 nm" mobile chip, albeit exclusive to Chinese markets and with much of the chip disabled.
In June 2018 at VLSI 2018, Samsung announced their "11LPP" and "8LPP" processes. "11LPP" was a hybrid based on Samsung "14 nm" and "10 nm" technology. "11LPP" was based on their "10 nm" BEOL, not their "20 nm" BEOL like the "14LPP". "8LPP" was based on the "10LPP" process.
Nvidia released their GeForce 30 series GPUs in September 2020. They were at that time made on a custom version of Samsung's "8 nm" process, called "Samsung 8N", with a transistor density of 44.56 million transistors per mm$^2$.

## Process nodes
### Foundry

| | ITRS Logic Device Ground Rules (2015) | ITRS Logic Device Ground Rules (2015) | Samsung | Samsung | Samsung | Samsung | Samsung | TSMC | Intel | Intel |
| Process name | 16/14 nm | 11/10 nm | 10LPE (10 nm) | 10LPP (10 nm) | 8LPP (8 nm) | 8LPU (8 nm) | 8LPA (8 nm) | 10FF (10 nm) | 10nm | 10nm SF (10 nm) |
| Transistor density (MTr / mm$^2$) | Un­known | Un­known | 51.82 | 51.82 | 61.18 | 61.18 | Un­known | 52.51 | 100.76 | 100.76 |
| Transistor gate pitch (nm) | 70 | 48 | 68 | 68 | 64 | 64 | Un­known | 66 | 54 | 54 |
| Interconnect pitch (nm) | 56 | 36 | 51 | 51 | Un­known | Un­known | Un­known | 44 | 36 | 36 |
| Transistor fin pitch (nm) | 42 | 36 | 42 | 42 | 42 | 42 | Un­known | 36 | 34 | 34 |
| Transistor fin height (nm) | 42 | 42 | 49 | 49 | Un­known | Un­known | Un­known | 42 | 53 | 53 |
| Production year | 2015 | 2017 | 2016 Q4 production | 2017 Q4 production | 2018 production | 2018 risk production 2019 production | 2021 production | 2016 risk production 2017 production | 2018 production (Cannon Lake) | 2020 production (Tiger Lake) |
* ↑ For 10nm ESF renamed Intel 7, see 7 nm
* ↑ Intel uses this formula: ${\rm {No.\ Transistors/mm^{2}=0.6\cdot {\frac {\rm {NAND2\ Tr\ Count}}{\rm {NAND2\ Cell\ Area}}}+0.4\cdot {\frac {\rm {Scan\ Flip\ Flop\ Tr\ Count}}{\rm {Scan\ Flip\ Flop\ Cell\ Area}}}}}$
Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch). Samsung reported their "10 nm" process as having a 64 nm transistor gate pitch and 48 nm interconnect pitch. TSMC reported their "10 nm" process as having a 64 nm transistor gate pitch and 42 nm interconnect pitch. Further investigation by Tech Insights revealed even these values to also be false, and they have been updated accordingly. In addition, the transistor fin height of Samsung's "10 nm" process was updated by MSSCORPS CO at SEMICON Taiwan 2017. GlobalFoundries decided not to develop a "10 nm" node, because it believed it would be short lived. Samsung's "8 nm" process was at that time the company's last to exclusively use DUV lithography.

## DRAM "10 nm class"

For the DRAM industry, the term "10 nm-class" is often used and this dimension generally refers to the half-pitch of the active area. The "10 nm" foundry structures are generally much larger.
Generally "10 nm class" refers to DRAM with a 10-19 nm feature size, and was first introduced c. 2016. As of 2020, there were three generations of "10 nm class" DRAM : 1x nm (19-17 nm, Gen1); 1y nm (16-14 nm, Gen2); and 1z nm (13-11 nm, Gen3). 3rd Generation "1z" DRAM was first introduced c. 2019 by Samsung, and was initially stated to be produced using ArF lithography without the use of EUV lithography; subsequent production did utilise EUV lithography.
Beyond 1z Samsung named its next node (fourth generation "10 nm class") DRAM : "D1a" (expected at that time to have been produced in 2021), and beyond that "D1b" (expected at that time to have been produced in 2022); whilst Micron referred to succeeding "nodes" as "D1α" and "D1β". Micron announced volume shipment of 1α class DRAM in early 2021.