# 14 nm process

The "14 nanometer process" refers to a marketing term for the MOSFET technology node that is the successor to the "22 nm" (or "20 nm") node. The "14 nm" was so named by the International Technology Roadmap for Semiconductors (ITRS). Until about 2011, the node following "22 nm" was expected to be "16 nm". All "14 nm" nodes use FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology that is a non-planar evolution of planar silicon CMOS technology.
Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit; neither gate length, metal pitch or gate pitch on a "14nm" device is fourteen nanometers. For example, TSMC and Samsung's "10 nm" processes are somewhere between Intel's "14 nm" and "10 nm" processes in transistor density, and TSMC's "7 nm" processes are dimensionally similar to Intel's "10 nm" process.
Samsung Electronics taped out a "14 nm" chip in 2014, before manufacturing "10 nm class" NAND flash chips in 2013. The same year, SK Hynix began mass-production of "16 nm" NAND flash, and TSMC began "16 nm" FinFET production. The following year, Intel began shipping "14 nm" scale devices to consumers.

## History
### Background

The resolutions of a "14 nm" device are difficult to achieve in a polymeric resist, even with electron beam lithography. In addition, the chemical effects of ionizing radiation also limit reliable resolution to about 30 nm, which is also achievable using current state-of-the-art immersion lithography. Hardmask materials and multiple patterning are required.
A more significant limitation comes from plasma damage to low-k materials. The extent of damage is typically 20 nm thick, but can also go up to about 100 nm. The damage sensitivity is expected to get worse as the low-k materials become more porous. For comparison, the atomic radius of an unconstrained silicon is 0.11 nm. Thus about 90 Si atoms would span the channel length, leading to substantial leakage.
Tela Innovations and Sequoia Design Systems developed a methodology allowing double exposure for the "16 nm"/"14 nm" node circa 2010. Samsung and Synopsys had also, at that time, begun implementing double patterning in "22 nm" and "16 nm" design flows. Mentor Graphics reported taping out "16 nm" test chips in 2010. On January 17, 2011, IBM announced that they were teaming up with ARM to develop "14 nm" chip processing technology.
On February 18, 2011, Intel announced that it would construct a new $5 billion semiconductor fabrication plant in Arizona, designed to manufacture chips using the "14 nm" manufacturing processes and leading-edge 300 mm wafers. The new fabrication plant was to be named Fab 42, and construction was meant to start in the middle of 2011. Intel billed the new facility as "the most advanced, high-volume manufacturing facility in the world," and said it would come on line in 2013. Intel since decided to postpone opening this facility and instead upgrade its existing facilities to support 14-nm chips. On May 17, 2011, Intel announced a roadmap for 2014 that included "14 nm" transistors for their Xeon, Core, and Atom product lines.

### Technology demos

In the late 1990s, Hisamoto's Japanese team from Hitachi Central Research Laboratory began collaborating with an international team of researchers on further developing FinFET technology, including TSMC's Chenming Hu and various UC Berkeley researchers. In 1998, the team successfully fabricated devices down to a 17 nm process. They later developed a 15 nm FinFET process in 2001. In 2002, an international team of researchers at UC Berkeley, including Shibly Ahmed (Bangladeshi), Scott Bell, Cyrus Tabery (Iranian), Jeffrey Bokor, David Kyser, Chenming Hu (Taiwan Semiconductor Manufacturing Company), and Tsu-Jae King Liu, demonstrated FinFET devices down to 10 nm gate length.
In 2005, Toshiba demonstrated a 15 nm FinFET process, with a 15 nm gate length and 10 nm fin width, using a sidewall spacer process. It had erstwhile been suggested in 2003 that for the 16 nm node, a logic transistor would have a gate length of about 5 nm. In December 2007, Toshiba demonstrated a prototype memory unit that used 15-nanometre thin lines.
In December 2009, National Nano Device Laboratories, owned by the Taiwanese government, produced a "16 nm" SRAM chip.
In September 2011, Hynix announced the development of "15 nm" NAND cells.
In December 2012, Samsung Electronics taped out a "14 nm" chip.
In September 2013, Intel demonstrated an Ultrabook laptop that used a "14 nm" Broadwell CPU, and Intel CEO Brian Krzanich said, "[CPU] will be shipping by the end of this year." However, as of February 2014, shipment had at time erstwhile been delayed further until Q4 2014.
In August 2014, Intel announced details of the "14 nm" microarchitecture for its upcoming Core M processors, the first product to be manufactured on Intel's "14 nm" manufacturing process. The first systems based on the Core M processor were to become available in Q4 2014 — according to the press release. "Intel's 14 nanometer technology uses second-generation tri-gate transistors to deliver industry-leading performance, power, density and cost per transistor," said Mark Bohr, Intel senior fellow, Technology and Manufacturing Group, and director, Process Architecture and Integration.
In 2018 a shortage of "14 nm" fab capacity was announced by Intel.

### Shipping devices

In 2013, SK Hynix began mass-production of "16 nm" NAND flash, TSMC began "16 nm" FinFET production, and Samsung began "10 nm class" NAND flash production.
On September 5, 2014, Intel launched the first three Broadwell-based processors that belonged to the low-TDP Core M family: Core M-5Y10, Core M-5Y10a, and Core M-5Y70.
In February 2015, Samsung announced that their flagship smartphones, the Galaxy S6 and S6 Edge, would feature "14 nm" Exynos systems on chip (SoCs).
On March 9, 2015, Apple Inc. released the "Early 2015" MacBook and MacBook Pro, which utilized "14 nm" Intel processors. Of note is the i7-5557U, which has Intel Iris Graphics 6100 and two cores running at 3.1 GHz, using only 28 watts.
On September 25, 2015, Apple Inc. released the iPhone 6S & 6S Plus, which were erstwhile equipped with "desktop-class" A9 chips that are fabricated in both "14 nm" by Samsung and "16 nm" by TSMC (Taiwan Semiconductor Manufacturing Company).
In May 2016, Nvidia released its GeForce 10 series GPUs based on the Pascal architecture, which incorporates TSMC's "16 nm" FinFET technology and Samsung's "14 nm" FinFET technology.
In June 2016, AMD released its Radeon RX 400 GPUs based on the Polaris architecture, which incorporated "14 nm" FinFET technology from Samsung. The technology had at that time been licensed to GlobalFoundries for dual sourcing.
On August 2, 2016, Microsoft released the Xbox One S, which utilized "16 nm" by TSMC.
On March 2, 2017, AMD released its Ryzen CPUs based on the Zen architecture, incorporating "14 nm" FinFET technology from Samsung which had erstwhile been licensed to GlobalFoundries for GlobalFoundries to build.
The NEC SX-Aurora TSUBASA processor, introduced in October 2017, used a "16 nm" FinFET process from TSMC and was designed for use with NEC SX supercomputers.
On July 22, 2018, GlobalFoundries announced their "12 nm" Leading-Performance (12LP) process, based on a licensed 14LP process from Samsung.
In September 2018, Nvidia released GPUs based on their Turing (microarchitecture), which were made on TSMC's "12 nm" process and had a transistor density of 24.67 million transistors per square millimeter.

## 14 nm process nodes

| | ITRS Logic Device Ground Rules (2015) | Samsung | Samsung | Samsung | TSMC | TSMC | TSMC | TSMC | Intel | Intel | Intel | GlobalFoundries | GlobalFoundries | GlobalFoundries | SMIC |
| Process name | 16/14 nm | 14LPE | 14LPP | 11LPP | 16FF (16 nm) | 16FF+ (16 nm) | 16FFC (16 nm) | 12FFC (12 nm) | 14 nm | 14 nm + | 14 nm ++ | 14LPP (14 nm) | 12LP (12 nm) | 12LP+ | 14 nm |
| Transistor density (MTr/mm$^2$) | Un­known | 32.94 | 32.94 | 54.38 | 28.88 | 28.88 | 28.88 | 33.8 | 37.5 44.67 | 37.5 44.67 | 37.5 44.67 | 30.59 | 36.71 | Un­known | 30 |
| Transistor gate pitch (nm) | 70 | 78 | 78 | 78 | 88 | 88 | 88 | 88 | 70 | 70 | 84 | 84 | 84 | Un­known | Un­known |
| Interconnect pitch (nm) | 56 | 67 | 67 | 67 | 70 | 70 | 70 | 70 | 52 | 52 | 52 | Un­known | Un­known | Un­known | Un­known |
| Transistor fin pitch (nm) | 42 | 49 | 49 | 49 | 45 | 45 | 45 | 45 | 42 | 42 | 42 | 48 | 48 | Un­known | Un­known |
| Transistor fin width (nm) | 8 | 8 | 8 | 8 | Un­known | Un­known | Un­known | Un­known | 8 | 8 | 8 | Un­known | Un­known | Un­known | Un­known |
| Transistor fin height (nm) | 42 | ~38 | ~38 | ~38 | 37 | 37 | 37 | 37 | 42 | 42 | 42 | Un­known | Un­known | Un­known | Un­known |
| Production year | 2015 | 2014 Q4 | 2016 Q1 | 2018 H2 | 2013 Q4 risk production 2014 production | 2015 Q3 | 2016 Q2 | 2017 | 2014 Q3 | 2016 H2 | 2017 | 2016 | 2018 | 2020 Q3 | 2019 |
* ↑ Second-sourced to GlobalFoundries.
* ↑ Based on Samsung's 14 nm process.
* ↑ Intel uses this formula: ${\rm {0.6\times {\frac {NAND2\ Tr\ Count}{NAND2\ Cell\ Area}}+0.4\times {\frac {Scan\ Flip\ Flop\ Tr\ Count}{Scan\ Flip\ Flop\ Cell\ Area}}=}}$ # ${\rm {Transistors/mm^{2}}}$
Lower numbers are better, except for transistor density, in which case the opposite is true. Transistor gate pitch is also referred to as CPP (contacted poly pitch), and interconnect pitch is also referred to as MMP (minimum metal pitch).