# HP Saturn

The Saturn family of 4-bit (datapath) microprocessors was developed by Hewlett-Packard in the 1980s first for the HP-71B handheld computer, released in 1984, and later for various HP calculators (starting with the HP-18C). It succeeded the Nut family of processors used in earlier calculators. The HP48SX and HP48S were the last models to use HP manufactured Saturn processors, later models used processors manufactured by NEC. The HP 49 series initially used the Saturn CPU until the NEC fab could no longer manufacture the processor for technical reasons in 2003. Starting with the HP 49g+ model in 2003, the calculators switched to a Samsung S3C2410 processor with an ARM920T core (part of the ARMv4T architecture) which ran an emulator of the Saturn hardware in software. In 2000, the HP 39G and HP 40G were the last calculators introduced based on the actual NEC fabricated Saturn hardware. The last calculators introduced to use the Saturn emulator were the HP 39gs, HP 40gs and HP 50g in 2006, as well as the 2007 revision of the hp 48gII. The HP 50g was the last calculator sold by HP using this emulator when it was discontinued in 2015 due to Samsung stopping production of the ARM processor on which it was based.

## Architecture

The Saturn hardware is a nibble serial design as opposed to its Nut predecessor, which was bit-serial. Internally, the Saturn CPU has four 4-bit data buses that allow for nearly 1-cycle per nibble performance with one or two buses acting as a source and one or two acting as a destination. The smallest addressable word is a 4-bit nibble which can hold one binary-coded decimal (BCD) digit. Any unit of data in the registers larger than a nibble, up to 64-bits, can be operated on as a whole, however the Saturn CPU performs the operation serially on a nibble-by-nibble basis internally.
The Saturn architecture has an internal register width of 64 bits and 20-bits of address, with memory being addressed to 4-bit (nibble) granularity. Saturn ALU instructions support variable data width, operating on one to 16 nibbles of a word. The original Saturn CPU chips provided a four-bit external data bus, but later Saturn-based SoCs included on chip bus conversion to an 8-bit external data bus and 19-bit external address bus.
The Saturn architecture has four 64-bit GPRs (General Purpose Registers), named A, B, C and D. In addition, there are also five 64-bit "scratch" registers named R0, R1, R2, R3 and R4. These can only store data. If an ALU operation is required for data in a scratch register, then the register in question must be transferred to a GPR first. Other registers include a 1-nibble "pointer" register named P, usually used to select a nibble in a GPR or a range of nibbles (or for aligning immediate data on a specific nibble in a GPR, with wrap-around). For memory access, there are two 20-bit data pointer registers named D0 and D1. The Saturn architecture also has a PC or program counter register which can interoperate with the GPRs. There is also an 8-level, circular, LIFO 20-bit hardware return stack named RSTK used when a subroutine call instruction is issued. Additionally, the Saturn CPU is equipped with a 16-bit software status register named ST and a 1-nibble hardware status register named HS, which notably, contains the SB or "sticky bit" flag indicating whether a binary 1 was right shifted off of a GPR. Furthermore, the Saturn architecture has a 12-bit OUT register and a 16-bit IN register, which in the Yorke and Clarke SoCs, are used to capture input from the keyboard and also control the beeper. There is also a 1-bit carry flag register.
In addition to the above, the Saturn CPU has a simple, non-prioritized interrupt system. When an interrupt occurs, the CPU finishes executing the current instruction, saves the program counter to the hardware return stack (RSTK) and jumps to address 0x0000Fh, where the preceding value is in nibbles. The CPU also interacts with the keyboard scanning logic directly.
The following diagram depicts the registers (with each white square being 4-bits / a nibble except for the Carry flag, which is 1 bit):
Saturn 64-bit GPR register format and fields:
HP Saturn register fields :
| Bits | Bits | 63–60 | 59–56 | 55–52 | 51–48 | 47–44 | 43–40 | 39–36 | 35–32 | 31–28 | 27–24 | 23–20 | 19–16 | 15–12 | 11–8 | 7–4 | 3–0 |
| Nibble | Nibble | F | E | D | C | B | A | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Fields | | | | | | | | | | | | | | | XS | B | B |
| Fields | | | | | | | | | | | | | A | A | A | A | A |
| Fields | | S | M | M | M | M | M | M | M | M | M | M | M | M | X | X | X |
| Fields | | W | W | W | W | W | W | W | W | W | W | W | W | W | W | W | W |
| Fields | P=0 | | | | | | | | | | | | | | | | P |
| Fields | P=7 | | | | | | | | | WP | WP | WP | WP | WP | WP | WP | WP |
Data in the general purpose registers can be accessed via fields that fall on nibble boundaries, whereas the scratch registers allow only load and store operations. The fields, as shown in the above diagram, are W (whole 64-bit GPR), A (address, first 5 nibbles of a GPR), S (sign of mantissa, most significant nibble of a GPR), XS (exponent sign, nibble 2 of a GPR), M (mantissa, nibbles 3–14 of a GPR), X (exponent, first 3 nibbles of a GPR) and B (first byte of a GPR). In addition, there is the P field which selects a nibble from a GPR based on the P register's 4-bit value. Also, there is the WP field which selects nibbles 0 through the nibble selected in the P register. The 64 bits (16 nibbles) can hold BCD-formatted coded floating point numbers composed of a sign nibble (which is "9" if the number is negative), 12 mantissa digits and a 3-digit 10's complement exponent stored in BCD format (±499). The internal representation of BCD floating point values are a 15-digit mantissa with one sign nibble in one register combined with a 20-bit exponent, in 10's complement format, in another register. The use of BCD instead of straight binary representation is advantageous for calculators as it avoids rounding problems that occur on the binary/decimal conversion.
The Saturn CPU's instruction and data addresses are also nibble-based. The three pointer registers (including the program counter) and address registers are 20 bits wide. Due to this, the Saturn architecture can address 1 M nibbles or, equivalently, 512 K bytes. Beyond that size (e.g. in the 48GX), bank switching is used.
The original HP-71B handheld computer and the HP-28C had the Saturn processor as a separate chip. In the HP 48S/SX, 48G/GX series and HP-28S, HP-27S, HP-42S, HP-32SII and HP-20S, the Saturn CPU core is integrated as part of a more complex integrated circuit (IC) SoC.

## Example code

The following is an integer implementation of a BCD decimal square root algorithm in Saturn Jazz / HP Tools assembly syntax:

## Chipsets and applications

The original Saturn CPU gave its name to the entire instruction set architecture. Later chips had their own code names:
| ISA level | Processor code-name | Used in calculator models | Properties |
| 0 | Saturn (1LF2) | HP-44A, HP-71B (1984) | |
| 1 | Saturn (1LK7) | HP-18C (1986), HP-28C (1987), HP-71B | 640 kHz, more instructions |
| 2 | Bert (1LU7) | HP-10B (1988), HP-20S (1988), HP-21S | 640 kHz, 10 KB ROM, 256 bytes RAM, LCD driver |
| 2 | Sacajawea (1LR3) | HP-14B, HP-22S, HP-32S (1988), HP-32S+, HP-32SII (1991) | 640 kHz, 16 KB ROM, 512 bytes RAM, LCD driver |
| 2 | Lewis (1LR2) | HP-17B (1988), HP 17BII (1990), HP-19B (1988), HP 19BII (1990), HP-27S (1988), HP-28S (1988), HP-42S (1988) | 1 MHz, 64 KB ROM, LCD driver, memory controller, IR control, 3 V CMOS |
| 2 | Clarke (1LT8) | HP 48SX (1990), HP 48S (1991) | 2 MHz, LCD controller, memory controller, UART and IR control, more instructions |
| 2 | Yorke 00048-80063 | HP 38G (1995), HP 38G+ (1998), HP 39G (2000), HP 40G (2000), HP 48GX (1993), HP 48G (1993), HP 48G+ (1998), HP 49G (1999) | 3.68–4 MHz, LCD controller, memory controller, UART and IR control, manufactured by NEC, more instructions, sometimes also known as Saturn 5 platform |
| ? | New-Yorke | HP 48GX prototype | 8 MHz, LCD controller, memory controller, UART and IR control. This was only made as an internal HP prototype and never released in the wild. |
| 2 | Apple series (Big Apple, Mid Apple, Little Apple) | hp 39g+ (2003), HP 39gs (2006), HP 40gs (2006), hp 49g+ (2003), hp 48gII (2003/2007), HP 50g (2006) | Virtual version of the Yorke CPU emulated by members of the 48/75 MHz Samsung S3C2410 processor family with ARM920T core (of the ARMv4T architecture) aka Saturn+ with additional virtual instructions |
The CPU code-names are inspired by members of the Lewis and Clark Expedition of 1804–1806, the first United States overland expedition to the Pacific coast and back. The virtual CPU / emulator code names were inspired by the prototype "New-Yorke" Saturn-based 8 MHz SoC that never made it to production. According to one of the ACO (Australian Calculator Operation) members, "Big Apple" was derived from the code name "New-Yorke" of the prototype 8 MHz Saturn-based SoC in a reference to New York city, hence the names "Big apple", "Mid Apple" and "Little Apple".