# Steamroller (microarchitecture)

AMD Steamroller Family 15h is a microarchitecture developed by AMD for AMD APUs, which succeeded Piledriver in the beginning of 2014 as the third-generation Bulldozer-based microarchitecture. Steamroller APUs continue to use two-core modules as their predecessors, while aiming at achieving greater levels of parallelism.

## Microarchitecture

Steamroller still features two-core modules found in Bulldozer and Piledriver designs called clustered multi-thread (CMT), meaning that one module is marketed as a dual-core processor. The focus of Steamroller is for greater parallelism. Improvements center on independent instruction decoders for each core within a module, 25% more of the maximum width dispatches per thread, better instruction schedulers, improved perceptron branch predictor, larger and smarter caches, up to 30% fewer instruction cache misses, branch misprediction rate reduced by 20%, dynamically resizable L2 cache, micro-operations queue, more internal register resources and improved memory controller.
AMD estimated that these improvements will increase instructions per cycle (IPC) up to 30% compared to the first-generation Bulldozer core while maintaining Piledriver's high clock rates with decreased power consumption. The final result was a 9% single-threaded IPC improvement, and 18% multi-threaded IPC improvement over Piledriver.
Steamroller, the microarchitecture for CPUs, as well as Graphics Core Next, the microarchitecture for GPUs, are paired together in the APU lines to support features specified in Heterogeneous System Architecture.

## History

In 2011, AMD announced a third-generation Bulldozer-based line of processors for 2013, with Next Generation Bulldozer as the working title, using the 28 nm manufacturing process.
On 21 September 2011, leaked AMD slides indicated that this third generation of Bulldozer core was codenamed Steamroller.
In January 2014, the first Kaveri APUs became available.
Starting from May 2015 till March 2016 new APUs were launched as Kaveri-refresh (codenamed Godavari).

## Features

The following table shows features of AMD's processors with 3D graphics, including APUs (see also: List of AMD processors with 3D graphics).
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| Platform | Platform | Platform | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | Low and ultra-low power | Low and ultra-low power | Low and ultra-low power | Low and ultra-low power | Low and ultra-low power | Low and ultra-low power | Low and ultra-low power | Low and ultra-low power | Low and ultra-low power |
| Codename | Server | Basic | | | | | | Toronto | | | | | | | | | | | | | | | | | |
| Codename | Server | Micro | | | | | | | | | | | | | | | | Kyoto | | | | | | | |
| Codename | Desktop | Performance | | | | | | | | | | | | | Raphael | Phoenix | | | | | | | | | |
| Codename | Desktop | Mainstream | Llano | Trinity | Richland | Kaveri | Kaveri Refresh (Godavari) | Carrizo | Bristol Ridge | Raven Ridge | Picasso | Renoir | Cezanne | | Raphael | Phoenix | | | | | | | | | |
| Codename | Desktop | Entry | Llano | Trinity | Richland | Kaveri | Kaveri Refresh (Godavari) | Carrizo | Bristol Ridge | Raven Ridge | Picasso | Renoir | Cezanne | | | | Phoenix | | | | | | | | | |
| Codename | Desktop | Basic | | | | | | | | | | | | | | | | Kabini | | | | Dalí | | | |
| Codename | Mobile | Performance | | | | | | | | | | Renoir | Cezanne | Rembrandt | Dragon Range | | | | | | | | | | |
| Codename | Mobile | Mainstream | Llano | Trinity | Richland | Kaveri | | Carrizo | Bristol Ridge | Raven Ridge | Picasso | Renoir Lucienne | Cezanne Barceló | Rembrandt | Dragon Range | Phoenix | | | | | | | | | |
| Codename | Mobile | Entry | Llano | Trinity | Richland | Kaveri | | Carrizo | Bristol Ridge | Raven Ridge | | | | | | | | | | | | Dalí | | | Mendocino |
| Codename | Mobile | Basic | | | | | | | | | | | | | | | Desna, Ontario, Zacate | Kabini, Temash | Beema, Mullins | Carrizo-L | Stoney Ridge | Dalí | Pollock | | Mendocino |
| Codename | Embedded | Embedded | | Trinity | | Bald Eagle | | Merlin Falcon, Brown Falcon | | Great Horned Owl | | Grey Hawk | | | | | Ontario, Zacate | Kabini | Steppe Eagle, Crowned Eagle, LX-Family | | Prairie Falcon | Banded Kestrel | | River Hawk | |
| Released | Released | Released | Aug 2011 | Oct 2012 | Jun 2013 | Jan 2014 | 2015 | Jun 2015 | Jun 2016 | Oct 2017 | Jan 2019 | Mar 2020 | Jan 2021 | Jan 2022 | Sep 2022 | Jan 2023 | Jan 2011 | May 2013 | Apr 2014 | May 2015 | Feb 2016 | Apr 2019 | Jul 2020 | Jun 2022 | Nov 2022 |
| CPU microarchitecture | CPU microarchitecture | CPU microarchitecture | K10 | Piledriver | Piledriver | Steamroller | Steamroller | Excavator | "Excavator+" | Zen | Zen+ | Zen 2 | Zen 3 | Zen 3+ | Zen 4 | Zen 4 | Bobcat | Jaguar | Puma | Puma+ | "Excavator+" | Zen | Zen | Zen+ | "Zen 2+" |
| ISA | ISA | ISA | x86-64 v1 | x86-64 v2 | x86-64 v2 | x86-64 v2 | x86-64 v2 | x86-64 v3 | x86-64 v3 | x86-64 v3 | x86-64 v3 | x86-64 v3 | x86-64 v3 | x86-64 v3 | x86-64 v4 | x86-64 v4 | x86-64 v1 | x86-64 v2 | x86-64 v2 | x86-64 v2 | x86-64 v3 | x86-64 v3 | x86-64 v3 | x86-64 v3 | x86-64 v3 |
| Socket | Desktop | Performance | — | — | — | — | — | — | — | — | — | — | — | — | AM5 | — | — | — | — | — | — | — | — | — | — |
| Socket | Desktop | Mainstream | — | — | — | — | — | AM4 | AM4 | AM4 | AM4 | AM4 | AM4 | — | AM5 | — | — | — | — | — | — | — | — | — | — |
| Socket | Desktop | Entry | FM1 | FM2 | FM2 | FM2+ | FM2+ | FM2+, AM4 | AM4 | AM4 | AM4 | AM4 | AM4 | — | — | — | | | — | — | — | — | — | — | — | — | — |
| Socket | Desktop | Basic | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | AM1 | — | — | — | FP5 | — | — | — |
| Socket | Other | Other | FS1 | FS1+, FP2 | FS1+, FP2 | FP3 | FP3 | FP4 | FP4 | FP5 | FP5 | FP6 | FP6 | FP7 | FL1 | FP7 FP7r2 FP8 | ? | FT1 | FT3 | FT3b | FT3b | FP4 | FP5 | FT5 | FP5 | FT6 |
| PCI Express version | PCI Express version | PCI Express version | 2.0 | 2.0 | 2.0 | 3.0 | 3.0 | 3.0 | 3.0 | 3.0 | 3.0 | 3.0 | 3.0 | 4.0 | 5.0 | 4.0 | 2.0 | 2.0 | 2.0 | 2.0 | 3.0 | 3.0 | 3.0 | 3.0 | 3.0 |
| CXL | CXL | CXL | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — |
| Fab. (nm) | Fab. (nm) | Fab. (nm) | GF 32SHP (HKMG SOI) | GF 32SHP (HKMG SOI) | GF 32SHP (HKMG SOI) | GF 28SHP (HKMG bulk) | GF 28SHP (HKMG bulk) | GF 28SHP (HKMG bulk) | GF 28SHP (HKMG bulk) | GF 14LPP (FinFET bulk) | GF 12LP (FinFET bulk) | TSMC N7 (FinFET bulk) | TSMC N7 (FinFET bulk) | TSMC N6 (FinFET bulk) | CCD: TSMC N5 (FinFET bulk) cIOD: TSMC N6 (FinFET bulk) | TSMC 4nm (FinFET bulk) | TSMC N40 (bulk) | TSMC N28 (HKMG bulk) | GF 28SHP (HKMG bulk) | GF 28SHP (HKMG bulk) | GF 28SHP (HKMG bulk) | GF 14LPP (FinFET bulk) | GF 14LPP (FinFET bulk) | GF 12LP (FinFET bulk) | TSMC N6 (FinFET bulk) |
| Die area (mm$^2$) | Die area (mm$^2$) | Die area (mm$^2$) | 228 | 246 | 246 | 245 | 245 | 245 | 250 | 210 | 210 | 156 | 180 | 210 | CCD: (2x) 70 cIOD: 122 | 178 | 75 (+ 28 FCH) | 107 | 107 | ? | 125 | 149 | | | ~100 |
| Min TDP (W) | Min TDP (W) | Min TDP (W) | 35 | 17 | 17 | 17 | 17 | 12 | 12 | 12 | 12 | 10 | 10 | 15 | 65 | 35 | 4.5 | 4 | 3.95 | 10 | 6 | 6 | 6 | 12 | 8 |
| Max APU TDP (W) | Max APU TDP (W) | Max APU TDP (W) | 100 | 100 | 100 | 95 | 95 | 65 | 65 | 65 | 65 | 65 | 65 | 45 | 170 | 54 | 18 | 25 | 25 | 25 | 25 | 25 | 6 | 54 | 15 |
| Max stock APU base clock (GHz) | Max stock APU base clock (GHz) | Max stock APU base clock (GHz) | 3 | 3.8 | 4.1 | 4.1 | 4.1 | 3.7 | 3.8 | 3.6 | 3.7 | 3.8 | 4.0 | 3.3 | 4.7 | 4.3 | 1.75 | 2.2 | 2 | 2.2 | 3.2 | 2.6 | 1.2 | 3.35 | 2.8 |
| Max APUs per node | Max APUs per node | Max APUs per node | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Max core dies per CPU | Max core dies per CPU | Max core dies per CPU | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 2 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Max CCX per core die | Max CCX per core die | Max CCX per core die | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 2 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Max cores per CCX | Max cores per CCX | Max cores per CCX | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 8 | 8 | 8 | 8 | 2 | 4 | 4 | 4 | 2 | 2 | 2 | 4 | 4 |
| Max CPU cores per APU | Max CPU cores per APU | Max CPU cores per APU | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 8 | 8 | 8 | 16 | 8 | 2 | 4 | 4 | 4 | 2 | 2 | 2 | 4 | 4 |
| Max threads per CPU core | Max threads per CPU core | Max threads per CPU core | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 1 | 1 | 1 | 1 | 1 | 2 | 2 | 2 | 2 |
| Integer pipeline structure | Integer pipeline structure | Integer pipeline structure | 3+3 | 2+2 | 2+2 | 2+2 | 2+2 | 2+2 | 2+2 | 4+2 | 4+2 | 4+2+1 | 1+3+3+1+2 | 1+3+3+1+2 | 1+3+3+1+2 | 1+3+3+1+2 | 1+1+1+1 | 1+1+1+1 | 1+1+1+1 | 1+1+1+1 | 2+2 | 4+2 | 4+2 | 4+2 | 4+2+1 |
| i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF | i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF | i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF | | | | | | | | | | | | | | | | | | | | | | | |
| IOMMU | IOMMU | IOMMU | — | v2 | v2 | v2 | v2 | v2 | v2 | v2 | v2 | v2 | v2 | v2 | v2 | v2 | v1 | v1 | v2 | v2 | v2 | v2 | v2 | v2 | v2 |
| BMI1, AES-NI, CLMUL, and F16C | BMI1, AES-NI, CLMUL, and F16C | BMI1, AES-NI, CLMUL, and F16C | — | | | | | | | | | | | | | | — | | | | | | | | | |
| MOVBE | MOVBE | MOVBE | — | — | — | — | — | | | | | | | | | | | | | | | | | | — | | | | | | | | | |
| AVIC, BMI2, RDRAND, and MWAITX/MONITORX | AVIC, BMI2, RDRAND, and MWAITX/MONITORX | AVIC, BMI2, RDRAND, and MWAITX/MONITORX | — | — | — | — | — | | | | | | | | | | — | — | — | — | | | | | |
| SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing | SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing | SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing | — | — | — | — | — | — | — | | | | | | | | — | — | — | — | — | | | | |
| GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT | GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT | GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT | — | — | — | — | — | — | — | — | — | | | | | | — | — | — | — | — | — | — | — | |
| MPK, VAES | MPK, VAES | MPK, VAES | — | — | — | — | — | — | — | — | — | — | | | | | — | — | — | — | — | — | — | — | — |
| SGX | SGX | SGX | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — |
| FPUs per core | FPUs per core | FPUs per core | 1 | 0.5 | 0.5 | 0.5 | 0.5 | 0.5 | 0.5 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0.5 | 1 | 1 | 1 | 1 |
| Pipes per FPU | Pipes per FPU | Pipes per FPU | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 |
| FPU pipe width | FPU pipe width | FPU pipe width | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 256-bit | 256-bit | 256-bit | 256-bit | 256-bit | 80-bit | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 256-bit |
| CPU instruction set SIMD level | CPU instruction set SIMD level | CPU instruction set SIMD level | SSE4a | AVX | AVX | AVX | AVX | AVX2 | AVX2 | AVX2 | AVX2 | AVX2 | AVX2 | AVX2 | AVX-512 | AVX-512 | SSSE3 | AVX | AVX | AVX | AVX2 | AVX2 | AVX2 | AVX2 | AVX2 |
| 3DNow! | 3DNow! | 3DNow! | 3DNow!+ | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — |
| PREFETCH/PREFETCHW | PREFETCH/PREFETCHW | PREFETCH/PREFETCHW | | | | | | | | | | | | | | | | | | | | | | | |
| GFNI | GFNI | GFNI | — | — | — | — | — | — | — | — | — | — | — | — | | | — | — | — | — | — | — | — | — | — |
| AMX | AMX | AMX | — | — | — | — | — | — | — | — | — | — | — | — | — | — | | | | | | | | | | | | | | — | — | — | — | — | — | — | — | — |
| FMA4, LWP, TBM, and XOP | FMA4, LWP, TBM, and XOP | FMA4, LWP, TBM, and XOP | — | | | | | | | — | — | — | — | — | — | — | — | — | — | — | | — | — | — | — |
| FMA3 | FMA3 | FMA3 | — | | | | | | | | | | | | | | — | — | — | — | | | | | |
| AMD XDNA | AMD XDNA | AMD XDNA | — | — | — | — | — | — | — | — | — | — | — | — | — | | — | — | — | — | — | — | — | — | — |
| L1 data cache per core (KiB) | L1 data cache per core (KiB) | L1 data cache per core (KiB) | 64 | 16 | 16 | 16 | 16 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 |
| L1 data cache associativity (ways) | L1 data cache associativity (ways) | L1 data cache associativity (ways) | 2 | 4 | 4 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 |
| L1 instruction caches per core | L1 instruction caches per core | L1 instruction caches per core | 1 | 0.5 | 0.5 | 0.5 | 0.5 | 0.5 | 0.5 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0.5 | 1 | 1 | 1 | 1 |
| Max APU total L1 instruction cache (KiB) | Max APU total L1 instruction cache (KiB) | Max APU total L1 instruction cache (KiB) | 256 | 128 | 128 | 192 | 192 | 192 | 192 | 256 | 256 | 256 | 256 | 256 | 512 | 256 | 64 | 64 | 128 | 128 | 96 | 128 | 128 | 128 | 128 |
| L1 instruction cache associativity (ways) | L1 instruction cache associativity (ways) | L1 instruction cache associativity (ways) | 2 | 2 | 2 | 3 | 3 | 3 | 3 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 2 | 2 | 2 | 2 | 3 | 4 | 4 | 4 | 8 |
| L2 caches per core | L2 caches per core | L2 caches per core | 1 | 0.5 | 0.5 | 0.5 | 0.5 | 0.5 | 0.5 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0.5 | 1 | 1 | 1 | 1 |
| Max APU total L2 cache (MiB) | Max APU total L2 cache (MiB) | Max APU total L2 cache (MiB) | 4 | 4 | 4 | 4 | 4 | 2 | 2 | 2 | 2 | 4 | 4 | 4 | 16 | | 1 | 2 | 2 | 2 | 1 | 1 | 1 | 2 | 2 |
| L2 cache associativity (ways) | L2 cache associativity (ways) | L2 cache associativity (ways) | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 16 | 16 | 16 | 16 | 16 | 8 | 8 | 8 | 8 |
| Max on--die L3 cache per CCX (MiB) | Max on--die L3 cache per CCX (MiB) | Max on--die L3 cache per CCX (MiB) | — | — | — | — | — | — | — | 4 | 4 | 4 | 16 | 16 | 32 | | — | — | — | — | — | — | 4 | 4 | 4 | 4 |
| Max 3D V-Cache per CCD (MiB) | Max 3D V-Cache per CCD (MiB) | Max 3D V-Cache per CCD (MiB) | — | — | — | — | — | — | — | — | — | — | — | — | 64 | — | — | — | — | — | — | — | — | — | — | — |
| Max total in-CCD L3 cache per APU (MiB) | Max total in-CCD L3 cache per APU (MiB) | Max total in-CCD L3 cache per APU (MiB) | — | — | — | — | — | — | — | 4 | 4 | 8 | 16 | 16 | 64 | | — | — | — | — | — | — | 4 | 4 | 4 | 4 |
| Max. total 3D V-Cache per APU (MiB) | Max. total 3D V-Cache per APU (MiB) | Max. total 3D V-Cache per APU (MiB) | — | — | — | — | — | — | — | — | — | — | — | — | 64 | — | — | — | — | — | — | — | — | — | — | — |
| Max. board L3 cache per APU (MiB) | Max. board L3 cache per APU (MiB) | Max. board L3 cache per APU (MiB) | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — |
| Max total L3 cache per APU (MiB) | Max total L3 cache per APU (MiB) | Max total L3 cache per APU (MiB) | — | — | — | — | — | — | — | 4 | 4 | 8 | 16 | 16 | 128 | | — | — | — | — | — | — | 4 | 4 | 4 | 4 |
| APU L3 cache associativity (ways) | APU L3 cache associativity (ways) | APU L3 cache associativity (ways) | — | — | — | — | — | — | — | 16 | 16 | 16 | 16 | 16 | 16 | 16 | — | — | — | — | — | — | 16 | 16 | 16 | 16 |
| L3 cache scheme | L3 cache scheme | L3 cache scheme | — | — | — | — | — | — | — | Victim | Victim | Victim | Victim | Victim | Victim | Victim | — | — | — | — | — | — | Victim | Victim | Victim | Victim |
| Max. L4 cache | Max. L4 cache | Max. L4 cache | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — |
| Max stock DRAM support | Max stock DRAM support | Max stock DRAM support | DDR3-1866 | DDR3-1866 | DDR3-2133 | DDR3-2133 | DDR3-2133 | DDR3-2133, DDR4-2400 | DDR4-2400 | DDR4-2933 | DDR4-2933 | DDR4-3200, LPDDR4-4266 | DDR4-3200, LPDDR4-4266 | DDR5-4800, LPDDR5-6400 | DDR5-5200 | DDR5-5600, LPDDR5x-7500 | DDR3L-1333 | DDR3L-1600 | DDR3L-1866 | DDR3L-1866 | DDR3-1866, DDR4-2400 | DDR4-2400 | DDR4-1600 | DDR4-3200 | LPDDR5-5500 |
| Max DRAM channels per APU | Max DRAM channels per APU | Max DRAM channels per APU | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 1 | 1 | 1 | 1 | 1 | 2 | 1 | 2 | 2 |
| Max stock DRAM bandwidth (GB/s) per APU | Max stock DRAM bandwidth (GB/s) per APU | Max stock DRAM bandwidth (GB/s) per APU | 29.866 | 29.866 | 34.132 | 34.132 | 34.132 | 38.400 | 38.400 | 46.932 | 46.932 | 68.256 | 68.256 | 102.400 | 83.200 | 120.000 | 10.666 | 12.800 | 14.933 | 14.933 | 19.200 | 38.400 | 12.800 | 51.200 | 88.000 |
| GPU microarchitecture | GPU microarchitecture | GPU microarchitecture | TeraScale 2 (VLIW5) | TeraScale 3 (VLIW4) | TeraScale 3 (VLIW4) | GCN 2nd gen | GCN 2nd gen | GCN 3rd gen | GCN 3rd gen | GCN 5th gen | GCN 5th gen | GCN 5th gen | GCN 5th gen | RDNA 2 | RDNA 2 | RDNA 3 | TeraScale 2 (VLIW5) | GCN 2nd gen | GCN 2nd gen | GCN 2nd gen | GCN 3rd gen | GCN 5th gen | GCN 5th gen | GCN 5th gen | RDNA 2 |
| GPU instruction set | GPU instruction set | GPU instruction set | TeraScale instruction set | TeraScale instruction set | TeraScale instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | RDNA instruction set | RDNA instruction set | RDNA instruction set | TeraScale instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | RDNA instruction set |
| Max stock GPU base clock (MHz) | Max stock GPU base clock (MHz) | Max stock GPU base clock (MHz) | 600 | 800 | 844 | 866 | 866 | 1108 | 1108 | 1250 | 1400 | 2100 | 2100 | 2400 | 400 | | 538 | 600 | ? | 847 | 900 | 1200 | 600 | 1300 | 1900 |
| Max stock GPU base GFLOPS | Max stock GPU base GFLOPS | Max stock GPU base GFLOPS | 480 | 614.4 | 648.1 | 886.7 | 886.7 | 1134.5 | 1134.5 | 1760 | 1971.2 | 2150.4 | 2150.4 | 3686.4 | 102.4 | | 86 | ? | ? | ? | 345.6 | 460.8 | 230.4 | 1331.2 | 486.4 |
| 3D engine | 3D engine | 3D engine | Up to 400:20:8 | Up to 384:24:6 | Up to 384:24:6 | Up to 512:32:8 | Up to 512:32:8 | Up to 512:32:8 | Up to 512:32:8 | Up to 704:44:16 | Up to 704:44:16 | Up to 512:32:8 | Up to 512:32:8 | 768:48:8 | 128:8:4 | | 80:8:4 | 128:8:4 | 128:8:4 | 128:8:4 | Up to 192:12:8 | Up to 192:12:4 | 192:12:4 | Up to 512:?:? | 128:?:? |
| 3D engine | 3D engine | 3D engine | IOMMUv1 | IOMMUv1 | IOMMUv1 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv1 | IOMMUv1 | ? | ? | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 |
| Video decoder | Video decoder | Video decoder | UVD 3.0 | UVD 3.0 | UVD 3.0 | UVD 4.2 | UVD 4.2 | UVD 6.0 | UVD 6.0 | VCN 1.0 | VCN 1.0 | VCN 2.1 | VCN 2.2 | VCN 3.1 | VCN 3.1 | ? | UVD 3.0 | UVD 4.0 | UVD 4.2 | UVD 6.0 | UVD 6.3 | VCN 1.0 | VCN 1.0 | VCN 1.0 | VCN 3.1 |
| Video encoder | Video encoder | Video encoder | — | VCE 1.0 | VCE 1.0 | VCE 2.0 | VCE 2.0 | VCE 3.1 | VCE 3.1 | VCN 1.0 | VCN 1.0 | VCN 2.1 | VCN 2.2 | VCN 3.1 | VCN 3.1 | ? | — | VCE 2.0 | VCE 2.0 | VCE 3.1 | VCE 3.1 | | VCN 1.0 | VCN 1.0 | VCN 1.0 | VCN 3.1 |
| AMD Fluid Motion | AMD Fluid Motion | AMD Fluid Motion | | | | | | | | | | | | | | | | | | | | | | | |
| GPU power saving | GPU power saving | GPU power saving | PowerPlay | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerPlay | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune |
| TrueAudio | TrueAudio | TrueAudio | — | — | — | | | | | | | | ? | ? | ? | ? | — | | | | | | | | |
| FreeSync | FreeSync | FreeSync | — | — | — | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | — | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 |
| HDCP | HDCP | HDCP | ? | ? | ? | 1.4 | 1.4 | 1.4 | 1.4 | 2.2 | 2.2 | 2.2 | 2.2 | 2.3 | 2.3 | 2.3 | ? | 1.4 | 1.4 | 1.4 | 1.4 | 2.2 | 2.2 | 2.2 | 2.3 |
| PlayReady | PlayReady | PlayReady | — | — | — | — | — | — | — | 3.0 not yet | 3.0 not yet | 3.0 not yet | 3.0 not yet | 3.0 not yet | 3.0 not yet | 3.0 not yet | — | — | — | — | — | 3.0 not yet | 3.0 not yet | 3.0 not yet | 3.0 not yet |
| Supported displays | Supported displays | Supported displays | 2–3 | 2–4 | 2–4 | 2–4 | 2–4 | 3 | 3 | 3 (desktop) 4 (mobile, embedded) | 3 (desktop) 4 (mobile, embedded) | 4 | 4 | 4 | 4 | 4 | 2 | 2 | 2 | 2 | 3 | 4 | | 4 | 4 |
| /drm/radeon | /drm/radeon | /drm/radeon | | | | | | | — | — | — | — | — | — | — | — | | | | | — | — | — | — | — |
| /drm/amdgpu | /drm/amdgpu | /drm/amdgpu | — | — | — | | | | | | | | | | | | — | | | | | | | | |
* ↑ For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845.
* ↑ A PC would be one node.
* ↑ An APU combines a CPU and a GPU. Both have cores.
* ↑ Requires firmware support.
* 1 2 Requires firmware support.
* ↑ No SSE4. No SSSE3.
* ↑ Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
* ↑ Unified shaders : texture mapping units : render output units
* 1 2 To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
* ↑ To feed more than two displays, the additional panels must have native DisplayPort support. Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
* 1 2 DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.

## Processors
### APU lines

* Kaveri A-series APU
** Desktop budget and mainstream markets (FM2+): The Trinity / Richland APU line was replaced in January 2014 by the Kaveri APU line, as the third generation of A10, A8, A6 and A4 series for the desktop market. Top-of-the-line model in 2014 was the quad-core A10-7850K APU, with a 3.7 GHz core frequency and 4 MB L2 cache, incorporating a 720 MHz GPU with 512 stream processors and over 856 GFLOPS of total processing power. In 2015 and 2016 new models with two to four enhanced Steamroller B cores were released as Kaveri-refresh / Godavari. A10-7890K, the new top-of-the-line model, features an increased core frequency of 4.1 GHz and an 866 MHz GPU.
** Two or four CPU cores based on the Steamroller microarchitecture
** Socket FM2+-only, Socket FM2 is not supported, support for PCIe 3.0
** DDR3 Dual-channel (2x64-bit) memory controller
** AMD Heterogeneous System Architecture (HSA) 2.0
** SIP blocks: Unified Video Decoder, Video Coding Engine, TrueAudio
** Three to eight Compute Units (CUs) based on the revised GCN 2nd gen microarchitecture; 1 Compute Unit (CU) consists of 64 Unified Shader Processors : 4 Texture Mapping Units (TMUs) : 1 Render Output Unit (ROP)
** AMD Eyefinity up to 4 monitors, 4K Ultra HD support, DisplayPort 1.2 Support
** Select models support AMD Hybrid Graphics by using a Radeon R7 240 or R7 250 discrete graphics card.
** Integrated custom ARM Cortex-A5 co-processor with TrustZone Security Extensions
* Berlin APU - canceled
** Announced in 2013 by AMD the Berlin APU were targeted at the enterprise and server markets featuring four Steamroller cores, up to 512 stream processors and support for ECC memory.

### FX lines (discontinued)

In November 2013 AMD confirmed it would not update the FX series in 2014, neither its Socket AM3+ version, nor will it receive a Steamroller version with a new socket.
AMD however, released a Kaveri based FX-770K for desktop and FX-7600P for mobile which are basically APUs with their integrated graphics disabled similar to the Athlon X4 FM2+ line. Those APUs were released for OEMs only.

### Server lines (canceled)

AMD's server roadmaps for 2014 showed:
* Berlin APU - quad-core x86 Steamroller architecture (as described above) for 1 Processor (1P) compute and media clusters
* Berlin CPU - quad-core x86 Steamroller architecture for 1P web and enterprise services clusters
* Seattle CPU - 4/8 core AArch64 Cortex-A57 architecture (Opteron A1100) for 1P web and enterprise services clusters
* Warsaw CPU - up to 16 core x86 Piledriver (2nd gen Bulldozer) architecture (Opteron 6338P and 6370P) for 2P/4P servers
However, plans for Steamroller Opteron products were cancelled, likely due to the poor energy efficiency achieved in this generation of the Bulldozer architecture. Energy efficiency was greatly increased in the following generation, Excavator, which exceeded Jaguar in performance per watt, and approximately doubled performance/watt over Steamroller (for example 20.74 pt/W vs 10.85 pt/W when comparing similar mobile APUs using rough arbitrary metrics).