# Penryn (microarchitecture)

In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23. In Core 2 processors, it is used with the code names Penryn (Socket P), Wolfdale (LGA 775) and Yorkfield (MCM, LGA 775), some of which are also sold as Celeron, Pentium and Xeon processors. In the Xeon brand, the Wolfdale-DP and Harpertown code names are used for LGA 771 based MCMs with two or four active Wolfdale cores.
Architectural improvements over 65-nanometer Core 2 CPUs include a new divider with reduced latency, a new shuffle engine, and SSE4.1 instructions (some of which are enabled by the new single-cycle shuffle engine).
Maximum L2 cache size per chip was increased from 4 to 6 MB, with L2 associativity increased from 16-way to 24-way. Cut-down versions with 3 MB L2 also exist, which are commonly called Penryn-3M and Wolfdale-3M as well as Yorkfield-6M, respectively. The single-core version of Penryn, listed as Penryn-L here, is not a separate model like Merom-L but a version of the Penryn-3M model with only one active core.

## CPU List

| Processor | Brand name | Model (list) | Cores | L2 Cache | Socket | TDP |
| Penryn-L | Core 2 Solo | SU3xxx | 1 | 3 MB | BGA956 | 5.5 W |
| Penryn-3M | Core 2 Duo | SU7xxx | 2 | 3 MB | BGA956 | 10 W |
| Penryn-3M | Core 2 Duo | SU9xxx | 2 | 3 MB | BGA956 | 10 W |
| Penryn | Core 2 Duo | SL9xxx | 2 | 6 MB | BGA956 | 17 W |
| Penryn | Core 2 Duo | SP9xxx | 2 | 6 MB | BGA956 | 25/28 W |
| Penryn-3M | Core 2 Duo | P7xxx | 2 | 3 MB | Socket P FCBGA6 | 25 W |
| Penryn-3M | Core 2 Duo | P8xxx | 2 | 3 MB | Socket P FCBGA6 | 25 W |
| Penryn | Core 2 Duo | P9xxx | 2 | 6 MB | Socket P FCBGA6 | 25 W |
| Penryn-3M | Core 2 Duo | T6xxx | 2 | 2 MB | Socket P FCBGA6 | 35 W |
| Penryn-3M | Core 2 Duo | T8xxx | 2 | 3 MB | Socket P FCBGA6 | 35 W |
| Penryn | Core 2 Duo | T9xxx | 2 | 6 MB | Socket P FCBGA6 | 35 W |
| Penryn | Core 2 Duo | E8x35 | 2 | 6 MB | Socket P | 35-55 W |
| Penryn-QC | Core 2 Quad | Q9xxx | 4 | 2x3-2x6 MB | Socket P | 45 W |
| Penryn XE | Core 2 Extreme | X9xxx | 2 | 6 MB | Socket P | 44 W |
| Penryn-QC | Core 2 Extreme | QX9xxx | 4 | 2x6 MB | Socket P | 45 W |
| Penryn-3M | Celeron | T3xxx | 2 | 1 MB | Socket P | 35 W |
| Penryn-3M | Celeron | SU2xxx | 2 | 1 MB | μFC-BGA 956 | 10 W |
| Penryn-L | Celeron | 9x0 | 1 | 1 MB | Socket P | 35 W |
| Penryn-L | Celeron | 7x3 | 1 | 1 MB | μFC-BGA 956 | 10 W |
| Penryn-3M | Pentium | T4xxx | 2 | 1 MB | Socket P | 35 W |
| Penryn-3M | Pentium | SU4xxx | 2 | 2 MB | μFC-BGA 956 | 10 W |
| Penryn-L | Pentium | SU2xxx | 1 | 2 MB | μFC-BGA 956 | 5.5 W |
| Wolfdale-3M |
| Wolfdale-3M | Celeron | E3xxx | 2 | 1 MB | LGA 775 | 65 W |
| Wolfdale-3M | Pentium | E2210 | 2 | 1 MB | LGA 775 | 65 W |
| Wolfdale-3M | Pentium | E5xxx | 2 | 2 MB | LGA 775 | 65 W |
| Wolfdale-3M | Pentium | E6xxx | 2 | 2 MB | LGA 775 | 65 W |
| Wolfdale-3M | Core 2 Duo | E7xxx | 2 | 3 MB | LGA 775 | 65 W |
| Wolfdale | Core 2 Duo | E8xxx | 2 | 6 MB | LGA 775 | 65 W |
| Wolfdale | Xeon | 31x0 | 2 | 6 MB | LGA 775 | 45-65 W |
| Wolfdale-CL | Xeon | 30x4 | 1 | 6 MB | LGA 771 | 30 W |
| Wolfdale-CL | Xeon | 31x3 | 2 | 6 MB | LGA 771 | 65 W |
| Yorkfield | Xeon | X33x0 | 4 | 2×3–2×6 MB | LGA 775 | 65–95 W |
| Yorkfield-CL | Xeon | X33x3 | 4 | 2×3–2×6 MB | LGA 771 | 80 W |
| Yorkfield-6M | Core 2 Quad | Q8xxx | 4 | 2×2 MB | LGA 775 | 65–95 W |
| Yorkfield-6M | Core 2 Quad | Q9x0x | 4 | 2×3 MB | LGA 775 | 65–95 W |
| Yorkfield | Core 2 Quad | Q9x5x | 4 | 2×6 MB | LGA 775 | 65–95 W |
| Yorkfield XE | Core 2 Extreme | QX9xxx | 4 | 2×6 MB | LGA 775 | 130–136 W |
| Yorkfield XE | Core 2 Extreme | QX9xx5 | 4 | 2×6 MB | LGA 771 | 150 W |
| Wolfdale-DP | Xeon | E52xx | 2 | 6 MB | LGA 771 | 65 W |
| Wolfdale-DP | Xeon | L52xx | 2 | 6 MB | LGA 771 | 20-55 W |
| Wolfdale-DP | Xeon | X52xx | 2 | 6 MB | LGA 771 | 80 W |
| Harpertown | Xeon | E54xx | 4 | 2×6 MB | LGA 771 | 80 W |
| Harpertown | Xeon | L54xx | 4 | 2×6 MB | LGA 771 | 40-50 W |
| Harpertown | Xeon | X54xx | 4 | 2×6 MB | LGA 771 | 120-150 W |

## Processor cores

The processors of the Core microarchitecture can be categorized by number of cores, cache size, and socket; each combination of these has a unique code name and product code that is used across a number of brands. For instance, code name "Allendale" with product code 80557 has two cores, 2 MB L2 cache and uses the desktop socket 775, but has been marketed as Celeron, Pentium, Core 2 and Xeon, each with different sets of features enabled. Most of the mobile and desktop processors come in two variants that differ in the size of the L2 cache, but the specific amount of L2 cache in a product can also be reduced by disabling parts at production time. Wolfdale-DP and all quad-core processors except Dunnington QC are multi-chip modules combining two dies. For the 65 nm processors, the same product code can be shared by processors with different dies, but the specific information about which one is used can be derived from the stepping.
| | fab | cores | Mobile | Mobile | Desktop, UP Server | Desktop, UP Server | CL Server | DP Server | MP Server |
| Single-Core 45 nm | 45 nm | 1 | | Penryn-L 80585 | | | | Wolfdale-CL 80588 | |
| Dual-Core 45 nm | 45 nm | 2 | Penryn-3M 80577 | Penryn 80576 | Wolfdale-3M 80571 | Wolfdale 80570 | Wolfdale-CL 80588 | Wolfdale-DP 80573 | |
| Quad-Core 45 nm | 45 nm | 4 | | Penryn-QC 80581 | Yorkfield-6M 80580 | Yorkfield 80569 | Yorkfield-CL 80584 | Harpertown 80574 | Dunnington QC 80583 |
| Six-Core 45 nm | 45 nm | 6 | | | | | | | Dunnington 80582 |

### Steppings using 45 nm process

| | | | | | | Mobile (Penryn) | Mobile (Penryn) | Mobile (Penryn) | Desktop (Wolfdale) | Desktop (Wolfdale) | Desktop (Wolfdale) | Desktop (Wolfdale) | Desktop (Yorkfield) | Desktop (Yorkfield) | Server (Wolfdale-DP, Harpertown, Dunnington) |
| Stepping | Released | Area | CPUID | L2 cache | Max. clock | Celeron | Pentium | Core 2 | Celeron | Pentium | Core 2 | Xeon | Core 2 | Xeon | Xeon |
| C0 | Nov 2007 | 107 mm$^2$ | 10676 | 6 MB | 3.00 GHz | | | E8000 P7000 T8000 T9000 P9000 SP9000 SL9000 X9000 | | | E8000 | 3100 | QX9000 | | 5200 5400 |
| M0 | Mar 2008 | 82 mm$^2$ | 10676 | 3 MB | 2.40 GHz | 7xx | | SU3000 P7000 P8000 T8000 SU9000 | | E5000 E2000 | E7000 | | | | |
| C1 | Mar 2008 | 107 mm$^2$ | 10677 | 6 MB | 3.20 GHz | | | | | | | | Q9000 QX9000 | 3300 | |
| M1 | Mar 2008 | 82 mm$^2$ | 10677 | 3 MB | 2.50 GHz | | | | | | | | Q8000 Q9000 | 3300 | |
| E0 | Aug 2008 | 107 mm$^2$ | 1067A | 6 MB | 3.33 GHz | | | T9000 P9000 SP9000 SL9000 Q9000 QX9000 | | | E8000 | 3100 | Q9000 Q9000S QX9000 | 3300 | 5200 5400 |
| R0 | Aug 2008 | 82 mm$^2$ | 1067A | 3 MB | 2.93 GHz | 7xx 900 SU2000 T3000 | T4000 SU2000 SU4000 | SU3000 T6000 SU7000 P8000 SU9000 | E3000 | E5000 E6000 | E7000 | | Q8000 Q8000S Q9000 Q9000S | 3300 | |
| A1 | Sep 2008 | 503 mm$^2$ | 106D1 | 3 MB | 2.67 GHz | | | | | | | | | | 7400 |
In the model 23 (cpuid 01067xh), Intel started marketing stepping with full (6 MB) and reduced (3 MB) L2 cache at the same time, and giving them identical cpuid values. All steppings have the new SSE4.1 instructions. Stepping C1/M1 was a bug fix version of C0/M0 specifically for quad core processors and only used in those. Stepping E0/R0 adds two new instructions (XSAVE/XRSTOR) and replaces all earlier steppings.
In mobile processors, stepping C0/M0 is only used in the Intel Mobile 965 Express (Santa Rosa refresh) platform, whereas stepping E0/R0 supports the later Intel Mobile 4 Express (Montevina) platform.
Model 29 stepping A1 (cpuid 106d1h) adds an L3 cache as well as six instead of the usual two cores, which leads to an unusually large die size of 503 mm$^2$. As of February 2008, it has only found its way into the very high-end Xeon 7400 series (Dunnington).

## Roadmap

vteIntel CPU core roadmaps from P6 to Panther Lake :
Atom (ULV)
Node name
Pentium/Core
Microarch.
Step
Microarch.
Step
600 nm
P6
Pentium Pro (133 MHz)
500 nm
Pentium Pro (150 MHz)
350 nm
Pentium Pro (166–200 MHz)
Klamath
250 nm
Deschutes
Katmai
NetBurst
180 nm
Coppermine
Willamette
130 nm
Tualatin
Northwood
Pentium M
Banias
NetBurst(HT)
NetBurst(×2)
90 nm
Dothan
Prescott
Prescott‑2M
Smithfield
Tejas
Cedarmill (Tejas)
65 nm
Yonah
Nehalem (NetBurst)
Cedar Mill
Presler
Core
Merom
4 cores on mainstream desktop, DDR3 introduced
Bonnell
Bonnell
45 nm
Penryn
Nehalem
Nehalem
HT reintroduced, integrated MC, PCH L3-cache introduced, 256KB L2-cache/core
Saltwell
32 nm
Westmere
Introduced GPU on same package and AES-NI
Sandy Bridge
Sandy Bridge
On-die ring bus, no more non-UEFI motherboards
Silvermont
Silvermont
22 nm
Ivy Bridge
Haswell
Haswell
Fully integrated voltage regulator
Airmont
14 nm
Broadwell
Skylake
Skylake
DDR4 introduced on mainstream desktop
Goldmont
Goldmont
Kaby Lake
Coffee Lake
6 cores on mainstream desktop
Amber Lake
Mobile-only
Goldmont Plus
Goldmont Plus
Whiskey Lake
Mobile-only
Coffee Lake Refresh
8 cores on mainstream desktop
Comet Lake
10 cores on mainstream desktop
Sunny Cove
Cypress Cove (Rocket Lake)
Backported Sunny Cove microarchitecture for 14nm
Tremont
Tremont
10 nm
Skylake
Palm Cove (Cannon Lake)
Mobile-only
Sunny Cove
Sunny Cove (Ice Lake)
512 KB L2-cache/core
Willow Cove (Tiger Lake)
X$^e$ graphics engine
Gracemont
Gracemont
Intel 7 (10nm ESF)
Golden Cove
Golden Cove (Alder Lake)
Hybrid, DDR5, PCIe 5.0
Raptor Cove (Raptor Lake)
Crestmont
Crestmont
Intel 4
Redwood Cove
Meteor Lake
Mobile-only NPU, chiplet architecture
Skymont
Skymont
N3B (TSMC)
Lion Cove
Lunar Lake
Low power mobile only (9-30W)
? (TSMC)
Arrow Lake
Darkmont
Darkmont
18A
Cougar Cove
Panther Lake
Strike-through indicates cancelled processors
Bold names are microarchitectures
Italic names are future processors :