# SyntheSys Research

SyntheSys Research was a Silicon Valley test equipment company that existed from 1989 to 2010, located in Menlo Park, California. The company was founded by Tom and Jim Waschura, with technical help from other ex-Ampex employees Rob Verity and Kirk Handley, and early marketing help from Bob Haya who was Tom and Jim's roommate. The first product was a 160 Mbit/s bit error rate tester (BERT) called the BitAlyzer 160 that debuted in 1989. The company patented key technologies used in modern signal integrity test; notably Error Location Analysis and statistically deep eye-diagramming integrated with BERT measurement called BERTScope. The company was the first to combine Jitter sources in its test signal generators to permit popular Stressed-Eye testing. The company developed many products over its 21-year span, including specialty products for disk-drive, television, high-definition television, optical, telecommunications, and computer applications. In 2010, SyntheSys Research was purchased by Tektronix (a subsidiary of Danaher Corporation) in an M&A transaction and the BERTScope and BitAlyzer instruments became product lines in Tektronix's high-speed Oscilloscope divisions.

## Founding

The company was founded by Tom and Jim Waschura, identical twins who formerly worked for Ampex Corporation in Redwood City, California. Tom Waschura's electrical engineering degree from M.I.T. landed him a job at Ampex's Data Systems division working on tape recording and early parallel-transfer disk drives. Jim Waschura's software engineering background proved useful in Ampex's Video Systems division, working on 'still stores' used for broadcast television, especially news production. Tom left Ampex and the brothers created a partnership called Designware Associates to assist a fledgling company called Systems West create the first polar-orbiting satellite image retrieval system for commercial boating and fishing. Bob's electrical engineering degree from RPI helped him head up marketing and sales. Later, Tom recalled a senior engineer at Ampex, John Corcoran, working to add digital communications channels to analog tape recorders that Ampex manufactured. John and Tom employed a device known as a Bit Error Rate tester (BERT) that generated a pseudo-random series of bits to record and later to be played-back into the BERT device that verified that the bits had been reproduced correctly. This effort was undertaken about the same time early personal computers were becoming available, known as "PC/AT" or 80286-based personal computers. Whereas the BERT device indicated the number of bits that were incorrectly reproduced, it became clear that the effort of implementing a digital communications channel on an analog tape recorder would be greatly helped if it were clear which bits were in error—not just the quantity of the erred bits—and it seemed the new powerful personal computers ought to be able to do this. This became the genesis of Error Location Analysis technology that was later patented and implemented in all BitAlyzer and BERTScope products, and that was licensed to Hewlett Packard Company (later called Agilent Technologies, and now called Keysight) who implemented it in their popular 86130 3.0 Gbit/s BERT instrument.
The first BitAlyzer was developed in the garage of a residence in the Emerald Hills area of Redwood City owned by Bob Haya. Rob Verity and Kirk Handley, each a former co-worker of Tom Waschura's, developed hardware modules, while Tom Waschura developed the system design and Jim Waschura developed the software. Bob Haya is credited with coming up with the name BitAlyzer. The company was incorporated as SyntheSys Research because DesignWare was not available for use. The first patent was filed on Error Location Analysis technology. The company moved to a small business park in Redwood City, California, where it resided for about a year before finally moving to Edison Technology Park in Menlo Park, California.

## Key technologies
### Error Location Analysis

Error Location Analysis became a cornerstone technique for diagnosing problems with digital communications by identifying the precise location of bit-errors during a bit error rate testing session. Fundamental bit error rate testing is accomplished by comparing a communicated bit-stream with a reference (correct) bit-stream. The correct bits may be stored in a memory device or synthesized in real-time as reception of the communicated bit-stream occurs. It is common for these bit-streams to contain pseudo-random binary sequence patterns that permit easy synchronization with just a few correctly received consecutive bits. This self-synchronizing feature of PRBS patterns make them ideal for BERT testing. Traditional BERT devices possess generators that produce test bit-streams for output, and detectors that receive test bit-streams and count the number of bits being received and the number of mis-matches between the received and the reference bit-streams. Using the simple formula,
the BER is calculated. Error location analysis extends these fundamental features by employing a hardware memory device that effectively stores the value of the received bit counter whenever a mismatching error is detected. This produces a stream of error locations that are processed in real-time, and/or stored for post-processing. Many types of statistical processing algorithms were developed by SyntheSys Research, producing a comprehensive set of error location analysis tools.
Error location analysis tools:
* Basic BER
* Burst BER Statistics
** Define a burst using 'Minimum Error Free Interval' and 'Minimum Burst Length' parameters
* Burst Length Histogram
* Error Free Interval Histogram
* Errors Modulo-N Histogram
* Errors Modulo External Hardware Trigger Histogram
* Pattern-Sensitivity Histogram
* 2D Error Mapping
* Simulated Error Correction Coding
** Define hypothetical multidimensional Reed-Solomon error correcting architecture to act as a filter and view all other analyses after correctable errors are removed from the error location stream.
One of the earliest uses of 2D Error Mapping was applied to the recorded errors from a transverse-scan digital tape recording device made by Ampex Corporation. The accompanying Media Scan image demonstrates that error locations are key to recognizing that multiple error-producing syndromes are occurring simultaneously and affecting the total bit error rate experienced during the test recording session.
This technique is described in U.S. Patent US6636994 B1

### Run-time Delay Calibration

Being able to position a data signal relative to a clock signal with very high resolution and accuracy is an important capability in a BERT. This feature is used on the output of a data generator to ensure the clock signal rising edge corresponds to the middle of the data signal's bit window, since both signals will use different cabling and routing and can be mis-matched. The capability is also used on the receiver side of a BERT where a separate delay device is used to evaluate BER when the clock signal is not perfectly aligned in the middle of the data signal's bit cell. As the clock signal approaches either side of the data bit cell window, the quantity of errors will rise and the steepness of the rise is based on the amount of jitter between the clock and data signals. This type of analysis is called a Bathtub Curve, which demonstrates a degree of system margin. This is an example of a signal integrity physical-layer test, utilizing BER measurement capability combined with accurate time delay capability.
There are numerous electronic circuits that will produce delay, ranging from different lengths of circuit-board traces that produce fixed amounts of delay, to voltage-controlled circuits that produce programmable amounts of delay. It is usual to combine fixed and variable portions with switches that enable different components when needed. Depending on manufacturing tolerances, temperature, and data-rate, however, the amount of delay achieved by a particular route may vary. Previous methods for building delay capabilities involved factory calibration of every combination of fixed and variable elements at all operating temperatures and data rates. This provided adjustment data that could be used to select and program fixed and variable elements to achieve a desired amount of delay for a given operating condition.
SyntheSys Research engineers, Andre Willis-Poskatcheev, Clint Fincher, and Tom Helmers developed a circuit sub-system for precisely measuring delay at run-time, requiring a few seconds to evaluate precise delay for all combination of fixed and variable elements in the current operating environment. This capability was an important selling-point, especially when utilized to produce eye-diagrams on very fast signals.
This technique is described in U.S. Patent EP 1560333 A3.

### Eye-diagramming on a BERT

BERT instruments are often found near oscilloscopes because they complement each other. The BERT provides the bottom-line capability of determining if digital bits are being communicated effectively, but if they are not, the oscilloscope provides the ability to see the underlying analog waveform used to communicate the digital bits. It is common for underlying analog problems, such as timing jitter or amplitude noise or slow rise-time, to translate into digital bit errors. Beginning in a digital television product called the DVA184-C, and then following with the high-definition video product HDVA-292, and every BERT product afterwards, SyntheSys Research engineers integrated the ability to display the analog eye-diagram of the signal being evaluated.
The notable advantage of this approach is two-fold. First, precisely the same electronic circuits and components that are used to produce the BER measurements are also used to produce the eye diagram display. This ensures that the differences between how two separate circuits would interpret the signal – owing to their unique frequency responses – are eliminated and there is perfect correlation between BER results and eye diagram results, which is very important and impossible to do otherwise. Second, the mechanism invented by Tom Waschura to create the eye diagram utilizes a counter and a variable-threshold comparator (in some instances, two comparators) to image the eye. By selecting different threshold levels in combination with certain time delays, individual pixels of the eye diagram are evaluated by counting the number of bits that exceed the threshold – or in the case of dual thresholds, are in between two thresholds. This capability is important because the speed of the evaluation is dependent on the clocking speed of the transmission that is often hundreds of times faster than the sampling rate of an oscilloscope. This is an important advantage in signal integrity test applications, where it is difficult to capture low-probability occurring events.
Based on deep measurements of a two-dimensional grid, the BERT instrument was capable of making common waveform measurements such as rise time, jitter, amplitude, and so on.
This technique is described in U.S. Patent EP 1315327 A3.

### BER Contour

By combining eye diagramming techniques with precisely positioned BER measurements, Jim Waschura invented a technique of sweeping the interior of an eye diagram to curve-fit measurements to mathematical models representing the interior slopes of the eye diagram for random and deterministic effects. This technique is notable because many performance criteria are defined in terms of the eye opening at a specified probability level (e.g. 1E-12), that requires an impossible amount of data acquisition to measure directly. This technique allows for modest extrapolations to be performed to evaluate the 1E-12 eye opening with measurements that are acquired in only a few minutes.
This technique also became a very powerful means to communicate the strength of the BERTScope's eye diagramming capability since it demonstrates how eyes that appear open if sampled to a shallow depth - such as those sampled by contemporary oscilloscopes - very quickly could become closed if the underlying problem was a random process such as jitter or noise. See the accompanying picture and compare how wide open the middle eye diagram appears versus how quickly the eye width shrinks with longer test intervals because of the random jitter and the low slope of the contour it produces.

### Stressed-Eye Testing

During the analog to digital transition that occurred during the life-span of SyntheSys Research, many techniques were employed by engineers to evaluate digital transmission. Analog transmission had been characterized by modestly simple measurements of the analog waveform such as rise-time, signal-to-noise ratio and frequency response. Digital transmission, however, employed sophisticated coding and error correction and other mechanisms that could perfectly recreate digital bits even if the underlying analog waveform was quite bad, and made it much more difficult to have a single qualitative figure of merit for the performance of the digital transmission. BER was a very useful measure, but it didn't degrade politely like analog signal-to-noise measurements. In digital communications, a cliff-effect occurs which means communication is often perfect until it fails completely.
Early digital testing was focused on the transmitter to ensure that the waveform transmission characteristics met a standard set of characteristics for parameters such as rise time, amplitude, jitter, and so on. It was assumed that if the signal originated correctly, and was communicated well, that the receiver would interpret it properly and reproduce the correct bits. This was often augmented with modest frame-based checksum approaches for the receiver to finally validate the BER of what it had received.
As transmission rates increased, however, it became important to allocate the system performance margin between both the transmitter and the receiver, and this produced new requirements to evaluate the receivers in the communications system. Each standards-body and groups of engineers approached this problem differently. Early digital television standards were the first to employ testing with a 100-meter length of cable (later replaced by an electronic circuit called a cable clone) to validate that the signal may be received properly when used under stress. 10 Gb Ethernet and other standards employed jitter and noise-producing circuits to electronically degrade the transmission and produce a Stressed-Eye for testing. It became very important to have multiple sources of different types of amplitude noise and time-domain modulated jitter sources to produce a calibrated cocktail of degradations that would close the transmitted eye for receiver testing, but making calibrated jitter and noise sources required difficult engineering that had to be reproduced exactly each time receiver testing was to be performed. In 2005, with the introduction of the BERTScope 12500-S, SyntheSys Research provided the first built-in stressed-eye sources that greatly assisted engineers in performing popular stressed-eye receiver testing.

### ECC Emulation

To increase communications channel data rates, common techniques are applied such as speeding up clocking rates, and increasing the dimensions of modulation, and increasing coding efficiencies. Ultimately, channels become so optimized they are operating at the extents of their physical limitations, and in these cases, improving reliability is done by adding Forward error correction (FEC) also known as Error Correcting Code (ECC) capabilities that trade the overhead of transmitting extra information with the advantage of being able to correct errors during transmission. To design efficient FEC strategies it is important to know the profile of the raw errors in the underlying channel and Error Location Analysis proved very helpful for this purpose. Features like Burst Length Histogram helped engineers choose FEC interleave depths, and features like Block Error Histogram indicated the correction strengths required for full correction.
The Error Location Analysis feature aimed at the FEC application was called ECC Emulation. Using this feature, the system could be configured to produce full-range error analysis of a raw communications channel as-if it had a specified FEC architecture operating on it. FEC architectures were specified by configuring the number of rows and columns and tables in a hypothetical 3-dimensional interleave FEC system, together with correction strengths in each dimension. The system also enabled activity monitoring for each layer of correction capability to observe headroom when operating on live or pre-recorded raw error sessions.

## Key roles

Tom and Jim Waschura were co-founders. Tom Waschura transitioned into Chief Technical Officer role providing key technical leadership, numerous inventions, and patent portfolio management, while Jim Waschura transitioned from software engineering into general management and then into operations management roles.
Dr. Lutz P. Henckels began as a business consultant and then transitioned into the chief executive officer role in 2004.
At the time of the M&A transaction, the board of directors included John Sadler, Dr. Lutz P. Henckels, John Rockwell, Mike Pehl, and Jim Waschura (chairman). John Rockwell and Mike Pehl represented venture capital investor Advent International. Dr. Lutz P. Henckels was the CEO, and John Sadler was an outside independent board member. Tom Waschura was a board observer.
Key department heads included: Rob Verity (Engineering), Guy Foster (Marketing), Mike Penta (Sales), Dennis Palmer (Operations), and Lincoln Turner (Finance).
Key support personnel included Sonia Isaac, Dawna Horsley, Maria Alvarado, Maria Vasta, Janet Hallock, and Roger Wong.
Key inventors included: Tom Waschura, Jim Waschura, Rob Verity, Andre Willis-Poskatcheev, Clint Fincher, Kevin Ziegler, Keith Bertrand, Senthil Thandapani, Jeff Fincher, Tony von Ruden, Bill Prescott, Jiaxun (Stephen) Yu, Valera Fooksman, Tom Helmers, Sasikumar Gandhi, Cynthia Nakatani, Thomas Brennan-Marquez, Carlos Cuturrufo, and Michael Jennett.
Key marketing and sales engineers included: Steve Reinhold, Jim Dunford, Craig Hartwig, Darren Gray, Patrick Weisgarber, Charlie Schafer, Bent Hessen-Schmidt, John Smith, Allen Wang, and James Zhang.
Key operations employees included: Bert Carner, Steve Spangler, David Arnbrister, Mark Nguyen, Michael Bowman, Sandy Ly, Phat Ly, and Harrison Pham.
Key professional services were provided by Frank Rahmani of Cooley-Godward (Legal), John Advani of Frank Rimmerman (Accounting & Tax), Douglas Chaiken (Patent Law), Allen Madanipour (IT), and SVB Silicon Valley Bank.

## Products

| Product | Year Introduction | Segment | Description |
| BitAlyzer 160 | 1989 | BERT | 160 Mbit/s bit error rate tester with error location analysis features. |
| BitAlyzer 400 | 1992 | BERT | 400 Mbit/s bit error rate tester with error location analysis features. |
| BitAlyzer 25 | 1994 | BERT | 25 Mbit/s bit error rate tester with error location analysis features. |
| DVA-184C | 1996 | Video | Standard-definition digital television analyzer (SMPTE 259M) with jitter measurement and eye-diagramming features. |
| BitAlyzer 622 | 1998 | BERT | 622 Mbit/s bit error rate tester with error location analysis features. Later extended to 800 Mbit/s and 1 Gbit/s. |
| BitAlyzer 3600 | 1999 | BERT | 3.6 Gbit/s bit error rate tester with error location analysis features. |
| Multi-BERT | 1995 | BERT | 8-channel simultaneous fundamental BERT measurement. |
| HDVA-292 | 1998 | Video | High-definition video analyzer (SMPTE 292M) with jitter spectrum and eye-diagramming features. |
| HDSG-292 | 1999 | Video | High-definition video signal generator (SMPTE 292M) with synthesized and image-based test patterns. Features included basic motion and stress. |
| BitAlyzer 14400P | 2000 | BERT | 16-channel simultaneous BERT measurements. Separate instruments for generation and detection. Combined 14 Gbit/s capacity. |
| MVA-3000 | 2000 | Video | Combination of high-definition generator and analyzer in one compact instrument. |
| BERTScope 12500 | 2005 | BERT | 12.5 Gbit/s bit error rate tester with physical-layer testing including eye diagramming, jitter bathtub, Q-factor analysis, and error location analysis features. |
| BERTScope CR12500 | 2006 | BERT | Standalone clock-recovery instrument with programmable frequency generation up to 12.5 GHz and selectable bandwidth and peaking features. |
| BERTScope 12500-S | 2007 | BERT | BERTScope 12500 with built-in stress capability for generator outputs. |
| BERTScope 7500 | 2007 | BERT | 7.5 Gbit/s bit error rate tester with physical-layer testing including eye diagramming, jitter bathtub, Q-factor analysis, and error location analysis features. |
| BERTScope DPP12500 | 2008 | BERT | Four-tap clocked de-emphasis instrument for pre-conditioning transmitted signals using frequency spectrum shaping. |
| BERTScope 17500 | 2009 | BERT | 17.5 Gbit/s bit error rate tester with physical-layer testing, error location analysis, and built-in stress capability. |
| BERTScope 25000 | 2010 | BERT | 25.0 Gbit/s bit error rate tester with physical-layer testing, error location analysis, and built-in stress capability. |

### Awards

National Association of Broadcasters Editors Pick of Show Award 1996 - DVA184C
National Association of Broadcasters Editors Pick of Show Award 1998 - HDVA292
National Association of Broadcasters Editors Pick of Show Award 1999 - HDSG292
DesignCon DesignVision Award 2006 - BERTScope CR12500 Clock Recovery
DesignCon DesignVision Award 2009 - BERTScope DPP12500A Deemphasis Preprocessor
Frost & Sullivan's Product Differentiation Innovation Award 2005 - BERTScope
Network Systems Design Conference Best Supporting Solution Award 2005 - BERTScope S with Live Data Option.
EDN's 20th annual Innovation Awards Finalist 2010 - BERTscope 12500A for 100-Gbit/s Ethernet

## Bootstrap and Venture Backing

From 1989 through 2004, the company was bootstrap funded by proceeds from selling products. In 1999, the company entered into a license agreement with Agilent Technologies to license the company's Error Location Analysis intellectual property and patents and assist Agilent by implementing these features inside the Agilent 86130 BERT. This inflow allowed the company to grow, but more-importantly, allowed it to continue developing products through the 2001-2003 economic hard-times known as the Telecom disaster, related to the internet Dot-com bubble. During this time, many of Agilent's customers were affected and ultimately Agilent itself was restructured and the Lightwave Division in Santa Rosa, who was the main proponent of the 86130 BERT product line containing SyntheSys Research Error Location Analysis technology, was closed. Due to these economic factors, SyntheSys Research was able to get rights back to the licensed technology and began producing BERTScope products for sale.
In 2003, Tom and Jim Waschura were visited by Dr. Lutz P. Henckels, who had been the CEO of LeCroy Corporation, where he had been successful with a public stock offering. After considerable time analyzing the state of SyntheSys Research's team, technogy, and markets. The three concluded that growth opportunities warranted stepping-up the momentum of SyntheSys Research by raising venture capital and targeting BER testing for 10 Gbit/s Ethernet, optical and other high-speed serial communications channels and devices. Dr. Lutz P. Henckels became CEO in 2004 to execute this strategy.
In 2004, the venture capital arm of the Boston-based Advent International private equity company invested in series-A preferred stock and the board of directors were changed to provide Advent with two board of directors positions. This lasted throughout the remaining lifespan of the company.
During the next five years, the company developed important BERTScope products with integrated stressed-eye and physical-layer testing capability, and introduced innovative accessory products including the Digital Preemphasis Processor and Clock Recovery that led the market. It increased investments in sales channel and marketing activities and was successful at establishing BERTScope as an important brand in high-speed BERT test.

## Acquisition by Danaher-Tektronix

In 2008, the largest maker of Oscilloscopes in the United States, Tektronix, of Beaverton, Oregon and SyntheSys Research signed an OEM agreement to sell the SyntheSys Research CR12500 clock-recovery instrument through Tektronix's sales channel. This was important because Tektronix sold an equivalent-time (‘sampling’) form of oscilloscope that required a very good time reference input, and contemporary high-speed signals were outpacing the existing Tektronix clock-recovery capabilities. The Tektronix engineers, sales engineers, and customers were pleased with the high-performance of the SyntheSys Research clock-recovery units. This relationship provided both organizations some view into the other, and as BERT testing became an important feature for high-speed customers, and because Tektronix did not possess their own BERT test instrument, in 2009, the two companies initiated merger discussions that were finalized early in 2010 with an acquisition.
Within Tektronix, Brian Reich, was the main proponent of the acquisition, and he became the general manager responsible for the successful business and technical integration of SyntheSys Research into the high-performance oscilloscopes division of Tektronix. Other hands-on roles were fulfilled by Dan Morgan, Joy Conley, John Calvin, and Jit-loke Lim. During the transition, SyntheSys Research product manufacturing was moved to Oregon, and engineering and sales were moved into a newly opened Tektronix Silicon Valley design center in Santa Clara, California.