# Zilog Z800

The Zilog Z800 was a 16-bit microprocessor designed by Zilog and meant to be released in 1985. It was instruction compatible with their existing Z80, and differed primarily in having on-chip cache and a memory management unit (MMU) to provide a 16 MB address range. It also added a huge number of new more orthogonal instructions and addressing modes.
Zilog essentially ignored the Z800 in favor of their 32-bit Z80000 and the Z800 never entered mass production. After more than five years had elapsed since it was originally introduced, the effort was redubbed the Z280 in 1986. An actual product, the Z280 would ship in 1987 with almost the same design as the Z800, but this time implemented in CMOS.
The Z800 contrasts with Zilog's first 16-bit effort, the Zilog Z8000, in that the Z800 was intended to be Z80 compatible, while the Z8000 was only Z80-like and did not offer any direct compatibility. Zilog sought to rectify the lack of Z80 compatibility exhibited by the Z8000 when introducing the Z800, seeking to offer Z80 binary compatibility with an eightfold performance increase over the Z80, mirroring plans by National Semiconductor to incorporate emulation of the Intel 8080 in certain products in its own 32000 series of microprocessors.

## Short description

There was no expansion of the register set but the registers and instructions were significantly orthogonalized in order to make them more general-purpose and powerful. Many new 8-bit and 16-bit operations were added, and the HL, IX, and IY registers were upgraded from their rather limited possibilities as accumulators in the Z80 to more versatile accumulators. In addition to the register operands possible in the Z80, they could be used with immediate data, direct address, register indirect, or indexed operands, even program counter-relative. Eight-bit operations had even more possibilities, including stack pointer-relative addressing and a choice of 8-bit or 16-bits immediate offsets.
The address bus was expanded to 24-bits to address 16 MB of memory. The chip was offered with either a 19-bit external bus for 512kB RAM, or a full 24-bit bus for 16MB RAM, the advantage to the smaller bus was a smaller 40-pin package. Like the Z80 before it, the Z800 retained the internal DRAM controller and clock, but added 256 bytes of RAM that could be used either as "scratchpad" RAM, or as a cache. When used in cache mode the programmer could configure it as a data or instruction cache, or both, and the internal memory controller then used it to reduce access to (slower) external memory.
There were also ambitious provisions for multiprocessing and either loosely or tightly coupled slave processors, with or without shared global memory. This was known as the extended processing architecture and extended processing units (EPU).
Another change was the addition of an optional 16-bit data bus, which doubled the rate at which it could access memory if set up properly. Combined with the two address bus sizes this meant that the chip was offered in a total of four versions:
| part # | # of pins | data bus | address bus |
| Z8108 | 40 | 8-bit | 19-bit (512kB) |
| Z8116 | 40 | 16-bit | 19-bit (512kB) |
| Z8208 | 64 | 8-bit | 24-bit (16MB) |
| Z8216 | 64 | 16-bit | 24-bit (16MB) |

## Reason for the failure

The Z800 was, in most ways, a minicomputer-inspired "super Z80" that would run existing, and larger, programs at considerably higher speeds. However the address and data buses were multiplexed and the chip was, also in other respects, somewhat complicated to program and interface to. Calculation of exact execution times was also very much harder to do than for the Z80. Moreover, the plain Z80 were good enough for most applications at the time so the extra computing power was, in many cases, not worth the added complexity. Bad marketing seems to have hurt the product as well.
Hitachi developed the HD64180, as a less ambitious Z80 derivative. It had great success, probably because it is almost as simple to program and interface to as the original Z80.

## More successful Z80 derivatives (from Zilog)

Apart from the successful Zilog Z180 (developed largely by Hitachi) and Zilog Z182 other attempts were made to extend the Z80 architecture, the 32-bit Z380 (introduced 1994) was a commercial disappointment except for some specific telecom applications. On the other hand, the fast 24-bit eZ80 (introduced 2001) has been both commercially successful and won engineering awards. Unlike the Z800, Z280, and Z380, the eZ80 does not introduce many new instructions or addressing modes, in comparison to the original Z80, but instead primarily extends the 16-bit registers of the Z80 to 24 bits wide. This enables it to reach 256 times as much memory, and adds a fully pipelined execution unit that executes Z80 opcodes 4× as fast as the original.