# Zen 3

Zen 3 is the name for a CPU microarchitecture by AMD, released on November 5, 2020. It is the successor to Zen 2 and uses TSMC's 7 nm process for the chiplets and GlobalFoundries's 14 nm process for the I/O die on the server chips and 12 nm for desktop chips. Zen 3 powers Ryzen 5000 mainstream desktop processors (codenamed "Vermeer") and Epyc server processors (codenamed "Milan"). Zen 3 is supported on motherboards with 500 series chipsets; 400 series boards also saw support on select B450 / X470 motherboards with certain BIOSes. Zen 3 is the last microarchitecture before AMD switched to DDR5 memory and new sockets, which are AM5 for the desktop "Ryzen" chips alongside SP5 and SP6 for the EPYC server platform and sTRX8. According to AMD, Zen 3 has a 19% higher instructions per cycle (IPC) on average than Zen 2.
On April 1, 2022, AMD released the new Ryzen 6000 series for laptops/mobile, using an improved Zen 3+ architecture featuring notable architectural improvements to power efficiency and power management. And slightly later, on April 20, 2022, AMD would also release the Ryzen 7 5800X3D desktop processor, which increased gaming performance by around +15% on average by using for the very first time in a PC product, a 3D vertically stacked L3 cache. Specifically in the form of a 64MB L3 cache "3D V Cache" die made on the same TSMC N7 process as the 8-core Zen 3 CCD which it gets direct copper to copper hybrid bonded to.

## Features

As the first largely "ground up redesign" of the Zen CPU core since the architecture family's original release in early 2017 with Zen 1/Ryzen 1000, Zen 3 was a significant architectural improvement over its predecessors; having a very significant IPC increase of +19% over the prior Zen 2 architecture in addition to being capable of reaching higher clock speeds.
Like Zen 2, Zen 3 is composed of up to 2 core complex dies (CCD) along with a separate IO die containing the I/O components. A Zen 3 CCD is composed of a single core complex (CCX) containing 8 CPU cores and 32 MB of shared L3 cache, this is in contrast to Zen 2 where each CCD is composed of 2 CCX, each containing 4 cores paired with 16 MB of L3 cache. The new configuration allows all 8 cores of the CCX to directly communicate with each other and the L3 Cache instead of having to use the IO die through the Infinity Fabric.
Zen 3 (along with AMD's RDNA2 GPUs) also implemented Resizable BAR, an optional feature introduced in PCIe 2.0, that was branded as Smart Access Memory (SAM). This technology allows CPU to directly access all of compatible video card's VRAM. Intel and Nvidia have since implemented this feature as well.
* A de-lidded Ryzen 5 5600X. Only one 6-core CCD is present. The contacts for a second CCD are visible.
* Close-up of the CCD, taken under infrared lighting. This die was damaged by the de-lidding process.
* Close-up of the I/O die
In Zen 3, a single 32MB L3 cache pool is shared among all 8 cores in a chiplet, vs. Zen 2's two 16MB pools each shared among 4 cores in a core complex, of which there were two per chiplet. This new arrangement improves the cache hit rate as well as performance in situations that require cache data to be exchanged among cores, but increases cache latency from 39 cycles in Zen 2 to 46 clock cycles and halves per-core cache bandwidth, although both problems are partially mitigated by higher clock speeds. Total cache bandwidth on all 8 cores combined remains the same due to power consumption concerns. L2 cache capacity and latency remain the same at 512KB and 12 cycles. All cache read and write operations are done at 32 bytes per cycle.
On April 20, 2022, AMD released the R7 5800X3D. It features, for the first time in a desktop PC product, 3D-stacked vertical L3 cache. Its extra 64MB comes via a TSMC N7 (7nm) "3D V Cache" die direct copper to copper hybrid bonded right on top of the 8-core Zen 3 CCD's usual 32MB, increasing the CPU's total L3 cache capacity to 96MB and bringing significant performance improvements for gaming in particular; now rivalling contemporary high-end consumer processors while being much more power efficient and running on older, cheaper motherboards using affordable DDR4 memory. And despite now spanning multiple dies and being three times larger (96MB vs 32MB), the L3 cache's performance remains nearly identical; with X3D only adding around ≈+2ns via an additional three to four cycles of latency. It would later be followed by the Ryzen 5 5600X3D and Ryzen 7 5700X3D for lower-end market segments, and succeeded by the Ryzen 7000X3D family of 3D V Cache equipped Zen 4 processors on the newer socket AM5 platform.

### Improvements

Zen 3 has made the following improvements over Zen 2:
* An increase of 19% in instructions per clock
* The base core chiplet has a single eight-core complex (versus two four-core complexes in Zen 2)
* A unified 32MB L3 cache pool equally available to all 8 cores in a chiplet, vs Zen 2's two 16MB pools each shared among 4 cores in a core complex.
** On mobile: A unified 16MB L3
* A unified 8-core CCX (from 2x 4-core CCX per CCD)
* Increased branch prediction bandwidth. L1 branch target buffer size increased to 1024 entries (vs 512 in Zen 2)
* New instructions
** VAES – 256-bit Vector AES instructions
** INVLPGB – Broadcast TLB flushing
** CET_SS – Control-flow Enforcement Technology / Shadow Stack
* Improved integer units
** 96 entry integer scheduler (up from 92)
** 192 entry physical register file (up from 180)
** 10 issue per cycle (up from 7)
** 256 entry reorder-buffer (up from 224)
** fewer cycles for DIV/IDIV ops (10...20 from 16...46)
* Improved floating point units
** 6 μOP dispatch width (up from 4)
** FMA latency reduced by 1 cycle (down from 5 to 4)
* Additional 64MB 3D vertically stacked dense library L3 cache (in -X3D models)

## Feature tables
### APUs

APU features table

## Products

On October 8, 2020, AMD announced four Zen 3-based desktop Ryzen processors, consisting of one Ryzen 5, one Ryzen 7, and two Ryzen 9 CPUs and featuring between 6 and 16 cores.

### Desktop CPUs

The Ryzen 5000 series desktop CPUs are codenamed Vermeer. The models in the second table are based on Cezanne APUs with the integrated GPU disabled. Meanwhile the Ryzen Threadripper Pro 5000 series were codenamed Chagall.
Common features of Ryzen 5000 desktop CPUs:
* Socket: AM4.
* All the CPUs support DDR4-3200 in dual-channel mode.
* All the CPUs support 24 PCIe 4.0 lanes. 4 of the lanes are reserved as link to the chipset.
* No integrated graphics.
* L1 cache: 64 KB per core (32 KB data + 32 KB instruction).
* L2 cache: 512 KB per core.
* Fabrication process: TSMC 7FF.
| Branding and model | Branding and model | Cores (threads) | Thermal solution | Clock rate (GHz) | Clock rate (GHz) | L3 cache (total) | TDP | Chiplets | Core config | Release date | MSRP |
| Branding and model | Branding and model | Cores (threads) | Thermal solution | Base | Boost | L3 cache (total) | TDP | Chiplets | Core config | Release date | MSRP |
| Ryzen 9 | 5950X | 16 (32) | — | 3.4 | 4.9 | 64 MB | 105 W | 2 × CCD 1 × I/OD | 2 × 8 | Nov 5, 2020 | US $799 |
| Ryzen 9 | 5900XT | 16 (32) | — | 3.3 | 4.8 | 64 MB | 105 W | 2 × CCD 1 × I/OD | 2 × 8 | Jul 31, 2024 | US $349 |
| Ryzen 9 | 5900X | 12 (24) | — | 3.7 | 4.8 | 64 MB | 105 W | 2 × CCD 1 × I/OD | 2 × 6 | Nov 5, 2020 | US $549 |
| Ryzen 9 | 5900 | 12 (24) | — | 3.0 | 4.7 | 64 MB | 65 W | 2 × CCD 1 × I/OD | 2 × 6 | Jan 12, 2021 | OEM |
| Ryzen 9 | PRO 5945 | 12 (24) | — | 3.0 | 4.7 | 64 MB | 65 W | 2 × CCD 1 × I/OD | 2 × 6 | Sep 2022 | OEM |
| Ryzen 7 | 5800X3D | 8 (16) | — | 3.4 | 4.5 | 96 MB | 105 W | 1 × CCD 1 × I/OD | 1 × 8 | Apr 20, 2022 | US $449 |
| Ryzen 7 | 5800XT | 8 (16) | Wraith Prism | 3.8 | 4.8 | 32 MB | 105 W | 1 × CCD 1 × I/OD | 1 × 8 | Jul 31, 2024 | US $249 |
| Ryzen 7 | 5800X | 8 (16) | — | 3.8 | 4.7 | 32 MB | 105 W | 1 × CCD 1 × I/OD | 1 × 8 | Nov 5, 2020 | US $449 |
| Ryzen 7 | 5800 | 8 (16) | — | 3.4 | 4.6 | 32 MB | 65 W | 1 × CCD 1 × I/OD | 1 × 8 | Jan 12, 2021 | OEM |
| Ryzen 7 | 5700X3D | 8 (16) | — | 3.0 | 4.1 | 96 MB | 105 W | 1 × CCD 1 × I/OD | 1 × 8 | Jan 31, 2024 | US $249 |
| Ryzen 7 | 5700X | 8 (16) | — | 3.4 | 4.6 | 32 MB | 65 W | 1 × CCD 1 × I/OD | 1 × 8 | Apr 4, 2022 | US $299 |
| Ryzen 7 | PRO 5845 | 8 (16) | — | 3.4 | 4.6 | 32 MB | 65 W | 1 × CCD 1 × I/OD | 1 × 8 | Sep 2022 | OEM |
| Ryzen 5 | 5600X3D | 6 (12) | — | 3.3 | 4.4 | 96 MB | 105 W | 1 × CCD 1 × I/OD | 1 × 6 | Jul 7, 2023 US Only | US $229 |
| Ryzen 5 | 5600X | 6 (12) | Wraith Stealth | 3.7 | 4.6 | 32 MB | 65 W | 1 × CCD 1 × I/OD | 1 × 6 | Nov 5, 2020 | US $299 |
| Ryzen 5 | 5600 | 6 (12) | Wraith Stealth | 3.5 | 4.4 | 32 MB | 65 W | 1 × CCD 1 × I/OD | 1 × 6 | Apr 4, 2022 | US $199 |
| Ryzen 5 | PRO 5645 | 6 (12) | — | 3.7 | 4.6 | 32 MB | 65 W | 1 × CCD 1 × I/OD | 1 × 6 | Sep 2022 | OEM |
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* ↑ Core Complexes (CCX) × cores per CCX
Common features of Ryzen 5000 (Cezanne) desktop CPUs:
* Socket: AM4.
* CPUs support DDR4-3200 in dual-channel mode.
* L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
* L2 cache: 512 KB per core.
* CPUs support 24 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset.
* No integrated graphics.
* Fabrication process: TSMC 7FF.
| Branding and model | Branding and model | Cores (threads) | Thermal solution | Clock rate (GHz) | Clock rate (GHz) | L3 cache (total) | TDP | Core config | Release date | MSRP (USD) |
| Branding and model | Branding and model | Cores (threads) | Thermal solution | Base | Boost | L3 cache (total) | TDP | Core config | Release date | MSRP (USD) |
| Ryzen 7 | 5700 | 8 (16) | Wraith Stealth | 3.7 | 4.6 | 16 MB | 65 W | 1 × 8 | Apr 4, 2022 (OEM), Dec 21, 2023 (retail) | $179 |
| Ryzen 5 | 5500 | 6 (12) | Wraith Stealth | 3.6 | 4.2 | 16 MB | 65 W | 1 × 6 | Apr 4, 2022 | $159 |
| Ryzen 3 | 5100 | 4 (8) | – | 3.8 | 4.2 | 8 MB | 65 W | 1 × 4 | 2023 | OEM |
* v
* t
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* ↑ Core Complexes (CCX) × cores per CCX
5100, 5500, and 5700 have no ECC support like non-Pro Ryzen 5000 Desktop APUs.
Common features of Ryzen 5000 workstation CPUs:
* Socket: sWRX8.
* All the CPUs support DDR4-3200 in octa-channel mode.
* L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
* L2 cache: 512 KB per core.
* All the CPUs support 128 PCIe 4.0 lanes. 8 of the lanes are reserved as link to the chipset.
* No integrated graphics.
* Fabrication process: TSMC 7FF.
| Branding and Model | Branding and Model | Cores (threads) | Clock rate (GHz) | Clock rate (GHz) | L3 cache (total) | TDP | Chiplets | Core config | Release date | MSRP |
| Branding and Model | Branding and Model | Cores (threads) | Base | Boost | L3 cache (total) | TDP | Chiplets | Core config | Release date | MSRP |
| Ryzen Threadripper PRO | 5995WX | 64 (128) | 2.7 | 4.5 | 256 MB | 280 W | 8 × CCD 1 × I/OD | 8 × 8 | Mar 8, 2022 (OEM) / ? (retail) | OEM / US $6500 |
| Ryzen Threadripper PRO | 5975WX | 32 (64) | 3.6 | 4.5 | 128 MB | 280 W | 4 × CCD 1 × I/OD | 4 × 8 | Mar 8, 2022 (OEM) / ? (retail) | OEM / US $3300 |
| Ryzen Threadripper PRO | 5965WX | 24 (48) | 3.8 | 4.5 | 128 MB | 280 W | 4 × CCD 1 × I/OD | 4 × 6 | Mar 8, 2022 (OEM) / ? (retail) | OEM / US $2400 |
| Ryzen Threadripper PRO | 5955WX | 16 (32) | 4.0 | 4.5 | 64 MB | 280 W | 2 × CCD 1 × I/OD | 2 × 8 | Mar 8, 2022 | OEM |
| Ryzen Threadripper PRO | 5945WX | 12 (24) | 4.1 | 4.5 | 64 MB | 280 W | 2 × CCD 1 × I/OD | 2 × 6 | Mar 8, 2022 | OEM |
* v
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* ↑ Core Complexes (CCX) × cores per CCX

### Desktop APUs
#### Cezanne

Common features of Ryzen 5000 desktop APUs:
* Socket: AM4.
* All the CPUs support DDR4-3200 in dual-channel mode.
* L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
* L2 cache: 512 KB per core.
* All the CPUs support 24 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset.
* Includes integrated GCN 5th generation GPU.
* Fabrication process: TSMC 7FF.
| Branding and model | Branding and model | CPU | CPU | CPU | CPU | CPU | GPU | GPU | GPU | Thermal solution | TDP | Release date | MSRP |
| Branding and model | Branding and model | Cores (threads) | Clock rate (GHz) | Clock rate (GHz) | L3 cache (total) | Core config | Clock (MHz) | Config | Processing power (GFLOPS) | Thermal solution | TDP | Release date | MSRP |
| Branding and model | Branding and model | Cores (threads) | Base | Boost | L3 cache (total) | Core config | Clock (MHz) | Config | Processing power (GFLOPS) | Thermal solution | TDP | Release date | MSRP |
| Ryzen 7 | 5700G | 8 (16) | 3.8 | 4.6 | 16 MB | 1 × 8 | 2000 | 512:32:8 8 CU | 2048 | Wraith Stealth | 65 W | Apr 13, 2021 (OEM), Aug 5, 2021 (retail) | US $359 |
| Ryzen 7 | 5700GE | 8 (16) | 3.2 | 4.6 | 16 MB | 1 × 8 | 2000 | 512:32:8 8 CU | 2048 | Wraith Stealth | 35 W | Apr 13, 2021 | OEM |
| Ryzen 5 | 5600GT | 6 (12) | 3.6 | 4.6 | 16 MB | 1 × 6 | 1900 | 448:28:8 7 CU | 1702.4 | Wraith Stealth | 65 W | Jan 31, 2024 | US $140 |
| Ryzen 5 | 5600G | 6 (12) | 3.9 | 4.4 | 16 MB | 1 × 6 | 1900 | 448:28:8 7 CU | 1702.4 | Wraith Stealth | 65 W | Apr 13, 2021 (OEM), Aug 5, 2021 (retail) | US $259 |
| Ryzen 5 | 5600GE | 6 (12) | 3.4 | 4.4 | 16 MB | 1 × 6 | 1900 | 448:28:8 7 CU | 1702.4 | Wraith Stealth | 35 W | Apr 13, 2021 | OEM |
| Ryzen 5 | 5500GT | 6 (12) | 3.6 | 4.4 | 16 MB | 1 × 6 | 1900 | 448:28:8 7 CU | 1702.4 | Wraith Stealth | 65 W | Jan 31, 2024 | US $125 |
| Ryzen 3 | 5300G | 4 (8) | 4.0 | 4.2 | 8 MB | 1 × 4 | 1700 | 384:24:8 6 CU | 1305.6 | OEM | 65 W | Apr 13, 2021 | OEM |
| Ryzen 3 | 5300GE | 4 (8) | 3.6 | 4.2 | 8 MB | 1 × 4 | 1700 | 384:24:8 6 CU | 1305.6 | OEM | 35 W | Apr 13, 2021 | OEM |
* v
* t
* e
* ↑ Core Complexes (CCX) × cores per CCX
* ↑ Unified shaders : texture mapping units : render output units and compute units (CU)
* ↑ Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
* ↑ All of the iGPUs are branded as AMD Radeon Graphics.
* 1 2 3 4 5 6 Model also available as PRO version as 5350GE, 5350G, 5650GE, 5650G, 5750GE, 5750G, released June 1, 2021.
* "AMD Ryzen 3 PRO 5350GE". AMD.
* "AMD Ryzen 3 PRO 5350G". AMD.
* "AMD Ryzen 5 PRO 5650GE". AMD.
* "AMD Ryzen 5 PRO 5650G". AMD.
* "AMD Ryzen 7 PRO 5750GE". AMD.
* "AMD Ryzen 7 PRO 5750G". AMD.
* btarunr (June 1, 2021). "AMD Announces Ryzen 5000G and PRO 5000G Desktop Processors". TechPowerUp.

### Mobile APUs
#### Cezanne

| Branding and Model | Branding and Model | CPU | CPU | CPU | CPU | CPU | GPU | GPU | GPU | GPU | TDP | Release date |
| Branding and Model | Branding and Model | Cores (Threads) | Clock rate (GHz) | Clock rate (GHz) | L3 cache (total) | Core config | Model | Clock (GHz) | Config | Processing power (GFLOPS) | TDP | Release date |
| Branding and Model | Branding and Model | Cores (Threads) | Base | Boost | L3 cache (total) | Core config | Model | Clock (GHz) | Config | Processing power (GFLOPS) | TDP | Release date |
| Ryzen 9 | 5980HX | 8 (16) | 3.3 | 4.8 | 16 MB | 1 × 8 | Radeon Graphics | 2.1 | 512:32:8 8 CUs | 2150.4 | 35–54 W | Jan 12, 2021 |
| Ryzen 9 | 5980HS | 8 (16) | 3.0 | 4.8 | 16 MB | 1 × 8 | Radeon Graphics | 2.1 | 512:32:8 8 CUs | 2150.4 | 35 W | Jan 12, 2021 |
| Ryzen 9 | 5900HX | 8 (16) | 3.3 | 4.6 | 16 MB | 1 × 8 | Radeon Graphics | 2.1 | 512:32:8 8 CUs | 2150.4 | 35–54 W | Jan 12, 2021 |
| Ryzen 9 | 5900HS | 8 (16) | 3.0 | 4.6 | 16 MB | 1 × 8 | Radeon Graphics | 2.1 | 512:32:8 8 CUs | 2150.4 | 35 W | Jan 12, 2021 |
| Ryzen 7 | 5800H | 8 (16) | 3.2 | 4.4 | 16 MB | 1 × 8 | Radeon Graphics | 2.0 | 512:32:8 8 CUs | 2048 | 35–54 W | Jan 12, 2021 |
| Ryzen 7 | 5800HS | 8 (16) | 2.8 | 4.4 | 16 MB | 1 × 8 | Radeon Graphics | 2.0 | 512:32:8 8 CUs | 2048 | 35 W | Jan 12, 2021 |
| Ryzen 7 | 5800U | 8 (16) | 1.9 | 4.4 | 16 MB | 1 × 8 | Radeon Graphics | 2.0 | 512:32:8 8 CUs | 2048 | 10–25 W | Jan 12, 2021 |
| Ryzen 5 | 5600H | 6 (12) | 3.3 | 4.2 | 16 MB | 1 × 6 | Radeon Graphics | 1.8 | 448:28:8 7 CUs | 1612.8 | 35–54 W | Jan 12, 2021 |
| Ryzen 5 | 5600HS | 6 (12) | 3.0 | 4.2 | 16 MB | 1 × 6 | Radeon Graphics | 1.8 | 448:28:8 7 CUs | 1612.8 | 35 W | Jan 12, 2021 |
| Ryzen 5 | 5600U | 6 (12) | 2.3 | 4.2 | 16 MB | 1 × 6 | Radeon Graphics | 1.8 | 448:28:8 7 CUs | 1612.8 | 10–25 W | Jan 12, 2021 |
| Ryzen 5 | 5560U | 6 (12) | 2.3 | 4.0 | 8 MB | 1 × 6 | Radeon Graphics | 1.6 | 384:24:8 6 CUs | 1228.8 | 10–25 W | Jan 12, 2021 |
| Ryzen 3 | 5400U | 4 (8) | 2.7 | 4.1 | 8 MB | 1 × 4 | Radeon Graphics | 1.6 | 384:24:8 6 CUs | 1228.8 | 10–25 W | Jan 12, 2021 |
* v
* t
* e
* ↑ All of the iGPUs are branded as AMD Radeon Graphics.
* ↑ Core Complexes (CCX) × cores per CCX
* ↑ Unified shaders : texture mapping units : render output units and compute units (CU)
* ↑ Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
* 1 2 3 Model also available as PRO version as 5450U, 5650U, 5850U, released on March 16, 2021.

#### Barceló

| Branding and model | Branding and model | CPU | CPU | CPU | CPU | CPU | GPU | GPU | GPU | GPU | TDP | Release date |
| Branding and model | Branding and model | Cores (Threads) | Clock rate (GHz) | Clock rate (GHz) | L3 cache (total) | Core config | Model | Clock (GHz) | Config | Processing power (GFLOPS) | TDP | Release date |
| Branding and model | Branding and model | Cores (Threads) | Base | Boost | L3 cache (total) | Core config | Model | Clock (GHz) | Config | Processing power (GFLOPS) | TDP | Release date |
| Ryzen 7 | 5825U | 8 (16) | 2.0 | 4.5 | 16 MB | 1 × 8 | Radeon Graphics | 2.0 | 512:32:8 8 CUs | 2048 | 15 W | Jan 4, 2022 |
| Ryzen 5 | 5625U | 6 (12) | 2.3 | 4.3 | 16 MB | 1 × 6 | Radeon Graphics | 1.8 | 448:28:8 7 CUs | 1612.8 | 15 W | Jan 4, 2022 |
| Ryzen 3 | 5125C | 2 (4) | 3.0 | — | 8 MB | 1 × 2 | Radeon Graphics | ? | 192:12:8 3 CU | ? | 15 W | May 5, 2022 |
* v
* t
* e
* ↑ All of the iGPUs are branded as AMD Radeon Graphics.
* ↑ Core Complexes (CCX) × cores per CCX
* ↑ Unified shaders : texture mapping units : render output units and compute units (CU)
* ↑ Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
* 1 2 Model also available as Pro version as 5475U, 5675U, 5875U, released on April 19, 2022.
* 1 2 Model also available as Chromebook optimized version as 5425C, 5625C, 5825C, released on May 5, 2022.

#### Barceló-R

Common features of Ryzen 7030 notebook APUs:
* Socket: FP6.
* All the CPUs support DDR4-3200 or LPDDR4-4266 in dual-channel mode.
* L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
* L2 cache: 512 KB per core.
* All the CPUs support 16 PCIe 3.0 lanes.
* Includes integrated GCN 5th generation GPU.
* Fabrication process: TSMC N7 FinFET.
| Branding and Model | Branding and Model | CPU | CPU | CPU | CPU | CPU | GPU | GPU | GPU | TDP | Release date |
| Branding and Model | Branding and Model | Cores (threads) | Clock rate (GHz) | Clock rate (GHz) | L3 cache (total) | Core config | Model | Clock (GHz) | Processing power (GFLOPS) | TDP | Release date |
| Branding and Model | Branding and Model | Cores (threads) | Base | Boost | L3 cache (total) | Core config | Model | Clock (GHz) | Processing power (GFLOPS) | TDP | Release date |
| Ryzen 7 | (PRO) 7730U | 8 (16) | 2.0 | 4.5 | 16 MB | 1 × 8 | Vega 8 CU | 2.0 | 2048 | 15 W | January 4, 2023 |
| Ryzen 5 | (PRO) 7530U | 6 (12) | 2.0 | 4.5 | 16 MB | 1 × 6 | Vega 7 CU | 2.0 | 1792 | 15 W | January 4, 2023 |
| Ryzen 3 | (PRO) 7330U | 4 (8) | 2.3 | 4.3 | 8 MB | 1 × 4 | Vega 6 CU | 1.8 | 1382.4 | 15 W | January 4, 2023 |
* v
* t
* e
* ↑ Core Complexes (CCX) × cores per CCX
* ↑ Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

### Embedded CPUs

| Model | Release date | Fab | CPU | CPU | CPU | CPU | CPU | CPU | Socket | PCIe support | Memory support | TDP |
| Model | Release date | Fab | Cores (threads) | Clock rate (GHz) | Clock rate (GHz) | Cache | Cache | Cache | | | Socket | PCIe support | Memory support | TDP |
| Model | Release date | Fab | Cores (threads) | Base | Boost | L1 | L2 | L3 | Socket | PCIe support | Memory support | TDP |
| V3C14 | September 27, 2022 | TSMC 7FF | 4 (8) | 2.3 | 3.8 | 32 KB inst. 32 KB data per core | 512 KB per core | 8 MB | FP7r2 | 20 (8+4+4+4) PCIe 4.0 | DDR5-4800 dual-channel | 15 W |
| V3C44 | September 27, 2022 | TSMC 7FF | 4 (8) | 3.5 | 3.8 | 32 KB inst. 32 KB data per core | 512 KB per core | 8 MB | FP7r2 | 20 (8+4+4+4) PCIe 4.0 | DDR5-4800 dual-channel | 45 W |
| V3C16 | September 27, 2022 | TSMC 7FF | 6 (12) | 2.0 | 3.8 | 32 KB inst. 32 KB data per core | 512 KB per core | 16 MB | FP7r2 | 20 (8+4+4+4) PCIe 4.0 | DDR5-4800 dual-channel | 15 W |
| V3C18I | September 27, 2022 | TSMC 7FF | 8 (16) | 1.9 | 3.8 | 32 KB inst. 32 KB data per core | 512 KB per core | 16 MB | FP7r2 | 20 (8+4+4+4) PCIe 4.0 | DDR5-4800 dual-channel | 15 W |
| V3C48 | September 27, 2022 | TSMC 7FF | 8 (16) | 3.3 | 3.8 | 32 KB inst. 32 KB data per core | 512 KB per core | 16 MB | FP7r2 | 20 (8+4+4+4) PCIe 4.0 | DDR5-4800 dual-channel | 45 W |
* v
* t
* e

### Server CPUs

The Epyc server line of chips based on Zen 3 is named Milan and is the final generation of chips using the SP3 socket. Epyc Milan was released on March 15, 2021.
Common features:
* SP3 socket
* Zen 3 microarchitecture
* TSMC 7 nm process for the compute and cache dies, GloFo 14 nm process for the I/O die
* MCM with one I/O die (IOD) and multiple compute dies (CCD), one core complex (CCX) per compute die with up to 8 cores and 32 MiB of L3 cache
* 7003X models use 64 MiB stacked cache dies for 96 MiB L3 cache per CCX (3D V-Cache)
* Eight-channel DDR4-3200
* 128 PCIe 4.0 lanes per socket, 64 of which are used for Infinity Fabric in 2P platforms
| Model | Chiplets | Cores (threads) | Core config | Clock rate (GHz) | Clock rate (GHz) | Cache | Cache | Cache | Socket & Scaling | TDP | Release Price |
| Model | Chiplets | Cores (threads) | Core config | Base | Boost | L1 | L2 | L3 | Socket & Scaling | TDP | Release Price |
| 7773X | 8 × CCD 1 × I/OD | 64 (128) | 8 × 8 | 2.20 | 3.50 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 768 MB (96 MB per CCX) | SP3 (up to) 2P | 280 W | $8800 |
| 7763 | 8 × CCD 1 × I/OD | 64 (128) | 8 × 8 | 2.45 | 3.40 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 256 MB 32 MB per CCX | SP3 (up to) 2P | 280 W | $7890 |
| 7713 | 8 × CCD 1 × I/OD | 64 (128) | 8 × 8 | 2.00 | 3.675 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 256 MB 32 MB per CCX | SP3 (up to) 2P | 225 W | $7060 |
| 7713P | 8 × CCD 1 × I/OD | 64 (128) | 8 × 8 | 2.00 | 3.675 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 256 MB 32 MB per CCX | SP3 1P | 225 W | $5010 |
| 7663 | 8 × CCD 1 × I/OD | 56 (112) | 8 × 7 | 2.00 | 3.50 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 256 MB 32 MB per CCX | SP3 (up to) 2P | 240 W | $6366 |
| 7663P | 8 × CCD 1 × I/OD | 56 (112) | 8 × 7 | 2.00 | 3.50 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 256 MB 32 MB per CCX | SP3 1P | 240 W | $3139 |
| 7643 | 8 × CCD 1 × I/OD | 48 (96) | 8 × 6 | 2.30 | 3.60 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 256 MB 32 MB per CCX | SP3 (up to) 2P | 225 W | $4995 |
| 7643P | 8 × CCD 1 × I/OD | 48 (96) | 8 × 6 | 2.30 | 3.60 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 256 MB 32 MB per CCX | SP3 1P | 225 W | $2722 |
| 7573X | 8 × CCD 1 × I/OD | 32 (64) | 8 × 4 | 2.80 | 3.60 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 768 MB (96 MB per CCX) | SP3 (up to) 2P | 280 W | $5590 |
| 75F3 | 8 × CCD 1 × I/OD | 32 (64) | 8 × 4 | 2.95 | 4.00 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 256 MB (32 MB per CCX) | SP3 (up to) 2P | 280 W | $4860 |
| 7543 | 8 × CCD 1 × I/OD | 32 (64) | 8 × 4 | 2.80 | 3.70 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 256 MB (32 MB per CCX) | SP3 (up to) 2P | 225 W | $3761 |
| 7543P | 8 × CCD 1 × I/OD | 32 (64) | 8 × 4 | 2.80 | 3.70 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 256 MB (32 MB per CCX) | SP3 1P | 225 W | $2730 |
| 7513 | 8 × CCD 1 × I/OD | 32 (64) | 8 × 4 | 2.60 | 3.65 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 128 MB (16 MB per CCX) | SP3 (up to) 2P | 200 W | $2840 |
| 7453 | 4 × CCD 1 × I/OD | 28 (56) | 4 × 7 | 2.75 | 3.45 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 64 MB (16 MB per CCX) | SP3 (up to) 2P | 225 W | $1570 |
| 7473X | 8 × CCD 1 × I/OD | 24 (48) | 8 × 3 | 2.80 | 3.70 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 768 MB (96 MB per CCX) | SP3 (up to) 2P | 240 W | $3900 |
| 74F3 | 8 × CCD 1 × I/OD | 24 (48) | 8 × 3 | 3.20 | 4.00 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 256 MB (32 MB per CCX) | SP3 (up to) 2P | 240 W | $2900 |
| 7443 | 4 × CCD 1 × I/OD | 24 (48) | 4 × 6 | 2.85 | 4.00 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 128 MB (32 MB per CCX) | SP3 (up to) 2P | 200 W | $2010 |
| 7443P | 4 × CCD 1 × I/OD | 24 (48) | 4 × 6 | 2.85 | 4.00 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 128 MB (32 MB per CCX) | SP3 1P | 200 W | $1337 |
| 7413 | 4 × CCD 1 × I/OD | 24 (48) | 4 × 6 | 2.65 | 3.60 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 128 MB (32 MB per CCX) | SP3 (up to) 2P | 180 W | $1825 |
| 7373X | 8 × CCD 1 × I/OD | 16 (32) | 8 × 2 | 3.05 | 3.80 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 768 MB (96 MB per CCX) | SP3 (up to) 2P | 240 W | $4185 |
| 73F3 | 8 × CCD 1 × I/OD | 16 (32) | 8 × 2 | 3.50 | 4.00 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 256 MB (32 MB per CCX) | SP3 (up to) 2P | 240 W | $3521 |
| 7343 | 4 × CCD 1 × I/OD | 16 (32) | 4 × 4 | 3.20 | 3.90 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 128 MB (32 MB per CCX) | SP3 (up to) 2P | 190 W | $1565 |
| 7313 | 4 × CCD 1 × I/OD | 16 (32) | 4 × 4 | 3.00 | 3.70 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 128 MB (32 MB per CCX) | SP3 (up to) 2P | 155 W | $1083 |
| 7313P | 4 × CCD 1 × I/OD | 16 (32) | 4 × 4 | 3.00 | 3.70 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 128 MB (32 MB per CCX) | SP3 1P | 155 W | $913 |
| 7303 | 2 × CCD 1 × I/OD | 16 (32) | 2 x 8 | 2.40 | 3.40 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 64 MB (32 MB per CCX) | SP3 (up to) 2P | 130 W | $604 |
| 7303P | 2 × CCD 1 × I/OD | 16 (32) | 2 x 8 | 2.40 | 3.40 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 64 MB (32 MB per CCX) | SP3 1P | 130 W | $594 |
| 72F3 | 8 × CCD 1 × I/OD | 8 (16) | 8 × 1 | 3.70 | 4.10 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 256 MB (32 MB per CCX) | SP3 (up to) 2P | 180 W | $2468 |
| 7203 | 2 × CCD 1 × I/OD | 8 (16) | 2 x 4 | 2.80 | 3.40 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 64 MB (32 MB per CCX) | SP3 (up to) 2P | 120 W | $348 |
| 7203P | 2 × CCD 1 × I/OD | 8 (16) | 2 x 4 | 2.80 | 3.40 | 32 KiB i-cache 32 KiB d-cache (per core) | 512 KB (per core) | 64 MB (32 MB per CCX) | SP3 1P | 120 W | $338 |
* v
* t
* e
* ↑ Core Complexes (CCX) × cores per CCX

## Zen 3+

Zen 3+ is the codename for a refresh of the Zen 3 microarchitecture, which focuses on power efficiency improvements. It was released in April 2022 with the Ryzen 6000 series of mobile processors.

### Features and improvements

Zen 3+ has 50 new or enhanced power management features over Zen 3, and also provides an adaptive power management framework, as well as new deep sleep states. Altogether, this brings improvements to efficiency both during idle, and when under load, with up to 30% performance-per-watt increase over Zen 3, as well as longer battery life.
IPC is identical to that of Zen 3; the performance improvements of Ryzen 6000 over Ryzen 5000 mobile processors stem from it having a higher efficiency (hence more performance in power-constrained form factors like laptops), as well as the increased clock speeds from being built on the smaller TSMC N6 node.
The Rembrandt implementation of Zen 3+ also has support for DDR5 and LPDDR5 memory.

### Products
#### Rembrandt

On April 1, 2022, AMD released the Ryzen 6000 series of mobile APUs, codenamed Rembrandt. It introduces PCIe 4.0 and DDR5/LPDDR5 for the first time in an APU for the laptop and also introduced RDNA2 integrated graphics to the PC. It is built on TSMC's 6 nm node.
Common features of Ryzen 6000 notebook APUs:
* Socket: FP7, FP7r2.
* All the CPUs support DDR5-4800 or LPDDR5-6400 in dual-channel mode.
* L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
* L2 cache: 512 KB per core.
* All the CPUs support 16 PCIe 4.0 lanes.
* Includes integrated RDNA 2 GPU.
* Fabrication process: TSMC N6 FinFET.
| Branding and model | Branding and model | CPU | CPU | CPU | CPU | CPU | GPU | GPU | GPU | GPU | TDP | Release date |
| Branding and model | Branding and model | Cores (threads) | Clock (GHz) | Clock (GHz) | L3 cache (total) | Core config | Model | Clock (GHz) | Config | Processing power (GFLOPS) | TDP | Release date |
| Branding and model | Branding and model | Cores (threads) | Base | Boost | L3 cache (total) | Core config | Model | Clock (GHz) | Config | Processing power (GFLOPS) | TDP | Release date |
| Ryzen 9 | 6980HX | 8 (16) | 3.3 | 5.0 | 16 MB | 1 × 8 | 680M | 2.4 | 768:48:8 12 CUs | 3686.4 | 45 W | Jan 4, 2022 |
| Ryzen 9 | 6980HS | 8 (16) | 3.3 | 5.0 | 16 MB | 1 × 8 | 680M | 2.4 | 768:48:8 12 CUs | 3686.4 | 35 W | Jan 4, 2022 |
| Ryzen 9 | 6900HX | 8 (16) | 3.3 | 4.9 | 16 MB | 1 × 8 | 680M | 2.4 | 768:48:8 12 CUs | 3686.4 | 45 W | Jan 4, 2022 |
| Ryzen 9 | 6900HS | 8 (16) | 3.3 | 4.9 | 16 MB | 1 × 8 | 680M | 2.4 | 768:48:8 12 CUs | 3686.4 | 35 W | Jan 4, 2022 |
| Ryzen 7 | 6800H | 8 (16) | 3.2 | 4.7 | 16 MB | 1 × 8 | 680M | 2.2 | 768:48:8 12 CUs | 3379.2 | 45 W | Jan 4, 2022 |
| Ryzen 7 | 6800HS | 8 (16) | 3.2 | 4.7 | 16 MB | 1 × 8 | 680M | 2.2 | 768:48:8 12 CUs | 3379.2 | 35 W | Jan 4, 2022 |
| Ryzen 7 | 6800U | 8 (16) | 2.7 | 4.7 | 16 MB | 1 × 8 | 680M | 2.2 | 768:48:8 12 CUs | 3379.2 | 15–28 W | Jan 4, 2022 |
| Ryzen 5 | 6600H | 6 (12) | 3.3 | 4.5 | 16 MB | 1 × 6 | 660M | 1.9 | 384:24:8 6 CUs | 1459.2 | 45 W | Jan 4, 2022 |
| Ryzen 5 | 6600HS | 6 (12) | 3.3 | 4.5 | 16 MB | 1 × 6 | 660M | 1.9 | 384:24:8 6 CUs | 1459.2 | 35 W | Jan 4, 2022 |
| Ryzen 5 | 6600U | 6 (12) | 2.9 | 4.5 | 16 MB | 1 × 6 | 660M | 1.9 | 384:24:8 6 CUs | 1459.2 | 15–28 W | Jan 4, 2022 |
* v
* t
* e
* ↑ Core Complexes (CCX) × cores per CCX
* ↑ Unified shaders : texture mapping units : render output units and compute units (CU)
* ↑ Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
* 1 2 3 4 5 6 7 8 Model also available as PRO version (6650U, 6650H, 6650HS, 6850U, 6850H, 6850HS, 6950H, 6950HS), released on April 19, 2022.
* "AMD Ryzen 5 PRO 6650U". AMD.
* "AMD Ryzen 5 PRO 6650H". AMD.
* "AMD Ryzen 5 PRO 6650HS". AMD.
* "AMD Ryzen 7 PRO 6850U". AMD.
* "AMD Ryzen 7 PRO 6850H". AMD.
* "AMD Ryzen 7 PRO 6850HS". AMD.
* "AMD Ryzen 9 PRO 6950H". AMD.
* "AMD Ryzen 9 PRO 6950HS". AMD.

#### Rembrandt-R

Rembrandt-R is the codename for a refresh of Rembrandt codenamed processors, released as the Ryzen 7035 series of mobile APUs in January 2023.
Common features of Ryzen 7035 notebook APUs:
* Socket: FP7, FP7r2.
* All the CPUs support DDR5-4800 or LPDDR5-6400 in dual-channel mode.
* L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
* L2 cache: 512 KB per core.
* All the CPUs support 16 PCIe 4.0 lanes.
* Includes integrated RDNA 2 GPU.
* Fabrication process: TSMC N6 FinFET.
| Branding and model | Branding and model | CPU | CPU | CPU | CPU | CPU | GPU | GPU | GPU | TDP | Release date |
| Branding and model | Branding and model | Cores (threads) | Clock (GHz) | Clock (GHz) | L3 cache (total) | Core config | Model | Clock (GHz) | Processing power (GFLOPS) | TDP | Release date |
| Branding and model | Branding and model | Cores (threads) | Base | Boost | L3 cache (total) | Core config | Model | Clock (GHz) | Processing power (GFLOPS) | TDP | Release date |
| Ryzen 7 | 7735HS | 8 (16) | 3.2 | 4.75 | 16 MB | 1 × 8 | 680M 12 CU | 2.2 | 3379.2 | 35–54 W | April 30, 2023 |
| Ryzen 7 | 7735H | 8 (16) | 3.2 | 4.75 | 16 MB | 1 × 8 | 680M 12 CU | 2.2 | 3379.2 | 35–54 W | April 30, 2023 |
| Ryzen 7 | 7736U | 8 (16) | 2.7 | 4.7 | 16 MB | 1 × 8 | 680M 12 CU | 2.2 | 3379.2 | 15–28 W | January 4, 2023 |
| Ryzen 7 | 7735U | 8 (16) | 2.7 | 4.75 | 16 MB | 1 × 8 | 680M 12 CU | 2.2 | 3379.2 | 15–30 W | January 4, 2023 |
| Ryzen 7 | 7435HS | 8 (16) | 3.1 | 4.5 | 16 MB | 1 × 8 | — | — | — | 35–54 W | 2024 |
| Ryzen 7 | 7435H | 8 (16) | 3.1 | 4.5 | 16 MB | 1 × 8 | — | — | — | 35–54 W | 2024 |
| Ryzen 5 | 7535HS | 6 (12) | 3.3 | 4.55 | 16 MB | 1 × 6 | 660M 6 CU | 1.9 | 1459.2 | 35–54 W | April 30, 2023 |
| Ryzen 5 | 7535H | 6 (12) | 3.3 | 4.55 | 16 MB | 1 × 6 | 660M 6 CU | 1.9 | 1459.2 | 35–54 W | April 30, 2023 |
| Ryzen 5 | 7535U | 6 (12) | 2.9 | 4.55 | 16 MB | 1 × 6 | 660M 6 CU | 1.9 | 1459.2 | 15–30 W | January 4, 2023 |
| Ryzen 5 | 7235HS | 4 (8) | 3.2 | 4.2 | 8 MB | 1 × 4 | — | — | — | 35–53 W | 2024 |
| Ryzen 5 | 7235H | 4 (8) | 3.2 | 4.2 | 8 MB | 1 × 4 | — | — | — | 35–53 W | 2024 |
| Ryzen 3 | 7335U | 4 (8) | 3.0 | 4.3 | 8 MB | 1 × 4 | 660M 4 CU | 1.8 | 921.6 | 15–30 W | January 4, 2023 |
* v
* t
* e
* ↑ Core Complexes (CCX) × cores per CCX
* ↑ Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.