# Display Data Channel

Display Data Channel (DDC) is a collection of protocols for digital communication between a computer display and a graphics adapter that enable the display to communicate its supported display modes to the adapter and that enable the computer host to adjust monitor parameters, such as brightness and contrast.
Like modern analog VGA connectors, the DVI and DisplayPort connectors include pins for DDC, but DisplayPort only supports DDC within its optional Dual-Mode DP (DP++) feature in DVI/HDMI mode.
The standard was created by the Video Electronics Standards Association (VESA).

## Overview

The DDC suite of standards aims to provide Plug and Play and DPMS power management experiences for computer displays.
DDC1 and DDC2B/Ab/B+/Bi protocols are a physical link between a monitor and a video card, which was originally carried on either two or three pins in a 15-pin analog VGA connector.
Extended display identification data (EDID) is a companion standard; it defines a compact binary file format describing the monitor's capabilities and supported graphics modes, stored in a read-only memory (EEPROM) chip programmed by the manufacturer of the monitor. The format uses a description block containing 128 bytes of data, with optional extension blocks to provide additional information. The most current version is Enhanced EDID (E-EDID) Release A, v2.0. DisplayID is aim to replace EDID, which supports many features such as HDR and color management.
The first version of the DDC standard was adopted in August 1994. It included the EDID 1.0 format and specified DDC1, DDC2B and DDC2Ab physical links.
DDC version 2, introduced in April 1996, split EDID into a separate standard and introduced the DDC2B+ protocol.
DDC version 3, December 1997, introduced the DDC2Bi protocol and support for VESA Plug and Display and Flat Panel Display Interface on separate device addresses, requiring them to comply with EDID 2.0.
The DDC standard has been superseded by E-DDC in 1999.
DDC is also used as a communication channel for implementing High-bandwidth Digital Content Protection (HDCP).

## Physical link

Prior to the DDC, the VGA standard had reserved four pins in the analog VGA connector, known as ID0, ID1, ID2 and ID3 (pins 11, 12, 4 and 15) for identification of monitor type. These ID pins, attached to resistors to pull one or more of them to ground (GND), allowed for the definition of the monitor type, with all open (n/c, not connected) meaning "no monitor".
In the most commonly documented scheme, the ID3 pin was unused and only the 3 remaining pins were defined. The ID0 was pulled to GND by color monitors, while the monochrome monitors pulled ID1 to GND. Finally, the ID2 pulled to GND signaled a monitor capable of 1024×768 resolution, such as IBM 8514. In this scheme, the input states of the ID pins would encode the monitor type as follows:
| ID2 (pin 4) | ID0 (pin 11) | ID1 (pin 12) | monitor type |
| n/c | n/c | n/c | no monitor connected |
| n/c | n/c | GND | < 1024×768, monochrome |
| n/c | GND | n/c | < 1024×768, color |
| GND | GND | n/c | ≥ 1024×768, color |
More elaborate schemes also existed that used all of the 4 ID pins while manipulating the HSync and VSync signals in order to extract 16 bits (4 ID pin values for each of the 4 combinations of HSync and VSync states) of monitor identification.
DDC changed the purpose of the ID pins to incorporate a serial link interface. However, during the transition, the change was not backwards-compatible and video cards using the old scheme could have problems if a DDC-capable monitor was connected. The DDC signal can be sent to or from a video graphics array (VGA) monitor with the I$^2$C protocol using the master's serial clock and serial data pins.

### DDC1

DDC1 is a simple, low-speed, unidirectional serial link protocol. Pin 12, ID1 functions as a data line that continuously transmits the 128-byte EDID block, and the data clock is synchronised with vertical sync, providing typical clock rates of 60 to 100 Hz.
Very few display devices implemented this protocol.

### DDC2

The most common version, called DDC2B, is based on I²C, a serial bus. Pin 12, ID1, of the VGA connector is used as the data pin of the I²C bus, and the formerly-unused pin 15 is the I²C clock. Pin 9, previously used as a mechanical key, supplies +5V DC power (up to 50mA) to power the EEPROM. With this, the host can read the EDID even if the monitor is powered off. Though I²C is fully bidirectional and supports multiple bus-masters, DDC2B is unidirectional and allows only one bus master—the graphics adapter. The monitor acts as a slave device at the 7-bit I²C address 50h, and provides 128-256 bytes of read-only EDID. Because this access is always a read, the first I²C octet will always be A1h.
DDC2Ab is an implementation of the I²C-based 100-kbit/s ACCESS.bus interface, which made it possible for monitor manufacturers to support external ACCESS.bus peripherals such as a mouse or keyboard with little to no additional effort. Such devices and monitors were briefly available in the mid-1990s, but they disappeared with the introduction of USB.
DDC2B+ and DDC2Bi are scaled-down versions of DDC2Ab which only support monitor and graphics card devices but still allow bidirectional communication between them.
DDC2 is not exclusive to the VGA interface. Both DVI and HDMI feature dedicated DDC2B wires.

## DDC/CI

DDC/CI (Command Interface) standard was introduced in August 1998. It specifies a means for a computer to send commands to the monitor, as well as receive sensor data from the monitor, over a bidirectional link. Specific commands to control monitors are defined in a separate Monitor Control Command Set (MCCS) standard version 1.0, released in September 1998.
DDC/CI monitors are sometimes supplied with an external color sensor to allow automatic calibration of the monitor's color balance. Some tilting DDC/CI monitors support an auto-pivot function, where a rotation sensor in the monitor enables the operating system to keep the display upright as the monitor is moved between its portrait and landscape positions.
Most DDC/CI monitors support only a small subset of MCCS commands and some have undocumented commands. Many manufacturers did not pay attention to DDC/CI in the past, but now almost all monitors support such general MCCS commands as brightness and contrast management.
DDC/CI standard describes a full suite of bidirectional control protocols - DDC2Ab, DDC2Bi and DDC2B+ - in a single standard and provides a means for packaging Monitor Control Command Set commands.
DDC/CI version 1.1 was adopted in October 2004.
Monitor Control Command Set version 2.0 was adopted in October 2003. A new MCCS V3 was introduced in July 2006, though did not gain enough industry attention yet. The latest release of V2 standard is version 2.2a, adopted January 2011.

### OS support for DDC/CI

Despite its ubiquity in post-2016 displays, DDC/CI is not generally used by the operating system by default for brightness control on external displays. Additional software can be used to send commands to the display, but the degree of system integration vary.
Windows exposes DDC/CI as the Monitor Configuration Win32 API series.

## E-DDC

Enhanced Display Data Channel (E-DDC) is the most recent revision of the DDC standard. Version 1 was introduced in September 1999 and featured the addition of a segment pointer which allowed up to 32 Kbytes of display information storage for use by the Enhanced EDID (E-EDID) standard.
Earlier DDC implementations used simple 8-bit data offset when communicating with the EDID memory in the monitor, limiting the storage size to 2$^8$ bytes = 256 bytes, but allowing the use of cheap 2-Kbit EEPROMs. In E-DDC, a special I²C addressing scheme was introduced, in which multiple 256-byte segments could be selected. To do this, a single 8-bit segment index is passed to the display via the I²C address 30h. (Because this access is always a write, the first I²C octet will always be 60h.) Data from the selected segment is then immediately read via the regular DDC2 address using a repeated I²C 'START' signal. However, VESA specification defines the segment index value range as 00h to 7Fh, so this only allows addressing 128 segments × 256 bytes = 32 KiB. The segment index register is volatile, defaulting to zero and automatically resetting to zero after each NACK or STOP. Therefore, it must be set every time access to data above the first 256-byte segment is performed. The auto-reset mechanism is to provide for backward compatibility to, for example, DDC2B hosts, otherwise they may be stuck at a segment other than 00h in some rare cases.
Other important changes were removal of the DDC1 and DDC2Ab protocols, deprecation of separate VESA P&D and FPDI device addresses, and clarifications to the DDC power requirements.
E-DDC Version 1.1, approved March 2004, featured support for HDMI and consumer electronics.
E-DDC Version 1.2, approved December 2007, introduced support for DisplayPort (which has no dedicated DDC2B links and uses its bidirectional auxiliary channel for EDID and MCCS communication) and DisplayID standards.
E-DDC Version 1.3 from September 2017 contains corrections for errata and minor clarifications.

## Disabling DDC

Some KVM switches (keyboard-video-mouse) and video extenders handle DDC traffic incorrectly, making it necessary to disable monitor plug and play features in the operating system, and maybe even physically remove pin 12 (serial data pin) from the analog VGA cables that connect such device to multiple PCs.
Microsoft Windows features a standard "Plug and Play Monitor" driver which uses the display's EDID information to construct a list of supported monitor modes. The Display Resolution control panel applet can be used to disable this driver's Plug and Play features and manually select any resolution or refresh rate supported by the video card. Many video card manufacturers and third parties provide control applications which can be used to select a custom display mode that does not conform to the EDID information or the monitor .INF file.