# K-202

K-202 was a 16-bit minicomputer, created by a team led by Polish scientist Jacek Karpiński between 1970–1973 in cooperation with British companies Data-Loop and M.B. Metals. The machine could perform about 1 million instructions per second, making it highly competitive with the US Data General SuperNOVA and UK CTL Modular One. Most other minicomputers of the era were significantly slower.
Approximately 30 units were claimed to be produced. All units shipped to M.B. Metals were returned for service. Due to friction resulting from competition with Elwro, a government-backed competitor, the production of K-202 was blocked and Karpiński thrown out of his company under the allegations of sabotage and embezzlement. Sometime later the K-202 had a successor, Mera 400 [pl], hundreds of which were built.

## Description

The K-202 was packaged in a metal box similar to other minicomputers in overall size, and capable of being fit into a 19-inch rack, which was common for other systems. Like most computers of the era, the front panel included a number of switches and lamps that could be used to directly set or read the values stored in main memory. A unique feature was a large dial on the right that selected what to display or set, allowing rapid access to the processor registers simply by rotating the dial. A key that turned on the power and unlocked the case was positioned on the right side of the case.
The system was designed to be highly expandable. A minimal setup consisted of the central processing unit (CPU), a minimum of 4 k 16-bit words of core memory (4 kW, or 8 kB), and a single input/output channel for use with a computer terminal. The basic system supported vectored interrupts for 32 input/output devices. At the other end of the scale, a maximally expanded system could include up to 4 MB of memory, a floating point unit (FPU), multiple multi-line programmable input/output systems, and even more than one CPU. At the maximum, it could support 272 I/O interrupt levels.
The expansion system was designed around two external buses, an 8-bit bus for input/output, and a 16-bit bus for memory and storage. Memory modules could hold from 16 to 64 kB per module, available in either 0.7 or 1.5 usec times, with access times about 40% of that due to the read-write nature of core. Store controllers were smart, buffered devices that could control up to eight disk drives or magnetic tape units that loaded and saved bulk data. The controller performed the entire transfer in a manner similar to a DMA controller, raising the appropriate interrupt when the operation was completed. The I/O modules were for slower devices like terminals, punch tape readers and computer printers that were primarily character oriented. Both could also have multiplexers for custom connections. Because the buses are not terminated on the CPU, it was also possible to connect several CPU modules to the various modules on the same bus, sharing devices like drives and printers across multiple machines.
The K-202 was capable of running about one million operations per second; however, its instruction set was not well suited to the typical tasks, making practical performance somewhat lower. In order to reach this level of performance in a physically small machine, the design made use of integrated circuits, which were not available in the required density from Warsaw Pact countries. The required components were sourced from the west through the UK partners.
The K-202 claimed to be the first mini-computer which used the paging technique, providing 8 MB of virtual memory; however, what its constructors called paging was actually segmented memory,. Furthermore, the advertised upper limit of 8 MB of memory was practically unreachable due to signal propagation delays, 144 KB being the largest available configuration. K-202 was based on small- and medium-scale integrated circuits.
* Multiprogramming
* Multiprocessing
* 16-bit word
* More than 90 instructions
* 7 universal registers
* 16 ways of determining argument
* Operating memory of up to 4 million words
* Direct addressing of up to 64k words
* Autonomic data exchange with operating memories at the speed of 16 Mbit/s [note: i.e. 1M words/s]
* Implementation method – TTL/MSI integrated circuits
* Memory cycle 0.7 μs
* Processing speed of 1 million operations/second