# Mostek 5065

The Mostek MK5065 was an 8-bit microprocessor introduced by Mostek in early 1974. The design was originally developed by Motorola for use in an Olivetti electronic calculator, and was licensed to Mostek for use in non-calculator roles. It featured three sets of processor registers, allowing it to switch to an interrupt handler in a single cycle, and a wait-for-data mode that aided direct memory access.
Despite a relatively low cost (for the era) of $58 in quantities of 100, the 5065 appears to have seen little use. The Fairchild F8 was introduced at about the same time, aimed at the same markets. The F8 had a number of advantages over the 5065 due to its more modern design. In June 1975, Mostek licensed the F8 under a second source arrangement. The 5065 disappeared from Mostek's 1975 catalog, which mentions only their F8, the MK3850.
Still convinced that they needed a microprocessor, and learning from their experience on the 5065, Motorola began design of their Motorola 6800 almost immediately after licensing the 5065 to Mostek.

## History

The 5065 began as a custom PMOS CPU design by Motorola for a desktop calculator being built by Olivetti. The design effort was led by Rod Orgill and Bill Mensch, producing the 5065. Motorola's existing fabs proved unable to produce the design, and they were forced to license it to Mostek under the condition they did not sell into the calculator market. Mostek launched their version in February 1974. By early 1975 it was in volume production and sold for $58 in lots from 100 to 499.
In September 1974, Fairchild Semiconductor launched the Fairchild F8 with sample shipments starting the next April and full production later that year. The F8 was almost identical to the 5065 in purpose, originally designed as a calculator CPU for Olympia-Werke, a German competitor to Olivetti. The F8 had a number of design features that made it very easy to implement, with typical designs requiring only two chips to provide all the needed ROM, RAM, clock and I/O. It also improved on the 5065 in that it was an NMOS-based chip, allowing it to be fabricated at a smaller feature size which lowered its cost and allowed it to run much faster.
In June 1975, Mostek licensed the F8 design from Fairchild and brought it up on their new NMOS line. Mentions of the 5065 disappear by the time their 1975 catalog, which mentions only their version of the F8, the MK3850. Mostek aggressively lowered the price of their F8 over the next year, reaching $10 in plastic packaging by 1976.

## Description
### Basic design

In the early 1970s the idea of a microprocessor being used as the basis for a standalone computer was still not common, and designs of the era generally included features intended to make them easy to use in what today would be known as the microcontroller area, processors that are used to control a device like a cash register or gas pump. These systems have to respond quickly to different inputs, which is normally accomplished via interrupts. As this is a common operation in these settings, many designs focused on ways to improve interrupt performance or implementation.
In the case of the 5065, this was accomplished by providing three separate sets of registers for the accumulator, program counter and the internal "main link" register, along with the carry flag. On the receipt of an interrupt, the processor completed the current instruction and then pointed to the selected set of these registers, or as they called them, "levels". This allowed the system to track three separate sections of code, corresponding to normal operation and two interrupt levels. External devices could raise an interrupt on two pins, INT 1 and INT 2, both of which could be turned on or off in software. So for instance, if INT 2 was enabled and triggered, the processor responded by completing the current instruction, switching to the level 2 registers, and continuing. Normal operation was level 3, which it returned to when a return-from-interrupt instruction was called. This makes interrupt servicing very rapid because the state information is being stored automatically in a single cycle, whereas many designs require this information to be stored out using user-written code that may take multiple cycles to complete.
The same system could also be used for fast subroutine calls instead of having to store out the register contents. As the processor state was saved separately, only the return address had to be explicitly written out in code. In this case, the first 256 locations in memory, the zero page, was used as a call stack. For this to work, this area had to be implemented in some form of writable memory. The page could hold up to 128 16-bit addresses, with the current value indicated by the "pointer register", what would be known as the stack pointer on other designs.
To aid direct memory access (DMA) implementations, the system included a WAIT pin that was raised by an external device that wanted access to memory. When this signal was received, the processor would continue with the current instruction, including any required reading and writing from memory. When the instruction was complete it would raise the DMA pin to indicate it was ready and then went into a paused state. The external device would then perform its DMA operations and then drop WAIT when it was finished. The processor would then drop the DMA pin, unpause, and pick up where it left off.

### Instructions and addressing

There were a total of 51 instructions, and 81 opcodes. The instructions come in many formats, but most of them in two-byte opcode-operand pairs. A small number of one-byte instructions were used for things like return-from-subroutine or shift-left, which do not need any additional information.
Those instructions that used memory (as opposed to registers) used a two-byte format with the opcode in the upper 6 bits of the first byte. The lower 2 bits controlled the type of memory access. The first (bit 1) indicated whether the following 8-bit operand was a direct or indirect address. The second (bit 0) controlled whether the 8-bit value was offset from the current memory page defined by the program counter, or in the zero page. The following operand byte contains an 8 bit address. This means that when using direct addressing, the data has to lie within 256 bytes of the current instruction, or within the first 256 bytes of memory. If access to the greater main memory is needed, indirect addressing must be used.
Indirect addresses used a two-step access pattern. First the processor reads lower 8-bits of the instruction and looks at bit 0 to see which offset to use. It then reads the byte at that location and the following byte, producing a 16-bit value held in a special buffer. It would then read or write the data to that 16-bit location. This pattern was commonly seen on minicomputers of the era, as it made certain forms of looping over data easy to implement.
The most significant bit of every address stored in memory was used to specify whether it was a direct or indirect address, this left 15-bits for the actual address, allowing up to 32 kB of memory. Since the address being pointed to by an indirect address might also have its high bit set, indirect addresses can form chains. This style of chained access was also seen on minicomputer systems like the IBM 1620, HP 2100 and Data General Nova, but was uncommon for microprocessors.
For branches, subroutine calls and jumps, a second format was used where the opcode used the upper 4 bits, and the lower 4 bits along with the 8-bit operand form a 12-bit address. This meant code could only call other code within a 4 kB "block". There were many other instruction formats for special purposes.
Input/output was not memory mapped and was handled through special instructions. The upper 4 bits of the opcode held the I/O instruction (input, output, status, etc.), while the lower 4 bits were a "free field". The program could place any value in these 4 bits and use it as an ad-hoc data field to send instructions to the device. Triggering the instruction resulted in a four-cycle process. In the first cycle the lower 6 bits of the instruction, including the 4 bit free field, were put on the H bus while the value of the accumulator was put on the L bus. The device could then read both to decode its instruction. On the second cycle, if the CPU was to send data to the device for output, the 8-bit value was put on the bus. On the third, any data being sent to the CPU was returned on the bus. The fourth indicated the end of the I/O cycle.

### Other details

The main bus was multiplexed, with a total of 16 pins used for both addressing and data. The bus was split into "high" (H) and "low" (L) sides, both 8-bits. During a memory access, the 15-bit address would be placed on the high and low sides, and then the data at that location read or written using the L bus only. This meant that memory accesses required two cycles, making it slower than designs with separate (non-multiplexed) address and data busses.
Built on the PMOS process that was common in the early 1970s, the 5065 required three voltage supply levels, -12V (VGG), +5V(VSS), -5V (VDD) and ground. It was packaged in a 40-pin DIP, as was common for most processors of the era. The use of the multiplexed bus reduced pin use to the point that five pins were left unconnected. As was the case for most PMOS designs, an external clock chip was required, in this case the MK5009. There were also plans to release a peripheral interface adaptor (PIA) in late 1975.
The system was released with an evaluation system, the two-board GEMS-8, short for General Evaluation Microprocessor System. This included the clock driver, 512 bytes of ROM, 1 to 12 kB of RAM, and a UART for use with a computer terminal. The ROM contained the "Program Aid Routine", a small system development tool and debugger utility. The processor board and PAR ROM was $597, the 12k RAM card another $597, or both together were $995. A cross assembler was also available for an unspecified "16-bit minicomputer".
Clock speeds for the 5065 do not appear in any surviving references. Instruction times are listed as 3 to 16 μsec. Although the instruction times are cited as 3 to 16 μsec, a 1 MHz clock can be used.