# Hitachi HD44780 LCD controller

The Hitachi HD44780 LCD controller is an alphanumeric dot matrix liquid crystal display (LCD) controller developed by Hitachi in the 1980s. The character set of the controller includes ASCII characters, Japanese Kana characters, and some symbols in two 40 character lines. Using an extension driver, the device can display up to 80 characters. Numerous third-party displays are compatible with its 16-pin interface and instruction set, making it a popular and cheap LCD driver.

## Architecture

The Hitachi HD44780 LCD controller is limited to monochrome text displays and is often used in copiers, fax machines, laser printers, industrial test equipment, and networking equipment, such as routers and storage devices.
Compatible LCD screens are manufactured in several standard configurations. Common sizes are one row of eight characters (8×1), and 16×2, 20×2 and 20×4 formats. Larger custom sizes are made with 32, 40 and 80 characters and with 1, 2, 4 or 8 lines. The most commonly manufactured larger configuration is 40×4 characters, which requires two individually addressable HD44780 controllers with expansion chips as a single HD44780 chip can only address up to 80 characters.
Character LCDs may have a backlight, which may be LED, fluorescent, or electroluminescent. The nominal operating voltage for LED backlights is 5V at full brightness, with dimming at lower voltages dependent on the details such as LED color. Non-LED backlights often require higher voltages.

### Interface

Character LCDs use a 16-contact interface, commonly using pins or card edge connections on 0.1 inch (2.54 mm) centers. Those without backlights may have only 14 pins, omitting the two pins powering the light. This interface was designed to be easily hooked up to the Intel MCS-51 XRAM interface, using only two address pins, which allowed displaying text on LCD using simple MOVX commands, offering a cost effective option for adding text display to devices.
The predominant pinout is as follows (exceptions exist):
| Pin# | Name | Direction | Description |
| 1 | Vss | Power | Power Supply Ground |
| 2 | Vcc | Power | Power Supply (+3.3 or +5 V depending on module) |
| 3 | Vee | Input | Contrast Adjustment (analog input) |
| 4 | RS | Input | Register Select (0 = command, 1 = data) |
| 5 | R/W | Input | Read/Write (0 = write to display module, 1 = read from display module) |
| 6 | E | Input | Clock Enable (falling-edge triggered) |
| 7 | DB0 | I/O | Data Bit 0 (not used in 4-bit operation) |
| 8 | DB1 | I/O | Data Bit 1 (not used in 4-bit operation) |
| 9 | DB2 | I/O | Data Bit 2 (not used in 4-bit operation) |
| 10 | DB3 | I/O | Data Bit 3 (not used in 4-bit operation) |
| 11 | DB4 | I/O | Data Bit 4 |
| 12 | DB5 | I/O | Data Bit 5 |
| 13 | DB6 | I/O | Data Bit 6 |
| 14 | DB7 | I/O | Data Bit 7 |
| 15 | LED+ | Power | Backlight Anode (+) (if applicable) |
| 16 | LED− | Power | Backlight Cathode (−) (if applicable) |
Notes:
* Vee (also V0): This is an analog input, typically connected to a potentiometer. The user must be able to control this voltage independent of all other adjustments, in order to optimise visibility of the display that varies i. a. with temperature and, in some cases, height above the sea level. With a wrong adjustment, the display will seem to malfunction.
* R/W: In most applications, reading from the HD44780 is not necessary. In that case, this pin can be permanently connected to ground and no processor pins need to be allocated to control it.

#### Mode selection

In 8-bit mode, all transfers happen in one cycle of the enable pin (E) with all 8 bits on the data bus and the RS and R/W pins stable. In 4-bit mode, data are transferred as pairs of 4-bit "nibbles" on the upper data pins, D7–D4, with two enable pulses and the RS and R/W pins stable. The four most significant bits (7–4) must be written first, followed by the four least significant bits (3–0). The high/low sequence must be completed each time or the controller will not properly receive further commands.
Selecting 4-bit or 8-bit mode requires careful selection of commands. There are two primary considerations. First, with D3–D0 unconnected, these lines will always appear high (binary 1111) to the HD44780 since there are internal pull-up MOSFETs. Second, the LCD may initially be in one of three states:
* State 1: 8-bit mode
* State 2: 4-bit mode, waiting for the first set of 4 bits
* State 3: 4-bit mode, waiting for the second set of 4 bits
State 3 may occur, for example, if a prior control was aborted after sending only the first 4 bits of a command while the HD44780 was in 4-bit mode.
The following algorithm ensures that the LCD is in the desired mode:
The same command is sent three times, Function Set with 8-bit interface D7–D4 = binary 0011, the lower four bits are "don't care", using single enable pulses. If the controller is in 4-bit mode, the lower four bits are ignored so they cannot be sent until the interface is in a known size configuration.
Starting in state 1 (8-bit configuration):
* Send Function Set command. Command will be executed, set 8-bit mode.
* Send Function Set command. Command will be executed, set 8-bit mode.
* Send Function Set command. Command will be executed, set 8-bit mode.
Starting in state 2 (4-bit configuration, waiting for first 4-bit transfer):
* Send Function Set command. First 4 bits received.
* Send Function Set command. Last 4 bits, command accepted, set 8-bit mode.
* Send Function Set command. Command will be executed, set 8-bit mode.
Starting in state 3 (4-bit configuration, waiting for last 4-bit transfer):
* Send Function Set command. Last 4 bits, unknown command executed.
* Send Function Set command. In 8-bit mode command will be executed, otherwise first 4 bits received.
* Send Function Set command. 8-bit command will be executed or last 4 bits of previous command; set 8-bit mode.
In all three starting cases, the bus interface is now in 8-bit mode, 1 line, 5×8 characters. If a different configuration 8-bit mode is desired, an 8-bit bus Function Set command should be sent to set the full parameters. If 4-bit mode is desired, binary 0010 should be sent on D7–D4 with a single enable pulse. Now the controller will be in 4-bit mode and a full 4-bit bus Function Set command sequence (two enables with command bits 7–4 and 3–0 on subsequent cycles) will complete the configuration of the Function Set register.

## Instruction set

The HD44780 instruction set is shown below:
HD44780U based instruction set :
| Instruction | Code | Code | Code | Code | Code | Code | Code | Code | Code | Code | Description | Execution time (max) (when f$_{cp}$ = 270 kHz) |
| Instruction | RS | R/W | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 | Description | Execution time (max) (when f$_{cp}$ = 270 kHz) |
| Clear display | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Clears display and returns cursor to the home position (address 0). | 1.52 ms |
| Cursor home | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | * | Returns cursor to home position. Also returns display being shifted to the original position. DDRAM content remains unchanged. | 1.52 ms |
| Entry mode set | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | I/D | S | Sets cursor move direction (I/D); specifies to shift the display (S). These operations are performed during data read/write. | 37 μs |
| Display on/off control | 0 | 0 | 0 | 0 | 0 | 0 | 1 | D | C | B | Sets on/off of all display (D), cursor on/off (C), and blink of cursor position character (B). | 37 μs |
| Cursor/display shift | 0 | 0 | 0 | 0 | 0 | 1 | S/C | R/L | * | * | Sets cursor-move or display-shift (S/C), shift direction (R/L). DDRAM content remains unchanged. | 37 μs |
| Function set | 0 | 0 | 0 | 0 | 1 | DL | N | F | * | * | Sets interface data length (DL), number of display line (N), and character font (F). | 37 μs |
| Set CGRAM address | 0 | 0 | 0 | 1 | CGRAM address | CGRAM address | CGRAM address | CGRAM address | CGRAM address | CGRAM address | Sets the CGRAM address. CGRAM data are sent and received after this setting. | 37 μs |
| Set DDRAM address | 0 | 0 | 1 | DDRAM address | DDRAM address | DDRAM address | DDRAM address | DDRAM address | DDRAM address | DDRAM address | Sets the DDRAM address. DDRAM data are sent and received after this setting. | 37 μs |
| Read busy flag & address counter | 0 | 1 | BF | CGRAM/DDRAM address | CGRAM/DDRAM address | CGRAM/DDRAM address | CGRAM/DDRAM address | CGRAM/DDRAM address | CGRAM/DDRAM address | CGRAM/DDRAM address | Reads busy flag (BF) indicating internal operation being performed and reads CGRAM or DDRAM address counter contents (depending on previous instruction). | 0 μs |
| Write CGRAM or DDRAM | 1 | 0 | Write Data | Write Data | Write Data | Write Data | Write Data | Write Data | Write Data | Write Data | Write data to CGRAM or DDRAM. | 37 μs |
| Read from CG/DDRAM | 1 | 1 | Read Data | Read Data | Read Data | Read Data | Read Data | Read Data | Read Data | Read Data | Read data from CGRAM or DDRAM. | 37 μs |
| Instruction bit names — I/D – 0 = decrement cursor position, 1 = increment cursor position; S – 0 = no display shift, 1 = display shift; D – 0 = display-off, 1 = display on; C – 0 = cursor off, 1 = cursor on; B – 0 = cursor blink off, 1 = cursor blink on; S/C – 0 = move cursor, 1 = shift display; R/L – 0 = shift left, 1 = shift right; DL – 0 = 4-bit interface, 1 = 8-bit interface; N – 0 = 1/8 or 1/11 duty (1 line), 1 = 1/16 duty (2 lines); F – 0 = 5×8 dots, 1 = 5×10 dots; BF – 0 = can accept instruction, 1 = internal operation in progress. |||||||||||||
DDRAM is Display Data RAM and CGRAM is Character Generator RAM. The DDRAM is 80 bytes (40 per row) addressed with a gap between the two rows. The first row is addresses 0 to 39 decimal or 0 to 27 hex. The second row is addresses 64 to 103 decimal or 40 to 67 hex.
The CGRAM is read/write memory used to encode up to 8 characters in the character generator. It consists of 64 fields at addresses 0 to 3F hex. Each field is 5 bits mapping to a row of pixels of each character. Each 8 fields in the CGRAM are used for each character. The lower 3 bits of the character codes from 0–7 and 8–15 select the groups of 8 fields in the CGRAM memory.
Reading and writing to the DDRAM is done by setting the RS input high during bus transfers. The DDRAM must also be selected by using the Set DDRAM address command which selects the DDRAM for access and also sets the starting address for DDRAM access.
Likewise reading and writing to the CGRAM is done by setting the RS input high during bus transfers. The CGRAM must also be selected by the Set CGRAM address command which selects the CGRAM for access and also sets the starting address for CGRAM access.
The execution times listed in this table are based on an oscillator frequency of 270 kHz. The data sheet indicates that for a resistor of 91 kΩ at V$_{CC}$=5 V the oscillator can vary between 190 kHz and 350 kHz resulting in wait times of 52.6 μs and 28.6 μs instead of 37 μs. If a display with the recommended 91 kΩ resistor is powered from 3.3 volts the oscillator will run much slower. If the busy bit is not used and instructions are timed by the external circuitry, this should be taken into account.

## Font

The original HD44780 character generator ROM contains 208 characters in a 5×8 dot matrix, and 32 characters in a 5×10 dot matrix. More recent compatible chips are available with higher resolution, matched to displays with more pixels.
Two versions of the ROM have been developed:
* HD44780UA00, the standard (Japanese) version, which includes katakana characters and some Greek letters and mathematical symbols
* HD44780UA02, a European version, which includes the complete set of Greek, Cyrillic and Western European characters (with diacritics)
The 7-bit ASCII subset for the Japanese version is non-standard: it supplies a Yen symbol where the backslash character is normally found, and left and right arrow symbols in place of tilde and the rubout character.
A limited number of custom characters can be programmed into the device in the form of a bitmap using special commands. These characters have to be written to the device each time it is switched on, as they are stored in volatile memory.