# Alchemy (processor)

Alchemy is a family of ultra low power embedded microprocessors originally designed by Alchemy Semiconductor for communication and media devices. Alchemy processors are SoCs integrating a CPU core, a memory controller, and a varying set of peripherals. All members of the family use the Au1 CPU core implementing the MIPS32 instruction set by MIPS Technologies.

## History

Alchemy Semiconductor was a fabless semiconductor company based in Austin, Texas. Founded in 1999 with a seed investment by Cadence Design Systems it licensed the 32-bit MIPS architecture to design, develop, and market high performance, ultra low power SoCs for the Internet Edge Device market. Peripherals were licensed from third parties. The founding team included former members of DEC's Austin Research and Design Center working on the StrongARM project, dissolved after DEC sold its microprocessors business to Intel. In May 2000 Alchemy Semiconductor became an independent company.
Alchemy Semiconductor unveiled the first member of the family, the Au1000 processor, at the Embedded Processor Forum in San Jose, CA, on June 13, 2000, with limited customer sampling in February 2001 and availability in production quantities in Q2 of that year, followed in 2001 and 2002 by the Au1500 and Au1100.
In February 2002 AMD acquired Alchemy in order to compete with Intel's ARM-based XScale processors, successor to the StrongARM line. They expanded the family with the Au1550 Security Network Processor and the Au1200 processor optimized for PMP applications, as well as the Am1772 wireless chipset consisting of the Am1770 transceiver and Am1771 integrated baseband/MAC chips. In Summer 2006 AMD sold its Alchemy assets to Raza Microelectronics, later renamed RMI Corporation. This company introduced the Au1210 and Au1250, based on and pin-compatible with the Au1200, and finally in 2009 the Au1300 series integrating a graphics processor. RMI merged with NetLogic Microsystems in late 2009, itself acquired by Broadcom Corporation in February 2012. Broadcom continued to sell Alchemy processors, if only under long term availability obligations, until at least 2017.

## Au1 CPU core

The Au1 CPU core designed by Alchemy implements the MIPS32 ISA Release 1 and supports the MIPS EJTAG interface. A floating-point unit is not present, FP instructions generate an exception and can be emulated by software. Code compression (MIPS16) and the optional Supervisor Mode were also omitted. Virtual address translation is TLB-based and relies on a fast exception handler rather than a hardware table walker. The core supports eight interrupt sources with prioritization by software. It has two low power modes where the clocks to all core units are stopped, one mode exempting the data cache to maintain cache coherency with the rest of the system.
Au1 is a scalar, in-order microarchitecture with a classic five stage RISC pipeline enhanced by several optimizations. It includes a 16 KiB, 4-way set associative instruction cache, a 16 KiB, 4-way, write-back, read-allocate data cache, a register file, a write buffer, and a 16/32-bit multiply-accumulate unit and 1 bit/cycle hardware divider. The cache supports prefetching by software, locking of cache lines, and a streaming mode. All pipeline stages complete in one cycle when data is available, and all pipeline hazards and dependencies are enforced by hardware interlocks. A few instructions require multiple cycles.

## Alchemy SoC

The Au1000 SoC is rated for core frequencies up to 500 MHz. At 400 MHz it operates at 1.5 V and the chip consumes no more than 500 mW, with a performance of over 900 Dhrystone-2.1 MIPS/Watt according to Alchemy Semiconductor. Au1000 and Au1500 processors were fabricated on a TSMC 180 nm LV logic 1.5V/3.3V 1P6M process, the Au1100 reduced power consumption further with a TSMC 130 nm process. Manufacturing details of later models were not disclosed.
The CPU core, the integrated memory controllers and peripherals are linked by an internal 32-bit system bus (SBUS) running at up to one half of the CPU core frequency. Slower non-bus master capable peripherals are attached with an ancillary peripheral bus. The core's data cache snoops the SBUS for coherency with other bus masters, e.g. a DMA engine. Au12xx models integrate a 64-bit side bus (RBUS) for peripherals requiring more bandwidth from the memory controller. Au13xx models have one RBUS per memory channel.
All Alchemy processors integrate a DRAM controller, a static bus controller, an 8-channel DMA controller for data transfers between memory and peripherals, interrupt controllers, timers, and a power management unit. The static bus controller supports SRAM, ROM, NAND/NOR Flash (Au1550), page mode Flash/ROM, PCMCIA/CompactFlash devices, and I/O peripherals such as an external LCD controller, IDE PIO mode up to ≈80 Mbit/s (Au12xx), or ATA-6/UDMA mode 5 (Au13xx). Au1550 and later processors have a more flexible 16-channel descriptor-based DMA controller. The Au1550 integrates a SafeNet Security Engine providing an entropy-based random number generator and accelerating the DES, 3DES, AES, and RC4 encryption algorithms, and the MD5 and SHA-1 hash algorithms.
Au1100 processors integrate an LCD controller which supports panels up to 800 × 600 pixels with 16 bit color depth. The LCD controller of Au12xx processors supports up to 2K resolution and up to 24 bits per pixel, four overlay windows, alpha blending, and gamma correction. The Camera Interface Module pins out an ITU-R BT.656 compatible 8/9/10-bit bus running at up to 33 MHz, and supports UYVY (YUV 4:2:2) and Bayer RGB to planar format conversion. The Media Acceleration Engine accelerates video decoding and supports the formats MPEG-1/2/4, DivX-3/4/5, H.263, and WMV 9/VC-1 at resolutions up to 720 × 576. It supports hardware colorspace conversion and image scaling with a 4-tap filter, also for the CIM. The MAE2 peripheral of Au13xx processors adds support for the H.264 and JPEG standards, hardware bit stream decoding, and resolutions up to 720p. The Graphics Processing Engine available on some Au13xx processors is an ARM Mali-200 and accelerates 2D and 3D graphics compatible with OpenVG 1.1 and OpenGL ES 1.1 and 2.0.
Each member of the family was available with different core frequency and hence power ratings, commercial and industrial temperature ranges, in a Pb-free or (earlier models) standard package. A low profile, fine pitch plastic ball grid array (LF-PBGA) package was used for all models, with ball counts from 324 (Au1000) to 537 (Au13xx), pitch 0.65 mm to 1.0 mm, and package size 17 mm × 17 mm × 1.7 mm to 23 mm × 23 mm × 1.5 mm.

## Alchemy Processor Family

| Series | Launch | Core frequ. (MHz) | TDP (mW) | DRAM | Static Bus | Integrated Peripherals | Integrated Peripherals | Integrated Peripherals | Integrated Peripherals | Integrated Peripherals | Integrated Peripherals | Integrated Peripherals | Integrated Peripherals | Integrated Peripherals | Integrated Peripherals | Integrated Peripherals | Integrated Peripherals | Datasheet | Notes |
| Series | Launch | Core frequ. (MHz) | TDP (mW) | DRAM | Static Bus | PCI | LCD | GPE | CIM | MAE | Hardware de/encrypt. | USB host ports | USB device port | Ethernet | SD card | Low speed busses | GPIOs max. | Datasheet | Notes |
| by Alchemy Semiconductor (2000–2002) ||||||||||||||||||||
| Au1000 | 2000-06-13 (announced) 2001-Q2 (available) | 266-500 | 300-900 typ. | 32-bit SDR-133 | 32-bit data/address | - | - | - | - | - | - | 2 × 1.1 | 1.1 | 2 × 10/100 | - | AC'97, I²S, IrDA, 2 × SSI, 4 × UART | 32 | | |
| Au1500 | 2001-06-11 (announced) 2001-12 (available) | 333-500 | 400-1200 typ. | 32-bit SDR-133 | 32-bit data/address | 2.2, 32 bit, 33/66 MHz | - | - | - | - | - | 2 × 1.1 | 1.1 | 2 × 10/100 | - | AC'97, 2 × UART | 39 | | |
| Au1100 | 2002-04-08 (announced) | 333-500 | 200-400 typ. | 32-bit SDR-133 2.5V/3.3V | 32-bit data/address | - | v1 | - | - | - | - | 2 × 1.1 | 1.1 | 1 × 10/100 | 2 × 1.1 | AC'97, I²S, IrDA, 2 × SSI, 3 × UART | 48 | | |
| by AMD (2002–2006) ||||||||||||||||||||
| Au1550 | 2004-02-24 (announced) | 333-500 | 400-600 typ., 1460 max. | 16/32-bit SDR-166/ DDR-400 | 32-bit data, 29-bit addr. | 2.2, 32 bit, 33/66 MHz | - | - | - | - | Security Engine | 2 × 1.1 | 1.1 OTG | 2 × 10/100 | 2 × 1.1 | 4 × PSC, 3 × UART | 43 | | |
| Au1200 | 2005-01-03 | 333-500 | 1600 max. | 16/32-bit DDR-400/ DDR2-533 | 16-bit data, 15/30-bit addr. | - | v2 | - | v1 | v1 | AES-128 | 1 × 2.0 | 2.0 OTG | - | 2 × 1.1 | 4 × PSC, 2 × UART | 48 | | |
| by RMI (2006–2009), NetLogic (2009–2011), Broadcom (2011–current) ||||||||||||||||||||
| Au1210 | 2007-01-09 (announced) 2007-06 (available) | 333-400 | 360-420 typ., 1000 max. | 16/32-bit DDR-400/ DDR2-533 | 16-bit data, 15/30-bit addr. | - | v2 | - | v1 | v1 | - | 1 × 2.0 | 2.0 OTG | - | 2 × 1.1 | 4 × PSC, 2 × UART | 48 | | |
| Au1250 | 2007-01-09 (announced) 2007-06 (available) | 400-700 | 560-580 typ., 1400 max. | 16/32-bit DDR-400/ DDR2-533 | 16-bit data, 15/30-bit addr. | - | v2 | - | v1 | v1 | AES-128 | 1 × 2.0 | 2.0 OTG | - | 2 × 1.1 | 4 × PSC, 2 × UART | 48 | | |
| Au1310 | 2009-01 (announced) | 533 | | 2 × 16-bit DDR2-667 | 16-bit data, 15/30-bit addr. | - | v2? | - | v2 | v2 | - | 1 × 2.0 | 2.0 OTG | - | 3 × ?, one port supporting 8-bit eMMC 4.3 | 4 × PSC, 4 × UART | 75 | | |
| Au1320 | 2009-01 (announced) | 667 | | 2 × 16-bit DDR2-667 | 16-bit data, 15/30-bit addr. | - | v2? | ✓ | v2 | v2 | ? | 1 × 2.0 | 2.0 OTG | - | 3 × ?, one port supporting 8-bit eMMC 4.3 | 4 × PSC, 4 × UART | 75 | | |
| Au1340 | 2009-01 (announced) | 533-667 | | 2 × 16-bit DDR2-667 | 16-bit data, 15/30-bit addr. | - | v2? | - | v2 | v2 | - | 1 × 2.0 | 2.0 OTG | - | 3 × ?, one port supporting 8-bit eMMC 4.3 | 4 × PSC, 4 × UART | 75 | | |
| Au1350/Au1354 | 2009-01 (announced) | 533-800 | | 2 × 16-bit DDR2-667 | 16-bit data, 15/30-bit addr. | - | v2? | ✓ | v2 | v2 | AES-128 | 1 × 2.0 | 2.0 OTG | - | 3 × ?, one port supporting 8-bit eMMC 4.3 | 4 × PSC, 4 × UART | 75 | | |
| Au1370/Au1374 | 2009-01 (announced) | 667-800 | | 2 × 16-bit DDR2-667 | 16-bit data, 15/30-bit addr. | - | v2? | - | v2 | v2 | - | 1 × 2.0 | 2.0 OTG | - | 3 × ?, one port supporting 8-bit eMMC 4.3 | 4 × PSC, 4 × UART | 75 | | |
| Au1380/Au1384 | 2009-01 (announced) | 667-1000 | | 2 × 16-bit DDR2-667 | 16-bit data, 15/30-bit addr. | - | v2? | ✓ | v2 | v2 | AES-128 | 1 × 2.0 | 2.0 OTG | - | 3 × ?, one port supporting 8-bit eMMC 4.3 | 4 × PSC, 4 × UART | 75 | | |
* 1 2 3 4 Programmable Serial Controller configurable as AC'97, I²S, SPI, SMBus interface.
* 1 2 3 15-bit address bus, 30 bit with an external latch.
* ↑ Used in CD-R King notebooks.

## Applications

Alchemy processors were marketed for wireless gateways and access points; VoIP, navigation, and NAS devices; STBs, thin clients, portable and automotive TV and media players, and digital photo frames.
Examples are the Sun Ray 2 family of thin clients., Several Cowon PMP devices, Dell DRAC5 remote administration cards, AirPort Extreme Base Station, embedded products for networking by Sun Microsystems; 4G Systems MTX-1 AccessCube MeshCube