# Zilog Z280

The Zilog Z280 is a 16-bit microprocessor designed by Zilog as an enhancement of the Zilog Z80 architecture and integrating improvements from the abandoned Zilog Z800 project. First introduced in July 1987, the Z280 is considered to be a commercial failure.
The Z280 was fabricated in CMOS, added a memory management unit (MMU) to expand the addressing range to 16 MB, features for multitasking and multiprocessor and coprocessor configurations, and 256 bytes of on-chip static RAM, configurable as either a cache for instructions and/or data, or as part of the ordinary address space. It has a huge number of new instructions and addressing modes giving a total of over 2000 combinations. It offers Supervisor and User operating modes, and optionally separate address spaces for instructions and data in both modes (four total possible address spaces). Its crystal or external clock signal is divided by half to drive the CPU. The CPU clock can be further divided by 1, 2, or 4 times to drive the bus (e.g. 12 MHz CPU divided by 4 will drive the bus at 3 MHz). Unlike the Z80 the Z280 multiplexes the lowest byte of its address onto the data bus; the rest of the address lines are not multiplexed. If running in Z-BUS mode, the data bus is expanded to 16 bits, multiplexed with the lower 16 bits of address. Although the z280 universally handles 16-bit math, moves, and even has a 16-bit bus option, it only supports 8-bit operations for logic functions such as AND, OR, and XOR.
More successful extensions of the Z80-architecture include the Hitachi HD64180 in 1986 and Zilog eZ80 in 2001, among others.
The Z280 had many advanced features for its time, most of them never seen again on a Zilog processor:
* On-chip instruction and/or data cache, or on-chip RAM
* Instruction pipelining
* High performance 16-bit Z-BUS interface or 8-bit Z80-compatible bus interface
* Built-in MMU with memory protection
* Ability to determine which register set is in context with instructions JAF and JAR
* Three on-chip 16-bit counter/timers
* Four on-chip DMA channels
* On-chip full duplex UART
* User I/O trap
* Supervisor mode (privileged instructions)
* Illegal instruction trap
* Coprocessor emulation trap
* Burst mode memory access
* Multiprocessor support, with many bus configuration modes
* Support for multiple external coprocessors through an accelerated communication interface
* Multiple I/O pages, which also allows for internal I/O devices without restricting the address range of the I/O ports like on eZ80, or conflicting with existing motherboard devices, like the Z180.
* Stack overflow warning
In the early 1990s, a small number of single-board computers based on the Zilog Z280 were designed and produced by Tilmann Reh, but the CPU was never used in any commercially produced computer.
In 2016, Lamar Owens contacted Tilmann Reh and obtained permission to have a small new run of the CPU280 system PCB's created, getting ten boards made and distributed to several beta builders. Wayne Warthen developed a build setup to rebuild the EPROM images and floppy disk images, and set up a page at Github for distribution and development. In spring 2018, another ten boards were made.