# NOP (code)

In computer science, a NOP, no-op, or NOOP (pronounced "no op"; short for no operation) is a machine language instruction and its assembly language mnemonic, programming language statement, or computer protocol command that does nothing.

## Machine language instructions

Some computer instruction sets include an instruction whose explicit purpose is to not change the state of any of the programmer-accessible registers, status flags, or memory. It often takes a well-defined number of clock cycles to execute. In other instruction sets, there is no explicit NOP instruction, but the assembly language mnemonic NOP represents an instruction which acts as a NOP; e.g., on the SPARC, sethi 0, %g0.
A NOP must not access memory, as that could cause a memory fault or page fault.
A NOP is most commonly used for timing purposes, to force memory alignment, to prevent hazards, to occupy a branch delay slot, to render void an existing instruction such as a jump, as a target of an execute instruction, or as a place-holder to be replaced by active instructions later on in program development (or to replace removed instructions when reorganizing would be problematic or time-consuming). In some cases, a NOP can have minor side effects; for example, on the Motorola 68000 series of processors, the NOP opcode causes a synchronization of the pipeline.
Listed below are the NOP instruction for some CPU architectures:
| CPU architecture | Instruction mnemonic | Bytes | Opcode | Notes |
| Intel x86 CPU family | NOP | 1 | 0x90 | 0x90 is the one-byte encoding for XCHG AX,AX in 16-bit code and XCHG EAX,EAX in 32-bit code. In long mode, XCHG RAX,RAX requires two bytes, as it would begin with an REX.W prefix, making the encoding 0x48 0x90. However, 0x90 is interpreted as a NOP in long mode regardless of whether it is preceded by 0x48. |
| Intel x86 CPU family | multi-byte NOP | 2–9 for Pentium Pro and later Intel processors, and all AMD AMD64 processors | 0x66 0x90 0x0F 0x1F 0x00 0x0F 0x1F 0x40 0x00 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | 0x66 is the operand-size override prefix. 0x0F 0x1F is a two-byte NOP opcode that takes a ModR/M operand upon which no operation is performed. Operands added to this are: 0x00 is [EAX] 0x40 0x00 is [EAX + 00H] 0x44 0x00 0x00 is [EAX + EAX*1 + 00H] 0x80 0x00 0x00 0x00 0x00 is [EAX + 00000000H] 0x84 0x00 0x00 0x00 0x00 0x00 is [EAX + EAX*1 + 00000000H]. |
| Intel 8008 | LAA | 1 | 0xC0 | Load A from A |
| Intel 8051 / MCS-51 family | NOP | 1 | 0x00 | |
| Intel 8080, Intel 8085, Z80 | NOP | 1 | 0x00 | |
| Intel IA-64 (Itanium) | (qp) NOP.b imm21 | 41 bits | 0x04000000000 | On IA-64, the NOP instruction has five forms, each of which can be executed only on a particular execution unit type. All five NOP forms include a 6-bit qp field (bits 5:0) and a 21-bit immediate field (bit 36 + bits 25:6). These fields may be set to any value with no effect on the operation of the instruction. (The encodings listed here result from setting these fields to all-0s - which is common but not required). The NOP.x form of the instruction additionally consumes a second 41-bit instruction slot - the contents of this slot is considered to be providing 41 additional immediate-bits, for a total immediate-size of 62 bits. |
| Intel IA-64 (Itanium) | (qp) NOP.f imm21 | 41 bits | 0x00008000000 | On IA-64, the NOP instruction has five forms, each of which can be executed only on a particular execution unit type. All five NOP forms include a 6-bit qp field (bits 5:0) and a 21-bit immediate field (bit 36 + bits 25:6). These fields may be set to any value with no effect on the operation of the instruction. (The encodings listed here result from setting these fields to all-0s - which is common but not required). The NOP.x form of the instruction additionally consumes a second 41-bit instruction slot - the contents of this slot is considered to be providing 41 additional immediate-bits, for a total immediate-size of 62 bits. |
| Intel IA-64 (Itanium) | (qp) NOP.i imm21 | 41 bits | 0x00008000000 | On IA-64, the NOP instruction has five forms, each of which can be executed only on a particular execution unit type. All five NOP forms include a 6-bit qp field (bits 5:0) and a 21-bit immediate field (bit 36 + bits 25:6). These fields may be set to any value with no effect on the operation of the instruction. (The encodings listed here result from setting these fields to all-0s - which is common but not required). The NOP.x form of the instruction additionally consumes a second 41-bit instruction slot - the contents of this slot is considered to be providing 41 additional immediate-bits, for a total immediate-size of 62 bits. |
| Intel IA-64 (Itanium) | (qp) NOP.m imm21 | 41 bits | 0x00008000000 | On IA-64, the NOP instruction has five forms, each of which can be executed only on a particular execution unit type. All five NOP forms include a 6-bit qp field (bits 5:0) and a 21-bit immediate field (bit 36 + bits 25:6). These fields may be set to any value with no effect on the operation of the instruction. (The encodings listed here result from setting these fields to all-0s - which is common but not required). The NOP.x form of the instruction additionally consumes a second 41-bit instruction slot - the contents of this slot is considered to be providing 41 additional immediate-bits, for a total immediate-size of 62 bits. |
| Intel IA-64 (Itanium) | (qp) NOP.x imm62 | 41+41 bits | 0x00008000000 imm41 | On IA-64, the NOP instruction has five forms, each of which can be executed only on a particular execution unit type. All five NOP forms include a 6-bit qp field (bits 5:0) and a 21-bit immediate field (bit 36 + bits 25:6). These fields may be set to any value with no effect on the operation of the instruction. (The encodings listed here result from setting these fields to all-0s - which is common but not required). The NOP.x form of the instruction additionally consumes a second 41-bit instruction slot - the contents of this slot is considered to be providing 41 additional immediate-bits, for a total immediate-size of 62 bits. |
| DEC Alpha | NOP | 4 | 0x47FF041F | Opcode for BIS r31,r31,r31, an instruction that bitwise-ORs the always-0 register with itself. |
| AMD 29k | NOP | 4 | 0x70400101 | Opcode for aseq 0x40,gr1,gr1, an instruction that asserts that the stack register is equal to itself. |
| ARM A32 | NOP | 4 | 0x*320F000 | Architectural ARM A32 NOP ("true" nop, with no register dependencies). Introduced with ARMv6K (ARM 1176, released in 2003), and present in all later ARM A32 processors. (The * indicates a 4-bit field that may take any value other than 0xF.) |
| ARM A32 | MOV r0,r0/NOP | 4 | 0xE1A00000 | Recommended A32 no-operation encoding for older 32-bit ARM processors that pre-date ARMv6K. Assemblers for A32 will usually output this opcode when given the "NOP" mnemonic unless they are told to target ARMv6K or later versions of the ARM architecture. |
| ARM A32 | ANDEQ r0,r0,r0 | 4 | 0x00000000 | Bitwise-AND r0 with itself if equal. Commonly used no-op encoding due to the simplicity of its encoding. |
| ARM A32 | MOVNV r0,r0 | 4 | 0xF1A00000 | Move r0 to itself never. Obsolete no-op encoding that used to be recommended for the ARM2/ARM3 processors in older Acorn Archimedes computers. Makes use of the NV ("never") condition code — which has been deprecated since 1993, with support fully removed with ARMv5. |
| ARM T32 (Thumb) | NOP | 2 | 0xBF00 | Architectural ARM T32 (Thumb-2) NOPs ("true" nops, with no register dependencies). Introduced with ARMv6T2 (ARM 1156, released in 2003), and present in all later ARM T32 processors. |
| ARM T32 (Thumb) | NOP.W | 4 | 0xF3AF8000 | Architectural ARM T32 (Thumb-2) NOPs ("true" nops, with no register dependencies). Introduced with ARMv6T2 (ARM 1156, released in 2003), and present in all later ARM T32 processors. |
| ARM T32 (Thumb) | MOV r8,r8/NOP | 2 | 0x46C0 | Recommended Thumb no-operation encoding for older 32-bit Thumb processors that pre-date ARMv6T2. Assemblers for T32 will usually output this opcode when given the "NOP" mnemonic unless they are told to target ARMv6T2 or later versions of the ARM Thumb architecture. |
| ARM A64 (64 bit) | NOP | 4 | 0xD503201F | Architectural NOP. |
| AVR | NOP | 2 | 0x0000 | one clock cycle |
| IBM System/360, IBM System/370, IBM System/390, z/Architecture, UNIVAC Series 90 | NOP | 4 | 0x47000000 or 0x470nnnnn or 0x47n0nnnn where "n" is any 4-bit value. | The NOP ("No-Op") and NOPR ("No-Op Register") are a subset of the "Branch on Condition" or "Branch on Condition Register" instructions, respectively; both versions have two options for generating a NO-OP. In the case of both the NOP and NOPR instructions, the first 0 in the second byte is the "mask" value, the condition to test such as equal, not equal, high, low, etc. If the mask is 0, no branch occurs. In the case of the NOPR instruction, the second value in the second byte is the register to branch on. If register 0 is chosen, no branch occurs regardless of the mask value. Thus, if either of the two values in the second byte is 0, the branch will not happen. If the first 0 in the second byte is 0, the value of the second value in the second byte is irrelevant on most processors; however, on the IBM System/360 Model 91, if that value refers to register 15, the instruction will wait for all previously-decoded instructions to complete before continuing. In the case of the NOP instruction, the second value in the second byte is the "base" register of a combined base register, displacement register and offset address. If the base register is also 0, the branch is not taken regardless of the value of the displacement register or displacement address. |
| IBM System/360, IBM System/370, IBM System/390, z/Architecture, UNIVAC Series 90 | NOPR | 2 | 0x0700 or 0x070n or 0x07n0 where "n" is any 4-bit value. | The NOP ("No-Op") and NOPR ("No-Op Register") are a subset of the "Branch on Condition" or "Branch on Condition Register" instructions, respectively; both versions have two options for generating a NO-OP. In the case of both the NOP and NOPR instructions, the first 0 in the second byte is the "mask" value, the condition to test such as equal, not equal, high, low, etc. If the mask is 0, no branch occurs. In the case of the NOPR instruction, the second value in the second byte is the register to branch on. If register 0 is chosen, no branch occurs regardless of the mask value. Thus, if either of the two values in the second byte is 0, the branch will not happen. If the first 0 in the second byte is 0, the value of the second value in the second byte is irrelevant on most processors; however, on the IBM System/360 Model 91, if that value refers to register 15, the instruction will wait for all previously-decoded instructions to complete before continuing. In the case of the NOP instruction, the second value in the second byte is the "base" register of a combined base register, displacement register and offset address. If the base register is also 0, the branch is not taken regardless of the value of the displacement register or displacement address. |
| SuperH | NOP | 2 | 0x0009 | |
| MIPS | NOP | 4 | 0x00000000 | Stands for sll r0,r0,0, meaning: Logically shift register 0 zero bits to the left and store the result in register 0. Writes to register 0 are ignored; it always contains 0. |
| MIPS-X | NOP | 4 | 0x60000019 | (extended opcode for add r0,r0,r0) |
| MIX | NOP | 1 word | ± * * * * 0 | The * bytes are arbitrary, and can be anything from 0 to the maximum byte (required to be in the range 63-99). MIX uses sign-magnitude representation. |
| MMIX | SWYM | 4 | 0xFD****** | SWYM stands for "Sympathize with your machinery". The * digits can be chosen arbitrarily. |
| Motorola 6800 | NOP | 1 | 0x01 | |
| Motorola 68000 family | NOP | 2 | 0x4E71 | This synchronizes the pipeline and prevents instruction overlap.$^{:3-21}$$^{:4-147}$ |
| Motorola 68000 family | TRAPF, TRAPF.W #data, TRAPF.L #data | 2, 4, 6 | 0x51FC, 0x51FA 0xnnnn, 0x51FB 0xnnnn 0xnnnn | Trap if false. Suggested opcode for 68020 and later 68k processors if a NOP without pipeline synchronization is desired. ('n' may take any 4-bit value.)$^{:3-21}$$^{:4-189}$ |
| Motorola 6809 | NOP | 1 | 0x12 | |
| MOS Technology 65xx (e.g. 6502) | NOP | 1 | 0xEA | NOP consumes two clock cycles. Undefined opcodes in the NMOS versions of the 65xx family were converted to be NOPs of varying instruction lengths and cycle times in the 65C02. |
| PA-RISC | NOP | 4 | 0x08000240 | Opcode for OR 0,0,0. |
| PA-RISC | LDI 26,0 | 4 | 0x34000034 | Palindromic NOP - that is, an instruction that executes as NOP regardless of whether byte order is interpreted as little-endian or big-endian. Some PA-RISC system instructions are required to be followed by seven palindromic NOPs. |
| POWER, PowerPC, Power ISA | NOP | 4 | 0x60000000 | Opcode for ori r0,r0,0. Under the Power ISA, many apparent no-op instruction encodings have significant side-effects − therefore, no-op encodings other than ori r0,r0,0 should be carefully avoided unless these side-effects are specifically intended. For example: ori r31,r31,0 is a serializing instruction. or rX,rX,rX with X=1,2,3,5,6,7 or 31 sets thread priority based on X. or r26,r26,r26 is a memory store writeback hint. xori r0,r0,0 is an explicitly unoptimized no-op for use in timing-loops. and rX,rX,rX with X=0,1 are performance-probe no-ops. ori r2,r2,0 is a "group ending NOP" in some POWER CPUs |
| PIC microcontroller | NOP | 12 bits | 0b000000000000 | |
| RISC-V | NOP | 4 | 0x00000013 | ADDI x0, x0, 0 |
| RISC-V | C.NOP | 2 | 0x0001 | C.ADDI x0, 0. Only available on RISC-V CPUs that support the "C" (compressed instructions) extension. |
| Signetics 8X300 | MOV AUX, AUX | 16 bits | 0x0000 | Move AUX to AUX with no rotate |
| SPARC | NOP | 4 | 0x01000000 | Stands for sethi 0, %g0 which zeroes the hardwired-to-zero %g0 register |
| PDP-10 | JFCL 0, (conventional) JUMP, SETA, SETAI, CAI, TRN, TLN | 1 word | 25500******* (octal) | Jump never Jump never, set nothing, skip never |
| PDP-11 | NOP | 2 | 000240 (octal) | Clear none of the condition codes |
| VAX | NOP | 1 | 0x01 | Delay is dependent on processor type |
| WD16 | NOP | 2 | 0x0000 | |
| LoongArch | NOP | 4 | 0x03400000 | Opcode for andi r0,r0,0, an instruction that bitwise-ANDs the always-0 register with zero. |
From a hardware design point of view, unmapped areas of a bus are often designed to return zeroes; since the NOP slide behavior is often desirable, it gives a bias to coding it with the all-zeroes opcode.

## Code

A function or a sequence of programming language statements is a NOP or null statement if it has no effect. Null statements may be required by the syntax of some languages in certain contexts.

### Ada

In Ada, the null statement serves as a NOP. As the syntax forbids that control statements or functions be empty, the null statement must be used to specify that no action is required. (Thus, if the programmer forgets to write a sequence of statements, the program will fail to compile.)

### C and derivatives

The simplest NOP statement in C is the null statement, which is just a semi-colon in a context requiring a statement.
Most C compilers generate no code for null statements, which has historical and performance reasons.
An empty block (compound statement) is also a NOP, and may be more legible, but will still have no code generated for it by the compiler.
In some cases, such as the body of a function, a block must be used, but this can be empty. In C, statements cannot be empty—simple statements must end with a ; (semicolon) while compound statements are enclosed in (braces), which does not itself need a following semicolon. Thus in contexts where a statement is grammatically required, some such null statement can be used.
The null statement is useless by itself, but it can have a syntactic use in a wider context, e.g., within the context of a loop:
alternatively,
or more tersely:
(note that the last form may be confusing, and as such generates a warning with some compilers or compiler options, as semicolon usually indicates an end of function call instruction when placed after a parenthesis on the end of line).
The above code continues calling the function getchar until it returns a \n (newline) character, essentially fast-forwarding the current reading location of standard input to the beginning of next line.

### Fortran

In Fortran, the CONTINUE statement is used in some contexts such as the last statement in a DO loop, although it can be used anywhere, and does not have any functionality.

### JavaScript

The JavaScript language does not have a built-in NOP statement. Many implementations are possible:
* Use the ; empty statement or the empty block statement the same way as in the C and derivatives examples;
* Use the undefined or the null expression as a complete statement (an expression statement) when the previous methods are not allowed by the syntax.
Alternatives, in situations where a function is required, are:
* Use the Function.prototype built-in function, that accepts any arguments and returns undefined;
* Use a NOP function available in a third-party library —see below;
* Define a custom NOP function, as in the following example (using the ES6 arrow function syntax):

#### AngularJS

The AngularJS framework provides angular.noop function that performs no operations.

#### jQuery

The jQuery library provides a function jQuery.noop, which does nothing.

#### Lodash

The Lodash library provides a function _.noop, which returns undefined and does nothing.

### Pascal

As with C, the ; used by itself can be used as a null statement in Pascal. In fact, due to the specification of the language, in a BEGIN / END block, the semicolon is optional before the END statement, thus a semicolon used there is superfluous.
Also, a block consisting of BEGIN END; may be used as a placeholder to indicate no action, even if placed inside another BEGIN / END block.

### Python

The Python programming language has a pass statement which has no effect when executed and thus serves as a NOP. It is primarily used to ensure correct syntax due to Python's indentation-sensitive syntax; for example the syntax for definition of a class requires an indented block with the class logic, which has to be expressed as pass when it should be empty.

### Shell scripting (bash, zsh, etc.)

The ':' [colon] command is a shell builtin that has similar effect to a "NOP" (a do-nothing operation). It is not technically an NOP, as it changes the special parameter $? (exit status of last command) to 0. It may be considered a synonym for the shell builtin 'true', and its exit status is true (0).

### TeX macro language (ConTeXt, LaTeX, etc.)

The TeX typographical system's macro language has the \relax command. It does nothing by itself, but may be used to prevent the immediately preceding command from parsing any subsequent tokens.

## NOP protocol commands

Many computer protocols, such as telnet, include a NOP command that a client can issue to request a response from the server without requesting any other actions. Such a command can be used to ensure the connection is still alive or that the server is responsive. A NOOP command is part of the following protocols (this is a partial list):
* telnet
* FTP
* SMTP
* X11
* POP3
* NNTP
* finger
* IMAP4
* BitTorrent
Note that unlike the other protocols listed, the IMAP4 NOOP command has a specific purpose—it allows the server to send any pending notifications to the client.
While most telnet or FTP servers respond to a NOOP command with "OK" or "+OK", some programmers have added quirky responses to the client. For example, the ftpd daemon of MINIX responds to NOOP with the message:

## Cracking

NOPs are often involved when cracking software that checks for serial numbers, specific hardware or software requirements, presence or absence of hardware dongles, etc. in the form of a NOP slide. This process is accomplished by altering functions and subroutines to bypass security checks and instead simply return the expected value being checked for. Because most of the instructions in the security check routine will be unused, these would be replaced with NOPs, thus removing the software's security functionality without altering the positioning of everything which follows in the binary.

## Security exploits

The NOP opcode can be used to form a NOP slide, which allows code to execute when the exact value of the instruction pointer is indeterminate (e.g., when a buffer overflow causes a function's return address on the stack to be overwritten).