# Turbo code

In information theory, turbo codes are a class of high-performance forward error correction (FEC) codes developed around 1990–91, but first published in 1993. They were the first practical codes to closely approach the maximum channel capacity or Shannon limit, a theoretical maximum for the code rate at which reliable communication is still possible given a specific noise level. Turbo codes are used in 3G/4G mobile communications (e.g., in UMTS and LTE) and in (deep space) satellite communications as well as other applications where designers seek to achieve reliable information transfer over bandwidth- or latency-constrained communication links in the presence of data-corrupting noise. Turbo codes compete with low-density parity-check (LDPC) codes, which provide similar performance. Until the patent for turbo codes expired, the patent-free status of LDPC codes was an important factor in LDPC's continued relevance.
The name "turbo code" arose from the feedback loop used during normal turbo code decoding, which was analogized to the exhaust feedback used for engine turbocharging. Hagenauer has argued the term turbo code is a misnomer since there is no feedback involved in the encoding process.

## History

The fundamental patent application for turbo codes was filed on 23 April 1991. The patent application lists Claude Berrou as the sole inventor of turbo codes. The patent filing resulted in several patents including US Patent 5,446,747, which expired 29 August 2013.
The first public paper on turbo codes was "Near Shannon Limit Error-correcting Coding and Decoding: Turbo-codes". This paper was published 1993 in the Proceedings of IEEE International Communications Conference. The 1993 paper was formed from three separate submissions that were combined due to space constraints. The merger caused the paper to list three authors: Berrou, Glavieux, and Thitimajshima (from Télécom Bretagne, former ENST Bretagne, France). However, it is clear from the original patent filing that Berrou is the sole inventor of turbo codes and that the other authors of the paper contributed material other than the core concepts.
Turbo codes were so revolutionary at the time of their introduction that many experts in the field of coding did not believe the reported results. When the performance was confirmed a small revolution in the world of coding took place that led to the investigation of many other types of iterative signal processing.
The first class of turbo code was the parallel concatenated convolutional code (PCCC). Since the introduction of the original parallel turbo codes in 1993, many other classes of turbo code have been discovered, including serial concatenated convolutional codes and repeat-accumulate codes. Iterative turbo decoding methods have also been applied to more conventional FEC systems, including Reed–Solomon corrected convolutional codes, although these systems are too complex for practical implementations of iterative decoders. Turbo equalization also flowed from the concept of turbo coding.
In addition to turbo codes, Berrou also invented recursive systematic convolutional (RSC) codes, which are used in the example implementation of turbo codes described in the patent. Turbo codes that use RSC codes seem to perform better than turbo codes that do not use RSC codes.
Prior to turbo codes, the best constructions were serial concatenated codes based on an outer Reed–Solomon error correction code combined with an inner Viterbi-decoded short constraint length convolutional code, also known as RSV codes.
In a later paper, Berrou gave credit to the intuition of "G. Battail, J. Hagenauer and P. Hoeher, who, in the late 80s, highlighted the interest of probabilistic processing." He adds "R. Gallager and M. Tanner had already imagined coding and decoding techniques whose general principles are closely related," although the necessary calculations were impractical at that time.

## An example encoder

There are many different instances of turbo codes, using different component encoders, input/output ratios, interleavers, and puncturing patterns. This example encoder implementation describes a classic turbo encoder, and demonstrates the general design of parallel turbo codes.
This encoder implementation sends three sub-blocks of bits. The first sub-block is the m-bit block of payload data. The second sub-block is n/2 parity bits for the payload data, computed using a recursive systematic convolutional code (RSC code). The third sub-block is n/2 parity bits for a known permutation of the payload data, again computed using an RSC code. Thus, two redundant but different sub-blocks of parity bits are sent with the payload. The complete block has m + n bits of data with a code rate of m/(m + n). The permutation of the payload data is carried out by a device called an interleaver.
Hardware-wise, this turbo code encoder consists of two identical RSC coders, C$_1$ and C$_2$, as depicted in the figure, which are connected to each other using a concatenation scheme, called parallel concatenation:
In the figure, M is a memory register. The delay line and interleaver force input bits d$_k$ to appear in different sequences. At first iteration, the input sequence d$_k$ appears at both outputs of the encoder, x$_k$ and y$_{1k}$ or y$_{2k}$ due to the encoder's systematic nature. If the encoders C$_1$ and C$_2$ are used in n$_1$ and n$_2$ iterations, their rates are respectively equal to
    ${\begin{aligned}~R_{1}&={\frac {n_{1}+n_{2}}{2n_{1}+n_{2}}}\\~R_{2}&={\frac {n_{1}+n_{2}}{n_{1}+2n_{2}}}\end{aligned}}$

## The decoder

The decoder is built in a similar way to the above encoder. Two elementary decoders are interconnected to each other, but in series, not in parallel. The $\textstyle DEC_{1}$ decoder operates on lower speed (i.e., $\textstyle R_{1}$), thus, it is intended for the $\textstyle C_{1}$ encoder, and $\textstyle DEC_{2}$ is for $\textstyle C_{2}$ correspondingly. $\textstyle DEC_{1}$ yields a soft decision which causes $\textstyle L_{1}$ delay. The same delay is caused by the delay line in the encoder. The $\textstyle DEC_{2}$'s operation causes $\textstyle L_{2}$ delay.
An interleaver installed between the two decoders is used here to scatter error bursts coming from $\textstyle DEC_{1}$ output. DI block is a demultiplexing and insertion module. It works as a switch, redirecting input bits to $\textstyle DEC_{1}$ at one moment and to $\textstyle DEC_{2}$ at another. In OFF state, it feeds both $\textstyle y_{1k}$ and $\textstyle y_{2k}$ inputs with padding bits (zeros).
Consider a memoryless AWGN channel, and assume that at k-th iteration, the decoder receives a pair of random variables:
    ${\begin{aligned}~x_{k}&=(2d_{k}-1)+a_{k}\\~y_{k}&=2(Y_{k}-1)+b_{k}\end{aligned}}$
where $\textstyle a_{k}$ and $\textstyle b_{k}$ are independent noise components having the same variance $\textstyle \sigma ^{2}$. $\textstyle Y_{k}$ is a k-th bit from $\textstyle y_{k}$ encoder output.
Redundant information is demultiplexed and sent through DI to $\textstyle DEC_{1}$ (when $\textstyle y_{k}=y_{1k}$) and to $\textstyle DEC_{2}$ (when $\textstyle y_{k}=y_{2k}$).
$\textstyle DEC_{1}$ yields a soft decision; i.e.:
    $\Lambda (d_{k})=\log {\frac {p(d_{k}=1)}{p(d_{k}=0)}}$
and delivers it to $\textstyle DEC_{2}$. $\textstyle \Lambda (d_{k})$ is called the logarithm of the likelihood ratio (LLR). $\textstyle p(d_{k}=i),\,i\in \{0,1\}$ is the a posteriori probability (APP) of the $\textstyle d_{k}$ data bit which shows the probability of interpreting a received $\textstyle d_{k}$ bit as $\textstyle i$. Taking the LLR into account, $\textstyle DEC_{2}$ yields a hard decision; i.e., a decoded bit.
It is known that the Viterbi algorithm is unable to calculate APP, thus it cannot be used in $\textstyle DEC_{1}$. Instead of that, a modified BCJR algorithm is used. For $\textstyle DEC_{2}$, the Viterbi algorithm is an appropriate one.
However, the depicted structure is not an optimal one, because $\textstyle DEC_{1}$ uses only a proper fraction of the available redundant information. In order to improve the structure, a feedback loop is used (see the dotted line on the figure).

## Soft decision approach

The decoder front-end produces an integer for each bit in the data stream. This integer is a measure of how likely it is that the bit is a 0 or 1 and is also called soft bit. The integer could be drawn from the range [−127, 127], where:
* −127 means "certainly 0"
* −100 means "very likely 0"
* 0 means "it could be either 0 or 1"
* 100 means "very likely 1"
* 127 means "certainly 1"
This introduces a probabilistic aspect to the data-stream from the front end, but it conveys more information about each bit than just 0 or 1.
For example, for each bit, the front end of a traditional wireless-receiver has to decide if an internal analog voltage is above or below a given threshold voltage level. For a turbo code decoder, the front end would provide an integer measure of how far the internal voltage is from the given threshold.
To decode the m + n-bit block of data, the decoder front-end creates a block of likelihood measures, with one likelihood measure for each bit in the data stream. There are two parallel decoders, one for each of the n⁄2-bit parity sub-blocks. Both decoders use the sub-block of m likelihoods for the payload data. The decoder working on the second parity sub-block knows the permutation that the coder used for this sub-block.

## Solving hypotheses to find bits

The key innovation of turbo codes is how they use the likelihood data to reconcile differences between the two decoders. Each of the two convolutional decoders generates a hypothesis (with derived likelihoods) for the pattern of m bits in the payload sub-block. The hypothesis bit-patterns are compared, and if they differ, the decoders exchange the derived likelihoods they have for each bit in the hypotheses. Each decoder incorporates the derived likelihood estimates from the other decoder to generate a new hypothesis for the bits in the payload. Then they compare these new hypotheses. This iterative process continues until the two decoders come up with the same hypothesis for the m-bit pattern of the payload, typically in 15 to 18 cycles.
An analogy can be drawn between this process and that of solving cross-reference puzzles like crossword or sudoku. Consider a partially completed, possibly garbled crossword puzzle. Two puzzle solvers (decoders) are trying to solve it: one possessing only the "down" clues (parity bits), and the other possessing only the "across" clues. To start, both solvers guess the answers (hypotheses) to their own clues, noting down how confident they are in each letter (payload bit). Then, they compare notes, by exchanging answers and confidence ratings with each other, noticing where and how they differ. Based on this new knowledge, they both come up with updated answers and confidence ratings, repeating the whole process until they converge to the same solution.

## Performance

Turbo codes perform well due to the attractive combination of the code's random appearance on the channel together with the physically realisable decoding structure. Turbo codes are affected by an error floor.

## Practical applications using turbo codes

Telecommunications:
* Turbo codes are used extensively in 3G and 4G mobile telephony standards; e.g., in HSPA, EV-DO and LTE.
* MediaFLO, terrestrial mobile television system from Qualcomm.
* The interaction channel of satellite communication systems, such as DVB-RCS and DVB-RCS2.
* Recent NASA missions such as Mars Reconnaissance Orbiter use turbo codes as an alternative to Reed–Solomon error correction-Viterbi decoder codes.
* IEEE 802.16 (WiMAX), a wireless metropolitan network standard, uses block turbo coding and convolutional turbo coding.

## Bayesian formulation

From an artificial intelligence viewpoint, turbo codes can be considered as an instance of loopy belief propagation in Bayesian networks.