# Zen 5

Zen 5 ("Nirvana") is the name for a CPU microarchitecture by AMD, shown on their roadmap in May 2022, launched for mobile in July 2024 and for desktop in August 2024. It is the successor to Zen 4 and is currently fabricated on TSMC's N4P process. Zen 5 is also planned to be fabricated on the N3E process in the future.
The Zen 5 microarchitecture powers Ryzen 9000 series desktop processors (codenamed "Granite Ridge"), Epyc 9005 server processors (codenamed "Turin"), and Ryzen AI 300 thin and light mobile processors (codenamed "Strix Point").

## Background

Zen 5 was first officially mentioned during AMD's Ryzen Processors: One Year Later presentation on April 9, 2018.
A roadmap shown during AMD's Financial Analyst Day on June 9, 2022 confirmed that Zen 5 and Zen 5c would be launching in 3nm and 4nm variants in 2024. The earliest details on the Zen 5 architecture promised a "re-pipelined front end and wide issue" with "integrated AI and Machine Learning optimizations".
During AMD's Q4 2023 earnings call on January 30, 2024, AMD CEO Lisa Su stated that Zen 5 products would be "coming in the second half of the year".

## Architecture

Zen 5 is a ground-up redesign of Zen 4 with a wider front-end, increased floating point throughput and more accurate branch prediction.

### Fabrication process

Zen 5 was designed with both 4nm and 3nm processes in mind. This acted as an insurance policy for AMD in the event that TSMC's mass production of its N3 nodes were to face delays, significant wafer defect issues or capacity issues. One industry analyst estimated early N3 wafer yields to be at 55% while others estimated yields to be similar to those of N5 at between 60-80%. Additionally, Apple, as TSMC's largest customer, is given priority access to the latest process nodes. In 2022, Apple was responsible for 23% of TSMC's $72 billion in total revenue. After N3 began ramping at the end of 2022, Apple bought up the entirety of TSMC's early N3B wafer production capacity to fabricate their A17 and M3 SoCs. Zen 5 desktop and server processors continue to use the N6 node for the I/O die fabrication.
Zen 5 CCDs are fabricated on TSMC's N4X node which is intended to accommodate higher frequencies for high-performance computing (HPC) applications. Zen 4-based mobile processors were fabricated on the N4P node which is targeted more towards power efficiency. N4X maintains IP compatibility with N4P and offers a 6% frequency gain over N4P at the same power but comes with the trade-off of moderate leakage. Compared to the N5 node used to produce Zen 4 CCDs, N4X can enable up to 15% higher frequencies while running at 1.2V.
The Zen 5 CCD, codenamed "Eldora", has a die size of 70.6mm$^2$, a 0.5% reduction in area from Zen 4's 71mm$^2$ CCD while achieving a 28% increase in transistor density due to the N4X process node. Zen 5's CCD contains 8.315 billion transistors compared to the Zen 4 CCD's 6.5 billion transistors. The size of an individual Zen 5 core is actually larger than a Zen 4 core but the CCD has been reduced via shrinking the L3 cache. The monolithic die used by "Strix Point" mobile processors, fabricated on TSMC's lower power N4P node, measures 232.5mm$^2$ in area.

### Front end
#### Branch Prediction

Zen 5's changes to branch prediction are the most significant divergence from any previous Zen microarchitecture. The branch predictor in a core tries to predict the outcome when there are diverging code paths. Zen 5's branch predictor is able to operate two-ahead where it can predict up to two branches per clock cycle. Previous architectures were limited to one branch instruction per clock cycle, limiting the instruction fetch throughput of branch-heavy programs. Two-ahead branch predictors have been discussed in academic research dating back to André Seznec et al.'s 1996 paper "Multiple-block ahead branch predictors". 28 years after it was first proposed in academic research, AMD's Zen 5 architecture became the first microarchitecture to fully implement two-ahead branch prediction. Increased data prefetching assists the branch predictor.

### Execution Engines
#### Integer Units

Zen 5 contains 6 Arithmetic Logic Units (ALUs), up from 4 ALUs in prior Zen architectures. A greater number of ALUs that handle common integer operations can increase per-cycle scalar integer throughput by 50%.

#### Vector Engines and Instructions

The vector engine in Zen 5 features 4 floating point pipes compared to 3 pipes in Zen 4. Zen 4 introduced AVX-512 instructions. AVX-512 capabilities have been expanded with Zen 5 with a doubling of the floating point pipe width to a native 512-bit floating point datapath. The AVX-512 datapath is configurable depending on the product. Ryzen 9000 series desktop processors and EPYC 9005 server processors feature the full 512-bit datapath but Ryzen AI 300 mobile processors feature a 256-bit datapath in order to reduce power consumption. AVX-512 instruction has been extended to VNNI/VEX instructions. Additionally, there is greater bfloat16 throughput which is beneficial for AI workloads.

### Cache
#### L1

The wider front end in the Zen 5 architecture necessitates larger caches and higher memory bandwidth in order to keep the cores fed with data. The L1 cache per core is increased from 64 KB to 80 KB per core. The L1 instruction cache remains the same at 32 KB but the L1 data cache is increased from 32 KB to 48 KB per core. Furthermore, the bandwidth of the L1 data cache for 512-bit floating point unit pipes has also been doubled. The L1 data cache's associativity has increased from 8-way to 12-way in order to accommodate its larger size.

#### L2

The L2 cache remains at 1 MB but its associativity has increased from 8-way to 16-way. Zen 5 also has a doubled L2 cache bandwidth of 64 bytes per clock.

#### L3

The L3 cache is filled from L2 cache victims and in-flight misses. Latency for accessing the L3 cache has been reduced by 3.5 cycles. A Zen 5 Core Complex Die (CCD) contains 32 MB of L3 cache shared between the 8 cores. In Zen 5 3D V-Cache CCDs, a piece of silicon containing 64 MB of extra L3 cache is placed under the cores rather than on top like in prior generations for a total of 96 MB. This allows for increased core frequency compared to previous generation 3D V-Cache implementations which were sensitive to higher voltages. The Zen 5-based Ryzen 7 9800X3D has a 500 MHz increased base frequency over the Zen 4-based Ryzen 7 7800X3D and allows overclocking for the first time.
Ryzen AI 300 APUs, codenamed "Strix Point", features 24 MB of total L3 cache which is split into two separate cache arrays. 16 MB of dedicated L3 cache is shared the 4 Zen 5 cores and 8 MB is shared by the 8 Zen 5c cores. Zen 5c cores are not able to access the 16 MB L3 cache array and vice versa.
| Cache | Cache | Zen 4 | Zen 5 |
| L1 Data | Size | 32 KB | 48 KB |
| L1 Data | Associativity | 8-way | 12-way |
| L1 Data | Bandwidth | 32B/clk | 64B/clk |
| L1 Instructions | Size | 32 KB | 32 KB |
| L1 Instructions | Associativity | 8-way | 8-way |
| L1 Instructions | Bandwidth | 64B/clk | 64B/clk |
| L2 | Size | 1 MB | 1 MB |
| L2 | Associativity | 8-way | 16-way |
| L2 | Bandwidth | 32B/clk | 64B/clk |
| L3 | Size | 32 MB | 32 MB |
| L3 | Associativity | 16-way | 16-way |
| L3 | Bandwidth | 32B/clk Read 16B/clk Write | 32B/clk Read 16B/clk Write |

### Other changes

Other features and changes in the Zen 5 architecture, compared to Zen 4, include:
* Memory speeds up to DDR5-5600 (From DDR5-5200) and LPDDR5X-7500 are officially supported.
Zen 4 vs Zen 5 capabilities :
| Attribute | Zen 4 | Zen 5 |
| L1/L2 BTB | 1.5K/7K | 16K/8K |
| Return Address Stack | 32 | 52 |
| ITLB L1/L2 | 64/512 | 64/2048 |
| Fetched/Decoded Instruction Bytes/cycle | 32 | 64 |
| Op Cache associativity | 12-way | 16-way |
| Op Cache bandwidth | 9 macro-ops | 12 inst or fused inst |
| Dispatch bandwidth (macro-ops/cycle) | 6 | 8 |
| AGU Scheduler | 3x24 ALU/AGU | 56 |
| ALU Scheduler | 1x24 ALU | 88 |
| ALU/AGU | 4/3 | 6/4 |
| Int PRF (red/flag) | 224/126 | 240/192 |
| Vector Reg | 192 | 384 |
| FP Pre-Sched Queue | 64 | 96 |
| FP Scheduler | 2x32 | 3x38 |
| FP Pipes | 3 | 4 |
| Vector Width | 256 | 256b/512b |
| ROB/Retire Queue | 320 | 448 |
| LS Mem Pipes support Load/Store | 3/1 | 4/2 |
| DTLB L1/L2 | 72/3072 | 96/4096 |

## Products
### Desktop
#### Granite Ridge

AMD announced an initial lineup of four models of Ryzen 9000 processors on June 3, 2024, including one Ryzen 5, one Ryzen 7 and two Ryzen 9 models. Manufactured on a 4 nm process, the processors feature between 6 and 16 cores. Ryzen 9000 processors were released in August 2024.
Common features of Ryzen 9000 desktop CPUs:
* Socket: AM5.
* All the CPUs support DDR5-5600 in dual-channel mode.
* All the CPUs support 28 PCIe 5.0 lanes. 4 of the lanes are reserved as link to the chipset.
* Includes integrated RDNA2 GPU with 2 CUs and base and boost clock speeds of 0.4 GHz and 2.2 GHz, respectively.
* L1 cache: 80 KB (48 KB data + 32 KB instruction) per core.
* L2 cache: 1 MB per core.
* Fabrication process: TSMC N4 FinFET (N6 FinFET for the I/O die).
| Branding and Model | Branding and Model | Cores (threads) | Clock rate (GHz) | Clock rate (GHz) | L3 cache (total) | Thermal solution | TDP | Chiplets | Core config | Release date | Launch price |
| Branding and Model | Branding and Model | Cores (threads) | Base | Boost | L3 cache (total) | Thermal solution | TDP | Chiplets | Core config | Release date | Launch price |
| Ryzen 9 | 9950X3D | 16 (32) | 4.3 | 5.7 | 128 MB | — | 170 W | 2 × CCD 1 × I/OD | 2 × 8 | March 12, 2025 | US $699 |
| Ryzen 9 | 9950X | 16 (32) | 4.3 | 5.7 | 64 MB | — | 170 W | 2 × CCD 1 × I/OD | 2 × 8 | August 15, 2024 | US $649 |
| Ryzen 9 | 9900X3D | 12 (24) | 4.4 | 5.5 | 128 MB | — | 120 W | 2 × CCD 1 × I/OD | 2 × 6 | March 12, 2025 | US $599 |
| Ryzen 9 | 9900X | 12 (24) | 4.4 | 5.6 | 64 MB | — | 120 W | 2 × CCD 1 × I/OD | 2 × 6 | August 15, 2024 | US $499 |
| Ryzen 7 | 9800X3D | 8 (16) | 4.7 | 5.2 | 96 MB | — | 120 W | 1 × CCD 1 × I/OD | 1 × 8 | November 7, 2024 | US $479 |
| Ryzen 7 | 9700X | 8 (16) | 3.8 | 5.5 | 32 MB | — | 65 W | 1 × CCD 1 × I/OD | 1 × 8 | August 8, 2024 | US $359 |
| Ryzen 5 | 9600X | 6 (12) | 3.9 | 5.4 | 32 MB | — | 65 W | 1 × CCD 1 × I/OD | 1 × 6 | August 8, 2024 | US $279 |
| Ryzen 5 | 9600 | 6 (12) | 3.8 | 5.2 | 32 MB | Wraith Stealth | 65 W | 1 × CCD 1 × I/OD | 1 × 6 | TBA | TBA |
* v
* t
* e
* ↑ Manufacturer suggested retail price at launch
* ↑ TDP configurable to 105 W
* ↑ Core Complexes (CCX) × cores per CCX
* 1 2 Only one of the two CCXes has 3D V-Cache.

### Mobile
#### Strix Point

The Ryzen AI 300 series of high-performance ultrathin notebook processors were announced on June 3, 2024. Codenamed Strix Point, these processors are named under a new model numbering system similar to Intel's Core and Core Ultra model numbering. Strix Point features a 3rd gen Ryzen AI engine based on XDNA 2, providing up to 50 TOPS of neural processing unit performance. The integrated graphics is upgraded to RDNA 3.5, and top end models have 16 CUs of GPU and 12 cores of CPU, an increase from the maximum of 8 CPU cores on previous generation Ryzen ultrathin mobile processors. Notebooks featuring Ryzen AI 300 series processors were released on July 17.
Common features of Ryzen AI 300 notebook APUs:
* Socket: BGA, FP8 package type.
* All models support DDR5-5600 or LPDDR5X-7500 in dual-channel mode.
* All models support 16 PCIe 4.0 lanes.
* Native USB 4 (40Gbps) Ports: 2
* Native USB 3.2 Gen 2 (10Gbps) Ports: 2
* iGPU uses the RDNA 3.5 microarchitecture.
* NPU uses the XDNA 2 AI Engine (Ryzen AI).
* Both Zen5 and Zen5c cores support AVX-512 using a half-width 256-bit FPU.
* L1 cache: 80 KB (48 KB data + 32 KB instruction) per core.
* L2 cache: 1 MB per core.
* Fabrication process: TSMC N4P FinFET.
| Branding and model | Branding and model | CPU | CPU | CPU | CPU | CPU | CPU | GPU | GPU | NPU (Ryzen AI) | TDP | Release date |
| Branding and model | Branding and model | Cores (threads) | Cores (threads) | Cores (threads) | Clock (GHz) | Clock (GHz) | L3 cache (total) | Model | Clock (GHz) | NPU (Ryzen AI) | TDP | Release date |
| Branding and model | Branding and model | Total | Zen 5 | Zen 5c | Base | Boost | L3 cache (total) | Model | Clock (GHz) | NPU (Ryzen AI) | TDP | Release date |
| Ryzen AI 9 | (PRO) HX 375 | 12 (24) | 4 (8) | 8 (16) | 2.0 | 5.1 | 24 MB | 890M 16 CUs | 2.9 | 55 TOPS | 15–54 W | June 2, 2024 |
| Ryzen AI 9 | (PRO) HX 370 | 12 (24) | 4 (8) | 8 (16) | 2.0 | 5.1 | 24 MB | 890M 16 CUs | 2.9 | 50 TOPS | 15–54 W | June 2, 2024 |
| Ryzen AI 9 | 365 | 10 (20) | 4 (8) | 6 (12) | 2.0 | 5.0 | 24 MB | 880M 12 CUs | 2.9 | 50 TOPS | 15–54 W | June 2, 2024 |
| Ryzen AI 7 | PRO 360 | 8 (16) | 3 (6) | 5 (10) | 2.0 | 5.0 | 16 MB | 880M 12 CUs | 2.9 | 50 TOPS | 15–54 W | October 10, 2024 |
| Ryzen AI 7 | (PRO) 350 | 8 (16) | 4 (8) | 4 (8) | 2.0 | 5.0 | 16 MB | 860M 8 CU | 3.0 | 50 TOPS | 15–54 W | Q1 2025 |
| Ryzen AI 5 | (PRO) 340 | 6 (12) | 3 (6) | 3 (6) | 2.0 | 4.8 | 16 MB | 840M 4 CU | 2.9 | 50 TOPS | 15–54 W | Q1 2025 |
* v
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* ↑ This is the maximum frequency for Zen 5 cores. Zen 5c cores boost to 3.3GHz.

#### Strix Halo

| Branding and Model | Branding and Model | CPU | CPU | CPU | CPU | GPU | GPU | NPU (Ryzen AI) | Chiplets | Core config | TDP | Release date |
| Branding and Model | Branding and Model | Cores (threads) | Clock (GHz) | Clock (GHz) | L3 cache (total) | Model | Clock (GHz) | NPU (Ryzen AI) | Chiplets | Core config | TDP | Release date |
| Branding and Model | Branding and Model | Cores (threads) | Base | Boost | L3 cache (total) | Model | Clock (GHz) | NPU (Ryzen AI) | Chiplets | Core config | TDP | Release date |
| Ryzen AI MAX+ | (PRO) 395 | 16 (32) | 3.0 | 5.1 | 64 MB | 8060S 40 CUs | 2.9 | 50 TOPS | 2 × CCD 1 × I/OD with GPU | 2 × 8 | 45–120 W | Q1 2025 |
| Ryzen AI MAX | (PRO) 390 | 12 (24) | 3.2 | 5.0 | 64 MB | 8050S 32 CUs | 2.8 | 50 TOPS | 2 × CCD 1 × I/OD with GPU | 2 × 6 | 45–120 W | Q1 2025 |
| Ryzen AI MAX | (PRO) 385 | 8 (16) | 3.6 | 5.0 | 32 MB | 8050S 32 CUs | 2.8 | 50 TOPS | 1 × CCD 1 × I/OD with GPU | 1 × 8 | 45–120 W | Q1 2025 |
| Ryzen AI MAX | PRO 380 | 6 (12) | 3.6 | 4.9 | 16 MB | 8040S 16 CUs | 2.8 | 50 TOPS | 1 × CCD 1 × I/OD with GPU | 1 × 6 | 45–120 W | Q1 2025 |

#### Fire Range

| Branding and Model | Branding and Model | Cores (threads) | Clock (GHz) | Clock (GHz) | L3 cache (total) | Chiplets | Core config | TDP | Release date |
| Branding and Model | Branding and Model | Cores (threads) | Base | Boost | L3 cache (total) | Chiplets | Core config | TDP | Release date |
| Ryzen 9 | 9955HX3D | 16 (32) | 2.3 | 5.4 | 128 MB | 2 × CCD 1 × I/OD | 2 × 8 | 54 W | 1H 2025 |
| Ryzen 9 | 9955HX | 16 (32) | 2.5 | 5.4 | 64 MB | 2 × CCD 1 × I/OD | 2 × 8 | 54 W | 1H 2025 |
| Ryzen 9 | 9850HX | 12 (24) | 3.0 | 5.2 | 64 MB | 2 × CCD 1 × I/OD | 2 × 6 | 54 W | 1H 2025 |

### Server
#### Turin

Alongside Granite Ridge desktop and Strix Point mobile processors, the Epyc 9005 series of high-performance server processors, codenamed Turin, were also announced at Computex on June 3, 2024. It uses the same SP5 socket as the previous Epyc 9004 series processors, and will pack up to 128 cores and 256 threads on the top-end model. Turin will be built on a TSMC 4 nm process.
Common features of EPYC 9000 server processors:
* Socket: SP5.
* The CPUs support up to DDR5-6400 in 12 channel mode.
* Fabrication process: TSMC N4X.
| Branding and Model | Branding and Model | Cores (threads) | Clock rate (GHz) | Clock rate (GHz) | L3 cache (total) | TDP | Chiplets | Core config | Release date | Launch price |
| Branding and Model | Branding and Model | Cores (threads) | Base | Boost | L3 cache (total) | TDP | Chiplets | Core config | Release date | Launch price |
| Epyc | 9755 | 128 (256) | 2.7 | 4.1 | 512 MB | 500 W | 16 × CCD 1 × I/OD | 16 × 8 | October 10, 2024 | US $12,984 |
| Epyc | 9655P | 96 (192) | 2.6 | 4.5 | 384 MB | 400 W | 12 × CCD 1 × I/OD | 12 × 8 | October 10, 2024 | US $10,811 |
| Epyc | 9655 | 96 (192) | 2.6 | 4.5 | 384 MB | 400 W | 12 × CCD 1 × I/OD | 12 × 8 | October 10, 2024 | US $11,852 |
| Epyc | 9565 | 72 (144) | 3.15 | 4.3 | 384 MB | 400 W | 12 × CCD 1 × I/OD | 12 × 6 | October 10, 2024 | US $10,486 |
| Epyc | 9575F | 64 (128) | 3.3 | 5.0 | 256 MB | 400 W | 8 × CCD 1 × I/OD | 8 × 8 | October 10, 2024 | US $11,791 |
| Epyc | 9555P | 64 (128) | 3.2 | 4.4 | 256 MB | 360 W | 8 × CCD 1 × I/OD | 8 × 8 | October 10, 2024 | US $7,983 |
| Epyc | 9555 | 64 (128) | 3.2 | 4.4 | 256 MB | 360 W | 8 × CCD 1 × I/OD | 8 × 8 | October 10, 2024 | US $9,826 |
| Epyc | 9535 | 64 (128) | 2.4 | 4.3 | 256 MB | 300 W | 8 × CCD 1 × I/OD | 8 × 8 | October 10, 2024 | US $8,992 |
| Epyc | 9475F | 48 (96) | 3.65 | 4.8 | 256 MB | 400 W | 8 × CCD 1 × I/OD | 8 × 6 | October 10, 2024 | US $7,592 |
| Epyc | 9455P | 48 (96) | 3.15 | 4.4 | 192 MB | 300 W | 6 × CCD 1 × I/OD | 6 × 8 | October 10, 2024 | US $4,819 |
| Epyc | 9455 | 48 (96) | 3.15 | 4.4 | 192 MB | 300 W | 6 × CCD 1 × I/OD | 6 × 8 | October 10, 2024 | US $5,412 |
| Epyc | 9365 | 36 (72) | 3.4 | 4.3 | 192 MB | 300 W | 6 × CCD 1 × I/OD | 6 × 6 | October 10, 2024 | US $4,341 |
| Epyc | 9375F | 32 (64) | 3.8 | 4.8 | 256 MB | 320 W | 8 × CCD 1 × I/OD | 8 × 4 | October 10, 2024 | US $5,306 |
| Epyc | 9355P | 32 (64) | 3.55 | 4.4 | 256 MB | 280 W | 8 × CCD 1 × I/OD | 8 × 4 | October 10, 2024 | US $2,998 |
| Epyc | 9355 | 32 (64) | 3.55 | 4.4 | 256 MB | 280 W | 8 × CCD 1 × I/OD | 8 × 4 | October 10, 2024 | US $3,694 |
| Epyc | 9335 | 32 (64) | 3.0 | 4.4 | 128 MB | 210 W | 4 × CCD 1 × I/OD | 4 × 8 | October 10, 2024 | US $3,178 |
| Epyc | 9275F | 24 (48) | 4.1 | 4.8 | 256 MB | 320 W | 8 × CCD 1 × I/OD | 8 × 3 | October 10, 2024 | US $3,439 |
| Epyc | 9255 | 24 (48) | 3.25 | 4.3 | 128 MB | 200 W | 4 × CCD 1 × I/OD | 4 × 6 | October 10, 2024 | US $2,495 |
| Epyc | 9175F | 16 (32) | 4.2 | 5.0 | 512 MB | 320 W | 16 × CCD 1 × I/OD | 16 × 1 | October 10, 2024 | US $4,256 |
| Epyc | 9135 | 16 (32) | 3.65 | 4.3 | 64 MB | 200 W | 2 × CCD 1 × I/OD | 2 × 8 | October 10, 2024 | US $1,214 |
| Epyc | 9115 | 16 (32) | 2.6 | 4.1 | 64 MB | 125 W | 2 × CCD 1 × I/OD | 2 × 8 | October 10, 2024 | US $726 |
| Epyc | 9015 | 8 (16) | 3.6 | 4.1 | 64 MB | 125 W | 2 × CCD 1 × I/OD | 2 × 4 | October 10, 2024 | US $527 |
* v
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* e
* ↑ Manufacturer suggested retail price at launch
* ↑ Core Complexes (CCX) × cores per CCX

#### Turin Dense

A variant of Epyc 9005 using Zen 5c ("Prometheus") cores was also shown off at Computex. It will feature a maximum of 192 cores and 384 threads, and be manufactured on a 3 nm process.
Common features of EPYC Dense 9000 server processers:
* Socket: SP5.
* All the CPUs support DDR5-6400 in 12 channel mode.
* Fabrication process: TSMC N3E.
| Branding and Model | Branding and Model | Cores (threads) | Clock rate (GHz) | Clock rate (GHz) | L3 cache (total) | TDP | Chiplets | Core config | Release date | Launch price |
| Branding and Model | Branding and Model | Cores (threads) | Base | Boost | L3 cache (total) | TDP | Chiplets | Core config | Release date | Launch price |
| Epyc | 9965 | 192 (384) | 2.25 | 3.7 | 384 MB | 500 W | 12 × CCD 1 × I/OD | 12 × 16 | October 10, 2024 | US $14,813 |
| Epyc | 9845 | 160 (360) | 2.1 | 3.7 | 320 MB | 390 W | 10 × CCD 1 × I/OD | 10 × 16 | October 10, 2024 | US $13,564 |
| Epyc | 9825 | 144 (288) | 2.2 | 3.7 | 384 MB | 390 W | 12 × CCD 1 × I/OD | 12 × 12 | October 10, 2024 | US $13,006 |
| Epyc | 9745 | 128 (256) | 2.4 | 3.7 | 256 MB | 400 W | 8 × CCD 1 × I/OD | 8 × 16 | October 10, 2024 | US $12,141 |
| Epyc | 9645 | 96 (192) | 2.3 | 3.7 | 256 MB | 320 W | 8 × CCD 1 × I/OD | 8 × 12 | October 10, 2024 | US $11,048 |
* v
* t
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* ↑ Manufacturer suggested retail price at launch
* ↑ Core Complexes (CCX) × cores per CCX

## Zen 5c

Zen 5c ("Prometheus") is a compact variant of the Zen 5 ("Nirvana") core, primarily targeted at hyperscale cloud compute server customers. It will succeed the Zen 4c ("Dionysus") and Zen 4 ("Persephone") core.