# Zilog Z8000

The Zilog Z8000 is a 16-bit microprocessor architecture designed by Zilog and introduced in early 1979. Two chips were initially released, differing only in the width of the address bus; the Z8001 had a 23-bit bus while the Z8002 had a 16-bit bus.
Bernard Peuto designed the architecture, while Masatoshi Shima did the logic and physical implementation, assisted by a small group. In contrast to most designs of the era, the Z8000 does not use microcode, which allowed it to be implemented in only 17,500 transistors. The Z8000 is not Z80-compatible, but includes a number of design elements from it, such as combining two registers into one with twice the number of bits. The Z8000 expanded on the Z80 by allowing two 16-bit registers to operate as a 32-bit register, or four to operate as a 64-bit register.
Although it saw some use in the early 1980s, it was never as popular as the Z80. It was released after the 16-bit 8086 (April 1978) and the same time as the less-expensive 8088, and only months before the 68000 (September 1979) with a 32-bit instruction set architecture and which is roughly twice as fast. The Z80000 was a 32-bit follow-on design that made it to a test sampling phase in 1986 without ever being released commercially.

## History
### Z80

In the early 1970s, Intel's management saw the microprocessor not so much as a product on its own, but as a way to create demand for their other products like static RAM and ROM. A reorganization in early 1974 further diluted the role of the microprocessor in the company. The designer of the Intel 4004 and Intel 8080, Federico Faggin, decided to leave the company and start one dedicated to microprocessor design. Faggin left on 31 October 1974, joined by Ralph Ungermann and, later, the logic designer Masatoshi Shima.
Initially working on a concept for a simple microcontroller, Faggin eventually concluded that the economics of the industry demanded that they introduce a product at the high-end, not the low-end. This led to a new concept initially known as the "Super 80", but eventually emerging as the Zilog Z80. The Z80 was a significant advance on the 8080, running on a single +5V power supply and adding several nice features from the Motorola 6800. Released in 1976, it was soon a huge hit.

### 16-bit design

While Shima was still working on the Z80 layout, Faggin began considering its future replacement by a 16-bit design, with the goal of being the first company to bring a new 16-bit single-chip design to market. He felt that expanding the Z80 to 16-bits was not appropriate, the larger computer word size meant that many more features could be offered in the instruction set and the deliberately simple instructions of earlier designs would lead to chips that would be outperformed by freshly-designed 16-bit designs.
In January 1976, Faggin hired Bernard Peuto, formerly of Amdahl Corporation. Peuto had previously studied and published extensively on the topic of word length, instruction sets and code density. The initial meetings on the concept were held at the end of March, at which time Faggin told Peuto he wanted the architecture completed in three months. The instruction set was delivered on time, but then it was time to turn that into a complete design. Peuto's design included the ability to work with 8-, 16- and 32-bit data, flexible addressing modes, and dedicated coprocessor support.
It was during this time that Ungermann explained the economics of the chip industry to Peuto, which were strongly influenced by the size of the chip. At the time, most processors used 40-pin dual in-line packages (DIPs), but some used 28-pin packages for lower-cost systems, while others were using 48 or 64-pin packages for more powerful systems like minicomputers. The need to balance cost and power ultimately led to the idea of having two versions of the chip, the Z8001 with 23 address bus pins in a 48-pin chip, and the Z8002 with 16 address pins in a 40-pin chip.
In order to have a single instruction set that could be used on either design, they made the decision to use segmented memory. In this concept, the basic instruction set uses 16-bit addresses, which could then be run on either version of the chip. To access larger amounts of memory, a separate set of instructions could set a 7-bit "segment number". On the 23-pin versions, the 7-bit segment number was sent out at the same time as the 16-bit base address, creating a single 23-bit address. This early design choice would ultimately have a profound effect on the desirability of the Z8000 series.
Shima would be responsible for turning the conceptual design into a physical one, and with the basic design completed, Shima first began considering it on 11 June 1976. At the time the system was to have eight 16-bit registers, and Shima began laying out such a design. But very late in the process the design team concluded that it needed more, and when they asked in October, Shima stated he had laid it out with enough room left over that they could double the number of registers.

### Introduction

In June 1978, while Shima was still working on the design of the Z8000, Intel introduced the Intel 8086. Zilog had missed its chance to be the first company with a new, dedicated 16-bit design. In some ways the 8086 was similar to the Z8000, including the use of segmented memory, but in general it was a less advanced design with fewer processor registers and a much smaller maximum memory of 1 megabyte rather than the 8000's 8 MB.
It was not until early 1979 that production samples of the Z8000 were released. Zilog stated that the Z8001 and Z8002 were merely differently packaged versions of the same Z8000 chip, "the difference being achieved by a bonding option during manufacture".
Even with 48 pins, there were not enough connections to allow for a complete 16-bit data bus and 24-bit address bus, as that would leave only 8 free pins, which is not nearly enough for various other interfacing needs like power, clocks and interrupts. To address this, the Z8001 multiplexed the address and data pins together. The first 16 pins of the 23-pin address bus were used on alternate cycles as a 16-bit data bus. This meant that every memory access took two complete memory cycles: first the address would be presented and had to be "latched" using external circuity, and then on the next cycle 16 bit of data would be read or written using the same pins. This means the Z8000 would run roughly half as fast as something like the 68000, which had separate 16 data pins and 24 address pins on a larger 64-pin chip.
Zilog already had a strategy to deal with this problem, the Zilog 8010 memory controller. The 8010 automatically folded the 7 and 16-bit parts of the address back together into a single 23-bit address, as well as offering a number of memory mapping features that made it useful for supporting multitasking and virtual memory. However, the 8010 was not ready when the 8001 was introduced. This meant that for 18 months, Intel had a single-chip solution that could access 1 MB, while the 8000 series was still practically limited to 64 kB. The 8010 was eventually released almost a year later, and even then it required two chips to do what the 8086 did with one.
The delays with the 8010 was particularly hurtful. In September 1979, Motorola introduced the Motorola 68000, which had a complete 24-bit address bus, which allowed it to access up to 16 MB without segmentation. It also offered all of the features Zilog advertised as being more advanced than the 8086, such as more registers and a wide set of addressing modes. The market generally chose Intel for lower-end offerings and the 68000 for the high-end. Shima left the company to return to Japan in 1980, and Faggen left shortly thereafter.

### Later versions

The series was later expanded to include the Z8003 and Z8004 updated versions of the Z8001 and Z8002, respectively. These versions were designed to provide improved support for virtual memory, adding new status registers to indicate segmentation faults (test and set) and provide an abort capability.

## Architecture
### Registers

There are sixteen 16-bit registers, labeled R0 through R15. The registers can be concatenated into eight 32-bit registers, labeled RR0/RR2/../RR14, or into four 64-bit registers, labeled RQ0/RQ4/RQ8/RQ12. The first eight registers can be also subdivided into sixteen 8-bit registers, labeled RL0 though RL7 for the lower byte and RH0 through RH7 for the upper (high) byte. Register R15 is designated as stack pointer. On the Z8001, register R14 is used to include a fixed segment in the stack pointer, and the program counter is expanded to 32 bits to include a similar segment.
There is both a user mode ("normal") and a supervisor mode, selected by bit 14 in the flag register. In supervisor mode, the stack registers point to the system stack and all privileged instructions are available. In user mode, the stack registers point to the normal stack and all privileged instructions will generate a fault. Having separate modes and stacks greatly adds to the performance of context switches between user programs and an operating system.$^{:6.1}$

### Memory handling

Like the Z80, the Z8000 includes a system to automatically refresh dynamic RAM. In most systems this is normally handled by the video display controller or external logic. This was implemented via a separate Refresh Counter (RC) register that held the currently updating page of memory. The feature is turned on by setting the most significant bit of the RC, bit 15, to 1. The following six bits, 14 through 9 are a rate, measured in terms of every 4th clock cycle. With a standard 4 MHz clock, that allows the refresh to be called every 1 to 64 microseconds. The remaining 8 bits select a row in memory to refresh.$^{:6.5,6.28}$
The Z8000 has a segmented memory map, with a 7-bit "segment number" and a 16-bit offset. Both numbers are represented by pins on the Z8001, meaning that it can directly address a 23-bit memory, or 8 MB.$^{:6.19}$ Instructions can only directly access a 16-bit offset. This allows the instruction format to be smaller; a system with direct access to a 23-bit address would need to read three bytes (24 bits) from memory for every address referred to in the code, thus requiring two reads on a 16-bit bus. With segments, the addresses need only a single 16-bit read which is then added to a segment number to produce the complete address. The segment number only needs to be updated when the data crosses the 16-bit/64 KB boundaries.$^{:6.3}$
Internally, addresses are all 32 bits: an upper 16-bit word with a leading 0 in bit 15, the 7-bit segment number, and then 8 zeros. This requires more memory to store, as each 23-bit address uses up 32 bits of register space, but allows the addresses to be cleanly stored in the 16-bit registers and can be more easily pushed and popped from the stack, which occurs in 16-bit words.$^{:6.6}$
The optional 48-pin Z8010 memory management unit (MMU) expands the memory map to 16 MB by translating the 23-bit address from the CPU to a 24-bit one. A Z8010 has 64 segment descriptor registers, each of which contains a 16-bit base physical address, an 8-bit limit, and an 8-bit set of attributes. When the CPU attempts to access a particular segment, a 7-bit value, the Z8010 uses the lower 6 bits of the segment number to select a segment descriptor register, checks the 16-bit offset in the segment against the limit value in that register and checks the permission bits in the attributes to see whether the access is allowed and, if the access is allowed, adds the base physical address to the segment offset to generate a physical address. This allows multiple programs to be spread out in physical RAM, each given its own space to work in while believing it is accessing the entire 8 MB of RAM. The segments are variable length, expanding up to 64 KB in order to allow the entire memory to be accessed from 64 segments. If more than 64 segments are needed, multiple Z8010s can be used, with the upper bit of the 7-bit segment number selecting which Z8010 is used. The Z8010 was not available at the time of launch, and was ultimately nine months to a year late.
With the release of the Z8003/Z8004, the Z8015 was added to the lineup, adding paged memory support. The main difference is that the Z8015 breaks down the memory into 64 2 KB blocks, whereas the Z8010 broke memory into 64 variable-sized blocks, up to 64 KB each. Additionally, the Z8015 expands the segment number from 7 to 12 bits, and then using those as the most significant bits of the 23-bit overall address, overriding the upper bits of the original 16-bit offset. The advantage to this access scheme is that it is easy to read or write 2 KB blocks to a hard drive, so this pattern more closely matches what will ultimately happen on a page fault.

### Example code

The following Z8000 assembly source code is for a subroutine named MEMCPY that copies a block of data words from one location to another. The data block is copied one word at a time, and the data movement and looping logic utilizes 16-bit operations. It demonstrates a variety of instructions but in practice it would not be coded this way as the Z8000 has a single instruction that will replace this entire subroutine: LDIR. The sample code will move one word every 34 cycles. Substituting the LDIR instruction will move a word in only 9 cycles.
| 1000 1000 93F4 1002 2114 1004 2F24 1006 A911 1008 A921 100A F285 100C 97F4 100E 9E08 1010 | ; memcpy -- ; Copy a block of memory from one location to another. ; This routine is the equivalent of ; LDIR @R2,@R1,R0 (LDIR @dst,@src,cnt) ; ; Entry registers ; R1 - Address of source data block ; R2 - Address of destination data block ; R0 - Number of words to copy ; ; Return registers ; R1 - First word after source data block ; R2 - First word after destination data block ; R0 - Zero ORG 1000h ;Origin at 1000h MEMCPY: PUSH @R15,R4 ;Save temp register like LDIR LOOP: LD R4,@R1 ;Load source word LD @R2,R4 ;save it INC R1,#2 ;Bump source by 2 for words INC R2,#2 ;Bump dest pointer DJNZ R0,LOOP ;Bump counter POP R4,@R15 ;Restore scratch register RET END |

### Other features

One uncommon feature found on the Z8000, more commonly associated with minicomputers, is direct support for vectored interrupts. Interrupts are used by external devices to notify the processor that some condition has been met; a common use is to indicate that data from a slow process like reading a floppy disk is now available and the CPU can read the data into memory.
Normally on small machines, an interrupt causes special code to run that examines various status bits and memory locations to decide what device actually called the interrupt and why. In some designs, especially those intended for realtime computing, an area of memory is set aside as a set of pointers, or vectors, to the code handling a particular device. The devices causing the interrupt then set some state, typically via pins on the CPU, to indicate a particular interrupt number, N. When the interrupt is called, the CPU immediately jumps through Nth entry in the table, avoiding any need to decode the interrupt. This can greatly speed up the interrupt servicing by avoiding having to run additional operations, while also simplifying the interrupt handling code.
In the Z8000, a new register supports vectors, the Program Status Area Pointer. This was similar to a memory address in a register, consisting of two 16-bit values with the upper 16 bits holding the segment number in its upper 8 bits. The lower 16 bits are then divided in half, the upper 8 bits containing an offset and the lower 8 bits zeroed. To call a particular vector, the external device presents the lower 8 bits (or 9 in some cases) on the address/data bus, and the complete vector address is constructed from the three values.$^{:6.8}$

## Support chips
### Zilog

* Z8010: Memory management Unit
* Z8016: Direct Memory Access Transfer Controller
* Z8030: Serial Communications Controller
* Z8036: Counter/Timer and Parallel I/O Unit
* Z8090: Universal Peripheral Controller
* Z8531: Clock Generator and Controller

### Sharp

* LH8010/LH8010A: Z8010/Z8010A compatible Memory Management Unit
* LH8036/LH8036A: Z8036/Z8036A compatible Counter/Timer and Parallel I/O Unit
* LH8072: serial parallel combination controller with internal 128-byte FIFO
* LH8073: GPIB controller
* LH8090: Z8090 compatible Universal Peripheral Controller.

## Z8000 CPU based systems

In the early 1980s, the Zilog Z8000 CPU was popular for desktop-sized Unix machines. These low-cost Unix systems allowed small businesses to run a true multi-user system and share resources (disk, printers) before networking was common. They usually had only RS-232 serial ports (4–16) and parallel printer ports instead of built-in graphics, as was typical for servers of the time.
Z8000-based computer systems included Zilog's own System 8000 series, as well as other manufacturers:
* 1980: C8002 made by Onyx Systems used the Z8002, ran Version 7 Unix, had C, FORTRAN 77 and COBOL compilers available. It had eight serial ports for terminal connections, 1 QIC tape drive and cost ~$25k. The main processor offloaded the disk, tape, and serial I/O operations to a Z80 processor on a second board.
* 1981: Zilog Systems Z-Lab 8000 Programmer's Development System, available as a Model 20 system with 256 KB of RAM and single 24 MB hard drive, priced at $27,000, or a Model 30 system with 512 KB of RAM and dual hard drives, priced at $33,950, ran the Zeus enhanced version of Unix from Zilog. Zilog followed up with the Series 8000, a multi-user business system that, like the Z-Lab 8000, was based on the 6 MHz Z8001A with three Z8010A memory management units.
* 1981-1982: Plexus Industries' P/40 employed an Z8000-based processor, specifically the Z8001, along with a number of peripheral controllers designed to maximise data transfer performance, claiming direct memory access throughput of up to 3 MB per second. A "typical eight-user P/40 configuration" with 512 KB of RAM and 72 MB hard drive cost $49,500, with a Unix licence costing $5,000 extra. Plexus followed up with the P/25 in 1982, claiming similar performance to a PDP-11/70 system. A later Plexus model, the P/60, employed the Z8000 as an input/output controller but introduced the Motorola 68000 as the main CPU. The Plexus P/35 retained this general architecture.
* 1982: BDC-600 from Bleasdale Computer Systems was offered in a configuration featuring the Z8000 running Xenix, providing 256 KB of RAM, a floppy drive system and 10 MB hard drive, supporting eight input/output ports. Based on the Multibus standard, other processor configurations were also announced involving boards utilising the 68000, Z80, 6809 and 8086. Bleasdale later focused on the 68000 architecture with its BDC-680 series.$^{:8}$
* 1982: Olivetti M20, a non-IBM-compatible PC that ran Olivetti PCOS, a derivative of COSMOS or CP/M 8000.
* 1982-1983: C5002A, C8002A and Sundance-16 from Onyx Systems used the Z8001 and ran Unix System III.
* 1983: Zilog Systems 8000 Series Two featured a faster 11.1 MHz Z8001B processor with 32 KB of cache memory, available in three models with 512 KB of RAM expandable to 2 MB in the base model and 4 MB in the other models, with prices for minimal configurations ranging from $19,950 to $29,950. These systems ran Unix System III.
* 1983: Exxon Office Systems 500 series and 8400 series.
* 1980-1986: Olivetti Linea 1 S1000, S6000, M30, M40, M50, M60, M70. These minicomputers from Olivetti all ran BCOS/COSMOS.
* 1985: the cancelled Commodore 900 computer project
* 1987–1989: the East German EAW (Elektro-Apparate-Werke) produced the Workstation/Multiuser System P8000 based on the East German U8000 clone of the Z8000.
The Zilog S8000 computer came out with a version of Unix called ZEUS (Zilog Enhanced Unix System). ZEUS was a port of Unix Version 7 and included what were referred to as 'the Berkeley Enhancements'. ZEUS included a version of COBOL called RM/COBOL (Ryan McFarland COBOL). The availability of RM/COBOL allowed many commercial applications to be quickly ported to the S8000 computer although this did not help its long-term success. The S8000 did find some success with the IRS and tax preparers in United States, who used the model for processing of electronically filed tax returns.
The Z8000 featured in Steve Ciarcia's Trump Card project for his Circuit Cellar column in Byte magazine, providing an expansion card with the Z8001 processor and 512 KB of RAM suitable for use with an IBM-compatible PC. Compilers for BASIC and C were supplied with the board, along with an assembler and a Z80 emulator that could run programs written for CP/M-80. It was envisaged that Unix would also be made available for the Trump Card.
Despite a somewhat positive reception as "a reasonably fast supermicro with generally good performance for the price", the 16-bit architectural limitations of the Z8000, with segment handling required to access more than 64 KB in a process, led to questions about the longevity of the Series 8000 products as 32-bit processor architectures from Motorola and National Semiconductor became more widely adopted. Zilog Systems eventually adopted AT&T's 32-bit WE32100 processor, introducing it in a new product, the System 8000/32, alongside 32-bit upgrades to its existing System 8000 Series 2 models. This enabled the introduction of Unix System V on Zilog Systems' products.
The adoption by Zilog's Systems Division of the WE32100, in preference to the continued use of products from Zilog's Component Division, was driven by diverging requirements. Zilog sought to introduce its 32-bit successor to the Z8000, the Z80000, to build on successful adoption of the 16-bit product in military and graphical applications, whereas its Systems Division prioritised Unix support and commercial applications. The conclusion was reached to adopt the WE32100 as "the premier UNIX chip". Zilog subsequently announced an agreement to manufacture the WE32100 chipset for a five year period, being the first alternative source of these products.
There was a Z8000 version of the Xenix Operating System. In 1982, Digital Research and Zilog announced an agreement to make CP/M available for the Z8000.
Namco used the Z8000 series in its Pole Position and Pole Position II arcade games. The machines used two Z8002's, the 64 KB versions of the Z8000.
In one instance, the Z8001 was used to implement a capability-based architecture, employing the segment number in the addressing model of the Z8001 to indicate a capability register in a virtual processor. Such virtual processors were provided through the augmentation of the Z8001 with an "intelligent memory device", this providing memory management and context switching facilities, with additional capability-related instructions being supported through emulation.
The reported inclusion of the device within military designs perhaps provides an explanation for the continued survival of the Z8000, in the shape of the Zilog Z16C01/02 CPUs. Also, the Standard Central Air Data Computer (SCADC) was using the Z8002. However, the end of life notice from Zilog was sent in 2012.

## Limited success

While the Z8000 did see some use in the early 1980s, it was passed over for other designs relatively quickly.
Federico Faggin, then CEO of Zilog, later suggested this was due to Zilog's financing arrangement with Exxon's venture capital arm, Exxon Enterprises. Enterprises had made a number of investments in the computer field, and by the early 1980s was positioning itself as a competitor to IBM in the large system space. Faggin suggested that IBM thus saw Zilog as a competitor, and refused to consider the Z8000 as a result.
However, Faggin did concede that the segmented architecture of the Z8000 was a disadvantage for emerging "graphics-based applications", where systems such as the Apple Macintosh needed to readily access more than 64 KB of memory in a single address space. The longer than anticipated process of bringing the product to market was also acknowledged as having contributed to its lack of adoption, Faggin noting that "being first and having the strongest marketing and the strongest momentum", as Intel had found itself with the 8086, would have been the only remaining route to success for a product of this kind.
An examination of the choices available to designers in the early 1980s suggests there are several prosaic reasons the Z8000 was not more popular:
Comparing assembly language versions of the Byte Sieve, one sees that the 5.5 MHz Z8000's 1.1 seconds is impressive when compared to the 8-bit designs it replaced, including Zilog's 4 MHz Z80 at 6.8 seconds, and the popular 1 MHz MOS 6502 at 13.9. Even the newer 1 MHz Motorola 6809 was much slower, at 5.1 seconds. It also fares well against the 8 MHz Intel 8086 which turned in a time of 1.9 seconds, or the less expensive 5 MHz Intel 8088 at 4 seconds.
While the Intel processors were easily outperformed by the Z8001, they were packaged in 40-pin DIPs, which made them less expensive to implement than the 48-pin Z8001. The Z8002 also used a 40-pin package, but had a 16-bit address bus that could only access 64 KB of RAM, whereas the Intel processors had a 20-bit bus that could access 1 MB of RAM. Internally, the 23-bit addresses of the Z8000 were also more complex to process than Intel's simpler system using 16-bit base addresses and separate segment registers. For those looking for a low-cost option able to access (what was then) large amounts of memory, the Intel designs were competitive and available over a year earlier.
For those looking for pure performance, the Z8000 was the fastest CPU available in early 1979. But this was true only for a period of a few months. The 16/32-bit 8 MHz Motorola 68000 came to market later the same year and turns in a time of 0.49 seconds on the same Sieve test, over twice as fast as the Z8000. Although it used an even larger 64-pin DIP layout, for those willing to move to more than 40 pins this was a small price to pay for what was by far the fastest processor of its era. Its 32-bit instructions and registers, combined with a 24-bit address bus with flat 16 MB addressing, also made it much more attractive to designers, something Faggin admits to.
To add to its problems, when the Z8000 was first released it contained a number of bugs. This was due to its complex instruction decoder, which, unlike most processors of the era, did not use microcode and was dependent on logic implemented directly in the CPU. This allowed the design to eliminate the microcode storage and the associated decoding logic, which reduced the transistor count to 17,500. In contrast, the contemporary Intel 8088 used 29,000 transistors, while the Motorola 68000 of a few months later used 68,000.

## Second sources

Several third parties manufactured the Z8000 including AMD, SGS-Ates, Toshiba and Sharp.
* Zilog Z8000 second sources
* AMD Z8002APC
* VEB Mikroelektronik "Karl Marx" Erfurt (MME) UB8001C
* Sharp LH8002P