# Nvidia Drive

NVIDIA DRIVE is a computer platform by Nvidia, aimed at providing autonomous car and driver assistance functionality powered by deep learning. The platform was introduced at the Consumer Electronics Show (CES) in Las Vegas in January 2015. An enhanced version, the Drive PX 2 was introduced at CES a year later, in January 2016.
The closely platform related software release program at some point in time was branded NVIDIA DRIVE Hyperion along with a revision number helping to match with the generation of hardware it is created for - and also creating ready to order bundles under those term. In former times there were only the terms Nvidia Drive SDK for the developer package and sub-included Nvidia Drive OS for the system software (aka OS) that came with the evaluation platforms or could be downloaded for OS switching and updating later on.

## Hardware and semiconductors
### Maxwell based

The first of Nvidia's autonomous chips was announced at CES 2015, based on the Maxwell GPU microarchitecture. The line-up consisted of two platforms:

#### Drive CX

The Drive CX was based on a single Tegra X1 SoC (System on a Chip) and was marketed as a digital cockpit computer, providing a rich dashboard, navigation and multimedia experience. Early Nvidia press releases reported that the Drive CX board will be capable of carrying either a Tegra K1 or a Tegra X1.

#### Drive PX

The first version of Drive PX is based on two Tegra X1 SoCs, and was an initial development platform targeted at (semi-)autonomous driving cars.

### Pascal based

Drive PX platforms based on the Pascal GPU microarchitecture were first announced at CES 2016. This time only a new version of Drive PX was announced, but in multiple configurations.

#### Drive PX 2

The Nvidia Drive PX 2 is based on one or two Tegra X2 SoCs where each SoC contains 2 Denver cores, 4 ARM A57 cores and a GPU from the Pascal generation. There are two real world board configurations:
* for AutoCruise: 1× Tegra X2 + 1 Pascal GPU
* for AutoChauffeur: 2× Tegra X2 + 2 Pascal GPU's
There is further the proposal from Nvidia for fully autonomous driving by means of combining multiple items of the AutoChauffeur board variant and connecting these boards using e.g. UART, CAN, LIN, FlexRay, USB, 1 Gbit Ethernet or 10 Gbit Ethernet. For any derived custom PCB design the option of linking the Tegra X2 Processors via some PCIe bus bridge is further available, according to board block diagrams that can be found on the web.
All Tesla Motors vehicles manufactured from mid-October 2016 include a Drive PX 2, which will be used for neural net processing to enable Enhanced Autopilot and full self-driving functionality. Other applications are Roborace. Disassembling the Nvidia-based control unit from a recent Tesla car showed that a Tesla was using a modified single-chip Drive PX 2 AutoCruise, with a GP106 GPU added as a MXM Module. The chip markings gave strong hints for the Tegra X2 Parker as the CPU SoC.

### Volta and Turing based

Systems based on the Volta GPU microarchitecture and Turing GPU microarchitecture were first announced at CES 2017. It was originally named Drive PX, but later changed to DRIVE AGX.

#### DRIVE AGX Xavier

The first Volta based Drive PX system was announced at CES 2017 as the Xavier AI Car Supercomputer. It was re-presented at CES 2018 as Drive PX Xavier. Initial reports of the Xavier SoC suggested a single chip with similar processing power to the Drive PX 2 Autochauffeur system. However, in 2017 the performance of the Xavier-based system was later revised upward, to 50% greater than Drive PX 2 Autochauffeur system. Drive PX Xavier is supposed to deliver 30 INT8 TOPS of performance while consuming only 30 watts of power. This spreads across two distinct units, the iGPU with 20 INT8 TOPS as published early and the somewhat later on announced, newly introduced DLA that provided an additional 10 INT8 TOPS.

#### DRIVE AGX Pegasus

In October 2017 Nvidia and partner development companies announced the Drive PX Pegasus system, based upon two Xavier CPU/iGPU devices and two Turing generation dGPUs. The companies stated the third generation Drive PX system would be capable of Level 5 autonomous driving, with a total of 320 INT8 TOPS of AI computational power and a 500 Watts TDP.

### Ampere based
#### DRIVE AGX Orin

The Drive AGX Orin board family was announced on December 18, 2019, at GTC China 2019. On May 14, 2020, Nvidia announced that Orin would be utilizing the new Ampere GPU microarchitecture and would begin sampling for manufacturers in 2021 and be available for production in 2022. Follow up variants are expected to be further equipped with chip models and/or modules from the Tegra Orin SoC.

### Ada Lovelace based
#### DRIVE Atlan (Cancelled)

Nvidia announced the SoC codenamed Atlan on April 12, 2021 at GTC 2021.
Nvidia announced the cancellation of Atlan on September 20, 2022, which was supposed to be equipped with a Grace-Next CPU, and an Ada Lovelace based GPU, and Nvidia announced that their next SoC was called Thor.

### Blackwell based
#### DRIVE AGX Thor

Announced on September 20, 2022, Nvidia DRIVE AGX Thor comes equipped with an Arm Neoverse V3AE CPU, and a Blackwell based GPU, which was announced on March 18, 2024. It features 8-bit floating point support (FP8) and delivers 1000 Sparse INT8 TOPS, 1000 Sparse FP8 TFLOPS or 500 Sparse FP16 TFLOPS of performance. Two Thor SoCs can be connected via NVLink-C2C.
BYD, Hyper, XPENG, Li Auto and ZEEKR have said to be use DRIVE AGX Thor in their vehicles. The Lynk & Co 900 is the first production vehicle to feature the DRIVE AGX Thor SoC.

## Software and bundling

With the label Hyperion added to their reference platform series Nvidia promotes their mass products so that others can easily test drive and then create their own automotive grade products on top. Especially the feature rich software part of the base system is meant to be a big help for these others to quickly go ahead into developing their application specific solutions. Third-party companies, such as DeepRoute.ai, have publicly indicated using these software platform as their base of choice. The whole design is concentrating on UNIX/Posix compatible or derived runtime environments (Linux, Android, QNX - aka the DRIVE OS variants) with special support for the semiconductors mentioned before in form of internal (CUDA, Vulkan) and external support (special interfaces and drivers for camera, lidar, CAN and many more) of the respective reference boards. For clearness Nvidia bundles the core of the developer needed software as Drive SDK that is sub-divided into DRIVE OS, DriveWorks, DRIVE AV, and DRIVE IX components.
| Hyperion Version | Announced | Latest Chip Launch | Start of Road Usage | Target Use Case | Semiconductors | Reference Platforms / Developer Kits | DRIVE OS Version | Sensor Support |
| 7.1 | | 2020 | | Level 2+ autonomous driving | Xavier, Turing GPU | DRIVE AGX Xavier, DRIVE AGX Pegasus | | vehicle external: 7x camera, 8x radar; vehicle internal: 1x camera |
| 8 | | 2020 | | | Xavier, Turing GPU | DRIVE AGX Xavier, DRIVE AGX Pegasus | 5.0.13.2 (linux) | vehicle external: 12x camera, 9x radar, 1x lidar |
| 8.1 | | 2022 | estimated for 2024 | | Orin, Xavier, Turing GPU | DRIVE AGX Orin, DRIVE AGX Pegasus, DRIVE Hyperion 8.1 Developer Kits | Orin: 6.0 (latest: 6.0.4) Xavier/Pegasus:5.2.6 | vehicle external: 12x camera, 9x radar, 1x lidar |
| 9 | March 2022 | 2024 | estimated for 2026 | | Atlan (Cancelled) | | | vehicle external: 14x camera, 9x radar, 3x lidar, 20x ultrasonic; vehicle internal: 3x camera, 1x radar |
Note: As of now the above table is still 'fresh' and thus might be incomplete.

## Developer kit comparison

| Nvidia provided developer kit | Drive CX | Drive PX | Drive PX 2 AutoCruise | Drive PX 2 (Tesla 2.0) | Drive PX 2 AutoChauffeur | Drive PX 2 (Tesla 2.5) | DRIVE AGX Xavier | DRIVE AGX Pegasus | DRIVE AGX Orin | DRIVE AGX Pegasus OA (Cancelled) | DRIVE Atlan (Cancelled) | DRIVE AGX Thor |
| GPU Microarchitecture | Maxwell (28 nm) | Maxwell (28 nm) | Pascal (16 nm) | Pascal (16 nm) | Pascal (16 nm) | Pascal (16 nm) | Volta (12 nm) Turing (12 nm) | Volta (12 nm) Turing (12 nm) | Ampere (8 nm) | Ampere (8 nm) | Ada Lovelace (TSMC 4N) | Blackwell (TSMC 4NP) |
| Announced | January 2015 | January 2015 | September 2016 | October 2016 | January 2016 | August 2017 | January 2017 | October 2017 | December 2019 | December 2019 | April 2021 | September 2022 |
| Launched | ? | ? | ? | ? | ? | ? | October 2018 | ? | 2022 | Cancelled | Cancelled | 2025 |
| Chips | 1x Tegra X1 | 2x Tegra X1 | 1x Tegra X2 (Parker) + 1x Pascal dGPU | 1x Tegra X2 (Parker) + 1x Pascal dGPU | 2x Tegra X2 (Parker) + 2x Pascal dGPU | 2x Tegra X2 (Parker) + 1x Pascal dGPU | 1x Xavier | 2x Xavier + 2x Turing T4 dGPU | 1x Orin | 1x Orin + 1x A100 dGPU | ?x Grace-Next CPU + ?x Ada Lovelace GPU | ?x Arm Neoverse Poseidon AE CPU + ?x Blackwell GPU |
| CPU | 4-core Cortex A57 4-core Cortex A53 | 2x 4-core Cortex A57 2x 4-core Cortex A53 | 2-core Denver 4-core Cortex A57 | 2-core Denver 4-core Cortex A57 | 2x 2-core Denver 2x 4-core Cortex A57 | 2x 2-core Denver 2x 4-core Cortex A57 | 8-core Carmel | 2x 8-core Carmel | 12-core Cortex A78AE | 12-core Cortex A78AE | ?-core Grace-Next | ?-core Arm Neoverse Poseidon AE |
| iGPU | 1x 2 SMM Maxwell iGPU (256 CUDA cores) | 2x 2 SMM Maxwell iGPU (256 CUDA cores) | 1x Parker iGPU (256 CUDA cores) | 1x Parker iGPU (256 CUDA cores) | 2x Parker iGPU (256 CUDA cores) | 2x Parker iGPU (256 CUDA cores) | 1x Volta iGPU (512 CUDA cores) | 2x Volta iGPU (512 CUDA cores) | 1x Ampere iGPU | 1x Ampere iGPU | ?x Ada Lovelace GPU | ?x Blackwell GPU |
| dGPU | — | — | 1x 2 SM Pascal dGPU (1280 CUDA cores) on a MXM slot | 1x 2 SM Pascal dGPU (1280 CUDA cores) on a MXM slot | 2x 2 SM Pascal dGPU (1280 CUDA cores) on MXM slots | 1x 2 SM Pascal dGPU (1280 CUDA cores) | — | 2x Turing dGPU (2560 CUDA cores) | — | 1x Ampere dGPU | ?x Ada Lovelace GPU | ?x Blackwell GPU |
| NPU | — | — | — | — | — | — | 1x DLA | 2x DLA | 1x DLA | 1x DLA | ? | ? |
| Vision Accelerator | — | — | — | — | — | — | 1x PVA | 2x PVA | 1x PVA | 1x PVA | ? | ? |
| Memory | ? | ? | 8 GB LPDDR4 4 GB GDDR5 (dGPU) | 8 GB LPDDR4 4 GB GDDR5 (dGPU) | 2x 8 GB LPDDR4 2x 4 GB GDDR5 (dGPU) | 2x 8 GB LPDDR4 4 GB GDDR5 (dGPU) | 16 GB LPDDR4 | 2x 16 GB LPDDR4 2x 16 GB GDDR6 (dGPU) | 32 GB LPDDR5 | 32 GB LPDDR5 80 GB HBM2e (dGPU) | ? | ? |
| Storage | ? | ? | 64 GB eMMC | ? | 128 GB eMMC | ? | ? | ? | 256 GB | 256 GB | ? | ? |
| Sparse Performance | — | — | — | — | — | — | — | — | 167 INT8 TOPS (iGPU) 87 INT8 TOPS (DLA) | 900 INT8 TOPS (dGPU) 167 INT8 TOPS (iGPU) 87 INT8 TOPS (DLA) | 1000 INT8 TOPS (Total) | 1000 INT8 TOPS (Total), 1000 FP8 TFLOPS (Total), 500 FP16 TFLOPS (Total) |
| Dense Performance | 1 FP16 TFLOPS (iGPU) | 2x 1 FP16 TFLOPS (iGPU) | 10-12 INT8 TOPS (Total) 4 FP32 TFLOPS (Total) | 10-12 INT8 TOPS (Total) 4 FP32 TFLOPS (Total) | 20-24 INT8 TOPS (Total) 16 FP16 TFLOPS (Total) 8 FP32 TFLOPS (Total) | 10-12 INT8 TOPS (Total) 4 FP32 TFLOPS (Total) | 20 INT8 TOPS, 1.3 FP32 TFLOPS (iGPU) 10 INT8 TOPS, 5 FP16 TFLOPS (DLA) 1.6 TOPS (PVA) | 2x 130 INT8 TOPS (dGPU) 2x 20 INT8 TOPS (iGPU) 2x 10 INT8 TOPS (DLA) 2x 1.6 TOPS (PVA) | 83.5 INT8 TOPS (iGPU) 43.5 INT8 TOPS (DLA) | 450 INT8 TOPS (dGPU) 83.5 INT8 TOPS (iGPU) 43.5 INT8 TOPS (DLA) | 500 INT8 TOPS (Total) | 500 INT8 TOPS (Total), 500 FP8 TFLOPS (Total), 250 FP16 TFLOPS (Total) |
| Power | ? | 20 W | 40 W SoC portion: 10 W | 40 W SoC portion: 10 W | 80 W SoC portion: 20 W | 60 W SoC portion: 20 W | 30 W | 500 W | 100 W | ? | ? | ? |
Note: dGPU and memory are stand-alone semiconductors; all other components, especially ARM CPU cores, iGPU, DLA and PVA are integrated components of the listed main computing device(s). Tesla 2.0 and 2.5 are products, not developer kits.