# Multi-threshold CMOS

Multi-threshold CMOS (MTCMOS) is a variation of CMOS chip technology which has transistors with multiple threshold voltages (V$_{th}$) in order to optimize delay or power. The V$_{th}$ of a MOSFET is the gate voltage where an inversion layer forms at the interface between the insulating layer (oxide) and the substrate (body) of the transistor. Low V$_{th}$ devices switch faster, and are therefore useful on critical delay paths to minimize clock periods. The penalty is that low V$_{th}$ devices have substantially higher static leakage power. High V$_{th}$ devices are used on non-critical paths to reduce static leakage power without incurring a delay penalty. Typical high V$_{th}$ devices reduce static leakage by 10 times compared with low V$_{th}$ devices.
One method of creating devices with multiple threshold voltages is to apply different bias voltages (Vb) to the base or bulk terminal of the transistors. Other methods involve adjusting the gate oxide thickness, gate oxide dielectric constant (material type), or dopant concentration in the channel region beneath the gate oxide.
A common method of fabricating multi-threshold CMOS involves simply adding additional photolithography and ion implantation steps. For a given fabrication process, the V$_{th}$ is adjusted by altering the concentration of dopant atoms in the channel region beneath the gate oxide. Typically, the concentration is adjusted by ion implantation method. For example, photolithography methods are applied to cover all devices except the p-MOSFETs with photoresist. Ion implantation is then completed, with ions of the chosen dopant type penetrating the gate oxide in areas where no photoresist is present. The photoresist is then stripped. Photolithography methods are again applied to cover all devices except the n-MOSFETs. Another implantation is then completed using a different dopant type, with ions penetrating the gate oxide. The photoresist is stripped. At some point during the subsequent fabrication process, implanted ions are activated by annealing at an elevated temperature.
In principle, any number of threshold voltage transistors can be produced. For CMOS having two threshold voltages, one additional photomasking and implantation step is required for each of p-MOSFET and n-MOSFET. For fabrication of normal, low, and high V$_{th}$ CMOS, four additional steps are required relative to conventional single-V$_{th}$ CMOS.

## Implementation

The most common implementation of MTCMOS for reducing power makes use of sleep transistors. Logic is supplied by a virtual power rail. Low V$_{th}$ devices are used in the logic where fast switching speed is important. High V$_{th}$ devices connecting the power rails and virtual power rails are turned on in active mode, off in sleep mode. High V$_{th}$ devices are used as sleep transistors to reduce static leakage power.
The design of the power switch which turns on and off the power supply to the logic gates is essential to low-voltage, high-speed circuit techniques such as MTCMOS. The speed, area, and power of a logic circuit are influenced by the characteristics of the power switch.
In a "coarse-grained" approach, high V$_{th}$ sleep transistors gate the power to entire logic blocks. The sleep signal is de-asserted during active mode, causing the transistor to turn on and provide virtual power (ground) to the low V$_{th}$ logic. The sleep signal is asserted during sleep mode, causing the transistor to turn off and disconnect power (ground) from the low V$_{th}$ logic. The drawbacks of this approach are that:
* logic blocks must be partitioned to determine when a block may be safely turned off (on)
* sleep transistors are large and must be carefully sized to supply the current required by the circuit block
* an always active (never in sleep mode) power management circuit must be added
In a "fine-grained" approach, high V$_{th}$ sleep transistors are incorporated within every gate. Low V$_{th}$ transistors are used for the pull-up and pull-down networks, and a high V$_{th}$ transistor is used to gate the leakage current between the two networks. This approach eliminates problems of logic block partitioning and sleep transistor sizing. However, a large amount of area overhead is added due both to inclusion of additional transistors in every Boolean gate, and in creating a sleep signal distribution tree.
An intermediate approach is to incorporate high V$_{th}$ sleep transistors into threshold gates having more complicated function. Since fewer such threshold gates are required to implement any arbitrary function compared to Boolean gates, incorporating MTCMOS into each gate requires less area overhead. Examples of threshold gates having more complicated function are found with Null Convention Logic (NCL) and Sleep Convention Logic (SCL). Some art is required to implement MTCMOS without causing glitches or other problems.