# F-14 CADC

The F-14's Central Air Data Computer, also abbreviated as CADC, computes altitude, vertical speed, air speed, and mach number from sensor inputs such as pitot and static pressure and temperature. From 1968 to 1970, the first CADC to use custom digital integrated circuits was developed for the F-14.

## History

The CADC was a multi-chip integrated flight control system developed by Garrett AiResearch and used in early versions of the US Navy's F-14 Tomcat fighter. It is notable for early use of MOS custom integrated circuits and has been claimed as the first microprocessor chipset. The first commercial microprocessor chip was the contemporary Intel 4004. The 4004 did not have nearly the computing power or interfacing capability required to perform the functions of the CADC. At the time, the best integrated circuit (chip) technology available lacked the scale (number of transistors per chip) necessary to build a single-chip microprocessor for a flight control system.
The CADC was designed and built by a team led by Steve Geller and Ray Holt, and supported by the startup American Microsystems. Design work started in 1968 and was completed in June 1970, beating a number of electromechanical systems that had also been designed for the F-14. It was classified by the Navy until 1998. Ray Holt's story of this design and development is presented in his autobiography The Accidental Engineer.
In 1971, Holt wrote an article about the system for Computer Design magazine. The Navy classified it, and released it in 1998.

## Components

The CADC consisted of an analog-to-digital converter, several quartz pressure sensors, and a number of MOS-based microchips. Inputs to the system included the primary flight controls, a number of switches, static and dynamic air pressure (for calculating stall points and aircraft speed) and a temperature gauge. The outputs controlled the wing sweep and the maneuver flaps and slats and limited allowable control inputs.
The CADC's MP944 chip set ran at 375 kHz, executing 9375 instructions per second and was based on a 20-bit fixed-point-fraction two's complement number system. The complete 28-chip system enabled by 74,442 transistors used the following 6 unique dual in-line package (DIP) chips:
| Chip name | Abbreviation | Pin count | Purpose | Number of chips used in the system |
| Read-only memory | ROM | 14 | provides instructions and constants | 19 |
| Steering logic unit | SLU | 28 | decodes instructions and routes data into a computation unit | 3 |
| Parallel multiplier unit | PMU | 28 | computation unit | 1 |
| Parallel divider unit | PDU | 28 | computation unit | 1 |
| Special logic function | SLF | 28 | computation unit | 1 |
| Random-access storage | RAS | 14 | stores data from its computation unit | 3 |
The system arranges these chips into 3 modules. Each module consists of a set of ROMs which serially send microinstructions and constants to that module's SLU, which routes data inputs to that module's computation unit (either a PMU, a PDU, or a SLF), whose results are written into that module's RAS and routed via the SLUs to any module. Each module forms its own pipeline and can be used without the others. This made it easy to expand the system with additional modules. Multiple pipelines worked at the same time, a parallel computing technique called "pipeline concurrency". The ROM stores 128 words of 20-bits each. A register counter in ROM can be reset, step through the words in sequence, accept a retain address command and hold the present address, and accept a numerical input for address modifying or loading.