# COP400

The COP400 or COP II is a 4-bit microcontroller family introduced in 1977 by National Semiconductor as a follow-on product to their original PMOS COP microcontroller. COP400 family members are complete microcomputers containing internal timing, logic, ROM, RAM, and I/O necessary to implement dedicated controllers. Some COP400 devices were second-sourced by Western Digital as the WD4200 family. In the Soviet Union several COP400 microcontrollers were manufactured as the 1820 series (e.g. the COP402 with designation КР1820ВЕ1).
The COP400 is implemented in CMOS or N-channel silicon gate MOS technology. It was typically packaged in 24- or 28-pin DIP packages. Instruction cycle time of the faster family members is 4 microseconds. The COP400 family offered several memory and pinout configurations.
Notable products that used COP400-family chips include the Apple Lisa, Milton Bradley and Mattel electronic games, Coleco Head to Head Basketball, the Grundy Newbrain, and others.

## Memory

The COP400 uses separate memory spaces for ROM and RAM. ROM addresses are 11-bit maximum, while data addresses are 7-bit maximum.

### ROM

Program memory consists of a 512, 1024, or 2048 × 8-bit ROM. ROM bytes may be program instructions, program data, or jump address pointers. Due to the special characteristics associated with the JP and JSRP instructions, ROM must often be conceived of as organized into pages of 64 bytes each. Also, because of the unique operations performed by the LQID and JID instructions, ROM pages must sometimes be thought of as organized into blocks of 256 bytes.

### RAM

Data memory consists of a 32, 64, or 128 × 4-bit RAM, organized as several data registers of 16 4-bit digits. RAM addressing is implemented by the 6- or 7-bit B register used as a pointer. The B register's upper 2 or 3 bits (Br) select one of 4 or 8 data registers and lower 4 bits (Bd) select one of 16 4-bit digits in the selected data register. The 4-bit contents of the RAM digit pointed to by the B register are usually loaded into, exchanged with, or operate on the A register.

## CPU registers

The register configuration shown in the diagram is for the COP400 family members with maximum ROM (2048 × 8 bits) and RAM (128 × 4 bits). Family members with only 512 or 1024 bytes of ROM will have only a 9- or 10-bit PC. Those with 64 or 32 locations of RAM will have only a 2-bit Br register. Some low end family members omit the SC stack register.
The 4-bit A register (accumulator) is the source and destination register for most arithmetic, logic, and data memory access operations. It can also be used to load the Br and Bd portions of the B register, to load and input 4 bits of the 8-bit Q latch data, to input 4 bits of the 8-bit L port and to perform data exchanges with the SIO register.
When transferring data to an 8-bit register (such as Q or an 8-bit I/O port), the least significant 4 bits are taken from RAM(B), the RAM location pointed to by the B register, and the most significant 4 bits are taken from A. When transferring data from an 8-bit register, the halves are reversed: the least significant 4 bits are written to A, and the most significant 4 bits are written to RAM(B).
A 4-bit ALU performs the arithmetic and logic functions, storing results in A. ASC and CASC operations output a carry to the 1-bit C register, most often employed to indicate arithmetic overflow.
All ROM addressing is accomplished via the 9-, 10-, or 11-bit PC register. Its binary value selects one of the bytes contained in ROM, usually the next program instruction. The value of PC is automatically incremented by 1 prior to the execution of the current instruction to point to the next sequential ROM location. This ensures that when executing a subroutine call, the saved PC is the address of the next instruction, and when executing any control transfer, the target address written to PC is used unmodified. The PC automatically rolls over to point to the next 64 byte page or 256 byte block of program memory. The upper bits of PC are also used to complete the 8-bit addresses specified by the JID and LQID instructions.
Three levels of subroutine are implemented by the subroutine save registers, SA, SB, and SC, providing a last-in, first-out (LIFO) hardware subroutine stack. Some implementations do not have a SC. One implementation detail is that the LQID instruction uses one level of the stack. The ROM address to be fetched from is copied to the PC register, and the stack is used to temporarily save its value, so LQID has the side effect of overwriting SC with a copy of SB.

## I/O registers and ports

There are no port numbers or memory addresses associated with the COP400 I/O devices. All the physical I/O registers and ports are referenced by the COP400 assembly language directly by name.

### Baseline

Nearly all COP400 family devices implement the following:
* Four general-purpose inputs, IN$_0$-IN$_3$, are provided. 24-pin packages do not have IN$_0$-IN$_3$.
* The D register provides four general purpose outputs and is the destination register for the 4-bit contents of Bd. The D register is useful for synchronizing up to 16 external devices associated with the RAM pointed to by the B register.
* The G register contains 4 general purpose bidirectional I/O ports.
* The Q register is an internal, latched, 8-bit register used to hold data loaded to or from RAM(B) and A, as well as 8-bit program data from ROM. Its contents are output to the L ports when the L drivers are enabled under program control. Also, the contents of L may be read directly into A and RAM(B).
* The SIO register functions as a 4-bit serial-in/serial-out shift register or as a binary counter depending on the contents of the EN register. Its contents can be exchanged with A, allowing it to input or output a continuous serial data stream.
* The EN register is an internal 4-bit register loaded under program control by the LEI instruction. The state of each bit of this register selects or deselects the particular feature associated with each bit of the EN register.
* Though not directly accessible with software, the 10-bit time base counter divides the instruction cycle frequency by 1,024, providing a pulse upon overflow. The SKT instruction tests for the occurrence of this pulse, allowing the programmer to implement timer routines. Some low-end COP400 family members do not have this time base counter nor the SKT instruction. Some high-end COP400 devices can read and write the upper eight bits of the timer.

### High end

There are a few high end members of the COP400 family such as the COP440 and COP2440 that have 40-pins. These have additional registers and ports:
* The R port is an additional eight-bit bidirectional I/O port, similar to Q. The R port contains latches and drivers. Data to be output is latched into the R register. The input path is from the pins to the accumulator and RAM. Input data at the R pins are not latched into the R register by any external signal. This must be done indirectly by the program. The R drivers, like the L drivers, can be put into a high impedance state.
* These devices have an additional bidirectional four-bit port, the H port. The H port is essentially a duplicate of the G port except that H cannot be directly tested.
* The EN register is expanded to 8 bits. EN$_4$-EN$_5$ select interrupt sources. EN$_6$ selects the source of the T counter. EN$_7$ controls the output drivers of the R port. The 8-bit EN is written with the CAME instruction and read with CEMA. The lower 4 bits can be written with LEI.

## Instruction set

The COP400 family is designed to have very compact code. All instructions are one or two bytes long. The most frequently used instructions are one byte. In some cases there are special one-byte forms of two-byte instructions. Some features that can be used to make object code more compact are:
* The LBI instruction loads the seven-bit B register with an immediate value. The general-form instruction takes two bytes. There is a one-byte form of LBI that can only set Br to 0, 1, 2, and 3 and can only set Bd to 9, 10, 11, 12, 13, 14, 15, and 0 (decimal). The single byte LBI can only access 32 RAM locations.
* Multiple LBI instructions can be stacked in series. Only the first LBI will be executed. Subsequent LBI instructions will execute as NOPs. This allows multiple entry points with different starting addresses for a shared routine.
* JSR, in the general subroutine branch form, is two bytes and can access any memory location directly. JSRP is a single-byte form of subroutine branch that can access only the locations in the third 64-byte page. This page is called the subroutine page or page 2, numbered from zero. A JSRP cannot be coded from inside page 2 or 3.
* JMP, in the general branch form, is two bytes and can access any memory location directly. JP is a single-byte form of branch that can access any location in the current 64-byte page. The upper bits of PC remain unchanged. If the JP instruction is executed inside page 2 or 3, then it can access any of the 128 addresses in pages 2 and 3. This is useful for creating a one byte JSRP entry point in page 2 that can then branch to a subroutine on page 3 with a single byte JP.
* The B register can be used to point to up to four RAM strings with little overhead. The LD, X, XIS, and XDS memory access instructions can Exclusive OR the lower two bits of Br with a two-bit immediate. This allows the register portion of B (Br) to be flipped to one of the other digit strings that share the same digit (Bd) address.
* The Bd register portion can be used as a memory pointer and a loop counter simultaneously. The XIS instruction will skip if Bd, after incrementing, overflows to zero, falling through the loop. Likewise the XDS instruction will skip if Bd, after decrementing, underflows to 15 (decimal).
COP400 family instruction set :
| Opcode | Opcode | Opcode | Opcode | Opcode | Opcode | Opcode | Opcode | Operand | Mnemonic | Description | Skip |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Operand | Mnemonic | Description | Skip |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | — | CLRA | A ← 0 | — |
| 0 | 0 | 0 | b$_0$ | 0 | 0 | b$_1$ | 1 | — | SKMBZ b | Skip if memory bit zero | RAM(B)$_b$ = 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | — | XOR | A ← A ⊻ RAM(B) | — |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | — | CASC | A ← ~A + RAM(B) + C, C ← Carry | C = 1 |
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | — | XABR | A ↔ Br, A$_3$ ← 0 | — |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | — | SKC | — | C = 1 |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | — | SKE | — | A = RAM(B) |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | — | SC | C ← 1 | — |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0rrrdddd | LDD r,d | A ← RAM(r,d) | — |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1rrrdddd | XAD r,d | A ↔ RAM(r,d) | — |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | — | ASC | A ← A + RAM(B) + C, C ← Carry | C = 1 |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | — | ADD | A ← A + RAM(B) | — |
| 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | — | RC | C ← 0 | — |
| 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | opcode | 33H prefix | See table below for instructions with this prefix | — |
| 0 | 0 | r | r | 0 | 1 | 0 | 0 | — | XIS r | A ↔ RAM(B), Br ← Br ⊻ r, Bd ← Bd + 1 | Bd = 0 |
| 0 | 0 | r | r | 0 | 1 | 0 | 1 | — | LD r | A ← RAM(B), Br ← Br ⊻ r | — |
| 0 | 0 | r | r | 0 | 1 | 1 | 0 | — | X r | A ↔ RAM(B), Br ← Br ⊻ r | — |
| 0 | 0 | r | r | 0 | 1 | 1 | 1 | — | XDS r | A ↔ RAM(B), Br ← Br ⊻ r, Bd ← Bd - 1 | Bd = 15 |
| 0 | 0 | r | r | 1 | d | d | d | — | LBI r,d | Br ← r, Bd ← (d+9)∧15 (Br = 0–3, Bd = 9–15, 0) | next LBI |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | — | COMP | A ← ~A | — |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | — | SKT | Skip on timer overflow | timer |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | — | RMB 2 | RAM(B)$_2$ ← 0 | — |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | — | RMB 3 | RAM(B)$_3$ ← 0 | — |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | — | NOP | No operation | — |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | — | RMB 1 | RAM(B)$_1$ ← 0 | — |
| 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | — | SMB 2 | RAM(B)$_2$ ← 1 | — |
| 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | — | SMB 1 | RAM(B)$_1$ ← 1 | — |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | — | RET | Pop PC (PC ← SA, SA ← SB, SB ← SC) | — |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | — | RETSK | Pop PC | always |
| 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | — | ADT | A ← A + 10 | — |
| 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | — | SMB 3 | RAM(B)$_3$ ← 1 | — |
| 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | — | RMB 0 | RAM(B)$_0$ ← 0 | — |
| 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | — | SMB 0 | RAM(B)$_0$ ← 1 | — |
| 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | — | CBA | A ← Bd | — |
| 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | — | XAS | A ↔ SIO, SK ← C | — |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | — | CAB | Bd ← A | — |
| 0 | 1 | 0 | 1 | y | y | y | y | — | AISC y | A ← A + y (1 ≤ y ≤ 15, C unchanged) | carry |
| 0 | 1 | 1 | 0 | 0 | addhi | addhi | addhi | addlo | JMP a | PC[10:8] ← addhi, PC[7:0] ← addlo | — |
| 0 | 1 | 1 | 0 | 1 | addhi | addhi | addhi | addlo | JSR a | Push PC, PC[10:8] ← addhi, PC[7:0] ← addlo | — |
| 0 | 1 | 1 | 1 | y | y | y | y | — | STII y | RAM(B) ← y, Bd ← Bd + 1 | — |
| 1 | addr | addr | addr | addr | addr | addr | addr | — | JP a | If PC[10:7] = 0001: PC[6:0] ← addr | — |
| 1 | 0 | addr | addr | addr | addr | addr | addr | — | JSRP a | If PC[10:7] ≠ 0001: Push PC, PC[10:6] ← 00010, PC[5:0] ← addr | — |
| 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | — | LQID | Q ← ROM(PC[10:8], A, RAM(B)), SC ← SB | — |
| 1 | 1 | addr | addr | addr | addr | addr | addr | — | JP a | If PC[10:7] ≠ 0001: PC[5:0] ← addr | — |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | — | JID | PC[7:0] ← ROM(PC[10:8], A, RAM(B)) | — |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Operand | Mnemonic | Description | Skip |
2-byte opcodes prefixed with 33H (support depends on CPU type) :
| Opcode | Opcode | Opcode | Opcode | Opcode | Opcode | Opcode | Opcode | Mnemonic | Description | Skip | CPU Types |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Mnemonic | Description | Skip | CPU Types |
| 0 | 0 | 0 | b$_0$ | 0 | 0 | b$_1$ | 1 | SKGBZ b | — | G$_b$ = 0 | All |
| 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | XAN | A[1:0] ↔ N, A[2:3] ← 0 | — | 3 |
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | CEMA | RAM(B) ← EN[7:4], A ← EN[3:0] | — | 3 |
| 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | LID | RAM(B), A ← ROM(PC[10:8], A, RAM(B)) | — | 3 |
| 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | OR | A ← A ∨ RAM(B) | — | 3 |
| 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | SKSZ | — | SIO = 0 | 3 |
| 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | CAME | EN[7:4] ← A, EN[3:0] ← RAM(B) | — | 3 |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | SKGZ | — | G = 0 | All |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | ININ | A ← IN | — | 2, 3 |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | INIL | A ← IL$_3$, 1, 0, IL$_0$ or A ← IL$_3$, CKO, 0, IL$_0$ | — | 2, 3 |
| 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | ING | A ← G | — | All |
| 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | INH | A ← H | — | 3 |
| 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | CQMA | RAM(B) ← Q[7:4], A ← Q[3:0] | — | 2, 3 |
| 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | INR | RAM(B) ← R[7:4], A ← R[3:0] | — | 3 |
| 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | INL | RAM(B) ← L[7:4], A ← L[3:0] | — | All |
| 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | CTMA | RAM(B) ← T[7:4], A ← T[3:0] | — | 3 |
| 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | HALT | Stop operation | — | CMOS |
| 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | IT | Stop until timer overflow | — | CMOS |
| 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | OMG | G ← RAM(B) | — | All |
| 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | OMH | H ← RAM(B) | — | 3 |
| 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | CAMQ | Q[7:4] ← A, Q[3:0] ← RAM(B) | — | All |
| 0 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | CAMR | R[7:4] ← A, R[3:0] ← RAM(B) | — | 3 |
| 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | OBD | D ← Bd | — | All |
| 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | CAMT | T[7:4] ← A, T[3:0] ← RAM(B) | — | 3 |
| 0 | 1 | 0 | 1 | y | y | y | y | OGI y | G ← y | — | 2, 3 |
| 0 | 1 | 1 | 0 | y | y | y | y | LEI y | EN ← y | — | All |
| 1 | r | r | r | d | d | d | d | LBI r,d | Br ← r, Bd ← d | next LBI | 2, 3 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Mnemonic | Description | Skip | Types supported |
Types supported: Type 1 is very low-end such as COP410. Type 2, such as the COP420, is most common. Type 3 typically have resources to support 40 pins even if package does not have 40 pins. Type 4 is not shown as there is no evidence that Type 4 was produced. CMOS includes COP424C, COP425C, COP426C, COP444C, COP445C, COP404C.

### Example code

This example code demonstrates several of the space saving features on the instruction set:
* single-byte LBI instructions
* multiple LBI instructions in series creating multiple entry points
* LD XORing Br so B is flipped to the destination and XIS flipping B back to source
* Bd sharing pointer and loop counter duties via the skip function in XIS
* single byte jump, JP
| 040 09 041 19 042 2F 043 15 044 14 045 C3 046 48 | ; Copy a block of memory from one location to another. ; ; There are three entry points: copyA, copyB, and copyC. ; The values of the LBI instructions are expressed as ; LBI Br, Bd. ; copyA: LBI 0,10 ;Copy 6 nibbles starting 0,10 to 1,10 copyB: LBI 1,10 ;Copy 6 nibbles starting 1,10 to 0,10 copyC: LBI 2,0 ;Copy 16 nibbles starting 2,0 to 3,0 loop: LD 1 ;Load src in A. XOR Br with 1 to get dest XIS 1 ;Save A in dest. Inc Bd. XOR Br with 1 to get src JP loop ;loop until Bd goes past last digit location RET |

## Interrupt

Early COP400 devices that have 28 pins or more support a single interrupt. The IN 1 line is used as the interrupt input. Interrupt is enabled by setting bit 1 of the EN register to 1 with a LEI instruction. In response to low-going pulse of at least two instruction cycles long on IN 1, all transfer of control instructions such as JP are completed and all sequential LBI instructions are executed. The PC is then pushed on the subroutine stack and control is transferred to the interrupt handler at address 0xFF. No subroutines may be called in the interrupt service routine on devices with a hardware stack. Curiously, later devices such as the COP440 support four interrupt sources and two service routines but only one interrupt source can be selected at a time. Subroutines are supported inside interrupt service routines on devices with a stack pointer.

## Architectural extensions

Although the majority of COP400 devices were targeted at low-end applications, several extensions to the architecture were created to address more demanding applications. Dual CPU, a deeper stack in RAM, and larger address spaces were added to some devices by 1985.

### Dual CPU

"Dual CPU" versions of the COP400 were announced by National Semiconductor in 1981. These single-chip barrel processors contain two ostensibly independent CPUs that share instructions, memory, and most IO devices. In reality, the CPUs are not fully independent and share hardware resources similar to Intel processors with Hyper-Threading Technology (HTT). Like HTT, the dual CPU version works by duplicating certain sections of the processor—those that store the architectural state—but not duplicating the main execution resources such as ALU, buses, and memory. Separate architectural states for each of the two virtual processors is established with duplicated A (accumulators), B (pointer registers), C (carry flags), N (stack pointers), and PC (program counters).
When the reset is deasserted, both processors start at location 0 which contains a CLRA instruction, then one processor jumps to location 401 (hex) followed an instruction cycle later by the second processor executing location 1. The processors will then alternately execute one byte of code each.
At maximum clock frequency, the instruction execution time (single byte instruction) for each processor is 4 microseconds, hence, the instruction cycle time for either processor is twice that amount, 8 microseconds.
Some dual CPU versions include the 40-pin COP2440N, the 28-pin COP2441N, and the 24-pin COP2442N.

### Return stack in RAM

Earlier COP400 devices included a two or three level dedicated hardware return stack. Later devices such as the COP440 feature a 4-level return stack implemented with a 2-bit stack pointer and RAM. Dual CPU versions have two separate 4-level return stacks implemented with two 2-bit stack pointers and two different RAM areas.

### Larger address space

The basic COP400 instruction set supports ROM addresses of up to 11-bits (2,048 bytes), while data addresses are 7-bits maximum (128 locations). The so-called group 4 devices extended the memory limit by adding three-byte JMP, JSR, and LBI instructions with more address bits. These support ROM addresses of 15-bits maximum (32,768 bytes), while data addresses are 9-bits maximum (512 locations). Devices that support these instructions include COP408, COP484, COP485, C0P409. It is unclear whether any of these group 4 devices were produced.

## Applications

* Apple Lisa utilized a COP421 to control the keyboard, mouse, RTC, and soft power switch. A second COP421 controls the spindle motor of the Widget hard disk drive.
* Several manufacturers used COP400 in their early electronic games:
** COP410 and COP411, 512 byte ROM, 32 x 4 RAM: Mattel's Funtronics Jacks, Red Light Green Light, Tag, and Plus One.
** COP420 and COP421, 1024 byte ROM, 64 x 4 RAM: Milton Bradley Lightfight and Electronic Battleship 1982. Castle Toy Company Einstein. Coleco Head to Head Basketball. National Semiconductor Quiz Kid Racer. LJN Toys Ltd I Took a Lickin' from a Chicken.
** COP444, 2048 byte ROM, 128 x 4 RAM: Entex Space Invader. Mattel Dalla$, Texas Instruments My Little Computer.
* Western Digital used a WD4200 (COP420) as the basis for their WD2412 time-of-day clock.
* The Grundy Newbrain computer uses a COP420 to manage its keyboard, tape I/O, and its built-in 16 character VF alphanumeric display.

## Intellectual property

T400 μController is an open source implementation of the COP400 microcontroller written in VHDL. COP420/421 and COP410L/411L devices are supported. T400 is intended to be a replacement for the original chip in SOCs recreating legacy systems. T400 has been implemented in several FPGA families. T400 is available under GNU General Public License.

## Emulator

There is an open-source MAME emulator for the COP400 family and several hand held games and specialty calculators.