# List of VIA microprocessor cores

This article lists x86-compliant microprocessors sold by VIA Technologies, grouped by technical merits: cores within same group have much in common.

## Cyrix design (Cyrix III)

* All models support: MMX, 3DNow!
| Marketing name | Core | Frequency | Front-side bus | L1-cache | L2-cache | FPU speed | Pipeline stages | Typical power | Voltage | Process |
| Cyrix III | Joshua | 350-450 MHz | 100-133 MHz | 64 KB | 256 KB | 100% | ? | 13-16 W | 2.2 V | 180 nm Al |

## Centaur Technology design
### Cyrix III, C3

* All models support: MMX, 3DNow!
| Marketing name | Core | Frequency | Front-side bus | L1 cache | L2 cache | FPU speed | Pipeline stages | Typical power | Voltage | Process |
| Cyrix III, C3, 1GigaPro | Samuel (C5A) | 466-733 MHz | 100-133 MHz | 128 KB | 0 KB | 50% | 12 | 6.8-10.6 W | 1.8-2.0 V | 180 nm Al |
| Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+ | Samuel 2 (C5B) | 600-800 MHz | 100-133 MHz | 128 KB | 64 KB | 50% | 12 | 5.8-6.6 W | 1.5-1.65 V | 150 nm Al |
| C3, Eden ESP | Ezra (C5C) | 733-933 MHz | 100-133 MHz | 128 KB | 64 KB | 50% | 12 | 5.3-5.9 W | 1.35 V | 130 nm Al |
| C3 | Ezra-T (C5N) | 800-1000 MHz | 100-133 MHz | 128 KB | 64 KB | 50% | 12 | 5.3-11.8 W | 1.35-1.45 V | 130 nm Al |

### C3, C7

* All models support: MMX, SSE
* SSE2, SSE3, NX bit supported by Esther (C5J)
* x86 (no x86-64)
| Marketing name | Core | Frequency | Front-side bus | L1 cache | L2 cache | FPU speed | Pipeline stages | Typical power | Voltage | Process |
| C3, Eden ESP, Eden-N | Nehemiah (C5XL) | 800-1400 MHz | 133 MHz | 128 KB | 64 KB | 100% | 16 | 15-19 W | 1.25 or 1.4-1.45 V | 130 nm Cu |
| C3 | Nehemiah+ (C5P) | 1-1.4 GHz | 133 MHz | 128 KB | 64 KB | 100% | 16 | 11-12 W | 1.25 V | 130 nm Cu |
| C7, C7-D, C7-M, Eden, Eden ULV | Esther (C5J) | 0.4-2.0 GHz | 400-533 MT/s | 128 KB | 128 KB | 100% | 16 | 12-20 W | 0.9-1.1(?) V | 90 nm SOI |
| Series | Model | Core | Frequency [MHz] | Front-side bus [MHz] | Year | Process [nm] | Package size [mm$^2$] | Power [W] | L2 cache [K] | L1 I/D cache [K] | Performance [SPEC2000] |
| Eden | Eden ESP | Samuel 2 | 300–600 | 66/100/133 | 2001 | 150 | 35×35 | 2.5–6 | 64 | 64/64 | Un­known |
| Eden | Eden ESP | Nehemiah | 667–1000 | 133/200 | 2003–2004 | 130 | 35×35 | 6–7 | 64 | 64/64 | Un­known |
| Eden | Eden-N | Nehemiah | 533–1000 | 133 | 2003 | 130 | 15×15 | 2.5–7 | 64 | 64/64 | Un­known |
| Eden | Eden | Esther | 400–1500 | 400–800 | 2006–2007 | 90 | 30 | <7.5 | 128 | 32/32 | Un­known |
| Eden | Eden X2 | Un­known | 800 | Un­known | 2011 | 40 | 11×6 | Un­known | Un­known | Un­known | Un­known |
| C3 | C3 | Samuel 2 | 667–800 | 100–133 | 2001 | 150 | Un­known | 13 | 64 | 64/64 | Un­known |
| C3 | C3 | Ezra | 800–1000 | 100–133 | 2002 | 130 | Un­known | 8.3–10 | 64 | 64/64 | Un­known |
| C3 | C3 | Nehemiah | 1000–1400 | 133–200 | 2003 | 130 | 35×35 | 15–21 | 64 | 64/64 | Un­known |
| C3 | C3-M | Nehemiah | 1000–1400 | 133–200 | 2003 | 130 | 35×35 | 11–19 | 64 | 64/64 | Un­known |
| C7 | C7-D | Esther | 1500–1800 | 400 | 2006 | 90 | 21×21 | 20–25 | 128 | 16/16 | Un­known |
| C7 | C7-M | Esther | 1000–2000 | 400 | 2005 | 90 | 21×21 | 12–20 | 128 | 16/16 | Un­known |
| C7 | C7 | Esther | 1500–2000 | 800 | 2007 | 90 | 21×21 | 12–20 | 128 | 16/16 | Un­known |

### Nano

* First VIA processor with x86-64 instruction set
| Series | Model | Core | Frequency [MHz] | Front-side bus [MHz] | Year | Process [nm] | Package size [mm$^2$] | Power [W] | L2 cache [K] | L1 I/D cache [K] | Performance [SPEC2000] |
| QuadCore | QuadCore | Isaiah | 1000-1460 | 1066 | 2011 | 40 | 21×21 | 27.5 | 4× 1024 | 4× 64/64 | 30.1/24.1 rate |
* See List of Nano microprocessors

### CHA

* Announced 2019. Discontinued in 2021 with the sales of Centaur to Intel.
* 8 cores + "NCORE" neural processor for AI acceleration.
* supports: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AES AVX AVX2 FMA3 SHA AVX512 AVX512F AVX512CD AVX512BW AVX512DQ AVX512VL AVX512IFMA AVX512VBMI.
| Marketing name | Code name | Core | Number of cores | Frequency | Microarchitecture | L1 cache | L2 cache | L3 cache | Announced | Expected Release | Process | Socket Type | Pipeline stages | PCIe Lanes |
| unknown | CHA | CNS | 8 | 2.5 GHz | CNS | 32 KiB | 256 KiB | 16 MB | 2019 | 2H 2020 | 16 nm | LGA | 20-22 | 44 |