# RP2350

RP2350 is a 32-bit dual-core microcontroller (containing selectable ARM Cortex-M33 and/or Hazard3 RISC-V cores) by Raspberry Pi Ltd. In August 2024, it was released as part of the Raspberry Pi Pico 2 board.

## Overview

Announced on 8 August 2024, the RP2350 is the second microcontroller designed by Raspberry Pi Ltd, after the RP2040. The microcontroller is low cost, with the Raspberry Pi Pico 2 being introduced at US$5 and the RP2350 itself costing as little as US$0.80 in bulk. The microcontroller is software-compatible with the RP2040 and can be programmed in assembly, C, C++, Free Pascal, Rust, MicroPython, CircuitPython, and other languages.
The RP2350 comes in four versions, which are identified by the number of cores (2), a numeral loosely correlated to the core type (3), log₂ of the number of 16 KB RAM blocks (5), log₂ of the number of 128 KB flash storage blocks (0 or 4), and a letter denoting package type (A or B):
* RP2350A - 30 GPIO in a 7 × 7 mm QFN-60EP package (EP means exposed pad in center)
* RP2350B - 48 GPIO in a 10 × 10 mm QFN-80EP package (EP means exposed pad in center)
* RP2354A - same package as RP2350A (above) includes 2 MB QSPI NOR flash
* RP2354B - same package as RP2350B (above) includes 2 MB QSPI NOR flash
Note: inside the "54" IC packages, a NOR flash die is stacked on top of the microcontroller die, then connected to its QSPI bus and first chip select.
At announcement time, seventeen other manufacturers had products expected to be available within a month.

## Features

The chip is a 5.3 mm$^2$ (0.0082 sq in) silicon die in a 7 × 7 mm QFN-60EP or 10 × 10 mm QFN-80EP surface-mount device (SMD) package.
* Key features:
** 150 MHz dual ARM Cortex-M33 (ARMv8-M) and dual Hazard3 RISC-V (RV32IMAC+) cores (only two active at a time)
*** Each Cortex-M33 core includes DSP instructions, single-precision (SP) floating-point instructions, and a simplified double-precision floating-point coprocessor provides add, subtract, multiply, divide, square root.
** 520 KB SRAM in ten concurrently accessible banks
** 8 KB of one-time-programmable (OTP) memory
** QSPI bus controller supports external flash and PSRAM
*** Optional in-package 2 MB QSPI NOR flash connected to first chip select
** DMA controller, 16 channel, 4 IRQ
** AHB crossbar, fully-connected
** On-chip switched-mode power supply and programmable low-dropout regulator (LDO) to generate core voltage
** Two on-chip PLLs to generate 48 MHz USB and 150MHz core clocks
** RP2350A has 30 GPIO pins, of which four can optionally be used as analog inputs, RP2350B has 48 GPIO pins where eight can be used as analog inputs.
** Optional boot signing with protected OTP storage
** Hardware SHA-256 accelerator
** Hardware random number generator (TRNG)
* Peripherals:
** One USB 1.1 (LS & FS) controller and PHY, host and device support, 1.5 Mbps (Low Speed) and 12 Mbps (Full Speed).
** Two UART controllers.
** Two SPI controllers.
** One QSPI (quad SPI) controller, supports 1 / 2 / 4-bit SPI transfers, 2 chip selects.
** Two I²C controllers.
** One HSTX (high-speed serial transmit) controller, output-only. This is meant for digital video output.
** 12 PIO (programmable input–output) state machines.
** 24 PWM channels.
** 4/8-channel 12-bit 500-Ksps SAR ADC, extra channel is connected to internal temperature sensor. QFN-60EP package has 4 channels, QFN-80EP package has 8 channels.

### Family comparison

The following is a simplified comparison of the RP2040 and RP2350 microcontroller families.
    FeatureRP2040RP2350 Package QFN-56EPQFN-60EP or QFN-80EP CPU Cores Two ARM Cortex-M0+Two ARM Cortex-M33 (FPU) Two Hazard3 RISC-V CPU Clock 200 MHz150 MHz SRAM 264 KB, 6 banks520 KB, 10 banks Flash NoneNone (RP2350), 2 MB (RP2354) OTP None8 KB DMA 12 chan, 2 IRQ16 chan, 4 IRQ PIO 2 (8 state machines)3 (12 state machines) PWM 1624 ADC 4-chan 12-bit ADC4-chan 12-bit (QFN-60EP), 8-chan 12-bit (QFN-80EP) DAC NoneNone HSTX NoneOne Engines  ?RNG, SHA-256

## GPIO hardware issue

The RP2350 chip was released with errata RP2350-E9, documenting a "Latching behaviour on Bank 0 GPIO pull-down resistors", which was later updated to "Increased leakage current on Bank 0 GPIO when pad input is enabled" due to multiple reports from users, such as developers of the Bus Pirate.
The defect causes pins configured as inputs to source about 120 μA when the input voltage is between logical low and logical high, pulling them to about 2.2V.
Luke Wren, one of the engineers working on RP2350 has stated that the supplier responsible for the pad circuitry has provided a faulty design. "We didn't modify the pad, we asked the vendor to modify their own pad. There was one particular structure on the RP2040 FT pad that limited its tolerance, but on inspection the modified layout we got back was a completely different circuit."