# Soft microprocessor

A soft microprocessor (also called softcore microprocessor or a soft processor) is a microprocessor core that can be wholly implemented using logic synthesis. It can be implemented via different semiconductor devices containing programmable logic (e.g., FPGA, CPLD), including both high-end and commodity variations.
Most systems, if they use a soft processor at all, only use a single soft processor. However, a few designers tile as many soft cores onto an FPGA as will fit. In those multi-core systems, rarely used resources can be shared between all the cores in a cluster.
While many people put exactly one soft microprocessor on a FPGA, a sufficiently large FPGA can hold two or more soft microprocessors, resulting in a multi-core processor. The number of soft processors on a single FPGA is limited only by the size of the FPGA. Some people have put dozens or hundreds of soft microprocessors on a single FPGA. This is one way to implement massive parallelism in computing and can likewise be applied to in-memory computing.
A soft microprocessor and its surrounding peripherals implemented in a FPGA is less vulnerable to obsolescence than a discrete processor.

## Core comparison

| Processor | Developer | Open source | Bus support | Notes | Project home | Description language |
| based on the ARM instruction set architecture |||||||
| Amber | Conor Santifort | LGPLv2.1 | Wishbone | ARMv2a 3-stage or 5-stage pipeline | Project page at Opencores | Verilog |
| Cortex-M1 | ARM | No | | 70–200 MHz, 32-bit RISC | | Verilog |
| based on the AVR instruction set architecture |||||||
| Navré | Sébastien Bourdeauducq | Yes | Direct SRAM | Atmel AVR-compatible 8-bit RISC | Project page at Opencores | Verilog |
| pAVR | Doru Cuturela | Yes | | Atmel AVR-compatible 8-bit RISC | Project page at Opencores | VHDL |
| softavrcore | Andras Pal | Yes | Standard AVR buses (core-coupled I/O, synchronous SRAM, synchronous program ROM) | Atmel AVR-compatible 8-bit RISC (up to AVR5), peripherals and SoC features included | Project page at Opencores | Verilog |
| based on the MicroBlaze instruction set architecture |||||||
| AEMB | Shawn Tan | Yes | Wishbone | MicroBlaze EDK 3.2 compatible | AEMB | Verilog |
| MicroBlaze | Xilinx | No | PLB, OPB, FSL, LMB, AXI4 | | Xilinx MicroBlaze | |
| OpenFire | Virginia Tech CCM Lab | Yes | OPB, FSL | Binary compatible with the MicroBlaze | | Verilog |
| SecretBlaze | LIRMM, University of Montpellier / CNRS | Yes | Wishbone | MicroBlaze ISA, VHDL | SecretBlaze | VHDL |
| based on the MCS-51 instruction set architecture |||||||
| MCL51 | MicroCore Labs | Yes | Ultra-small-footprint microsequencer-based 8051 core | 312 Artix-7 LUTs. Quad-core 8051 version is 1227 LUTs. | MCL51 Core | |
| TSK51/52 | Altium | Royalty-free | Wishbone / Intel 8051 | 8-bit Intel 8051 instruction set compatible, lower clock cycle alternative | Embedded Design on Altium Wiki | |
| based on the MIPS instruction set architecture |||||||
| BERI | University of Cambridge | BSD | | MIPS | Project page | Bluespec |
| Dossmatik | René Doss | CC BY-NC 3.0, except commercial applicants have to pay a licence fee. | Pipelined bus | MIPS I instruction set pipeline stages | Dossmatik | VHDL |
| TSK3000A | Altium | Royalty-free | Wishbone | 32-bit R3000-style RISC modified Harvard-architecture CPU | Embedded Design on Altium Wiki | |
| based on the PicoBlaze instruction set architecture |||||||
| PacoBlaze | Pablo Bleyer | Yes | | Compatible with the PicoBlaze processors | PacoBlaze | Verilog |
| PicoBlaze | Xilinx | No | | | Xilinx PicoBlaze | VHDL, Verilog |
| based on the RISC-V instruction set architecture |||||||
| f32c | University of Zagreb | BSD | AXI, SDRAM, SRAM | 32-bit, RISC-V / MIPS ISA subsets (retargetable), GCC toolchain | f32c | VHDL |
| NEORV32 | Stephan Nolting | BSD | Wishbone b4, AXI4 | rv32[i/e] [m] [a] [c] [b] [u] [Zfinx] [Zicsr] [Zifencei], RISC-V-compliant, CPU & SoC available, highly customizable, GCC toolchain | GitHub OpenCores | VHDL |
| VexRiscv | SpinalHDL | Yes | AXI4 / Avalon | 32-bit, RISC-V, up to 340 MHz on Artix 7. Up to 1.44 DMIPS/MHz. | https://github.com/SpinalHDL/VexRiscv | VHDLVerilog (SpinalHDL) |
| based on the SPARC instruction set architecture |||||||
| LEON2(-FT) | ESA | Yes | AMBA2 | SPARC V8 | ESA | VHDL |
| LEON3/4 | Aeroflex Gaisler | Yes | AMBA2 | SPARC V8 | Aeroflex Gaisler | VHDL |
| OpenPiton | Princeton Parallel Group | Yes | | Manycore SPARC V9 | OpenPiton | Verilog |
| OpenSPARC T1 | Sun | Yes | | 64-bit | OpenSPARC.net | Verilog |
| Tacus/PIPE5 | TemLib | Yes | Pipelined bus | SPARC V8 | TEMLIB | VHDL |
| based on the x86 instruction set architecture |||||||
| CPU86 | HT-Lab | Yes | | 8088-compatible CPU in VHDL | cpu86 | VHDL |
| MCL86 | MicroCore Labs | Yes | 8088 BIU provided. Others easy to create. | Cycle accurate 8088/8086 implemented with a microsequencer. Less than 2% utilization of Kintex-7. | MCL86 Core | |
| s80x86 | Jamie Iles | GPLv3 | Custom | 80186-compatible GPLv3 core | s80x86 | SystemVerilog |
| Zet | Zeus Gómez Marmolejo | Yes | Wishbone | x86 PC clone | Zet | Verilog |
| ao486 | Aleksander Osman | 3-Clause BSD | Avalon | i486 SX compatible core | ao486 | Verilog |
| based on the PowerPC/Power instruction set architecture |||||||
| PowerPC 405S | IBM | No | CoreConnect | 32-bit PowerPC v.2.03 Book E | IBM | Verilog |
| PowerPC 440S | IBM | No | CoreConnect | 32-bit PowerPC v.2.03 Book E | IBM | Verilog |
| PowerPC 470S | IBM | No | CoreConnect | 32-bit PowerPC v.2.05 Book E | IBM | Verilog |
| Microwatt | IBM/OpenPOWER | CC-BY 4.0 | Wishbone | 64-bit PowerISA 3.0 proof of concept | Microwatt @ Github | VHDL |
| Chiselwatt | IBM/OpenPOWER | CC-BY 4.0 | Wishbone | 64-bit PowerISA 3.0 | Chiselwatt @ Github | Chisel |
| Libre-SOC | Libre-SoC.org | BSD/LGPLv2+ | Wishbone | 64-bit PowerISA 3.0. CPU/GPU/VPU implementation and custom vector instructions | Libre-SoC.org | python/nMigen |
| A2I | IBM/OpenPOWER | CC-BY 4.0 | Custom PBus | 64-bit PowerPC 2.6 Book E. In order core | A2I @ Github | VHDL |
| A2O | IBM/OpenPOWER | CC-BY 4.0 | Custom PBus | 64-bit PowerPC 2.7 Book E. Out of order core | A2O @ Github | Verilog |
| Other architectures |||||||
| ARC | ARC International, Synopsys | No | | 16/32/64-bit ISA RISC | DesignWare ARC | Verilog |
| ERIC5 | Entner Electronics | No | | 9-bit RISC, very small size, C-programmable | ERIC5 Archived 2016-03-05 at the Wayback Machine | VHDL |
| H2 CPU | Richard James Howe | MIT | Custom | 16-bit Stack Machine, designed to execute Forth directly, small | H2 CPU | VHDL |
| Instant SoC | FPGA Cores | No | Custom | 32-bit RISC-V M Extension, SoC defined by C++ | Instant SoC | VHDL |
| JOP | Martin Schoeberl | Yes | SimpCon / Wishbone (extension) | Stack-oriented, hard real-time support, executing Java bytecode directly | Jop | VHDL |
| LatticeMico8 | Lattice | Yes | Wishbone | | LatticeMico8 | Verilog |
| LatticeMico32 | Lattice | Yes | Wishbone | | LatticeMico32 | Verilog |
| LXP32 | Alex Kuznetsov | MIT | Wishbone | 32-bit, 3-stage pipeline, register file based on block RAM | lxp32 | VHDL |
| MCL65 | MicroCore Labs | Yes | Ultra-small-footprint microsequencer-based 6502 core | 252 Spartan-7 LUTs. Clock cycle-exact. | MCL65 Core | |
| MRISC32-A1 | Marcus Geelnard | Yes | Wishbone, B4/pipelined | 32-bit RISC/Vector CPU implementing the MRISC32 ISA | MRISC32 | VHDL |
| NEO430 | Stephan Nolting | Yes | Wishbone (Avalon, AXI4-Lite) | 16-bit MSP430 ISA-compatible, very small size, many peripherals, highly customizable | NEO430 | VHDL |
| Nios, Nios II | Altera | No | Avalon | | Altera Nios II | Verilog |
| OpenRISC | OpenCores | Yes | Wishbone | 32-bit; done in ASIC, Actel, Altera, Xilinx FPGA. | | Verilog |
| SpartanMC | TU Darmstadt / TU Dresden | Yes | Custom (AXI support in development) | 18-bit ISA (GNU Binutils / GCC support in development) | SpartanMC | Verilog |
| SYNPIC12 | Miguel Angel Ajo Pelayo | MIT | | PIC12F compatible, program synthesised in gates | nbee.es | VHDL |
| xr16 | Jan Gray | No | XSOC abstract bus | 16-bit RISC CPU and SoC featured in Circuit Cellar Magazine #116-118 | XSOC/xr16 | Schematic |
| YASEP | Yann Guidon | AGPLv3 | Direct SRAM | 16 or 32 bits, RTL in VHDL & asm in JS, microcontroller subset : ready | yasep.org (Firefox required) | VHDL |
| ZipCPU | Gisselquist Technology | GPLv3 | Wishbone, B4/pipelined | 32-bit CPU targeted for minimal FPGA resource usage | zipcpu.com | Verilog |
| ZPU | Zylin AS | Yes | Wishbone | Stack based CPU, configurable 16/32 bit datapath, eCos support | Zylin CPU | VHDL |
| RISC5 | Niklaus Wirth | Yes | Custom | Running a complete graphical Oberon System including an editor and compiler. Software can be developed and ran on the same FPGA board. | www.projectoberon.com/ | Verilog |