# Selective area epitaxy

Selective area epitaxy is the local growth of epitaxial layer through a patterned amorphous dielectric mask (typically SiO$_2$ or Si$_3$N$_4$) deposited on a semiconductor substrate. Semiconductor growth conditions are selected to ensure epitaxial growth on the exposed substrate, but not on the dielectric mask. SAE can be executed in various epitaxial growth methods such as molecular beam epitaxy (MBE), metalorganic vapour phase epitaxy (MOVPE) and chemical beam epitaxy (CBE). By SAE, semiconductor nanostructures such as quantum dots and nanowires can be grown to their designed places.

## Concepts
### Mask

The mask used in SAE is usually amorphous dielectric such as SiO2 or SiN4 which is deposited on the semiconductor substrate. The patterns (holes) in the mask are fabricated using standard microfabrication techniques lithography and etching. Variety of lithography and etching techniques can be implemented to SAE mask fabrication. Suitable techniques depend on the pattern feature size and used materials. Electron beam lithography is widely used due to its nanometer resolution. The mask should withstand the high temperature growth conditions of semiconductors in order to limit the growth to the patterned holes in the mask.

### Selectivity

Selectivity in SAE is used to express the growth on the mask. The selectivity of the growth is originated from the property that atoms don't favor sticking to the mask i.e. they have low sticking coefficient. Sticking coefficient can be reduced by the choice of mask material, having lower material flow and having higher growth temperature. High selectivity i.e. no growth on the mask is desired.

## Growth mechanism

Epitaxial growth mechanism in SAE can be divided in to two parts: Growth before the mask level and growth after the mask level.

### Growth before mask level

Before the mask level, the growth is confined to occur only in the hole in the mask. The growth starts to exceed the crystal of the substrate crystal following the pattern of the mask. The grown semiconductor has the structure of the pattern. This is employed in template assisted selective area epitaxy (TASE), where deep patterns in the mask are used as a template for the whole semiconductor structure and the growth is stopped before the mask level.

### Growth after the mask level

After the mask level, the growth can exceed to any direction, because the mask is no longer limiting the growth direction. The growth continues to the direction which is energetically favorable for crystal to expand in existing growth conditions. The growth is referred as faceted growth, because it is favorable for crystal to form facets. Therefore, in SAE grown semiconductor structures, clear crystalline facets are seen. The growth direction, or more precisely, the growth rates of different crystal facets can be tuned. Growth temperature, V/III ratio, orientation of the pattern and shape of the pattern are properties that affect to the growth rates of facets. By adjusting these properties, the structure of grown semiconductor can be engineered. SAE grown nanowires and epitaxial lateral overgrown structures (ELO) are an example of structures that are engineered by SAE growth conditions. In nanowire growth, the growth rate of lateral facets is suppressed and the structure grows only in vertical direction. In ELO, the growth is initiated in the mask openings, and after mask level the growth proceeds laterally on the mask, eventually joining the grown semiconductor structures together. The main principle in ELO is to reduce the defects caused by lattice mismatch of the substrate and the grown semiconductor.

### Factors that affect to SAE

* Temperature of growth
* V/III ratio
* Choice of mask material
* Orientation of window
* Mask to window ratio
* Quality of mask
* Shape of the pattern

## Techniques

SAE can be achieved in various epitaxial growth techniques, which are listed below.
* Metalorganic vapour-phase epitaxy
* Molecular beam epitaxy
* Chemical beam epitaxy
* Liquid phase epitaxy

## Applications

* Nanowires
* Quantum dots
* III/V-Silicon integration
* Topological quantum computer