# Burroughs Scientific Processor

The Burroughs Scientific Processor, or BSP, was a one-off supercomputer built by Burroughs Corporation that combined features from the early massively parallel computer PEPE with a high-performance gather/scatter system. The system used a single Control Processor that fed instructions to a Parallel Processor with sixteen units. Its peak performance was about 50 million floating point operations per second (50 MFLOPS), and real-world performance was over 20 MFLOPS, almost the same as the real-world performance of a Cray-1.
Development began in 1973, shortly after Burroughs began building the PEPE machine for the US Army. PEPE was designed to be a much larger machine with up to 288 processors, allowing it to track every visible nuclear warhead launched from the Soviet Union in an all-out ICBM attack. The BSP was essentially a version of the PEPE system scaled down to smaller sizes. When it was announced, the 50 MFLOPS speed of the BSP would make it among the fastest machines in the world, but it was simpler than the other high-end designs. The prototype was delivered in 1978, by which time new machines like the Cray-1 had shipped, and there were no sales for the BSP.

## Description

The system consisted of a single central processing unit known as the Control Processor (CP) and a Parallel Processor consisting of sixteen Arithmetic Elements. The Elements are similar to a modern floating point unit (FPU) although they also contained some logic that would normally be part of the arithmetic logic unit (ALU). The CP read instructions from memory and either performed them locally in some cases or routed them to the Elements, which all had to perform the same operation at any given cycle. In modern terminology, the BSP is a SIMD machine, as it has a single instruction running on multiple data. At the time, this concept was known as an "array processor".
BSP was based on a 48-bit word, which was at that time a popular choice for scientific computers as a single computer word contained enough bits that a single precision value was still useful for many calculations. It also was a good choice for systems that had to support older code, because a single word could cleanly store six ASCII or eight six-bit character codes.
The system was memory-memory, meaning that instructions read operands from memory and stored results back to memory. This contrasts with most high-performance designs of the era (and today), which rely heavily on processor registers to avoid having to deal with main memory whenever possible. The upside to the memory-memory approach is that it allows vectors to be any length, whereas in a register-register machine like the Cray-1, the vectors have to be loaded in parts if they are larger than the register set. In order for this solution to work in a supercomputing application, the memory must be very fast. The concept trades off complexity in the instruction decoding and running, which is simplified, for complexity in the memory system.
The BSP solved the memory performance problem by splitting storage across independent memory units, which could be read or written in parallel. Any processor could access any bank at any time, and as long as the data was spread across them, they could do so at the same time. To increase the likelihood this would happen, the memory was split into seventeen modules, the smallest prime number greater than the sixteen Elements, which would spread arrays across the modules unless the array length happened to be 17. Data was moved to and from main memory using a 16 x 17 crossbar switch, which could move sixteen 48-bit words every 160 nS, giving a throughput of 100 MW per second. Most operations on the Elements required two cycles, so peak performance was 50 MFLOPS.
Other machines of the era, notably the TI ASC and CDC Star-100, worked in a fashion similar to the BSP, being memory-to-memory machines. Both were also quite slow in real-world tests. These machines suffered from long setup times for the vectors, which required a number of machine cycles to decode and load the processor pipeline that drove the vector unit. In contrast, BSP loaded the setup into the crossbar and ran, part of a short five-stage pipeline. This allowed it to work well on shorter vectors, whereas the other machines only worked well when the vectors were large enough that the pipeline speed could overcome the setup time.
Even by standards of the early 1970s, the BSP's 160 ns cycle time, corresponding to 14 MHz, was not particularly fast. The designers believed that the slower speed would be made up by the parallel processing and the lack of waiting for memory. In theory, the system would run the same speed as a 224 MHz single-PP machine, making it competitive with the fastest machines of the era. As the designer J.H. Austin noted "Simply put, the clock frequency does not indicate how fast a machine runs, just how often it stops!" For comparison, the Cray-1, first delivered in 1976, ran at 80 MHz.
Further improvement in throughput was achieved with a separate File Memory, a dedicated high-speed storage system that acted as a cache for the various mass storage devices. It was based on early semiconductor-based random access memory (RAM) with a 12.5 MW transfer speed. Each memory unit held 16 MW, and a single machine could hold four for a total of 64 MW. In order for the system to keep up with the 50 MFLOP processing speed, input/output instructions had to occur at a maximum of once in five operations. This was well within the real-world mix which was often 100-to-1.
The first pre-production machine was finally ready in 1978, after five years of development, by which time the Cray-1 had been shipping for over a year. Burroughs decided to cancel development in 1979, having failed to find any customers. The global memory pool was a novel feature and led to significant market interest, but the cost of implementing the switching system was so high that later machines did not use this architecture.