# OpenRISC

OpenRISC is a project to develop a series of open-source hardware based central processing units (CPUs) on established reduced instruction set computer (RISC) principles. It includes an instruction set architecture (ISA) using an open-source license. It is the original flagship project of the OpenCores community.
The first (and as of 2019 only) architectural description is for the OpenRISC 1000 ("OR1k"), describing a family of 32-bit and 64-bit processors with optional floating-point arithmetic and vector processing support. The OpenRISC 1200 implementation of this specification was designed by Damjan Lampret in 2000, written in the Verilog hardware description language (HDL). The later mor1kx implementation, which has some advantages compared to the OR 1200, was designed by Julius Baxter and is also written in Verilog. Software simulators also exist which implement the OR1k specification.
The hardware design was released under the GNU Lesser General Public License (LGPL), while the models and firmware were released under the GNU General Public License (GPL).
A reference system on a chip (SoC) implementation based on the OpenRISC 1200 was developed, named the OpenRISC Reference Platform System-on-Chip (ORPSoC). Several groups have demonstrated ORPSoC and other OR1200 based designs running on field-programmable gate arrays (FPGAs), and there have been several commercial derivatives produced.
Later SoC designs, also based on an OpenRisc 1000 CPU implementation, are minSoC, OpTiMSoC and MiSoC.

## Instruction set

The instruction set is a reasonably simple traditional RISC architecture reminiscent of MIPS using a 3-operand load-store architecture, with 16 or 32 general-purpose registers and a fixed 32-bit instruction length. The instruction set is mostly identical between the 32- and 64-bit versions of the specification, the main difference being the register width (32 or 64 bits) and page table layout. The OpenRISC specification includes all features common to modern desktop and server processors: a supervisor mode and virtual memory system, optional read, write, and execute control for memory pages, and instructions for synchronizing and interrupt handling between multiple processors.
Another notable feature is a rich set of single instruction, multiple data (SIMD) instructions intended for digital signal processing.

## Implementations

Most implementations are on field-programmable gate arrays (FPGAs) which give the possibility to iterate on the design at the cost of performance.
By 2018, the OpenRISC 1000 was considered stable, so ORSoC (owner of OpenCores) began a crowdfunding project to build a cost-efficient application-specific integrated circuit (ASIC) to get improved performance. ORSoC faced criticism for this from the community. The project did not reach the goal.
As of May 2024, no open-source ASIC had been produced.

### Commercial implementations

Several commercial organizations have developed derivatives of the OpenRISC 1000 architecture, including the ORC32-1208 from ORSoC and the BA12, BA14, and BA22 from Beyond Semiconductor. Dynalith Systems provide the iNCITE FPGA prototyping board, which can run both the OpenRISC 1000 and BA12. Flextronics (Flex) and Jennic Limited manufactured the OpenRISC as part of an application-specific integrated circuit (ASIC). Samsung uses the OpenRISC 1000 in their DTV system-on-chips (SDP83 B-Series, SDP92 C-Series, SDP1001/SDP1002 D-Series, SDP1103/SDP1106 E-Series). Allwinner Technology are reported to use an OpenRISC core in their AR100 power controller, which forms part of the A31 ARM-based SoC.
Cadence Design Systems have begun using OpenRISC as a reference architecture in documenting tool chain flows (for example the UVM reference flow, now contributed to Accellera).
TechEdSat, the first NASA OpenRISC architecture based Linux computer launched in July 2012, and was deployed in October 2012 to the International Space Station with hardware provided, built, and tested by ÅAC Microtec and ÅAC Microtec North America.

### Academic and non-commercial use

Being open source, OpenRISC has proved popular in academic and hobbyist circles. For example, Stefan Wallentowitz and his team at the Institute for Integrated Systems at the Technische Universität München have used OpenRISC in research into multi-core processor architectures. The Open Source Hardware User Group (OSHUG) in the UK has on two occasions run sessions on OpenRISC, while hobbyist Sven-Åke Andersson has written a comprehensive blog on OpenRISC for beginners, which attracted the interest of Electronic Engineering Times (EE Times). Sebastian Macke has implemented jor1k, an OpenRISC 1000 emulator in JavaScript, running Linux with X Window System and Wayland support.

## Toolchain support

The OpenRISC community have ported the GNU toolchain to OpenRISC to support development in the programming languages C and C++. Using this toolchain the newlib, uClibc, musl (as of release 1.1.4), and glibc libraries have been ported to the processor. Dynalith provides OpenIDEA, a graphical integrated development environment (IDE) based on this toolchain. A project to port LLVM to the OpenRISC 1000 architecture began in early 2012.
GCC 9 released with OpenRISC support.
The OR1K project provides an instruction set simulator, or1ksim. The flagship implementation, the OR1200, is a register-transfer level (RTL) model in Verilog HDL, from which a SystemC-based cycle-accurate model can be built in ORPSoC. A high speed model of the OpenRISC 1200 is also available through the Open Virtual Platforms (OVP) initiative (see OVPsim), set up by Imperas.

## Operating system support
### Linux support

The mainline Linux kernel gained support for OpenRISC in version 3.1. The implementation merged in this release is the 32-bit OpenRISC 1000 family (or1k). Formerly OpenRISC 1000 architecture, it has been superseded by the mainline port.

### RTOS support

Several real-time operating systems (RTOS) have been ported to OpenRISC, including NuttX, RTEMS, FreeRTOS, and eCos.

## QEMU support

Since version 1.2, QEMU supports emulating OpenRISC platforms.