# IBM System/4 Pi

The IBM System/4 Pi is a family of avionics computers used, in various versions, on the F-15 Eagle fighter, E-3 Sentry AWACS, Harpoon Missile, NASA's Skylab, MOL, and the Space Shuttle, as well as other aircraft. Development began in 1965, deliveries in 1967. They were developed by the IBM Federal Systems Division and produced by the Electronics Systems Center in Owego, NY.
It descends from the approach used in the System/360 mainframe family of computers, in which the members of the family were intended for use in many varied user applications. (This is expressed in the name: there are 4π steradians in a sphere, just as there are 360 degrees in a circle.) Previously, custom computers had been designed for each aerospace application, which was extremely costly.

## Early models

In 1967, the System/4 Pi family consisted of these basic models:
Specifications :
| Model | ISA (instructions) | Performance (IPS) | Weight (pounds) |
| TC | 54 | 48,500 | 17.3 pounds (7.8 kg) |
| CP | 36 | 91,000 | 80 pounds (36 kg) |
| CP-2 | 36 | 125,000 | 47 pounds (21 kg) |
| EP | 70 | 190,000 | 75 pounds (34 kg) |
* Model TC (Tactical Computer) - A briefcase-size computer for applications such as missile guidance, helicopters, satellites and submarines.
* Model CP (Customized Processor/Cost Performance) - An intermediate-range processor for applications such as aircraft navigation, weapons delivery, radar correlation and mobile battlefield systems.
** Model CP-2 (Cost Performance - Model 2)
* Model EP (Extended Performance) - A large-scale data processor for applications requiring real-time processing of large volumes of data, such as crewed spacecraft, airborne warning and control systems and command and control systems. Model EP used an instruction subset of IBM System/360 (Model 44) - user programs could be checked on System/360
The Skylab space station employed the model TC-1, which had a 16-bit word length and 16,384 words of memory with a custom input/output assembly. Skylab had two, redundant, TC-1 computers: a prime (energized) and a backup (non energized.) There would be an automatic switchover (taking on the order of one second) to the backup in the event of a critical failure of the prime. A total of twelve were delivered to NASA by 1972. Two were flown on Skylab in 1973-1974; the others were used for testing and mission simulators. The software management effort was led by Harlan Mills and Fred Brooks. The Skylab flight software development process incorporated many lessons learned during the IBM System/360 Operating System project, as described in Brooks' 1975 book The Mythical Man-Month.

## Advanced Processor

The AP-101, being the top-of-the-line of the System/4 Pi range, shares its general architecture with the System/360 mainframes. It is a repackaged version of the IBM Advanced Processor-1 (AP-1) used in the F-15 fighter. The AP-1 prototypes were delivered in 1971 and the AP-101 in 1973. It has 16 32-bit registers. Originally only 16 bits were available for addressing memory; later this was extended with four bits from the program status word register, allowing a directly addressable memory range of 1M locations. This avionics computer has been used in the U.S. Space Shuttle, the B-52 and B-1B bombers, and other aircraft. It remained in service on the Space Shuttle because it worked, was flight-certified, and developing a new system would have been too expensive.
There were a number of variants of the AP101. The Offensive Avionics System, a retrofit update of the B-52, contains two AP-101C computers. The AP-101C prototypes were delivered in 1978. The B-1B employs a network of eight model AP-101F computers. The Space Shuttle used two variants of the AP-101: the earlier AP-101B and the upgraded AP-101S. The AP-101B was used for a series of Approach and Landing Tests in 1977. The first ascent to orbit was in 1981. The AP-101S first launched in 2000.
Each AP-101 on the Shuttle was coupled with an input-output processor (IOP), consisting of one Master Sequence Controller (MSC) and 24 Bus Control Elements (BCEs). The MSC and BCEs executed programs from the same memory system as the main CPU, offloading control of the Shuttle's serial data bus system from the CPU. The AP-101B originally used in the Space Shuttle had magnetic-core memory. The upgrade to the AP-101S in the early 1990s replaced the core with semiconductor memory and reduced the size from two to one chassis. It was augmented by glass cockpit technology. Both variants use a microprogram to define the instruction set architecture. The early AP-101 variants used IBM'S Multipurpose Midline Processor (MMP) architecture. The AP-101B microprogram implemented MMP with 154 instructions. The AP101S could operate with a backwards compatible MMP with 158 instructions or the MIL-STD-1750A architecture with 243 instructions. It was based on the AP-101F used in the B-1B. The AP-101S/G was an interim processor. The AP-101B performance was 0.420 MIPS, while the AP-101S was 1.27 MIPS. James E. Tomayko, who was contracted by NASA to write a history of computers in spaceflight, has said:
   "It was available in basically its present form when NASA was specifying requirements for the shuttle contracts in the 1970s. As such, it represents the first manned spacecraft computer system with hardware intentionally behind the state of the art."
The Space Shuttle used five AP-101 computers as General-Purpose Computers (GPCs). Four operated in sync, for redundancy, while the fifth was a backup running software written independently. The Shuttle's guidance, navigation and control software was written in HAL/S, a special-purpose high-level programming language, while much of the operating system and low-level utility software was written in assembly language. AP-101s used by the US Air Force are mostly programmed in JOVIAL, such as the system found on the B-1B bomber.
The AP-102 variant design began in 1984. It is a MIL-STD-1750A standard instruction set architecture. It was first used in the F-117A Nighthawk. It was upgraded to the AP-102A in the early 1990s.