# ETRAX CRIS

The ETRAX CRIS is a RISC ISA and series of CPUs designed and manufactured by Axis Communications for use in embedded systems since 1993. The name is an acronym of the chip's features: Ethernet, Token Ring, AXis - Code Reduced Instruction Set. Token Ring support has been taken out from the latest chips as it has become obsolete.

## Types of chips

The CGA-1 (Coax Gate Array) was the first microprocessor developed by Axis Communications. It contains IBM 3270 (coax) and IBM 5250 (Twinax) communications. The chip has a microcontroller and various I/O's such as serial and parallel. The CGA-1 chip was designed by Martin Gren and Staffan Göransson.

### ETRAX

* In 1993, Axis developed the ETRAX-1 Ethernet Controller, which has 10 Mbit/s Ethernet and Token Ring controllers.
* In 1995, Axis introduced the ETRAX-4 SoC which contains a Ethernet Controller, CPU, Memory Interface, SCSI controller, and parallel and serial I/O.
* In 1997, Axis introduced the ETRAX 100 SoC which features a 10/100 Mbit/s Ethernet Controller, ATA controller, and Wide SCSI controller. The chip introduced on-chip unified instruction and data cache along with direct memory access.

### ETRAX 100LX

In 2000, Axis Introduced the ETRAX 100LX SoC which features a MMU, USB controller, and SDRAM interface. The CPU is capable of 100 MIPS. The chip is able to run the Linux kernel without modifications except for low-level support. The chip's maximum TDP is 0.35 Watts. As of Linux kernel 4.17, the architecture has been dropped due to being obsolete.
Specifications:
* 32-bit RISC CPU core
* 10/100 Mbit/s Ethernet controller
* 4 asynchronous serial ports
* 2 synchronous serial ports
* 2 USB ports
* 2 Parallel ports
* 4 ATA (IDE) ports
* 2 Narrow SCSI ports (or 1 Wide)
* Support for SDRAM, Flash, EEPROM, SRAM

### ETRAX 100LX MCM

The ETRAX 100LX MCM is based on the ETRAX 100 LX. The chip has internal flash memory, SDRAM, and an Ethernet PHYceiver. The Chip can come with 2 MB flash and 8 MB SDRAM or 4 MB flash and 16 MB SDRAM.

### ETRAX FS

Introduced in 2005 with full Linux 2.6 support, the chip features:
* A 200 MIPS 32-bit RISC CRIS CPU core with 16 kB instruction and data cache
* 128 kB on-chip RAM
* Two 10/100 Mbit/s Ethernet controllers
* Crypto accelerator supporting AES, DES, Triple DES, SHA-1, and MD5
* I/O processor supporting PC-Card, PCI, USB, SCSI and ATA

### ARTPEC

The Axis Real-Time Picture Encoder Chip (ARTPEC) is a system on a chip (SoC) developed by Axis Communications. There are currently eight generations of the chip, all of which run AXIS OS, a modified version of Linux designed for embedded devices. Not all products developed by Axis Communications use its custom chip. The chip is typically found in high-performance devices such as higher-end cameras, while lower-cost devices use SoCs from Ambarella.
The ARTPEC-1 ASIC is the first ASIC designed in-house by Axis Communications for Network Video. Initial development began in 1996 to support hardware compression and encoding of video. At the time processors were not available for network video. Its internal firmware is based on an embedded operating system called μClinux which became known as Embedded Linux.
The ARTPEC-2 SoC released in 2003, is based on the ETRAX CRIS architecture. Unlike ARTPEC-1 which relies on an external CPU, ARTPEC-2 has an internal ETRAX CPU which improves power efficiency and performance. The SoC has a MPEG-4 encoder and decoder which reduces bandwidth when streaming and recording video.
The ARTPEC-3 SoC released in 2007, is based on the ETRAX CRIS architecture. This is the first SoC developed by Axis which supports the H.264 standard for video encoding. The image processing pipeline is capable of capturing a 1080P video source at 30 frames per second.
The ARTPEC-4 SoC released in 2011, has a single-core multi-threaded MIPS CPU (34Kc). The image processing pipeline is based on ETRAX CRIS. The SoC has Lightfinder, a technology which allows a camera to see color in challenging light conditions and P-Iris which reduces lens refraction.
The ARTPEC-5 SoC released in 2013, has a dual-core MIPS CPU (1004Kf) with dual hardware threads and support for Symmetric multiprocessing. The image processing pipeline is based on ETRAX CRIS. The chip actively increases forensic details in a scene via a technology called Forensic Capture and lowers bandwidth while preserving forensic details in an image via a technology called Zipstream.
The ARTPEC-6 SoC released in 2017, is powered by an ARM Cortex-A9 CPU. The image processing pipeline is based on ETRAX CRIS. The SoC is capable of capturing 4K video at 30 frames per second. The chip actively increases forensic details in a scene via a technology called Forensic WDR and runs video analytics.
The ARTPEC-7 SoC released in 2019, is powered by an ARM Cortex-A9 CPU. The image processing pipeline is based on ETRAX CRIS. This is the first SoC developed by Axis which supports the H.265 standard for video encoding. ARTPEC-7 has features such as secure boot which prevents booting of unauthorized firmware, improvements in low light imaging via Lightfinder 2.0, and a machine learning processor.