# Montecito (processor)

Montecito is the code-name of a major release of Intel's Itanium 2 Processor Family (IPF), which implements the Intel Itanium architecture on a dual-core processor. It was officially launched by Intel on July 18, 2006, as the "Dual-Core Intel Itanium 2 processor". According to Intel, Montecito doubles performance versus the previous, single-core Itanium 2 processor, and reduces power consumption by about 20%. It also adds multi-threading capabilities (two threads per core), a greatly expanded cache subsystem (12 MB per core), and silicon support for virtualization.

## Architectural features and attributes

* Two cores per die
* 2-way coarse-grained multithreading per core (not simultaneous). Montecito-flavour of multi-threading is dubbed temporal, or TMT. This is also known as switch-on-event multithreading, or SoEMT. The two separate threads do not run simultaneously, but the core switches thread in case of a high latency event, like an L3 cache miss which would otherwise stall execution. By this technique, multi-threaded workloads, including database-like workloads, should improve by 15-35%.
* a total of 4 threads per die
* separate 16 KB Instruction L1 and 16 KB Data L1 cache per core
* separate 1 MB Instruction L2 and 256 KB Data L2 cache per core, improved hierarchy
* 12 MB L3 cache per core, 24 MB L3 per die
* 1.72 billion transistors per die, which is added up from:
** core logic — 57M, or 28.5M per core
** core caches — 106.5M
** 24 MB L3 cache — 1550M
** bus logic & I/O — 6.7M
* Die size is 27.72 mm × 21.5 mm, or 596 mm$^2$
* 90 nanometer design
* Lower power consumption and thermal dissipation than earlier flagship Itaniums, despite the high transistor count; 75-104 W. This is mainly achieved by applying different types of transistors. By default, slower and low-leakage transistors were used, while high-speed, thus high-leakage ones where it was necessary.
* Advanced compensation for errors in cache, for reliable operation under mission-critical workloads. This was code-named Pellston technology during development, and has recently been renamed Intel Cache Safe Technology.
* Virtualization technology allowing multiple OS instances per chip. This was known as Silvervale technology during development, and is now called Intel Virtualization Technology.
* Improved, higher bandwidth front side bus (FSB), with three times the capacity of the existing bus design. It is meant to be at system level (per node, with 4 dies). System throughput per node should be at least 21 GB/s, which suggest dual 333.333 MHz (double pumped, resulting 2×667 effective MHz) front side bus. However, it is up to system integrators how they organize their bus topology.
* All Montecito processors support 533 MHz / 400 MHz FSB speed.
* Also available with legacy FSB for upgrading existing system designs.
* Eliminates the hardware-based x86 instruction emulation circuitry, in favor of the more efficient software-based IA-32 Execution Layer.
On October 25, 2005, Intel announced that the first dual-core Itanium processor would be delayed until "the middle of next year." Archived 2008-05-16 at the Wayback Machine Montecito was launched on July 18, 2006. Due to unspecified issues, Intel's Foxton power management technology was disabled in the first release of Montecito, and the front-side bus frequency was reduced to 267 MHz (533.333 MHz effective) instead of the 333 MHz speed originally scheduled for the design [3].
At the time of launch, the following models and pricing were available:
* Itanium 2 9050 1.60 GHz / 24 MB L3 — $3,692
* Itanium 2 9040 1.60 GHz / 16 MB L3 — $1,980
* Itanium 2 9030 1.60 GHz / 8 MB L3 — $1,552
* Itanium 2 9020 1.42 GHz / 12 MB L3 — $910
* Itanium 2 9015 1.40 GHz / 12 MB L3 — $749
* Itanium 2 9010 1.60 GHz / 6 MB L3 / single core — $696
There are no plans for additional Montecito processors; the successor, Montvale was released in late 2007.

## Successors

See Itanium future processors