# Multiclet

MultiClet is an ongoing innovation project for a microprocessor that became the first post von Neumann, multicellular microprocessor, breaking the paradigm for computing technology that has been in place for more than 60 years. There have been attempts in the past to shift away from the von Neumann architecture. Under MultiClet, a 4-cellular dynamically reconfigurable microprocessor is implemented.

## History

* In April 2013, the Russian company Sputnix signed an agreement for joint development of the MultiClet microprocessor.
* In January 2014, an announcement was made that the FreeRTOS operating system be ported to the MultiClet microprocessor, this demonstrates that the microprocessor potentially can perform tasks that makes it suitable for real products.
* In April 2014, the Kickstarter project Key_P1 MultiClet: Your Powerful Digital Guardian, failed to raise sufficient funding.
* Since June 2014, the MultiClet microprocessor has been reportedly under test in real space conditions onboard Sputnix’s microsatellite TabletSat-Aurora.
* In March 2014, Multiclet present first multicellular dynamically reconfigurable microprocessor in Inatronics 2014.

## Financing

Since 2004, more than 300 million roubles have been provided for the project by the Danish venture fund Symbion Capital and the Bortnik Fund. In 2009, there was an unsuccessful request for co-financing by Rusnano. In 2010, it was reported that more than 1 billion roubles would be needed in total before any actual production could take place. In 2011, the MultiClet company, currently responsible for the development of the microprocessor was founded with a capital of 323 million roubles.
In August 2014, a financial request for 80 million US dollars from the Russian-Chinese Investment Fund (RKIF) was made in order to develop a MultiClet based computer.

## Technical concept

As opposed to the traditional multi-core processor architecture each individual cell in the microprocessor can communicate with each other, without the need to store intermediate results in memory registers. This removes the concept of assembly language instructions with sequential dependence, in favor of realizing a high level programming language directly on the computer hardware. The smallest indivisible unit is a set of instructions described in the triadic language. Each triad can describe an operation between references to other triads, rather than references to the current contents in memory registers. The result of the sequence of triads is evaluated when selected, e.g. when an operation to write the result to a memory register is issued.

## Potential benefits

The multicellular microprocessor architecture makes it easier to perform parallel execution because the need to access intermediate memory for each operation is eliminated, thus each cell can operate independently until the result is needed. The microprocessor can operate with reduced performance if one or more of the microprocessor cells become non-functioning. The dynamic reconfiguration of the microprocessor, in case of permanent failures makes it ideal for operation under harsh conditions such as in space applications.
Realization of all operations within each statement, without memory involvement improves computing power by 4–5 times and reduces the microprocessor energy consumption by up to 10 times.

## Criticism

In July 2012, a critical view was posted on a forum which discusses potential challenges related to scaling of the technology. The main obstacle would be the high level of communication required between the different cells of the multicellular architecture and its implementation using CMOS semiconductor process technology below 180 nanometer.

## Variants

Available and suggested multicellular processor variants:
| Type | Description |
| P | high Рerformance and simultaneous reduction of power consumption |
| C | ultra-low power Consumption and high performance |
| R | dynamic Reconfiguration |
| L | Liveness, fault tolerance |

## Models

Available multicellular processor models:
| Article | Cells | Clock frequency | Type | Process | Year | Manufacturer |
| MCp041P100104 | 4 | 120 MHz | P1 | 180 nanometer | 2013 | SilTerra Malaysia |
| MCp0411100101 | 4 | 120 MHz | P1 | 180 nanometer | 2013 | SilTerra Malaysia |
| MCp042R100102 | 4 | 80 MHz | R1 | 180 nanometer | 2014 | SilTerra Malaysia |

## In design

* Variants currently in design
* 4-cell microprocessor of the L variant
* 16-cell microprocessor for audio and video applications, using a 45 nanometer CMOS manufacturing process
* 64-cell microprocessor for supercomputers, using a 22 nanometer CMOS manufacturing process