# Motorola 68060

The Motorola 68060 ("sixty-eight-oh-sixty") is a 32-bit microprocessor from Motorola released in April 1994. It is the successor to the Motorola 68040 and is the highest performing member of the 68000 series. Two derivatives were produced, the 68LC060 and the 68EC060.

## Architecture

There is an LC (Low-Cost) version, without an FPU and EC (Embedded Controller), without MMU and FPU. The 68060 design was led by Joe Circello.
The 68060 shares most architectural features with the P5 Pentium. Both have a very similar superscalar in-order dual instruction pipeline configuration, and an instruction decoder which breaks down complex instructions into simpler ones before execution, described publicly as "two four-stage RISC engines [that] execute the fixed-format instructions emitted by the instruction converter". However, a significant difference is that the 68060 FPU is not pipelined and is therefore up to three times slower than the Pentium in floating point applications. In contrast to that, integer multiplications and bit shifting instructions are significantly faster on the 68060. The 68060 has the ability to execute simple instructions in the address generation unit (AGU) and thereby supply the result two cycles before the ALU. In the development of the 68060, large amounts of commercial compiled code were analyzed for clues as to which instructions would be the best candidates for performance optimization.
Against the Pentium, the 68060 can perform better on mixed code; Pentium's decoder cannot issue an FP instruction every opportunity and hence the FPU is not superscalar as the ALUs were. If the 68060's non-pipelined FPU can accept an instruction, it can be issued one by the decoder. This means that optimizing for the 68060 is easier: no rules prevent FP instructions from being issued whenever was convenient for the programmer other than well understood instruction latencies. However, with properly optimized and scheduled code, the Pentium's FPU is capable of double the clock for clock throughput of the 68060's FPU.
The 68060 is the last development of the 68000 family for general purpose use, abandoned in favor of the PowerPC chips. It saw use in some late-model Amiga machines and Amiga accelerator cards as well as some Atari ST clones and Falcon accelerator boards (CT60/CT63/CT60e, the latter of which was created in 2015), and very late models of the Alpha Microsystems multiuser computers before their migration to x86, but Apple Inc. and the Unix world had moved onto various RISC platforms by the time the 68060 was available. Apple had already announced its adoption of PowerPC, developed by IBM and Motorola, prior to the availability of the 68060. Upon introduction of low-power variants of the 68040 and other devices, Motorola anticipated that Apple might leave a space in its product range for 68060-based products, giving the company "a high performance hedge in case the transition to RISC proves problematic": a situation that did not transpire.
The 68060 was introduced at 50 MHz on Motorola's 0.6 μm manufacturing process. A few years later it was shrunk to 0.42 μm and clock speed raised to 66 MHz and 75 MHz. Some users managed to overclock rev6. 68060 CPU-s (mask: 71E41J) up to 120 or 133 MHz. Motorola projected a performance of around three-and-a-half times that of a 25 MHz 68040 at the initial clock rate of 50 MHz for the 68060, this described as being "about 77 MIPS", later adjusting such claims to three times the performance of the 68040 for a 68060 running at twice the frequency of the 68040. Benchmarking of the 50 MHz 68060 fitted in accelerator cards for the Commodore Amiga indicated Dhrystone 2.1 benchmark results of around 80,000 Dhrystones per second, this being broadly comparable to a Sun SPARCstation 10 workstation.
Developments of the basic core continue, intended for embedded systems. Here they are combined with a number of peripheral interfaces to reduce the overall complexity and power requirements of a design. A number of chips, each with different sets of interfaces, are sold under the names ColdFire and DragonBall.

## History

Model numbers with even second-to-last digit (68000, 68020, 68040, 68060) were reserved for major revisions to the 680x0 core architecture. Model numbers with odd second-to-last digit (68010, 68030) were reserved for upgrades to the architecture of the previous chip. Motorola never produced a 68050.
For example, the Motorola 68010 (and the obscure 68012) is a 68000 with improvements to the loop instruction and the ability to suspend then continue an instruction in the event of a page fault, enabling the use of virtual memory with the appropriate MMU hardware. There were, however, no major overhauls of the core architecture. Similarly, the Motorola 68030 represents a process improvement on the 68020 with the MMU and a small data cache (256 bytes) moved on-chip. The 68030 was released in speed ratings up to 50 MHz.
The jump from the 68000/68010 to the 68020/68030, however, represents a major overhaul, with innumerable individual changes.
By the time the 68060 was in production, Motorola had abandoned development of the 68000 family in favor of the PowerPC. The 68060 is the last 68000 family processor from Motorola.
Signetics (Philips) produced a 68000-based variant that they somewhat confusingly named the 68070. It contains a modestly-improved 68000 CPU, a simple on-chip MMU and an I²C bus controller. It came out long before the 68060 and was used principally as an embedded processor in some consumer electronics items, notably CD-i consoles.

## Usage

Chyron's iNFiNiT!, Max!, and Maxine! series of television character generators use the 68060 as the main processor. These character generators were a fixture on many American television networks' affiliate stations.
In desktops, the 68060 is used in some variants of the Amiga 4000T produced by Amiga Technologies, and available as a third party upgrade for other Amiga models. It is also used in the Amiga clone DraCo non-linear video system.
The Q60 extended the Sinclair QL design similarly from the slowest start to the ultimate pace of the 68K architecture's capabilities; these 68060-based motherboards—at 66 MHz for the full 68060 or a non-FPU 68LC060 option overclocked to 80 MHz—are more than 100 times faster than the Sinclair QL while running the same operating systems.
The 68060 was used in Nortel Meridian 1 Option 51, 61 and 81 large office PBX systems, powering the CP3 and CP4 core processor boards. A pair of these boards each sporting a 68060 could be used to make the PBX fault tolerant. This was a logical application as previous Meridian 1 cores used other Motorola chips. Nortel later changed the architecture to use Intel processors.
The Motorola Vanguard 6560 multiprotocol router uses a 50 MHz 68EC060 processor.
Motorola MVME-17x and Force Computer SYS68K VMEbus systems use a 68060 CPU.
Alpha Microsystems AM-6000, AM-6060, and AM-7000 use a 68060. After Motorola stopped developing newer processors, Alpha Microsystems migrated to x86.

## Variants
### 68EC060

The 68EC060 is a version of the Motorola 68060 microprocessor, intended for embedded controllers (EC). It differs from the 68060 in that it has neither an FPU nor an MMU. This makes it less expensive and it draws less power.

### 68LC060

The 68LC060 is a low cost version of the Motorola 68060 microprocessor with no FPU. This makes it less expensive and it draws less power.

### Feature table

| Variant | MMU | FPU | Max Frequency |
| 68060 | Yes | Yes | 75 MHz or 133 MHz overclocked |
| 68LC060 | Yes | No | 75 MHz or 133 MHz overclocked |
| 68EC060 | No | No | 75 MHz or 133 MHz overclocked |

## Technical data

| CPU clock rate | Officially: 50, 60, 66, 75 MHz Overclocked: 66 (rev1-2), 80 (rev3-4), 110, 120, 133 and 150 MHz (rev5-6) |
| Voltage supply | Vcore 3.3 V I/O 5 V |
| Temperature | −40 °C .. 70 °C (85 °C with the current mask) |
| Logic family | Static CMOS |
| Production process | CMOS 0.6 μm and later 0.42 μm |
| Chip carrier | PGA 206 (compatible with 68040), TBGA 304 31*31*1.7P1.27 |
| Address bus | 32 bit |
| Data bus | 32 bit |
| Instruction set | CISC |
| Cache | 8 KB DCache (4-way associative) 8 KB ICache (4-way associative) 96 byte FIFO Instruction Buffer 256 Entry Branch Cache 64 Entry ATC* MMU Buffer (4-way associative) |
| Register | 10 for Address operations (7 gen., 2 stack, 1 pc) 8 for Data operations 1 for CPU flags (status register) |
| Transistors | ~2,500,000 |
| Performance | ~67 MIPS @ 50 MHz ~88 MIPS @ 66 MHz ~110 MIPS @ 75 MHz ~36 MFlops @ 66 MHz ~160 MIPS @ 120 MHz ~177 MIPS @ 133 MHz (estimate) ~200 MIPS @ 150 MHz (estimate) |
ATC = Address Translation Cache