# Zen (microarchitecture)

Zen is a family of computer processor microarchitectures from AMD, first launched in February 2017 with the first generation of its Ryzen CPUs. It is used in Ryzen (desktop and mobile), Ryzen Threadripper (workstation and high end desktop), and Epyc (server).

## Comparison

| Microarchitecture | Microarchitecture | Microarchitecture | Microarchitecture | Zen | Zen | Zen 2 | Zen 3 | Zen 3 | Zen 4 | Zen 4 | Zen 5 | Zen 5 |
| Microarchitecture variants | Microarchitecture variants | Microarchitecture variants | Microarchitecture variants | Zen | Zen+ | Zen 2 | Zen 3 | Zen 3+ | Zen 4 | Zen 4c | Zen 5 | Zen 5c |
| Fabrication process (nm) | Fabrication process (nm) | Fabrication process (nm) | Fabrication process (nm) | 14 nm | 12 nm | 7 nm | 7 nm | 6 nm | 5 nm | 5 nm | 4 nm | 3 nm |
| Cache | μop | μop | μop | 2K | 2K | 4K | 4K | 4K | 6.75K | 6.75K | | |
| Cache | L1 | Data | Size | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB | 48 KB | 48 KB |
| Cache | L1 | Data | Ways | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 12 | 12 |
| Cache | L1 | Data | Latency | | | | 4–8 | 4–8 | | | | |
| Cache | L1 | Instruction | Size | 64 KB | 64 KB | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB |
| Cache | L1 | Instruction | Ways | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 |
| Cache | L1 | Instruction | Latency | 4–8 | 4–8 | 4–8 | 4–8 | 4–8 | | | | |
| Cache | L1 | TLB | TLB | 512-entry | 512-entry | 512-entry | 1024-entry | 1024-entry | | | | |
| Cache | L2 | L2 | Size | 512 KB/core | 512 KB/core | 512 KB/core | 512 KB/core | 512 KB/core | 1024 KB/core | 1024 KB/core | 1024 KB/core | 1024 KB/core |
| Cache | L2 | L2 | Ways | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 |
| Cache | L2 | L2 | Latency | 17 | 12 | 12 | 12 | 12 | 14 | 14 | | |
| Cache | L2 | L2 | TLB | 1536-entry | 1536-entry | 2048-entry | 2048-entry | 2048-entry | 3072-entry | 3072-entry | | |
| Cache | L3 | L3 | Size (per CCX) | 8 MB | 8 MB | 16 MB | 32 MB | APU-only | 32 MB | 16 MB | 32 MB | 16 MB |
| Cache | L3 | L3 | Ways | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 |
| Cache | L3 | L3 | Latency | 35 | 35 | 40 | 46 | 46 | 50 | 50 | | |
| Max. CPU cores | Max. CPU cores | Max. CPU cores | Max. CPU cores | 32 | 32 | 64 | 64 | 8 | 96 | 128 | 128 | 192 |
| Simultaneous multithreading (SMT) | Simultaneous multithreading (SMT) | Simultaneous multithreading (SMT) | Simultaneous multithreading (SMT) | | | | | | | | | |
| OoO window (ROB) | OoO window (ROB) | OoO window (ROB) | OoO window (ROB) | 192 | 192 | 224 | 256 | 256 | 320 | 320 | 448 | 448 |
| Pipeline | Stages | Stages | Stages | 19 | 19 | 19 | | | | | | |
| Pipeline | Decode (ways) | Decode (ways) | Decode (ways) | 4 | 4 | | | 6 | 6 | | | |
| Scheduler | Scheduler | Scheduler | Entries | | | | | | | | | |
| Scheduler | Scheduler | Scheduler | Dispatch | 6 | 6 | | | | | | | |
| Register file | Register file | Register file | Integer | 168 | 168 | 180 | 192 | 192 | 224 | 224 | 240 | 240 |
| Register file | Register file | Register file | Floating-point | 160 | 160 | 160 | 160 | 160 | 192 | 192 | 384 | 384 |
| Queue | Queue | Queue | Instruction | 72 | 72 | | | | | | | |
| Queue | Queue | Queue | Allocation | 44 | 44 | | | | | | | |
| AGUs | AGUs | AGUs | AGUs | 2 | 2 | 3 | 3 | | | | 4 | 4 |

## History
### First generation

The first generation Zen was launched with the Ryzen 1000 series of CPUs (codenamed Summit Ridge) in February 2017. The first Zen-based preview system was demonstrated at E3 2016, and first substantially detailed at an event hosted a block away from the Intel Developer Forum 2016. The first Zen-based CPUs reached the market in early March 2017, and Zen-derived Epyc server processors (codenamed "Naples") launched in June 2017 and Zen-based APUs (codenamed "Raven Ridge") arrived in November 2017. This first iteration of Zen utilized GlobalFoundries' 14 nm manufacturing process. Modified Zen-based processors for the Chinese market were also built under the AMD–Chinese joint venture.

#### First generation refresh

Zen+ was first released in April 2018, powering the second generation of Ryzen processors, known as Ryzen 2000 (codenamed "Pinnacle Ridge") for mainstream desktop systems, and Threadripper 2000 (codenamed "Colfax") for high-end desktop setups. Zen+ used GlobalFoundries' 12 nm process, an enhanced version of their 14 nm node.

### Second generation

The Ryzen 3000 series CPUs were released on July 7, 2019, while the Zen 2-based Epyc server CPUs (codename "Rome") were released on August 7, 2019. Zen 2 Matisse products were the first consumer CPUs to use the 7 nm process node, from TSMC. Zen 2 introduced the chiplet based architecture, where desktop, workstation, and server CPUs are all produced as multi-chip modules (MCMs); these Zen 2 products utilise the same core chiplets but are attached to different uncore silicon (different IO dies) in a hub and spoke topology. This approach differs from Zen 1 products, where the same die (Zeppelin) is used in a simple monolithic package for Summit Ridge products (Ryzen 1000 series) or used as interconnected building blocks in an MCM (up to four Zeppelin dies) for first generation Epyc and Threadripper products. For earlier Zen 2 products the IO and uncore functions are performed within this separate IO die, which contains the memory controllers, the fabric to enable core to core communication, and the bulk of uncore functions. The IO die used by Matisse processors is a small chip produced on GF 12 nm, whereas the server IO die utilized for Threadripper and Epyc is far larger. The server IO die is able to serve as a hub to connect up to eight 8-core chiplets, while the IO die for Matisse is able to connect up to two 8-core chiplets. These chiplets are linked by AMD's own second generation Infinity Fabric, allowing a low-latency interconnect between the cores and to IO. The processing cores in the chiplets are organized in CCXs (Core Complexes) of four cores, linked together to form a single eight core CCD (Core Chiplet Die).
Zen 2 also powers a line of mobile and desktop APUs marketed as Ryzen 4000, as well as fourth generation Xbox consoles and the PlayStation 5. The Zen 2 core microarchitecture is also used in the Mendocino APU, a 6 nm system on a chip aimed at mainstream mobile and other energy efficient low power computing products.

### Third generation

Zen 3 was released on November 5, 2020, using a more matured 7 nm manufacturing process, powering Ryzen 5000 series CPUs and APUs (codename "Vermeer" (CPU) and "Cézanne" (APU)) and Epyc processors (codename "Milan"). Zen 3's main performance gain over Zen 2 is the introduction of a unified CCX, which means that each core chiplet is now composed of eight cores with access to 32 MB of L3 cache, instead of two sets of four cores with access to 16 MB of L3 cache each.
On April 1, 2022, AMD released the new Ryzen 6000 series for the laptop, using an improved Zen 3+ architecture, bringing RDNA 2 graphics integrated in a APU to the PC for the first time.
Zen 3 with 3D V-Cache was officially previewed on May 31, 2021. It differs from Zen 3 in that it includes 3D-stacked L3 cache on top of the normal L3 cache in the CCD, providing a total of 96 MB. The first product that uses it, the Ryzen 7 5800X3D, was released on April 20, 2022. The added cache brings an approximately 15% performance increase in gaming applications on average.
Zen 3 with 3D V-Cache for server, codenamed Milan-X, was announced in AMD's Accelerated Data Center Premiere Keynote on November 8, 2021. It brings a 50% increase in select datacenter applications over Zen 3's Milan CPUs while maintaining socket compatibility with them. Milan-X was released on March 21, 2022.

### Fourth generation

Epyc server CPUs with Zen 4, codenamed Genoa, were officially unveiled at AMD's Accelerated Data Center Premiere Keynote on November 8, 2021, and released a year later in November 2022. They have up to 96 Zen 4 cores and support both PCIe 5.0 and DDR5.
Furthermore, Zen 4 Cloud (a variant of Zen 4), abbreviated to Zen 4c, was also announced. Zen 4c is designed to have significantly greater density than standard Zen 4 while delivering greater power efficiency. This is achieved by redesigning Zen 4's core and cache to maximise density and compute throughput. It has 50% less L3 cache than Zen 4 and is not able to clock as high. Bergamo (Epyc 9704 series) has up to 128 Zen 4c cores and is socket-compatible with Genoa. It was released in June 2023. Another server product line that uses Zen 4c cores is Siena (Epyc 8004 series), which has up to 64 cores, uses a different smaller socket and is intended for use cases that favour smaller size, cost, power and thermal footprints over high performance.
Both Zen 4 and Zen 4 Cloud are manufactured on TSMC's 5 nm node.
In addition to the Epyc 9004, 9704 and 8004 server processors (Genoa, Bergamo and Siena respectively), Zen 4 also powers Ryzen 7000 mainstream desktop processors (codenamed "Raphael"), high-end mobile processors (codenamed "Dragon Range") and thin-and-light mobile processors (codenamed "Phoenix"). It also powers the Ryzen 8000 G-series of desktop APUs.

### Fifth generation

Zen 5 was shown on AMD's Zen roadmap in May 2022. It is believed to use TSMC's 4 nm and 3 nm processes. It will power Ryzen 9000 mainstream desktop processors (codenamed "Granite Ridge"), high-end mobile processors (codenamed "Strix Point"), and Epyc 9005 server processors (codenamed "Turin").
Zen 5c is a compact variant of the Zen 5 core, primarily targeted at hyperscale cloud compute server customers.

## Sinkclose vulnerability

On August 9, 2024 a vulnerability termed "Sinkclose" was announced affecting all Zen-based processors to that date. Sinkclose affects the System Management Mode (SMM). It can only be exploited by first compromising the operating system kernel. Once effected, it is possible to avoid detection by antivirus software and even compromise a system after the operating system has been re-installed. AMD followed up with patches to be released on August 20, 2024.