# Ian A. Young

Ian A. Young is an Intel engineer. Young is a co-author of 50 research papers, and has 71 patents in switched capacitor circuits, DRAM, SRAM, BiCMOS, x86 clocking, Photonics and spintronics.

## Biography

Born in Melbourne, Australia, Young received his bachelor's and master's degrees in electrical engineering from the University of Melbourne, Australia. He received his PhD in electrical engineering from the University of California, Berkeley in 1978, where he did research on MOSFET switched-capacitor filters.

## Technical career
### Early career, analog MOS integrated circuits and switched capacitor filters

Young obtained his PhD from University of California, Berkeley in 1978, working with David A. Hodges, developing the switched MOS capacitor circuits.

### Intel BiCMOS for Logic and SRAM

Young started at Intel in 1983 with the development of circuits for 1 Mb DRAM in 1 μm CMOS in 1985, and first 64 K SRAM in 1 μm CMOS. This was also the first military qualified SRAM under the VHIC program. At 600 nanometre node, Intel adopted BiCMOS for logic requiring the development of a BiCMOS SRAM for cache and a new family of standard logic circuits. The BiCMOS logic family employed the npn devices in the pull-up path of the BiCMOS gate, to form a low power CMOS logic family with high capacitive drive capability. Intel's BiCMOS technology was enabled by an innovative triple diffused npn transistor. This led to a highly manufacturable low cost process due to minimum number of additional process steps. In contrast, other companies employed BiCMOS to implement emitter-coupled logic for microprocessors, which consumed much more power. The BiCMOS circuits were developed for the Pentium processor family and its follow-on generations, Pentium Pro, Pentium II processor family.

### Pentium era and clock scaling

Young developed a Phase Locked Loop (PLL) based clocking circuit in a microprocessor while working on the 50 MHz Intel 80486 processor design. He subsequently developed the core PLL clocking circuit building blocks used in each generation of Intel microprocessors through the 0.13 μm 3.2 GHz Pentium 4. The successful introduction of GHz clocking contributed to improvements in computing power.
The integration of an on-chip PLL enabled the clock rates to exceed the off chip interconnect I/O rate in DX2. This led to the integration of an on-chip cache, paving the path for the first microprocessor with 1 million transistors.
The clock rate scaling ushered by Intel and AMD ended as the thermal power dissipation of processors reached 100 W/cm^2. By the end of the race for clock speed, the clock rates had increased by a factor of more than 50. Intel subsequently shifted to multi-core era with modified Intel Core architecture and concurrent improvements in cache sizes to take advantage of the continued success of Moore's law.

### Beyond CMOS computing

He is the founding editor-in-chief of IEEE Journal of Exploratory Solid State Computational Devices.

## Awards and honours

* 1992–2005: member of technical program committee of International Solid-State Circuits Conference (ISSCC)
* 1994: December guest editor for the IEEE Journal of Solid-State Circuits (JSSCC)
* 1996: Fellow of Intel (highest technical position at Intel until 2002)
* 1996: April guest editor for JSSCC
* 1997: April guest editor for JSSCC
* 1999: Fellow of IEEE
* 1991–1996: program committee for the Symposium on VLSI Circuits
* 1995–1996: Chair of the technical program committee for the Symposium on VLSI Circuits
* 1997–1998: chairman of the Symposium on VLSI Circuits
* 1997–2003: Digital Subcommittee chair of International Solid-State Circuits Conference (ISSCC)
* 2004: Senior Fellow of Intel (highest technical position at Intel since 2002)
* 2005: Technical Program Committee chairman of the 2005 ISSCC
* 2006–2011: member of administration committee of IEEE Solid-State Circuits Society
* 2008–2010: IEEE Solid State Circuits Society, Distinguished Lecturer
* 2009: International Solid-State Circuits Conference's Jack Raper Award for Outstanding Technology Directions paper
* 2012: Plenary Speaker at IEEE Device Research Conference
* 2013: Guest Editor of IEEE Journal of Selected Topics in Quantum Electronics (JSTQE)
* 2014: Editor-in-Chief of IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

## Selected works

* Young, I.A.; Greason, J.K.; Wong, K.L.. "A PLL clock generator with 5 to 110 MHz of lock range for microprocessors," Solid-State Circuits, IEEE Journal of, vol.27, no.11, pp. 1599–1607, Nov. 1992.
* Young, Ian A., Monte F. Mar, and Bharat Bhushan. "A 0.35 μm CMOS 3–880 MHz PLL N/2 clock multiplier and distribution network with low jitter for microprocessors." Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC, 1997 IEEE International. IEEE, 1997.
* Young, I.A.; Hodges, D.A. "MOS switched-capacitor analog sampled-data direct-form recursive filters," IEEE Journal of Solid-State Circuits, vol.14, no.6, pp. 1020–1033, Dec. 1979
* Young, Ian. A History of the Continuously Innovative Analog Integrated Circuit.
* Young, Ian A., et al. "Optical I/O technology for tera-scale computing." Solid-State Circuits, IEEE Journal of 45.1 (2010): 235–248.
* Muthali, H.S.; Thomas, T.P.; Young, I.A. "A CMOS 10-gb/s SONET transceiver," Solid-State Circuits, IEEE Journal of, vol.39, no.7, pp. 1026– 1033, July 2004.
* Manipatruni, S.; Lipson, M.; Young, I. "Device Scaling Considerations for Nanophotonic CMOS Global Interconnects," IEEE Journal of Selected Topics in Quantum Electronics, vol.PP, no.99, pp. 1.
* D.E. Nikonov, I. A. Young, Overview of Beyond-CMOS Devices and A Uniform Methodology for Their Benchmarking IEDM 2012
* Avci, U.E.; Rios, R.; Kuhn, K.; Young, I.A. "Comparison of performance, switching energy and process variations for the TFET and MOSFET in logic," VLSI Technology (VLSIT), 2011 Symposium on, vol., no., pp. 124,125, 14–16 June 2011.
* Manipatruni, S.; Nikonov. D.E.; Young, Ian."Material Targets for Scaling All-Spin Logic", Phys. Rev. Applied 5, 014002.

## Selected patents

* 5,412,349, PLL clock generator integrated with microprocessor, 5 February 1995
* 5,446,867, Microprocessor PLL clock circuit with selectable delayed feedback, 29 August 1995
* 5,280,605, Clock speed limiter for microprocessor, 18 January 1994
* 6,081,141, Hierarchical Clock Frequency Domains for a Semiconductor Device, 27 June 2000
* 6,512,861, Packaging and assembly method for optical coupling, 28 January 2003
* 6,636,976, Mechanism to Control di/dt for a Microprocessor, 21 October 2003
* 6,075,908 Paniccia, Mario J., Valluri RM Rao, and Ian A. Young. "Method and apparatus for optically modulating light through the back side of an integrated circuit die." 13 June 2000.
* 7,049,704 Chakravorty, K. K., Swan, J., Barnett, B. C., Ahadian, J. F., Thomas, T. P., & Young, I. (2006). US Patent No.
* 6,125,217 Paniccia, M. J., Young, I. A., Thomas, T. P., & Rao, V. R. (2000)