# AMD APU

AMD Accelerated Processing Unit (APU), formerly known as Fusion, is a series of 64-bit microprocessors from Advanced Micro Devices (AMD), combining a general-purpose AMD64 central processing unit (CPU) and 3D integrated graphics processing unit (IGPU) on a single die.
AMD announced the first generation APUs, Llano for high-performance and Brazos for low-power devices, in January 2011. The second generation Trinity for high-performance and Brazos-2 for low-power devices were announced in June 2012. The third generation Kaveri for high performance devices were launched in January 2014, while Kabini and Temash for low-power devices were announced in the summer of 2013. Since the launch of the Zen microarchitecture, Ryzen and Athlon APUs have released to the global market as Raven Ridge on the DDR4 platform, after Bristol Ridge a year prior.
AMD has also supplied semi-custom APUs for consoles starting with the release of Sony PlayStation 4 and Microsoft Xbox One eighth generation video game consoles.

## History

The AMD Fusion project started in 2006 with the aim of developing a system on a chip that combined a CPU with a GPU on a single die. This effort was moved forward by AMD's acquisition of graphics chipset manufacturer ATI in 2006. The project reportedly required three internal iterations of the Fusion concept to create a product deemed worthy of release. Reasons contributing to the delay of the project include the technical difficulties of combining a CPU and GPU on the same die at a 45 nm process, and conflicting views on what the role of the CPU and GPU should be within the project.
The first generation desktop and laptop APU, codenamed Llano, was announced on 4 January 2011 at the 2011 Consumer Electronics Show in Las Vegas and released shortly thereafter. It featured K10 CPU cores and a Radeon HD 6000 series GPU on the same die on the FM1 socket. An APU for low-power devices was announced as the Brazos platform, based on the Bobcat microarchitecture and a Radeon HD 6000 series GPU on the same die.
At a conference in January 2012, corporate fellow Phil Rogers announced that AMD would re-brand the Fusion platform as the Heterogeneous System Architecture (HSA), stating that "it's only fitting that the name of this evolving architecture and platform be representative of the entire, technical community that is leading the way in this very important area of technology and programming development." However, it was later revealed that AMD had been the subject of a trademark infringement lawsuit by the Swiss company Arctic, who used the name "Fusion" for a line of power supply products.
The second generation desktop and laptop APU, codenamed Trinity, was announced at AMD's 2010 Financial Analyst Day and released in October 2012. It featured Piledriver CPU cores and Radeon HD 7000 series GPU cores on the FM2 socket. AMD released a new APU based on the Piledriver microarchitecture on 12 March 2013 for Laptops/Mobile and on 4 June 2013 for desktops under the codename Richland. The second generation APU for low-power devices, Brazos 2.0, used exactly the same APU chip, but ran at higher clock speed and rebranded the GPU as Radeon HD 7000 series and used a new I/O controller chip.
Semi-custom chips were introduced in the Microsoft Xbox One and Sony PlayStation 4 video game consoles, and subsequently in the Microsoft Xbox Series X|S and Sony PlayStation 5 consoles.
A third generation of the technology was released on 14 January 2014, featuring greater integration between CPU and GPU. The desktop and laptop variant is codenamed Kaveri, based on the Steamroller architecture, while the low-power variants, codenamed Kabini and Temash, are based on the Jaguar architecture.
Since the introduction of Zen-based processors, AMD renamed their APUs as the Ryzen with Radeon Graphics and Athlon with Radeon Graphics, with desktop units assigned with G suffix on their model numbers (e.g. Ryzen 5 3400G & Athlon 3000G) to distinguish them from regular processors or with basic graphics and also to differentiate away from their former Bulldozer era A-series APUs. The mobile counterparts were always paired with Radeon Graphics regardless of suffixes.
In November 2017, HP released the Envy x360, featuring the Ryzen 5 2500U APU, the first 4th generation APU, based on the Zen CPU architecture and the Vega graphics architecture.

## Features
### Heterogeneous System Architecture

AMD is a founding member of the Heterogeneous System Architecture (HSA) Foundation and is consequently actively working on developing HSA in cooperation with other members. The following hardware and software implementations are available in AMD's APU-branded products:
| Type | HSA feature | First implemented | Notes |
| Optimized Platform | GPU Compute C++ Support | 2012 Trinity APUs | Support OpenCL C++ directions and Microsoft's C++ AMP language extension. This eases programming of both CPU and GPU working together to process support parallel workloads. |
| Optimized Platform | HSA-aware MMU | 2012 Trinity APUs | GPU can access the entire system memory through the translation services and page fault management of the HSA MMU. |
| Optimized Platform | Shared Power Management | 2012 Trinity APUs | CPU and GPU now share the power budget. Priority goes to the processor most suited to the current tasks. |
| Architectural Integration | Heterogeneous Memory Management: the CPU's MMU and the GPU's IOMMU share the same address space. | 2014 PlayStation 4, Kaveri APUs | CPU and GPU now access the memory with the same address space. Pointers can now be freely passed between CPU and GPU, hence enabling zero-copy. |
| Architectural Integration | Fully coherent memory between CPU and GPU | 2014 PlayStation 4, Kaveri APUs | GPU can now access and cache data from coherent memory regions in the system memory, and also reference the data from CPU's cache. Cache coherency is maintained. |
| Architectural Integration | GPU uses pageable system memory via CPU pointers | 2014 PlayStation 4, Kaveri APUs | GPU can take advantage of the shared virtual memory between CPU and GPU, and pageable system memory can now be referenced directly by the GPU, instead of being copied or pinned before accessing. |
| System Integration | GPU compute context switch | 2015 Carrizo APU | Compute tasks on GPU can be context switched, allowing a multi-tasking environment and also faster interpretation between applications, compute and graphics. |
| System Integration | GPU graphics pre-emption | 2015 Carrizo APU | Long-running graphics tasks can be pre-empted so processes have low latency access to the GPU. |
| System Integration | Quality of service | 2015 Carrizo APU | In addition to context switch and pre-emption, hardware resources can be either equalized or prioritized among multiple users and applications. |

### Feature overview

The following table shows features of AMD's processors with 3D graphics, including APUs (see also: List of AMD processors with 3D graphics).
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| Platform | Platform | Platform | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | High, standard and low power | Low and ultra-low power | Low and ultra-low power | Low and ultra-low power | Low and ultra-low power | Low and ultra-low power | Low and ultra-low power | Low and ultra-low power | Low and ultra-low power | Low and ultra-low power |
| Codename | Server | Basic | | | | | | Toronto | | | | | | | | | | | | | | | | | |
| Codename | Server | Micro | | | | | | | | | | | | | | | | Kyoto | | | | | | | |
| Codename | Desktop | Performance | | | | | | | | | | | | | Raphael | Phoenix | | | | | | | | | |
| Codename | Desktop | Mainstream | Llano | Trinity | Richland | Kaveri | Kaveri Refresh (Godavari) | Carrizo | Bristol Ridge | Raven Ridge | Picasso | Renoir | Cezanne | | Raphael | Phoenix | | | | | | | | | |
| Codename | Desktop | Entry | Llano | Trinity | Richland | Kaveri | Kaveri Refresh (Godavari) | Carrizo | Bristol Ridge | Raven Ridge | Picasso | Renoir | Cezanne | | | | Phoenix | | | | | | | | | |
| Codename | Desktop | Basic | | | | | | | | | | | | | | | | Kabini | | | | Dalí | | | |
| Codename | Mobile | Performance | | | | | | | | | | Renoir | Cezanne | Rembrandt | Dragon Range | | | | | | | | | | |
| Codename | Mobile | Mainstream | Llano | Trinity | Richland | Kaveri | | Carrizo | Bristol Ridge | Raven Ridge | Picasso | Renoir Lucienne | Cezanne Barceló | Rembrandt | Dragon Range | Phoenix | | | | | | | | | |
| Codename | Mobile | Entry | Llano | Trinity | Richland | Kaveri | | Carrizo | Bristol Ridge | Raven Ridge | | | | | | | | | | | | Dalí | | | Mendocino |
| Codename | Mobile | Basic | | | | | | | | | | | | | | | Desna, Ontario, Zacate | Kabini, Temash | Beema, Mullins | Carrizo-L | Stoney Ridge | Dalí | Pollock | | Mendocino |
| Codename | Embedded | Embedded | | Trinity | | Bald Eagle | | Merlin Falcon, Brown Falcon | | Great Horned Owl | | Grey Hawk | | | | | Ontario, Zacate | Kabini | Steppe Eagle, Crowned Eagle, LX-Family | | Prairie Falcon | Banded Kestrel | | River Hawk | |
| Released | Released | Released | Aug 2011 | Oct 2012 | Jun 2013 | Jan 2014 | 2015 | Jun 2015 | Jun 2016 | Oct 2017 | Jan 2019 | Mar 2020 | Jan 2021 | Jan 2022 | Sep 2022 | Jan 2023 | Jan 2011 | May 2013 | Apr 2014 | May 2015 | Feb 2016 | Apr 2019 | Jul 2020 | Jun 2022 | Nov 2022 |
| CPU microarchitecture | CPU microarchitecture | CPU microarchitecture | K10 | Piledriver | Piledriver | Steamroller | Steamroller | Excavator | "Excavator+" | Zen | Zen+ | Zen 2 | Zen 3 | Zen 3+ | Zen 4 | Zen 4 | Bobcat | Jaguar | Puma | Puma+ | "Excavator+" | Zen | Zen | Zen+ | "Zen 2+" |
| ISA | ISA | ISA | x86-64 v1 | x86-64 v2 | x86-64 v2 | x86-64 v2 | x86-64 v2 | x86-64 v3 | x86-64 v3 | x86-64 v3 | x86-64 v3 | x86-64 v3 | x86-64 v3 | x86-64 v3 | x86-64 v4 | x86-64 v4 | x86-64 v1 | x86-64 v2 | x86-64 v2 | x86-64 v2 | x86-64 v3 | x86-64 v3 | x86-64 v3 | x86-64 v3 | x86-64 v3 |
| Socket | Desktop | Performance | — | — | — | — | — | — | — | — | — | — | — | — | AM5 | — | — | — | — | — | — | — | — | — | — |
| Socket | Desktop | Mainstream | — | — | — | — | — | AM4 | AM4 | AM4 | AM4 | AM4 | AM4 | — | AM5 | — | — | — | — | — | — | — | — | — | — |
| Socket | Desktop | Entry | FM1 | FM2 | FM2 | FM2+ | FM2+ | FM2+, AM4 | AM4 | AM4 | AM4 | AM4 | AM4 | — | — | — | | | — | — | — | — | — | — | — | — | — |
| Socket | Desktop | Basic | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | AM1 | — | — | — | FP5 | — | — | — |
| Socket | Other | Other | FS1 | FS1+, FP2 | FS1+, FP2 | FP3 | FP3 | FP4 | FP4 | FP5 | FP5 | FP6 | FP6 | FP7 | FL1 | FP7 FP7r2 FP8 | ? | FT1 | FT3 | FT3b | FT3b | FP4 | FP5 | FT5 | FP5 | FT6 |
| PCI Express version | PCI Express version | PCI Express version | 2.0 | 2.0 | 2.0 | 3.0 | 3.0 | 3.0 | 3.0 | 3.0 | 3.0 | 3.0 | 3.0 | 4.0 | 5.0 | 4.0 | 2.0 | 2.0 | 2.0 | 2.0 | 3.0 | 3.0 | 3.0 | 3.0 | 3.0 |
| CXL | CXL | CXL | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — |
| Fab. (nm) | Fab. (nm) | Fab. (nm) | GF 32SHP (HKMG SOI) | GF 32SHP (HKMG SOI) | GF 32SHP (HKMG SOI) | GF 28SHP (HKMG bulk) | GF 28SHP (HKMG bulk) | GF 28SHP (HKMG bulk) | GF 28SHP (HKMG bulk) | GF 14LPP (FinFET bulk) | GF 12LP (FinFET bulk) | TSMC N7 (FinFET bulk) | TSMC N7 (FinFET bulk) | TSMC N6 (FinFET bulk) | CCD: TSMC N5 (FinFET bulk) cIOD: TSMC N6 (FinFET bulk) | TSMC 4nm (FinFET bulk) | TSMC N40 (bulk) | TSMC N28 (HKMG bulk) | GF 28SHP (HKMG bulk) | GF 28SHP (HKMG bulk) | GF 28SHP (HKMG bulk) | GF 14LPP (FinFET bulk) | GF 14LPP (FinFET bulk) | GF 12LP (FinFET bulk) | TSMC N6 (FinFET bulk) |
| Die area (mm$^2$) | Die area (mm$^2$) | Die area (mm$^2$) | 228 | 246 | 246 | 245 | 245 | 245 | 250 | 210 | 210 | 156 | 180 | 210 | CCD: (2x) 70 cIOD: 122 | 178 | 75 (+ 28 FCH) | 107 | 107 | ? | 125 | 149 | | | ~100 |
| Min TDP (W) | Min TDP (W) | Min TDP (W) | 35 | 17 | 17 | 17 | 17 | 12 | 12 | 12 | 12 | 10 | 10 | 15 | 65 | 35 | 4.5 | 4 | 3.95 | 10 | 6 | 6 | 6 | 12 | 8 |
| Max APU TDP (W) | Max APU TDP (W) | Max APU TDP (W) | 100 | 100 | 100 | 95 | 95 | 65 | 65 | 65 | 65 | 65 | 65 | 45 | 170 | 54 | 18 | 25 | 25 | 25 | 25 | 25 | 6 | 54 | 15 |
| Max stock APU base clock (GHz) | Max stock APU base clock (GHz) | Max stock APU base clock (GHz) | 3 | 3.8 | 4.1 | 4.1 | 4.1 | 3.7 | 3.8 | 3.6 | 3.7 | 3.8 | 4.0 | 3.3 | 4.7 | 4.3 | 1.75 | 2.2 | 2 | 2.2 | 3.2 | 2.6 | 1.2 | 3.35 | 2.8 |
| Max APUs per node | Max APUs per node | Max APUs per node | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Max core dies per CPU | Max core dies per CPU | Max core dies per CPU | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 2 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Max CCX per core die | Max CCX per core die | Max CCX per core die | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 2 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Max cores per CCX | Max cores per CCX | Max cores per CCX | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 8 | 8 | 8 | 8 | 2 | 4 | 4 | 4 | 2 | 2 | 2 | 4 | 4 |
| Max CPU cores per APU | Max CPU cores per APU | Max CPU cores per APU | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 8 | 8 | 8 | 16 | 8 | 2 | 4 | 4 | 4 | 2 | 2 | 2 | 4 | 4 |
| Max threads per CPU core | Max threads per CPU core | Max threads per CPU core | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 1 | 1 | 1 | 1 | 1 | 2 | 2 | 2 | 2 |
| Integer pipeline structure | Integer pipeline structure | Integer pipeline structure | 3+3 | 2+2 | 2+2 | 2+2 | 2+2 | 2+2 | 2+2 | 4+2 | 4+2 | 4+2+1 | 1+3+3+1+2 | 1+3+3+1+2 | 1+3+3+1+2 | 1+3+3+1+2 | 1+1+1+1 | 1+1+1+1 | 1+1+1+1 | 1+1+1+1 | 2+2 | 4+2 | 4+2 | 4+2 | 4+2+1 |
| i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF | i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF | i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF | | | | | | | | | | | | | | | | | | | | | | | |
| IOMMU | IOMMU | IOMMU | — | v2 | v2 | v2 | v2 | v2 | v2 | v2 | v2 | v2 | v2 | v2 | v2 | v2 | v1 | v1 | v2 | v2 | v2 | v2 | v2 | v2 | v2 |
| BMI1, AES-NI, CLMUL, and F16C | BMI1, AES-NI, CLMUL, and F16C | BMI1, AES-NI, CLMUL, and F16C | — | | | | | | | | | | | | | | — | | | | | | | | | |
| MOVBE | MOVBE | MOVBE | — | — | — | — | — | | | | | | | | | | | | | | | | | | — | | | | | | | | | |
| AVIC, BMI2, RDRAND, and MWAITX/MONITORX | AVIC, BMI2, RDRAND, and MWAITX/MONITORX | AVIC, BMI2, RDRAND, and MWAITX/MONITORX | — | — | — | — | — | | | | | | | | | | — | — | — | — | | | | | |
| SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing | SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing | SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing | — | — | — | — | — | — | — | | | | | | | | — | — | — | — | — | | | | |
| GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT | GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT | GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT | — | — | — | — | — | — | — | — | — | | | | | | — | — | — | — | — | — | — | — | |
| MPK, VAES | MPK, VAES | MPK, VAES | — | — | — | — | — | — | — | — | — | — | | | | | — | — | — | — | — | — | — | — | — |
| SGX | SGX | SGX | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — |
| FPUs per core | FPUs per core | FPUs per core | 1 | 0.5 | 0.5 | 0.5 | 0.5 | 0.5 | 0.5 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0.5 | 1 | 1 | 1 | 1 |
| Pipes per FPU | Pipes per FPU | Pipes per FPU | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 |
| FPU pipe width | FPU pipe width | FPU pipe width | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 256-bit | 256-bit | 256-bit | 256-bit | 256-bit | 80-bit | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 128-bit | 256-bit |
| CPU instruction set SIMD level | CPU instruction set SIMD level | CPU instruction set SIMD level | SSE4a | AVX | AVX | AVX | AVX | AVX2 | AVX2 | AVX2 | AVX2 | AVX2 | AVX2 | AVX2 | AVX-512 | AVX-512 | SSSE3 | AVX | AVX | AVX | AVX2 | AVX2 | AVX2 | AVX2 | AVX2 |
| 3DNow! | 3DNow! | 3DNow! | 3DNow!+ | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — |
| PREFETCH/PREFETCHW | PREFETCH/PREFETCHW | PREFETCH/PREFETCHW | | | | | | | | | | | | | | | | | | | | | | | |
| GFNI | GFNI | GFNI | — | — | — | — | — | — | — | — | — | — | — | — | | | — | — | — | — | — | — | — | — | — |
| AMX | AMX | AMX | — | — | — | — | — | — | — | — | — | — | — | — | — | — | | | | | | | | | | | | | | — | — | — | — | — | — | — | — | — |
| FMA4, LWP, TBM, and XOP | FMA4, LWP, TBM, and XOP | FMA4, LWP, TBM, and XOP | — | | | | | | | — | — | — | — | — | — | — | — | — | — | — | | — | — | — | — |
| FMA3 | FMA3 | FMA3 | — | | | | | | | | | | | | | | — | — | — | — | | | | | |
| AMD XDNA | AMD XDNA | AMD XDNA | — | — | — | — | — | — | — | — | — | — | — | — | — | | — | — | — | — | — | — | — | — | — |
| L1 data cache per core (KiB) | L1 data cache per core (KiB) | L1 data cache per core (KiB) | 64 | 16 | 16 | 16 | 16 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 | 32 |
| L1 data cache associativity (ways) | L1 data cache associativity (ways) | L1 data cache associativity (ways) | 2 | 4 | 4 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 |
| L1 instruction caches per core | L1 instruction caches per core | L1 instruction caches per core | 1 | 0.5 | 0.5 | 0.5 | 0.5 | 0.5 | 0.5 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0.5 | 1 | 1 | 1 | 1 |
| Max APU total L1 instruction cache (KiB) | Max APU total L1 instruction cache (KiB) | Max APU total L1 instruction cache (KiB) | 256 | 128 | 128 | 192 | 192 | 192 | 192 | 256 | 256 | 256 | 256 | 256 | 512 | 256 | 64 | 64 | 128 | 128 | 96 | 128 | 128 | 128 | 128 |
| L1 instruction cache associativity (ways) | L1 instruction cache associativity (ways) | L1 instruction cache associativity (ways) | 2 | 2 | 2 | 3 | 3 | 3 | 3 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 2 | 2 | 2 | 2 | 3 | 4 | 4 | 4 | 8 |
| L2 caches per core | L2 caches per core | L2 caches per core | 1 | 0.5 | 0.5 | 0.5 | 0.5 | 0.5 | 0.5 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0.5 | 1 | 1 | 1 | 1 |
| Max APU total L2 cache (MiB) | Max APU total L2 cache (MiB) | Max APU total L2 cache (MiB) | 4 | 4 | 4 | 4 | 4 | 2 | 2 | 2 | 2 | 4 | 4 | 4 | 16 | | 1 | 2 | 2 | 2 | 1 | 1 | 1 | 2 | 2 |
| L2 cache associativity (ways) | L2 cache associativity (ways) | L2 cache associativity (ways) | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 16 | 16 | 16 | 16 | 16 | 8 | 8 | 8 | 8 |
| Max on--die L3 cache per CCX (MiB) | Max on--die L3 cache per CCX (MiB) | Max on--die L3 cache per CCX (MiB) | — | — | — | — | — | — | — | 4 | 4 | 4 | 16 | 16 | 32 | | — | — | — | — | — | — | 4 | 4 | 4 | 4 |
| Max 3D V-Cache per CCD (MiB) | Max 3D V-Cache per CCD (MiB) | Max 3D V-Cache per CCD (MiB) | — | — | — | — | — | — | — | — | — | — | — | — | 64 | — | — | — | — | — | — | — | — | — | — | — |
| Max total in-CCD L3 cache per APU (MiB) | Max total in-CCD L3 cache per APU (MiB) | Max total in-CCD L3 cache per APU (MiB) | — | — | — | — | — | — | — | 4 | 4 | 8 | 16 | 16 | 64 | | — | — | — | — | — | — | 4 | 4 | 4 | 4 |
| Max. total 3D V-Cache per APU (MiB) | Max. total 3D V-Cache per APU (MiB) | Max. total 3D V-Cache per APU (MiB) | — | — | — | — | — | — | — | — | — | — | — | — | 64 | — | — | — | — | — | — | — | — | — | — | — |
| Max. board L3 cache per APU (MiB) | Max. board L3 cache per APU (MiB) | Max. board L3 cache per APU (MiB) | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — |
| Max total L3 cache per APU (MiB) | Max total L3 cache per APU (MiB) | Max total L3 cache per APU (MiB) | — | — | — | — | — | — | — | 4 | 4 | 8 | 16 | 16 | 128 | | — | — | — | — | — | — | 4 | 4 | 4 | 4 |
| APU L3 cache associativity (ways) | APU L3 cache associativity (ways) | APU L3 cache associativity (ways) | — | — | — | — | — | — | — | 16 | 16 | 16 | 16 | 16 | 16 | 16 | — | — | — | — | — | — | 16 | 16 | 16 | 16 |
| L3 cache scheme | L3 cache scheme | L3 cache scheme | — | — | — | — | — | — | — | Victim | Victim | Victim | Victim | Victim | Victim | Victim | — | — | — | — | — | — | Victim | Victim | Victim | Victim |
| Max. L4 cache | Max. L4 cache | Max. L4 cache | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — | — |
| Max stock DRAM support | Max stock DRAM support | Max stock DRAM support | DDR3-1866 | DDR3-1866 | DDR3-2133 | DDR3-2133 | DDR3-2133 | DDR3-2133, DDR4-2400 | DDR4-2400 | DDR4-2933 | DDR4-2933 | DDR4-3200, LPDDR4-4266 | DDR4-3200, LPDDR4-4266 | DDR5-4800, LPDDR5-6400 | DDR5-5200 | DDR5-5600, LPDDR5x-7500 | DDR3L-1333 | DDR3L-1600 | DDR3L-1866 | DDR3L-1866 | DDR3-1866, DDR4-2400 | DDR4-2400 | DDR4-1600 | DDR4-3200 | LPDDR5-5500 |
| Max DRAM channels per APU | Max DRAM channels per APU | Max DRAM channels per APU | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 1 | 1 | 1 | 1 | 1 | 2 | 1 | 2 | 2 |
| Max stock DRAM bandwidth (GB/s) per APU | Max stock DRAM bandwidth (GB/s) per APU | Max stock DRAM bandwidth (GB/s) per APU | 29.866 | 29.866 | 34.132 | 34.132 | 34.132 | 38.400 | 38.400 | 46.932 | 46.932 | 68.256 | 68.256 | 102.400 | 83.200 | 120.000 | 10.666 | 12.800 | 14.933 | 14.933 | 19.200 | 38.400 | 12.800 | 51.200 | 88.000 |
| GPU microarchitecture | GPU microarchitecture | GPU microarchitecture | TeraScale 2 (VLIW5) | TeraScale 3 (VLIW4) | TeraScale 3 (VLIW4) | GCN 2nd gen | GCN 2nd gen | GCN 3rd gen | GCN 3rd gen | GCN 5th gen | GCN 5th gen | GCN 5th gen | GCN 5th gen | RDNA 2 | RDNA 2 | RDNA 3 | TeraScale 2 (VLIW5) | GCN 2nd gen | GCN 2nd gen | GCN 2nd gen | GCN 3rd gen | GCN 5th gen | GCN 5th gen | GCN 5th gen | RDNA 2 |
| GPU instruction set | GPU instruction set | GPU instruction set | TeraScale instruction set | TeraScale instruction set | TeraScale instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | RDNA instruction set | RDNA instruction set | RDNA instruction set | TeraScale instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | GCN instruction set | RDNA instruction set |
| Max stock GPU base clock (MHz) | Max stock GPU base clock (MHz) | Max stock GPU base clock (MHz) | 600 | 800 | 844 | 866 | 866 | 1108 | 1108 | 1250 | 1400 | 2100 | 2100 | 2400 | 400 | | 538 | 600 | ? | 847 | 900 | 1200 | 600 | 1300 | 1900 |
| Max stock GPU base GFLOPS | Max stock GPU base GFLOPS | Max stock GPU base GFLOPS | 480 | 614.4 | 648.1 | 886.7 | 886.7 | 1134.5 | 1134.5 | 1760 | 1971.2 | 2150.4 | 2150.4 | 3686.4 | 102.4 | | 86 | ? | ? | ? | 345.6 | 460.8 | 230.4 | 1331.2 | 486.4 |
| 3D engine | 3D engine | 3D engine | Up to 400:20:8 | Up to 384:24:6 | Up to 384:24:6 | Up to 512:32:8 | Up to 512:32:8 | Up to 512:32:8 | Up to 512:32:8 | Up to 704:44:16 | Up to 704:44:16 | Up to 512:32:8 | Up to 512:32:8 | 768:48:8 | 128:8:4 | | 80:8:4 | 128:8:4 | 128:8:4 | 128:8:4 | Up to 192:12:8 | Up to 192:12:4 | 192:12:4 | Up to 512:?:? | 128:?:? |
| 3D engine | 3D engine | 3D engine | IOMMUv1 | IOMMUv1 | IOMMUv1 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv1 | IOMMUv1 | ? | ? | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 | IOMMUv2 |
| Video decoder | Video decoder | Video decoder | UVD 3.0 | UVD 3.0 | UVD 3.0 | UVD 4.2 | UVD 4.2 | UVD 6.0 | UVD 6.0 | VCN 1.0 | VCN 1.0 | VCN 2.1 | VCN 2.2 | VCN 3.1 | VCN 3.1 | ? | UVD 3.0 | UVD 4.0 | UVD 4.2 | UVD 4.2 | UVD 6.2 | VCN 1.0 | VCN 1.0 | VCN 1.0 | VCN 3.1 |
| Video encoder | Video encoder | Video encoder | — | VCE 1.0 | VCE 1.0 | VCE 2.0 | VCE 2.0 | VCE 3.1 | VCE 3.1 | VCN 1.0 | VCN 1.0 | VCN 2.1 | VCN 2.2 | VCN 3.1 | VCN 3.1 | ? | — | VCE 2.0 | VCE 2.0 | VCE 2.0 | VCE 3.4 | VCN 1.0 | VCN 1.0 | VCN 1.0 | VCN 3.1 |
| AMD Fluid Motion | AMD Fluid Motion | AMD Fluid Motion | | | | | | | | | | | | | | | | | | | | | | | |
| GPU power saving | GPU power saving | GPU power saving | PowerPlay | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerPlay | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune | PowerTune |
| TrueAudio | TrueAudio | TrueAudio | — | — | — | | | | | | | | ? | ? | ? | ? | — | | | | | | | | |
| FreeSync | FreeSync | FreeSync | — | — | — | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | — | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 | 1 2 |
| HDCP | HDCP | HDCP | ? | ? | ? | 1.4 | 1.4 | 1.4 | 1.4 | 2.2 | 2.2 | 2.2 | 2.2 | 2.3 | 2.3 | 2.3 | ? | 1.4 | 1.4 | 1.4 | 1.4 | 2.2 | 2.2 | 2.2 | 2.3 |
| PlayReady | PlayReady | PlayReady | — | — | — | — | — | — | — | 3.0 not yet | 3.0 not yet | 3.0 not yet | 3.0 not yet | 3.0 not yet | 3.0 not yet | 3.0 not yet | — | — | — | — | — | 3.0 not yet | 3.0 not yet | 3.0 not yet | 3.0 not yet |
| Supported displays | Supported displays | Supported displays | 2–3 | 2–4 | 2–4 | 2–4 | 2–4 | 3 | 3 | 3 (desktop) 4 (mobile, embedded) | 3 (desktop) 4 (mobile, embedded) | 4 | 4 | 4 | 4 | 4 | 2 | 2 | 2 | 2 | 3 | 4 | | 4 | 4 |
| /drm/radeon | /drm/radeon | /drm/radeon | | | | | | | — | — | — | — | — | — | — | — | | | | | — | — | — | — | — |
| /drm/amdgpu | /drm/amdgpu | /drm/amdgpu | — | — | — | | | | | | | | | | | | — | | | | | | | | |
* ↑ For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845.
* ↑ A PC would be one node.
* ↑ An APU combines a CPU and a GPU. Both have cores.
* ↑ Requires firmware support.
* 1 2 Requires firmware support.
* ↑ No SSE4. No SSSE3.
* ↑ Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
* ↑ Unified shaders : texture mapping units : render output units
* 1 2 To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
* ↑ To feed more than two displays, the additional panels must have native DisplayPort support. Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
* 1 2 DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.

## APU or Radeon Graphics branded platforms

AMD APUs have CPU modules, cache, and a discrete-class graphics processor, all on the same die using the same bus. This architecture allows for the use of graphics accelerators, such as OpenCL, with the integrated graphics processor. The goal is to create a "fully integrated" APU, which, according to AMD, will eventually feature 'heterogeneous cores' capable of processing both CPU and GPU work automatically, depending on the workload requirement.

### TeraScale-based GPU
#### K10 architecture (2011): Llano

* "Stars" AMD K10-cores
* Integrated Evergreen/VLIW5-based GPU (branded Radeon HD 6000 series)
* Northbridge
* PCIe
* DDR3 memory controller to arbitrate between coherent and non-coherent memory requests. The physical memory is partitioned between the GPU (up to 512 MB) and the CPU (the remainder).
* Unified Video Decoder
* AMD Eyefinity multi-monitor-support
The first generation APU, released in June 2011, was used in both desktops and laptops. It was based on the K10 architecture and built on a 32 nm process featuring two to four CPU cores on a thermal design power (TDP) of 65-100 W, and integrated graphics based on the Radeon HD 6000 series with support for DirectX 11, OpenGL 4.2 and OpenCL 1.2. In performance comparisons against the similarly priced Intel Core i3-2105, the Llano APU was criticised for its poor CPU performance and praised for its better GPU performance. AMD was later criticised for abandoning Socket FM1 after one generation.

#### Bobcat architecture (2011): Ontario, Zacate, Desna, Hondo

* Bobcat-based CPU
* Evergreen/VLIW5-based GPU (branded Radeon HD 6000 series and Radeon HD 7000 series)
* Northbridge
* PCIe support.
* DDR3 SDRAM memory controller to arbitrate between coherent and non-coherent memory requests. The physical memory is partitioned between the GPU (up to 512 MB) and the CPU (the remainder).
* Unified Video Decoder (UVD)
The AMD Brazos platform was introduced on 4 January 2011, targeting the subnotebook, netbook and low power small form factor markets. It features the 9-watt AMD C-Series APU (codename: Ontario) for netbooks and low power devices as well as the 18-watt AMD E-Series APU (codename: Zacate) for mainstream and value notebooks, all-in-ones and small form factor desktops. Both APUs feature one or two Bobcat x86 cores and a Radeon Evergreen Series GPU with full DirectX11, DirectCompute and OpenCL support including UVD3 video acceleration for HD video including 1080p.
AMD expanded the Brazos platform on 5 June 2011 with the announcement of the 5.9-watt AMD Z-Series APU (codename: Desna) designed for the Tablet market. The Desna APU is based on the 9-watt Ontario APU. Energy savings were achieved by lowering the CPU, GPU and northbridge voltages, reducing the idle clocks of the CPU and GPU as well as introducing a hardware thermal control mode. A bidirectional turbo core mode was also introduced.
AMD announced the Brazos-T platform on 9 October 2012. It comprised the 4.5-watt AMD Z-Series APU (codenamed Hondo) and the A55T Fusion Controller Hub (FCH), designed for the tablet computer market. The Hondo APU is a redesign of the Desna APU. AMD lowered energy use by optimizing the APU and FCH for tablet computers.
The Deccan platform including Krishna and Wichita APUs were cancelled in 2011. AMD had originally planned to release them in the second half 2012.

#### Piledriver architecture (2012): Trinity and Richland

* Piledriver-based CPU
* Northern Islands/VLIW4-based GPU (branded Radeon HD 7000 and 8000 series)
* Unified Northbridge – includes AMD Turbo Core 3.0, which enables automatic bidirectional power management between CPU modules and GPU. Power to the CPU and GPU is controlled automatically by changing the clock rate depending on the load. For example, for a non-overclocked A10-5800K APU the CPU frequency can change from 1.4 GHz to 4.2 GHz, and the GPU frequency can change from 304 MHz to 800 MHz. In addition, CC6 mode is capable of powering down individual CPU cores, while PC6 mode is able to lower the power on the entire rail.
* AMD HD Media Accelerator – includes AMD Perfect Picture HD, AMD Quick Stream technology, and AMD Steady Video technology.
* Display controllers: AMD Eyefinity-support for multi-monitor set-ups, HDMI, DisplayPort 1.2, DVI

##### Trinity

The first iteration of the second generation platform, released in October 2012, brought improvements to CPU and GPU performance to both desktops and laptops. The platform features 2 to 4 Piledriver CPU cores built on a 32 nm process with a TDP between 65 W and 100 W, and a GPU based on the Radeon HD7000 series with support for DirectX 11, OpenGL 4.2, and OpenCL 1.2. The Trinity APU was praised for the improvements to CPU performance compared to the Llano APU.

##### Richland

* "Enhanced Piledriver" CPU cores
* Temperature Smart Turbo Core technology. An advancement of the existing Turbo Core technology, which allows internal software to adjust the CPU and GPU clock speed to maximise performance within the constraints of the Thermal design power of the APU.
* New low-power consumption CPUs with only 45 W TDP
The release of this second iteration of this generation was 12 March 2013 for mobile parts and 5 June 2013 for desktop parts.

### Graphics Core Next-based GPU
#### Jaguar architecture (2013): Kabini and Temash

* Jaguar-based CPU
* Graphics Core Next 2nd Gen-based GPU
* Socket AM1 and Socket FT3 support
* Target segment desktop and mobile
In January 2013 the Jaguar-based Kabini and Temash APUs were unveiled as the successors of the Bobcat-based Ontario, Zacate and Hondo APUs. The Kabini APU is aimed at the low-power, subnotebook, netbook, ultra-thin and small form factor markets, while the Temash APU is aimed at the tablet, ultra-low power and small form factor markets. The two to four Jaguar cores of the Kabini and Temash APUs feature numerous architectural improvements regarding power requirement and performance, such as support for newer x86-instructions, a higher IPC count, a CC6 power state mode and clock gating. Kabini and Temash are AMD's first, and also the first ever quad-core x86 based SoCs. The integrated Fusion Controller Hubs (FCH) for Kabini and Temash are codenamed "Yangtze" and "Salton", respectively. The Yangtze FCH features support for two USB 3.0 ports, two SATA 6 Gbit/s ports, as well as the xHCI 1.0 and SD/SDIO 3.0 protocols for SD-card support. Both chips feature DirectX 11.1-compliant GCN-based graphics as well as numerous HSA improvements. They were fabricated at a 28 nm process in an FT3 ball grid array package by Taiwan Semiconductor Manufacturing Company (TSMC), and were released on 23 May 2013.
The PlayStation 4 and Xbox One were revealed to both be powered by 8-core semi-custom Jaguar-derived APUs.

#### Steamroller architecture (2014): Kaveri

* Steamroller-based CPU with 2–4 cores
* Graphics Core Next 2nd Gen-based GPU with 192–512 shader processors
* 15–95 W thermal design power
* Fastest mobile processor of this series: AMD FX-7600P (35 W)
* Fastest desktop processor of this series: AMD A10-7850K (95 W)
* Socket FM2+ and Socket FP3
* Target segment desktop and mobile
* Heterogeneous System Architecture-enabled zero-copying through pointer passing
The third generation of the platform, codenamed Kaveri, was partly released on 14 January 2014. Kaveri contains up to four Steamroller CPU cores clocked to 3.9 GHz with a turbo mode of 4.1 GHz, up to a 512-core Graphics Core Next GPU, two decode units per module instead of one (which allows each core to decode four instructions per cycle instead of two), AMD TrueAudio, Mantle API, an on-chip ARM Cortex-A5 MPCore, and will release with a new socket, FM2+. Ian Cutress and Rahul Garg of Anandtech asserted that Kaveri represented the unified system-on-a-chip realization of AMD's acquisition of ATI. The performance of the 45 W A8-7600 Kaveri APU was found to be similar to that of the 100 W Richland part, leading to the claim that AMD made significant improvements in on-die graphics performance per watt; however, CPU performance was found to lag behind similarly specified Intel processors, a lag that was unlikely to be resolved in the Bulldozer family APUs. The A8-7600 component was delayed from a Q1 launch to an H1 launch because the Steamroller architecture components allegedly did not scale well at higher clock speeds.
AMD announced the release of the Kaveri APU for the mobile market on 4 June 2014 at Computex 2014, shortly after the accidental announcement on the AMD website on 26 May 2014. The announcement included components targeted at the standard voltage, low-voltage, and ultra-low voltage segments of the market. In early-access performance testing of a Kaveri prototype laptop, AnandTech found that the 35 W FX-7600P was competitive with the similarly priced 17 W Intel i7-4500U in synthetic CPU-focused benchmarks, and was significantly better than previous integrated GPU systems on GPU-focused benchmarks. Tom's Hardware reported the performance of the Kaveri FX-7600P against the 35 W Intel i7-4702MQ, finding that the i7-4702MQ was significantly better than the FX-7600P in synthetic CPU-focused benchmarks, whereas the FX-7600P was significantly better than the i7-4702MQ's Intel HD 4600 iGPU in the four games that could be tested in the time available to the team.

#### Puma architecture (2014): Beema and Mullins

* Puma-based CPU
* Graphics Core Next 2nd Gen-based GPU with 128 shader processors
* Socket FT3
* Target segment ultra-mobile

#### Puma+ architecture (2015): Carrizo-L

* Puma+-based CPU with 2–4 cores
* Graphics Core Next 2nd Gen-based GPU with 128 shader processors
* 12–25 W configurable TDP
* Socket FP4 support; pin-compatible with Carrizo
* Target segment mobile and ultra-mobile

#### Excavator architecture (2015): Carrizo

* Excavator-based CPU with 4 cores
* Graphics Core Next 3rd Gen-based GPU
* Memory controller supports DDR3 SDRAM at 2133 MHz and DDR4 SDRAM at 1866 MHz
* 15–35 W configurable TDP (with the 15 W cTDP unit having reduced performance)
* Integrated southbridge
* Socket FP4
* Target segment mobile
* Announced by AMD on YouTube (19 November 2014)

#### Steamroller architecture (Q2–Q3 2015): Godavari

* Update of the desktop Kaveri series with higher clock frequencies or smaller power envelope
* Steamroller-based CPU with 4 cores
* Graphics Core Next 2nd Gen-based GPU
* Memory controller supports DDR3 SDRAM at 2133 MHz
* 65/95 W TDP with support for configurable TDP
* Socket FM2+
* Target segment desktop
* Listed since Q2 2015

#### Excavator architecture (2016): Bristol Ridge and Stoney Ridge

* Excavator-based CPU with 2–4 cores
* 1 MB L2 cache per module
* Graphics Core Next 3rd Gen-based GPU
* Memory controller supports DDR4 SDRAM
* 15/35/45/65 W TDP with support for configurable TDP
* 28 nm
* Socket AM4 for desktop
* Target segment desktop, mobile and ultra-mobile

#### Zen architecture (2017): Raven Ridge

* Zen-based CPU cores with simultaneous multithreading (SMT)
* 512 KB L2 cache per core
* 4 MB L3 cache
* Precision Boost 2
* Graphics Core Next 5th Gen "Vega"-based GPU
* Memory controller supports DDR4 SDRAM
* Video Core Next as successor of UVD+VCE
* 14 nm at GlobalFoundries
* Socket FP5 for mobile and AM4 for desktop
* Target segment desktop and mobile
* Listed since Q4 2017

#### Zen+ architecture (2018): Picasso

* Zen+-based CPU microarchitecture
* Refresh of Raven Ridge on 12 nm with improved latency and efficiency/clock frequency. Features similar to Raven Ridge
* Launched April 2018

#### Zen 2 architecture (2019): Renoir

* Zen 2-based CPU microarchitecture
* Graphics Core Next 5th Gen "Vega"-based GPU
* VCN 2.1
* Memory controller supports DDR4 and LPDDR4X SDRAM up to 4266 MHz
* 15 and 45 W TDP for mobile and 35 and 65 W TDP for desktop
* 7 nm at TSMC
* Socket FP6 for mobile and socket AM4 for desktop
* Release July 2019

#### Zen 3 architecture (2020): Cezanne

* Zen 3-based CPU microarchitecture
* Graphics Core Next 5th Gen "Vega"-based GPU
* Memory controller supports DDR4 and LPDDR4X SDRAM up to 4266 MHz
* Up to 45 W TDP for mobile; 35W to 65W TDP for desktop.
* 7 nm at TSMC
* Socket AM4 for desktop
* Socket FP6 for mobile
* Released for mobiles early 2021 with desktop counterparts released in November 2020.

### RDNA-based GPU
#### Zen 3+ architecture (2022): Rembrandt

* Zen 3+ based CPU microarchitecture
* RDNA 2-based GPU
* Memory controller supports DDR5-4800 and LPDDR5-6400
* Up to 45 W TDP for mobile
* Node: TSMC N6
* Socket FP7 for mobile
* Released for mobiles early 2022