# 555 timer IC

The 555 timer IC is an integrated circuit used in a variety of timer, delay, pulse generation, and oscillator applications. It is one of the most popular timing ICs due to its flexibility and price. Derivatives provide two (556) or four (558) timing circuits in one package. The design was first marketed in 1972 by Signetics and used bipolar junction transistors. Since then, numerous companies have made the original timers and later similar low-power CMOS timers. In 2017, it was said that over a billion 555 timers are produced annually by some estimates, and that the design was "probably the most popular integrated circuit ever made".

## History

The timer IC was designed in 1971 by Hans Camenzind under contract to Signetics. In 1968, he was hired by Signetics to develop a phase-locked loop (PLL) IC. He designed an oscillator for PLLs such that the frequency did not depend on the power supply voltage or temperature. Signetics subsequently laid off half of its employees due to the 1970 recession, and development on the PLL was thus frozen. Camenzind proposed the development of a universal circuit based on the oscillator for PLLs and asked that he develop it alone, borrowing equipment from Signetics instead of having his pay cut in half. Camenzind's idea was originally rejected, since other engineers argued the product could be built from existing parts sold by the company; however, the marketing manager approved the idea.
The first design for the 555 was reviewed in the summer of 1971. After this design was tested and found to be without errors, Camenzind got the idea of using a direct resistance instead of a constant current source, finding that it worked satisfactorily. The design change decreased the required 9 external pins to 8, so the IC could be fit in an 8-pin package instead of a 14-pin package. This revised version passed a second design review, and the prototypes were completed in October 1971 as the NE555V (plastic DIP) and SE555T (metal TO-5). The 9-pin version had already been released by another company founded by an engineer who had attended the first review and had retired from Signetics; that firm withdrew its version soon after the 555 was released. The 555 timer was manufactured by 12 companies in 1972, and it became a best-selling product.
The 555 found many applications beyond timers. Camenzind noted in 1997 that "nine out of 10 of its applications were in areas and ways I had never contemplated. For months I was inundated by phone calls from engineers who had new ideas for using the device."

### Name

Several books report the name "555" timer IC derived from the three 5 kΩ resistors inside the chip. However, in a recorded interview with an online transistor museum curator, Hans Camenzind said "It was just arbitrarily chosen. It was Art Fury (marketing manager) who thought the circuit was gonna sell big who picked the name '555' timer IC."

## Design

Depending on the manufacturer, the standard 555 package incorporated the equivalent of 25 transistors, 2 diodes, and 15 resistors on a silicon chip packaged into an 8-pin dual in-line package (DIP-8). Variants available included the 556 (a DIP-14 combining two complete 555s on one chip), and 558 / 559 (both variants were a DIP-16 combining four reduced-functionality timers on one chip).
The NE555 parts were commercial temperature range, 0 °C to +70 °C, and the SE555 part number designated the military temperature range, −55 °C to +125 °C. These chips were available in both high-reliability metal can (T package) and inexpensive epoxy plastic (V package) form factors. Thus, the full part numbers were NE555V, NE555T, SE555V, and SE555T.
Low-power CMOS versions of the 555 are now available, such as the Intersil ICM7555 and Texas Instruments LMC555, TLC555, TLC551.

### Internal schematic

The internal block diagram and schematic of the 555 timer are highlighted with the same color across all three drawings to clarify how the chip is implemented:
* Voltage divider: Between the positive supply voltage V$_{CC}$ and the ground GND is a voltage divider consisting of three identical resistors (5 kΩ for bipolar timers, 100 kΩ or higher for CMOS) to create reference voltages for the analog comparators. CONTROL is connected between the upper two resistors, allowing an external voltage to control the reference voltages:
** When CONTROL is not driven, this divider creates an upper reference voltage of 2⁄3 V$_{CC}$ and a lower reference voltage of 1⁄3 V$_{CC}$.
** When CONTROL is driven, the upper reference voltage will instead be V$_{CONTROL}$ and the lower reference voltage will be 1⁄2 V$_{CONTROL}$.
* Threshold comparator: The comparator's negative input is connected to voltage divider's upper reference voltage, and the comparator's positive input is connected to THRESHOLD.
* Trigger comparator: The comparator's positive input is connected to voltage divider's lower reference, and the comparator's negative input is connected to TRIGGER.
* Latch: A set-reset latch stores the state of the timer and is controlled by the two comparators. RESET overrides the other two inputs, thus the latch (and therefore the entire timer) can be reset at any time.
* Output: The output of the latch is followed by an output stage with push–pull output drivers that can supply up to 200 mA for bipolar timers, lower for CMOS timers.
* Discharge: Also, the output of the latch controls a transistor acting as an electronic switch that connects DISCHARGE to ground.
* 555 internal block diagram
* 555 internal schematic of bipolar version
* 555 internal schematic of CMOS version

### Pinout

The pinout of the 8-pin 555 timer and 14-pin 556 dual timer are shown in the following table. Since the 556 is conceptually two 555 timers that share power pins, the pin numbers for each half are split across two columns.
| 555 pin# | 556 (unit 1) | 556 (unit 2) | Pin name | Pin direction | Pin description |
| 1 | 7 | 7 | GND | Power | Ground supply: this pin is the ground reference voltage (zero volts). |
| 2 | 6 | 8 | TRIGGER | Input | Trigger: when V$_{TRIGGER}$ falls below 1⁄2 V$_{CONTROL}$ (1⁄3 V$_{CC}$, except when CONTROL is driven by an external signal), OUTPUT goes to the high state and a timing interval starts. As long as TRIGGER continues to be kept at a low voltage, OUTPUT will remain in the high state. |
| 3 | 5 | 9 | OUTPUT | Output | Output: this pin is a push-pull (P.P.) output that is driven to either a low state (GND) or a high state (V$_{CC}$ minus approximately 1.7 volts for bipolar timers, or V$_{CC}$ for CMOS timers). |
| 4 | 4 | 10 | RESET | Input | Reset: a timing interval may be reset by driving this pin to GND, but the timing does not begin again until this pin rises above approximately 0.7 volts. This pin overrides TRIGGER, which in turn overrides THRESHOLD. If this pin is not used, it should be connected to V$_{CC}$ to prevent electrical noise accidentally causing a reset. |
| 5 | 3 | 11 | CONTROL | Input | Control: this pin provides access to the internal voltage divider (2⁄3 V$_{CC}$ by default). By applying a voltage to this pin, the timing characteristics can be changed. In astable mode, this pin can be used to frequency-modulate the OUTPUT state. If this pin is not used, it should be connected to a 10 nF decoupling capacitor (between this pin and GND) to ensure electrical noise doesn't affect the internal voltage divider. |
| 6 | 2 | 12 | THRESHOLD | Input | Threshold: when the voltage at this pin is greater than V$_{CONTROL}$ (2⁄3 V$_{CC}$ by default except when CONTROL is driven by an external signal), then the OUTPUT high state timing interval ends, causing OUTPUT to go to the low state. |
| 7 | 1 | 13 | DISCHARGE | Output | Discharge: This pin is an open-collector (O.C.) output for bipolar timers, or an open-drain (O.D.) output for CMOS timers. This pin can be used to discharge a capacitor when OUTPUT is low. In bistable latch and bistable inverter modes, this pin is unused, which allows it to be used as an alternate output. |
| 8 | 14 | 14 | V$_{CC}$ | Power | Positive supply: For bipolar timers, the supply voltage range is typically 4.5 to 16 volts (some are spec'ed for up to 18 volts, though most will operate as low as 3 volts). For CMOS timers, the supply voltage range is typically 2 to 15 volts (some are spec'ed for up to 18 volts, and some are spec'ed as low as 1 volt). See the supply min and max columns in the derivatives table in this article. Decoupling capacitor(s) are generally applied (between this pin and GND) as a good practice. |
* Pinout of 555 single timer
* Pinout of 556 dual timer

## Modes

The 555 IC has the following operating modes:
* Astable (free-running) mode – The 555 operates as an electronic oscillator. Applications include:
** Light emitting diode and lamp flashers, pulse generation, pulse-width modulation (PWM), logic clocks, tone generation, security alarms, pulse-position modulation, etc.
** Analog-to-digital conversion (ADC) from an analog value represented by a resistance or capacitance into a digital pulse length.
*** e.g., selecting a thermistor as timing resistor allows the use of the 555 in a temperature sensor with the period of the output pulse determined by the temperature. A microprocessor can then convert the pulse period to temperature, linearize it, and even provide calibration.
* Monostable (one-shot) mode – The 555 operates as a "one-shot" pulse generator. Applications include:
** timers, missing pulse detection, bounce-free switches, touch switches, frequency dividers, triggered measurement of resistance or capacitance, PWM, etc.
* Bistable (latch) mode – The 555 operates as a set-reset latch. Applications include:
** switch debouncing.
* Schmitt trigger (inverter) mode – the 555 operates as a Schmitt trigger inverter gate. Application:
** Converts a noisy input into a clean digital output.

### Astable

In the astable configuration, the 555 timer puts out a continuous stream of rectangular pulses having a specific period.
The astable configuration is implemented using two resistors, $R_{1}$ and $R_{2},$ and one capacitor $C$. The threshold and trigger pins are both connected to the capacitor; thus they have the same voltage.
Its repeated operating cycle (starting with the capacitor uncharged) is:
* Since the capacitor's voltage will be below 1⁄3 V$_{CC}$, the trigger pin causes the 555's internal latch to change state, causing OUT to go high and the internal discharge transistor to cut-off.
* Since the discharge pin is no longer short-circuited to ground, the capacitor starts charging via current from Vcc through the resistors $R_{1}$ and $R_{2}$.
* Once the capacitor charge reaches 2⁄3 Vcc, the threshold pin causes the 555's internal latch to change state, causing OUT to go low and the internal discharge transistor to go into saturation (maximal-conductivity) mode.
* This discharge transistor provides a discharge path, so the capacitor starts discharging through $R_{2}$.
* Once the capacitor's voltage drops below 1⁄3 V$_{CC}$, the cycle repeats from step 1.
During the first pulse, the capacitor charges from 0 V to 2⁄3 V$_{CC}$, however, in later pulses, it only charges from 1⁄3 V$_{CC}$ to 2⁄3 V$_{CC}$. Consequently, the first pulse has a longer high time interval compared to later pulses. Moreover, the capacitor charges through both resistors but only discharges through $R_{2}$, thus the output high interval is longer than the low interval. This is shown in the following equations:
The output high time interval of each pulse is given by:
    $t_{\text{high}}=\ln(2)\cdot (R_{1}+R_{2})\cdot C$
The output low time interval of each pulse is given by:
    $t_{\text{low}}=\ln(2)\cdot R_{2}\cdot C$
Hence, the frequency $f$ of the pulse is given by:
    $f={\frac {1}{t_{\text{high}}+t_{\text{low}}}}={\frac {1}{\ln(2)\cdot (R_{1}+2\,R_{2})\cdot C}}$
and the duty cycle $D$ is given by:
    $D~(\%)={\frac {t_{\text{high}}}{t_{\text{high}}+t_{\text{low}}}}\cdot 100={\frac {R_{1}+R_{2}}{R_{1}+2\,R_{2}}}\cdot 100$
where $t$ is the time in seconds, $R$ is the resistance in ohms, $C$ is the capacitance in farads, and $\ln(2)$ is the natural log of 2 constant.
Resistor $R_{1}$ requirements:
* The maximum current through $R_{1}$ must be lower than the maximum current rating of the internal transisor at the DISCHARGE pin, because this transistor "shorts" the DISCHARGE pin to the GND pin (per internal schematics above) to drain the capacitor. This is the reason why $R_{1}$ shouldn't be a very low resistance, such as when a variable trimmer or potentiometer is used instead of a fixed value resistor.
* The maximum power rating of $R_{1}$ must be greater than ${\frac {{V_{\text{CC}}}^{2}}{R_{1}}}$, per Ohm's law.

#### Shorter duty cycle

To create an output high time shorter than the low time (i.e., a duty cycle less than 50%) a fast diode (i.e. 1N4148 signal diode) can be placed in parallel with R$_2$, with the cathode on the capacitor side. This bypasses R$_2$ during the high part of the cycle, so that the high interval depends only on R$_1$ and C, with an adjustment based on the voltage drop across the diode. The low time is unaffected by the diode and so remains ln⁡(2)R$_2$C.{\textstyle \ln(2)\, R_{2}\, C\, .} But the diode's forward voltage drop V$_{diode}$ slows charging on the capacitor, so the high time is longer than the often-cited ln⁡(2)R$_1$C{\textstyle \ln(2)\, R_{1}\, C} to become:
    $t_{\text{high}}=\ln \left({\frac {2\,V_{\text{CC}}-3\,V_{\text{diode}}}{V_{\text{CC}}-3\,V_{\text{diode}}}}\right)\cdot R_{1}\cdot C,$
where V$_{diode}$ is when the diode's "on" current is 1⁄2 of V$_{CC}$/R$_1$ (which depends on the type of diode and can be found in datasheets or measured). When V$_{diode}$ is small relative to V$_{cc}$, this charging is faster and approaches ln⁡(2)R$_1$C{\textstyle \ln(2)\, R_{1}\, C} but is slower the closer V$_{diode}$ is to V$_{cc}$:
   As an extreme example, when V$_{CC}$ = 5 V, and V$_{diode}$ = 0.7 V, high time is 1.00 R$_1$C, which is 45% longer than the "expected" 0.693 R$_1$C. At the other extreme, when V$_{cc}$ = 15 V, and V$_{diode}$ = 0.3 V, the high time is 0.725 R$_1$C, which is closer to the expected 0.693 R$_1$C. The equation approaches 0.693 R$_1$C as V$_{diode}$ approaches 0 V.

#### Voltage-controlled pulse-width modulation

In the previous example schematics, the control pin was not used, thus it should connected to ground through a 10 nF decoupling capacitor to shunt electrical noise. However if a time-varying voltage source was applied to the control pin, then the pulse widths would be dependent on the control voltage.

### Monostable

Monostable mode produces an output pulse when the trigger signals drops below 1⁄3 V$_{CC}$. An RC circuit sets the output pulse's duration as the time $t$ in seconds it takes to charge C to 2⁄3 V$_{CC}$:
    $t=\ln(3)\cdot R\cdot C,$
where $R$ is the resistance in ohms, $C$ is the capacitance in farads, $\ln(3)$ is the natural log of 3 constant. The output pulse duration can be lengthened or shortened as desired by adjusting the values of R and C. Subsequent triggering before the end of this timing interval won't affect the output pulse.

#### Example values

The timing table (right) shows common electronic component value solutions for various powers of 10 timings.
Scaling R and C by opposite powers of 10 will provide the same timing. For instance:
* 1 ms ≅ 1 nF and 910 kΩ,
* 1 ms ≅ 10 nF and 91 kΩ (values from table),
* 1 ms ≅ 100 nF and 9.1 kΩ.
For each row in the example table (right), additional timing values can easily be created by adding one to three of the same resistor value in parallel and/or series. A second resistor in parallel, the new timing is half the table time. A second resistor in series, the new timing is double the table time.
* 2.5 ms (0.25x) ≅ 100 nF and 22.75 kΩ (four 91 kΩ resistors in parallel),
* 5 ms (0.5x) ≅ 100 nF and 45.5 kΩ (two 91 kΩ resistors in parallel),
* 10 ms (1x) ≅ 100 nF and 91 kΩ (values from table),
* 15 ms (1.5x) ≅ 100 nF and 136.5 kΩ (one 91 kΩ resistor in series with "two 91 kΩ resistors in parallel"),
* 20 ms (2x) ≅ 100 nF and 182 kΩ (two 91 kΩ resistors in series),
* 25 ms (2.5x) ≅ 100 nF and 227.5 kΩ ("two 91 kΩ resistors in series" in series with "two 91 kΩ resistors in parallel"),
* 30 ms (3x) ≅ 100 nF and 273 kΩ (three 91 kΩ resistors in series),
* 40 ms (4x) ≅ 100 nF and 364 kΩ (four 91 kΩ resistors in series).

### Bistable SR latch

A 555 timer can act as an active-low SR latch (though without an inverted Q output) with two outputs: output pin is a push-pull output, discharge pin is an open-collector output (requires a pull-up resistor).
For the schematic on the right, a Reset input signal connects to the RESET pin and connecting a Set input signal to the TR pin. Thus, pulling Set momentarily low acts as a "set" and transitions the output to the high state (V$_{CC}$). Conversely, pulling Reset momentarily low acts as a "reset" and transitions the Out pin to the low state (GND).
No timing capacitors are required in a bistable configuration. The threshold input is grounded because it is unused. The trigger and reset inputs may be held high via pull-up resistors if they are normally Hi-Z and only enabled by connecting to ground.

### Bistable Schmitt trigger inverter gate

A 555 timer can be used to create a Schmitt trigger inverter gate with two outputs: output pin is a push-pull output, discharge pin is an open-collector output (requires a pull-up resistor).
For the schematic on the right, an input signal is AC-coupled through a low value series capacitor, then biased by identical high-resistance resistors $R_{1}$ and $R_{2}$, which causes the signal to be centered at 1⁄2 V$_{cc}$. This centered signal is connected to both the trigger and threshold input pins of the timer. The input signal must be strong enough to excite the trigger levels of the comparators to exceed the lower 1⁄3 V$_{CC}$ and upper 2⁄3 V$_{CC}$ thresholds in order to cause them to change state, thus providing the Schmitt trigger feature.
No timing capacitors are required in a bistable configuration.

## Packages

In 1972, Signetics originally released the 555 timer in DIP-8 and TO5-8 metal can packages, and the 556 timer was released in a DIP-14 package.
In 2006, the dual 556 timer was available in through-hole packages as DIP-14 (2.54 mm pitch), and surface-mount packages as SO-14 (1.27 mm pitch) and SSOP-14 (0.65 mm pitch).
In 2012, the 555 was available in through-hole packages as DIP-8 (2.54 mm pitch), and surface-mount packages as SO-8 (1.27 mm pitch), SSOP-8 / TSSOP-8 / VSSOP-8 (0.65 mm pitch), BGA (0.5 mm pitch).
The MIC1555 is a CMOS 555-type timer with three fewer pins available in SOT23-5 (0.95 mm pitch) surface-mount package.

## Specifications

These specifications apply to the original bipolar NE555. Other 555 timers can have different specifications depending on the grade (industrial, military, medical, etc.).
| Part number | NE555 |
| IC Process | Bipolar |
| Supply voltage (V$_{CC}$) | 4.5 to 16 V |
| Supply current (V$_{CC}$ = +5 V) | 3 to 6 mA |
| Supply current (V$_{CC}$ = +15 V) | 10 to 15 mA |
| Output current (maximum) | 200 mA |
| Maximum Power dissipation | 600 mW |
| Power consumption (minimum operating) | 30 mW @ 5 V, 225 mW @ 15 V |
| Operating temperature | 0 to 70 °C |

## Derivatives

Numerous companies have manufactured one or more variants of the 555, 556, 558 timers over the past decades, under many different part numbers. The following is a partial list:
| Manufacturer | Part number | Production status | IC process | Timers total | Supply min. (volt) | Supply max. (volt) | I$_q$ (μA) at 5 V supply | Frequency max. (MHz) | Remarks |
| Custom Silicon Solutions (CSS) | CSS555 | Active | CMOS | 1 | 1.2 | 5.5 | 4.3 | 1.0 | Internal EEPROM, requires programmer |
| Diodes Inc | ZSCT1555 | Discontinued | Bipolar | 1 | 0.9 | 6 | 150 | 0.33 | Designed by Hans Camenzind |
| Japan Radio Company (JRC) | NJM555 | Discontinued | Bipolar | 1 | 4.5 | 16 | 3000 | 0.1* | Also available in SIP-8 package. |
| Microchip | MIC1555/7 | Active | CMOS | 1* | 2.7 | 18 | 240 | 5.0* | Reduced pins & features (only astable & monostable & no reset for MIC1555, astable only for MIC1557), only available in SOT23-5, TSOT23-5, UTDFN-10 packages. |
| ON | MC1455 | Active | Bipolar | 1 | 4.5 | 16 | 3000 | 0.1* | — |
| Renesas | ICM7555 | Active | CMOS | 1 | 2 | 18 | 40 | 1.0 | |
| Renesas | ICM7556 | Active | CMOS | 2 | 2 | 18 | 80 | 1.0 | |
| Signetics | NE555 | Active (TI) | Bipolar | 1 | 4.5 | 16 | 3000 | 0.1* | First 555 timer, DIP-8 or TO5-8 packages. |
| Signetics | NE556 | Active (TI) | Bipolar | 2 | 4.5 | 16 | 6000 | 0.1* | First 556 timer, DIP-14 package. |
| Signetics | NE558 | Discontinued | Bipolar | 4* | 4.5 | 16 | 4800* | 0.1* | First 558 timer, DIP-16 package. |
| STMicroelectronics (ST) | TS555 | Active | CMOS | 1 | 2 | 16 | 110 | 2.7 | — |
| Texas Instruments (TI) | LM555 | Active | Bipolar | 1 | 4.5 | 16 | 3000 | 0.1 | |
| Texas Instruments | LM556 | Discontinued | Bipolar | 2 | 4.5 | 16 | 6000 | 0.1 | |
| Texas Instruments | LMC555 | Active | CMOS | 1 | 1.5 | 15 | 100 | 3.0 | Also available in DSBGA-8 package. |
| Texas Instruments | NE555 | Active | Bipolar | 1 | 4.5 | 16 | 3000 | 0.1* | — |
| Texas Instruments | NE556 | Active | Bipolar | 2 | 4.5 | 16 | 6000 | 0.1* | — |
| Texas Instruments | TLC551 | Active | CMOS | 1 | 1 | 15 | 170 | 1.8 | |
| Texas Instruments | TLC552 | Active | CMOS | 2 | 1 | 15 | 340 | 1.8 | |
| Texas Instruments | TLC555 | Active | CMOS | 1 | 2 | 15 | 170 | 2.1 | — |
| Texas Instruments | TLC556 | Active | CMOS | 2 | 2 | 15 | 340 | 2.1 | — |
| X-REL | XTR655 | Active | SOI | 1 | 2.8 | 5.5 | 170 | 4.0 | Extreme (−60 °C to +230 °C), ceramic DIP-8 package or bare die. |

### Table notes

* All information in the above table was pulled from references in the datasheet column, except where denoted below.
* For the "Total timers" column, a "*" denotes parts that are missing 555 timer features.
* For the "I$_q$" column, a 5-volt supply was chosen as a common voltage to make it easier to compare. The value for Signetics NE558 is an estimate because NE558 datasheets don't state I$_q$ at 5 V. The value listed in this table was estimated by comparing the 5 V to 15 V ratio of other bipolar datasheets, then derating the 15 V parameter for the NE558 part, which is denoted by the "*".
* For the "Frequency max." column, a "*" denotes values that may not be the actual maximum frequency limit of the part. The MIC1555 datasheet discusses limitations from 1 to 5 MHz. Though most bipolar timers don't state the maximum frequency in their datasheets, they all have a maximum frequency limitation of hundreds of kHz across their full temperature range. Section 8.1 of the Texas Instruments NE555 datasheet states a value of 100 kHz, and their website shows a value of 100 kHz in timer comparison tables. Signetics App Note 170 states that most devices will oscillate up to 1 MHz; however, when considering temperature stability, it should be limited to about 500 kHz. The application note from HFO mentions that at higher supply voltages the maximum power dissipation of the circuit might limit the operating frequency, as the supply current increases with frequency.
* For the "Manufacturer" column, the following associates historical 555 timer manufacturers to current company names.
** Fairchild Semiconductor was sold to ON Semiconductor in 2016. ON Semiconductor was founded in 1999 as a spinoff of Motorola Semiconductor Components Group. The MC1455 started as a Motorola product.
** Intersil was sold to Renesas Electronics in 2017. The ICM7555 and ICM7556 started as Intersil products.
** Micrel was sold to Microchip Technology in 2015. The MIC1555 started as a Micrel product.
** National Semiconductor was sold to Texas Instruments in 2011. The LM555 and LM556 started as a National Semiconductor products.
** Signetics was sold to Philips Semiconductor in 1975, later to NXP Semiconductors in 2006.
** Zetex Semiconductors was sold to Diodes Incorporated in 2008. The ZSCT1555 started as a Zetex product.

### 556 dual timer

The dual version is called 556. It features two complete 555 timers in a 14-pin package; only the two power-supply pins are shared between the two timers. In 2020, the bipolar version was available as the NE556, and the CMOS versions were available as the Intersil ICM7556 and Texas Instruments TLC556 and TLC552. See derivatives table in this article.

### 558 quad timer

The quad version is called 558 and has four reduced-functionality timers in a 16-pin package designed primarily for monostable multivibrator applications. By 2014, many versions of 16-pin NE558 have become obsolete.
Partial list of differences between 558 and 555 chips:
* One V$_{CC}$ and one GND, similar to 556 chip.
* Four "Reset" are tied together internally to one external pin (558).
* Four "Control Voltage" are tied together internally to one external pin (558).
* Four "Triggers" are falling-edge sensitive (558), instead of level sensitive (555).
* Two resistors in the voltage divider (558), instead of three resistors (555).
* One comparator (558), instead of two comparators (555).
* Four "Output" are open-collector (O.C.) type (558), instead of push–pull (P.P.) type (555).