# I386

The Intel 386, originally released as the 80386 and later renamed i386, is the third-generation x86 architecture microprocessor from Intel. It was the first 32-bit processor in the line, making it a significant evolution in the x86 architecture. Pre-production samples of the 386 were released to select developers in 1985, while mass production commenced in 1986. The 386 was the central processing unit (CPU) of many workstations and high-end personal computers of the time. The 386 began to fall out of public use starting with the release of the i486 processor in 1989, while in embedded systems the 386 remained in widespread use until Intel finally discontinued it in 2007.
Compared to its predecessor the Intel 80286 ("286"), the 80386 added a three-stage instruction pipeline which it brings up to total of 6-stage instruction pipeline, extended the architecture from 16-bits to 32-bits, and added an on-chip memory management unit. This paging translation unit made it much easier to implement operating systems that used virtual memory. It also offered support for register debugging. The 386 featured three operating modes: real mode, protected mode and virtual mode. The protected mode, which debuted in the 286, was extended to allow the 386 to address up to 4 GB of memory. With the addition of segmented addressing system, it can expand up to 64 terabytes of virtual memory. The all new virtual 8086 mode (or VM86) made it possible to run one or more real mode programs in a protected environment, although some programs were not compatible.
The 32-bit i386 can correctly execute most code intended for the earlier 16-bit processors such as 8086 and 80286 that were ubiquitous in early PCs. As the original implementation of the 32-bit extension of the 80286 architecture, the i386 instruction set, programming model, and binary encodings are still the common denominator for all 32-bit x86 processors, which is termed the i386 architecture, x86, or IA-32, depending on context. Over the years, successively newer implementations of the same architecture have become several hundreds of times faster than the original 80386 (and thousands of times faster than the 8086).

## Production history

Development of i386 technology began in 1982 under the internal name of P3. The tape-out of the 80386 development was finalized in July 1985. The 80386 was introduced as pre-production samples for software development workstations in October 1985. Manufacturing of the chips in significant quantities commenced in June 1986, along with the first plug-in device that allowed existing 80286-based computers to be upgraded to the 386, the Translator 386 by American Computer and Peripheral. The 80386 being sole sourced made the CPU very expensive. Mainboards for 80386-based computer systems were cumbersome and expensive at first, but manufacturing was justified upon the 80386's mainstream adoption. The first personal computer to make use of the 80386 was the Deskpro 386, designed and manufactured by Compaq; this marked the first time a fundamental component in the IBM PC compatible de facto standard was updated by a company other than IBM.
The first versions of the 386 have 275,000 transistors. The 20 MHz version operates at 4–5 MIPS. It also performs between 8,000 and 9,000 Dhrystones per second. The 25 MHz 386 version is capable of 7 MIPS. A 33 MHz 80386 was reportedly measured to operate at about 11.4 and 11.5 MIPS. At that same speed, it has the performance of 8 VAX MIPS. These processors run about 4.4 clocks per instruction.
In May 2006, Intel announced that i386 production would stop at the end of September 2007. Although it had long been obsolete as a personal computer CPU, Intel and others had continued making the chip for embedded systems. Such systems using an i386 or one of many derivatives are common in aerospace technology and electronic musical instruments, among others. Some mobile phones also used (later fully static CMOS variants of) the i386 processor, such as the BlackBerry 950 and Nokia 9000 Communicator. Linux continued to support i386 processors until December 11, 2012, when the kernel cut 386-specific instructions in version 3.8.

## Architecture

The processor was a significant evolution in the x86 architecture, and extended a long line of processors that stretched back to the Intel 8008. The predecessor of the 80386 was the Intel 80286, a 16-bit processor with a segment-based memory management and protection system. The 80386 added a three-stage instruction pipeline which it brought up to total of 6-stage instruction pipeline, extended the architecture from 16-bits to 32-bits, and added an on-chip memory management unit. This paging translation unit made it much easier to implement operating systems that used virtual memory. It also offered support for register debugging.
The 80386 featured three operating modes: real mode, protected mode and virtual mode. The protected mode, which debuted in the 286, was extended to allow the 386 to address up to 4 GB of memory. With the addition of segmented addressing system, it can expand up to 64 terabytes of virtual memory. The all new virtual 8086 mode (or VM86) made it possible to run one or more real mode programs in a protected environment, although some programs were not compatible. It features scaled indexing and 64-bit barrel shifter.
The ability for a 386 to be set up to act like it had a flat memory model in protected mode despite the fact that it uses a segmented memory model in all modes was arguably the most important feature change for the x86 processor family until AMD released the x86-64 in 2003.
Several new instructions have been added to 386: BSF, BSR, BT, BTS, BTR, BTC, CDQ, CWDE, LFS, LGS, LSS, MOVSX, MOVZX, SETcc, SHLD, SHRD.
Two new segment registers have been added (FS and GS) for general-purpose programs. The single Machine Status Word of the 286 grew into eight control registers CR0–CR7. Debug registers DR0–DR7 were added for hardware breakpoints. New forms of the MOV instruction are used to access them.
The chief architect in the development of the 80386 was John H. Crawford. He was responsible for extending the 80286 architecture and instruction set to 32-bits, and then led the microprogram development for the 80386 chip.
The i486 and P5 Pentium line of processors were descendants of the i386 design.

### Data types

The following data types are directly supported and thus implemented by one or more i386 machine instructions; these data types are briefly described here.:
* Bit (Boolean value), bit field (group of up to 32 bits) and bit string (up to 4 Gbit in length).
* 8-bit integer (byte), either signed (range −128..127) or unsigned (range 0..255).
* 16-bit integer, either signed (range −32,768..32,767) or unsigned (range 0..65,535).
* 32-bit integer, either signed (range −2$^{31}$..2$^{31}$−1) or unsigned (range 0..2$^{32}$−1).
* Offset, a 16- or 32-bit displacement referring to a memory location (using any addressing mode).
* Pointer, a 16-bit selector together with a 16- or 32-bit offset.
* Character (8-bit character code).
* String, a sequence of 8-, 16- or 32-bit words (up to 4 Gbyte in length).
* BCD, decimal digits (0..9) represented by unpacked bytes.
* Packed BCD, two BCD digits in one byte (range 0..99).

## Example code

The following i386 assembly source code is for a subroutine named _strtolower that copies a null-terminated ASCIIZ character string from one location to another, converting all alphabetic characters to lower case. The string is copied one byte (8-bit character) at a time.
| 00000000 55 00000001 89E5 00000003 8B750C 00000006 8B7D08 00000009 FC 0000000A AC 0000000B 3C41 0000000D 7C06 0000000F 3C5A 00000011 7F02 00000013 0420 00000015 AA 00000016 84C0 00000018 75F0 0000001A 5D 0000001B C3 | ; _strtolower: ; Copy a null-terminated ASCII string, converting ; all alphabetic characters to lower case. ; ; Entry stack parameters ; [ESP+8] = src, Address of source string ; [ESP+4] = dst, Address of target string ; [ESP+0] = Return address ; _strtolower proc push ebp ; Set up the call frame mov ebp,esp mov esi,[ebp+0xc] ; Set ESI = src mov edi,[ebp+0x8] ; Set EDI = dst cld ; Auto-increment ESI and EDI again: lodsb ; Load AL from [src] and increment ESI cmp al,'A' ; If AL < 'A', jl copy ; Skip conversion cmp al,'Z' ; If AL > 'Z', jg copy ; Skip conversion add al,'a'-'A' ; Convert AL to lowercase copy: stosb ; Store AL to [dst] test al,al ; If AL != 0, jnz again ; Repeat the loop pop ebp ; Restore the previous call ret ; Return to caller end proc |
The example code uses the EBP (base pointer) register to establish a call frame, an area on the stack that contains all of the parameters and local variables for the execution of the subroutine. This kind of calling convention supports reentrant and recursive code and has been used by Algol-like languages since the late 1950s. A flat memory model is assumed, specifically, that the DS and ES segments address the same region of memory.

## Business importance

The first PC based on the Intel 80386 was the Compaq Deskpro 386. By extending the 16/24-bit IBM PC/AT standard into a natively 32-bit computing environment, Compaq became the first company to design and manufacture such a major technical hardware advance on the PC platform. IBM was offered use of the 80386, but had manufacturing rights for the earlier 80286. IBM therefore chose to rely on that processor for a couple more years. The early success of the Compaq Deskpro 386 played an important role in legitimizing the PC "clone" industry and in de-emphasizing IBM's role within it. The first computer system sold with the 386SX was the Compaq Deskpro 386S, released in July 1988.
Prior to the 386, the difficulty of manufacturing microchips and the uncertainty of reliable supply made it desirable that any mass-market semiconductor be multi-sourced, that is, made by two or more manufacturers, the second and subsequent companies manufacturing under license from the originating company. The 386 was for a time (4.7 years) only available from Intel, since Andy Grove, Intel's CEO at the time, made the decision not to encourage other manufacturers to produce the processor as second sources. This decision was ultimately crucial to Intel's success in the market. The 386 was the first significant microprocessor to be single-sourced. Single-sourcing the 386 allowed Intel greater control over its development and substantially greater profits in later years.
AMD introduced its compatible Am386 processor in March 1991 after overcoming legal obstacles, thus ending Intel's 4.7-year monopoly on 386-compatible processors. From 1991 IBM also manufactured 386 chips under license for use only in IBM PCs and boards.

## Compatibles

* The AMD Am386SX and Am386DX were almost exact clones of the i386SX and i386DX. Legal disputes caused production delays for several years, but AMD's 40 MHz part eventually became very popular with computer enthusiasts as a low-cost and low-power alternative to the 25 MHz 486SX. The power draw was further reduced in the "notebook models" (Am386 DXL/SXL/DXLV/SXLV), which could operate with 3.3 V and were implemented in fully static CMOS circuitry.
* Chips and Technologies Super386 38600SX and 38600DX were developed using reverse engineering. They sold poorly, due to some technical errors and incompatibilities, as well as their late appearance on the market. They were therefore short-lived products.
* Cyrix Cx486SLC/Cx486DLC could be (simplistically) described as a kind of 386/486 hybrid chip that included a small amount of on-chip cache. It was popular among computer enthusiasts but did poorly with OEMs. The Cyrix Cx486SLC and Cyrix Cx486DLC processors were pin-compatible with i386SX and i386DX respectively. These processors were also manufactured and sold by Texas Instruments.
* IBM 386SLC and 486SLC/DLC were variants of Intel's design which contained a large amount of on-chip cache (8 KB, and later 16 KB). The agreement with Intel limited their use to IBM's own line of computers and upgrade boards only, so they were not available on the open market.
* V.M. Technology VM386SX+ was developed by Tsukuba, Japan-based fabless microprocessor design firm V.M. Technology (VMT), founded by former Intel 4004 and Zilog Z80 microprocessor design engineer Masatoshi Shima, with its primary funding originating from ASCII Corporation. The chip was primarily marketed in East Asia, avoiding the US market deliberately. ALi M6117 SoC contains an x86 core derived from VM386SX+.

## Early problems

Intel originally intended for the 80386 to debut at 16 MHz. However, due to poor yields, it was instead introduced at 12.5 MHz.
Early in production, Intel discovered a marginal circuit that could cause a system to return incorrect results from 32-bit multiply operations. Not all of the processors already manufactured were affected, so Intel tested its inventory. Processors that were found to be bug-free were marked with a double sigma (ΣΣ), and affected processors were marked "16 BIT S/W ONLY". These latter processors were sold as good parts, since at the time 32-bit capability was not relevant for most users.
The i387 math coprocessor was not ready in time for the introduction of the 80386, and so many of the early 80386 motherboards instead provided a socket and hardware logic to make use of an 80287. In this configuration the FPU operated asynchronously to the CPU, usually with a clock rate of 10 MHz. The original Compaq Deskpro 386 is an example of such design. However, this was an annoyance to those who depended on floating-point performance, as the performance advantages of the 80387 over the 80287 were significant.
* A very early 80386 at 12 MHz (A80386-12), before the 32-bit multiply bug was found
* An A80386-16 marked "16 BIT S/W ONLY" with the multiply bug
* A bug-free A80386-16 marked "ΣΣ"

## Pin-compatible upgrades

Intel later offered a modified version of its 486DX in i386 packaging, branded as the Intel RapidCAD. This provided an upgrade path for users with i386-compatible hardware. The upgrade was a pair of chips that replaced both the i386 and i387. Since the 486DX design contained an FPU, the chip that replaced the i386 contained the floating-point functionality, and the chip that replaced the i387 served very little purpose. However, the latter chip was necessary in order to provide the FERR signal to the mainboard and appear to function as a normal floating-point unit.
Third parties offered a wide range of upgrades, for both SX and DX systems. The most popular ones were based on the Cyrix 486DLC/SLC core, which typically offered a substantial speed improvement due to its more efficient instruction pipeline and internal L1 SRAM cache. The cache was usually 1 KB, or sometimes 8 KB in the TI variant. Some of these upgrade chips (such as the 486DRx2/SRx2) were marketed by Cyrix themselves, but they were more commonly found in kits offered by upgrade specialists such as Kingston, Evergreen Technologies and Improve-It Technologies. Some of the fastest CPU upgrade modules featured the IBM SLC/DLC family (notable for its 16 KB L1 cache), or even the Intel 486 itself. Many 386 upgrade kits were advertised as being simple drop-in replacements, but often required complicated software to control the cache or clock doubling. Part of the problem was that on most 386 motherboards, the A20 line was controlled entirely by the motherboard with the CPU being unaware, which caused problems on CPUs with internal caches.
Overall, it was very difficult to configure upgrades to produce the results advertised on the packaging, and upgrades were often not very stable or not fully compatible.

## Models and variants
### Early 5 V models
#### i386DX

Original version, released in October 1985. The 16 MHz version was available for 299 USD in quantities of 100. The 20 MHz version was available for US$599 in quantities of 100. The 33 MHz version was available on April 10, 1989.
* Capable of working with 16- or 32-bit external busses
* Package: PGA-132 which was available in sampling for fourth quarter of 1985 or PQFP-132
* Process: First types CHMOS III, 1.5 μm, later CHMOS IV, 1 μm
* Die size: 104 mm² (ca. 10 mm × 10 mm) in CHMOS III and 39 mm² (6 mm × 6.5 mm) in CHMOS IV.
* Transistor count: 275,000
* Specified max clock: 12 MHz (early models), later 16, 20, 25 and 33 MHz

#### M80386

The military version was made using the CHMOS III process technology. It was made to withstand 105 Rads (Si) or greater. It was available for US$945 each in quantities of 100.

#### 80386SX

In 1988, Intel introduced the 80386SX, most often referred to as the 386SX, a cut-down version of the 80386 with a 16-bit data bus, mainly intended for lower-cost PCs aimed at the home, educational, and small-business markets, while the 386DX remained the high-end variant used in workstations, servers, and other demanding tasks. The CPU remained fully 32-bit internally, but the 16-bit bus was intended to simplify circuit-board layout and reduce total cost. The 16-bit bus simplified designs but hampered performance. Only 24 pins were connected to the address bus, therefore limiting addressing to 16 MB, but this was not a critical constraint at the time. Performance differences were due not only to differing data-bus widths, but also due to performance-enhancing cache memories often employed on boards using the original chip. This version can run 32-bit application software at 70 to 90 percent compared to the regular Intel386 DX CPU.
The original 80386 was subsequently renamed i386DX to avoid confusion. However, Intel subsequently used the "DX" suffix to refer to the floating-point capability of the i486DX. The 387SX was an 80387 part that was compatible with the 386SX (i.e. with a 16-bit databus). The 386SX was packaged in a surface-mount QFP and sometimes offered in a socket to allow for an upgrade.
The 16 MHz 386SX contains the 100-lead BQFP. It was available for USD $165 in quantities of 1000. It has the performance of 2.5 to 3 MIPS as well. The low-power version was available on April 10, 1989. This version that uses 20 to 30 percent less power and has higher operating temperature up to 100 °C than the regular version.
* 80386SX 16 MHz
* A surface-mount version of Intel 80386SX processor in a Compaq Deskpro computer. It is non-upgradable unless hot-air circuit-board rework is performed
* Die of Intel 80386SX

#### 80386SL

The 80386SL was introduced as a power-efficient version for laptop computers. The processor offered several power-management options (e.g. SMM), as well as different "sleep" modes to conserve battery power. It also contained support for an external cache of 16 to 64 KB. The extra functions and circuit implementation techniques caused this variant to have over 3 times as many transistors as the i386DX. The i386SL was first available at 20 MHz clock speed, with the 25 MHz model later added. With this system, it reduced up to 40% foot space than the Intel386 SX system. That translate to lighter and more portable cost-effective system.
Dave Vannier, the chief architect designed this microprocessor. It took them two years to complete this design since it uses the existing 386 architecture to implement. That assist with advanced computer-aided design tools which includes a complete simulation of system board. This die contains the 386 CPU core, AT Bus Controller, Memory Controller, Internal Bus Controller, Cache Control Logic along with Cache Tag SRAM and Clock. This CPU contains 855,000 transistors using one-micron CHMOS IV technology. It was available for USD $176 in 1,000 unit in quantities. The 25-MHz version was available in samples for USD $189 in 1,000-piece quantities, that version was finally made available in production by the end of 1991. It supports up to 32 Megabytes of physical address space. There was a 20-MHz cacheless version of Intel386 SL microprocessor, at the press time samples of this version were available for USD $101 in 1,000-piece quantities. There were low-voltage 20-Mhz version and cacheless 16- and 20-Mhz version microprocessors. These low voltage uses 3.3 Volts to supplied them and they do support full static mode as well. They were available for USD $94, $48 and $78 respectively in 1,000 pieces quantities.
* i386SL from 1990

#### SnapIn 386

In May 1991, Intel introduced an upgrade for IBM PS/2 Model 50 and 60 systems which contain 80286 microprocessors, converting them to full blown 32-bit systems. The SnapIn 386 module is a daughtercard with 20-MHz 386SX and 16-Kbyte direct-mapped cache SRAM memory. It directly plugs into the existing 286 socket with no cables, jumpers or switches. In the winter of 1992, an additional to this module now supported to IBM PS/2 Model 50 Z, 30 286 and 25 286 systems. Both modules were available for USD $495.

#### RapidCAD

A specially packaged Intel 486DX and a dummy floating-point unit (FPU) designed as pin-compatible replacements for an i386 processor and i387 FPU.

### Versions for embedded systems
#### 80376

This was an embedded version of the 80386SX which did not support real mode and paging in the MMU.

#### i386EX, i386EXTB and i386EXTC

System and power management and built in peripheral and support functions: Two 82C59A interrupt controllers; Timer, Counter (3 channels); Asynchronous SIO (2 channels); Synchronous SIO (1 channel); Watchdog timer (Hardware/Software); PIO. Usable with 80387SX or i387SL FPUs.
* Data/address bus: 16 / 26 bits
* Package: PQFP-132, SQFP-144 and PGA-168
* Process: CHMOS V, 0.8 μm
* Specified max clock:
** i386EX: 16 MHz @2.7–3.3 volts or 20 MHz @3.0–3.6 volts or 25 MHz @4.5–5.5 volts
** i386EXTB: 20 MHz @2.7–3.6 volts or 25 MHz @3.0–3.6 volts
** i386EXTC: 25 MHz @4.5–5.5 volts or 33 MHz @4.5–5.5 volts

#### i386CXSA and i386SXSA (or i386SXTA)

Transparent power management mode, integrated MMU and TTL compatible inputs (only 386SXSA). Usable with i387SX or i387SL FPUs.
* Data/address bus: 16 / 26 bits (24 bits for i386SXSA)
* Package: BQFP-100
* Voltage: 4.5–5.5 volts (25 and 33 MHz); 4.75–5.25 volts (40 MHz)
* Process: CHMOS V, 0.8 μm
* Specified max clock: 25, 33, 40 MHz

#### i386CXSB

Transparent power management mode and integrated MMU. Usable with i387SX or i387SL FPUs.
* Data/address bus: 16 / 26 bits
* Package: BQFP-100
* Voltage: 3.0 volts (16 MHz) or 3.3 volts (25 MHz)
* Process: CHMOS V, 0.8 μm
* Specified max clock: 16, 25 MHz

## Obsolescence

Windows 95 was the only entry in the Windows 9x series to officially support the 386, requiring at least a 386DX, though a 486 or better was recommended; Windows 98 requires a 486DX or higher. In the Windows NT family, Windows NT 3.51 was the last version with 386 support.
Debian GNU/Linux dropped 386 support with the release of 3.1 (Sarge) in 2005 and completely removed support in 2007 with 4.0 (Etch). Citing the maintenance burden around SMP primitives, the Linux kernel developers cut support from the development codebase in December 2012, later released as kernel version 3.8.
Among the BSDs, FreeBSD's 5.x releases were the last to support the 386; support for the 386SX was cut with release 5.2, while the remaining 386 support was removed with the 6.0 release in 2005. OpenBSD removed 386 support with version 4.2 (2007), DragonFly BSD with release 1.12 (2008), and NetBSD with the 5.0 release (2009).